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[mirror_ubuntu-jammy-kernel.git] / drivers / net / ethernet / stmicro / stmmac / stmmac_ethtool.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*******************************************************************************
3 STMMAC Ethtool support
4
5 Copyright (C) 2007-2009 STMicroelectronics Ltd
6
7
8 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
9 *******************************************************************************/
10
11 #include <linux/etherdevice.h>
12 #include <linux/ethtool.h>
13 #include <linux/interrupt.h>
14 #include <linux/mii.h>
15 #include <linux/phylink.h>
16 #include <linux/net_tstamp.h>
17 #include <asm/io.h>
18
19 #include "stmmac.h"
20 #include "dwmac_dma.h"
21 #include "dwxgmac2.h"
22
23 #define REG_SPACE_SIZE 0x1060
24 #define GMAC4_REG_SPACE_SIZE 0x116C
25 #define MAC100_ETHTOOL_NAME "st_mac100"
26 #define GMAC_ETHTOOL_NAME "st_gmac"
27 #define XGMAC_ETHTOOL_NAME "st_xgmac"
28
29 /* Same as DMA_CHAN_BASE_ADDR defined in dwmac4_dma.h
30 *
31 * It is here because dwmac_dma.h and dwmac4_dam.h can not be included at the
32 * same time due to the conflicting macro names.
33 */
34 #define GMAC4_DMA_CHAN_BASE_ADDR 0x00001100
35
36 #define ETHTOOL_DMA_OFFSET 55
37
38 struct stmmac_stats {
39 char stat_string[ETH_GSTRING_LEN];
40 int sizeof_stat;
41 int stat_offset;
42 };
43
44 #define STMMAC_STAT(m) \
45 { #m, sizeof_field(struct stmmac_extra_stats, m), \
46 offsetof(struct stmmac_priv, xstats.m)}
47
48 static const struct stmmac_stats stmmac_gstrings_stats[] = {
49 /* Transmit errors */
50 STMMAC_STAT(tx_underflow),
51 STMMAC_STAT(tx_carrier),
52 STMMAC_STAT(tx_losscarrier),
53 STMMAC_STAT(vlan_tag),
54 STMMAC_STAT(tx_deferred),
55 STMMAC_STAT(tx_vlan),
56 STMMAC_STAT(tx_jabber),
57 STMMAC_STAT(tx_frame_flushed),
58 STMMAC_STAT(tx_payload_error),
59 STMMAC_STAT(tx_ip_header_error),
60 /* Receive errors */
61 STMMAC_STAT(rx_desc),
62 STMMAC_STAT(sa_filter_fail),
63 STMMAC_STAT(overflow_error),
64 STMMAC_STAT(ipc_csum_error),
65 STMMAC_STAT(rx_collision),
66 STMMAC_STAT(rx_crc_errors),
67 STMMAC_STAT(dribbling_bit),
68 STMMAC_STAT(rx_length),
69 STMMAC_STAT(rx_mii),
70 STMMAC_STAT(rx_multicast),
71 STMMAC_STAT(rx_gmac_overflow),
72 STMMAC_STAT(rx_watchdog),
73 STMMAC_STAT(da_rx_filter_fail),
74 STMMAC_STAT(sa_rx_filter_fail),
75 STMMAC_STAT(rx_missed_cntr),
76 STMMAC_STAT(rx_overflow_cntr),
77 STMMAC_STAT(rx_vlan),
78 STMMAC_STAT(rx_split_hdr_pkt_n),
79 /* Tx/Rx IRQ error info */
80 STMMAC_STAT(tx_undeflow_irq),
81 STMMAC_STAT(tx_process_stopped_irq),
82 STMMAC_STAT(tx_jabber_irq),
83 STMMAC_STAT(rx_overflow_irq),
84 STMMAC_STAT(rx_buf_unav_irq),
85 STMMAC_STAT(rx_process_stopped_irq),
86 STMMAC_STAT(rx_watchdog_irq),
87 STMMAC_STAT(tx_early_irq),
88 STMMAC_STAT(fatal_bus_error_irq),
89 /* Tx/Rx IRQ Events */
90 STMMAC_STAT(rx_early_irq),
91 STMMAC_STAT(threshold),
92 STMMAC_STAT(tx_pkt_n),
93 STMMAC_STAT(rx_pkt_n),
94 STMMAC_STAT(normal_irq_n),
95 STMMAC_STAT(rx_normal_irq_n),
96 STMMAC_STAT(napi_poll),
97 STMMAC_STAT(tx_normal_irq_n),
98 STMMAC_STAT(tx_clean),
99 STMMAC_STAT(tx_set_ic_bit),
100 STMMAC_STAT(irq_receive_pmt_irq_n),
101 /* MMC info */
102 STMMAC_STAT(mmc_tx_irq_n),
103 STMMAC_STAT(mmc_rx_irq_n),
104 STMMAC_STAT(mmc_rx_csum_offload_irq_n),
105 /* EEE */
106 STMMAC_STAT(irq_tx_path_in_lpi_mode_n),
107 STMMAC_STAT(irq_tx_path_exit_lpi_mode_n),
108 STMMAC_STAT(irq_rx_path_in_lpi_mode_n),
109 STMMAC_STAT(irq_rx_path_exit_lpi_mode_n),
110 STMMAC_STAT(phy_eee_wakeup_error_n),
111 /* Extended RDES status */
112 STMMAC_STAT(ip_hdr_err),
113 STMMAC_STAT(ip_payload_err),
114 STMMAC_STAT(ip_csum_bypassed),
115 STMMAC_STAT(ipv4_pkt_rcvd),
116 STMMAC_STAT(ipv6_pkt_rcvd),
117 STMMAC_STAT(no_ptp_rx_msg_type_ext),
118 STMMAC_STAT(ptp_rx_msg_type_sync),
119 STMMAC_STAT(ptp_rx_msg_type_follow_up),
120 STMMAC_STAT(ptp_rx_msg_type_delay_req),
121 STMMAC_STAT(ptp_rx_msg_type_delay_resp),
122 STMMAC_STAT(ptp_rx_msg_type_pdelay_req),
123 STMMAC_STAT(ptp_rx_msg_type_pdelay_resp),
124 STMMAC_STAT(ptp_rx_msg_type_pdelay_follow_up),
125 STMMAC_STAT(ptp_rx_msg_type_announce),
126 STMMAC_STAT(ptp_rx_msg_type_management),
127 STMMAC_STAT(ptp_rx_msg_pkt_reserved_type),
128 STMMAC_STAT(ptp_frame_type),
129 STMMAC_STAT(ptp_ver),
130 STMMAC_STAT(timestamp_dropped),
131 STMMAC_STAT(av_pkt_rcvd),
132 STMMAC_STAT(av_tagged_pkt_rcvd),
133 STMMAC_STAT(vlan_tag_priority_val),
134 STMMAC_STAT(l3_filter_match),
135 STMMAC_STAT(l4_filter_match),
136 STMMAC_STAT(l3_l4_filter_no_match),
137 /* PCS */
138 STMMAC_STAT(irq_pcs_ane_n),
139 STMMAC_STAT(irq_pcs_link_n),
140 STMMAC_STAT(irq_rgmii_n),
141 /* DEBUG */
142 STMMAC_STAT(mtl_tx_status_fifo_full),
143 STMMAC_STAT(mtl_tx_fifo_not_empty),
144 STMMAC_STAT(mmtl_fifo_ctrl),
145 STMMAC_STAT(mtl_tx_fifo_read_ctrl_write),
146 STMMAC_STAT(mtl_tx_fifo_read_ctrl_wait),
147 STMMAC_STAT(mtl_tx_fifo_read_ctrl_read),
148 STMMAC_STAT(mtl_tx_fifo_read_ctrl_idle),
149 STMMAC_STAT(mac_tx_in_pause),
150 STMMAC_STAT(mac_tx_frame_ctrl_xfer),
151 STMMAC_STAT(mac_tx_frame_ctrl_idle),
152 STMMAC_STAT(mac_tx_frame_ctrl_wait),
153 STMMAC_STAT(mac_tx_frame_ctrl_pause),
154 STMMAC_STAT(mac_gmii_tx_proto_engine),
155 STMMAC_STAT(mtl_rx_fifo_fill_level_full),
156 STMMAC_STAT(mtl_rx_fifo_fill_above_thresh),
157 STMMAC_STAT(mtl_rx_fifo_fill_below_thresh),
158 STMMAC_STAT(mtl_rx_fifo_fill_level_empty),
159 STMMAC_STAT(mtl_rx_fifo_read_ctrl_flush),
160 STMMAC_STAT(mtl_rx_fifo_read_ctrl_read_data),
161 STMMAC_STAT(mtl_rx_fifo_read_ctrl_status),
162 STMMAC_STAT(mtl_rx_fifo_read_ctrl_idle),
163 STMMAC_STAT(mtl_rx_fifo_ctrl_active),
164 STMMAC_STAT(mac_rx_frame_ctrl_fifo),
165 STMMAC_STAT(mac_gmii_rx_proto_engine),
166 /* TSO */
167 STMMAC_STAT(tx_tso_frames),
168 STMMAC_STAT(tx_tso_nfrags),
169 /* EST */
170 STMMAC_STAT(mtl_est_cgce),
171 STMMAC_STAT(mtl_est_hlbs),
172 STMMAC_STAT(mtl_est_hlbf),
173 STMMAC_STAT(mtl_est_btre),
174 STMMAC_STAT(mtl_est_btrlm),
175 };
176 #define STMMAC_STATS_LEN ARRAY_SIZE(stmmac_gstrings_stats)
177
178 /* HW MAC Management counters (if supported) */
179 #define STMMAC_MMC_STAT(m) \
180 { #m, sizeof_field(struct stmmac_counters, m), \
181 offsetof(struct stmmac_priv, mmc.m)}
182
183 static const struct stmmac_stats stmmac_mmc[] = {
184 STMMAC_MMC_STAT(mmc_tx_octetcount_gb),
185 STMMAC_MMC_STAT(mmc_tx_framecount_gb),
186 STMMAC_MMC_STAT(mmc_tx_broadcastframe_g),
187 STMMAC_MMC_STAT(mmc_tx_multicastframe_g),
188 STMMAC_MMC_STAT(mmc_tx_64_octets_gb),
189 STMMAC_MMC_STAT(mmc_tx_65_to_127_octets_gb),
190 STMMAC_MMC_STAT(mmc_tx_128_to_255_octets_gb),
191 STMMAC_MMC_STAT(mmc_tx_256_to_511_octets_gb),
192 STMMAC_MMC_STAT(mmc_tx_512_to_1023_octets_gb),
193 STMMAC_MMC_STAT(mmc_tx_1024_to_max_octets_gb),
194 STMMAC_MMC_STAT(mmc_tx_unicast_gb),
195 STMMAC_MMC_STAT(mmc_tx_multicast_gb),
196 STMMAC_MMC_STAT(mmc_tx_broadcast_gb),
197 STMMAC_MMC_STAT(mmc_tx_underflow_error),
198 STMMAC_MMC_STAT(mmc_tx_singlecol_g),
199 STMMAC_MMC_STAT(mmc_tx_multicol_g),
200 STMMAC_MMC_STAT(mmc_tx_deferred),
201 STMMAC_MMC_STAT(mmc_tx_latecol),
202 STMMAC_MMC_STAT(mmc_tx_exesscol),
203 STMMAC_MMC_STAT(mmc_tx_carrier_error),
204 STMMAC_MMC_STAT(mmc_tx_octetcount_g),
205 STMMAC_MMC_STAT(mmc_tx_framecount_g),
206 STMMAC_MMC_STAT(mmc_tx_excessdef),
207 STMMAC_MMC_STAT(mmc_tx_pause_frame),
208 STMMAC_MMC_STAT(mmc_tx_vlan_frame_g),
209 STMMAC_MMC_STAT(mmc_rx_framecount_gb),
210 STMMAC_MMC_STAT(mmc_rx_octetcount_gb),
211 STMMAC_MMC_STAT(mmc_rx_octetcount_g),
212 STMMAC_MMC_STAT(mmc_rx_broadcastframe_g),
213 STMMAC_MMC_STAT(mmc_rx_multicastframe_g),
214 STMMAC_MMC_STAT(mmc_rx_crc_error),
215 STMMAC_MMC_STAT(mmc_rx_align_error),
216 STMMAC_MMC_STAT(mmc_rx_run_error),
217 STMMAC_MMC_STAT(mmc_rx_jabber_error),
218 STMMAC_MMC_STAT(mmc_rx_undersize_g),
219 STMMAC_MMC_STAT(mmc_rx_oversize_g),
220 STMMAC_MMC_STAT(mmc_rx_64_octets_gb),
221 STMMAC_MMC_STAT(mmc_rx_65_to_127_octets_gb),
222 STMMAC_MMC_STAT(mmc_rx_128_to_255_octets_gb),
223 STMMAC_MMC_STAT(mmc_rx_256_to_511_octets_gb),
224 STMMAC_MMC_STAT(mmc_rx_512_to_1023_octets_gb),
225 STMMAC_MMC_STAT(mmc_rx_1024_to_max_octets_gb),
226 STMMAC_MMC_STAT(mmc_rx_unicast_g),
227 STMMAC_MMC_STAT(mmc_rx_length_error),
228 STMMAC_MMC_STAT(mmc_rx_autofrangetype),
229 STMMAC_MMC_STAT(mmc_rx_pause_frames),
230 STMMAC_MMC_STAT(mmc_rx_fifo_overflow),
231 STMMAC_MMC_STAT(mmc_rx_vlan_frames_gb),
232 STMMAC_MMC_STAT(mmc_rx_watchdog_error),
233 STMMAC_MMC_STAT(mmc_rx_ipc_intr_mask),
234 STMMAC_MMC_STAT(mmc_rx_ipc_intr),
235 STMMAC_MMC_STAT(mmc_rx_ipv4_gd),
236 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr),
237 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay),
238 STMMAC_MMC_STAT(mmc_rx_ipv4_frag),
239 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl),
240 STMMAC_MMC_STAT(mmc_rx_ipv4_gd_octets),
241 STMMAC_MMC_STAT(mmc_rx_ipv4_hderr_octets),
242 STMMAC_MMC_STAT(mmc_rx_ipv4_nopay_octets),
243 STMMAC_MMC_STAT(mmc_rx_ipv4_frag_octets),
244 STMMAC_MMC_STAT(mmc_rx_ipv4_udsbl_octets),
245 STMMAC_MMC_STAT(mmc_rx_ipv6_gd_octets),
246 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr_octets),
247 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay_octets),
248 STMMAC_MMC_STAT(mmc_rx_ipv6_gd),
249 STMMAC_MMC_STAT(mmc_rx_ipv6_hderr),
250 STMMAC_MMC_STAT(mmc_rx_ipv6_nopay),
251 STMMAC_MMC_STAT(mmc_rx_udp_gd),
252 STMMAC_MMC_STAT(mmc_rx_udp_err),
253 STMMAC_MMC_STAT(mmc_rx_tcp_gd),
254 STMMAC_MMC_STAT(mmc_rx_tcp_err),
255 STMMAC_MMC_STAT(mmc_rx_icmp_gd),
256 STMMAC_MMC_STAT(mmc_rx_icmp_err),
257 STMMAC_MMC_STAT(mmc_rx_udp_gd_octets),
258 STMMAC_MMC_STAT(mmc_rx_udp_err_octets),
259 STMMAC_MMC_STAT(mmc_rx_tcp_gd_octets),
260 STMMAC_MMC_STAT(mmc_rx_tcp_err_octets),
261 STMMAC_MMC_STAT(mmc_rx_icmp_gd_octets),
262 STMMAC_MMC_STAT(mmc_rx_icmp_err_octets),
263 STMMAC_MMC_STAT(mmc_tx_fpe_fragment_cntr),
264 STMMAC_MMC_STAT(mmc_tx_hold_req_cntr),
265 STMMAC_MMC_STAT(mmc_rx_packet_assembly_err_cntr),
266 STMMAC_MMC_STAT(mmc_rx_packet_smd_err_cntr),
267 STMMAC_MMC_STAT(mmc_rx_packet_assembly_ok_cntr),
268 STMMAC_MMC_STAT(mmc_rx_fpe_fragment_cntr),
269 };
270 #define STMMAC_MMC_STATS_LEN ARRAY_SIZE(stmmac_mmc)
271
272 static const char stmmac_qstats_tx_string[][ETH_GSTRING_LEN] = {
273 "tx_pkt_n",
274 "tx_irq_n",
275 #define STMMAC_TXQ_STATS ARRAY_SIZE(stmmac_qstats_tx_string)
276 };
277
278 static const char stmmac_qstats_rx_string[][ETH_GSTRING_LEN] = {
279 "rx_pkt_n",
280 "rx_irq_n",
281 #define STMMAC_RXQ_STATS ARRAY_SIZE(stmmac_qstats_rx_string)
282 };
283
284 static void stmmac_ethtool_getdrvinfo(struct net_device *dev,
285 struct ethtool_drvinfo *info)
286 {
287 struct stmmac_priv *priv = netdev_priv(dev);
288
289 if (priv->plat->has_gmac || priv->plat->has_gmac4)
290 strlcpy(info->driver, GMAC_ETHTOOL_NAME, sizeof(info->driver));
291 else if (priv->plat->has_xgmac)
292 strlcpy(info->driver, XGMAC_ETHTOOL_NAME, sizeof(info->driver));
293 else
294 strlcpy(info->driver, MAC100_ETHTOOL_NAME,
295 sizeof(info->driver));
296
297 if (priv->plat->pdev) {
298 strlcpy(info->bus_info, pci_name(priv->plat->pdev),
299 sizeof(info->bus_info));
300 }
301 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
302 }
303
304 static int stmmac_ethtool_get_link_ksettings(struct net_device *dev,
305 struct ethtool_link_ksettings *cmd)
306 {
307 struct stmmac_priv *priv = netdev_priv(dev);
308
309 if (priv->hw->pcs & STMMAC_PCS_RGMII ||
310 priv->hw->pcs & STMMAC_PCS_SGMII) {
311 struct rgmii_adv adv;
312 u32 supported, advertising, lp_advertising;
313
314 if (!priv->xstats.pcs_link) {
315 cmd->base.speed = SPEED_UNKNOWN;
316 cmd->base.duplex = DUPLEX_UNKNOWN;
317 return 0;
318 }
319 cmd->base.duplex = priv->xstats.pcs_duplex;
320
321 cmd->base.speed = priv->xstats.pcs_speed;
322
323 /* Get and convert ADV/LP_ADV from the HW AN registers */
324 if (stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv))
325 return -EOPNOTSUPP; /* should never happen indeed */
326
327 /* Encoding of PSE bits is defined in 802.3z, 37.2.1.4 */
328
329 ethtool_convert_link_mode_to_legacy_u32(
330 &supported, cmd->link_modes.supported);
331 ethtool_convert_link_mode_to_legacy_u32(
332 &advertising, cmd->link_modes.advertising);
333 ethtool_convert_link_mode_to_legacy_u32(
334 &lp_advertising, cmd->link_modes.lp_advertising);
335
336 if (adv.pause & STMMAC_PCS_PAUSE)
337 advertising |= ADVERTISED_Pause;
338 if (adv.pause & STMMAC_PCS_ASYM_PAUSE)
339 advertising |= ADVERTISED_Asym_Pause;
340 if (adv.lp_pause & STMMAC_PCS_PAUSE)
341 lp_advertising |= ADVERTISED_Pause;
342 if (adv.lp_pause & STMMAC_PCS_ASYM_PAUSE)
343 lp_advertising |= ADVERTISED_Asym_Pause;
344
345 /* Reg49[3] always set because ANE is always supported */
346 cmd->base.autoneg = ADVERTISED_Autoneg;
347 supported |= SUPPORTED_Autoneg;
348 advertising |= ADVERTISED_Autoneg;
349 lp_advertising |= ADVERTISED_Autoneg;
350
351 if (adv.duplex) {
352 supported |= (SUPPORTED_1000baseT_Full |
353 SUPPORTED_100baseT_Full |
354 SUPPORTED_10baseT_Full);
355 advertising |= (ADVERTISED_1000baseT_Full |
356 ADVERTISED_100baseT_Full |
357 ADVERTISED_10baseT_Full);
358 } else {
359 supported |= (SUPPORTED_1000baseT_Half |
360 SUPPORTED_100baseT_Half |
361 SUPPORTED_10baseT_Half);
362 advertising |= (ADVERTISED_1000baseT_Half |
363 ADVERTISED_100baseT_Half |
364 ADVERTISED_10baseT_Half);
365 }
366 if (adv.lp_duplex)
367 lp_advertising |= (ADVERTISED_1000baseT_Full |
368 ADVERTISED_100baseT_Full |
369 ADVERTISED_10baseT_Full);
370 else
371 lp_advertising |= (ADVERTISED_1000baseT_Half |
372 ADVERTISED_100baseT_Half |
373 ADVERTISED_10baseT_Half);
374 cmd->base.port = PORT_OTHER;
375
376 ethtool_convert_legacy_u32_to_link_mode(
377 cmd->link_modes.supported, supported);
378 ethtool_convert_legacy_u32_to_link_mode(
379 cmd->link_modes.advertising, advertising);
380 ethtool_convert_legacy_u32_to_link_mode(
381 cmd->link_modes.lp_advertising, lp_advertising);
382
383 return 0;
384 }
385
386 return phylink_ethtool_ksettings_get(priv->phylink, cmd);
387 }
388
389 static int
390 stmmac_ethtool_set_link_ksettings(struct net_device *dev,
391 const struct ethtool_link_ksettings *cmd)
392 {
393 struct stmmac_priv *priv = netdev_priv(dev);
394
395 if (priv->hw->pcs & STMMAC_PCS_RGMII ||
396 priv->hw->pcs & STMMAC_PCS_SGMII) {
397 u32 mask = ADVERTISED_Autoneg | ADVERTISED_Pause;
398
399 /* Only support ANE */
400 if (cmd->base.autoneg != AUTONEG_ENABLE)
401 return -EINVAL;
402
403 mask &= (ADVERTISED_1000baseT_Half |
404 ADVERTISED_1000baseT_Full |
405 ADVERTISED_100baseT_Half |
406 ADVERTISED_100baseT_Full |
407 ADVERTISED_10baseT_Half |
408 ADVERTISED_10baseT_Full);
409
410 mutex_lock(&priv->lock);
411 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0);
412 mutex_unlock(&priv->lock);
413
414 return 0;
415 }
416
417 return phylink_ethtool_ksettings_set(priv->phylink, cmd);
418 }
419
420 static u32 stmmac_ethtool_getmsglevel(struct net_device *dev)
421 {
422 struct stmmac_priv *priv = netdev_priv(dev);
423 return priv->msg_enable;
424 }
425
426 static void stmmac_ethtool_setmsglevel(struct net_device *dev, u32 level)
427 {
428 struct stmmac_priv *priv = netdev_priv(dev);
429 priv->msg_enable = level;
430
431 }
432
433 static int stmmac_check_if_running(struct net_device *dev)
434 {
435 if (!netif_running(dev))
436 return -EBUSY;
437 return 0;
438 }
439
440 static int stmmac_ethtool_get_regs_len(struct net_device *dev)
441 {
442 struct stmmac_priv *priv = netdev_priv(dev);
443
444 if (priv->plat->has_xgmac)
445 return XGMAC_REGSIZE * 4;
446 else if (priv->plat->has_gmac4)
447 return GMAC4_REG_SPACE_SIZE;
448 return REG_SPACE_SIZE;
449 }
450
451 static void stmmac_ethtool_gregs(struct net_device *dev,
452 struct ethtool_regs *regs, void *space)
453 {
454 struct stmmac_priv *priv = netdev_priv(dev);
455 u32 *reg_space = (u32 *) space;
456
457 stmmac_dump_mac_regs(priv, priv->hw, reg_space);
458 stmmac_dump_dma_regs(priv, priv->ioaddr, reg_space);
459
460 /* Copy DMA registers to where ethtool expects them */
461 if (priv->plat->has_gmac4) {
462 /* GMAC4 dumps its DMA registers at its DMA_CHAN_BASE_ADDR */
463 memcpy(&reg_space[ETHTOOL_DMA_OFFSET],
464 &reg_space[GMAC4_DMA_CHAN_BASE_ADDR / 4],
465 NUM_DWMAC4_DMA_REGS * 4);
466 } else if (!priv->plat->has_xgmac) {
467 memcpy(&reg_space[ETHTOOL_DMA_OFFSET],
468 &reg_space[DMA_BUS_MODE / 4],
469 NUM_DWMAC1000_DMA_REGS * 4);
470 }
471 }
472
473 static int stmmac_nway_reset(struct net_device *dev)
474 {
475 struct stmmac_priv *priv = netdev_priv(dev);
476
477 return phylink_ethtool_nway_reset(priv->phylink);
478 }
479
480 static void stmmac_get_ringparam(struct net_device *netdev,
481 struct ethtool_ringparam *ring)
482 {
483 struct stmmac_priv *priv = netdev_priv(netdev);
484
485 ring->rx_max_pending = DMA_MAX_RX_SIZE;
486 ring->tx_max_pending = DMA_MAX_TX_SIZE;
487 ring->rx_pending = priv->dma_rx_size;
488 ring->tx_pending = priv->dma_tx_size;
489 }
490
491 static int stmmac_set_ringparam(struct net_device *netdev,
492 struct ethtool_ringparam *ring)
493 {
494 if (ring->rx_mini_pending || ring->rx_jumbo_pending ||
495 ring->rx_pending < DMA_MIN_RX_SIZE ||
496 ring->rx_pending > DMA_MAX_RX_SIZE ||
497 !is_power_of_2(ring->rx_pending) ||
498 ring->tx_pending < DMA_MIN_TX_SIZE ||
499 ring->tx_pending > DMA_MAX_TX_SIZE ||
500 !is_power_of_2(ring->tx_pending))
501 return -EINVAL;
502
503 return stmmac_reinit_ringparam(netdev, ring->rx_pending,
504 ring->tx_pending);
505 }
506
507 static void
508 stmmac_get_pauseparam(struct net_device *netdev,
509 struct ethtool_pauseparam *pause)
510 {
511 struct stmmac_priv *priv = netdev_priv(netdev);
512 struct rgmii_adv adv_lp;
513
514 if (priv->hw->pcs && !stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv_lp)) {
515 pause->autoneg = 1;
516 if (!adv_lp.pause)
517 return;
518 } else {
519 phylink_ethtool_get_pauseparam(priv->phylink, pause);
520 }
521 }
522
523 static int
524 stmmac_set_pauseparam(struct net_device *netdev,
525 struct ethtool_pauseparam *pause)
526 {
527 struct stmmac_priv *priv = netdev_priv(netdev);
528 struct rgmii_adv adv_lp;
529
530 if (priv->hw->pcs && !stmmac_pcs_get_adv_lp(priv, priv->ioaddr, &adv_lp)) {
531 pause->autoneg = 1;
532 if (!adv_lp.pause)
533 return -EOPNOTSUPP;
534 return 0;
535 } else {
536 return phylink_ethtool_set_pauseparam(priv->phylink, pause);
537 }
538 }
539
540 static void stmmac_get_per_qstats(struct stmmac_priv *priv, u64 *data)
541 {
542 u32 tx_cnt = priv->plat->tx_queues_to_use;
543 u32 rx_cnt = priv->plat->rx_queues_to_use;
544 int q, stat;
545 char *p;
546
547 for (q = 0; q < tx_cnt; q++) {
548 p = (char *)priv + offsetof(struct stmmac_priv,
549 xstats.txq_stats[q].tx_pkt_n);
550 for (stat = 0; stat < STMMAC_TXQ_STATS; stat++) {
551 *data++ = (*(u64 *)p);
552 p += sizeof(u64 *);
553 }
554 }
555 for (q = 0; q < rx_cnt; q++) {
556 p = (char *)priv + offsetof(struct stmmac_priv,
557 xstats.rxq_stats[q].rx_pkt_n);
558 for (stat = 0; stat < STMMAC_RXQ_STATS; stat++) {
559 *data++ = (*(u64 *)p);
560 p += sizeof(u64 *);
561 }
562 }
563 }
564
565 static void stmmac_get_ethtool_stats(struct net_device *dev,
566 struct ethtool_stats *dummy, u64 *data)
567 {
568 struct stmmac_priv *priv = netdev_priv(dev);
569 u32 rx_queues_count = priv->plat->rx_queues_to_use;
570 u32 tx_queues_count = priv->plat->tx_queues_to_use;
571 unsigned long count;
572 int i, j = 0, ret;
573
574 if (priv->dma_cap.asp) {
575 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) {
576 if (!stmmac_safety_feat_dump(priv, &priv->sstats, i,
577 &count, NULL))
578 data[j++] = count;
579 }
580 }
581
582 /* Update the DMA HW counters for dwmac10/100 */
583 ret = stmmac_dma_diagnostic_fr(priv, &dev->stats, (void *) &priv->xstats,
584 priv->ioaddr);
585 if (ret) {
586 /* If supported, for new GMAC chips expose the MMC counters */
587 if (priv->dma_cap.rmon) {
588 stmmac_mmc_read(priv, priv->mmcaddr, &priv->mmc);
589
590 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) {
591 char *p;
592 p = (char *)priv + stmmac_mmc[i].stat_offset;
593
594 data[j++] = (stmmac_mmc[i].sizeof_stat ==
595 sizeof(u64)) ? (*(u64 *)p) :
596 (*(u32 *)p);
597 }
598 }
599 if (priv->eee_enabled) {
600 int val = phylink_get_eee_err(priv->phylink);
601 if (val)
602 priv->xstats.phy_eee_wakeup_error_n = val;
603 }
604
605 if (priv->synopsys_id >= DWMAC_CORE_3_50)
606 stmmac_mac_debug(priv, priv->ioaddr,
607 (void *)&priv->xstats,
608 rx_queues_count, tx_queues_count);
609 }
610 for (i = 0; i < STMMAC_STATS_LEN; i++) {
611 char *p = (char *)priv + stmmac_gstrings_stats[i].stat_offset;
612 data[j++] = (stmmac_gstrings_stats[i].sizeof_stat ==
613 sizeof(u64)) ? (*(u64 *)p) : (*(u32 *)p);
614 }
615 stmmac_get_per_qstats(priv, &data[j]);
616 }
617
618 static int stmmac_get_sset_count(struct net_device *netdev, int sset)
619 {
620 struct stmmac_priv *priv = netdev_priv(netdev);
621 u32 tx_cnt = priv->plat->tx_queues_to_use;
622 u32 rx_cnt = priv->plat->rx_queues_to_use;
623 int i, len, safety_len = 0;
624
625 switch (sset) {
626 case ETH_SS_STATS:
627 len = STMMAC_STATS_LEN +
628 STMMAC_TXQ_STATS * tx_cnt +
629 STMMAC_RXQ_STATS * rx_cnt;
630
631 if (priv->dma_cap.rmon)
632 len += STMMAC_MMC_STATS_LEN;
633 if (priv->dma_cap.asp) {
634 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) {
635 if (!stmmac_safety_feat_dump(priv,
636 &priv->sstats, i,
637 NULL, NULL))
638 safety_len++;
639 }
640
641 len += safety_len;
642 }
643
644 return len;
645 case ETH_SS_TEST:
646 return stmmac_selftest_get_count(priv);
647 default:
648 return -EOPNOTSUPP;
649 }
650 }
651
652 static void stmmac_get_qstats_string(struct stmmac_priv *priv, u8 *data)
653 {
654 u32 tx_cnt = priv->plat->tx_queues_to_use;
655 u32 rx_cnt = priv->plat->rx_queues_to_use;
656 int q, stat;
657
658 for (q = 0; q < tx_cnt; q++) {
659 for (stat = 0; stat < STMMAC_TXQ_STATS; stat++) {
660 snprintf(data, ETH_GSTRING_LEN, "q%d_%s", q,
661 stmmac_qstats_tx_string[stat]);
662 data += ETH_GSTRING_LEN;
663 }
664 }
665 for (q = 0; q < rx_cnt; q++) {
666 for (stat = 0; stat < STMMAC_RXQ_STATS; stat++) {
667 snprintf(data, ETH_GSTRING_LEN, "q%d_%s", q,
668 stmmac_qstats_rx_string[stat]);
669 data += ETH_GSTRING_LEN;
670 }
671 }
672 }
673
674 static void stmmac_get_strings(struct net_device *dev, u32 stringset, u8 *data)
675 {
676 int i;
677 u8 *p = data;
678 struct stmmac_priv *priv = netdev_priv(dev);
679
680 switch (stringset) {
681 case ETH_SS_STATS:
682 if (priv->dma_cap.asp) {
683 for (i = 0; i < STMMAC_SAFETY_FEAT_SIZE; i++) {
684 const char *desc;
685 if (!stmmac_safety_feat_dump(priv,
686 &priv->sstats, i,
687 NULL, &desc)) {
688 memcpy(p, desc, ETH_GSTRING_LEN);
689 p += ETH_GSTRING_LEN;
690 }
691 }
692 }
693 if (priv->dma_cap.rmon)
694 for (i = 0; i < STMMAC_MMC_STATS_LEN; i++) {
695 memcpy(p, stmmac_mmc[i].stat_string,
696 ETH_GSTRING_LEN);
697 p += ETH_GSTRING_LEN;
698 }
699 for (i = 0; i < STMMAC_STATS_LEN; i++) {
700 memcpy(p, stmmac_gstrings_stats[i].stat_string,
701 ETH_GSTRING_LEN);
702 p += ETH_GSTRING_LEN;
703 }
704 stmmac_get_qstats_string(priv, p);
705 break;
706 case ETH_SS_TEST:
707 stmmac_selftest_get_strings(priv, p);
708 break;
709 default:
710 WARN_ON(1);
711 break;
712 }
713 }
714
715 /* Currently only support WOL through Magic packet. */
716 static void stmmac_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
717 {
718 struct stmmac_priv *priv = netdev_priv(dev);
719
720 if (!priv->plat->pmt)
721 return phylink_ethtool_get_wol(priv->phylink, wol);
722
723 mutex_lock(&priv->lock);
724 if (device_can_wakeup(priv->device)) {
725 wol->supported = WAKE_MAGIC | WAKE_UCAST;
726 if (priv->hw_cap_support && !priv->dma_cap.pmt_magic_frame)
727 wol->supported &= ~WAKE_MAGIC;
728 wol->wolopts = priv->wolopts;
729 }
730 mutex_unlock(&priv->lock);
731 }
732
733 static int stmmac_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
734 {
735 struct stmmac_priv *priv = netdev_priv(dev);
736 u32 support = WAKE_MAGIC | WAKE_UCAST;
737
738 if (!device_can_wakeup(priv->device))
739 return -EOPNOTSUPP;
740
741 if (!priv->plat->pmt) {
742 int ret = phylink_ethtool_set_wol(priv->phylink, wol);
743
744 if (!ret)
745 device_set_wakeup_enable(priv->device, !!wol->wolopts);
746 return ret;
747 }
748
749 /* By default almost all GMAC devices support the WoL via
750 * magic frame but we can disable it if the HW capability
751 * register shows no support for pmt_magic_frame. */
752 if ((priv->hw_cap_support) && (!priv->dma_cap.pmt_magic_frame))
753 wol->wolopts &= ~WAKE_MAGIC;
754
755 if (wol->wolopts & ~support)
756 return -EINVAL;
757
758 if (wol->wolopts) {
759 pr_info("stmmac: wakeup enable\n");
760 device_set_wakeup_enable(priv->device, 1);
761 enable_irq_wake(priv->wol_irq);
762 } else {
763 device_set_wakeup_enable(priv->device, 0);
764 disable_irq_wake(priv->wol_irq);
765 }
766
767 mutex_lock(&priv->lock);
768 priv->wolopts = wol->wolopts;
769 mutex_unlock(&priv->lock);
770
771 return 0;
772 }
773
774 static int stmmac_ethtool_op_get_eee(struct net_device *dev,
775 struct ethtool_eee *edata)
776 {
777 struct stmmac_priv *priv = netdev_priv(dev);
778
779 if (!priv->dma_cap.eee)
780 return -EOPNOTSUPP;
781
782 edata->eee_enabled = priv->eee_enabled;
783 edata->eee_active = priv->eee_active;
784 edata->tx_lpi_timer = priv->tx_lpi_timer;
785 edata->tx_lpi_enabled = priv->tx_lpi_enabled;
786
787 return phylink_ethtool_get_eee(priv->phylink, edata);
788 }
789
790 static int stmmac_ethtool_op_set_eee(struct net_device *dev,
791 struct ethtool_eee *edata)
792 {
793 struct stmmac_priv *priv = netdev_priv(dev);
794 int ret;
795
796 if (!priv->dma_cap.eee)
797 return -EOPNOTSUPP;
798
799 if (priv->tx_lpi_enabled != edata->tx_lpi_enabled)
800 netdev_warn(priv->dev,
801 "Setting EEE tx-lpi is not supported\n");
802
803 if (priv->hw->xpcs) {
804 ret = xpcs_config_eee(priv->hw->xpcs,
805 priv->plat->mult_fact_100ns,
806 edata->eee_enabled);
807 if (ret)
808 return ret;
809 }
810
811 if (!edata->eee_enabled)
812 stmmac_disable_eee_mode(priv);
813
814 ret = phylink_ethtool_set_eee(priv->phylink, edata);
815 if (ret)
816 return ret;
817
818 if (edata->eee_enabled &&
819 priv->tx_lpi_timer != edata->tx_lpi_timer) {
820 priv->tx_lpi_timer = edata->tx_lpi_timer;
821 stmmac_eee_init(priv);
822 }
823
824 return 0;
825 }
826
827 static u32 stmmac_usec2riwt(u32 usec, struct stmmac_priv *priv)
828 {
829 unsigned long clk = clk_get_rate(priv->plat->stmmac_clk);
830
831 if (!clk) {
832 clk = priv->plat->clk_ref_rate;
833 if (!clk)
834 return 0;
835 }
836
837 return (usec * (clk / 1000000)) / 256;
838 }
839
840 static u32 stmmac_riwt2usec(u32 riwt, struct stmmac_priv *priv)
841 {
842 unsigned long clk = clk_get_rate(priv->plat->stmmac_clk);
843
844 if (!clk) {
845 clk = priv->plat->clk_ref_rate;
846 if (!clk)
847 return 0;
848 }
849
850 return (riwt * 256) / (clk / 1000000);
851 }
852
853 static int __stmmac_get_coalesce(struct net_device *dev,
854 struct ethtool_coalesce *ec,
855 int queue)
856 {
857 struct stmmac_priv *priv = netdev_priv(dev);
858 u32 max_cnt;
859 u32 rx_cnt;
860 u32 tx_cnt;
861
862 rx_cnt = priv->plat->rx_queues_to_use;
863 tx_cnt = priv->plat->tx_queues_to_use;
864 max_cnt = max(rx_cnt, tx_cnt);
865
866 if (queue < 0)
867 queue = 0;
868 else if (queue >= max_cnt)
869 return -EINVAL;
870
871 if (queue < tx_cnt) {
872 ec->tx_coalesce_usecs = priv->tx_coal_timer[queue];
873 ec->tx_max_coalesced_frames = priv->tx_coal_frames[queue];
874 } else {
875 ec->tx_coalesce_usecs = 0;
876 ec->tx_max_coalesced_frames = 0;
877 }
878
879 if (priv->use_riwt && queue < rx_cnt) {
880 ec->rx_max_coalesced_frames = priv->rx_coal_frames[queue];
881 ec->rx_coalesce_usecs = stmmac_riwt2usec(priv->rx_riwt[queue],
882 priv);
883 } else {
884 ec->rx_max_coalesced_frames = 0;
885 ec->rx_coalesce_usecs = 0;
886 }
887
888 return 0;
889 }
890
891 static int stmmac_get_coalesce(struct net_device *dev,
892 struct ethtool_coalesce *ec,
893 struct kernel_ethtool_coalesce *kernel_coal,
894 struct netlink_ext_ack *extack)
895 {
896 return __stmmac_get_coalesce(dev, ec, -1);
897 }
898
899 static int stmmac_get_per_queue_coalesce(struct net_device *dev, u32 queue,
900 struct ethtool_coalesce *ec)
901 {
902 return __stmmac_get_coalesce(dev, ec, queue);
903 }
904
905 static int __stmmac_set_coalesce(struct net_device *dev,
906 struct ethtool_coalesce *ec,
907 int queue)
908 {
909 struct stmmac_priv *priv = netdev_priv(dev);
910 bool all_queues = false;
911 unsigned int rx_riwt;
912 u32 max_cnt;
913 u32 rx_cnt;
914 u32 tx_cnt;
915
916 rx_cnt = priv->plat->rx_queues_to_use;
917 tx_cnt = priv->plat->tx_queues_to_use;
918 max_cnt = max(rx_cnt, tx_cnt);
919
920 if (queue < 0)
921 all_queues = true;
922 else if (queue >= max_cnt)
923 return -EINVAL;
924
925 if (priv->use_riwt && (ec->rx_coalesce_usecs > 0)) {
926 rx_riwt = stmmac_usec2riwt(ec->rx_coalesce_usecs, priv);
927
928 if ((rx_riwt > MAX_DMA_RIWT) || (rx_riwt < MIN_DMA_RIWT))
929 return -EINVAL;
930
931 if (all_queues) {
932 int i;
933
934 for (i = 0; i < rx_cnt; i++) {
935 priv->rx_riwt[i] = rx_riwt;
936 stmmac_rx_watchdog(priv, priv->ioaddr,
937 rx_riwt, i);
938 priv->rx_coal_frames[i] =
939 ec->rx_max_coalesced_frames;
940 }
941 } else if (queue < rx_cnt) {
942 priv->rx_riwt[queue] = rx_riwt;
943 stmmac_rx_watchdog(priv, priv->ioaddr,
944 rx_riwt, queue);
945 priv->rx_coal_frames[queue] =
946 ec->rx_max_coalesced_frames;
947 }
948 }
949
950 if ((ec->tx_coalesce_usecs == 0) &&
951 (ec->tx_max_coalesced_frames == 0))
952 return -EINVAL;
953
954 if ((ec->tx_coalesce_usecs > STMMAC_MAX_COAL_TX_TICK) ||
955 (ec->tx_max_coalesced_frames > STMMAC_TX_MAX_FRAMES))
956 return -EINVAL;
957
958 if (all_queues) {
959 int i;
960
961 for (i = 0; i < tx_cnt; i++) {
962 priv->tx_coal_frames[i] =
963 ec->tx_max_coalesced_frames;
964 priv->tx_coal_timer[i] =
965 ec->tx_coalesce_usecs;
966 }
967 } else if (queue < tx_cnt) {
968 priv->tx_coal_frames[queue] =
969 ec->tx_max_coalesced_frames;
970 priv->tx_coal_timer[queue] =
971 ec->tx_coalesce_usecs;
972 }
973
974 return 0;
975 }
976
977 static int stmmac_set_coalesce(struct net_device *dev,
978 struct ethtool_coalesce *ec,
979 struct kernel_ethtool_coalesce *kernel_coal,
980 struct netlink_ext_ack *extack)
981 {
982 return __stmmac_set_coalesce(dev, ec, -1);
983 }
984
985 static int stmmac_set_per_queue_coalesce(struct net_device *dev, u32 queue,
986 struct ethtool_coalesce *ec)
987 {
988 return __stmmac_set_coalesce(dev, ec, queue);
989 }
990
991 static int stmmac_get_rxnfc(struct net_device *dev,
992 struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
993 {
994 struct stmmac_priv *priv = netdev_priv(dev);
995
996 switch (rxnfc->cmd) {
997 case ETHTOOL_GRXRINGS:
998 rxnfc->data = priv->plat->rx_queues_to_use;
999 break;
1000 default:
1001 return -EOPNOTSUPP;
1002 }
1003
1004 return 0;
1005 }
1006
1007 static u32 stmmac_get_rxfh_key_size(struct net_device *dev)
1008 {
1009 struct stmmac_priv *priv = netdev_priv(dev);
1010
1011 return sizeof(priv->rss.key);
1012 }
1013
1014 static u32 stmmac_get_rxfh_indir_size(struct net_device *dev)
1015 {
1016 struct stmmac_priv *priv = netdev_priv(dev);
1017
1018 return ARRAY_SIZE(priv->rss.table);
1019 }
1020
1021 static int stmmac_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
1022 u8 *hfunc)
1023 {
1024 struct stmmac_priv *priv = netdev_priv(dev);
1025 int i;
1026
1027 if (indir) {
1028 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++)
1029 indir[i] = priv->rss.table[i];
1030 }
1031
1032 if (key)
1033 memcpy(key, priv->rss.key, sizeof(priv->rss.key));
1034 if (hfunc)
1035 *hfunc = ETH_RSS_HASH_TOP;
1036
1037 return 0;
1038 }
1039
1040 static int stmmac_set_rxfh(struct net_device *dev, const u32 *indir,
1041 const u8 *key, const u8 hfunc)
1042 {
1043 struct stmmac_priv *priv = netdev_priv(dev);
1044 int i;
1045
1046 if ((hfunc != ETH_RSS_HASH_NO_CHANGE) && (hfunc != ETH_RSS_HASH_TOP))
1047 return -EOPNOTSUPP;
1048
1049 if (indir) {
1050 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++)
1051 priv->rss.table[i] = indir[i];
1052 }
1053
1054 if (key)
1055 memcpy(priv->rss.key, key, sizeof(priv->rss.key));
1056
1057 return stmmac_rss_configure(priv, priv->hw, &priv->rss,
1058 priv->plat->rx_queues_to_use);
1059 }
1060
1061 static void stmmac_get_channels(struct net_device *dev,
1062 struct ethtool_channels *chan)
1063 {
1064 struct stmmac_priv *priv = netdev_priv(dev);
1065
1066 chan->rx_count = priv->plat->rx_queues_to_use;
1067 chan->tx_count = priv->plat->tx_queues_to_use;
1068 chan->max_rx = priv->dma_cap.number_rx_queues;
1069 chan->max_tx = priv->dma_cap.number_tx_queues;
1070 }
1071
1072 static int stmmac_set_channels(struct net_device *dev,
1073 struct ethtool_channels *chan)
1074 {
1075 struct stmmac_priv *priv = netdev_priv(dev);
1076
1077 if (chan->rx_count > priv->dma_cap.number_rx_queues ||
1078 chan->tx_count > priv->dma_cap.number_tx_queues ||
1079 !chan->rx_count || !chan->tx_count)
1080 return -EINVAL;
1081
1082 return stmmac_reinit_queues(dev, chan->rx_count, chan->tx_count);
1083 }
1084
1085 static int stmmac_get_ts_info(struct net_device *dev,
1086 struct ethtool_ts_info *info)
1087 {
1088 struct stmmac_priv *priv = netdev_priv(dev);
1089
1090 if ((priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) {
1091
1092 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
1093 SOF_TIMESTAMPING_TX_HARDWARE |
1094 SOF_TIMESTAMPING_RX_SOFTWARE |
1095 SOF_TIMESTAMPING_RX_HARDWARE |
1096 SOF_TIMESTAMPING_SOFTWARE |
1097 SOF_TIMESTAMPING_RAW_HARDWARE;
1098
1099 if (priv->ptp_clock)
1100 info->phc_index = ptp_clock_index(priv->ptp_clock);
1101
1102 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
1103
1104 info->rx_filters = ((1 << HWTSTAMP_FILTER_NONE) |
1105 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
1106 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
1107 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
1108 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
1109 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
1110 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
1111 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) |
1112 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) |
1113 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) |
1114 (1 << HWTSTAMP_FILTER_ALL));
1115 return 0;
1116 } else
1117 return ethtool_op_get_ts_info(dev, info);
1118 }
1119
1120 static int stmmac_get_tunable(struct net_device *dev,
1121 const struct ethtool_tunable *tuna, void *data)
1122 {
1123 struct stmmac_priv *priv = netdev_priv(dev);
1124 int ret = 0;
1125
1126 switch (tuna->id) {
1127 case ETHTOOL_RX_COPYBREAK:
1128 *(u32 *)data = priv->rx_copybreak;
1129 break;
1130 default:
1131 ret = -EINVAL;
1132 break;
1133 }
1134
1135 return ret;
1136 }
1137
1138 static int stmmac_set_tunable(struct net_device *dev,
1139 const struct ethtool_tunable *tuna,
1140 const void *data)
1141 {
1142 struct stmmac_priv *priv = netdev_priv(dev);
1143 int ret = 0;
1144
1145 switch (tuna->id) {
1146 case ETHTOOL_RX_COPYBREAK:
1147 priv->rx_copybreak = *(u32 *)data;
1148 break;
1149 default:
1150 ret = -EINVAL;
1151 break;
1152 }
1153
1154 return ret;
1155 }
1156
1157 static const struct ethtool_ops stmmac_ethtool_ops = {
1158 .supported_coalesce_params = ETHTOOL_COALESCE_USECS |
1159 ETHTOOL_COALESCE_MAX_FRAMES,
1160 .begin = stmmac_check_if_running,
1161 .get_drvinfo = stmmac_ethtool_getdrvinfo,
1162 .get_msglevel = stmmac_ethtool_getmsglevel,
1163 .set_msglevel = stmmac_ethtool_setmsglevel,
1164 .get_regs = stmmac_ethtool_gregs,
1165 .get_regs_len = stmmac_ethtool_get_regs_len,
1166 .get_link = ethtool_op_get_link,
1167 .nway_reset = stmmac_nway_reset,
1168 .get_ringparam = stmmac_get_ringparam,
1169 .set_ringparam = stmmac_set_ringparam,
1170 .get_pauseparam = stmmac_get_pauseparam,
1171 .set_pauseparam = stmmac_set_pauseparam,
1172 .self_test = stmmac_selftest_run,
1173 .get_ethtool_stats = stmmac_get_ethtool_stats,
1174 .get_strings = stmmac_get_strings,
1175 .get_wol = stmmac_get_wol,
1176 .set_wol = stmmac_set_wol,
1177 .get_eee = stmmac_ethtool_op_get_eee,
1178 .set_eee = stmmac_ethtool_op_set_eee,
1179 .get_sset_count = stmmac_get_sset_count,
1180 .get_rxnfc = stmmac_get_rxnfc,
1181 .get_rxfh_key_size = stmmac_get_rxfh_key_size,
1182 .get_rxfh_indir_size = stmmac_get_rxfh_indir_size,
1183 .get_rxfh = stmmac_get_rxfh,
1184 .set_rxfh = stmmac_set_rxfh,
1185 .get_ts_info = stmmac_get_ts_info,
1186 .get_coalesce = stmmac_get_coalesce,
1187 .set_coalesce = stmmac_set_coalesce,
1188 .get_per_queue_coalesce = stmmac_get_per_queue_coalesce,
1189 .set_per_queue_coalesce = stmmac_set_per_queue_coalesce,
1190 .get_channels = stmmac_get_channels,
1191 .set_channels = stmmac_set_channels,
1192 .get_tunable = stmmac_get_tunable,
1193 .set_tunable = stmmac_set_tunable,
1194 .get_link_ksettings = stmmac_ethtool_get_link_ksettings,
1195 .set_link_ksettings = stmmac_ethtool_set_link_ksettings,
1196 };
1197
1198 void stmmac_set_ethtool_ops(struct net_device *netdev)
1199 {
1200 netdev->ethtool_ops = &stmmac_ethtool_ops;
1201 }
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