drivers/net/ieee802154/mrf24j40.c

   1 /*
   2  * Driver for Microchip MRF24J40 802.15.4 Wireless-PAN Networking controller
   3  *
   4  * Copyright (C) 2012 Alan Ott <alan@signal11.us>
   5  *                    Signal 11 Software
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/spi/spi.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/module.h>
  21 #include <linux/regmap.h>
  22 #include <linux/ieee802154.h>
  23 #include <net/cfg802154.h>
  24 #include <net/mac802154.h>
  25
  26 /* MRF24J40 Short Address Registers */
  27 #define REG_RXMCR       0x00  /* Receive MAC control */
  28 #define REG_PANIDL      0x01  /* PAN ID (low) */
  29 #define REG_PANIDH      0x02  /* PAN ID (high) */
  30 #define REG_SADRL       0x03  /* Short address (low) */
  31 #define REG_SADRH       0x04  /* Short address (high) */
  32 #define REG_EADR0       0x05  /* Long address (low) (high is EADR7) */
  33 #define REG_EADR1       0x06
  34 #define REG_EADR2       0x07
  35 #define REG_EADR3       0x08
  36 #define REG_EADR4       0x09
  37 #define REG_EADR5       0x0A
  38 #define REG_EADR6       0x0B
  39 #define REG_EADR7       0x0C
  40 #define REG_RXFLUSH     0x0D
  41 #define REG_ORDER       0x10
  42 #define REG_TXMCR       0x11  /* Transmit MAC control */
  43 #define REG_ACKTMOUT    0x12
  44 #define REG_ESLOTG1     0x13
  45 #define REG_SYMTICKL    0x14
  46 #define REG_SYMTICKH    0x15
  47 #define REG_PACON0      0x16  /* Power Amplifier Control */
  48 #define REG_PACON1      0x17  /* Power Amplifier Control */
  49 #define REG_PACON2      0x18  /* Power Amplifier Control */
  50 #define REG_TXBCON0     0x1A
  51 #define REG_TXNCON      0x1B  /* Transmit Normal FIFO Control */
  52 #define REG_TXG1CON     0x1C
  53 #define REG_TXG2CON     0x1D
  54 #define REG_ESLOTG23    0x1E
  55 #define REG_ESLOTG45    0x1F
  56 #define REG_ESLOTG67    0x20
  57 #define REG_TXPEND      0x21
  58 #define REG_WAKECON     0x22
  59 #define REG_FROMOFFSET  0x23
  60 #define REG_TXSTAT      0x24  /* TX MAC Status Register */
  61 #define REG_TXBCON1     0x25
  62 #define REG_GATECLK     0x26
  63 #define REG_TXTIME      0x27
  64 #define REG_HSYMTMRL    0x28
  65 #define REG_HSYMTMRH    0x29
  66 #define REG_SOFTRST     0x2A  /* Soft Reset */
  67 #define REG_SECCON0     0x2C
  68 #define REG_SECCON1     0x2D
  69 #define REG_TXSTBL      0x2E  /* TX Stabilization */
  70 #define REG_RXSR        0x30
  71 #define REG_INTSTAT     0x31  /* Interrupt Status */
  72 #define REG_INTCON      0x32  /* Interrupt Control */
  73 #define REG_GPIO        0x33  /* GPIO */
  74 #define REG_TRISGPIO    0x34  /* GPIO direction */
  75 #define REG_SLPACK      0x35
  76 #define REG_RFCTL       0x36  /* RF Control Mode Register */
  77 #define REG_SECCR2      0x37
  78 #define REG_BBREG0      0x38
  79 #define REG_BBREG1      0x39  /* Baseband Registers */
  80 #define REG_BBREG2      0x3A  /* */
  81 #define REG_BBREG3      0x3B
  82 #define REG_BBREG4      0x3C
  83 #define REG_BBREG6      0x3E  /* */
  84 #define REG_CCAEDTH     0x3F  /* Energy Detection Threshold */
  85
  86 /* MRF24J40 Long Address Registers */
  87 #define REG_RFCON0      0x200  /* RF Control Registers */
  88 #define REG_RFCON1      0x201
  89 #define REG_RFCON2      0x202
  90 #define REG_RFCON3      0x203
  91 #define REG_RFCON5      0x205
  92 #define REG_RFCON6      0x206
  93 #define REG_RFCON7      0x207
  94 #define REG_RFCON8      0x208
  95 #define REG_SLPCAL0     0x209
  96 #define REG_SLPCAL1     0x20A
  97 #define REG_SLPCAL2     0x20B
  98 #define REG_RFSTATE     0x20F
  99 #define REG_RSSI        0x210
 100 #define REG_SLPCON0     0x211  /* Sleep Clock Control Registers */
 101 #define REG_SLPCON1     0x220
 102 #define REG_WAKETIMEL   0x222  /* Wake-up Time Match Value Low */
 103 #define REG_WAKETIMEH   0x223  /* Wake-up Time Match Value High */
 104 #define REG_REMCNTL     0x224
 105 #define REG_REMCNTH     0x225
 106 #define REG_MAINCNT0    0x226
 107 #define REG_MAINCNT1    0x227
 108 #define REG_MAINCNT2    0x228
 109 #define REG_MAINCNT3    0x229
 110 #define REG_TESTMODE    0x22F  /* Test mode */
 111 #define REG_ASSOEAR0    0x230
 112 #define REG_ASSOEAR1    0x231
 113 #define REG_ASSOEAR2    0x232
 114 #define REG_ASSOEAR3    0x233
 115 #define REG_ASSOEAR4    0x234
 116 #define REG_ASSOEAR5    0x235
 117 #define REG_ASSOEAR6    0x236
 118 #define REG_ASSOEAR7    0x237
 119 #define REG_ASSOSAR0    0x238
 120 #define REG_ASSOSAR1    0x239
 121 #define REG_UNONCE0     0x240
 122 #define REG_UNONCE1     0x241
 123 #define REG_UNONCE2     0x242
 124 #define REG_UNONCE3     0x243
 125 #define REG_UNONCE4     0x244
 126 #define REG_UNONCE5     0x245
 127 #define REG_UNONCE6     0x246
 128 #define REG_UNONCE7     0x247
 129 #define REG_UNONCE8     0x248
 130 #define REG_UNONCE9     0x249
 131 #define REG_UNONCE10    0x24A
 132 #define REG_UNONCE11    0x24B
 133 #define REG_UNONCE12    0x24C
 134 #define REG_RX_FIFO     0x300  /* Receive FIFO */
 135
 136 /* Device configuration: Only channels 11-26 on page 0 are supported. */
 137 #define MRF24J40_CHAN_MIN 11
 138 #define MRF24J40_CHAN_MAX 26
 139 #define CHANNEL_MASK (((u32)1 << (MRF24J40_CHAN_MAX + 1)) \
 140                       - ((u32)1 << MRF24J40_CHAN_MIN))
 141
 142 #define TX_FIFO_SIZE 128 /* From datasheet */
 143 #define RX_FIFO_SIZE 144 /* From datasheet */
 144 #define SET_CHANNEL_DELAY_US 192 /* From datasheet */
 145
 146 enum mrf24j40_modules { MRF24J40, MRF24J40MA, MRF24J40MC };
 147
 148 /* Device Private Data */
 149 struct mrf24j40 {
 150         struct spi_device *spi;
 151         struct ieee802154_hw *hw;
 152
 153         struct regmap *regmap_short;
 154         struct regmap *regmap_long;
 155
 156         /* for writing txfifo */
 157         struct spi_message tx_msg;
 158         u8 tx_hdr_buf[2];
 159         struct spi_transfer tx_hdr_trx;
 160         u8 tx_len_buf[2];
 161         struct spi_transfer tx_len_trx;
 162         struct spi_transfer tx_buf_trx;
 163         struct sk_buff *tx_skb;
 164
 165         /* post transmit message to send frame out  */
 166         struct spi_message tx_post_msg;
 167         u8 tx_post_buf[2];
 168         struct spi_transfer tx_post_trx;
 169
 170         struct mutex buffer_mutex; /* only used to protect buf */
 171         u8 *buf; /* 3 bytes. Used for SPI single-register transfers. */
 172 };
 173
 174 /* regmap information for short address register access */
 175 #define MRF24J40_SHORT_WRITE    0x01
 176 #define MRF24J40_SHORT_READ     0x00
 177 #define MRF24J40_SHORT_NUMREGS  0x3F
 178
 179 /* regmap information for long address register access */
 180 #define MRF24J40_LONG_ACCESS    0x80
 181 #define MRF24J40_LONG_NUMREGS   0x38F
 182
 183 /* Read/Write SPI Commands for Short and Long Address registers. */
 184 #define MRF24J40_READSHORT(reg) ((reg) << 1)
 185 #define MRF24J40_WRITESHORT(reg) ((reg) << 1 | 1)
 186 #define MRF24J40_READLONG(reg) (1 << 15 | (reg) << 5)
 187 #define MRF24J40_WRITELONG(reg) (1 << 15 | (reg) << 5 | 1 << 4)
 188
 189 /* The datasheet indicates the theoretical maximum for SCK to be 10MHz */
 190 #define MAX_SPI_SPEED_HZ 10000000
 191
 192 #define printdev(X) (&X->spi->dev)
 193
 194 static bool
 195 mrf24j40_short_reg_writeable(struct device *dev, unsigned int reg)
 196 {
 197         switch (reg) {
 198         case REG_RXMCR:
 199         case REG_PANIDL:
 200         case REG_PANIDH:
 201         case REG_SADRL:
 202         case REG_SADRH:
 203         case REG_EADR0:
 204         case REG_EADR1:
 205         case REG_EADR2:
 206         case REG_EADR3:
 207         case REG_EADR4:
 208         case REG_EADR5:
 209         case REG_EADR6:
 210         case REG_EADR7:
 211         case REG_RXFLUSH:
 212         case REG_ORDER:
 213         case REG_TXMCR:
 214         case REG_ACKTMOUT:
 215         case REG_ESLOTG1:
 216         case REG_SYMTICKL:
 217         case REG_SYMTICKH:
 218         case REG_PACON0:
 219         case REG_PACON1:
 220         case REG_PACON2:
 221         case REG_TXBCON0:
 222         case REG_TXNCON:
 223         case REG_TXG1CON:
 224         case REG_TXG2CON:
 225         case REG_ESLOTG23:
 226         case REG_ESLOTG45:
 227         case REG_ESLOTG67:
 228         case REG_TXPEND:
 229         case REG_WAKECON:
 230         case REG_FROMOFFSET:
 231         case REG_TXBCON1:
 232         case REG_GATECLK:
 233         case REG_TXTIME:
 234         case REG_HSYMTMRL:
 235         case REG_HSYMTMRH:
 236         case REG_SOFTRST:
 237         case REG_SECCON0:
 238         case REG_SECCON1:
 239         case REG_TXSTBL:
 240         case REG_RXSR:
 241         case REG_INTCON:
 242         case REG_TRISGPIO:
 243         case REG_GPIO:
 244         case REG_RFCTL:
 245         case REG_SLPACK:
 246         case REG_BBREG0:
 247         case REG_BBREG1:
 248         case REG_BBREG2:
 249         case REG_BBREG3:
 250         case REG_BBREG4:
 251         case REG_BBREG6:
 252         case REG_CCAEDTH:
 253                 return true;
 254         default:
 255                 return false;
 256         }
 257 }
 258
 259 static bool
 260 mrf24j40_short_reg_readable(struct device *dev, unsigned int reg)
 261 {
 262         bool rc;
 263
 264         /* all writeable are also readable */
 265         rc = mrf24j40_short_reg_writeable(dev, reg);
 266         if (rc)
 267                 return rc;
 268
 269         /* readonly regs */
 270         switch (reg) {
 271         case REG_TXSTAT:
 272         case REG_INTSTAT:
 273                 return true;
 274         default:
 275                 return false;
 276         }
 277 }
 278
 279 static bool
 280 mrf24j40_short_reg_volatile(struct device *dev, unsigned int reg)
 281 {
 282         /* can be changed during runtime */
 283         switch (reg) {
 284         case REG_TXSTAT:
 285         case REG_INTSTAT:
 286         case REG_RXFLUSH:
 287         case REG_TXNCON:
 288         case REG_SOFTRST:
 289         case REG_RFCTL:
 290         case REG_TXBCON0:
 291         case REG_TXG1CON:
 292         case REG_TXG2CON:
 293         case REG_TXBCON1:
 294         case REG_SECCON0:
 295         case REG_RXSR:
 296         case REG_SLPACK:
 297         case REG_SECCR2:
 298         case REG_BBREG6:
 299         /* use them in spi_async and regmap so it's volatile */
 300         case REG_BBREG1:
 301                 return true;
 302         default:
 303                 return false;
 304         }
 305 }
 306
 307 static bool
 308 mrf24j40_short_reg_precious(struct device *dev, unsigned int reg)
 309 {
 310         /* don't clear irq line on read */
 311         switch (reg) {
 312         case REG_INTSTAT:
 313                 return true;
 314         default:
 315                 return false;
 316         }
 317 }
 318
 319 static const struct regmap_config mrf24j40_short_regmap = {
 320         .name = "mrf24j40_short",
 321         .reg_bits = 7,
 322         .val_bits = 8,
 323         .pad_bits = 1,
 324         .write_flag_mask = MRF24J40_SHORT_WRITE,
 325         .read_flag_mask = MRF24J40_SHORT_READ,
 326         .cache_type = REGCACHE_RBTREE,
 327         .max_register = MRF24J40_SHORT_NUMREGS,
 328         .writeable_reg = mrf24j40_short_reg_writeable,
 329         .readable_reg = mrf24j40_short_reg_readable,
 330         .volatile_reg = mrf24j40_short_reg_volatile,
 331         .precious_reg = mrf24j40_short_reg_precious,
 332 };
 333
 334 static bool
 335 mrf24j40_long_reg_writeable(struct device *dev, unsigned int reg)
 336 {
 337         switch (reg) {
 338         case REG_RFCON0:
 339         case REG_RFCON1:
 340         case REG_RFCON2:
 341         case REG_RFCON3:
 342         case REG_RFCON5:
 343         case REG_RFCON6:
 344         case REG_RFCON7:
 345         case REG_RFCON8:
 346         case REG_SLPCAL2:
 347         case REG_SLPCON0:
 348         case REG_SLPCON1:
 349         case REG_WAKETIMEL:
 350         case REG_WAKETIMEH:
 351         case REG_REMCNTL:
 352         case REG_REMCNTH:
 353         case REG_MAINCNT0:
 354         case REG_MAINCNT1:
 355         case REG_MAINCNT2:
 356         case REG_MAINCNT3:
 357         case REG_TESTMODE:
 358         case REG_ASSOEAR0:
 359         case REG_ASSOEAR1:
 360         case REG_ASSOEAR2:
 361         case REG_ASSOEAR3:
 362         case REG_ASSOEAR4:
 363         case REG_ASSOEAR5:
 364         case REG_ASSOEAR6:
 365         case REG_ASSOEAR7:
 366         case REG_ASSOSAR0:
 367         case REG_ASSOSAR1:
 368         case REG_UNONCE0:
 369         case REG_UNONCE1:
 370         case REG_UNONCE2:
 371         case REG_UNONCE3:
 372         case REG_UNONCE4:
 373         case REG_UNONCE5:
 374         case REG_UNONCE6:
 375         case REG_UNONCE7:
 376         case REG_UNONCE8:
 377         case REG_UNONCE9:
 378         case REG_UNONCE10:
 379         case REG_UNONCE11:
 380         case REG_UNONCE12:
 381                 return true;
 382         default:
 383                 return false;
 384         }
 385 }
 386
 387 static bool
 388 mrf24j40_long_reg_readable(struct device *dev, unsigned int reg)
 389 {
 390         bool rc;
 391
 392         /* all writeable are also readable */
 393         rc = mrf24j40_long_reg_writeable(dev, reg);
 394         if (rc)
 395                 return rc;
 396
 397         /* readonly regs */
 398         switch (reg) {
 399         case REG_SLPCAL0:
 400         case REG_SLPCAL1:
 401         case REG_RFSTATE:
 402         case REG_RSSI:
 403                 return true;
 404         default:
 405                 return false;
 406         }
 407 }
 408
 409 static bool
 410 mrf24j40_long_reg_volatile(struct device *dev, unsigned int reg)
 411 {
 412         /* can be changed during runtime */
 413         switch (reg) {
 414         case REG_SLPCAL0:
 415         case REG_SLPCAL1:
 416         case REG_SLPCAL2:
 417         case REG_RFSTATE:
 418         case REG_RSSI:
 419         case REG_MAINCNT3:
 420                 return true;
 421         default:
 422                 return false;
 423         }
 424 }
 425
 426 static const struct regmap_config mrf24j40_long_regmap = {
 427         .name = "mrf24j40_long",
 428         .reg_bits = 11,
 429         .val_bits = 8,
 430         .pad_bits = 5,
 431         .write_flag_mask = MRF24J40_LONG_ACCESS,
 432         .read_flag_mask = MRF24J40_LONG_ACCESS,
 433         .cache_type = REGCACHE_RBTREE,
 434         .max_register = MRF24J40_LONG_NUMREGS,
 435         .writeable_reg = mrf24j40_long_reg_writeable,
 436         .readable_reg = mrf24j40_long_reg_readable,
 437         .volatile_reg = mrf24j40_long_reg_volatile,
 438 };
 439
 440 static int mrf24j40_long_regmap_write(void *context, const void *data,
 441                                       size_t count)
 442 {
 443         struct spi_device *spi = context;
 444         u8 buf[3];
 445
 446         if (count > 3)
 447                 return -EINVAL;
 448
 449         /* regmap supports read/write mask only in frist byte
 450          * long write access need to set the 12th bit, so we
 451          * make special handling for write.
 452          */
 453         memcpy(buf, data, count);
 454         buf[1] |= (1 << 4);
 455
 456         return spi_write(spi, buf, count);
 457 }
 458
 459 static int
 460 mrf24j40_long_regmap_read(void *context, const void *reg, size_t reg_size,
 461                           void *val, size_t val_size)
 462 {
 463         struct spi_device *spi = context;
 464
 465         return spi_write_then_read(spi, reg, reg_size, val, val_size);
 466 }
 467
 468 static const struct regmap_bus mrf24j40_long_regmap_bus = {
 469         .write = mrf24j40_long_regmap_write,
 470         .read = mrf24j40_long_regmap_read,
 471         .reg_format_endian_default = REGMAP_ENDIAN_BIG,
 472         .val_format_endian_default = REGMAP_ENDIAN_BIG,
 473 };
 474
 475 static int write_short_reg(struct mrf24j40 *devrec, u8 reg, u8 value)
 476 {
 477         int ret;
 478         struct spi_message msg;
 479         struct spi_transfer xfer = {
 480                 .len = 2,
 481                 .tx_buf = devrec->buf,
 482                 .rx_buf = devrec->buf,
 483         };
 484
 485         spi_message_init(&msg);
 486         spi_message_add_tail(&xfer, &msg);
 487
 488         mutex_lock(&devrec->buffer_mutex);
 489         devrec->buf[0] = MRF24J40_WRITESHORT(reg);
 490         devrec->buf[1] = value;
 491
 492         ret = spi_sync(devrec->spi, &msg);
 493         if (ret)
 494                 dev_err(printdev(devrec),
 495                         "SPI write Failed for short register 0x%hhx\n", reg);
 496
 497         mutex_unlock(&devrec->buffer_mutex);
 498         return ret;
 499 }
 500
 501 static int read_short_reg(struct mrf24j40 *devrec, u8 reg, u8 *val)
 502 {
 503         int ret = -1;
 504         struct spi_message msg;
 505         struct spi_transfer xfer = {
 506                 .len = 2,
 507                 .tx_buf = devrec->buf,
 508                 .rx_buf = devrec->buf,
 509         };
 510
 511         spi_message_init(&msg);
 512         spi_message_add_tail(&xfer, &msg);
 513
 514         mutex_lock(&devrec->buffer_mutex);
 515         devrec->buf[0] = MRF24J40_READSHORT(reg);
 516         devrec->buf[1] = 0;
 517
 518         ret = spi_sync(devrec->spi, &msg);
 519         if (ret)
 520                 dev_err(printdev(devrec),
 521                         "SPI read Failed for short register 0x%hhx\n", reg);
 522         else
 523                 *val = devrec->buf[1];
 524
 525         mutex_unlock(&devrec->buffer_mutex);
 526         return ret;
 527 }
 528
 529 static int read_long_reg(struct mrf24j40 *devrec, u16 reg, u8 *value)
 530 {
 531         int ret;
 532         u16 cmd;
 533         struct spi_message msg;
 534         struct spi_transfer xfer = {
 535                 .len = 3,
 536                 .tx_buf = devrec->buf,
 537                 .rx_buf = devrec->buf,
 538         };
 539
 540         spi_message_init(&msg);
 541         spi_message_add_tail(&xfer, &msg);
 542
 543         cmd = MRF24J40_READLONG(reg);
 544         mutex_lock(&devrec->buffer_mutex);
 545         devrec->buf[0] = cmd >> 8 & 0xff;
 546         devrec->buf[1] = cmd & 0xff;
 547         devrec->buf[2] = 0;
 548
 549         ret = spi_sync(devrec->spi, &msg);
 550         if (ret)
 551                 dev_err(printdev(devrec),
 552                         "SPI read Failed for long register 0x%hx\n", reg);
 553         else
 554                 *value = devrec->buf[2];
 555
 556         mutex_unlock(&devrec->buffer_mutex);
 557         return ret;
 558 }
 559
 560 static void write_tx_buf_complete(void *context)
 561 {
 562         struct mrf24j40 *devrec = context;
 563         __le16 fc = ieee802154_get_fc_from_skb(devrec->tx_skb);
 564         u8 val = 0x01;
 565         int ret;
 566
 567         if (ieee802154_is_ackreq(fc))
 568                 val |= 0x04;
 569
 570         devrec->tx_post_msg.complete = NULL;
 571         devrec->tx_post_buf[0] = MRF24J40_WRITESHORT(REG_TXNCON);
 572         devrec->tx_post_buf[1] = val;
 573
 574         ret = spi_async(devrec->spi, &devrec->tx_post_msg);
 575         if (ret)
 576                 dev_err(printdev(devrec), "SPI write Failed for transmit buf\n");
 577 }
 578
 579 /* This function relies on an undocumented write method. Once a write command
 580    and address is set, as many bytes of data as desired can be clocked into
 581    the device. The datasheet only shows setting one byte at a time. */
 582 static int write_tx_buf(struct mrf24j40 *devrec, u16 reg,
 583                         const u8 *data, size_t length)
 584 {
 585         u16 cmd;
 586         int ret;
 587
 588         /* Range check the length. 2 bytes are used for the length fields.*/
 589         if (length > TX_FIFO_SIZE-2) {
 590                 dev_err(printdev(devrec), "write_tx_buf() was passed too large a buffer. Performing short write.\n");
 591                 length = TX_FIFO_SIZE-2;
 592         }
 593
 594         cmd = MRF24J40_WRITELONG(reg);
 595         devrec->tx_hdr_buf[0] = cmd >> 8 & 0xff;
 596         devrec->tx_hdr_buf[1] = cmd & 0xff;
 597         devrec->tx_len_buf[0] = 0x0; /* Header Length. Set to 0 for now. TODO */
 598         devrec->tx_len_buf[1] = length; /* Total length */
 599         devrec->tx_buf_trx.tx_buf = data;
 600         devrec->tx_buf_trx.len = length;
 601
 602         ret = spi_async(devrec->spi, &devrec->tx_msg);
 603         if (ret)
 604                 dev_err(printdev(devrec), "SPI write Failed for TX buf\n");
 605
 606         return ret;
 607 }
 608
 609 static int mrf24j40_tx(struct ieee802154_hw *hw, struct sk_buff *skb)
 610 {
 611         struct mrf24j40 *devrec = hw->priv;
 612
 613         dev_dbg(printdev(devrec), "tx packet of %d bytes\n", skb->len);
 614         devrec->tx_skb = skb;
 615
 616         return write_tx_buf(devrec, 0x000, skb->data, skb->len);
 617 }
 618
 619 static int mrf24j40_read_rx_buf(struct mrf24j40 *devrec,
 620                                 u8 *data, u8 *len, u8 *lqi)
 621 {
 622         u8 rx_len;
 623         u8 addr[2];
 624         u8 lqi_rssi[2];
 625         u16 cmd;
 626         int ret;
 627         struct spi_message msg;
 628         struct spi_transfer addr_xfer = {
 629                 .len = 2,
 630                 .tx_buf = &addr,
 631         };
 632         struct spi_transfer data_xfer = {
 633                 .len = 0x0, /* set below */
 634                 .rx_buf = data,
 635         };
 636         struct spi_transfer status_xfer = {
 637                 .len = 2,
 638                 .rx_buf = &lqi_rssi,
 639         };
 640
 641         /* Get the length of the data in the RX FIFO. The length in this
 642          * register exclues the 1-byte length field at the beginning. */
 643         ret = read_long_reg(devrec, REG_RX_FIFO, &rx_len);
 644         if (ret)
 645                 goto out;
 646
 647         /* Range check the RX FIFO length, accounting for the one-byte
 648          * length field at the beginning. */
 649         if (rx_len > RX_FIFO_SIZE-1) {
 650                 dev_err(printdev(devrec), "Invalid length read from device. Performing short read.\n");
 651                 rx_len = RX_FIFO_SIZE-1;
 652         }
 653
 654         if (rx_len > *len) {
 655                 /* Passed in buffer wasn't big enough. Should never happen. */
 656                 dev_err(printdev(devrec), "Buffer not big enough. Performing short read\n");
 657                 rx_len = *len;
 658         }
 659
 660         /* Set up the commands to read the data. */
 661         cmd = MRF24J40_READLONG(REG_RX_FIFO+1);
 662         addr[0] = cmd >> 8 & 0xff;
 663         addr[1] = cmd & 0xff;
 664         data_xfer.len = rx_len;
 665
 666         spi_message_init(&msg);
 667         spi_message_add_tail(&addr_xfer, &msg);
 668         spi_message_add_tail(&data_xfer, &msg);
 669         spi_message_add_tail(&status_xfer, &msg);
 670
 671         ret = spi_sync(devrec->spi, &msg);
 672         if (ret) {
 673                 dev_err(printdev(devrec), "SPI RX Buffer Read Failed.\n");
 674                 goto out;
 675         }
 676
 677         *lqi = lqi_rssi[0];
 678         *len = rx_len;
 679
 680 #ifdef DEBUG
 681         print_hex_dump(KERN_DEBUG, "mrf24j40 rx: ",
 682                        DUMP_PREFIX_OFFSET, 16, 1, data, *len, 0);
 683         pr_debug("mrf24j40 rx: lqi: %02hhx rssi: %02hhx\n",
 684                  lqi_rssi[0], lqi_rssi[1]);
 685 #endif
 686
 687 out:
 688         return ret;
 689 }
 690
 691 static int mrf24j40_ed(struct ieee802154_hw *hw, u8 *level)
 692 {
 693         /* TODO: */
 694         pr_warn("mrf24j40: ed not implemented\n");
 695         *level = 0;
 696         return 0;
 697 }
 698
 699 static int mrf24j40_start(struct ieee802154_hw *hw)
 700 {
 701         struct mrf24j40 *devrec = hw->priv;
 702
 703         dev_dbg(printdev(devrec), "start\n");
 704
 705         /* Clear TXNIE and RXIE. Enable interrupts */
 706         return regmap_update_bits(devrec->regmap_short, REG_INTCON,
 707                                   0x01 | 0x08, 0x00);
 708 }
 709
 710 static void mrf24j40_stop(struct ieee802154_hw *hw)
 711 {
 712         struct mrf24j40 *devrec = hw->priv;
 713
 714         dev_dbg(printdev(devrec), "stop\n");
 715
 716         /* Set TXNIE and RXIE. Disable Interrupts */
 717         regmap_update_bits(devrec->regmap_short, REG_INTCON, 0x01 | 0x08,
 718                            0x01 | 0x08);
 719 }
 720
 721 static int mrf24j40_set_channel(struct ieee802154_hw *hw, u8 page, u8 channel)
 722 {
 723         struct mrf24j40 *devrec = hw->priv;
 724         u8 val;
 725         int ret;
 726
 727         dev_dbg(printdev(devrec), "Set Channel %d\n", channel);
 728
 729         WARN_ON(page != 0);
 730         WARN_ON(channel < MRF24J40_CHAN_MIN);
 731         WARN_ON(channel > MRF24J40_CHAN_MAX);
 732
 733         /* Set Channel TODO */
 734         val = (channel-11) << 4 | 0x03;
 735         ret = regmap_update_bits(devrec->regmap_long, REG_RFCON0, 0xf0, val);
 736         if (ret)
 737                 return ret;
 738
 739         /* RF Reset */
 740         ret = regmap_update_bits(devrec->regmap_short, REG_RFCTL, 0x04, 0x04);
 741         if (ret)
 742                 return ret;
 743
 744         ret = regmap_update_bits(devrec->regmap_short, REG_RFCTL, 0x04, 0x00);
 745         if (!ret)
 746                 udelay(SET_CHANNEL_DELAY_US); /* per datasheet */
 747
 748         return ret;
 749 }
 750
 751 static int mrf24j40_filter(struct ieee802154_hw *hw,
 752                            struct ieee802154_hw_addr_filt *filt,
 753                            unsigned long changed)
 754 {
 755         struct mrf24j40 *devrec = hw->priv;
 756
 757         dev_dbg(printdev(devrec), "filter\n");
 758
 759         if (changed & IEEE802154_AFILT_SADDR_CHANGED) {
 760                 /* Short Addr */
 761                 u8 addrh, addrl;
 762
 763                 addrh = le16_to_cpu(filt->short_addr) >> 8 & 0xff;
 764                 addrl = le16_to_cpu(filt->short_addr) & 0xff;
 765
 766                 regmap_write(devrec->regmap_short, REG_SADRH, addrh);
 767                 regmap_write(devrec->regmap_short, REG_SADRL, addrl);
 768                 dev_dbg(printdev(devrec),
 769                         "Set short addr to %04hx\n", filt->short_addr);
 770         }
 771
 772         if (changed & IEEE802154_AFILT_IEEEADDR_CHANGED) {
 773                 /* Device Address */
 774                 u8 i, addr[8];
 775
 776                 memcpy(addr, &filt->ieee_addr, 8);
 777                 for (i = 0; i < 8; i++)
 778                         regmap_write(devrec->regmap_short, REG_EADR0 + i,
 779                                      addr[i]);
 780
 781 #ifdef DEBUG
 782                 pr_debug("Set long addr to: ");
 783                 for (i = 0; i < 8; i++)
 784                         pr_debug("%02hhx ", addr[7 - i]);
 785                 pr_debug("\n");
 786 #endif
 787         }
 788
 789         if (changed & IEEE802154_AFILT_PANID_CHANGED) {
 790                 /* PAN ID */
 791                 u8 panidl, panidh;
 792
 793                 panidh = le16_to_cpu(filt->pan_id) >> 8 & 0xff;
 794                 panidl = le16_to_cpu(filt->pan_id) & 0xff;
 795                 regmap_write(devrec->regmap_short, REG_PANIDH, panidh);
 796                 regmap_write(devrec->regmap_short, REG_PANIDL, panidl);
 797
 798                 dev_dbg(printdev(devrec), "Set PANID to %04hx\n", filt->pan_id);
 799         }
 800
 801         if (changed & IEEE802154_AFILT_PANC_CHANGED) {
 802                 /* Pan Coordinator */
 803                 u8 val;
 804                 int ret;
 805
 806                 if (filt->pan_coord)
 807                         val = 0x8;
 808                 else
 809                         val = 0x0;
 810                 ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR, 0x8,
 811                                          val);
 812                 if (ret)
 813                         return ret;
 814
 815                 /* REG_SLOTTED is maintained as default (unslotted/CSMA-CA).
 816                  * REG_ORDER is maintained as default (no beacon/superframe).
 817                  */
 818
 819                 dev_dbg(printdev(devrec), "Set Pan Coord to %s\n",
 820                         filt->pan_coord ? "on" : "off");
 821         }
 822
 823         return 0;
 824 }
 825
 826 static int mrf24j40_handle_rx(struct mrf24j40 *devrec)
 827 {
 828         u8 len = RX_FIFO_SIZE;
 829         u8 lqi = 0;
 830         u8 val;
 831         int ret = 0;
 832         int ret2;
 833         struct sk_buff *skb;
 834
 835         /* Turn off reception of packets off the air. This prevents the
 836          * device from overwriting the buffer while we're reading it. */
 837         ret = read_short_reg(devrec, REG_BBREG1, &val);
 838         if (ret)
 839                 goto out;
 840         val |= 4; /* SET RXDECINV */
 841         write_short_reg(devrec, REG_BBREG1, val);
 842
 843         skb = dev_alloc_skb(len);
 844         if (!skb) {
 845                 ret = -ENOMEM;
 846                 goto out;
 847         }
 848
 849         ret = mrf24j40_read_rx_buf(devrec, skb_put(skb, len), &len, &lqi);
 850         if (ret < 0) {
 851                 dev_err(printdev(devrec), "Failure reading RX FIFO\n");
 852                 kfree_skb(skb);
 853                 ret = -EINVAL;
 854                 goto out;
 855         }
 856
 857         /* TODO: Other drivers call ieee20154_rx_irqsafe() here (eg: cc2040,
 858          * also from a workqueue).  I think irqsafe is not necessary here.
 859          * Can someone confirm? */
 860         ieee802154_rx_irqsafe(devrec->hw, skb, lqi);
 861
 862         dev_dbg(printdev(devrec), "RX Handled\n");
 863
 864 out:
 865         /* Turn back on reception of packets off the air. */
 866         ret2 = read_short_reg(devrec, REG_BBREG1, &val);
 867         if (ret2)
 868                 return ret2;
 869         val &= ~0x4; /* Clear RXDECINV */
 870         write_short_reg(devrec, REG_BBREG1, val);
 871
 872         return ret;
 873 }
 874
 875 static const struct ieee802154_ops mrf24j40_ops = {
 876         .owner = THIS_MODULE,
 877         .xmit_async = mrf24j40_tx,
 878         .ed = mrf24j40_ed,
 879         .start = mrf24j40_start,
 880         .stop = mrf24j40_stop,
 881         .set_channel = mrf24j40_set_channel,
 882         .set_hw_addr_filt = mrf24j40_filter,
 883 };
 884
 885 static irqreturn_t mrf24j40_isr(int irq, void *data)
 886 {
 887         struct mrf24j40 *devrec = data;
 888         u8 intstat;
 889         int ret;
 890
 891         /* Read the interrupt status */
 892         ret = read_short_reg(devrec, REG_INTSTAT, &intstat);
 893         if (ret)
 894                 goto out;
 895
 896         /* Check for TX complete */
 897         if (intstat & 0x1)
 898                 ieee802154_xmit_complete(devrec->hw, devrec->tx_skb, false);
 899
 900         /* Check for Rx */
 901         if (intstat & 0x8)
 902                 mrf24j40_handle_rx(devrec);
 903
 904 out:
 905         return IRQ_HANDLED;
 906 }
 907
 908 static int mrf24j40_hw_init(struct mrf24j40 *devrec)
 909 {
 910         int ret;
 911
 912         /* Initialize the device.
 913                 From datasheet section 3.2: Initialization. */
 914         ret = regmap_write(devrec->regmap_short, REG_SOFTRST, 0x07);
 915         if (ret)
 916                 goto err_ret;
 917
 918         ret = regmap_write(devrec->regmap_short, REG_PACON2, 0x98);
 919         if (ret)
 920                 goto err_ret;
 921
 922         ret = regmap_write(devrec->regmap_short, REG_TXSTBL, 0x95);
 923         if (ret)
 924                 goto err_ret;
 925
 926         ret = regmap_write(devrec->regmap_long, REG_RFCON0, 0x03);
 927         if (ret)
 928                 goto err_ret;
 929
 930         ret = regmap_write(devrec->regmap_long, REG_RFCON1, 0x01);
 931         if (ret)
 932                 goto err_ret;
 933
 934         ret = regmap_write(devrec->regmap_long, REG_RFCON2, 0x80);
 935         if (ret)
 936                 goto err_ret;
 937
 938         ret = regmap_write(devrec->regmap_long, REG_RFCON6, 0x90);
 939         if (ret)
 940                 goto err_ret;
 941
 942         ret = regmap_write(devrec->regmap_long, REG_RFCON7, 0x80);
 943         if (ret)
 944                 goto err_ret;
 945
 946         ret = regmap_write(devrec->regmap_long, REG_RFCON8, 0x10);
 947         if (ret)
 948                 goto err_ret;
 949
 950         ret = regmap_write(devrec->regmap_long, REG_SLPCON1, 0x21);
 951         if (ret)
 952                 goto err_ret;
 953
 954         ret = regmap_write(devrec->regmap_short, REG_BBREG2, 0x80);
 955         if (ret)
 956                 goto err_ret;
 957
 958         ret = regmap_write(devrec->regmap_short, REG_CCAEDTH, 0x60);
 959         if (ret)
 960                 goto err_ret;
 961
 962         ret = regmap_write(devrec->regmap_short, REG_BBREG6, 0x40);
 963         if (ret)
 964                 goto err_ret;
 965
 966         ret = regmap_write(devrec->regmap_short, REG_RFCTL, 0x04);
 967         if (ret)
 968                 goto err_ret;
 969
 970         ret = regmap_write(devrec->regmap_short, REG_RFCTL, 0x0);
 971         if (ret)
 972                 goto err_ret;
 973
 974         udelay(192);
 975
 976         /* Set RX Mode. RXMCR<1:0>: 0x0 normal, 0x1 promisc, 0x2 error */
 977         ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR, 0x03, 0x00);
 978         if (ret)
 979                 goto err_ret;
 980
 981         if (spi_get_device_id(devrec->spi)->driver_data == MRF24J40MC) {
 982                 /* Enable external amplifier.
 983                  * From MRF24J40MC datasheet section 1.3: Operation.
 984                  */
 985                 regmap_update_bits(devrec->regmap_long, REG_TESTMODE, 0x07,
 986                                    0x07);
 987
 988                 /* Set GPIO3 as output. */
 989                 regmap_update_bits(devrec->regmap_short, REG_TRISGPIO, 0x08,
 990                                    0x08);
 991
 992                 /* Set GPIO3 HIGH to enable U5 voltage regulator */
 993                 regmap_update_bits(devrec->regmap_short, REG_GPIO, 0x08, 0x08);
 994
 995                 /* Reduce TX pwr to meet FCC requirements.
 996                  * From MRF24J40MC datasheet section 3.1.1
 997                  */
 998                 regmap_write(devrec->regmap_long, REG_RFCON3, 0x28);
 999         }
1000
1001         return 0;
1002
1003 err_ret:
1004         return ret;
1005 }
1006
1007 static void
1008 mrf24j40_setup_tx_spi_messages(struct mrf24j40 *devrec)
1009 {
1010         spi_message_init(&devrec->tx_msg);
1011         devrec->tx_msg.context = devrec;
1012         devrec->tx_msg.complete = write_tx_buf_complete;
1013         devrec->tx_hdr_trx.len = 2;
1014         devrec->tx_hdr_trx.tx_buf = devrec->tx_hdr_buf;
1015         spi_message_add_tail(&devrec->tx_hdr_trx, &devrec->tx_msg);
1016         devrec->tx_len_trx.len = 2;
1017         devrec->tx_len_trx.tx_buf = devrec->tx_len_buf;
1018         spi_message_add_tail(&devrec->tx_len_trx, &devrec->tx_msg);
1019         spi_message_add_tail(&devrec->tx_buf_trx, &devrec->tx_msg);
1020
1021         spi_message_init(&devrec->tx_post_msg);
1022         devrec->tx_post_msg.context = devrec;
1023         devrec->tx_post_trx.len = 2;
1024         devrec->tx_post_trx.tx_buf = devrec->tx_post_buf;
1025         spi_message_add_tail(&devrec->tx_post_trx, &devrec->tx_post_msg);
1026 }
1027
1028 static void  mrf24j40_phy_setup(struct mrf24j40 *devrec)
1029 {
1030         ieee802154_random_extended_addr(&devrec->hw->phy->perm_extended_addr);
1031         devrec->hw->phy->current_channel = 11;
1032 }
1033
1034 static int mrf24j40_probe(struct spi_device *spi)
1035 {
1036         int ret = -ENOMEM;
1037         struct ieee802154_hw *hw;
1038         struct mrf24j40 *devrec;
1039
1040         dev_info(&spi->dev, "probe(). IRQ: %d\n", spi->irq);
1041
1042         /* Register with the 802154 subsystem */
1043
1044         hw = ieee802154_alloc_hw(sizeof(*devrec), &mrf24j40_ops);
1045         if (!hw)
1046                 goto err_ret;
1047
1048         devrec = hw->priv;
1049         devrec->spi = spi;
1050         spi_set_drvdata(spi, devrec);
1051         devrec->hw = hw;
1052         devrec->hw->parent = &spi->dev;
1053         devrec->hw->phy->supported.channels[0] = CHANNEL_MASK;
1054         devrec->hw->flags = IEEE802154_HW_TX_OMIT_CKSUM | IEEE802154_HW_AFILT;
1055
1056         mrf24j40_setup_tx_spi_messages(devrec);
1057
1058         devrec->regmap_short = devm_regmap_init_spi(spi,
1059                                                     &mrf24j40_short_regmap);
1060         if (IS_ERR(devrec->regmap_short)) {
1061                 ret = PTR_ERR(devrec->regmap_short);
1062                 dev_err(&spi->dev, "Failed to allocate short register map: %d\n",
1063                         ret);
1064                 goto err_register_device;
1065         }
1066
1067         devrec->regmap_long = devm_regmap_init(&spi->dev,
1068                                                &mrf24j40_long_regmap_bus,
1069                                                spi, &mrf24j40_long_regmap);
1070         if (IS_ERR(devrec->regmap_long)) {
1071                 ret = PTR_ERR(devrec->regmap_long);
1072                 dev_err(&spi->dev, "Failed to allocate long register map: %d\n",
1073                         ret);
1074                 goto err_register_device;
1075         }
1076
1077         devrec->buf = devm_kzalloc(&spi->dev, 3, GFP_KERNEL);
1078         if (!devrec->buf)
1079                 goto err_register_device;
1080
1081         if (spi->max_speed_hz > MAX_SPI_SPEED_HZ) {
1082                 dev_warn(&spi->dev, "spi clock above possible maximum: %d",
1083                          MAX_SPI_SPEED_HZ);
1084                 return -EINVAL;
1085         }
1086
1087         mutex_init(&devrec->buffer_mutex);
1088
1089         ret = mrf24j40_hw_init(devrec);
1090         if (ret)
1091                 goto err_register_device;
1092
1093         mrf24j40_phy_setup(devrec);
1094
1095         ret = devm_request_threaded_irq(&spi->dev,
1096                                         spi->irq,
1097                                         NULL,
1098                                         mrf24j40_isr,
1099                                         IRQF_TRIGGER_LOW|IRQF_ONESHOT,
1100                                         dev_name(&spi->dev),
1101                                         devrec);
1102
1103         if (ret) {
1104                 dev_err(printdev(devrec), "Unable to get IRQ");
1105                 goto err_register_device;
1106         }
1107
1108         dev_dbg(printdev(devrec), "registered mrf24j40\n");
1109         ret = ieee802154_register_hw(devrec->hw);
1110         if (ret)
1111                 goto err_register_device;
1112
1113         return 0;
1114
1115 err_register_device:
1116         ieee802154_free_hw(devrec->hw);
1117 err_ret:
1118         return ret;
1119 }
1120
1121 static int mrf24j40_remove(struct spi_device *spi)
1122 {
1123         struct mrf24j40 *devrec = spi_get_drvdata(spi);
1124
1125         dev_dbg(printdev(devrec), "remove\n");
1126
1127         ieee802154_unregister_hw(devrec->hw);
1128         ieee802154_free_hw(devrec->hw);
1129         /* TODO: Will ieee802154_free_device() wait until ->xmit() is
1130          * complete? */
1131
1132         return 0;
1133 }
1134
1135 static const struct of_device_id mrf24j40_of_match[] = {
1136         { .compatible = "microchip,mrf24j40", .data = (void *)MRF24J40 },
1137         { .compatible = "microchip,mrf24j40ma", .data = (void *)MRF24J40MA },
1138         { .compatible = "microchip,mrf24j40mc", .data = (void *)MRF24J40MC },
1139         { },
1140 };
1141 MODULE_DEVICE_TABLE(of, mrf24j40_of_match);
1142
1143 static const struct spi_device_id mrf24j40_ids[] = {
1144         { "mrf24j40", MRF24J40 },
1145         { "mrf24j40ma", MRF24J40MA },
1146         { "mrf24j40mc", MRF24J40MC },
1147         { },
1148 };
1149 MODULE_DEVICE_TABLE(spi, mrf24j40_ids);
1150
1151 static struct spi_driver mrf24j40_driver = {
1152         .driver = {
1153                 .of_match_table = of_match_ptr(mrf24j40_of_match),
1154                 .name = "mrf24j40",
1155                 .owner = THIS_MODULE,
1156         },
1157         .id_table = mrf24j40_ids,
1158         .probe = mrf24j40_probe,
1159         .remove = mrf24j40_remove,
1160 };
1161
1162 module_spi_driver(mrf24j40_driver);
1163
1164 MODULE_LICENSE("GPL");
1165 MODULE_AUTHOR("Alan Ott");
1166 MODULE_DESCRIPTION("MRF24J40 SPI 802.15.4 Controller Driver");