drivers/net/phy/dp83867.c

   1 /*
   2  * Driver for the Texas Instruments DP83867 PHY
   3  *
   4  * Copyright (C) 2015 Texas Instruments Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/ethtool.h>
  17 #include <linux/kernel.h>
  18 #include <linux/mii.h>
  19 #include <linux/module.h>
  20 #include <linux/of.h>
  21 #include <linux/phy.h>
  22
  23 #include <dt-bindings/net/ti-dp83867.h>
  24
  25 #define DP83867_PHY_ID          0x2000a231
  26 #define DP83867_DEVADDR         0x1f
  27
  28 #define MII_DP83867_PHYCTRL     0x10
  29 #define MII_DP83867_MICR        0x12
  30 #define MII_DP83867_ISR         0x13
  31 #define DP83867_CTRL            0x1f
  32 #define DP83867_CFG3            0x1e
  33
  34 /* Extended Registers */
  35 #define DP83867_RGMIICTL        0x0032
  36 #define DP83867_RGMIIDCTL       0x0086
  37 #define DP83867_IO_MUX_CFG      0x0170
  38
  39 #define DP83867_SW_RESET        BIT(15)
  40 #define DP83867_SW_RESTART      BIT(14)
  41
  42 /* MICR Interrupt bits */
  43 #define MII_DP83867_MICR_AN_ERR_INT_EN          BIT(15)
  44 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN      BIT(14)
  45 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN   BIT(13)
  46 #define MII_DP83867_MICR_PAGE_RXD_INT_EN        BIT(12)
  47 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN    BIT(11)
  48 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN   BIT(10)
  49 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN   BIT(8)
  50 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
  51 #define MII_DP83867_MICR_WOL_INT_EN             BIT(3)
  52 #define MII_DP83867_MICR_XGMII_ERR_INT_EN       BIT(2)
  53 #define MII_DP83867_MICR_POL_CHNG_INT_EN        BIT(1)
  54 #define MII_DP83867_MICR_JABBER_INT_EN          BIT(0)
  55
  56 /* RGMIICTL bits */
  57 #define DP83867_RGMII_TX_CLK_DELAY_EN           BIT(1)
  58 #define DP83867_RGMII_RX_CLK_DELAY_EN           BIT(0)
  59
  60 /* PHY CTRL bits */
  61 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT          14
  62 #define DP83867_PHYCR_FIFO_DEPTH_MASK           (3 << 14)
  63
  64 /* RGMIIDCTL bits */
  65 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT        4
  66
  67 /* IO_MUX_CFG bits */
  68 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL    0x1f
  69
  70 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX     0x0
  71 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN     0x1f
  72
  73 struct dp83867_private {
  74         int rx_id_delay;
  75         int tx_id_delay;
  76         int fifo_depth;
  77         int io_impedance;
  78 };
  79
  80 static int dp83867_ack_interrupt(struct phy_device *phydev)
  81 {
  82         int err = phy_read(phydev, MII_DP83867_ISR);
  83
  84         if (err < 0)
  85                 return err;
  86
  87         return 0;
  88 }
  89
  90 static int dp83867_config_intr(struct phy_device *phydev)
  91 {
  92         int micr_status;
  93
  94         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
  95                 micr_status = phy_read(phydev, MII_DP83867_MICR);
  96                 if (micr_status < 0)
  97                         return micr_status;
  98
  99                 micr_status |=
 100                         (MII_DP83867_MICR_AN_ERR_INT_EN |
 101                         MII_DP83867_MICR_SPEED_CHNG_INT_EN |
 102                         MII_DP83867_MICR_AUTONEG_COMP_INT_EN |
 103                         MII_DP83867_MICR_LINK_STS_CHNG_INT_EN |
 104                         MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
 105                         MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);
 106
 107                 return phy_write(phydev, MII_DP83867_MICR, micr_status);
 108         }
 109
 110         micr_status = 0x0;
 111         return phy_write(phydev, MII_DP83867_MICR, micr_status);
 112 }
 113
 114 #ifdef CONFIG_OF_MDIO
 115 static int dp83867_of_init(struct phy_device *phydev)
 116 {
 117         struct dp83867_private *dp83867 = phydev->priv;
 118         struct device *dev = &phydev->mdio.dev;
 119         struct device_node *of_node = dev->of_node;
 120         int ret;
 121
 122         if (!of_node)
 123                 return -ENODEV;
 124
 125         dp83867->io_impedance = -EINVAL;
 126
 127         /* Optional configuration */
 128         if (of_property_read_bool(of_node, "ti,max-output-impedance"))
 129                 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
 130         else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
 131                 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
 132
 133         ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
 134                                    &dp83867->rx_id_delay);
 135         if (ret &&
 136             (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
 137              phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID))
 138                 return ret;
 139
 140         ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
 141                                    &dp83867->tx_id_delay);
 142         if (ret &&
 143             (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
 144              phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID))
 145                 return ret;
 146
 147         return of_property_read_u32(of_node, "ti,fifo-depth",
 148                                    &dp83867->fifo_depth);
 149 }
 150 #else
 151 static int dp83867_of_init(struct phy_device *phydev)
 152 {
 153         return 0;
 154 }
 155 #endif /* CONFIG_OF_MDIO */
 156
 157 static int dp83867_config_init(struct phy_device *phydev)
 158 {
 159         struct dp83867_private *dp83867;
 160         int ret, val;
 161         u16 delay;
 162
 163         if (!phydev->priv) {
 164                 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
 165                                        GFP_KERNEL);
 166                 if (!dp83867)
 167                         return -ENOMEM;
 168
 169                 phydev->priv = dp83867;
 170                 ret = dp83867_of_init(phydev);
 171                 if (ret)
 172                         return ret;
 173         } else {
 174                 dp83867 = (struct dp83867_private *)phydev->priv;
 175         }
 176
 177         if (phy_interface_is_rgmii(phydev)) {
 178                 val = phy_read(phydev, MII_DP83867_PHYCTRL);
 179                 if (val < 0)
 180                         return val;
 181                 val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
 182                 val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
 183                 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
 184                 if (ret)
 185                         return ret;
 186         }
 187
 188         if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) &&
 189             (phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) {
 190                 val = phy_read_mmd_indirect(phydev, DP83867_RGMIICTL,
 191                                             DP83867_DEVADDR);
 192
 193                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
 194                         val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
 195
 196                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 197                         val |= DP83867_RGMII_TX_CLK_DELAY_EN;
 198
 199                 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
 200                         val |= DP83867_RGMII_RX_CLK_DELAY_EN;
 201
 202                 phy_write_mmd_indirect(phydev, DP83867_RGMIICTL,
 203                                        DP83867_DEVADDR, val);
 204
 205                 delay = (dp83867->rx_id_delay |
 206                         (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
 207
 208                 phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL,
 209                                        DP83867_DEVADDR, delay);
 210
 211                 if (dp83867->io_impedance >= 0) {
 212                         val = phy_read_mmd_indirect(phydev, DP83867_IO_MUX_CFG,
 213                                                     DP83867_DEVADDR);
 214
 215                         val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
 216                         val |= dp83867->io_impedance &
 217                                DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
 218
 219                         phy_write_mmd_indirect(phydev, DP83867_IO_MUX_CFG,
 220                                                DP83867_DEVADDR, val);
 221                 }
 222         }
 223
 224         /* Enable Interrupt output INT_OE in CFG3 register */
 225         if (phy_interrupt_is_valid(phydev)) {
 226                 val = phy_read(phydev, DP83867_CFG3);
 227                 val |= BIT(7);
 228                 phy_write(phydev, DP83867_CFG3, val);
 229         }
 230
 231         return 0;
 232 }
 233
 234 static int dp83867_phy_reset(struct phy_device *phydev)
 235 {
 236         int err;
 237
 238         err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
 239         if (err < 0)
 240                 return err;
 241
 242         return dp83867_config_init(phydev);
 243 }
 244
 245 static struct phy_driver dp83867_driver[] = {
 246         {
 247                 .phy_id         = DP83867_PHY_ID,
 248                 .phy_id_mask    = 0xfffffff0,
 249                 .name           = "TI DP83867",
 250                 .features       = PHY_GBIT_FEATURES,
 251                 .flags          = PHY_HAS_INTERRUPT,
 252
 253                 .config_init    = dp83867_config_init,
 254                 .soft_reset     = dp83867_phy_reset,
 255
 256                 /* IRQ related */
 257                 .ack_interrupt  = dp83867_ack_interrupt,
 258                 .config_intr    = dp83867_config_intr,
 259
 260                 .config_aneg    = genphy_config_aneg,
 261                 .read_status    = genphy_read_status,
 262                 .suspend        = genphy_suspend,
 263                 .resume         = genphy_resume,
 264         },
 265 };
 266 module_phy_driver(dp83867_driver);
 267
 268 static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
 269         { DP83867_PHY_ID, 0xfffffff0 },
 270         { }
 271 };
 272
 273 MODULE_DEVICE_TABLE(mdio, dp83867_tbl);
 274
 275 MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
 276 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
 277 MODULE_LICENSE("GPL");