2 * Driver for the Texas Instruments DP83867 PHY
4 * Copyright (C) 2015 Texas Instruments Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/ethtool.h>
17 #include <linux/kernel.h>
18 #include <linux/mii.h>
19 #include <linux/module.h>
21 #include <linux/phy.h>
23 #include <dt-bindings/net/ti-dp83867.h>
25 #define DP83867_PHY_ID 0x2000a231
26 #define DP83867_DEVADDR 0x1f
28 #define MII_DP83867_PHYCTRL 0x10
29 #define MII_DP83867_MICR 0x12
30 #define MII_DP83867_ISR 0x13
31 #define DP83867_CTRL 0x1f
32 #define DP83867_CFG3 0x1e
34 /* Extended Registers */
35 #define DP83867_RGMIICTL 0x0032
36 #define DP83867_RGMIIDCTL 0x0086
37 #define DP83867_IO_MUX_CFG 0x0170
39 #define DP83867_SW_RESET BIT(15)
40 #define DP83867_SW_RESTART BIT(14)
42 /* MICR Interrupt bits */
43 #define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15)
44 #define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14)
45 #define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13)
46 #define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12)
47 #define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11)
48 #define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10)
49 #define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8)
50 #define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
51 #define MII_DP83867_MICR_WOL_INT_EN BIT(3)
52 #define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2)
53 #define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1)
54 #define MII_DP83867_MICR_JABBER_INT_EN BIT(0)
57 #define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1)
58 #define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0)
61 #define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14
62 #define DP83867_PHYCR_FIFO_DEPTH_MASK (3 << 14)
65 #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
68 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL 0x1f
70 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
71 #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
73 struct dp83867_private
{
80 static int dp83867_ack_interrupt(struct phy_device
*phydev
)
82 int err
= phy_read(phydev
, MII_DP83867_ISR
);
90 static int dp83867_config_intr(struct phy_device
*phydev
)
94 if (phydev
->interrupts
== PHY_INTERRUPT_ENABLED
) {
95 micr_status
= phy_read(phydev
, MII_DP83867_MICR
);
100 (MII_DP83867_MICR_AN_ERR_INT_EN
|
101 MII_DP83867_MICR_SPEED_CHNG_INT_EN
|
102 MII_DP83867_MICR_AUTONEG_COMP_INT_EN
|
103 MII_DP83867_MICR_LINK_STS_CHNG_INT_EN
|
104 MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN
|
105 MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN
);
107 return phy_write(phydev
, MII_DP83867_MICR
, micr_status
);
111 return phy_write(phydev
, MII_DP83867_MICR
, micr_status
);
114 #ifdef CONFIG_OF_MDIO
115 static int dp83867_of_init(struct phy_device
*phydev
)
117 struct dp83867_private
*dp83867
= phydev
->priv
;
118 struct device
*dev
= &phydev
->mdio
.dev
;
119 struct device_node
*of_node
= dev
->of_node
;
125 dp83867
->io_impedance
= -EINVAL
;
127 /* Optional configuration */
128 if (of_property_read_bool(of_node
, "ti,max-output-impedance"))
129 dp83867
->io_impedance
= DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX
;
130 else if (of_property_read_bool(of_node
, "ti,min-output-impedance"))
131 dp83867
->io_impedance
= DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN
;
133 ret
= of_property_read_u32(of_node
, "ti,rx-internal-delay",
134 &dp83867
->rx_id_delay
);
138 ret
= of_property_read_u32(of_node
, "ti,tx-internal-delay",
139 &dp83867
->tx_id_delay
);
143 return of_property_read_u32(of_node
, "ti,fifo-depth",
144 &dp83867
->fifo_depth
);
147 static int dp83867_of_init(struct phy_device
*phydev
)
151 #endif /* CONFIG_OF_MDIO */
153 static int dp83867_config_init(struct phy_device
*phydev
)
155 struct dp83867_private
*dp83867
;
160 dp83867
= devm_kzalloc(&phydev
->mdio
.dev
, sizeof(*dp83867
),
165 phydev
->priv
= dp83867
;
166 ret
= dp83867_of_init(phydev
);
170 dp83867
= (struct dp83867_private
*)phydev
->priv
;
173 if (phy_interface_is_rgmii(phydev
)) {
174 val
= phy_read(phydev
, MII_DP83867_PHYCTRL
);
177 val
&= ~DP83867_PHYCR_FIFO_DEPTH_MASK
;
178 val
|= (dp83867
->fifo_depth
<< DP83867_PHYCR_FIFO_DEPTH_SHIFT
);
179 ret
= phy_write(phydev
, MII_DP83867_PHYCTRL
, val
);
184 if ((phydev
->interface
>= PHY_INTERFACE_MODE_RGMII_ID
) &&
185 (phydev
->interface
<= PHY_INTERFACE_MODE_RGMII_RXID
)) {
186 val
= phy_read_mmd_indirect(phydev
, DP83867_RGMIICTL
,
189 if (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_ID
)
190 val
|= (DP83867_RGMII_TX_CLK_DELAY_EN
| DP83867_RGMII_RX_CLK_DELAY_EN
);
192 if (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_TXID
)
193 val
|= DP83867_RGMII_TX_CLK_DELAY_EN
;
195 if (phydev
->interface
== PHY_INTERFACE_MODE_RGMII_RXID
)
196 val
|= DP83867_RGMII_RX_CLK_DELAY_EN
;
198 phy_write_mmd_indirect(phydev
, DP83867_RGMIICTL
,
199 DP83867_DEVADDR
, val
);
201 delay
= (dp83867
->rx_id_delay
|
202 (dp83867
->tx_id_delay
<< DP83867_RGMII_TX_CLK_DELAY_SHIFT
));
204 phy_write_mmd_indirect(phydev
, DP83867_RGMIIDCTL
,
205 DP83867_DEVADDR
, delay
);
207 if (dp83867
->io_impedance
>= 0) {
208 val
= phy_read_mmd_indirect(phydev
, DP83867_IO_MUX_CFG
,
211 val
&= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL
;
212 val
|= dp83867
->io_impedance
&
213 DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL
;
215 phy_write_mmd_indirect(phydev
, DP83867_IO_MUX_CFG
,
216 DP83867_DEVADDR
, val
);
220 /* Enable Interrupt output INT_OE in CFG3 register */
221 if (phy_interrupt_is_valid(phydev
)) {
222 val
= phy_read(phydev
, DP83867_CFG3
);
224 phy_write(phydev
, DP83867_CFG3
, val
);
230 static int dp83867_phy_reset(struct phy_device
*phydev
)
234 err
= phy_write(phydev
, DP83867_CTRL
, DP83867_SW_RESET
);
238 return dp83867_config_init(phydev
);
241 static struct phy_driver dp83867_driver
[] = {
243 .phy_id
= DP83867_PHY_ID
,
244 .phy_id_mask
= 0xfffffff0,
245 .name
= "TI DP83867",
246 .features
= PHY_GBIT_FEATURES
,
247 .flags
= PHY_HAS_INTERRUPT
,
249 .config_init
= dp83867_config_init
,
250 .soft_reset
= dp83867_phy_reset
,
253 .ack_interrupt
= dp83867_ack_interrupt
,
254 .config_intr
= dp83867_config_intr
,
256 .config_aneg
= genphy_config_aneg
,
257 .read_status
= genphy_read_status
,
258 .suspend
= genphy_suspend
,
259 .resume
= genphy_resume
,
262 module_phy_driver(dp83867_driver
);
264 static struct mdio_device_id __maybe_unused dp83867_tbl
[] = {
265 { DP83867_PHY_ID
, 0xfffffff0 },
269 MODULE_DEVICE_TABLE(mdio
, dp83867_tbl
);
271 MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
272 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
273 MODULE_LICENSE("GPL");