]> git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blob - drivers/net/phy/marvell.c
projects / mirror_ubuntu-zesty-kernel.git / blob
? search:


ed0d235cf850ea11564bb446f8c8fc53879a9e73
[mirror_ubuntu-zesty-kernel.git] / drivers / net / phy / marvell.c
1 /*
2 * drivers/net/phy/marvell.c
3 *
4 * Driver for Marvell PHYs
5 *
6 * Author: Andy Fleming
7 *
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
9 *
10 * Copyright (c) 2013 Michael Stapelberg <michael@stapelberg.de>
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 */
18 #include <linux/kernel.h>
19 #include <linux/string.h>
20 #include <linux/errno.h>
21 #include <linux/unistd.h>
22 #include <linux/interrupt.h>
23 #include <linux/init.h>
24 #include <linux/delay.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/skbuff.h>
28 #include <linux/spinlock.h>
29 #include <linux/mm.h>
30 #include <linux/module.h>
31 #include <linux/mii.h>
32 #include <linux/ethtool.h>
33 #include <linux/phy.h>
34 #include <linux/marvell_phy.h>
35 #include <linux/of.h>
36
37 #include <linux/io.h>
38 #include <asm/irq.h>
39 #include <linux/uaccess.h>
40
41 #define MII_MARVELL_PHY_PAGE 22
42
43 #define MII_M1011_IEVENT 0x13
44 #define MII_M1011_IEVENT_CLEAR 0x0000
45
46 #define MII_M1011_IMASK 0x12
47 #define MII_M1011_IMASK_INIT 0x6400
48 #define MII_M1011_IMASK_CLEAR 0x0000
49
50 #define MII_M1011_PHY_SCR 0x10
51 #define MII_M1011_PHY_SCR_MDI 0x0000
52 #define MII_M1011_PHY_SCR_MDI_X 0x0020
53 #define MII_M1011_PHY_SCR_AUTO_CROSS 0x0060
54
55 #define MII_M1145_PHY_EXT_ADDR_PAGE 0x16
56 #define MII_M1145_PHY_EXT_SR 0x1b
57 #define MII_M1145_PHY_EXT_CR 0x14
58 #define MII_M1145_RGMII_RX_DELAY 0x0080
59 #define MII_M1145_RGMII_TX_DELAY 0x0002
60 #define MII_M1145_HWCFG_MODE_SGMII_NO_CLK 0x4
61 #define MII_M1145_HWCFG_MODE_MASK 0xf
62 #define MII_M1145_HWCFG_FIBER_COPPER_AUTO 0x8000
63
64 #define MII_M1145_HWCFG_MODE_SGMII_NO_CLK 0x4
65 #define MII_M1145_HWCFG_MODE_MASK 0xf
66 #define MII_M1145_HWCFG_FIBER_COPPER_AUTO 0x8000
67
68 #define MII_M1111_PHY_LED_CONTROL 0x18
69 #define MII_M1111_PHY_LED_DIRECT 0x4100
70 #define MII_M1111_PHY_LED_COMBINE 0x411c
71 #define MII_M1111_PHY_EXT_CR 0x14
72 #define MII_M1111_RX_DELAY 0x80
73 #define MII_M1111_TX_DELAY 0x2
74 #define MII_M1111_PHY_EXT_SR 0x1b
75
76 #define MII_M1111_HWCFG_MODE_MASK 0xf
77 #define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb
78 #define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3
79 #define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4
80 #define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9
81 #define MII_M1111_HWCFG_FIBER_COPPER_AUTO 0x8000
82 #define MII_M1111_HWCFG_FIBER_COPPER_RES 0x2000
83
84 #define MII_M1111_COPPER 0
85 #define MII_M1111_FIBER 1
86
87 #define MII_88E1121_PHY_MSCR_PAGE 2
88 #define MII_88E1121_PHY_MSCR_REG 21
89 #define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5)
90 #define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4)
91 #define MII_88E1121_PHY_MSCR_DELAY_MASK (~(0x3 << 4))
92
93 #define MII_88E1318S_PHY_MSCR1_REG 16
94 #define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6)
95
96 /* Copper Specific Interrupt Enable Register */
97 #define MII_88E1318S_PHY_CSIER 0x12
98 /* WOL Event Interrupt Enable */
99 #define MII_88E1318S_PHY_CSIER_WOL_EIE BIT(7)
100
101 /* LED Timer Control Register */
102 #define MII_88E1318S_PHY_LED_PAGE 0x03
103 #define MII_88E1318S_PHY_LED_TCR 0x12
104 #define MII_88E1318S_PHY_LED_TCR_FORCE_INT BIT(15)
105 #define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE BIT(7)
106 #define MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW BIT(11)
107
108 /* Magic Packet MAC address registers */
109 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD2 0x17
110 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD1 0x18
111 #define MII_88E1318S_PHY_MAGIC_PACKET_WORD0 0x19
112
113 #define MII_88E1318S_PHY_WOL_PAGE 0x11
114 #define MII_88E1318S_PHY_WOL_CTRL 0x10
115 #define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS BIT(12)
116 #define MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE BIT(14)
117
118 #define MII_88E1121_PHY_LED_CTRL 16
119 #define MII_88E1121_PHY_LED_PAGE 3
120 #define MII_88E1121_PHY_LED_DEF 0x0030
121
122 #define MII_M1011_PHY_STATUS 0x11
123 #define MII_M1011_PHY_STATUS_1000 0x8000
124 #define MII_M1011_PHY_STATUS_100 0x4000
125 #define MII_M1011_PHY_STATUS_SPD_MASK 0xc000
126 #define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000
127 #define MII_M1011_PHY_STATUS_RESOLVED 0x0800
128 #define MII_M1011_PHY_STATUS_LINK 0x0400
129
130 #define MII_M1116R_CONTROL_REG_MAC 21
131
132 #define MII_88E3016_PHY_SPEC_CTRL 0x10
133 #define MII_88E3016_DISABLE_SCRAMBLER 0x0200
134 #define MII_88E3016_AUTO_MDIX_CROSSOVER 0x0030
135
136 #define MII_88E1510_GEN_CTRL_REG_1 0x14
137 #define MII_88E1510_GEN_CTRL_REG_1_MODE_MASK 0x7
138 #define MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII 0x1 /* SGMII to copper */
139 #define MII_88E1510_GEN_CTRL_REG_1_RESET 0x8000 /* Soft reset */
140
141 #define LPA_FIBER_1000HALF 0x40
142 #define LPA_FIBER_1000FULL 0x20
143
144 #define LPA_PAUSE_FIBER 0x180
145 #define LPA_PAUSE_ASYM_FIBER 0x100
146
147 #define ADVERTISE_FIBER_1000HALF 0x40
148 #define ADVERTISE_FIBER_1000FULL 0x20
149
150 #define ADVERTISE_PAUSE_FIBER 0x180
151 #define ADVERTISE_PAUSE_ASYM_FIBER 0x100
152
153 #define REGISTER_LINK_STATUS 0x400
154 #define NB_FIBER_STATS 1
155
156 MODULE_DESCRIPTION("Marvell PHY driver");
157 MODULE_AUTHOR("Andy Fleming");
158 MODULE_LICENSE("GPL");
159
160 struct marvell_hw_stat {
161 const char *string;
162 u8 page;
163 u8 reg;
164 u8 bits;
165 };
166
167 static struct marvell_hw_stat marvell_hw_stats[] = {
168 { "phy_receive_errors_copper", 0, 21, 16},
169 { "phy_idle_errors", 0, 10, 8 },
170 { "phy_receive_errors_fiber", 1, 21, 16},
171 };
172
173 struct marvell_priv {
174 u64 stats[ARRAY_SIZE(marvell_hw_stats)];
175 };
176
177 static int marvell_ack_interrupt(struct phy_device *phydev)
178 {
179 int err;
180
181 /* Clear the interrupts by reading the reg */
182 err = phy_read(phydev, MII_M1011_IEVENT);
183
184 if (err < 0)
185 return err;
186
187 return 0;
188 }
189
190 static int marvell_config_intr(struct phy_device *phydev)
191 {
192 int err;
193
194 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
195 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
196 else
197 err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
198
199 return err;
200 }
201
202 static int marvell_set_polarity(struct phy_device *phydev, int polarity)
203 {
204 int reg;
205 int err;
206 int val;
207
208 /* get the current settings */
209 reg = phy_read(phydev, MII_M1011_PHY_SCR);
210 if (reg < 0)
211 return reg;
212
213 val = reg;
214 val &= ~MII_M1011_PHY_SCR_AUTO_CROSS;
215 switch (polarity) {
216 case ETH_TP_MDI:
217 val |= MII_M1011_PHY_SCR_MDI;
218 break;
219 case ETH_TP_MDI_X:
220 val |= MII_M1011_PHY_SCR_MDI_X;
221 break;
222 case ETH_TP_MDI_AUTO:
223 case ETH_TP_MDI_INVALID:
224 default:
225 val |= MII_M1011_PHY_SCR_AUTO_CROSS;
226 break;
227 }
228
229 if (val != reg) {
230 /* Set the new polarity value in the register */
231 err = phy_write(phydev, MII_M1011_PHY_SCR, val);
232 if (err)
233 return err;
234 }
235
236 return 0;
237 }
238
239 static int marvell_config_aneg(struct phy_device *phydev)
240 {
241 int err;
242
243 /* The Marvell PHY has an errata which requires
244 * that certain registers get written in order
245 * to restart autonegotiation */
246 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
247
248 if (err < 0)
249 return err;
250
251 err = phy_write(phydev, 0x1d, 0x1f);
252 if (err < 0)
253 return err;
254
255 err = phy_write(phydev, 0x1e, 0x200c);
256 if (err < 0)
257 return err;
258
259 err = phy_write(phydev, 0x1d, 0x5);
260 if (err < 0)
261 return err;
262
263 err = phy_write(phydev, 0x1e, 0);
264 if (err < 0)
265 return err;
266
267 err = phy_write(phydev, 0x1e, 0x100);
268 if (err < 0)
269 return err;
270
271 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
272 if (err < 0)
273 return err;
274
275 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
276 MII_M1111_PHY_LED_DIRECT);
277 if (err < 0)
278 return err;
279
280 err = genphy_config_aneg(phydev);
281 if (err < 0)
282 return err;
283
284 if (phydev->autoneg != AUTONEG_ENABLE) {
285 int bmcr;
286
287 /*
288 * A write to speed/duplex bits (that is performed by
289 * genphy_config_aneg() call above) must be followed by
290 * a software reset. Otherwise, the write has no effect.
291 */
292 bmcr = phy_read(phydev, MII_BMCR);
293 if (bmcr < 0)
294 return bmcr;
295
296 err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET);
297 if (err < 0)
298 return err;
299 }
300
301 return 0;
302 }
303
304 static int m88e1111_config_aneg(struct phy_device *phydev)
305 {
306 int err;
307
308 /* The Marvell PHY has an errata which requires
309 * that certain registers get written in order
310 * to restart autonegotiation
311 */
312 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
313
314 err = marvell_set_polarity(phydev, phydev->mdix_ctrl);
315 if (err < 0)
316 return err;
317
318 err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL,
319 MII_M1111_PHY_LED_DIRECT);
320 if (err < 0)
321 return err;
322
323 err = genphy_config_aneg(phydev);
324 if (err < 0)
325 return err;
326
327 if (phydev->autoneg != AUTONEG_ENABLE) {
328 int bmcr;
329
330 /* A write to speed/duplex bits (that is performed by
331 * genphy_config_aneg() call above) must be followed by
332 * a software reset. Otherwise, the write has no effect.
333 */
334 bmcr = phy_read(phydev, MII_BMCR);
335 if (bmcr < 0)
336 return bmcr;
337
338 err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET);
339 if (err < 0)
340 return err;
341 }
342
343 return 0;
344 }
345
346 #ifdef CONFIG_OF_MDIO
347 /*
348 * Set and/or override some configuration registers based on the
349 * marvell,reg-init property stored in the of_node for the phydev.
350 *
351 * marvell,reg-init = <reg-page reg mask value>,...;
352 *
353 * There may be one or more sets of <reg-page reg mask value>:
354 *
355 * reg-page: which register bank to use.
356 * reg: the register.
357 * mask: if non-zero, ANDed with existing register value.
358 * value: ORed with the masked value and written to the regiser.
359 *
360 */
361 static int marvell_of_reg_init(struct phy_device *phydev)
362 {
363 const __be32 *paddr;
364 int len, i, saved_page, current_page, ret;
365
366 if (!phydev->mdio.dev.of_node)
367 return 0;
368
369 paddr = of_get_property(phydev->mdio.dev.of_node,
370 "marvell,reg-init", &len);
371 if (!paddr || len < (4 * sizeof(*paddr)))
372 return 0;
373
374 saved_page = phy_read(phydev, MII_MARVELL_PHY_PAGE);
375 if (saved_page < 0)
376 return saved_page;
377 current_page = saved_page;
378
379 ret = 0;
380 len /= sizeof(*paddr);
381 for (i = 0; i < len - 3; i += 4) {
382 u16 reg_page = be32_to_cpup(paddr + i);
383 u16 reg = be32_to_cpup(paddr + i + 1);
384 u16 mask = be32_to_cpup(paddr + i + 2);
385 u16 val_bits = be32_to_cpup(paddr + i + 3);
386 int val;
387
388 if (reg_page != current_page) {
389 current_page = reg_page;
390 ret = phy_write(phydev, MII_MARVELL_PHY_PAGE, reg_page);
391 if (ret < 0)
392 goto err;
393 }
394
395 val = 0;
396 if (mask) {
397 val = phy_read(phydev, reg);
398 if (val < 0) {
399 ret = val;
400 goto err;
401 }
402 val &= mask;
403 }
404 val |= val_bits;
405
406 ret = phy_write(phydev, reg, val);
407 if (ret < 0)
408 goto err;
409
410 }
411 err:
412 if (current_page != saved_page) {
413 i = phy_write(phydev, MII_MARVELL_PHY_PAGE, saved_page);
414 if (ret == 0)
415 ret = i;
416 }
417 return ret;
418 }
419 #else
420 static int marvell_of_reg_init(struct phy_device *phydev)
421 {
422 return 0;
423 }
424 #endif /* CONFIG_OF_MDIO */
425
426 static int m88e1121_config_aneg(struct phy_device *phydev)
427 {
428 int err, oldpage, mscr;
429
430 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
431
432 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
433 MII_88E1121_PHY_MSCR_PAGE);
434 if (err < 0)
435 return err;
436
437 if (phy_interface_is_rgmii(phydev)) {
438
439 mscr = phy_read(phydev, MII_88E1121_PHY_MSCR_REG) &
440 MII_88E1121_PHY_MSCR_DELAY_MASK;
441
442 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
443 mscr |= (MII_88E1121_PHY_MSCR_RX_DELAY |
444 MII_88E1121_PHY_MSCR_TX_DELAY);
445 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
446 mscr |= MII_88E1121_PHY_MSCR_RX_DELAY;
447 else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
448 mscr |= MII_88E1121_PHY_MSCR_TX_DELAY;
449
450 err = phy_write(phydev, MII_88E1121_PHY_MSCR_REG, mscr);
451 if (err < 0)
452 return err;
453 }
454
455 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
456
457 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
458 if (err < 0)
459 return err;
460
461 err = phy_write(phydev, MII_M1011_PHY_SCR,
462 MII_M1011_PHY_SCR_AUTO_CROSS);
463 if (err < 0)
464 return err;
465
466 return genphy_config_aneg(phydev);
467 }
468
469 static int m88e1318_config_aneg(struct phy_device *phydev)
470 {
471 int err, oldpage, mscr;
472
473 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
474
475 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
476 MII_88E1121_PHY_MSCR_PAGE);
477 if (err < 0)
478 return err;
479
480 mscr = phy_read(phydev, MII_88E1318S_PHY_MSCR1_REG);
481 mscr |= MII_88E1318S_PHY_MSCR1_PAD_ODD;
482
483 err = phy_write(phydev, MII_88E1318S_PHY_MSCR1_REG, mscr);
484 if (err < 0)
485 return err;
486
487 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
488 if (err < 0)
489 return err;
490
491 return m88e1121_config_aneg(phydev);
492 }
493
494 /**
495 * ethtool_adv_to_fiber_adv_t
496 * @ethadv: the ethtool advertisement settings
497 *
498 * A small helper function that translates ethtool advertisement
499 * settings to phy autonegotiation advertisements for the
500 * MII_ADV register for fiber link.
501 */
502 static inline u32 ethtool_adv_to_fiber_adv_t(u32 ethadv)
503 {
504 u32 result = 0;
505
506 if (ethadv & ADVERTISED_1000baseT_Half)
507 result |= ADVERTISE_FIBER_1000HALF;
508 if (ethadv & ADVERTISED_1000baseT_Full)
509 result |= ADVERTISE_FIBER_1000FULL;
510
511 if ((ethadv & ADVERTISE_PAUSE_ASYM) && (ethadv & ADVERTISE_PAUSE_CAP))
512 result |= LPA_PAUSE_ASYM_FIBER;
513 else if (ethadv & ADVERTISE_PAUSE_CAP)
514 result |= (ADVERTISE_PAUSE_FIBER
515 & (~ADVERTISE_PAUSE_ASYM_FIBER));
516
517 return result;
518 }
519
520 /**
521 * marvell_config_aneg_fiber - restart auto-negotiation or write BMCR
522 * @phydev: target phy_device struct
523 *
524 * Description: If auto-negotiation is enabled, we configure the
525 * advertising, and then restart auto-negotiation. If it is not
526 * enabled, then we write the BMCR. Adapted for fiber link in
527 * some Marvell's devices.
528 */
529 static int marvell_config_aneg_fiber(struct phy_device *phydev)
530 {
531 int changed = 0;
532 int err;
533 int adv, oldadv;
534 u32 advertise;
535
536 if (phydev->autoneg != AUTONEG_ENABLE)
537 return genphy_setup_forced(phydev);
538
539 /* Only allow advertising what this PHY supports */
540 phydev->advertising &= phydev->supported;
541 advertise = phydev->advertising;
542
543 /* Setup fiber advertisement */
544 adv = phy_read(phydev, MII_ADVERTISE);
545 if (adv < 0)
546 return adv;
547
548 oldadv = adv;
549 adv &= ~(ADVERTISE_FIBER_1000HALF | ADVERTISE_FIBER_1000FULL
550 | LPA_PAUSE_FIBER);
551 adv |= ethtool_adv_to_fiber_adv_t(advertise);
552
553 if (adv != oldadv) {
554 err = phy_write(phydev, MII_ADVERTISE, adv);
555 if (err < 0)
556 return err;
557
558 changed = 1;
559 }
560
561 if (changed == 0) {
562 /* Advertisement hasn't changed, but maybe aneg was never on to
563 * begin with? Or maybe phy was isolated?
564 */
565 int ctl = phy_read(phydev, MII_BMCR);
566
567 if (ctl < 0)
568 return ctl;
569
570 if (!(ctl & BMCR_ANENABLE) || (ctl & BMCR_ISOLATE))
571 changed = 1; /* do restart aneg */
572 }
573
574 /* Only restart aneg if we are advertising something different
575 * than we were before.
576 */
577 if (changed > 0)
578 changed = genphy_restart_aneg(phydev);
579
580 return changed;
581 }
582
583 static int m88e1510_config_aneg(struct phy_device *phydev)
584 {
585 int err;
586
587 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
588 if (err < 0)
589 goto error;
590
591 /* Configure the copper link first */
592 err = m88e1318_config_aneg(phydev);
593 if (err < 0)
594 goto error;
595
596 /* Then the fiber link */
597 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_FIBER);
598 if (err < 0)
599 goto error;
600
601 err = marvell_config_aneg_fiber(phydev);
602 if (err < 0)
603 goto error;
604
605 return phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
606
607 error:
608 phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
609 return err;
610 }
611
612 static int marvell_config_init(struct phy_device *phydev)
613 {
614 /* Set registers from marvell,reg-init DT property */
615 return marvell_of_reg_init(phydev);
616 }
617
618 static int m88e1116r_config_init(struct phy_device *phydev)
619 {
620 int temp;
621 int err;
622
623 temp = phy_read(phydev, MII_BMCR);
624 temp |= BMCR_RESET;
625 err = phy_write(phydev, MII_BMCR, temp);
626 if (err < 0)
627 return err;
628
629 mdelay(500);
630
631 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
632 if (err < 0)
633 return err;
634
635 temp = phy_read(phydev, MII_M1011_PHY_SCR);
636 temp |= (7 << 12); /* max number of gigabit attempts */
637 temp |= (1 << 11); /* enable downshift */
638 temp |= MII_M1011_PHY_SCR_AUTO_CROSS;
639 err = phy_write(phydev, MII_M1011_PHY_SCR, temp);
640 if (err < 0)
641 return err;
642
643 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 2);
644 if (err < 0)
645 return err;
646 temp = phy_read(phydev, MII_M1116R_CONTROL_REG_MAC);
647 temp |= (1 << 5);
648 temp |= (1 << 4);
649 err = phy_write(phydev, MII_M1116R_CONTROL_REG_MAC, temp);
650 if (err < 0)
651 return err;
652 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
653 if (err < 0)
654 return err;
655
656 temp = phy_read(phydev, MII_BMCR);
657 temp |= BMCR_RESET;
658 err = phy_write(phydev, MII_BMCR, temp);
659 if (err < 0)
660 return err;
661
662 mdelay(500);
663
664 return marvell_config_init(phydev);
665 }
666
667 static int m88e3016_config_init(struct phy_device *phydev)
668 {
669 int reg;
670
671 /* Enable Scrambler and Auto-Crossover */
672 reg = phy_read(phydev, MII_88E3016_PHY_SPEC_CTRL);
673 if (reg < 0)
674 return reg;
675
676 reg &= ~MII_88E3016_DISABLE_SCRAMBLER;
677 reg |= MII_88E3016_AUTO_MDIX_CROSSOVER;
678
679 reg = phy_write(phydev, MII_88E3016_PHY_SPEC_CTRL, reg);
680 if (reg < 0)
681 return reg;
682
683 return marvell_config_init(phydev);
684 }
685
686 static int m88e1111_config_init(struct phy_device *phydev)
687 {
688 int err;
689 int temp;
690
691 if (phy_interface_is_rgmii(phydev)) {
692
693 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
694 if (temp < 0)
695 return temp;
696
697 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
698 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
699 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
700 temp &= ~MII_M1111_TX_DELAY;
701 temp |= MII_M1111_RX_DELAY;
702 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
703 temp &= ~MII_M1111_RX_DELAY;
704 temp |= MII_M1111_TX_DELAY;
705 }
706
707 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
708 if (err < 0)
709 return err;
710
711 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
712 if (temp < 0)
713 return temp;
714
715 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
716
717 if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES)
718 temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII;
719 else
720 temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII;
721
722 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
723 if (err < 0)
724 return err;
725 }
726
727 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
728 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
729 if (temp < 0)
730 return temp;
731
732 temp &= ~(MII_M1111_HWCFG_MODE_MASK);
733 temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK;
734 temp |= MII_M1111_HWCFG_FIBER_COPPER_AUTO;
735
736 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
737 if (err < 0)
738 return err;
739
740 /* make sure copper is selected */
741 err = phy_read(phydev, MII_M1145_PHY_EXT_ADDR_PAGE);
742 if (err < 0)
743 return err;
744
745 err = phy_write(phydev, MII_M1145_PHY_EXT_ADDR_PAGE,
746 err & (~0xff));
747 if (err < 0)
748 return err;
749 }
750
751 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
752 temp = phy_read(phydev, MII_M1111_PHY_EXT_CR);
753 if (temp < 0)
754 return temp;
755 temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY);
756 err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp);
757 if (err < 0)
758 return err;
759
760 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
761 if (temp < 0)
762 return temp;
763 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
764 temp |= 0x7 | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
765 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
766 if (err < 0)
767 return err;
768
769 /* soft reset */
770 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
771 if (err < 0)
772 return err;
773 do
774 temp = phy_read(phydev, MII_BMCR);
775 while (temp & BMCR_RESET);
776
777 temp = phy_read(phydev, MII_M1111_PHY_EXT_SR);
778 if (temp < 0)
779 return temp;
780 temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES);
781 temp |= MII_M1111_HWCFG_MODE_COPPER_RTBI | MII_M1111_HWCFG_FIBER_COPPER_AUTO;
782 err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp);
783 if (err < 0)
784 return err;
785 }
786
787 err = marvell_of_reg_init(phydev);
788 if (err < 0)
789 return err;
790
791 return phy_write(phydev, MII_BMCR, BMCR_RESET);
792 }
793
794 static int m88e1121_config_init(struct phy_device *phydev)
795 {
796 int err, oldpage;
797
798 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
799
800 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_88E1121_PHY_LED_PAGE);
801 if (err < 0)
802 return err;
803
804 /* Default PHY LED config: LED[0] .. Link, LED[1] .. Activity */
805 err = phy_write(phydev, MII_88E1121_PHY_LED_CTRL,
806 MII_88E1121_PHY_LED_DEF);
807 if (err < 0)
808 return err;
809
810 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
811
812 /* Set marvell,reg-init configuration from device tree */
813 return marvell_config_init(phydev);
814 }
815
816 static int m88e1510_config_init(struct phy_device *phydev)
817 {
818 int err;
819 int temp;
820
821 /* SGMII-to-Copper mode initialization */
822 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
823 /* Select page 18 */
824 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 18);
825 if (err < 0)
826 return err;
827
828 /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */
829 temp = phy_read(phydev, MII_88E1510_GEN_CTRL_REG_1);
830 temp &= ~MII_88E1510_GEN_CTRL_REG_1_MODE_MASK;
831 temp |= MII_88E1510_GEN_CTRL_REG_1_MODE_SGMII;
832 err = phy_write(phydev, MII_88E1510_GEN_CTRL_REG_1, temp);
833 if (err < 0)
834 return err;
835
836 /* PHY reset is necessary after changing MODE[2:0] */
837 temp |= MII_88E1510_GEN_CTRL_REG_1_RESET;
838 err = phy_write(phydev, MII_88E1510_GEN_CTRL_REG_1, temp);
839 if (err < 0)
840 return err;
841
842 /* Reset page selection */
843 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0);
844 if (err < 0)
845 return err;
846 }
847
848 return m88e1121_config_init(phydev);
849 }
850
851 static int m88e1118_config_aneg(struct phy_device *phydev)
852 {
853 int err;
854
855 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
856 if (err < 0)
857 return err;
858
859 err = phy_write(phydev, MII_M1011_PHY_SCR,
860 MII_M1011_PHY_SCR_AUTO_CROSS);
861 if (err < 0)
862 return err;
863
864 err = genphy_config_aneg(phydev);
865 return 0;
866 }
867
868 static int m88e1118_config_init(struct phy_device *phydev)
869 {
870 int err;
871
872 /* Change address */
873 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
874 if (err < 0)
875 return err;
876
877 /* Enable 1000 Mbit */
878 err = phy_write(phydev, 0x15, 0x1070);
879 if (err < 0)
880 return err;
881
882 /* Change address */
883 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0003);
884 if (err < 0)
885 return err;
886
887 /* Adjust LED Control */
888 if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
889 err = phy_write(phydev, 0x10, 0x1100);
890 else
891 err = phy_write(phydev, 0x10, 0x021e);
892 if (err < 0)
893 return err;
894
895 err = marvell_of_reg_init(phydev);
896 if (err < 0)
897 return err;
898
899 /* Reset address */
900 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
901 if (err < 0)
902 return err;
903
904 return phy_write(phydev, MII_BMCR, BMCR_RESET);
905 }
906
907 static int m88e1149_config_init(struct phy_device *phydev)
908 {
909 int err;
910
911 /* Change address */
912 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002);
913 if (err < 0)
914 return err;
915
916 /* Enable 1000 Mbit */
917 err = phy_write(phydev, 0x15, 0x1048);
918 if (err < 0)
919 return err;
920
921 err = marvell_of_reg_init(phydev);
922 if (err < 0)
923 return err;
924
925 /* Reset address */
926 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0);
927 if (err < 0)
928 return err;
929
930 return phy_write(phydev, MII_BMCR, BMCR_RESET);
931 }
932
933 static int m88e1145_config_init(struct phy_device *phydev)
934 {
935 int err;
936 int temp;
937
938 /* Take care of errata E0 & E1 */
939 err = phy_write(phydev, 0x1d, 0x001b);
940 if (err < 0)
941 return err;
942
943 err = phy_write(phydev, 0x1e, 0x418f);
944 if (err < 0)
945 return err;
946
947 err = phy_write(phydev, 0x1d, 0x0016);
948 if (err < 0)
949 return err;
950
951 err = phy_write(phydev, 0x1e, 0xa2da);
952 if (err < 0)
953 return err;
954
955 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) {
956 int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR);
957 if (temp < 0)
958 return temp;
959
960 temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY);
961
962 err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp);
963 if (err < 0)
964 return err;
965
966 if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) {
967 err = phy_write(phydev, 0x1d, 0x0012);
968 if (err < 0)
969 return err;
970
971 temp = phy_read(phydev, 0x1e);
972 if (temp < 0)
973 return temp;
974
975 temp &= 0xf03f;
976 temp |= 2 << 9; /* 36 ohm */
977 temp |= 2 << 6; /* 39 ohm */
978
979 err = phy_write(phydev, 0x1e, temp);
980 if (err < 0)
981 return err;
982
983 err = phy_write(phydev, 0x1d, 0x3);
984 if (err < 0)
985 return err;
986
987 err = phy_write(phydev, 0x1e, 0x8000);
988 if (err < 0)
989 return err;
990 }
991 }
992
993 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
994 temp = phy_read(phydev, MII_M1145_PHY_EXT_SR);
995 if (temp < 0)
996 return temp;
997
998 temp &= ~MII_M1145_HWCFG_MODE_MASK;
999 temp |= MII_M1145_HWCFG_MODE_SGMII_NO_CLK;
1000 temp |= MII_M1145_HWCFG_FIBER_COPPER_AUTO;
1001
1002 err = phy_write(phydev, MII_M1145_PHY_EXT_SR, temp);
1003 if (err < 0)
1004 return err;
1005 }
1006
1007 err = marvell_of_reg_init(phydev);
1008 if (err < 0)
1009 return err;
1010
1011 return 0;
1012 }
1013
1014 /**
1015 * fiber_lpa_to_ethtool_lpa_t
1016 * @lpa: value of the MII_LPA register for fiber link
1017 *
1018 * A small helper function that translates MII_LPA
1019 * bits to ethtool LP advertisement settings.
1020 */
1021 static u32 fiber_lpa_to_ethtool_lpa_t(u32 lpa)
1022 {
1023 u32 result = 0;
1024
1025 if (lpa & LPA_FIBER_1000HALF)
1026 result |= ADVERTISED_1000baseT_Half;
1027 if (lpa & LPA_FIBER_1000FULL)
1028 result |= ADVERTISED_1000baseT_Full;
1029
1030 return result;
1031 }
1032
1033 /**
1034 * marvell_update_link - update link status in real time in @phydev
1035 * @phydev: target phy_device struct
1036 *
1037 * Description: Update the value in phydev->link to reflect the
1038 * current link value.
1039 */
1040 static int marvell_update_link(struct phy_device *phydev, int fiber)
1041 {
1042 int status;
1043
1044 /* Use the generic register for copper link, or specific
1045 * register for fiber case */
1046 if (fiber) {
1047 status = phy_read(phydev, MII_M1011_PHY_STATUS);
1048 if (status < 0)
1049 return status;
1050
1051 if ((status & REGISTER_LINK_STATUS) == 0)
1052 phydev->link = 0;
1053 else
1054 phydev->link = 1;
1055 } else {
1056 return genphy_update_link(phydev);
1057 }
1058
1059 return 0;
1060 }
1061
1062 /* marvell_read_status_page
1063 *
1064 * Description:
1065 * Check the link, then figure out the current state
1066 * by comparing what we advertise with what the link partner
1067 * advertises. Start by checking the gigabit possibilities,
1068 * then move on to 10/100.
1069 */
1070 static int marvell_read_status_page(struct phy_device *phydev, int page)
1071 {
1072 int adv;
1073 int err;
1074 int lpa;
1075 int lpagb;
1076 int status = 0;
1077 int fiber;
1078
1079 /* Detect and update the link, but return if there
1080 * was an error */
1081 if (page == MII_M1111_FIBER)
1082 fiber = 1;
1083 else
1084 fiber = 0;
1085
1086 err = marvell_update_link(phydev, fiber);
1087 if (err)
1088 return err;
1089
1090 if (AUTONEG_ENABLE == phydev->autoneg) {
1091 status = phy_read(phydev, MII_M1011_PHY_STATUS);
1092 if (status < 0)
1093 return status;
1094
1095 lpa = phy_read(phydev, MII_LPA);
1096 if (lpa < 0)
1097 return lpa;
1098
1099 lpagb = phy_read(phydev, MII_STAT1000);
1100 if (lpagb < 0)
1101 return lpagb;
1102
1103 adv = phy_read(phydev, MII_ADVERTISE);
1104 if (adv < 0)
1105 return adv;
1106
1107 lpa &= adv;
1108
1109 if (status & MII_M1011_PHY_STATUS_FULLDUPLEX)
1110 phydev->duplex = DUPLEX_FULL;
1111 else
1112 phydev->duplex = DUPLEX_HALF;
1113
1114 status = status & MII_M1011_PHY_STATUS_SPD_MASK;
1115 phydev->pause = phydev->asym_pause = 0;
1116
1117 switch (status) {
1118 case MII_M1011_PHY_STATUS_1000:
1119 phydev->speed = SPEED_1000;
1120 break;
1121
1122 case MII_M1011_PHY_STATUS_100:
1123 phydev->speed = SPEED_100;
1124 break;
1125
1126 default:
1127 phydev->speed = SPEED_10;
1128 break;
1129 }
1130
1131 if (!fiber) {
1132 phydev->lp_advertising = mii_stat1000_to_ethtool_lpa_t(lpagb) |
1133 mii_lpa_to_ethtool_lpa_t(lpa);
1134
1135 if (phydev->duplex == DUPLEX_FULL) {
1136 phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
1137 phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
1138 }
1139 } else {
1140 /* The fiber link is only 1000M capable */
1141 phydev->lp_advertising = fiber_lpa_to_ethtool_lpa_t(lpa);
1142
1143 if (phydev->duplex == DUPLEX_FULL) {
1144 if (!(lpa & LPA_PAUSE_FIBER)) {
1145 phydev->pause = 0;
1146 phydev->asym_pause = 0;
1147 } else if ((lpa & LPA_PAUSE_ASYM_FIBER)) {
1148 phydev->pause = 1;
1149 phydev->asym_pause = 1;
1150 } else {
1151 phydev->pause = 1;
1152 phydev->asym_pause = 0;
1153 }
1154 }
1155 }
1156 } else {
1157 int bmcr = phy_read(phydev, MII_BMCR);
1158
1159 if (bmcr < 0)
1160 return bmcr;
1161
1162 if (bmcr & BMCR_FULLDPLX)
1163 phydev->duplex = DUPLEX_FULL;
1164 else
1165 phydev->duplex = DUPLEX_HALF;
1166
1167 if (bmcr & BMCR_SPEED1000)
1168 phydev->speed = SPEED_1000;
1169 else if (bmcr & BMCR_SPEED100)
1170 phydev->speed = SPEED_100;
1171 else
1172 phydev->speed = SPEED_10;
1173
1174 phydev->pause = phydev->asym_pause = 0;
1175 phydev->lp_advertising = 0;
1176 }
1177
1178 return 0;
1179 }
1180
1181 /* marvell_read_status
1182 *
1183 * Some Marvell's phys have two modes: fiber and copper.
1184 * Both need status checked.
1185 * Description:
1186 * First, check the fiber link and status.
1187 * If the fiber link is down, check the copper link and status which
1188 * will be the default value if both link are down.
1189 */
1190 static int marvell_read_status(struct phy_device *phydev)
1191 {
1192 int err;
1193
1194 /* Check the fiber mode first */
1195 if (phydev->supported & SUPPORTED_FIBRE &&
1196 phydev->interface != PHY_INTERFACE_MODE_SGMII) {
1197 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_FIBER);
1198 if (err < 0)
1199 goto error;
1200
1201 err = marvell_read_status_page(phydev, MII_M1111_FIBER);
1202 if (err < 0)
1203 goto error;
1204
1205 /* If the fiber link is up, it is the selected and used link.
1206 * In this case, we need to stay in the fiber page.
1207 * Please to be careful about that, avoid to restore Copper page
1208 * in other functions which could break the behaviour
1209 * for some fiber phy like 88E1512.
1210 * */
1211 if (phydev->link)
1212 return 0;
1213
1214 /* If fiber link is down, check and save copper mode state */
1215 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
1216 if (err < 0)
1217 goto error;
1218 }
1219
1220 return marvell_read_status_page(phydev, MII_M1111_COPPER);
1221
1222 error:
1223 phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
1224 return err;
1225 }
1226
1227 /* marvell_suspend
1228 *
1229 * Some Marvell's phys have two modes: fiber and copper.
1230 * Both need to be suspended
1231 */
1232 static int marvell_suspend(struct phy_device *phydev)
1233 {
1234 int err;
1235
1236 /* Suspend the fiber mode first */
1237 if (!(phydev->supported & SUPPORTED_FIBRE)) {
1238 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_FIBER);
1239 if (err < 0)
1240 goto error;
1241
1242 /* With the page set, use the generic suspend */
1243 err = genphy_suspend(phydev);
1244 if (err < 0)
1245 goto error;
1246
1247 /* Then, the copper link */
1248 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
1249 if (err < 0)
1250 goto error;
1251 }
1252
1253 /* With the page set, use the generic suspend */
1254 return genphy_suspend(phydev);
1255
1256 error:
1257 phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
1258 return err;
1259 }
1260
1261 /* marvell_resume
1262 *
1263 * Some Marvell's phys have two modes: fiber and copper.
1264 * Both need to be resumed
1265 */
1266 static int marvell_resume(struct phy_device *phydev)
1267 {
1268 int err;
1269
1270 /* Resume the fiber mode first */
1271 if (!(phydev->supported & SUPPORTED_FIBRE)) {
1272 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_FIBER);
1273 if (err < 0)
1274 goto error;
1275
1276 /* With the page set, use the generic resume */
1277 err = genphy_resume(phydev);
1278 if (err < 0)
1279 goto error;
1280
1281 /* Then, the copper link */
1282 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
1283 if (err < 0)
1284 goto error;
1285 }
1286
1287 /* With the page set, use the generic resume */
1288 return genphy_resume(phydev);
1289
1290 error:
1291 phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_M1111_COPPER);
1292 return err;
1293 }
1294
1295 static int marvell_aneg_done(struct phy_device *phydev)
1296 {
1297 int retval = phy_read(phydev, MII_M1011_PHY_STATUS);
1298 return (retval < 0) ? retval : (retval & MII_M1011_PHY_STATUS_RESOLVED);
1299 }
1300
1301 static int m88e1121_did_interrupt(struct phy_device *phydev)
1302 {
1303 int imask;
1304
1305 imask = phy_read(phydev, MII_M1011_IEVENT);
1306
1307 if (imask & MII_M1011_IMASK_INIT)
1308 return 1;
1309
1310 return 0;
1311 }
1312
1313 static void m88e1318_get_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
1314 {
1315 wol->supported = WAKE_MAGIC;
1316 wol->wolopts = 0;
1317
1318 if (phy_write(phydev, MII_MARVELL_PHY_PAGE,
1319 MII_88E1318S_PHY_WOL_PAGE) < 0)
1320 return;
1321
1322 if (phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL) &
1323 MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE)
1324 wol->wolopts |= WAKE_MAGIC;
1325
1326 if (phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00) < 0)
1327 return;
1328 }
1329
1330 static int m88e1318_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
1331 {
1332 int err, oldpage, temp;
1333
1334 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
1335
1336 if (wol->wolopts & WAKE_MAGIC) {
1337 /* Explicitly switch to page 0x00, just to be sure */
1338 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00);
1339 if (err < 0)
1340 return err;
1341
1342 /* Enable the WOL interrupt */
1343 temp = phy_read(phydev, MII_88E1318S_PHY_CSIER);
1344 temp |= MII_88E1318S_PHY_CSIER_WOL_EIE;
1345 err = phy_write(phydev, MII_88E1318S_PHY_CSIER, temp);
1346 if (err < 0)
1347 return err;
1348
1349 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
1350 MII_88E1318S_PHY_LED_PAGE);
1351 if (err < 0)
1352 return err;
1353
1354 /* Setup LED[2] as interrupt pin (active low) */
1355 temp = phy_read(phydev, MII_88E1318S_PHY_LED_TCR);
1356 temp &= ~MII_88E1318S_PHY_LED_TCR_FORCE_INT;
1357 temp |= MII_88E1318S_PHY_LED_TCR_INTn_ENABLE;
1358 temp |= MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW;
1359 err = phy_write(phydev, MII_88E1318S_PHY_LED_TCR, temp);
1360 if (err < 0)
1361 return err;
1362
1363 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
1364 MII_88E1318S_PHY_WOL_PAGE);
1365 if (err < 0)
1366 return err;
1367
1368 /* Store the device address for the magic packet */
1369 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD2,
1370 ((phydev->attached_dev->dev_addr[5] << 8) |
1371 phydev->attached_dev->dev_addr[4]));
1372 if (err < 0)
1373 return err;
1374 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD1,
1375 ((phydev->attached_dev->dev_addr[3] << 8) |
1376 phydev->attached_dev->dev_addr[2]));
1377 if (err < 0)
1378 return err;
1379 err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD0,
1380 ((phydev->attached_dev->dev_addr[1] << 8) |
1381 phydev->attached_dev->dev_addr[0]));
1382 if (err < 0)
1383 return err;
1384
1385 /* Clear WOL status and enable magic packet matching */
1386 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
1387 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
1388 temp |= MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
1389 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
1390 if (err < 0)
1391 return err;
1392 } else {
1393 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
1394 MII_88E1318S_PHY_WOL_PAGE);
1395 if (err < 0)
1396 return err;
1397
1398 /* Clear WOL status and disable magic packet matching */
1399 temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL);
1400 temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS;
1401 temp &= ~MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE;
1402 err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp);
1403 if (err < 0)
1404 return err;
1405 }
1406
1407 err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
1408 if (err < 0)
1409 return err;
1410
1411 return 0;
1412 }
1413
1414 static int marvell_get_sset_count(struct phy_device *phydev)
1415 {
1416 if (phydev->supported & SUPPORTED_FIBRE)
1417 return ARRAY_SIZE(marvell_hw_stats);
1418 else
1419 return ARRAY_SIZE(marvell_hw_stats) - NB_FIBER_STATS;
1420 }
1421
1422 static void marvell_get_strings(struct phy_device *phydev, u8 *data)
1423 {
1424 int i;
1425
1426 for (i = 0; i < ARRAY_SIZE(marvell_hw_stats); i++) {
1427 memcpy(data + i * ETH_GSTRING_LEN,
1428 marvell_hw_stats[i].string, ETH_GSTRING_LEN);
1429 }
1430 }
1431
1432 #ifndef UINT64_MAX
1433 #define UINT64_MAX (u64)(~((u64)0))
1434 #endif
1435 static u64 marvell_get_stat(struct phy_device *phydev, int i)
1436 {
1437 struct marvell_hw_stat stat = marvell_hw_stats[i];
1438 struct marvell_priv *priv = phydev->priv;
1439 int err, oldpage, val;
1440 u64 ret;
1441
1442 oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE);
1443 err = phy_write(phydev, MII_MARVELL_PHY_PAGE,
1444 stat.page);
1445 if (err < 0)
1446 return UINT64_MAX;
1447
1448 val = phy_read(phydev, stat.reg);
1449 if (val < 0) {
1450 ret = UINT64_MAX;
1451 } else {
1452 val = val & ((1 << stat.bits) - 1);
1453 priv->stats[i] += val;
1454 ret = priv->stats[i];
1455 }
1456
1457 phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage);
1458
1459 return ret;
1460 }
1461
1462 static void marvell_get_stats(struct phy_device *phydev,
1463 struct ethtool_stats *stats, u64 *data)
1464 {
1465 int i;
1466
1467 for (i = 0; i < ARRAY_SIZE(marvell_hw_stats); i++)
1468 data[i] = marvell_get_stat(phydev, i);
1469 }
1470
1471 static int marvell_probe(struct phy_device *phydev)
1472 {
1473 struct marvell_priv *priv;
1474
1475 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
1476 if (!priv)
1477 return -ENOMEM;
1478
1479 phydev->priv = priv;
1480
1481 return 0;
1482 }
1483
1484 static struct phy_driver marvell_drivers[] = {
1485 {
1486 .phy_id = MARVELL_PHY_ID_88E1101,
1487 .phy_id_mask = MARVELL_PHY_ID_MASK,
1488 .name = "Marvell 88E1101",
1489 .features = PHY_GBIT_FEATURES,
1490 .probe = marvell_probe,
1491 .flags = PHY_HAS_INTERRUPT,
1492 .config_init = &marvell_config_init,
1493 .config_aneg = &marvell_config_aneg,
1494 .read_status = &genphy_read_status,
1495 .ack_interrupt = &marvell_ack_interrupt,
1496 .config_intr = &marvell_config_intr,
1497 .resume = &genphy_resume,
1498 .suspend = &genphy_suspend,
1499 .get_sset_count = marvell_get_sset_count,
1500 .get_strings = marvell_get_strings,
1501 .get_stats = marvell_get_stats,
1502 },
1503 {
1504 .phy_id = MARVELL_PHY_ID_88E1112,
1505 .phy_id_mask = MARVELL_PHY_ID_MASK,
1506 .name = "Marvell 88E1112",
1507 .features = PHY_GBIT_FEATURES,
1508 .flags = PHY_HAS_INTERRUPT,
1509 .probe = marvell_probe,
1510 .config_init = &m88e1111_config_init,
1511 .config_aneg = &marvell_config_aneg,
1512 .read_status = &genphy_read_status,
1513 .ack_interrupt = &marvell_ack_interrupt,
1514 .config_intr = &marvell_config_intr,
1515 .resume = &genphy_resume,
1516 .suspend = &genphy_suspend,
1517 .get_sset_count = marvell_get_sset_count,
1518 .get_strings = marvell_get_strings,
1519 .get_stats = marvell_get_stats,
1520 },
1521 {
1522 .phy_id = MARVELL_PHY_ID_88E1111,
1523 .phy_id_mask = MARVELL_PHY_ID_MASK,
1524 .name = "Marvell 88E1111",
1525 .features = PHY_GBIT_FEATURES,
1526 .flags = PHY_HAS_INTERRUPT,
1527 .probe = marvell_probe,
1528 .config_init = &m88e1111_config_init,
1529 .config_aneg = &m88e1111_config_aneg,
1530 .read_status = &marvell_read_status,
1531 .ack_interrupt = &marvell_ack_interrupt,
1532 .config_intr = &marvell_config_intr,
1533 .resume = &genphy_resume,
1534 .suspend = &genphy_suspend,
1535 .get_sset_count = marvell_get_sset_count,
1536 .get_strings = marvell_get_strings,
1537 .get_stats = marvell_get_stats,
1538 },
1539 {
1540 .phy_id = MARVELL_PHY_ID_88E1118,
1541 .phy_id_mask = MARVELL_PHY_ID_MASK,
1542 .name = "Marvell 88E1118",
1543 .features = PHY_GBIT_FEATURES,
1544 .flags = PHY_HAS_INTERRUPT,
1545 .probe = marvell_probe,
1546 .config_init = &m88e1118_config_init,
1547 .config_aneg = &m88e1118_config_aneg,
1548 .read_status = &genphy_read_status,
1549 .ack_interrupt = &marvell_ack_interrupt,
1550 .config_intr = &marvell_config_intr,
1551 .resume = &genphy_resume,
1552 .suspend = &genphy_suspend,
1553 .get_sset_count = marvell_get_sset_count,
1554 .get_strings = marvell_get_strings,
1555 .get_stats = marvell_get_stats,
1556 },
1557 {
1558 .phy_id = MARVELL_PHY_ID_88E1121R,
1559 .phy_id_mask = MARVELL_PHY_ID_MASK,
1560 .name = "Marvell 88E1121R",
1561 .features = PHY_GBIT_FEATURES,
1562 .flags = PHY_HAS_INTERRUPT,
1563 .probe = marvell_probe,
1564 .config_init = &m88e1121_config_init,
1565 .config_aneg = &m88e1121_config_aneg,
1566 .read_status = &marvell_read_status,
1567 .ack_interrupt = &marvell_ack_interrupt,
1568 .config_intr = &marvell_config_intr,
1569 .did_interrupt = &m88e1121_did_interrupt,
1570 .resume = &genphy_resume,
1571 .suspend = &genphy_suspend,
1572 .get_sset_count = marvell_get_sset_count,
1573 .get_strings = marvell_get_strings,
1574 .get_stats = marvell_get_stats,
1575 },
1576 {
1577 .phy_id = MARVELL_PHY_ID_88E1318S,
1578 .phy_id_mask = MARVELL_PHY_ID_MASK,
1579 .name = "Marvell 88E1318S",
1580 .features = PHY_GBIT_FEATURES,
1581 .flags = PHY_HAS_INTERRUPT,
1582 .probe = marvell_probe,
1583 .config_init = &m88e1121_config_init,
1584 .config_aneg = &m88e1318_config_aneg,
1585 .read_status = &marvell_read_status,
1586 .ack_interrupt = &marvell_ack_interrupt,
1587 .config_intr = &marvell_config_intr,
1588 .did_interrupt = &m88e1121_did_interrupt,
1589 .get_wol = &m88e1318_get_wol,
1590 .set_wol = &m88e1318_set_wol,
1591 .resume = &genphy_resume,
1592 .suspend = &genphy_suspend,
1593 .get_sset_count = marvell_get_sset_count,
1594 .get_strings = marvell_get_strings,
1595 .get_stats = marvell_get_stats,
1596 },
1597 {
1598 .phy_id = MARVELL_PHY_ID_88E1145,
1599 .phy_id_mask = MARVELL_PHY_ID_MASK,
1600 .name = "Marvell 88E1145",
1601 .features = PHY_GBIT_FEATURES,
1602 .flags = PHY_HAS_INTERRUPT,
1603 .probe = marvell_probe,
1604 .config_init = &m88e1145_config_init,
1605 .config_aneg = &marvell_config_aneg,
1606 .read_status = &genphy_read_status,
1607 .ack_interrupt = &marvell_ack_interrupt,
1608 .config_intr = &marvell_config_intr,
1609 .resume = &genphy_resume,
1610 .suspend = &genphy_suspend,
1611 .get_sset_count = marvell_get_sset_count,
1612 .get_strings = marvell_get_strings,
1613 .get_stats = marvell_get_stats,
1614 },
1615 {
1616 .phy_id = MARVELL_PHY_ID_88E1149R,
1617 .phy_id_mask = MARVELL_PHY_ID_MASK,
1618 .name = "Marvell 88E1149R",
1619 .features = PHY_GBIT_FEATURES,
1620 .flags = PHY_HAS_INTERRUPT,
1621 .probe = marvell_probe,
1622 .config_init = &m88e1149_config_init,
1623 .config_aneg = &m88e1118_config_aneg,
1624 .read_status = &genphy_read_status,
1625 .ack_interrupt = &marvell_ack_interrupt,
1626 .config_intr = &marvell_config_intr,
1627 .resume = &genphy_resume,
1628 .suspend = &genphy_suspend,
1629 .get_sset_count = marvell_get_sset_count,
1630 .get_strings = marvell_get_strings,
1631 .get_stats = marvell_get_stats,
1632 },
1633 {
1634 .phy_id = MARVELL_PHY_ID_88E1240,
1635 .phy_id_mask = MARVELL_PHY_ID_MASK,
1636 .name = "Marvell 88E1240",
1637 .features = PHY_GBIT_FEATURES,
1638 .flags = PHY_HAS_INTERRUPT,
1639 .probe = marvell_probe,
1640 .config_init = &m88e1111_config_init,
1641 .config_aneg = &marvell_config_aneg,
1642 .read_status = &genphy_read_status,
1643 .ack_interrupt = &marvell_ack_interrupt,
1644 .config_intr = &marvell_config_intr,
1645 .resume = &genphy_resume,
1646 .suspend = &genphy_suspend,
1647 .get_sset_count = marvell_get_sset_count,
1648 .get_strings = marvell_get_strings,
1649 .get_stats = marvell_get_stats,
1650 },
1651 {
1652 .phy_id = MARVELL_PHY_ID_88E1116R,
1653 .phy_id_mask = MARVELL_PHY_ID_MASK,
1654 .name = "Marvell 88E1116R",
1655 .features = PHY_GBIT_FEATURES,
1656 .flags = PHY_HAS_INTERRUPT,
1657 .probe = marvell_probe,
1658 .config_init = &m88e1116r_config_init,
1659 .config_aneg = &genphy_config_aneg,
1660 .read_status = &genphy_read_status,
1661 .ack_interrupt = &marvell_ack_interrupt,
1662 .config_intr = &marvell_config_intr,
1663 .resume = &genphy_resume,
1664 .suspend = &genphy_suspend,
1665 .get_sset_count = marvell_get_sset_count,
1666 .get_strings = marvell_get_strings,
1667 .get_stats = marvell_get_stats,
1668 },
1669 {
1670 .phy_id = MARVELL_PHY_ID_88E1510,
1671 .phy_id_mask = MARVELL_PHY_ID_MASK,
1672 .name = "Marvell 88E1510",
1673 .features = PHY_GBIT_FEATURES | SUPPORTED_FIBRE,
1674 .flags = PHY_HAS_INTERRUPT,
1675 .probe = marvell_probe,
1676 .config_init = &m88e1510_config_init,
1677 .config_aneg = &m88e1510_config_aneg,
1678 .read_status = &marvell_read_status,
1679 .ack_interrupt = &marvell_ack_interrupt,
1680 .config_intr = &marvell_config_intr,
1681 .did_interrupt = &m88e1121_did_interrupt,
1682 .get_wol = &m88e1318_get_wol,
1683 .set_wol = &m88e1318_set_wol,
1684 .resume = &marvell_resume,
1685 .suspend = &marvell_suspend,
1686 .get_sset_count = marvell_get_sset_count,
1687 .get_strings = marvell_get_strings,
1688 .get_stats = marvell_get_stats,
1689 },
1690 {
1691 .phy_id = MARVELL_PHY_ID_88E1540,
1692 .phy_id_mask = MARVELL_PHY_ID_MASK,
1693 .name = "Marvell 88E1540",
1694 .features = PHY_GBIT_FEATURES,
1695 .flags = PHY_HAS_INTERRUPT,
1696 .probe = marvell_probe,
1697 .config_init = &marvell_config_init,
1698 .config_aneg = &m88e1510_config_aneg,
1699 .read_status = &marvell_read_status,
1700 .ack_interrupt = &marvell_ack_interrupt,
1701 .config_intr = &marvell_config_intr,
1702 .did_interrupt = &m88e1121_did_interrupt,
1703 .resume = &genphy_resume,
1704 .suspend = &genphy_suspend,
1705 .get_sset_count = marvell_get_sset_count,
1706 .get_strings = marvell_get_strings,
1707 .get_stats = marvell_get_stats,
1708 },
1709 {
1710 .phy_id = MARVELL_PHY_ID_88E3016,
1711 .phy_id_mask = MARVELL_PHY_ID_MASK,
1712 .name = "Marvell 88E3016",
1713 .features = PHY_BASIC_FEATURES,
1714 .flags = PHY_HAS_INTERRUPT,
1715 .probe = marvell_probe,
1716 .config_aneg = &genphy_config_aneg,
1717 .config_init = &m88e3016_config_init,
1718 .aneg_done = &marvell_aneg_done,
1719 .read_status = &marvell_read_status,
1720 .ack_interrupt = &marvell_ack_interrupt,
1721 .config_intr = &marvell_config_intr,
1722 .did_interrupt = &m88e1121_did_interrupt,
1723 .resume = &genphy_resume,
1724 .suspend = &genphy_suspend,
1725 .get_sset_count = marvell_get_sset_count,
1726 .get_strings = marvell_get_strings,
1727 .get_stats = marvell_get_stats,
1728 },
1729 };
1730
1731 module_phy_driver(marvell_drivers);
1732
1733 static struct mdio_device_id __maybe_unused marvell_tbl[] = {
1734 { MARVELL_PHY_ID_88E1101, MARVELL_PHY_ID_MASK },
1735 { MARVELL_PHY_ID_88E1112, MARVELL_PHY_ID_MASK },
1736 { MARVELL_PHY_ID_88E1111, MARVELL_PHY_ID_MASK },
1737 { MARVELL_PHY_ID_88E1118, MARVELL_PHY_ID_MASK },
1738 { MARVELL_PHY_ID_88E1121R, MARVELL_PHY_ID_MASK },
1739 { MARVELL_PHY_ID_88E1145, MARVELL_PHY_ID_MASK },
1740 { MARVELL_PHY_ID_88E1149R, MARVELL_PHY_ID_MASK },
1741 { MARVELL_PHY_ID_88E1240, MARVELL_PHY_ID_MASK },
1742 { MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK },
1743 { MARVELL_PHY_ID_88E1116R, MARVELL_PHY_ID_MASK },
1744 { MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK },
1745 { MARVELL_PHY_ID_88E1540, MARVELL_PHY_ID_MASK },
1746 { MARVELL_PHY_ID_88E3016, MARVELL_PHY_ID_MASK },
1747 { }
1748 };
1749
1750 MODULE_DEVICE_TABLE(mdio, marvell_tbl);
ubuntu-zesty-kernel mirror