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1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2005-2008 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11 #include <linux/module.h>
12 #include <linux/pci.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/delay.h>
16 #include <linux/notifier.h>
17 #include <linux/ip.h>
18 #include <linux/tcp.h>
19 #include <linux/in.h>
20 #include <linux/crc32.h>
21 #include <linux/ethtool.h>
22 #include <linux/topology.h>
23 #include "net_driver.h"
24 #include "ethtool.h"
25 #include "tx.h"
26 #include "rx.h"
27 #include "efx.h"
28 #include "mdio_10g.h"
29 #include "falcon.h"
30
31 #define EFX_MAX_MTU (9 * 1024)
32
33 /* RX slow fill workqueue. If memory allocation fails in the fast path,
34 * a work item is pushed onto this work queue to retry the allocation later,
35 * to avoid the NIC being starved of RX buffers. Since this is a per cpu
36 * workqueue, there is nothing to be gained in making it per NIC
37 */
38 static struct workqueue_struct *refill_workqueue;
39
40 /* Reset workqueue. If any NIC has a hardware failure then a reset will be
41 * queued onto this work queue. This is not a per-nic work queue, because
42 * efx_reset_work() acquires the rtnl lock, so resets are naturally serialised.
43 */
44 static struct workqueue_struct *reset_workqueue;
45
46 /**************************************************************************
47 *
48 * Configurable values
49 *
50 *************************************************************************/
51
52 /*
53 * Enable large receive offload (LRO) aka soft segment reassembly (SSR)
54 *
55 * This sets the default for new devices. It can be controlled later
56 * using ethtool.
57 */
58 static int lro = true;
59 module_param(lro, int, 0644);
60 MODULE_PARM_DESC(lro, "Large receive offload acceleration");
61
62 /*
63 * Use separate channels for TX and RX events
64 *
65 * Set this to 1 to use separate channels for TX and RX. It allows us
66 * to control interrupt affinity separately for TX and RX.
67 *
68 * This is only used in MSI-X interrupt mode
69 */
70 static unsigned int separate_tx_channels;
71 module_param(separate_tx_channels, uint, 0644);
72 MODULE_PARM_DESC(separate_tx_channels,
73 "Use separate channels for TX and RX");
74
75 /* This is the weight assigned to each of the (per-channel) virtual
76 * NAPI devices.
77 */
78 static int napi_weight = 64;
79
80 /* This is the time (in jiffies) between invocations of the hardware
81 * monitor, which checks for known hardware bugs and resets the
82 * hardware and driver as necessary.
83 */
84 unsigned int efx_monitor_interval = 1 * HZ;
85
86 /* This controls whether or not the driver will initialise devices
87 * with invalid MAC addresses stored in the EEPROM or flash. If true,
88 * such devices will be initialised with a random locally-generated
89 * MAC address. This allows for loading the sfc_mtd driver to
90 * reprogram the flash, even if the flash contents (including the MAC
91 * address) have previously been erased.
92 */
93 static unsigned int allow_bad_hwaddr;
94
95 /* Initial interrupt moderation settings. They can be modified after
96 * module load with ethtool.
97 *
98 * The default for RX should strike a balance between increasing the
99 * round-trip latency and reducing overhead.
100 */
101 static unsigned int rx_irq_mod_usec = 60;
102
103 /* Initial interrupt moderation settings. They can be modified after
104 * module load with ethtool.
105 *
106 * This default is chosen to ensure that a 10G link does not go idle
107 * while a TX queue is stopped after it has become full. A queue is
108 * restarted when it drops below half full. The time this takes (assuming
109 * worst case 3 descriptors per packet and 1024 descriptors) is
110 * 512 / 3 * 1.2 = 205 usec.
111 */
112 static unsigned int tx_irq_mod_usec = 150;
113
114 /* This is the first interrupt mode to try out of:
115 * 0 => MSI-X
116 * 1 => MSI
117 * 2 => legacy
118 */
119 static unsigned int interrupt_mode;
120
121 /* This is the requested number of CPUs to use for Receive-Side Scaling (RSS),
122 * i.e. the number of CPUs among which we may distribute simultaneous
123 * interrupt handling.
124 *
125 * Cards without MSI-X will only target one CPU via legacy or MSI interrupt.
126 * The default (0) means to assign an interrupt to each package (level II cache)
127 */
128 static unsigned int rss_cpus;
129 module_param(rss_cpus, uint, 0444);
130 MODULE_PARM_DESC(rss_cpus, "Number of CPUs to use for Receive-Side Scaling");
131
132 static int phy_flash_cfg;
133 module_param(phy_flash_cfg, int, 0644);
134 MODULE_PARM_DESC(phy_flash_cfg, "Set PHYs into reflash mode initially");
135
136 static unsigned irq_adapt_low_thresh = 10000;
137 module_param(irq_adapt_low_thresh, uint, 0644);
138 MODULE_PARM_DESC(irq_adapt_low_thresh,
139 "Threshold score for reducing IRQ moderation");
140
141 static unsigned irq_adapt_high_thresh = 20000;
142 module_param(irq_adapt_high_thresh, uint, 0644);
143 MODULE_PARM_DESC(irq_adapt_high_thresh,
144 "Threshold score for increasing IRQ moderation");
145
146 /**************************************************************************
147 *
148 * Utility functions and prototypes
149 *
150 *************************************************************************/
151 static void efx_remove_channel(struct efx_channel *channel);
152 static void efx_remove_port(struct efx_nic *efx);
153 static void efx_fini_napi(struct efx_nic *efx);
154 static void efx_fini_channels(struct efx_nic *efx);
155
156 #define EFX_ASSERT_RESET_SERIALISED(efx) \
157 do { \
158 if (efx->state == STATE_RUNNING) \
159 ASSERT_RTNL(); \
160 } while (0)
161
162 /**************************************************************************
163 *
164 * Event queue processing
165 *
166 *************************************************************************/
167
168 /* Process channel's event queue
169 *
170 * This function is responsible for processing the event queue of a
171 * single channel. The caller must guarantee that this function will
172 * never be concurrently called more than once on the same channel,
173 * though different channels may be being processed concurrently.
174 */
175 static int efx_process_channel(struct efx_channel *channel, int rx_quota)
176 {
177 struct efx_nic *efx = channel->efx;
178 int rx_packets;
179
180 if (unlikely(efx->reset_pending != RESET_TYPE_NONE ||
181 !channel->enabled))
182 return 0;
183
184 rx_packets = falcon_process_eventq(channel, rx_quota);
185 if (rx_packets == 0)
186 return 0;
187
188 /* Deliver last RX packet. */
189 if (channel->rx_pkt) {
190 __efx_rx_packet(channel, channel->rx_pkt,
191 channel->rx_pkt_csummed);
192 channel->rx_pkt = NULL;
193 }
194
195 efx_rx_strategy(channel);
196
197 efx_fast_push_rx_descriptors(&efx->rx_queue[channel->channel]);
198
199 return rx_packets;
200 }
201
202 /* Mark channel as finished processing
203 *
204 * Note that since we will not receive further interrupts for this
205 * channel before we finish processing and call the eventq_read_ack()
206 * method, there is no need to use the interrupt hold-off timers.
207 */
208 static inline void efx_channel_processed(struct efx_channel *channel)
209 {
210 /* The interrupt handler for this channel may set work_pending
211 * as soon as we acknowledge the events we've seen. Make sure
212 * it's cleared before then. */
213 channel->work_pending = false;
214 smp_wmb();
215
216 falcon_eventq_read_ack(channel);
217 }
218
219 /* NAPI poll handler
220 *
221 * NAPI guarantees serialisation of polls of the same device, which
222 * provides the guarantee required by efx_process_channel().
223 */
224 static int efx_poll(struct napi_struct *napi, int budget)
225 {
226 struct efx_channel *channel =
227 container_of(napi, struct efx_channel, napi_str);
228 int rx_packets;
229
230 EFX_TRACE(channel->efx, "channel %d NAPI poll executing on CPU %d\n",
231 channel->channel, raw_smp_processor_id());
232
233 rx_packets = efx_process_channel(channel, budget);
234
235 if (rx_packets < budget) {
236 struct efx_nic *efx = channel->efx;
237
238 if (channel->used_flags & EFX_USED_BY_RX &&
239 efx->irq_rx_adaptive &&
240 unlikely(++channel->irq_count == 1000)) {
241 unsigned old_irq_moderation = channel->irq_moderation;
242
243 if (unlikely(channel->irq_mod_score <
244 irq_adapt_low_thresh)) {
245 channel->irq_moderation =
246 max_t(int,
247 channel->irq_moderation -
248 FALCON_IRQ_MOD_RESOLUTION,
249 FALCON_IRQ_MOD_RESOLUTION);
250 } else if (unlikely(channel->irq_mod_score >
251 irq_adapt_high_thresh)) {
252 channel->irq_moderation =
253 min(channel->irq_moderation +
254 FALCON_IRQ_MOD_RESOLUTION,
255 efx->irq_rx_moderation);
256 }
257
258 if (channel->irq_moderation != old_irq_moderation)
259 falcon_set_int_moderation(channel);
260
261 channel->irq_count = 0;
262 channel->irq_mod_score = 0;
263 }
264
265 /* There is no race here; although napi_disable() will
266 * only wait for napi_complete(), this isn't a problem
267 * since efx_channel_processed() will have no effect if
268 * interrupts have already been disabled.
269 */
270 napi_complete(napi);
271 efx_channel_processed(channel);
272 }
273
274 return rx_packets;
275 }
276
277 /* Process the eventq of the specified channel immediately on this CPU
278 *
279 * Disable hardware generated interrupts, wait for any existing
280 * processing to finish, then directly poll (and ack ) the eventq.
281 * Finally reenable NAPI and interrupts.
282 *
283 * Since we are touching interrupts the caller should hold the suspend lock
284 */
285 void efx_process_channel_now(struct efx_channel *channel)
286 {
287 struct efx_nic *efx = channel->efx;
288
289 BUG_ON(!channel->used_flags);
290 BUG_ON(!channel->enabled);
291
292 /* Disable interrupts and wait for ISRs to complete */
293 falcon_disable_interrupts(efx);
294 if (efx->legacy_irq)
295 synchronize_irq(efx->legacy_irq);
296 if (channel->irq)
297 synchronize_irq(channel->irq);
298
299 /* Wait for any NAPI processing to complete */
300 napi_disable(&channel->napi_str);
301
302 /* Poll the channel */
303 efx_process_channel(channel, efx->type->evq_size);
304
305 /* Ack the eventq. This may cause an interrupt to be generated
306 * when they are reenabled */
307 efx_channel_processed(channel);
308
309 napi_enable(&channel->napi_str);
310 falcon_enable_interrupts(efx);
311 }
312
313 /* Create event queue
314 * Event queue memory allocations are done only once. If the channel
315 * is reset, the memory buffer will be reused; this guards against
316 * errors during channel reset and also simplifies interrupt handling.
317 */
318 static int efx_probe_eventq(struct efx_channel *channel)
319 {
320 EFX_LOG(channel->efx, "chan %d create event queue\n", channel->channel);
321
322 return falcon_probe_eventq(channel);
323 }
324
325 /* Prepare channel's event queue */
326 static void efx_init_eventq(struct efx_channel *channel)
327 {
328 EFX_LOG(channel->efx, "chan %d init event queue\n", channel->channel);
329
330 channel->eventq_read_ptr = 0;
331
332 falcon_init_eventq(channel);
333 }
334
335 static void efx_fini_eventq(struct efx_channel *channel)
336 {
337 EFX_LOG(channel->efx, "chan %d fini event queue\n", channel->channel);
338
339 falcon_fini_eventq(channel);
340 }
341
342 static void efx_remove_eventq(struct efx_channel *channel)
343 {
344 EFX_LOG(channel->efx, "chan %d remove event queue\n", channel->channel);
345
346 falcon_remove_eventq(channel);
347 }
348
349 /**************************************************************************
350 *
351 * Channel handling
352 *
353 *************************************************************************/
354
355 static int efx_probe_channel(struct efx_channel *channel)
356 {
357 struct efx_tx_queue *tx_queue;
358 struct efx_rx_queue *rx_queue;
359 int rc;
360
361 EFX_LOG(channel->efx, "creating channel %d\n", channel->channel);
362
363 rc = efx_probe_eventq(channel);
364 if (rc)
365 goto fail1;
366
367 efx_for_each_channel_tx_queue(tx_queue, channel) {
368 rc = efx_probe_tx_queue(tx_queue);
369 if (rc)
370 goto fail2;
371 }
372
373 efx_for_each_channel_rx_queue(rx_queue, channel) {
374 rc = efx_probe_rx_queue(rx_queue);
375 if (rc)
376 goto fail3;
377 }
378
379 channel->n_rx_frm_trunc = 0;
380
381 return 0;
382
383 fail3:
384 efx_for_each_channel_rx_queue(rx_queue, channel)
385 efx_remove_rx_queue(rx_queue);
386 fail2:
387 efx_for_each_channel_tx_queue(tx_queue, channel)
388 efx_remove_tx_queue(tx_queue);
389 fail1:
390 return rc;
391 }
392
393
394 static void efx_set_channel_names(struct efx_nic *efx)
395 {
396 struct efx_channel *channel;
397 const char *type = "";
398 int number;
399
400 efx_for_each_channel(channel, efx) {
401 number = channel->channel;
402 if (efx->n_channels > efx->n_rx_queues) {
403 if (channel->channel < efx->n_rx_queues) {
404 type = "-rx";
405 } else {
406 type = "-tx";
407 number -= efx->n_rx_queues;
408 }
409 }
410 snprintf(channel->name, sizeof(channel->name),
411 "%s%s-%d", efx->name, type, number);
412 }
413 }
414
415 /* Channels are shutdown and reinitialised whilst the NIC is running
416 * to propagate configuration changes (mtu, checksum offload), or
417 * to clear hardware error conditions
418 */
419 static void efx_init_channels(struct efx_nic *efx)
420 {
421 struct efx_tx_queue *tx_queue;
422 struct efx_rx_queue *rx_queue;
423 struct efx_channel *channel;
424
425 /* Calculate the rx buffer allocation parameters required to
426 * support the current MTU, including padding for header
427 * alignment and overruns.
428 */
429 efx->rx_buffer_len = (max(EFX_PAGE_IP_ALIGN, NET_IP_ALIGN) +
430 EFX_MAX_FRAME_LEN(efx->net_dev->mtu) +
431 efx->type->rx_buffer_padding);
432 efx->rx_buffer_order = get_order(efx->rx_buffer_len);
433
434 /* Initialise the channels */
435 efx_for_each_channel(channel, efx) {
436 EFX_LOG(channel->efx, "init chan %d\n", channel->channel);
437
438 efx_init_eventq(channel);
439
440 efx_for_each_channel_tx_queue(tx_queue, channel)
441 efx_init_tx_queue(tx_queue);
442
443 /* The rx buffer allocation strategy is MTU dependent */
444 efx_rx_strategy(channel);
445
446 efx_for_each_channel_rx_queue(rx_queue, channel)
447 efx_init_rx_queue(rx_queue);
448
449 WARN_ON(channel->rx_pkt != NULL);
450 efx_rx_strategy(channel);
451 }
452 }
453
454 /* This enables event queue processing and packet transmission.
455 *
456 * Note that this function is not allowed to fail, since that would
457 * introduce too much complexity into the suspend/resume path.
458 */
459 static void efx_start_channel(struct efx_channel *channel)
460 {
461 struct efx_rx_queue *rx_queue;
462
463 EFX_LOG(channel->efx, "starting chan %d\n", channel->channel);
464
465 if (!(channel->efx->net_dev->flags & IFF_UP))
466 netif_napi_add(channel->napi_dev, &channel->napi_str,
467 efx_poll, napi_weight);
468
469 /* The interrupt handler for this channel may set work_pending
470 * as soon as we enable it. Make sure it's cleared before
471 * then. Similarly, make sure it sees the enabled flag set. */
472 channel->work_pending = false;
473 channel->enabled = true;
474 smp_wmb();
475
476 napi_enable(&channel->napi_str);
477
478 /* Load up RX descriptors */
479 efx_for_each_channel_rx_queue(rx_queue, channel)
480 efx_fast_push_rx_descriptors(rx_queue);
481 }
482
483 /* This disables event queue processing and packet transmission.
484 * This function does not guarantee that all queue processing
485 * (e.g. RX refill) is complete.
486 */
487 static void efx_stop_channel(struct efx_channel *channel)
488 {
489 struct efx_rx_queue *rx_queue;
490
491 if (!channel->enabled)
492 return;
493
494 EFX_LOG(channel->efx, "stop chan %d\n", channel->channel);
495
496 channel->enabled = false;
497 napi_disable(&channel->napi_str);
498
499 /* Ensure that any worker threads have exited or will be no-ops */
500 efx_for_each_channel_rx_queue(rx_queue, channel) {
501 spin_lock_bh(&rx_queue->add_lock);
502 spin_unlock_bh(&rx_queue->add_lock);
503 }
504 }
505
506 static void efx_fini_channels(struct efx_nic *efx)
507 {
508 struct efx_channel *channel;
509 struct efx_tx_queue *tx_queue;
510 struct efx_rx_queue *rx_queue;
511 int rc;
512
513 EFX_ASSERT_RESET_SERIALISED(efx);
514 BUG_ON(efx->port_enabled);
515
516 rc = falcon_flush_queues(efx);
517 if (rc)
518 EFX_ERR(efx, "failed to flush queues\n");
519 else
520 EFX_LOG(efx, "successfully flushed all queues\n");
521
522 efx_for_each_channel(channel, efx) {
523 EFX_LOG(channel->efx, "shut down chan %d\n", channel->channel);
524
525 efx_for_each_channel_rx_queue(rx_queue, channel)
526 efx_fini_rx_queue(rx_queue);
527 efx_for_each_channel_tx_queue(tx_queue, channel)
528 efx_fini_tx_queue(tx_queue);
529 efx_fini_eventq(channel);
530 }
531 }
532
533 static void efx_remove_channel(struct efx_channel *channel)
534 {
535 struct efx_tx_queue *tx_queue;
536 struct efx_rx_queue *rx_queue;
537
538 EFX_LOG(channel->efx, "destroy chan %d\n", channel->channel);
539
540 efx_for_each_channel_rx_queue(rx_queue, channel)
541 efx_remove_rx_queue(rx_queue);
542 efx_for_each_channel_tx_queue(tx_queue, channel)
543 efx_remove_tx_queue(tx_queue);
544 efx_remove_eventq(channel);
545
546 channel->used_flags = 0;
547 }
548
549 void efx_schedule_slow_fill(struct efx_rx_queue *rx_queue, int delay)
550 {
551 queue_delayed_work(refill_workqueue, &rx_queue->work, delay);
552 }
553
554 /**************************************************************************
555 *
556 * Port handling
557 *
558 **************************************************************************/
559
560 /* This ensures that the kernel is kept informed (via
561 * netif_carrier_on/off) of the link status, and also maintains the
562 * link status's stop on the port's TX queue.
563 */
564 static void efx_link_status_changed(struct efx_nic *efx)
565 {
566 /* SFC Bug 5356: A net_dev notifier is registered, so we must ensure
567 * that no events are triggered between unregister_netdev() and the
568 * driver unloading. A more general condition is that NETDEV_CHANGE
569 * can only be generated between NETDEV_UP and NETDEV_DOWN */
570 if (!netif_running(efx->net_dev))
571 return;
572
573 if (efx->port_inhibited) {
574 netif_carrier_off(efx->net_dev);
575 return;
576 }
577
578 if (efx->link_up != netif_carrier_ok(efx->net_dev)) {
579 efx->n_link_state_changes++;
580
581 if (efx->link_up)
582 netif_carrier_on(efx->net_dev);
583 else
584 netif_carrier_off(efx->net_dev);
585 }
586
587 /* Status message for kernel log */
588 if (efx->link_up) {
589 EFX_INFO(efx, "link up at %uMbps %s-duplex (MTU %d)%s\n",
590 efx->link_speed, efx->link_fd ? "full" : "half",
591 efx->net_dev->mtu,
592 (efx->promiscuous ? " [PROMISC]" : ""));
593 } else {
594 EFX_INFO(efx, "link down\n");
595 }
596
597 }
598
599 static void efx_fini_port(struct efx_nic *efx);
600
601 /* This call reinitialises the MAC to pick up new PHY settings. The
602 * caller must hold the mac_lock */
603 void __efx_reconfigure_port(struct efx_nic *efx)
604 {
605 WARN_ON(!mutex_is_locked(&efx->mac_lock));
606
607 EFX_LOG(efx, "reconfiguring MAC from PHY settings on CPU %d\n",
608 raw_smp_processor_id());
609
610 /* Serialise the promiscuous flag with efx_set_multicast_list. */
611 if (efx_dev_registered(efx)) {
612 netif_addr_lock_bh(efx->net_dev);
613 netif_addr_unlock_bh(efx->net_dev);
614 }
615
616 falcon_deconfigure_mac_wrapper(efx);
617
618 /* Reconfigure the PHY, disabling transmit in mac level loopback. */
619 if (LOOPBACK_INTERNAL(efx))
620 efx->phy_mode |= PHY_MODE_TX_DISABLED;
621 else
622 efx->phy_mode &= ~PHY_MODE_TX_DISABLED;
623 efx->phy_op->reconfigure(efx);
624
625 if (falcon_switch_mac(efx))
626 goto fail;
627
628 efx->mac_op->reconfigure(efx);
629
630 /* Inform kernel of loss/gain of carrier */
631 efx_link_status_changed(efx);
632 return;
633
634 fail:
635 EFX_ERR(efx, "failed to reconfigure MAC\n");
636 efx->port_enabled = false;
637 efx_fini_port(efx);
638 }
639
640 /* Reinitialise the MAC to pick up new PHY settings, even if the port is
641 * disabled. */
642 void efx_reconfigure_port(struct efx_nic *efx)
643 {
644 EFX_ASSERT_RESET_SERIALISED(efx);
645
646 mutex_lock(&efx->mac_lock);
647 __efx_reconfigure_port(efx);
648 mutex_unlock(&efx->mac_lock);
649 }
650
651 /* Asynchronous efx_reconfigure_port work item. To speed up efx_flush_all()
652 * we don't efx_reconfigure_port() if the port is disabled. Care is taken
653 * in efx_stop_all() and efx_start_port() to prevent PHY events being lost */
654 static void efx_phy_work(struct work_struct *data)
655 {
656 struct efx_nic *efx = container_of(data, struct efx_nic, phy_work);
657
658 mutex_lock(&efx->mac_lock);
659 if (efx->port_enabled)
660 __efx_reconfigure_port(efx);
661 mutex_unlock(&efx->mac_lock);
662 }
663
664 static void efx_mac_work(struct work_struct *data)
665 {
666 struct efx_nic *efx = container_of(data, struct efx_nic, mac_work);
667
668 mutex_lock(&efx->mac_lock);
669 if (efx->port_enabled)
670 efx->mac_op->irq(efx);
671 mutex_unlock(&efx->mac_lock);
672 }
673
674 static int efx_probe_port(struct efx_nic *efx)
675 {
676 int rc;
677
678 EFX_LOG(efx, "create port\n");
679
680 /* Connect up MAC/PHY operations table and read MAC address */
681 rc = falcon_probe_port(efx);
682 if (rc)
683 goto err;
684
685 if (phy_flash_cfg)
686 efx->phy_mode = PHY_MODE_SPECIAL;
687
688 /* Sanity check MAC address */
689 if (is_valid_ether_addr(efx->mac_address)) {
690 memcpy(efx->net_dev->dev_addr, efx->mac_address, ETH_ALEN);
691 } else {
692 EFX_ERR(efx, "invalid MAC address %pM\n",
693 efx->mac_address);
694 if (!allow_bad_hwaddr) {
695 rc = -EINVAL;
696 goto err;
697 }
698 random_ether_addr(efx->net_dev->dev_addr);
699 EFX_INFO(efx, "using locally-generated MAC %pM\n",
700 efx->net_dev->dev_addr);
701 }
702
703 return 0;
704
705 err:
706 efx_remove_port(efx);
707 return rc;
708 }
709
710 static int efx_init_port(struct efx_nic *efx)
711 {
712 int rc;
713
714 EFX_LOG(efx, "init port\n");
715
716 rc = efx->phy_op->init(efx);
717 if (rc)
718 return rc;
719 mutex_lock(&efx->mac_lock);
720 efx->phy_op->reconfigure(efx);
721 rc = falcon_switch_mac(efx);
722 mutex_unlock(&efx->mac_lock);
723 if (rc)
724 goto fail;
725 efx->mac_op->reconfigure(efx);
726
727 efx->port_initialized = true;
728 efx_stats_enable(efx);
729 return 0;
730
731 fail:
732 efx->phy_op->fini(efx);
733 return rc;
734 }
735
736 /* Allow efx_reconfigure_port() to be scheduled, and close the window
737 * between efx_stop_port and efx_flush_all whereby a previously scheduled
738 * efx_phy_work()/efx_mac_work() may have been cancelled */
739 static void efx_start_port(struct efx_nic *efx)
740 {
741 EFX_LOG(efx, "start port\n");
742 BUG_ON(efx->port_enabled);
743
744 mutex_lock(&efx->mac_lock);
745 efx->port_enabled = true;
746 __efx_reconfigure_port(efx);
747 efx->mac_op->irq(efx);
748 mutex_unlock(&efx->mac_lock);
749 }
750
751 /* Prevent efx_phy_work, efx_mac_work, and efx_monitor() from executing,
752 * and efx_set_multicast_list() from scheduling efx_phy_work. efx_phy_work
753 * and efx_mac_work may still be scheduled via NAPI processing until
754 * efx_flush_all() is called */
755 static void efx_stop_port(struct efx_nic *efx)
756 {
757 EFX_LOG(efx, "stop port\n");
758
759 mutex_lock(&efx->mac_lock);
760 efx->port_enabled = false;
761 mutex_unlock(&efx->mac_lock);
762
763 /* Serialise against efx_set_multicast_list() */
764 if (efx_dev_registered(efx)) {
765 netif_addr_lock_bh(efx->net_dev);
766 netif_addr_unlock_bh(efx->net_dev);
767 }
768 }
769
770 static void efx_fini_port(struct efx_nic *efx)
771 {
772 EFX_LOG(efx, "shut down port\n");
773
774 if (!efx->port_initialized)
775 return;
776
777 efx_stats_disable(efx);
778 efx->phy_op->fini(efx);
779 efx->port_initialized = false;
780
781 efx->link_up = false;
782 efx_link_status_changed(efx);
783 }
784
785 static void efx_remove_port(struct efx_nic *efx)
786 {
787 EFX_LOG(efx, "destroying port\n");
788
789 falcon_remove_port(efx);
790 }
791
792 /**************************************************************************
793 *
794 * NIC handling
795 *
796 **************************************************************************/
797
798 /* This configures the PCI device to enable I/O and DMA. */
799 static int efx_init_io(struct efx_nic *efx)
800 {
801 struct pci_dev *pci_dev = efx->pci_dev;
802 dma_addr_t dma_mask = efx->type->max_dma_mask;
803 int rc;
804
805 EFX_LOG(efx, "initialising I/O\n");
806
807 rc = pci_enable_device(pci_dev);
808 if (rc) {
809 EFX_ERR(efx, "failed to enable PCI device\n");
810 goto fail1;
811 }
812
813 pci_set_master(pci_dev);
814
815 /* Set the PCI DMA mask. Try all possibilities from our
816 * genuine mask down to 32 bits, because some architectures
817 * (e.g. x86_64 with iommu_sac_force set) will allow 40 bit
818 * masks event though they reject 46 bit masks.
819 */
820 while (dma_mask > 0x7fffffffUL) {
821 if (pci_dma_supported(pci_dev, dma_mask) &&
822 ((rc = pci_set_dma_mask(pci_dev, dma_mask)) == 0))
823 break;
824 dma_mask >>= 1;
825 }
826 if (rc) {
827 EFX_ERR(efx, "could not find a suitable DMA mask\n");
828 goto fail2;
829 }
830 EFX_LOG(efx, "using DMA mask %llx\n", (unsigned long long) dma_mask);
831 rc = pci_set_consistent_dma_mask(pci_dev, dma_mask);
832 if (rc) {
833 /* pci_set_consistent_dma_mask() is not *allowed* to
834 * fail with a mask that pci_set_dma_mask() accepted,
835 * but just in case...
836 */
837 EFX_ERR(efx, "failed to set consistent DMA mask\n");
838 goto fail2;
839 }
840
841 efx->membase_phys = pci_resource_start(efx->pci_dev,
842 efx->type->mem_bar);
843 rc = pci_request_region(pci_dev, efx->type->mem_bar, "sfc");
844 if (rc) {
845 EFX_ERR(efx, "request for memory BAR failed\n");
846 rc = -EIO;
847 goto fail3;
848 }
849 efx->membase = ioremap_nocache(efx->membase_phys,
850 efx->type->mem_map_size);
851 if (!efx->membase) {
852 EFX_ERR(efx, "could not map memory BAR %d at %llx+%x\n",
853 efx->type->mem_bar,
854 (unsigned long long)efx->membase_phys,
855 efx->type->mem_map_size);
856 rc = -ENOMEM;
857 goto fail4;
858 }
859 EFX_LOG(efx, "memory BAR %u at %llx+%x (virtual %p)\n",
860 efx->type->mem_bar, (unsigned long long)efx->membase_phys,
861 efx->type->mem_map_size, efx->membase);
862
863 return 0;
864
865 fail4:
866 pci_release_region(efx->pci_dev, efx->type->mem_bar);
867 fail3:
868 efx->membase_phys = 0;
869 fail2:
870 pci_disable_device(efx->pci_dev);
871 fail1:
872 return rc;
873 }
874
875 static void efx_fini_io(struct efx_nic *efx)
876 {
877 EFX_LOG(efx, "shutting down I/O\n");
878
879 if (efx->membase) {
880 iounmap(efx->membase);
881 efx->membase = NULL;
882 }
883
884 if (efx->membase_phys) {
885 pci_release_region(efx->pci_dev, efx->type->mem_bar);
886 efx->membase_phys = 0;
887 }
888
889 pci_disable_device(efx->pci_dev);
890 }
891
892 /* Get number of RX queues wanted. Return number of online CPU
893 * packages in the expectation that an IRQ balancer will spread
894 * interrupts across them. */
895 static int efx_wanted_rx_queues(void)
896 {
897 cpumask_t core_mask;
898 int count;
899 int cpu;
900
901 cpus_clear(core_mask);
902 count = 0;
903 for_each_online_cpu(cpu) {
904 if (!cpu_isset(cpu, core_mask)) {
905 ++count;
906 cpus_or(core_mask, core_mask,
907 topology_core_siblings(cpu));
908 }
909 }
910
911 return count;
912 }
913
914 /* Probe the number and type of interrupts we are able to obtain, and
915 * the resulting numbers of channels and RX queues.
916 */
917 static void efx_probe_interrupts(struct efx_nic *efx)
918 {
919 int max_channels =
920 min_t(int, efx->type->phys_addr_channels, EFX_MAX_CHANNELS);
921 int rc, i;
922
923 if (efx->interrupt_mode == EFX_INT_MODE_MSIX) {
924 struct msix_entry xentries[EFX_MAX_CHANNELS];
925 int wanted_ints;
926 int rx_queues;
927
928 /* We want one RX queue and interrupt per CPU package
929 * (or as specified by the rss_cpus module parameter).
930 * We will need one channel per interrupt.
931 */
932 rx_queues = rss_cpus ? rss_cpus : efx_wanted_rx_queues();
933 wanted_ints = rx_queues + (separate_tx_channels ? 1 : 0);
934 wanted_ints = min(wanted_ints, max_channels);
935
936 for (i = 0; i < wanted_ints; i++)
937 xentries[i].entry = i;
938 rc = pci_enable_msix(efx->pci_dev, xentries, wanted_ints);
939 if (rc > 0) {
940 EFX_ERR(efx, "WARNING: Insufficient MSI-X vectors"
941 " available (%d < %d).\n", rc, wanted_ints);
942 EFX_ERR(efx, "WARNING: Performance may be reduced.\n");
943 EFX_BUG_ON_PARANOID(rc >= wanted_ints);
944 wanted_ints = rc;
945 rc = pci_enable_msix(efx->pci_dev, xentries,
946 wanted_ints);
947 }
948
949 if (rc == 0) {
950 efx->n_rx_queues = min(rx_queues, wanted_ints);
951 efx->n_channels = wanted_ints;
952 for (i = 0; i < wanted_ints; i++)
953 efx->channel[i].irq = xentries[i].vector;
954 } else {
955 /* Fall back to single channel MSI */
956 efx->interrupt_mode = EFX_INT_MODE_MSI;
957 EFX_ERR(efx, "could not enable MSI-X\n");
958 }
959 }
960
961 /* Try single interrupt MSI */
962 if (efx->interrupt_mode == EFX_INT_MODE_MSI) {
963 efx->n_rx_queues = 1;
964 efx->n_channels = 1;
965 rc = pci_enable_msi(efx->pci_dev);
966 if (rc == 0) {
967 efx->channel[0].irq = efx->pci_dev->irq;
968 } else {
969 EFX_ERR(efx, "could not enable MSI\n");
970 efx->interrupt_mode = EFX_INT_MODE_LEGACY;
971 }
972 }
973
974 /* Assume legacy interrupts */
975 if (efx->interrupt_mode == EFX_INT_MODE_LEGACY) {
976 efx->n_rx_queues = 1;
977 efx->n_channels = 1 + (separate_tx_channels ? 1 : 0);
978 efx->legacy_irq = efx->pci_dev->irq;
979 }
980 }
981
982 static void efx_remove_interrupts(struct efx_nic *efx)
983 {
984 struct efx_channel *channel;
985
986 /* Remove MSI/MSI-X interrupts */
987 efx_for_each_channel(channel, efx)
988 channel->irq = 0;
989 pci_disable_msi(efx->pci_dev);
990 pci_disable_msix(efx->pci_dev);
991
992 /* Remove legacy interrupt */
993 efx->legacy_irq = 0;
994 }
995
996 static void efx_set_channels(struct efx_nic *efx)
997 {
998 struct efx_tx_queue *tx_queue;
999 struct efx_rx_queue *rx_queue;
1000
1001 efx_for_each_tx_queue(tx_queue, efx) {
1002 if (separate_tx_channels)
1003 tx_queue->channel = &efx->channel[efx->n_channels-1];
1004 else
1005 tx_queue->channel = &efx->channel[0];
1006 tx_queue->channel->used_flags |= EFX_USED_BY_TX;
1007 }
1008
1009 efx_for_each_rx_queue(rx_queue, efx) {
1010 rx_queue->channel = &efx->channel[rx_queue->queue];
1011 rx_queue->channel->used_flags |= EFX_USED_BY_RX;
1012 }
1013 }
1014
1015 static int efx_probe_nic(struct efx_nic *efx)
1016 {
1017 int rc;
1018
1019 EFX_LOG(efx, "creating NIC\n");
1020
1021 /* Carry out hardware-type specific initialisation */
1022 rc = falcon_probe_nic(efx);
1023 if (rc)
1024 return rc;
1025
1026 /* Determine the number of channels and RX queues by trying to hook
1027 * in MSI-X interrupts. */
1028 efx_probe_interrupts(efx);
1029
1030 efx_set_channels(efx);
1031
1032 /* Initialise the interrupt moderation settings */
1033 efx_init_irq_moderation(efx, tx_irq_mod_usec, rx_irq_mod_usec, true);
1034
1035 return 0;
1036 }
1037
1038 static void efx_remove_nic(struct efx_nic *efx)
1039 {
1040 EFX_LOG(efx, "destroying NIC\n");
1041
1042 efx_remove_interrupts(efx);
1043 falcon_remove_nic(efx);
1044 }
1045
1046 /**************************************************************************
1047 *
1048 * NIC startup/shutdown
1049 *
1050 *************************************************************************/
1051
1052 static int efx_probe_all(struct efx_nic *efx)
1053 {
1054 struct efx_channel *channel;
1055 int rc;
1056
1057 /* Create NIC */
1058 rc = efx_probe_nic(efx);
1059 if (rc) {
1060 EFX_ERR(efx, "failed to create NIC\n");
1061 goto fail1;
1062 }
1063
1064 /* Create port */
1065 rc = efx_probe_port(efx);
1066 if (rc) {
1067 EFX_ERR(efx, "failed to create port\n");
1068 goto fail2;
1069 }
1070
1071 /* Create channels */
1072 efx_for_each_channel(channel, efx) {
1073 rc = efx_probe_channel(channel);
1074 if (rc) {
1075 EFX_ERR(efx, "failed to create channel %d\n",
1076 channel->channel);
1077 goto fail3;
1078 }
1079 }
1080 efx_set_channel_names(efx);
1081
1082 return 0;
1083
1084 fail3:
1085 efx_for_each_channel(channel, efx)
1086 efx_remove_channel(channel);
1087 efx_remove_port(efx);
1088 fail2:
1089 efx_remove_nic(efx);
1090 fail1:
1091 return rc;
1092 }
1093
1094 /* Called after previous invocation(s) of efx_stop_all, restarts the
1095 * port, kernel transmit queue, NAPI processing and hardware interrupts,
1096 * and ensures that the port is scheduled to be reconfigured.
1097 * This function is safe to call multiple times when the NIC is in any
1098 * state. */
1099 static void efx_start_all(struct efx_nic *efx)
1100 {
1101 struct efx_channel *channel;
1102
1103 EFX_ASSERT_RESET_SERIALISED(efx);
1104
1105 /* Check that it is appropriate to restart the interface. All
1106 * of these flags are safe to read under just the rtnl lock */
1107 if (efx->port_enabled)
1108 return;
1109 if ((efx->state != STATE_RUNNING) && (efx->state != STATE_INIT))
1110 return;
1111 if (efx_dev_registered(efx) && !netif_running(efx->net_dev))
1112 return;
1113
1114 /* Mark the port as enabled so port reconfigurations can start, then
1115 * restart the transmit interface early so the watchdog timer stops */
1116 efx_start_port(efx);
1117 if (efx_dev_registered(efx))
1118 efx_wake_queue(efx);
1119
1120 efx_for_each_channel(channel, efx)
1121 efx_start_channel(channel);
1122
1123 falcon_enable_interrupts(efx);
1124
1125 /* Start hardware monitor if we're in RUNNING */
1126 if (efx->state == STATE_RUNNING)
1127 queue_delayed_work(efx->workqueue, &efx->monitor_work,
1128 efx_monitor_interval);
1129 }
1130
1131 /* Flush all delayed work. Should only be called when no more delayed work
1132 * will be scheduled. This doesn't flush pending online resets (efx_reset),
1133 * since we're holding the rtnl_lock at this point. */
1134 static void efx_flush_all(struct efx_nic *efx)
1135 {
1136 struct efx_rx_queue *rx_queue;
1137
1138 /* Make sure the hardware monitor is stopped */
1139 cancel_delayed_work_sync(&efx->monitor_work);
1140
1141 /* Ensure that all RX slow refills are complete. */
1142 efx_for_each_rx_queue(rx_queue, efx)
1143 cancel_delayed_work_sync(&rx_queue->work);
1144
1145 /* Stop scheduled port reconfigurations */
1146 cancel_work_sync(&efx->mac_work);
1147 cancel_work_sync(&efx->phy_work);
1148
1149 }
1150
1151 /* Quiesce hardware and software without bringing the link down.
1152 * Safe to call multiple times, when the nic and interface is in any
1153 * state. The caller is guaranteed to subsequently be in a position
1154 * to modify any hardware and software state they see fit without
1155 * taking locks. */
1156 static void efx_stop_all(struct efx_nic *efx)
1157 {
1158 struct efx_channel *channel;
1159
1160 EFX_ASSERT_RESET_SERIALISED(efx);
1161
1162 /* port_enabled can be read safely under the rtnl lock */
1163 if (!efx->port_enabled)
1164 return;
1165
1166 /* Disable interrupts and wait for ISR to complete */
1167 falcon_disable_interrupts(efx);
1168 if (efx->legacy_irq)
1169 synchronize_irq(efx->legacy_irq);
1170 efx_for_each_channel(channel, efx) {
1171 if (channel->irq)
1172 synchronize_irq(channel->irq);
1173 }
1174
1175 /* Stop all NAPI processing and synchronous rx refills */
1176 efx_for_each_channel(channel, efx)
1177 efx_stop_channel(channel);
1178
1179 /* Stop all asynchronous port reconfigurations. Since all
1180 * event processing has already been stopped, there is no
1181 * window to loose phy events */
1182 efx_stop_port(efx);
1183
1184 /* Flush efx_phy_work, efx_mac_work, refill_workqueue, monitor_work */
1185 efx_flush_all(efx);
1186
1187 /* Isolate the MAC from the TX and RX engines, so that queue
1188 * flushes will complete in a timely fashion. */
1189 falcon_drain_tx_fifo(efx);
1190
1191 /* Stop the kernel transmit interface late, so the watchdog
1192 * timer isn't ticking over the flush */
1193 if (efx_dev_registered(efx)) {
1194 efx_stop_queue(efx);
1195 netif_tx_lock_bh(efx->net_dev);
1196 netif_tx_unlock_bh(efx->net_dev);
1197 }
1198 }
1199
1200 static void efx_remove_all(struct efx_nic *efx)
1201 {
1202 struct efx_channel *channel;
1203
1204 efx_for_each_channel(channel, efx)
1205 efx_remove_channel(channel);
1206 efx_remove_port(efx);
1207 efx_remove_nic(efx);
1208 }
1209
1210 /* A convinience function to safely flush all the queues */
1211 void efx_flush_queues(struct efx_nic *efx)
1212 {
1213 EFX_ASSERT_RESET_SERIALISED(efx);
1214
1215 efx_stop_all(efx);
1216
1217 efx_fini_channels(efx);
1218 efx_init_channels(efx);
1219
1220 efx_start_all(efx);
1221 }
1222
1223 /**************************************************************************
1224 *
1225 * Interrupt moderation
1226 *
1227 **************************************************************************/
1228
1229 /* Set interrupt moderation parameters */
1230 void efx_init_irq_moderation(struct efx_nic *efx, int tx_usecs, int rx_usecs,
1231 bool rx_adaptive)
1232 {
1233 struct efx_tx_queue *tx_queue;
1234 struct efx_rx_queue *rx_queue;
1235
1236 EFX_ASSERT_RESET_SERIALISED(efx);
1237
1238 efx_for_each_tx_queue(tx_queue, efx)
1239 tx_queue->channel->irq_moderation = tx_usecs;
1240
1241 efx->irq_rx_adaptive = rx_adaptive;
1242 efx->irq_rx_moderation = rx_usecs;
1243 efx_for_each_rx_queue(rx_queue, efx)
1244 rx_queue->channel->irq_moderation = rx_usecs;
1245 }
1246
1247 /**************************************************************************
1248 *
1249 * Hardware monitor
1250 *
1251 **************************************************************************/
1252
1253 /* Run periodically off the general workqueue. Serialised against
1254 * efx_reconfigure_port via the mac_lock */
1255 static void efx_monitor(struct work_struct *data)
1256 {
1257 struct efx_nic *efx = container_of(data, struct efx_nic,
1258 monitor_work.work);
1259 int rc;
1260
1261 EFX_TRACE(efx, "hardware monitor executing on CPU %d\n",
1262 raw_smp_processor_id());
1263
1264 /* If the mac_lock is already held then it is likely a port
1265 * reconfiguration is already in place, which will likely do
1266 * most of the work of check_hw() anyway. */
1267 if (!mutex_trylock(&efx->mac_lock))
1268 goto out_requeue;
1269 if (!efx->port_enabled)
1270 goto out_unlock;
1271 rc = efx->board_info.monitor(efx);
1272 if (rc) {
1273 EFX_ERR(efx, "Board sensor %s; shutting down PHY\n",
1274 (rc == -ERANGE) ? "reported fault" : "failed");
1275 efx->phy_mode |= PHY_MODE_LOW_POWER;
1276 falcon_sim_phy_event(efx);
1277 }
1278 efx->phy_op->poll(efx);
1279 efx->mac_op->poll(efx);
1280
1281 out_unlock:
1282 mutex_unlock(&efx->mac_lock);
1283 out_requeue:
1284 queue_delayed_work(efx->workqueue, &efx->monitor_work,
1285 efx_monitor_interval);
1286 }
1287
1288 /**************************************************************************
1289 *
1290 * ioctls
1291 *
1292 *************************************************************************/
1293
1294 /* Net device ioctl
1295 * Context: process, rtnl_lock() held.
1296 */
1297 static int efx_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
1298 {
1299 struct efx_nic *efx = netdev_priv(net_dev);
1300
1301 EFX_ASSERT_RESET_SERIALISED(efx);
1302
1303 return generic_mii_ioctl(&efx->mii, if_mii(ifr), cmd, NULL);
1304 }
1305
1306 /**************************************************************************
1307 *
1308 * NAPI interface
1309 *
1310 **************************************************************************/
1311
1312 static int efx_init_napi(struct efx_nic *efx)
1313 {
1314 struct efx_channel *channel;
1315
1316 efx_for_each_channel(channel, efx) {
1317 channel->napi_dev = efx->net_dev;
1318 }
1319 return 0;
1320 }
1321
1322 static void efx_fini_napi(struct efx_nic *efx)
1323 {
1324 struct efx_channel *channel;
1325
1326 efx_for_each_channel(channel, efx) {
1327 channel->napi_dev = NULL;
1328 }
1329 }
1330
1331 /**************************************************************************
1332 *
1333 * Kernel netpoll interface
1334 *
1335 *************************************************************************/
1336
1337 #ifdef CONFIG_NET_POLL_CONTROLLER
1338
1339 /* Although in the common case interrupts will be disabled, this is not
1340 * guaranteed. However, all our work happens inside the NAPI callback,
1341 * so no locking is required.
1342 */
1343 static void efx_netpoll(struct net_device *net_dev)
1344 {
1345 struct efx_nic *efx = netdev_priv(net_dev);
1346 struct efx_channel *channel;
1347
1348 efx_for_each_channel(channel, efx)
1349 efx_schedule_channel(channel);
1350 }
1351
1352 #endif
1353
1354 /**************************************************************************
1355 *
1356 * Kernel net device interface
1357 *
1358 *************************************************************************/
1359
1360 /* Context: process, rtnl_lock() held. */
1361 static int efx_net_open(struct net_device *net_dev)
1362 {
1363 struct efx_nic *efx = netdev_priv(net_dev);
1364 EFX_ASSERT_RESET_SERIALISED(efx);
1365
1366 EFX_LOG(efx, "opening device %s on CPU %d\n", net_dev->name,
1367 raw_smp_processor_id());
1368
1369 if (efx->state == STATE_DISABLED)
1370 return -EIO;
1371 if (efx->phy_mode & PHY_MODE_SPECIAL)
1372 return -EBUSY;
1373
1374 efx_start_all(efx);
1375 return 0;
1376 }
1377
1378 /* Context: process, rtnl_lock() held.
1379 * Note that the kernel will ignore our return code; this method
1380 * should really be a void.
1381 */
1382 static int efx_net_stop(struct net_device *net_dev)
1383 {
1384 struct efx_nic *efx = netdev_priv(net_dev);
1385
1386 EFX_LOG(efx, "closing %s on CPU %d\n", net_dev->name,
1387 raw_smp_processor_id());
1388
1389 if (efx->state != STATE_DISABLED) {
1390 /* Stop the device and flush all the channels */
1391 efx_stop_all(efx);
1392 efx_fini_channels(efx);
1393 efx_init_channels(efx);
1394 }
1395
1396 return 0;
1397 }
1398
1399 void efx_stats_disable(struct efx_nic *efx)
1400 {
1401 spin_lock(&efx->stats_lock);
1402 ++efx->stats_disable_count;
1403 spin_unlock(&efx->stats_lock);
1404 }
1405
1406 void efx_stats_enable(struct efx_nic *efx)
1407 {
1408 spin_lock(&efx->stats_lock);
1409 --efx->stats_disable_count;
1410 spin_unlock(&efx->stats_lock);
1411 }
1412
1413 /* Context: process, dev_base_lock or RTNL held, non-blocking. */
1414 static struct net_device_stats *efx_net_stats(struct net_device *net_dev)
1415 {
1416 struct efx_nic *efx = netdev_priv(net_dev);
1417 struct efx_mac_stats *mac_stats = &efx->mac_stats;
1418 struct net_device_stats *stats = &net_dev->stats;
1419
1420 /* Update stats if possible, but do not wait if another thread
1421 * is updating them or if MAC stats fetches are temporarily
1422 * disabled; slightly stale stats are acceptable.
1423 */
1424 if (!spin_trylock(&efx->stats_lock))
1425 return stats;
1426 if (!efx->stats_disable_count) {
1427 efx->mac_op->update_stats(efx);
1428 falcon_update_nic_stats(efx);
1429 }
1430 spin_unlock(&efx->stats_lock);
1431
1432 stats->rx_packets = mac_stats->rx_packets;
1433 stats->tx_packets = mac_stats->tx_packets;
1434 stats->rx_bytes = mac_stats->rx_bytes;
1435 stats->tx_bytes = mac_stats->tx_bytes;
1436 stats->multicast = mac_stats->rx_multicast;
1437 stats->collisions = mac_stats->tx_collision;
1438 stats->rx_length_errors = (mac_stats->rx_gtjumbo +
1439 mac_stats->rx_length_error);
1440 stats->rx_over_errors = efx->n_rx_nodesc_drop_cnt;
1441 stats->rx_crc_errors = mac_stats->rx_bad;
1442 stats->rx_frame_errors = mac_stats->rx_align_error;
1443 stats->rx_fifo_errors = mac_stats->rx_overflow;
1444 stats->rx_missed_errors = mac_stats->rx_missed;
1445 stats->tx_window_errors = mac_stats->tx_late_collision;
1446
1447 stats->rx_errors = (stats->rx_length_errors +
1448 stats->rx_over_errors +
1449 stats->rx_crc_errors +
1450 stats->rx_frame_errors +
1451 stats->rx_fifo_errors +
1452 stats->rx_missed_errors +
1453 mac_stats->rx_symbol_error);
1454 stats->tx_errors = (stats->tx_window_errors +
1455 mac_stats->tx_bad);
1456
1457 return stats;
1458 }
1459
1460 /* Context: netif_tx_lock held, BHs disabled. */
1461 static void efx_watchdog(struct net_device *net_dev)
1462 {
1463 struct efx_nic *efx = netdev_priv(net_dev);
1464
1465 EFX_ERR(efx, "TX stuck with stop_count=%d port_enabled=%d:"
1466 " resetting channels\n",
1467 atomic_read(&efx->netif_stop_count), efx->port_enabled);
1468
1469 efx_schedule_reset(efx, RESET_TYPE_TX_WATCHDOG);
1470 }
1471
1472
1473 /* Context: process, rtnl_lock() held. */
1474 static int efx_change_mtu(struct net_device *net_dev, int new_mtu)
1475 {
1476 struct efx_nic *efx = netdev_priv(net_dev);
1477 int rc = 0;
1478
1479 EFX_ASSERT_RESET_SERIALISED(efx);
1480
1481 if (new_mtu > EFX_MAX_MTU)
1482 return -EINVAL;
1483
1484 efx_stop_all(efx);
1485
1486 EFX_LOG(efx, "changing MTU to %d\n", new_mtu);
1487
1488 efx_fini_channels(efx);
1489 net_dev->mtu = new_mtu;
1490 efx_init_channels(efx);
1491
1492 efx_start_all(efx);
1493 return rc;
1494 }
1495
1496 static int efx_set_mac_address(struct net_device *net_dev, void *data)
1497 {
1498 struct efx_nic *efx = netdev_priv(net_dev);
1499 struct sockaddr *addr = data;
1500 char *new_addr = addr->sa_data;
1501
1502 EFX_ASSERT_RESET_SERIALISED(efx);
1503
1504 if (!is_valid_ether_addr(new_addr)) {
1505 EFX_ERR(efx, "invalid ethernet MAC address requested: %pM\n",
1506 new_addr);
1507 return -EINVAL;
1508 }
1509
1510 memcpy(net_dev->dev_addr, new_addr, net_dev->addr_len);
1511
1512 /* Reconfigure the MAC */
1513 efx_reconfigure_port(efx);
1514
1515 return 0;
1516 }
1517
1518 /* Context: netif_addr_lock held, BHs disabled. */
1519 static void efx_set_multicast_list(struct net_device *net_dev)
1520 {
1521 struct efx_nic *efx = netdev_priv(net_dev);
1522 struct dev_mc_list *mc_list = net_dev->mc_list;
1523 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
1524 bool promiscuous = !!(net_dev->flags & IFF_PROMISC);
1525 bool changed = (efx->promiscuous != promiscuous);
1526 u32 crc;
1527 int bit;
1528 int i;
1529
1530 efx->promiscuous = promiscuous;
1531
1532 /* Build multicast hash table */
1533 if (promiscuous || (net_dev->flags & IFF_ALLMULTI)) {
1534 memset(mc_hash, 0xff, sizeof(*mc_hash));
1535 } else {
1536 memset(mc_hash, 0x00, sizeof(*mc_hash));
1537 for (i = 0; i < net_dev->mc_count; i++) {
1538 crc = ether_crc_le(ETH_ALEN, mc_list->dmi_addr);
1539 bit = crc & (EFX_MCAST_HASH_ENTRIES - 1);
1540 set_bit_le(bit, mc_hash->byte);
1541 mc_list = mc_list->next;
1542 }
1543 }
1544
1545 if (!efx->port_enabled)
1546 /* Delay pushing settings until efx_start_port() */
1547 return;
1548
1549 if (changed)
1550 queue_work(efx->workqueue, &efx->phy_work);
1551
1552 /* Create and activate new global multicast hash table */
1553 falcon_set_multicast_hash(efx);
1554 }
1555
1556 static const struct net_device_ops efx_netdev_ops = {
1557 .ndo_open = efx_net_open,
1558 .ndo_stop = efx_net_stop,
1559 .ndo_get_stats = efx_net_stats,
1560 .ndo_tx_timeout = efx_watchdog,
1561 .ndo_start_xmit = efx_hard_start_xmit,
1562 .ndo_validate_addr = eth_validate_addr,
1563 .ndo_do_ioctl = efx_ioctl,
1564 .ndo_change_mtu = efx_change_mtu,
1565 .ndo_set_mac_address = efx_set_mac_address,
1566 .ndo_set_multicast_list = efx_set_multicast_list,
1567 #ifdef CONFIG_NET_POLL_CONTROLLER
1568 .ndo_poll_controller = efx_netpoll,
1569 #endif
1570 };
1571
1572 static void efx_update_name(struct efx_nic *efx)
1573 {
1574 strcpy(efx->name, efx->net_dev->name);
1575 efx_mtd_rename(efx);
1576 efx_set_channel_names(efx);
1577 }
1578
1579 static int efx_netdev_event(struct notifier_block *this,
1580 unsigned long event, void *ptr)
1581 {
1582 struct net_device *net_dev = ptr;
1583
1584 if (net_dev->netdev_ops == &efx_netdev_ops &&
1585 event == NETDEV_CHANGENAME)
1586 efx_update_name(netdev_priv(net_dev));
1587
1588 return NOTIFY_DONE;
1589 }
1590
1591 static struct notifier_block efx_netdev_notifier = {
1592 .notifier_call = efx_netdev_event,
1593 };
1594
1595 static ssize_t
1596 show_phy_type(struct device *dev, struct device_attribute *attr, char *buf)
1597 {
1598 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
1599 return sprintf(buf, "%d\n", efx->phy_type);
1600 }
1601 static DEVICE_ATTR(phy_type, 0644, show_phy_type, NULL);
1602
1603 static int efx_register_netdev(struct efx_nic *efx)
1604 {
1605 struct net_device *net_dev = efx->net_dev;
1606 int rc;
1607
1608 net_dev->watchdog_timeo = 5 * HZ;
1609 net_dev->irq = efx->pci_dev->irq;
1610 net_dev->netdev_ops = &efx_netdev_ops;
1611 SET_NETDEV_DEV(net_dev, &efx->pci_dev->dev);
1612 SET_ETHTOOL_OPS(net_dev, &efx_ethtool_ops);
1613
1614 /* Always start with carrier off; PHY events will detect the link */
1615 netif_carrier_off(efx->net_dev);
1616
1617 /* Clear MAC statistics */
1618 efx->mac_op->update_stats(efx);
1619 memset(&efx->mac_stats, 0, sizeof(efx->mac_stats));
1620
1621 rc = register_netdev(net_dev);
1622 if (rc) {
1623 EFX_ERR(efx, "could not register net dev\n");
1624 return rc;
1625 }
1626
1627 rtnl_lock();
1628 efx_update_name(efx);
1629 rtnl_unlock();
1630
1631 rc = device_create_file(&efx->pci_dev->dev, &dev_attr_phy_type);
1632 if (rc) {
1633 EFX_ERR(efx, "failed to init net dev attributes\n");
1634 goto fail_registered;
1635 }
1636
1637 return 0;
1638
1639 fail_registered:
1640 unregister_netdev(net_dev);
1641 return rc;
1642 }
1643
1644 static void efx_unregister_netdev(struct efx_nic *efx)
1645 {
1646 struct efx_tx_queue *tx_queue;
1647
1648 if (!efx->net_dev)
1649 return;
1650
1651 BUG_ON(netdev_priv(efx->net_dev) != efx);
1652
1653 /* Free up any skbs still remaining. This has to happen before
1654 * we try to unregister the netdev as running their destructors
1655 * may be needed to get the device ref. count to 0. */
1656 efx_for_each_tx_queue(tx_queue, efx)
1657 efx_release_tx_buffers(tx_queue);
1658
1659 if (efx_dev_registered(efx)) {
1660 strlcpy(efx->name, pci_name(efx->pci_dev), sizeof(efx->name));
1661 device_remove_file(&efx->pci_dev->dev, &dev_attr_phy_type);
1662 unregister_netdev(efx->net_dev);
1663 }
1664 }
1665
1666 /**************************************************************************
1667 *
1668 * Device reset and suspend
1669 *
1670 **************************************************************************/
1671
1672 /* Tears down the entire software state and most of the hardware state
1673 * before reset. */
1674 void efx_reset_down(struct efx_nic *efx, enum reset_type method,
1675 struct ethtool_cmd *ecmd)
1676 {
1677 EFX_ASSERT_RESET_SERIALISED(efx);
1678
1679 efx_stats_disable(efx);
1680 efx_stop_all(efx);
1681 mutex_lock(&efx->mac_lock);
1682 mutex_lock(&efx->spi_lock);
1683
1684 efx->phy_op->get_settings(efx, ecmd);
1685
1686 efx_fini_channels(efx);
1687 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE)
1688 efx->phy_op->fini(efx);
1689 }
1690
1691 /* This function will always ensure that the locks acquired in
1692 * efx_reset_down() are released. A failure return code indicates
1693 * that we were unable to reinitialise the hardware, and the
1694 * driver should be disabled. If ok is false, then the rx and tx
1695 * engines are not restarted, pending a RESET_DISABLE. */
1696 int efx_reset_up(struct efx_nic *efx, enum reset_type method,
1697 struct ethtool_cmd *ecmd, bool ok)
1698 {
1699 int rc;
1700
1701 EFX_ASSERT_RESET_SERIALISED(efx);
1702
1703 rc = falcon_init_nic(efx);
1704 if (rc) {
1705 EFX_ERR(efx, "failed to initialise NIC\n");
1706 ok = false;
1707 }
1708
1709 if (efx->port_initialized && method != RESET_TYPE_INVISIBLE) {
1710 if (ok) {
1711 rc = efx->phy_op->init(efx);
1712 if (rc)
1713 ok = false;
1714 }
1715 if (!ok)
1716 efx->port_initialized = false;
1717 }
1718
1719 if (ok) {
1720 efx_init_channels(efx);
1721
1722 if (efx->phy_op->set_settings(efx, ecmd))
1723 EFX_ERR(efx, "could not restore PHY settings\n");
1724 }
1725
1726 mutex_unlock(&efx->spi_lock);
1727 mutex_unlock(&efx->mac_lock);
1728
1729 if (ok) {
1730 efx_start_all(efx);
1731 efx_stats_enable(efx);
1732 }
1733 return rc;
1734 }
1735
1736 /* Reset the NIC as transparently as possible. Do not reset the PHY
1737 * Note that the reset may fail, in which case the card will be left
1738 * in a most-probably-unusable state.
1739 *
1740 * This function will sleep. You cannot reset from within an atomic
1741 * state; use efx_schedule_reset() instead.
1742 *
1743 * Grabs the rtnl_lock.
1744 */
1745 static int efx_reset(struct efx_nic *efx)
1746 {
1747 struct ethtool_cmd ecmd;
1748 enum reset_type method = efx->reset_pending;
1749 int rc = 0;
1750
1751 /* Serialise with kernel interfaces */
1752 rtnl_lock();
1753
1754 /* If we're not RUNNING then don't reset. Leave the reset_pending
1755 * flag set so that efx_pci_probe_main will be retried */
1756 if (efx->state != STATE_RUNNING) {
1757 EFX_INFO(efx, "scheduled reset quenched. NIC not RUNNING\n");
1758 goto out_unlock;
1759 }
1760
1761 EFX_INFO(efx, "resetting (%d)\n", method);
1762
1763 efx_reset_down(efx, method, &ecmd);
1764
1765 rc = falcon_reset_hw(efx, method);
1766 if (rc) {
1767 EFX_ERR(efx, "failed to reset hardware\n");
1768 goto out_disable;
1769 }
1770
1771 /* Allow resets to be rescheduled. */
1772 efx->reset_pending = RESET_TYPE_NONE;
1773
1774 /* Reinitialise bus-mastering, which may have been turned off before
1775 * the reset was scheduled. This is still appropriate, even in the
1776 * RESET_TYPE_DISABLE since this driver generally assumes the hardware
1777 * can respond to requests. */
1778 pci_set_master(efx->pci_dev);
1779
1780 /* Leave device stopped if necessary */
1781 if (method == RESET_TYPE_DISABLE) {
1782 efx_reset_up(efx, method, &ecmd, false);
1783 rc = -EIO;
1784 } else {
1785 rc = efx_reset_up(efx, method, &ecmd, true);
1786 }
1787
1788 out_disable:
1789 if (rc) {
1790 EFX_ERR(efx, "has been disabled\n");
1791 efx->state = STATE_DISABLED;
1792 dev_close(efx->net_dev);
1793 } else {
1794 EFX_LOG(efx, "reset complete\n");
1795 }
1796
1797 out_unlock:
1798 rtnl_unlock();
1799 return rc;
1800 }
1801
1802 /* The worker thread exists so that code that cannot sleep can
1803 * schedule a reset for later.
1804 */
1805 static void efx_reset_work(struct work_struct *data)
1806 {
1807 struct efx_nic *nic = container_of(data, struct efx_nic, reset_work);
1808
1809 efx_reset(nic);
1810 }
1811
1812 void efx_schedule_reset(struct efx_nic *efx, enum reset_type type)
1813 {
1814 enum reset_type method;
1815
1816 if (efx->reset_pending != RESET_TYPE_NONE) {
1817 EFX_INFO(efx, "quenching already scheduled reset\n");
1818 return;
1819 }
1820
1821 switch (type) {
1822 case RESET_TYPE_INVISIBLE:
1823 case RESET_TYPE_ALL:
1824 case RESET_TYPE_WORLD:
1825 case RESET_TYPE_DISABLE:
1826 method = type;
1827 break;
1828 case RESET_TYPE_RX_RECOVERY:
1829 case RESET_TYPE_RX_DESC_FETCH:
1830 case RESET_TYPE_TX_DESC_FETCH:
1831 case RESET_TYPE_TX_SKIP:
1832 method = RESET_TYPE_INVISIBLE;
1833 break;
1834 default:
1835 method = RESET_TYPE_ALL;
1836 break;
1837 }
1838
1839 if (method != type)
1840 EFX_LOG(efx, "scheduling reset (%d:%d)\n", type, method);
1841 else
1842 EFX_LOG(efx, "scheduling reset (%d)\n", method);
1843
1844 efx->reset_pending = method;
1845
1846 queue_work(reset_workqueue, &efx->reset_work);
1847 }
1848
1849 /**************************************************************************
1850 *
1851 * List of NICs we support
1852 *
1853 **************************************************************************/
1854
1855 /* PCI device ID table */
1856 static struct pci_device_id efx_pci_table[] __devinitdata = {
1857 {PCI_DEVICE(EFX_VENDID_SFC, FALCON_A_P_DEVID),
1858 .driver_data = (unsigned long) &falcon_a_nic_type},
1859 {PCI_DEVICE(EFX_VENDID_SFC, FALCON_B_P_DEVID),
1860 .driver_data = (unsigned long) &falcon_b_nic_type},
1861 {0} /* end of list */
1862 };
1863
1864 /**************************************************************************
1865 *
1866 * Dummy PHY/MAC/Board operations
1867 *
1868 * Can be used for some unimplemented operations
1869 * Needed so all function pointers are valid and do not have to be tested
1870 * before use
1871 *
1872 **************************************************************************/
1873 int efx_port_dummy_op_int(struct efx_nic *efx)
1874 {
1875 return 0;
1876 }
1877 void efx_port_dummy_op_void(struct efx_nic *efx) {}
1878 void efx_port_dummy_op_blink(struct efx_nic *efx, bool blink) {}
1879
1880 static struct efx_mac_operations efx_dummy_mac_operations = {
1881 .reconfigure = efx_port_dummy_op_void,
1882 .poll = efx_port_dummy_op_void,
1883 .irq = efx_port_dummy_op_void,
1884 };
1885
1886 static struct efx_phy_operations efx_dummy_phy_operations = {
1887 .init = efx_port_dummy_op_int,
1888 .reconfigure = efx_port_dummy_op_void,
1889 .poll = efx_port_dummy_op_void,
1890 .fini = efx_port_dummy_op_void,
1891 .clear_interrupt = efx_port_dummy_op_void,
1892 };
1893
1894 static struct efx_board efx_dummy_board_info = {
1895 .init = efx_port_dummy_op_int,
1896 .init_leds = efx_port_dummy_op_void,
1897 .set_id_led = efx_port_dummy_op_blink,
1898 .monitor = efx_port_dummy_op_int,
1899 .blink = efx_port_dummy_op_blink,
1900 .fini = efx_port_dummy_op_void,
1901 };
1902
1903 /**************************************************************************
1904 *
1905 * Data housekeeping
1906 *
1907 **************************************************************************/
1908
1909 /* This zeroes out and then fills in the invariants in a struct
1910 * efx_nic (including all sub-structures).
1911 */
1912 static int efx_init_struct(struct efx_nic *efx, struct efx_nic_type *type,
1913 struct pci_dev *pci_dev, struct net_device *net_dev)
1914 {
1915 struct efx_channel *channel;
1916 struct efx_tx_queue *tx_queue;
1917 struct efx_rx_queue *rx_queue;
1918 int i;
1919
1920 /* Initialise common structures */
1921 memset(efx, 0, sizeof(*efx));
1922 spin_lock_init(&efx->biu_lock);
1923 spin_lock_init(&efx->phy_lock);
1924 mutex_init(&efx->spi_lock);
1925 INIT_WORK(&efx->reset_work, efx_reset_work);
1926 INIT_DELAYED_WORK(&efx->monitor_work, efx_monitor);
1927 efx->pci_dev = pci_dev;
1928 efx->state = STATE_INIT;
1929 efx->reset_pending = RESET_TYPE_NONE;
1930 strlcpy(efx->name, pci_name(pci_dev), sizeof(efx->name));
1931 efx->board_info = efx_dummy_board_info;
1932
1933 efx->net_dev = net_dev;
1934 efx->rx_checksum_enabled = true;
1935 spin_lock_init(&efx->netif_stop_lock);
1936 spin_lock_init(&efx->stats_lock);
1937 efx->stats_disable_count = 1;
1938 mutex_init(&efx->mac_lock);
1939 efx->mac_op = &efx_dummy_mac_operations;
1940 efx->phy_op = &efx_dummy_phy_operations;
1941 efx->mii.dev = net_dev;
1942 INIT_WORK(&efx->phy_work, efx_phy_work);
1943 INIT_WORK(&efx->mac_work, efx_mac_work);
1944 atomic_set(&efx->netif_stop_count, 1);
1945
1946 for (i = 0; i < EFX_MAX_CHANNELS; i++) {
1947 channel = &efx->channel[i];
1948 channel->efx = efx;
1949 channel->channel = i;
1950 channel->work_pending = false;
1951 }
1952 for (i = 0; i < EFX_TX_QUEUE_COUNT; i++) {
1953 tx_queue = &efx->tx_queue[i];
1954 tx_queue->efx = efx;
1955 tx_queue->queue = i;
1956 tx_queue->buffer = NULL;
1957 tx_queue->channel = &efx->channel[0]; /* for safety */
1958 tx_queue->tso_headers_free = NULL;
1959 }
1960 for (i = 0; i < EFX_MAX_RX_QUEUES; i++) {
1961 rx_queue = &efx->rx_queue[i];
1962 rx_queue->efx = efx;
1963 rx_queue->queue = i;
1964 rx_queue->channel = &efx->channel[0]; /* for safety */
1965 rx_queue->buffer = NULL;
1966 spin_lock_init(&rx_queue->add_lock);
1967 INIT_DELAYED_WORK(&rx_queue->work, efx_rx_work);
1968 }
1969
1970 efx->type = type;
1971
1972 /* Sanity-check NIC type */
1973 EFX_BUG_ON_PARANOID(efx->type->txd_ring_mask &
1974 (efx->type->txd_ring_mask + 1));
1975 EFX_BUG_ON_PARANOID(efx->type->rxd_ring_mask &
1976 (efx->type->rxd_ring_mask + 1));
1977 EFX_BUG_ON_PARANOID(efx->type->evq_size &
1978 (efx->type->evq_size - 1));
1979 /* As close as we can get to guaranteeing that we don't overflow */
1980 EFX_BUG_ON_PARANOID(efx->type->evq_size <
1981 (efx->type->txd_ring_mask + 1 +
1982 efx->type->rxd_ring_mask + 1));
1983 EFX_BUG_ON_PARANOID(efx->type->phys_addr_channels > EFX_MAX_CHANNELS);
1984
1985 /* Higher numbered interrupt modes are less capable! */
1986 efx->interrupt_mode = max(efx->type->max_interrupt_mode,
1987 interrupt_mode);
1988
1989 /* Would be good to use the net_dev name, but we're too early */
1990 snprintf(efx->workqueue_name, sizeof(efx->workqueue_name), "sfc%s",
1991 pci_name(pci_dev));
1992 efx->workqueue = create_singlethread_workqueue(efx->workqueue_name);
1993 if (!efx->workqueue)
1994 return -ENOMEM;
1995
1996 return 0;
1997 }
1998
1999 static void efx_fini_struct(struct efx_nic *efx)
2000 {
2001 if (efx->workqueue) {
2002 destroy_workqueue(efx->workqueue);
2003 efx->workqueue = NULL;
2004 }
2005 }
2006
2007 /**************************************************************************
2008 *
2009 * PCI interface
2010 *
2011 **************************************************************************/
2012
2013 /* Main body of final NIC shutdown code
2014 * This is called only at module unload (or hotplug removal).
2015 */
2016 static void efx_pci_remove_main(struct efx_nic *efx)
2017 {
2018 EFX_ASSERT_RESET_SERIALISED(efx);
2019
2020 /* Skip everything if we never obtained a valid membase */
2021 if (!efx->membase)
2022 return;
2023
2024 efx_fini_channels(efx);
2025 efx_fini_port(efx);
2026
2027 /* Shutdown the board, then the NIC and board state */
2028 efx->board_info.fini(efx);
2029 falcon_fini_interrupt(efx);
2030
2031 efx_fini_napi(efx);
2032 efx_remove_all(efx);
2033 }
2034
2035 /* Final NIC shutdown
2036 * This is called only at module unload (or hotplug removal).
2037 */
2038 static void efx_pci_remove(struct pci_dev *pci_dev)
2039 {
2040 struct efx_nic *efx;
2041
2042 efx = pci_get_drvdata(pci_dev);
2043 if (!efx)
2044 return;
2045
2046 /* Mark the NIC as fini, then stop the interface */
2047 rtnl_lock();
2048 efx->state = STATE_FINI;
2049 dev_close(efx->net_dev);
2050
2051 /* Allow any queued efx_resets() to complete */
2052 rtnl_unlock();
2053
2054 if (efx->membase == NULL)
2055 goto out;
2056
2057 efx_unregister_netdev(efx);
2058
2059 efx_mtd_remove(efx);
2060
2061 /* Wait for any scheduled resets to complete. No more will be
2062 * scheduled from this point because efx_stop_all() has been
2063 * called, we are no longer registered with driverlink, and
2064 * the net_device's have been removed. */
2065 cancel_work_sync(&efx->reset_work);
2066
2067 efx_pci_remove_main(efx);
2068
2069 out:
2070 efx_fini_io(efx);
2071 EFX_LOG(efx, "shutdown successful\n");
2072
2073 pci_set_drvdata(pci_dev, NULL);
2074 efx_fini_struct(efx);
2075 free_netdev(efx->net_dev);
2076 };
2077
2078 /* Main body of NIC initialisation
2079 * This is called at module load (or hotplug insertion, theoretically).
2080 */
2081 static int efx_pci_probe_main(struct efx_nic *efx)
2082 {
2083 int rc;
2084
2085 /* Do start-of-day initialisation */
2086 rc = efx_probe_all(efx);
2087 if (rc)
2088 goto fail1;
2089
2090 rc = efx_init_napi(efx);
2091 if (rc)
2092 goto fail2;
2093
2094 /* Initialise the board */
2095 rc = efx->board_info.init(efx);
2096 if (rc) {
2097 EFX_ERR(efx, "failed to initialise board\n");
2098 goto fail3;
2099 }
2100
2101 rc = falcon_init_nic(efx);
2102 if (rc) {
2103 EFX_ERR(efx, "failed to initialise NIC\n");
2104 goto fail4;
2105 }
2106
2107 rc = efx_init_port(efx);
2108 if (rc) {
2109 EFX_ERR(efx, "failed to initialise port\n");
2110 goto fail5;
2111 }
2112
2113 efx_init_channels(efx);
2114
2115 rc = falcon_init_interrupt(efx);
2116 if (rc)
2117 goto fail6;
2118
2119 return 0;
2120
2121 fail6:
2122 efx_fini_channels(efx);
2123 efx_fini_port(efx);
2124 fail5:
2125 fail4:
2126 efx->board_info.fini(efx);
2127 fail3:
2128 efx_fini_napi(efx);
2129 fail2:
2130 efx_remove_all(efx);
2131 fail1:
2132 return rc;
2133 }
2134
2135 /* NIC initialisation
2136 *
2137 * This is called at module load (or hotplug insertion,
2138 * theoretically). It sets up PCI mappings, tests and resets the NIC,
2139 * sets up and registers the network devices with the kernel and hooks
2140 * the interrupt service routine. It does not prepare the device for
2141 * transmission; this is left to the first time one of the network
2142 * interfaces is brought up (i.e. efx_net_open).
2143 */
2144 static int __devinit efx_pci_probe(struct pci_dev *pci_dev,
2145 const struct pci_device_id *entry)
2146 {
2147 struct efx_nic_type *type = (struct efx_nic_type *) entry->driver_data;
2148 struct net_device *net_dev;
2149 struct efx_nic *efx;
2150 int i, rc;
2151
2152 /* Allocate and initialise a struct net_device and struct efx_nic */
2153 net_dev = alloc_etherdev(sizeof(*efx));
2154 if (!net_dev)
2155 return -ENOMEM;
2156 net_dev->features |= (NETIF_F_IP_CSUM | NETIF_F_SG |
2157 NETIF_F_HIGHDMA | NETIF_F_TSO);
2158 if (lro)
2159 net_dev->features |= NETIF_F_GRO;
2160 /* Mask for features that also apply to VLAN devices */
2161 net_dev->vlan_features |= (NETIF_F_ALL_CSUM | NETIF_F_SG |
2162 NETIF_F_HIGHDMA | NETIF_F_TSO);
2163 efx = netdev_priv(net_dev);
2164 pci_set_drvdata(pci_dev, efx);
2165 rc = efx_init_struct(efx, type, pci_dev, net_dev);
2166 if (rc)
2167 goto fail1;
2168
2169 EFX_INFO(efx, "Solarflare Communications NIC detected\n");
2170
2171 /* Set up basic I/O (BAR mappings etc) */
2172 rc = efx_init_io(efx);
2173 if (rc)
2174 goto fail2;
2175
2176 /* No serialisation is required with the reset path because
2177 * we're in STATE_INIT. */
2178 for (i = 0; i < 5; i++) {
2179 rc = efx_pci_probe_main(efx);
2180
2181 /* Serialise against efx_reset(). No more resets will be
2182 * scheduled since efx_stop_all() has been called, and we
2183 * have not and never have been registered with either
2184 * the rtnetlink or driverlink layers. */
2185 cancel_work_sync(&efx->reset_work);
2186
2187 if (rc == 0) {
2188 if (efx->reset_pending != RESET_TYPE_NONE) {
2189 /* If there was a scheduled reset during
2190 * probe, the NIC is probably hosed anyway */
2191 efx_pci_remove_main(efx);
2192 rc = -EIO;
2193 } else {
2194 break;
2195 }
2196 }
2197
2198 /* Retry if a recoverably reset event has been scheduled */
2199 if ((efx->reset_pending != RESET_TYPE_INVISIBLE) &&
2200 (efx->reset_pending != RESET_TYPE_ALL))
2201 goto fail3;
2202
2203 efx->reset_pending = RESET_TYPE_NONE;
2204 }
2205
2206 if (rc) {
2207 EFX_ERR(efx, "Could not reset NIC\n");
2208 goto fail4;
2209 }
2210
2211 /* Switch to the running state before we expose the device to
2212 * the OS. This is to ensure that the initial gathering of
2213 * MAC stats succeeds. */
2214 efx->state = STATE_RUNNING;
2215
2216 efx_mtd_probe(efx); /* allowed to fail */
2217
2218 rc = efx_register_netdev(efx);
2219 if (rc)
2220 goto fail5;
2221
2222 EFX_LOG(efx, "initialisation successful\n");
2223 return 0;
2224
2225 fail5:
2226 efx_pci_remove_main(efx);
2227 fail4:
2228 fail3:
2229 efx_fini_io(efx);
2230 fail2:
2231 efx_fini_struct(efx);
2232 fail1:
2233 EFX_LOG(efx, "initialisation failed. rc=%d\n", rc);
2234 free_netdev(net_dev);
2235 return rc;
2236 }
2237
2238 static struct pci_driver efx_pci_driver = {
2239 .name = EFX_DRIVER_NAME,
2240 .id_table = efx_pci_table,
2241 .probe = efx_pci_probe,
2242 .remove = efx_pci_remove,
2243 };
2244
2245 /**************************************************************************
2246 *
2247 * Kernel module interface
2248 *
2249 *************************************************************************/
2250
2251 module_param(interrupt_mode, uint, 0444);
2252 MODULE_PARM_DESC(interrupt_mode,
2253 "Interrupt mode (0=>MSIX 1=>MSI 2=>legacy)");
2254
2255 static int __init efx_init_module(void)
2256 {
2257 int rc;
2258
2259 printk(KERN_INFO "Solarflare NET driver v" EFX_DRIVER_VERSION "\n");
2260
2261 rc = register_netdevice_notifier(&efx_netdev_notifier);
2262 if (rc)
2263 goto err_notifier;
2264
2265 refill_workqueue = create_workqueue("sfc_refill");
2266 if (!refill_workqueue) {
2267 rc = -ENOMEM;
2268 goto err_refill;
2269 }
2270 reset_workqueue = create_singlethread_workqueue("sfc_reset");
2271 if (!reset_workqueue) {
2272 rc = -ENOMEM;
2273 goto err_reset;
2274 }
2275
2276 rc = pci_register_driver(&efx_pci_driver);
2277 if (rc < 0)
2278 goto err_pci;
2279
2280 return 0;
2281
2282 err_pci:
2283 destroy_workqueue(reset_workqueue);
2284 err_reset:
2285 destroy_workqueue(refill_workqueue);
2286 err_refill:
2287 unregister_netdevice_notifier(&efx_netdev_notifier);
2288 err_notifier:
2289 return rc;
2290 }
2291
2292 static void __exit efx_exit_module(void)
2293 {
2294 printk(KERN_INFO "Solarflare NET driver unloading\n");
2295
2296 pci_unregister_driver(&efx_pci_driver);
2297 destroy_workqueue(reset_workqueue);
2298 destroy_workqueue(refill_workqueue);
2299 unregister_netdevice_notifier(&efx_netdev_notifier);
2300
2301 }
2302
2303 module_init(efx_init_module);
2304 module_exit(efx_exit_module);
2305
2306 MODULE_AUTHOR("Michael Brown <mbrown@fensystems.co.uk> and "
2307 "Solarflare Communications");
2308 MODULE_DESCRIPTION("Solarflare Communications network driver");
2309 MODULE_LICENSE("GPL");
2310 MODULE_DEVICE_TABLE(pci, efx_pci_table);