2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/pci-aspm.h>
52 #include <linux/ethtool.h>
53 #include <linux/uaccess.h>
54 #include <linux/slab.h>
56 #include <net/ieee80211_radiotap.h>
58 #include <asm/unaligned.h>
65 static int modparam_nohwcrypt
;
66 module_param_named(nohwcrypt
, modparam_nohwcrypt
, bool, S_IRUGO
);
67 MODULE_PARM_DESC(nohwcrypt
, "Disable hardware encryption.");
69 static int modparam_all_channels
;
70 module_param_named(all_channels
, modparam_all_channels
, bool, S_IRUGO
);
71 MODULE_PARM_DESC(all_channels
, "Expose all channels the device can use.");
79 MODULE_AUTHOR("Jiri Slaby");
80 MODULE_AUTHOR("Nick Kossifidis");
81 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
82 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
83 MODULE_LICENSE("Dual BSD/GPL");
84 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
88 static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table
) = {
89 { PCI_VDEVICE(ATHEROS
, 0x0207) }, /* 5210 early */
90 { PCI_VDEVICE(ATHEROS
, 0x0007) }, /* 5210 */
91 { PCI_VDEVICE(ATHEROS
, 0x0011) }, /* 5311 - this is on AHB bus !*/
92 { PCI_VDEVICE(ATHEROS
, 0x0012) }, /* 5211 */
93 { PCI_VDEVICE(ATHEROS
, 0x0013) }, /* 5212 */
94 { PCI_VDEVICE(3COM_2
, 0x0013) }, /* 3com 5212 */
95 { PCI_VDEVICE(3COM
, 0x0013) }, /* 3com 3CRDAG675 5212 */
96 { PCI_VDEVICE(ATHEROS
, 0x1014) }, /* IBM minipci 5212 */
97 { PCI_VDEVICE(ATHEROS
, 0x0014) }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS
, 0x0015) }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS
, 0x0016) }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS
, 0x0017) }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS
, 0x0018) }, /* 5212 combatible */
102 { PCI_VDEVICE(ATHEROS
, 0x0019) }, /* 5212 combatible */
103 { PCI_VDEVICE(ATHEROS
, 0x001a) }, /* 2413 Griffin-lite */
104 { PCI_VDEVICE(ATHEROS
, 0x001b) }, /* 5413 Eagle */
105 { PCI_VDEVICE(ATHEROS
, 0x001c) }, /* PCI-E cards */
106 { PCI_VDEVICE(ATHEROS
, 0x001d) }, /* 2417 Nala */
109 MODULE_DEVICE_TABLE(pci
, ath5k_pci_id_table
);
112 static const struct ath5k_srev_name srev_names
[] = {
113 { "5210", AR5K_VERSION_MAC
, AR5K_SREV_AR5210
},
114 { "5311", AR5K_VERSION_MAC
, AR5K_SREV_AR5311
},
115 { "5311A", AR5K_VERSION_MAC
, AR5K_SREV_AR5311A
},
116 { "5311B", AR5K_VERSION_MAC
, AR5K_SREV_AR5311B
},
117 { "5211", AR5K_VERSION_MAC
, AR5K_SREV_AR5211
},
118 { "5212", AR5K_VERSION_MAC
, AR5K_SREV_AR5212
},
119 { "5213", AR5K_VERSION_MAC
, AR5K_SREV_AR5213
},
120 { "5213A", AR5K_VERSION_MAC
, AR5K_SREV_AR5213A
},
121 { "2413", AR5K_VERSION_MAC
, AR5K_SREV_AR2413
},
122 { "2414", AR5K_VERSION_MAC
, AR5K_SREV_AR2414
},
123 { "5424", AR5K_VERSION_MAC
, AR5K_SREV_AR5424
},
124 { "5413", AR5K_VERSION_MAC
, AR5K_SREV_AR5413
},
125 { "5414", AR5K_VERSION_MAC
, AR5K_SREV_AR5414
},
126 { "2415", AR5K_VERSION_MAC
, AR5K_SREV_AR2415
},
127 { "5416", AR5K_VERSION_MAC
, AR5K_SREV_AR5416
},
128 { "5418", AR5K_VERSION_MAC
, AR5K_SREV_AR5418
},
129 { "2425", AR5K_VERSION_MAC
, AR5K_SREV_AR2425
},
130 { "2417", AR5K_VERSION_MAC
, AR5K_SREV_AR2417
},
131 { "xxxxx", AR5K_VERSION_MAC
, AR5K_SREV_UNKNOWN
},
132 { "5110", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5110
},
133 { "5111", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5111
},
134 { "5111A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5111A
},
135 { "2111", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2111
},
136 { "5112", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112
},
137 { "5112A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112A
},
138 { "5112B", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5112B
},
139 { "2112", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112
},
140 { "2112A", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112A
},
141 { "2112B", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2112B
},
142 { "2413", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2413
},
143 { "5413", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5413
},
144 { "2316", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2316
},
145 { "2317", AR5K_VERSION_RAD
, AR5K_SREV_RAD_2317
},
146 { "5424", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5424
},
147 { "5133", AR5K_VERSION_RAD
, AR5K_SREV_RAD_5133
},
148 { "xxxxx", AR5K_VERSION_RAD
, AR5K_SREV_UNKNOWN
},
151 static const struct ieee80211_rate ath5k_rates
[] = {
153 .hw_value
= ATH5K_RATE_CODE_1M
, },
155 .hw_value
= ATH5K_RATE_CODE_2M
,
156 .hw_value_short
= ATH5K_RATE_CODE_2M
| AR5K_SET_SHORT_PREAMBLE
,
157 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
159 .hw_value
= ATH5K_RATE_CODE_5_5M
,
160 .hw_value_short
= ATH5K_RATE_CODE_5_5M
| AR5K_SET_SHORT_PREAMBLE
,
161 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
163 .hw_value
= ATH5K_RATE_CODE_11M
,
164 .hw_value_short
= ATH5K_RATE_CODE_11M
| AR5K_SET_SHORT_PREAMBLE
,
165 .flags
= IEEE80211_RATE_SHORT_PREAMBLE
},
167 .hw_value
= ATH5K_RATE_CODE_6M
,
170 .hw_value
= ATH5K_RATE_CODE_9M
,
173 .hw_value
= ATH5K_RATE_CODE_12M
,
176 .hw_value
= ATH5K_RATE_CODE_18M
,
179 .hw_value
= ATH5K_RATE_CODE_24M
,
182 .hw_value
= ATH5K_RATE_CODE_36M
,
185 .hw_value
= ATH5K_RATE_CODE_48M
,
188 .hw_value
= ATH5K_RATE_CODE_54M
,
194 * Prototypes - PCI stack related functions
196 static int __devinit
ath5k_pci_probe(struct pci_dev
*pdev
,
197 const struct pci_device_id
*id
);
198 static void __devexit
ath5k_pci_remove(struct pci_dev
*pdev
);
199 #ifdef CONFIG_PM_SLEEP
200 static int ath5k_pci_suspend(struct device
*dev
);
201 static int ath5k_pci_resume(struct device
*dev
);
203 static SIMPLE_DEV_PM_OPS(ath5k_pm_ops
, ath5k_pci_suspend
, ath5k_pci_resume
);
204 #define ATH5K_PM_OPS (&ath5k_pm_ops)
206 #define ATH5K_PM_OPS NULL
207 #endif /* CONFIG_PM_SLEEP */
209 static struct pci_driver ath5k_pci_driver
= {
210 .name
= KBUILD_MODNAME
,
211 .id_table
= ath5k_pci_id_table
,
212 .probe
= ath5k_pci_probe
,
213 .remove
= __devexit_p(ath5k_pci_remove
),
214 .driver
.pm
= ATH5K_PM_OPS
,
220 * Prototypes - MAC 802.11 stack related functions
222 static int ath5k_tx(struct ieee80211_hw
*hw
, struct sk_buff
*skb
);
223 static int ath5k_tx_queue(struct ieee80211_hw
*hw
, struct sk_buff
*skb
,
224 struct ath5k_txq
*txq
);
225 static int ath5k_reset(struct ath5k_softc
*sc
, struct ieee80211_channel
*chan
);
226 static int ath5k_start(struct ieee80211_hw
*hw
);
227 static void ath5k_stop(struct ieee80211_hw
*hw
);
228 static int ath5k_add_interface(struct ieee80211_hw
*hw
,
229 struct ieee80211_vif
*vif
);
230 static void ath5k_remove_interface(struct ieee80211_hw
*hw
,
231 struct ieee80211_vif
*vif
);
232 static int ath5k_config(struct ieee80211_hw
*hw
, u32 changed
);
233 static u64
ath5k_prepare_multicast(struct ieee80211_hw
*hw
,
234 struct netdev_hw_addr_list
*mc_list
);
235 static void ath5k_configure_filter(struct ieee80211_hw
*hw
,
236 unsigned int changed_flags
,
237 unsigned int *new_flags
,
239 static int ath5k_set_key(struct ieee80211_hw
*hw
,
240 enum set_key_cmd cmd
,
241 struct ieee80211_vif
*vif
, struct ieee80211_sta
*sta
,
242 struct ieee80211_key_conf
*key
);
243 static int ath5k_get_stats(struct ieee80211_hw
*hw
,
244 struct ieee80211_low_level_stats
*stats
);
245 static int ath5k_get_survey(struct ieee80211_hw
*hw
,
246 int idx
, struct survey_info
*survey
);
247 static u64
ath5k_get_tsf(struct ieee80211_hw
*hw
);
248 static void ath5k_set_tsf(struct ieee80211_hw
*hw
, u64 tsf
);
249 static void ath5k_reset_tsf(struct ieee80211_hw
*hw
);
250 static int ath5k_beacon_update(struct ieee80211_hw
*hw
,
251 struct ieee80211_vif
*vif
);
252 static void ath5k_bss_info_changed(struct ieee80211_hw
*hw
,
253 struct ieee80211_vif
*vif
,
254 struct ieee80211_bss_conf
*bss_conf
,
256 static void ath5k_sw_scan_start(struct ieee80211_hw
*hw
);
257 static void ath5k_sw_scan_complete(struct ieee80211_hw
*hw
);
258 static void ath5k_set_coverage_class(struct ieee80211_hw
*hw
,
261 static const struct ieee80211_ops ath5k_hw_ops
= {
263 .start
= ath5k_start
,
265 .add_interface
= ath5k_add_interface
,
266 .remove_interface
= ath5k_remove_interface
,
267 .config
= ath5k_config
,
268 .prepare_multicast
= ath5k_prepare_multicast
,
269 .configure_filter
= ath5k_configure_filter
,
270 .set_key
= ath5k_set_key
,
271 .get_stats
= ath5k_get_stats
,
272 .get_survey
= ath5k_get_survey
,
274 .get_tsf
= ath5k_get_tsf
,
275 .set_tsf
= ath5k_set_tsf
,
276 .reset_tsf
= ath5k_reset_tsf
,
277 .bss_info_changed
= ath5k_bss_info_changed
,
278 .sw_scan_start
= ath5k_sw_scan_start
,
279 .sw_scan_complete
= ath5k_sw_scan_complete
,
280 .set_coverage_class
= ath5k_set_coverage_class
,
284 * Prototypes - Internal functions
287 static int ath5k_attach(struct pci_dev
*pdev
,
288 struct ieee80211_hw
*hw
);
289 static void ath5k_detach(struct pci_dev
*pdev
,
290 struct ieee80211_hw
*hw
);
291 /* Channel/mode setup */
292 static inline short ath5k_ieee2mhz(short chan
);
293 static unsigned int ath5k_copy_channels(struct ath5k_hw
*ah
,
294 struct ieee80211_channel
*channels
,
297 static int ath5k_setup_bands(struct ieee80211_hw
*hw
);
298 static int ath5k_chan_set(struct ath5k_softc
*sc
,
299 struct ieee80211_channel
*chan
);
300 static void ath5k_setcurmode(struct ath5k_softc
*sc
,
302 static void ath5k_mode_setup(struct ath5k_softc
*sc
);
304 /* Descriptor setup */
305 static int ath5k_desc_alloc(struct ath5k_softc
*sc
,
306 struct pci_dev
*pdev
);
307 static void ath5k_desc_free(struct ath5k_softc
*sc
,
308 struct pci_dev
*pdev
);
310 static int ath5k_rxbuf_setup(struct ath5k_softc
*sc
,
311 struct ath5k_buf
*bf
);
312 static int ath5k_txbuf_setup(struct ath5k_softc
*sc
,
313 struct ath5k_buf
*bf
,
314 struct ath5k_txq
*txq
, int padsize
);
316 static inline void ath5k_txbuf_free_skb(struct ath5k_softc
*sc
,
317 struct ath5k_buf
*bf
)
322 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, bf
->skb
->len
,
324 dev_kfree_skb_any(bf
->skb
);
327 bf
->desc
->ds_data
= 0;
330 static inline void ath5k_rxbuf_free_skb(struct ath5k_softc
*sc
,
331 struct ath5k_buf
*bf
)
333 struct ath5k_hw
*ah
= sc
->ah
;
334 struct ath_common
*common
= ath5k_hw_common(ah
);
339 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, common
->rx_bufsize
,
341 dev_kfree_skb_any(bf
->skb
);
344 bf
->desc
->ds_data
= 0;
349 static struct ath5k_txq
*ath5k_txq_setup(struct ath5k_softc
*sc
,
350 int qtype
, int subtype
);
351 static int ath5k_beaconq_setup(struct ath5k_hw
*ah
);
352 static int ath5k_beaconq_config(struct ath5k_softc
*sc
);
353 static void ath5k_txq_drainq(struct ath5k_softc
*sc
,
354 struct ath5k_txq
*txq
);
355 static void ath5k_txq_cleanup(struct ath5k_softc
*sc
);
356 static void ath5k_txq_release(struct ath5k_softc
*sc
);
358 static int ath5k_rx_start(struct ath5k_softc
*sc
);
359 static void ath5k_rx_stop(struct ath5k_softc
*sc
);
360 static unsigned int ath5k_rx_decrypted(struct ath5k_softc
*sc
,
362 struct ath5k_rx_status
*rs
);
363 static void ath5k_tasklet_rx(unsigned long data
);
365 static void ath5k_tx_processq(struct ath5k_softc
*sc
,
366 struct ath5k_txq
*txq
);
367 static void ath5k_tasklet_tx(unsigned long data
);
368 /* Beacon handling */
369 static int ath5k_beacon_setup(struct ath5k_softc
*sc
,
370 struct ath5k_buf
*bf
);
371 static void ath5k_beacon_send(struct ath5k_softc
*sc
);
372 static void ath5k_beacon_config(struct ath5k_softc
*sc
);
373 static void ath5k_beacon_update_timers(struct ath5k_softc
*sc
, u64 bc_tsf
);
374 static void ath5k_tasklet_beacon(unsigned long data
);
375 static void ath5k_tasklet_ani(unsigned long data
);
377 static inline u64
ath5k_extend_tsf(struct ath5k_hw
*ah
, u32 rstamp
)
379 u64 tsf
= ath5k_hw_get_tsf64(ah
);
381 if ((tsf
& 0x7fff) < rstamp
)
384 return (tsf
& ~0x7fff) | rstamp
;
387 /* Interrupt handling */
388 static int ath5k_init(struct ath5k_softc
*sc
);
389 static int ath5k_stop_locked(struct ath5k_softc
*sc
);
390 static int ath5k_stop_hw(struct ath5k_softc
*sc
);
391 static irqreturn_t
ath5k_intr(int irq
, void *dev_id
);
392 static void ath5k_reset_work(struct work_struct
*work
);
394 static void ath5k_tasklet_calibrate(unsigned long data
);
397 * Module init/exit functions
406 ret
= pci_register_driver(&ath5k_pci_driver
);
408 printk(KERN_ERR
"ath5k_pci: can't register pci driver\n");
418 pci_unregister_driver(&ath5k_pci_driver
);
420 ath5k_debug_finish();
423 module_init(init_ath5k_pci
);
424 module_exit(exit_ath5k_pci
);
427 /********************\
428 * PCI Initialization *
429 \********************/
432 ath5k_chip_name(enum ath5k_srev_type type
, u_int16_t val
)
434 const char *name
= "xxxxx";
437 for (i
= 0; i
< ARRAY_SIZE(srev_names
); i
++) {
438 if (srev_names
[i
].sr_type
!= type
)
441 if ((val
& 0xf0) == srev_names
[i
].sr_val
)
442 name
= srev_names
[i
].sr_name
;
444 if ((val
& 0xff) == srev_names
[i
].sr_val
) {
445 name
= srev_names
[i
].sr_name
;
452 static unsigned int ath5k_ioread32(void *hw_priv
, u32 reg_offset
)
454 struct ath5k_hw
*ah
= (struct ath5k_hw
*) hw_priv
;
455 return ath5k_hw_reg_read(ah
, reg_offset
);
458 static void ath5k_iowrite32(void *hw_priv
, u32 val
, u32 reg_offset
)
460 struct ath5k_hw
*ah
= (struct ath5k_hw
*) hw_priv
;
461 ath5k_hw_reg_write(ah
, val
, reg_offset
);
464 static const struct ath_ops ath5k_common_ops
= {
465 .read
= ath5k_ioread32
,
466 .write
= ath5k_iowrite32
,
470 ath5k_pci_probe(struct pci_dev
*pdev
,
471 const struct pci_device_id
*id
)
474 struct ath5k_softc
*sc
;
475 struct ath_common
*common
;
476 struct ieee80211_hw
*hw
;
481 * L0s needs to be disabled on all ath5k cards.
483 * For distributions shipping with CONFIG_PCIEASPM (this will be enabled
484 * by default in the future in 2.6.36) this will also mean both L1 and
485 * L0s will be disabled when a pre 1.1 PCIe device is detected. We do
486 * know L1 works correctly even for all ath5k pre 1.1 PCIe devices
487 * though but cannot currently undue the effect of a blacklist, for
488 * details you can read pcie_aspm_sanity_check() and see how it adjusts
489 * the device link capability.
491 * It may be possible in the future to implement some PCI API to allow
492 * drivers to override blacklists for pre 1.1 PCIe but for now it is
493 * best to accept that both L0s and L1 will be disabled completely for
494 * distributions shipping with CONFIG_PCIEASPM rather than having this
495 * issue present. Motivation for adding this new API will be to help
496 * with power consumption for some of these devices.
498 pci_disable_link_state(pdev
, PCIE_LINK_STATE_L0S
);
500 ret
= pci_enable_device(pdev
);
502 dev_err(&pdev
->dev
, "can't enable device\n");
506 /* XXX 32-bit addressing only */
507 ret
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
509 dev_err(&pdev
->dev
, "32-bit DMA not available\n");
514 * Cache line size is used to size and align various
515 * structures used to communicate with the hardware.
517 pci_read_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, &csz
);
520 * Linux 2.4.18 (at least) writes the cache line size
521 * register as a 16-bit wide register which is wrong.
522 * We must have this setup properly for rx buffer
523 * DMA to work so force a reasonable value here if it
526 csz
= L1_CACHE_BYTES
>> 2;
527 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, csz
);
530 * The default setting of latency timer yields poor results,
531 * set it to the value used by other systems. It may be worth
532 * tweaking this setting more.
534 pci_write_config_byte(pdev
, PCI_LATENCY_TIMER
, 0xa8);
536 /* Enable bus mastering */
537 pci_set_master(pdev
);
540 * Disable the RETRY_TIMEOUT register (0x41) to keep
541 * PCI Tx retries from interfering with C3 CPU state.
543 pci_write_config_byte(pdev
, 0x41, 0);
545 ret
= pci_request_region(pdev
, 0, "ath5k");
547 dev_err(&pdev
->dev
, "cannot reserve PCI memory region\n");
551 mem
= pci_iomap(pdev
, 0, 0);
553 dev_err(&pdev
->dev
, "cannot remap PCI memory region\n") ;
559 * Allocate hw (mac80211 main struct)
560 * and hw->priv (driver private data)
562 hw
= ieee80211_alloc_hw(sizeof(*sc
), &ath5k_hw_ops
);
564 dev_err(&pdev
->dev
, "cannot allocate ieee80211_hw\n");
569 dev_info(&pdev
->dev
, "registered as '%s'\n", wiphy_name(hw
->wiphy
));
571 /* Initialize driver private data */
572 SET_IEEE80211_DEV(hw
, &pdev
->dev
);
573 hw
->flags
= IEEE80211_HW_RX_INCLUDES_FCS
|
574 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING
|
575 IEEE80211_HW_SIGNAL_DBM
;
577 hw
->wiphy
->interface_modes
=
578 BIT(NL80211_IFTYPE_AP
) |
579 BIT(NL80211_IFTYPE_STATION
) |
580 BIT(NL80211_IFTYPE_ADHOC
) |
581 BIT(NL80211_IFTYPE_MESH_POINT
);
583 hw
->extra_tx_headroom
= 2;
584 hw
->channel_change_time
= 5000;
589 ath5k_debug_init_device(sc
);
592 * Mark the device as detached to avoid processing
593 * interrupts until setup is complete.
595 __set_bit(ATH_STAT_INVALID
, sc
->status
);
597 sc
->iobase
= mem
; /* So we can unmap it on detach */
598 sc
->opmode
= NL80211_IFTYPE_STATION
;
600 mutex_init(&sc
->lock
);
601 spin_lock_init(&sc
->rxbuflock
);
602 spin_lock_init(&sc
->txbuflock
);
603 spin_lock_init(&sc
->block
);
605 /* Set private data */
606 pci_set_drvdata(pdev
, sc
);
608 /* Setup interrupt handler */
609 ret
= request_irq(pdev
->irq
, ath5k_intr
, IRQF_SHARED
, "ath", sc
);
611 ATH5K_ERR(sc
, "request_irq failed\n");
615 /*If we passed the test malloc a ath5k_hw struct*/
616 sc
->ah
= kzalloc(sizeof(struct ath5k_hw
), GFP_KERNEL
);
619 ATH5K_ERR(sc
, "out of memory\n");
624 sc
->ah
->ah_iobase
= sc
->iobase
;
625 common
= ath5k_hw_common(sc
->ah
);
626 common
->ops
= &ath5k_common_ops
;
629 common
->cachelsz
= csz
<< 2; /* convert to bytes */
631 /* Initialize device */
632 ret
= ath5k_hw_attach(sc
);
637 /* set up multi-rate retry capabilities */
638 if (sc
->ah
->ah_version
== AR5K_AR5212
) {
640 hw
->max_rate_tries
= 11;
643 /* Finish private driver data initialization */
644 ret
= ath5k_attach(pdev
, hw
);
648 ATH5K_INFO(sc
, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
649 ath5k_chip_name(AR5K_VERSION_MAC
, sc
->ah
->ah_mac_srev
),
651 sc
->ah
->ah_phy_revision
);
653 if (!sc
->ah
->ah_single_chip
) {
654 /* Single chip radio (!RF5111) */
655 if (sc
->ah
->ah_radio_5ghz_revision
&&
656 !sc
->ah
->ah_radio_2ghz_revision
) {
657 /* No 5GHz support -> report 2GHz radio */
658 if (!test_bit(AR5K_MODE_11A
,
659 sc
->ah
->ah_capabilities
.cap_mode
)) {
660 ATH5K_INFO(sc
, "RF%s 2GHz radio found (0x%x)\n",
661 ath5k_chip_name(AR5K_VERSION_RAD
,
662 sc
->ah
->ah_radio_5ghz_revision
),
663 sc
->ah
->ah_radio_5ghz_revision
);
664 /* No 2GHz support (5110 and some
665 * 5Ghz only cards) -> report 5Ghz radio */
666 } else if (!test_bit(AR5K_MODE_11B
,
667 sc
->ah
->ah_capabilities
.cap_mode
)) {
668 ATH5K_INFO(sc
, "RF%s 5GHz radio found (0x%x)\n",
669 ath5k_chip_name(AR5K_VERSION_RAD
,
670 sc
->ah
->ah_radio_5ghz_revision
),
671 sc
->ah
->ah_radio_5ghz_revision
);
672 /* Multiband radio */
674 ATH5K_INFO(sc
, "RF%s multiband radio found"
676 ath5k_chip_name(AR5K_VERSION_RAD
,
677 sc
->ah
->ah_radio_5ghz_revision
),
678 sc
->ah
->ah_radio_5ghz_revision
);
681 /* Multi chip radio (RF5111 - RF2111) ->
682 * report both 2GHz/5GHz radios */
683 else if (sc
->ah
->ah_radio_5ghz_revision
&&
684 sc
->ah
->ah_radio_2ghz_revision
){
685 ATH5K_INFO(sc
, "RF%s 5GHz radio found (0x%x)\n",
686 ath5k_chip_name(AR5K_VERSION_RAD
,
687 sc
->ah
->ah_radio_5ghz_revision
),
688 sc
->ah
->ah_radio_5ghz_revision
);
689 ATH5K_INFO(sc
, "RF%s 2GHz radio found (0x%x)\n",
690 ath5k_chip_name(AR5K_VERSION_RAD
,
691 sc
->ah
->ah_radio_2ghz_revision
),
692 sc
->ah
->ah_radio_2ghz_revision
);
697 /* ready to process interrupts */
698 __clear_bit(ATH_STAT_INVALID
, sc
->status
);
702 ath5k_hw_detach(sc
->ah
);
704 free_irq(pdev
->irq
, sc
);
708 ieee80211_free_hw(hw
);
710 pci_iounmap(pdev
, mem
);
712 pci_release_region(pdev
, 0);
714 pci_disable_device(pdev
);
719 static void __devexit
720 ath5k_pci_remove(struct pci_dev
*pdev
)
722 struct ath5k_softc
*sc
= pci_get_drvdata(pdev
);
724 ath5k_debug_finish_device(sc
);
725 ath5k_detach(pdev
, sc
->hw
);
726 ath5k_hw_detach(sc
->ah
);
728 free_irq(pdev
->irq
, sc
);
729 pci_iounmap(pdev
, sc
->iobase
);
730 pci_release_region(pdev
, 0);
731 pci_disable_device(pdev
);
732 ieee80211_free_hw(sc
->hw
);
735 #ifdef CONFIG_PM_SLEEP
736 static int ath5k_pci_suspend(struct device
*dev
)
738 struct ath5k_softc
*sc
= pci_get_drvdata(to_pci_dev(dev
));
744 static int ath5k_pci_resume(struct device
*dev
)
746 struct pci_dev
*pdev
= to_pci_dev(dev
);
747 struct ath5k_softc
*sc
= pci_get_drvdata(pdev
);
750 * Suspend/Resume resets the PCI configuration space, so we have to
751 * re-disable the RETRY_TIMEOUT register (0x41) to keep
752 * PCI Tx retries from interfering with C3 CPU state
754 pci_write_config_byte(pdev
, 0x41, 0);
756 ath5k_led_enable(sc
);
759 #endif /* CONFIG_PM_SLEEP */
762 /***********************\
763 * Driver Initialization *
764 \***********************/
766 static int ath5k_reg_notifier(struct wiphy
*wiphy
, struct regulatory_request
*request
)
768 struct ieee80211_hw
*hw
= wiphy_to_ieee80211_hw(wiphy
);
769 struct ath5k_softc
*sc
= hw
->priv
;
770 struct ath_regulatory
*regulatory
= ath5k_hw_regulatory(sc
->ah
);
772 return ath_reg_notifier_apply(wiphy
, request
, regulatory
);
776 ath5k_attach(struct pci_dev
*pdev
, struct ieee80211_hw
*hw
)
778 struct ath5k_softc
*sc
= hw
->priv
;
779 struct ath5k_hw
*ah
= sc
->ah
;
780 struct ath_regulatory
*regulatory
= ath5k_hw_regulatory(ah
);
781 u8 mac
[ETH_ALEN
] = {};
784 ATH5K_DBG(sc
, ATH5K_DEBUG_ANY
, "devid 0x%x\n", pdev
->device
);
787 * Check if the MAC has multi-rate retry support.
788 * We do this by trying to setup a fake extended
789 * descriptor. MAC's that don't have support will
790 * return false w/o doing anything. MAC's that do
791 * support it will return true w/o doing anything.
793 ret
= ath5k_hw_setup_mrr_tx_desc(ah
, NULL
, 0, 0, 0, 0, 0, 0);
798 __set_bit(ATH_STAT_MRRETRY
, sc
->status
);
801 * Collect the channel list. The 802.11 layer
802 * is resposible for filtering this list based
803 * on settings like the phy mode and regulatory
804 * domain restrictions.
806 ret
= ath5k_setup_bands(hw
);
808 ATH5K_ERR(sc
, "can't get channels\n");
812 /* NB: setup here so ath5k_rate_update is happy */
813 if (test_bit(AR5K_MODE_11A
, ah
->ah_modes
))
814 ath5k_setcurmode(sc
, AR5K_MODE_11A
);
816 ath5k_setcurmode(sc
, AR5K_MODE_11B
);
819 * Allocate tx+rx descriptors and populate the lists.
821 ret
= ath5k_desc_alloc(sc
, pdev
);
823 ATH5K_ERR(sc
, "can't allocate descriptors\n");
828 * Allocate hardware transmit queues: one queue for
829 * beacon frames and one data queue for each QoS
830 * priority. Note that hw functions handle reseting
831 * these queues at the needed time.
833 ret
= ath5k_beaconq_setup(ah
);
835 ATH5K_ERR(sc
, "can't setup a beacon xmit queue\n");
839 sc
->cabq
= ath5k_txq_setup(sc
, AR5K_TX_QUEUE_CAB
, 0);
840 if (IS_ERR(sc
->cabq
)) {
841 ATH5K_ERR(sc
, "can't setup cab queue\n");
842 ret
= PTR_ERR(sc
->cabq
);
846 sc
->txq
= ath5k_txq_setup(sc
, AR5K_TX_QUEUE_DATA
, AR5K_WME_AC_BK
);
847 if (IS_ERR(sc
->txq
)) {
848 ATH5K_ERR(sc
, "can't setup xmit queue\n");
849 ret
= PTR_ERR(sc
->txq
);
853 tasklet_init(&sc
->rxtq
, ath5k_tasklet_rx
, (unsigned long)sc
);
854 tasklet_init(&sc
->txtq
, ath5k_tasklet_tx
, (unsigned long)sc
);
855 tasklet_init(&sc
->calib
, ath5k_tasklet_calibrate
, (unsigned long)sc
);
856 tasklet_init(&sc
->beacontq
, ath5k_tasklet_beacon
, (unsigned long)sc
);
857 tasklet_init(&sc
->ani_tasklet
, ath5k_tasklet_ani
, (unsigned long)sc
);
859 INIT_WORK(&sc
->reset_work
, ath5k_reset_work
);
861 ret
= ath5k_eeprom_read_mac(ah
, mac
);
863 ATH5K_ERR(sc
, "unable to read address from EEPROM: 0x%04x\n",
868 SET_IEEE80211_PERM_ADDR(hw
, mac
);
869 /* All MAC address bits matter for ACKs */
870 memcpy(sc
->bssidmask
, ath_bcast_mac
, ETH_ALEN
);
871 ath5k_hw_set_bssid_mask(sc
->ah
, sc
->bssidmask
);
873 regulatory
->current_rd
= ah
->ah_capabilities
.cap_eeprom
.ee_regdomain
;
874 ret
= ath_regd_init(regulatory
, hw
->wiphy
, ath5k_reg_notifier
);
876 ATH5K_ERR(sc
, "can't initialize regulatory system\n");
880 ret
= ieee80211_register_hw(hw
);
882 ATH5K_ERR(sc
, "can't register ieee80211 hw\n");
886 if (!ath_is_world_regd(regulatory
))
887 regulatory_hint(hw
->wiphy
, regulatory
->alpha2
);
891 ath5k_sysfs_register(sc
);
895 ath5k_txq_release(sc
);
897 ath5k_hw_release_tx_queue(ah
, sc
->bhalq
);
899 ath5k_desc_free(sc
, pdev
);
905 ath5k_detach(struct pci_dev
*pdev
, struct ieee80211_hw
*hw
)
907 struct ath5k_softc
*sc
= hw
->priv
;
910 * NB: the order of these is important:
911 * o call the 802.11 layer before detaching ath5k_hw to
912 * insure callbacks into the driver to delete global
913 * key cache entries can be handled
914 * o reclaim the tx queue data structures after calling
915 * the 802.11 layer as we'll get called back to reclaim
916 * node state and potentially want to use them
917 * o to cleanup the tx queues the hal is called, so detach
919 * XXX: ??? detach ath5k_hw ???
920 * Other than that, it's straightforward...
922 ieee80211_unregister_hw(hw
);
923 ath5k_desc_free(sc
, pdev
);
924 ath5k_txq_release(sc
);
925 ath5k_hw_release_tx_queue(sc
->ah
, sc
->bhalq
);
926 ath5k_unregister_leds(sc
);
928 ath5k_sysfs_unregister(sc
);
930 * NB: can't reclaim these until after ieee80211_ifdetach
931 * returns because we'll get called back to reclaim node
932 * state and potentially want to use them.
939 /********************\
940 * Channel/mode setup *
941 \********************/
944 * Convert IEEE channel number to MHz frequency.
947 ath5k_ieee2mhz(short chan
)
949 if (chan
<= 14 || chan
>= 27)
950 return ieee80211chan2mhz(chan
);
952 return 2212 + chan
* 20;
956 * Returns true for the channel numbers used without all_channels modparam.
958 static bool ath5k_is_standard_channel(short chan
)
960 return ((chan
<= 14) ||
962 ((chan
& 3) == 0 && chan
>= 36 && chan
<= 64) ||
964 ((chan
& 3) == 0 && chan
>= 100 && chan
<= 140) ||
966 ((chan
& 3) == 1 && chan
>= 149 && chan
<= 165));
970 ath5k_copy_channels(struct ath5k_hw
*ah
,
971 struct ieee80211_channel
*channels
,
975 unsigned int i
, count
, size
, chfreq
, freq
, ch
;
977 if (!test_bit(mode
, ah
->ah_modes
))
982 case AR5K_MODE_11A_TURBO
:
983 /* 1..220, but 2GHz frequencies are filtered by check_channel */
985 chfreq
= CHANNEL_5GHZ
;
989 case AR5K_MODE_11G_TURBO
:
991 chfreq
= CHANNEL_2GHZ
;
994 ATH5K_WARN(ah
->ah_sc
, "bad mode, not copying channels\n");
998 for (i
= 0, count
= 0; i
< size
&& max
> 0; i
++) {
1000 freq
= ath5k_ieee2mhz(ch
);
1002 /* Check if channel is supported by the chipset */
1003 if (!ath5k_channel_ok(ah
, freq
, chfreq
))
1006 if (!modparam_all_channels
&& !ath5k_is_standard_channel(ch
))
1009 /* Write channel info and increment counter */
1010 channels
[count
].center_freq
= freq
;
1011 channels
[count
].band
= (chfreq
== CHANNEL_2GHZ
) ?
1012 IEEE80211_BAND_2GHZ
: IEEE80211_BAND_5GHZ
;
1016 channels
[count
].hw_value
= chfreq
| CHANNEL_OFDM
;
1018 case AR5K_MODE_11A_TURBO
:
1019 case AR5K_MODE_11G_TURBO
:
1020 channels
[count
].hw_value
= chfreq
|
1021 CHANNEL_OFDM
| CHANNEL_TURBO
;
1024 channels
[count
].hw_value
= CHANNEL_B
;
1035 ath5k_setup_rate_idx(struct ath5k_softc
*sc
, struct ieee80211_supported_band
*b
)
1039 for (i
= 0; i
< AR5K_MAX_RATES
; i
++)
1040 sc
->rate_idx
[b
->band
][i
] = -1;
1042 for (i
= 0; i
< b
->n_bitrates
; i
++) {
1043 sc
->rate_idx
[b
->band
][b
->bitrates
[i
].hw_value
] = i
;
1044 if (b
->bitrates
[i
].hw_value_short
)
1045 sc
->rate_idx
[b
->band
][b
->bitrates
[i
].hw_value_short
] = i
;
1050 ath5k_setup_bands(struct ieee80211_hw
*hw
)
1052 struct ath5k_softc
*sc
= hw
->priv
;
1053 struct ath5k_hw
*ah
= sc
->ah
;
1054 struct ieee80211_supported_band
*sband
;
1055 int max_c
, count_c
= 0;
1058 BUILD_BUG_ON(ARRAY_SIZE(sc
->sbands
) < IEEE80211_NUM_BANDS
);
1059 max_c
= ARRAY_SIZE(sc
->channels
);
1062 sband
= &sc
->sbands
[IEEE80211_BAND_2GHZ
];
1063 sband
->band
= IEEE80211_BAND_2GHZ
;
1064 sband
->bitrates
= &sc
->rates
[IEEE80211_BAND_2GHZ
][0];
1066 if (test_bit(AR5K_MODE_11G
, sc
->ah
->ah_capabilities
.cap_mode
)) {
1068 memcpy(sband
->bitrates
, &ath5k_rates
[0],
1069 sizeof(struct ieee80211_rate
) * 12);
1070 sband
->n_bitrates
= 12;
1072 sband
->channels
= sc
->channels
;
1073 sband
->n_channels
= ath5k_copy_channels(ah
, sband
->channels
,
1074 AR5K_MODE_11G
, max_c
);
1076 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = sband
;
1077 count_c
= sband
->n_channels
;
1079 } else if (test_bit(AR5K_MODE_11B
, sc
->ah
->ah_capabilities
.cap_mode
)) {
1081 memcpy(sband
->bitrates
, &ath5k_rates
[0],
1082 sizeof(struct ieee80211_rate
) * 4);
1083 sband
->n_bitrates
= 4;
1085 /* 5211 only supports B rates and uses 4bit rate codes
1086 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
1089 if (ah
->ah_version
== AR5K_AR5211
) {
1090 for (i
= 0; i
< 4; i
++) {
1091 sband
->bitrates
[i
].hw_value
=
1092 sband
->bitrates
[i
].hw_value
& 0xF;
1093 sband
->bitrates
[i
].hw_value_short
=
1094 sband
->bitrates
[i
].hw_value_short
& 0xF;
1098 sband
->channels
= sc
->channels
;
1099 sband
->n_channels
= ath5k_copy_channels(ah
, sband
->channels
,
1100 AR5K_MODE_11B
, max_c
);
1102 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = sband
;
1103 count_c
= sband
->n_channels
;
1106 ath5k_setup_rate_idx(sc
, sband
);
1108 /* 5GHz band, A mode */
1109 if (test_bit(AR5K_MODE_11A
, sc
->ah
->ah_capabilities
.cap_mode
)) {
1110 sband
= &sc
->sbands
[IEEE80211_BAND_5GHZ
];
1111 sband
->band
= IEEE80211_BAND_5GHZ
;
1112 sband
->bitrates
= &sc
->rates
[IEEE80211_BAND_5GHZ
][0];
1114 memcpy(sband
->bitrates
, &ath5k_rates
[4],
1115 sizeof(struct ieee80211_rate
) * 8);
1116 sband
->n_bitrates
= 8;
1118 sband
->channels
= &sc
->channels
[count_c
];
1119 sband
->n_channels
= ath5k_copy_channels(ah
, sband
->channels
,
1120 AR5K_MODE_11A
, max_c
);
1122 hw
->wiphy
->bands
[IEEE80211_BAND_5GHZ
] = sband
;
1124 ath5k_setup_rate_idx(sc
, sband
);
1126 ath5k_debug_dump_bands(sc
);
1132 * Set/change channels. We always reset the chip.
1133 * To accomplish this we must first cleanup any pending DMA,
1134 * then restart stuff after a la ath5k_init.
1136 * Called with sc->lock.
1139 ath5k_chan_set(struct ath5k_softc
*sc
, struct ieee80211_channel
*chan
)
1141 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
,
1142 "channel set, resetting (%u -> %u MHz)\n",
1143 sc
->curchan
->center_freq
, chan
->center_freq
);
1146 * To switch channels clear any pending DMA operations;
1147 * wait long enough for the RX fifo to drain, reset the
1148 * hardware at the new frequency, and then re-enable
1149 * the relevant bits of the h/w.
1151 return ath5k_reset(sc
, chan
);
1155 ath5k_setcurmode(struct ath5k_softc
*sc
, unsigned int mode
)
1159 if (mode
== AR5K_MODE_11A
) {
1160 sc
->curband
= &sc
->sbands
[IEEE80211_BAND_5GHZ
];
1162 sc
->curband
= &sc
->sbands
[IEEE80211_BAND_2GHZ
];
1167 ath5k_mode_setup(struct ath5k_softc
*sc
)
1169 struct ath5k_hw
*ah
= sc
->ah
;
1172 /* configure rx filter */
1173 rfilt
= sc
->filter_flags
;
1174 ath5k_hw_set_rx_filter(ah
, rfilt
);
1176 if (ath5k_hw_hasbssidmask(ah
))
1177 ath5k_hw_set_bssid_mask(ah
, sc
->bssidmask
);
1179 /* configure operational mode */
1180 ath5k_hw_set_opmode(ah
, sc
->opmode
);
1182 ATH5K_DBG(sc
, ATH5K_DEBUG_MODE
, "mode setup opmode %d\n", sc
->opmode
);
1183 ATH5K_DBG(sc
, ATH5K_DEBUG_MODE
, "RX filter 0x%x\n", rfilt
);
1187 ath5k_hw_to_driver_rix(struct ath5k_softc
*sc
, int hw_rix
)
1191 /* return base rate on errors */
1192 if (WARN(hw_rix
< 0 || hw_rix
>= AR5K_MAX_RATES
,
1193 "hw_rix out of bounds: %x\n", hw_rix
))
1196 rix
= sc
->rate_idx
[sc
->curband
->band
][hw_rix
];
1197 if (WARN(rix
< 0, "invalid hw_rix: %x\n", hw_rix
))
1208 struct sk_buff
*ath5k_rx_skb_alloc(struct ath5k_softc
*sc
, dma_addr_t
*skb_addr
)
1210 struct ath_common
*common
= ath5k_hw_common(sc
->ah
);
1211 struct sk_buff
*skb
;
1214 * Allocate buffer with headroom_needed space for the
1215 * fake physical layer header at the start.
1217 skb
= ath_rxbuf_alloc(common
,
1222 ATH5K_ERR(sc
, "can't alloc skbuff of size %u\n",
1223 common
->rx_bufsize
);
1227 *skb_addr
= pci_map_single(sc
->pdev
,
1228 skb
->data
, common
->rx_bufsize
,
1229 PCI_DMA_FROMDEVICE
);
1230 if (unlikely(pci_dma_mapping_error(sc
->pdev
, *skb_addr
))) {
1231 ATH5K_ERR(sc
, "%s: DMA mapping failed\n", __func__
);
1239 ath5k_rxbuf_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
)
1241 struct ath5k_hw
*ah
= sc
->ah
;
1242 struct sk_buff
*skb
= bf
->skb
;
1243 struct ath5k_desc
*ds
;
1247 skb
= ath5k_rx_skb_alloc(sc
, &bf
->skbaddr
);
1254 * Setup descriptors. For receive we always terminate
1255 * the descriptor list with a self-linked entry so we'll
1256 * not get overrun under high load (as can happen with a
1257 * 5212 when ANI processing enables PHY error frames).
1259 * To ensure the last descriptor is self-linked we create
1260 * each descriptor as self-linked and add it to the end. As
1261 * each additional descriptor is added the previous self-linked
1262 * entry is "fixed" naturally. This should be safe even
1263 * if DMA is happening. When processing RX interrupts we
1264 * never remove/process the last, self-linked, entry on the
1265 * descriptor list. This ensures the hardware always has
1266 * someplace to write a new frame.
1269 ds
->ds_link
= bf
->daddr
; /* link to self */
1270 ds
->ds_data
= bf
->skbaddr
;
1271 ret
= ath5k_hw_setup_rx_desc(ah
, ds
, ah
->common
.rx_bufsize
, 0);
1273 ATH5K_ERR(sc
, "%s: could not setup RX desc\n", __func__
);
1277 if (sc
->rxlink
!= NULL
)
1278 *sc
->rxlink
= bf
->daddr
;
1279 sc
->rxlink
= &ds
->ds_link
;
1283 static enum ath5k_pkt_type
get_hw_packet_type(struct sk_buff
*skb
)
1285 struct ieee80211_hdr
*hdr
;
1286 enum ath5k_pkt_type htype
;
1289 hdr
= (struct ieee80211_hdr
*)skb
->data
;
1290 fc
= hdr
->frame_control
;
1292 if (ieee80211_is_beacon(fc
))
1293 htype
= AR5K_PKT_TYPE_BEACON
;
1294 else if (ieee80211_is_probe_resp(fc
))
1295 htype
= AR5K_PKT_TYPE_PROBE_RESP
;
1296 else if (ieee80211_is_atim(fc
))
1297 htype
= AR5K_PKT_TYPE_ATIM
;
1298 else if (ieee80211_is_pspoll(fc
))
1299 htype
= AR5K_PKT_TYPE_PSPOLL
;
1301 htype
= AR5K_PKT_TYPE_NORMAL
;
1307 ath5k_txbuf_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
,
1308 struct ath5k_txq
*txq
, int padsize
)
1310 struct ath5k_hw
*ah
= sc
->ah
;
1311 struct ath5k_desc
*ds
= bf
->desc
;
1312 struct sk_buff
*skb
= bf
->skb
;
1313 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
1314 unsigned int pktlen
, flags
, keyidx
= AR5K_TXKEYIX_INVALID
;
1315 struct ieee80211_rate
*rate
;
1316 unsigned int mrr_rate
[3], mrr_tries
[3];
1323 flags
= AR5K_TXDESC_INTREQ
| AR5K_TXDESC_CLRDMASK
;
1325 /* XXX endianness */
1326 bf
->skbaddr
= pci_map_single(sc
->pdev
, skb
->data
, skb
->len
,
1329 rate
= ieee80211_get_tx_rate(sc
->hw
, info
);
1331 if (info
->flags
& IEEE80211_TX_CTL_NO_ACK
)
1332 flags
|= AR5K_TXDESC_NOACK
;
1334 rc_flags
= info
->control
.rates
[0].flags
;
1335 hw_rate
= (rc_flags
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
) ?
1336 rate
->hw_value_short
: rate
->hw_value
;
1340 /* FIXME: If we are in g mode and rate is a CCK rate
1341 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1342 * from tx power (value is in dB units already) */
1343 if (info
->control
.hw_key
) {
1344 keyidx
= info
->control
.hw_key
->hw_key_idx
;
1345 pktlen
+= info
->control
.hw_key
->icv_len
;
1347 if (rc_flags
& IEEE80211_TX_RC_USE_RTS_CTS
) {
1348 flags
|= AR5K_TXDESC_RTSENA
;
1349 cts_rate
= ieee80211_get_rts_cts_rate(sc
->hw
, info
)->hw_value
;
1350 duration
= le16_to_cpu(ieee80211_rts_duration(sc
->hw
,
1351 sc
->vif
, pktlen
, info
));
1353 if (rc_flags
& IEEE80211_TX_RC_USE_CTS_PROTECT
) {
1354 flags
|= AR5K_TXDESC_CTSENA
;
1355 cts_rate
= ieee80211_get_rts_cts_rate(sc
->hw
, info
)->hw_value
;
1356 duration
= le16_to_cpu(ieee80211_ctstoself_duration(sc
->hw
,
1357 sc
->vif
, pktlen
, info
));
1359 ret
= ah
->ah_setup_tx_desc(ah
, ds
, pktlen
,
1360 ieee80211_get_hdrlen_from_skb(skb
), padsize
,
1361 get_hw_packet_type(skb
),
1362 (sc
->power_level
* 2),
1364 info
->control
.rates
[0].count
, keyidx
, ah
->ah_tx_ant
, flags
,
1365 cts_rate
, duration
);
1369 memset(mrr_rate
, 0, sizeof(mrr_rate
));
1370 memset(mrr_tries
, 0, sizeof(mrr_tries
));
1371 for (i
= 0; i
< 3; i
++) {
1372 rate
= ieee80211_get_alt_retry_rate(sc
->hw
, info
, i
);
1376 mrr_rate
[i
] = rate
->hw_value
;
1377 mrr_tries
[i
] = info
->control
.rates
[i
+ 1].count
;
1380 ath5k_hw_setup_mrr_tx_desc(ah
, ds
,
1381 mrr_rate
[0], mrr_tries
[0],
1382 mrr_rate
[1], mrr_tries
[1],
1383 mrr_rate
[2], mrr_tries
[2]);
1386 ds
->ds_data
= bf
->skbaddr
;
1388 spin_lock_bh(&txq
->lock
);
1389 list_add_tail(&bf
->list
, &txq
->q
);
1390 if (txq
->link
== NULL
) /* is this first packet? */
1391 ath5k_hw_set_txdp(ah
, txq
->qnum
, bf
->daddr
);
1392 else /* no, so only link it */
1393 *txq
->link
= bf
->daddr
;
1395 txq
->link
= &ds
->ds_link
;
1396 ath5k_hw_start_tx_dma(ah
, txq
->qnum
);
1398 spin_unlock_bh(&txq
->lock
);
1402 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
, PCI_DMA_TODEVICE
);
1406 /*******************\
1407 * Descriptors setup *
1408 \*******************/
1411 ath5k_desc_alloc(struct ath5k_softc
*sc
, struct pci_dev
*pdev
)
1413 struct ath5k_desc
*ds
;
1414 struct ath5k_buf
*bf
;
1419 /* allocate descriptors */
1420 sc
->desc_len
= sizeof(struct ath5k_desc
) *
1421 (ATH_TXBUF
+ ATH_RXBUF
+ ATH_BCBUF
+ 1);
1422 sc
->desc
= pci_alloc_consistent(pdev
, sc
->desc_len
, &sc
->desc_daddr
);
1423 if (sc
->desc
== NULL
) {
1424 ATH5K_ERR(sc
, "can't allocate descriptors\n");
1429 da
= sc
->desc_daddr
;
1430 ATH5K_DBG(sc
, ATH5K_DEBUG_ANY
, "DMA map: %p (%zu) -> %llx\n",
1431 ds
, sc
->desc_len
, (unsigned long long)sc
->desc_daddr
);
1433 bf
= kcalloc(1 + ATH_TXBUF
+ ATH_RXBUF
+ ATH_BCBUF
,
1434 sizeof(struct ath5k_buf
), GFP_KERNEL
);
1436 ATH5K_ERR(sc
, "can't allocate bufptr\n");
1442 INIT_LIST_HEAD(&sc
->rxbuf
);
1443 for (i
= 0; i
< ATH_RXBUF
; i
++, bf
++, ds
++, da
+= sizeof(*ds
)) {
1446 list_add_tail(&bf
->list
, &sc
->rxbuf
);
1449 INIT_LIST_HEAD(&sc
->txbuf
);
1450 sc
->txbuf_len
= ATH_TXBUF
;
1451 for (i
= 0; i
< ATH_TXBUF
; i
++, bf
++, ds
++,
1452 da
+= sizeof(*ds
)) {
1455 list_add_tail(&bf
->list
, &sc
->txbuf
);
1465 pci_free_consistent(pdev
, sc
->desc_len
, sc
->desc
, sc
->desc_daddr
);
1472 ath5k_desc_free(struct ath5k_softc
*sc
, struct pci_dev
*pdev
)
1474 struct ath5k_buf
*bf
;
1476 ath5k_txbuf_free_skb(sc
, sc
->bbuf
);
1477 list_for_each_entry(bf
, &sc
->txbuf
, list
)
1478 ath5k_txbuf_free_skb(sc
, bf
);
1479 list_for_each_entry(bf
, &sc
->rxbuf
, list
)
1480 ath5k_rxbuf_free_skb(sc
, bf
);
1482 /* Free memory associated with all descriptors */
1483 pci_free_consistent(pdev
, sc
->desc_len
, sc
->desc
, sc
->desc_daddr
);
1500 static struct ath5k_txq
*
1501 ath5k_txq_setup(struct ath5k_softc
*sc
,
1502 int qtype
, int subtype
)
1504 struct ath5k_hw
*ah
= sc
->ah
;
1505 struct ath5k_txq
*txq
;
1506 struct ath5k_txq_info qi
= {
1507 .tqi_subtype
= subtype
,
1508 .tqi_aifs
= AR5K_TXQ_USEDEFAULT
,
1509 .tqi_cw_min
= AR5K_TXQ_USEDEFAULT
,
1510 .tqi_cw_max
= AR5K_TXQ_USEDEFAULT
1515 * Enable interrupts only for EOL and DESC conditions.
1516 * We mark tx descriptors to receive a DESC interrupt
1517 * when a tx queue gets deep; otherwise waiting for the
1518 * EOL to reap descriptors. Note that this is done to
1519 * reduce interrupt load and this only defers reaping
1520 * descriptors, never transmitting frames. Aside from
1521 * reducing interrupts this also permits more concurrency.
1522 * The only potential downside is if the tx queue backs
1523 * up in which case the top half of the kernel may backup
1524 * due to a lack of tx descriptors.
1526 qi
.tqi_flags
= AR5K_TXQ_FLAG_TXEOLINT_ENABLE
|
1527 AR5K_TXQ_FLAG_TXDESCINT_ENABLE
;
1528 qnum
= ath5k_hw_setup_tx_queue(ah
, qtype
, &qi
);
1531 * NB: don't print a message, this happens
1532 * normally on parts with too few tx queues
1534 return ERR_PTR(qnum
);
1536 if (qnum
>= ARRAY_SIZE(sc
->txqs
)) {
1537 ATH5K_ERR(sc
, "hw qnum %u out of range, max %tu!\n",
1538 qnum
, ARRAY_SIZE(sc
->txqs
));
1539 ath5k_hw_release_tx_queue(ah
, qnum
);
1540 return ERR_PTR(-EINVAL
);
1542 txq
= &sc
->txqs
[qnum
];
1546 INIT_LIST_HEAD(&txq
->q
);
1547 spin_lock_init(&txq
->lock
);
1550 return &sc
->txqs
[qnum
];
1554 ath5k_beaconq_setup(struct ath5k_hw
*ah
)
1556 struct ath5k_txq_info qi
= {
1557 .tqi_aifs
= AR5K_TXQ_USEDEFAULT
,
1558 .tqi_cw_min
= AR5K_TXQ_USEDEFAULT
,
1559 .tqi_cw_max
= AR5K_TXQ_USEDEFAULT
,
1560 /* NB: for dynamic turbo, don't enable any other interrupts */
1561 .tqi_flags
= AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1564 return ath5k_hw_setup_tx_queue(ah
, AR5K_TX_QUEUE_BEACON
, &qi
);
1568 ath5k_beaconq_config(struct ath5k_softc
*sc
)
1570 struct ath5k_hw
*ah
= sc
->ah
;
1571 struct ath5k_txq_info qi
;
1574 ret
= ath5k_hw_get_tx_queueprops(ah
, sc
->bhalq
, &qi
);
1578 if (sc
->opmode
== NL80211_IFTYPE_AP
||
1579 sc
->opmode
== NL80211_IFTYPE_MESH_POINT
) {
1581 * Always burst out beacon and CAB traffic
1582 * (aifs = cwmin = cwmax = 0)
1587 } else if (sc
->opmode
== NL80211_IFTYPE_ADHOC
) {
1589 * Adhoc mode; backoff between 0 and (2 * cw_min).
1593 qi
.tqi_cw_max
= 2 * ah
->ah_cw_min
;
1596 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
1597 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1598 qi
.tqi_aifs
, qi
.tqi_cw_min
, qi
.tqi_cw_max
);
1600 ret
= ath5k_hw_set_tx_queueprops(ah
, sc
->bhalq
, &qi
);
1602 ATH5K_ERR(sc
, "%s: unable to update parameters for beacon "
1603 "hardware queue!\n", __func__
);
1606 ret
= ath5k_hw_reset_tx_queue(ah
, sc
->bhalq
); /* push to h/w */
1610 /* reconfigure cabq with ready time to 80% of beacon_interval */
1611 ret
= ath5k_hw_get_tx_queueprops(ah
, AR5K_TX_QUEUE_ID_CAB
, &qi
);
1615 qi
.tqi_ready_time
= (sc
->bintval
* 80) / 100;
1616 ret
= ath5k_hw_set_tx_queueprops(ah
, AR5K_TX_QUEUE_ID_CAB
, &qi
);
1620 ret
= ath5k_hw_reset_tx_queue(ah
, AR5K_TX_QUEUE_ID_CAB
);
1626 ath5k_txq_drainq(struct ath5k_softc
*sc
, struct ath5k_txq
*txq
)
1628 struct ath5k_buf
*bf
, *bf0
;
1631 * NB: this assumes output has been stopped and
1632 * we do not need to block ath5k_tx_tasklet
1634 spin_lock_bh(&txq
->lock
);
1635 list_for_each_entry_safe(bf
, bf0
, &txq
->q
, list
) {
1636 ath5k_debug_printtxbuf(sc
, bf
);
1638 ath5k_txbuf_free_skb(sc
, bf
);
1640 spin_lock_bh(&sc
->txbuflock
);
1641 list_move_tail(&bf
->list
, &sc
->txbuf
);
1643 spin_unlock_bh(&sc
->txbuflock
);
1646 spin_unlock_bh(&txq
->lock
);
1650 * Drain the transmit queues and reclaim resources.
1653 ath5k_txq_cleanup(struct ath5k_softc
*sc
)
1655 struct ath5k_hw
*ah
= sc
->ah
;
1658 /* XXX return value */
1659 if (likely(!test_bit(ATH_STAT_INVALID
, sc
->status
))) {
1660 /* don't touch the hardware if marked invalid */
1661 ath5k_hw_stop_tx_dma(ah
, sc
->bhalq
);
1662 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "beacon queue %x\n",
1663 ath5k_hw_get_txdp(ah
, sc
->bhalq
));
1664 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++)
1665 if (sc
->txqs
[i
].setup
) {
1666 ath5k_hw_stop_tx_dma(ah
, sc
->txqs
[i
].qnum
);
1667 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "txq [%u] %x, "
1670 ath5k_hw_get_txdp(ah
,
1676 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++)
1677 if (sc
->txqs
[i
].setup
)
1678 ath5k_txq_drainq(sc
, &sc
->txqs
[i
]);
1682 ath5k_txq_release(struct ath5k_softc
*sc
)
1684 struct ath5k_txq
*txq
= sc
->txqs
;
1687 for (i
= 0; i
< ARRAY_SIZE(sc
->txqs
); i
++, txq
++)
1689 ath5k_hw_release_tx_queue(sc
->ah
, txq
->qnum
);
1702 * Enable the receive h/w following a reset.
1705 ath5k_rx_start(struct ath5k_softc
*sc
)
1707 struct ath5k_hw
*ah
= sc
->ah
;
1708 struct ath_common
*common
= ath5k_hw_common(ah
);
1709 struct ath5k_buf
*bf
;
1712 common
->rx_bufsize
= roundup(IEEE80211_MAX_LEN
, common
->cachelsz
);
1714 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "cachelsz %u rx_bufsize %u\n",
1715 common
->cachelsz
, common
->rx_bufsize
);
1717 spin_lock_bh(&sc
->rxbuflock
);
1719 list_for_each_entry(bf
, &sc
->rxbuf
, list
) {
1720 ret
= ath5k_rxbuf_setup(sc
, bf
);
1722 spin_unlock_bh(&sc
->rxbuflock
);
1726 bf
= list_first_entry(&sc
->rxbuf
, struct ath5k_buf
, list
);
1727 ath5k_hw_set_rxdp(ah
, bf
->daddr
);
1728 spin_unlock_bh(&sc
->rxbuflock
);
1730 ath5k_hw_start_rx_dma(ah
); /* enable recv descriptors */
1731 ath5k_mode_setup(sc
); /* set filters, etc. */
1732 ath5k_hw_start_rx_pcu(ah
); /* re-enable PCU/DMA engine */
1740 * Disable the receive h/w in preparation for a reset.
1743 ath5k_rx_stop(struct ath5k_softc
*sc
)
1745 struct ath5k_hw
*ah
= sc
->ah
;
1747 ath5k_hw_stop_rx_pcu(ah
); /* disable PCU */
1748 ath5k_hw_set_rx_filter(ah
, 0); /* clear recv filter */
1749 ath5k_hw_stop_rx_dma(ah
); /* disable DMA engine */
1751 ath5k_debug_printrxbuffs(sc
, ah
);
1755 ath5k_rx_decrypted(struct ath5k_softc
*sc
, struct sk_buff
*skb
,
1756 struct ath5k_rx_status
*rs
)
1758 struct ath5k_hw
*ah
= sc
->ah
;
1759 struct ath_common
*common
= ath5k_hw_common(ah
);
1760 struct ieee80211_hdr
*hdr
= (void *)skb
->data
;
1761 unsigned int keyix
, hlen
;
1763 if (!(rs
->rs_status
& AR5K_RXERR_DECRYPT
) &&
1764 rs
->rs_keyix
!= AR5K_RXKEYIX_INVALID
)
1765 return RX_FLAG_DECRYPTED
;
1767 /* Apparently when a default key is used to decrypt the packet
1768 the hw does not set the index used to decrypt. In such cases
1769 get the index from the packet. */
1770 hlen
= ieee80211_hdrlen(hdr
->frame_control
);
1771 if (ieee80211_has_protected(hdr
->frame_control
) &&
1772 !(rs
->rs_status
& AR5K_RXERR_DECRYPT
) &&
1773 skb
->len
>= hlen
+ 4) {
1774 keyix
= skb
->data
[hlen
+ 3] >> 6;
1776 if (test_bit(keyix
, common
->keymap
))
1777 return RX_FLAG_DECRYPTED
;
1785 ath5k_check_ibss_tsf(struct ath5k_softc
*sc
, struct sk_buff
*skb
,
1786 struct ieee80211_rx_status
*rxs
)
1788 struct ath_common
*common
= ath5k_hw_common(sc
->ah
);
1791 struct ieee80211_mgmt
*mgmt
= (struct ieee80211_mgmt
*)skb
->data
;
1793 if (ieee80211_is_beacon(mgmt
->frame_control
) &&
1794 le16_to_cpu(mgmt
->u
.beacon
.capab_info
) & WLAN_CAPABILITY_IBSS
&&
1795 memcmp(mgmt
->bssid
, common
->curbssid
, ETH_ALEN
) == 0) {
1797 * Received an IBSS beacon with the same BSSID. Hardware *must*
1798 * have updated the local TSF. We have to work around various
1799 * hardware bugs, though...
1801 tsf
= ath5k_hw_get_tsf64(sc
->ah
);
1802 bc_tstamp
= le64_to_cpu(mgmt
->u
.beacon
.timestamp
);
1803 hw_tu
= TSF_TO_TU(tsf
);
1805 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
1806 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1807 (unsigned long long)bc_tstamp
,
1808 (unsigned long long)rxs
->mactime
,
1809 (unsigned long long)(rxs
->mactime
- bc_tstamp
),
1810 (unsigned long long)tsf
);
1813 * Sometimes the HW will give us a wrong tstamp in the rx
1814 * status, causing the timestamp extension to go wrong.
1815 * (This seems to happen especially with beacon frames bigger
1816 * than 78 byte (incl. FCS))
1817 * But we know that the receive timestamp must be later than the
1818 * timestamp of the beacon since HW must have synced to that.
1820 * NOTE: here we assume mactime to be after the frame was
1821 * received, not like mac80211 which defines it at the start.
1823 if (bc_tstamp
> rxs
->mactime
) {
1824 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
1825 "fixing mactime from %llx to %llx\n",
1826 (unsigned long long)rxs
->mactime
,
1827 (unsigned long long)tsf
);
1832 * Local TSF might have moved higher than our beacon timers,
1833 * in that case we have to update them to continue sending
1834 * beacons. This also takes care of synchronizing beacon sending
1835 * times with other stations.
1837 if (hw_tu
>= sc
->nexttbtt
)
1838 ath5k_beacon_update_timers(sc
, bc_tstamp
);
1843 ath5k_update_beacon_rssi(struct ath5k_softc
*sc
, struct sk_buff
*skb
, int rssi
)
1845 struct ieee80211_mgmt
*mgmt
= (struct ieee80211_mgmt
*)skb
->data
;
1846 struct ath5k_hw
*ah
= sc
->ah
;
1847 struct ath_common
*common
= ath5k_hw_common(ah
);
1849 /* only beacons from our BSSID */
1850 if (!ieee80211_is_beacon(mgmt
->frame_control
) ||
1851 memcmp(mgmt
->bssid
, common
->curbssid
, ETH_ALEN
) != 0)
1854 ah
->ah_beacon_rssi_avg
= ath5k_moving_average(ah
->ah_beacon_rssi_avg
,
1857 /* in IBSS mode we should keep RSSI statistics per neighbour */
1858 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1862 * Compute padding position. skb must contains an IEEE 802.11 frame
1864 static int ath5k_common_padpos(struct sk_buff
*skb
)
1866 struct ieee80211_hdr
* hdr
= (struct ieee80211_hdr
*)skb
->data
;
1867 __le16 frame_control
= hdr
->frame_control
;
1870 if (ieee80211_has_a4(frame_control
)) {
1873 if (ieee80211_is_data_qos(frame_control
)) {
1874 padpos
+= IEEE80211_QOS_CTL_LEN
;
1881 * This function expects a 802.11 frame and returns the number of
1882 * bytes added, or -1 if we don't have enought header room.
1885 static int ath5k_add_padding(struct sk_buff
*skb
)
1887 int padpos
= ath5k_common_padpos(skb
);
1888 int padsize
= padpos
& 3;
1890 if (padsize
&& skb
->len
>padpos
) {
1892 if (skb_headroom(skb
) < padsize
)
1895 skb_push(skb
, padsize
);
1896 memmove(skb
->data
, skb
->data
+padsize
, padpos
);
1904 * This function expects a 802.11 frame and returns the number of
1908 static int ath5k_remove_padding(struct sk_buff
*skb
)
1910 int padpos
= ath5k_common_padpos(skb
);
1911 int padsize
= padpos
& 3;
1913 if (padsize
&& skb
->len
>=padpos
+padsize
) {
1914 memmove(skb
->data
+ padsize
, skb
->data
, padpos
);
1915 skb_pull(skb
, padsize
);
1923 ath5k_receive_frame(struct ath5k_softc
*sc
, struct sk_buff
*skb
,
1924 struct ath5k_rx_status
*rs
)
1926 struct ieee80211_rx_status
*rxs
;
1928 /* The MAC header is padded to have 32-bit boundary if the
1929 * packet payload is non-zero. The general calculation for
1930 * padsize would take into account odd header lengths:
1931 * padsize = (4 - hdrlen % 4) % 4; However, since only
1932 * even-length headers are used, padding can only be 0 or 2
1933 * bytes and we can optimize this a bit. In addition, we must
1934 * not try to remove padding from short control frames that do
1935 * not have payload. */
1936 ath5k_remove_padding(skb
);
1938 rxs
= IEEE80211_SKB_RXCB(skb
);
1941 if (unlikely(rs
->rs_status
& AR5K_RXERR_MIC
))
1942 rxs
->flag
|= RX_FLAG_MMIC_ERROR
;
1945 * always extend the mac timestamp, since this information is
1946 * also needed for proper IBSS merging.
1948 * XXX: it might be too late to do it here, since rs_tstamp is
1949 * 15bit only. that means TSF extension has to be done within
1950 * 32768usec (about 32ms). it might be necessary to move this to
1951 * the interrupt handler, like it is done in madwifi.
1953 * Unfortunately we don't know when the hardware takes the rx
1954 * timestamp (beginning of phy frame, data frame, end of rx?).
1955 * The only thing we know is that it is hardware specific...
1956 * On AR5213 it seems the rx timestamp is at the end of the
1957 * frame, but i'm not sure.
1959 * NOTE: mac80211 defines mactime at the beginning of the first
1960 * data symbol. Since we don't have any time references it's
1961 * impossible to comply to that. This affects IBSS merge only
1962 * right now, so it's not too bad...
1964 rxs
->mactime
= ath5k_extend_tsf(sc
->ah
, rs
->rs_tstamp
);
1965 rxs
->flag
|= RX_FLAG_TSFT
;
1967 rxs
->freq
= sc
->curchan
->center_freq
;
1968 rxs
->band
= sc
->curband
->band
;
1970 rxs
->signal
= sc
->ah
->ah_noise_floor
+ rs
->rs_rssi
;
1972 rxs
->antenna
= rs
->rs_antenna
;
1974 if (rs
->rs_antenna
> 0 && rs
->rs_antenna
< 5)
1975 sc
->stats
.antenna_rx
[rs
->rs_antenna
]++;
1977 sc
->stats
.antenna_rx
[0]++; /* invalid */
1979 rxs
->rate_idx
= ath5k_hw_to_driver_rix(sc
, rs
->rs_rate
);
1980 rxs
->flag
|= ath5k_rx_decrypted(sc
, skb
, rs
);
1982 if (rxs
->rate_idx
>= 0 && rs
->rs_rate
==
1983 sc
->curband
->bitrates
[rxs
->rate_idx
].hw_value_short
)
1984 rxs
->flag
|= RX_FLAG_SHORTPRE
;
1986 ath5k_debug_dump_skb(sc
, skb
, "RX ", 0);
1988 ath5k_update_beacon_rssi(sc
, skb
, rs
->rs_rssi
);
1990 /* check beacons in IBSS mode */
1991 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
)
1992 ath5k_check_ibss_tsf(sc
, skb
, rxs
);
1994 ieee80211_rx(sc
->hw
, skb
);
1997 /** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
1999 * Check if we want to further process this frame or not. Also update
2000 * statistics. Return true if we want this frame, false if not.
2003 ath5k_receive_frame_ok(struct ath5k_softc
*sc
, struct ath5k_rx_status
*rs
)
2005 sc
->stats
.rx_all_count
++;
2007 if (unlikely(rs
->rs_status
)) {
2008 if (rs
->rs_status
& AR5K_RXERR_CRC
)
2009 sc
->stats
.rxerr_crc
++;
2010 if (rs
->rs_status
& AR5K_RXERR_FIFO
)
2011 sc
->stats
.rxerr_fifo
++;
2012 if (rs
->rs_status
& AR5K_RXERR_PHY
) {
2013 sc
->stats
.rxerr_phy
++;
2014 if (rs
->rs_phyerr
> 0 && rs
->rs_phyerr
< 32)
2015 sc
->stats
.rxerr_phy_code
[rs
->rs_phyerr
]++;
2018 if (rs
->rs_status
& AR5K_RXERR_DECRYPT
) {
2020 * Decrypt error. If the error occurred
2021 * because there was no hardware key, then
2022 * let the frame through so the upper layers
2023 * can process it. This is necessary for 5210
2024 * parts which have no way to setup a ``clear''
2027 * XXX do key cache faulting
2029 sc
->stats
.rxerr_decrypt
++;
2030 if (rs
->rs_keyix
== AR5K_RXKEYIX_INVALID
&&
2031 !(rs
->rs_status
& AR5K_RXERR_CRC
))
2034 if (rs
->rs_status
& AR5K_RXERR_MIC
) {
2035 sc
->stats
.rxerr_mic
++;
2039 /* let crypto-error packets fall through in MNTR */
2040 if ((rs
->rs_status
& ~(AR5K_RXERR_DECRYPT
|AR5K_RXERR_MIC
)) ||
2041 sc
->opmode
!= NL80211_IFTYPE_MONITOR
)
2045 if (unlikely(rs
->rs_more
)) {
2046 sc
->stats
.rxerr_jumbo
++;
2053 ath5k_tasklet_rx(unsigned long data
)
2055 struct ath5k_rx_status rs
= {};
2056 struct sk_buff
*skb
, *next_skb
;
2057 dma_addr_t next_skb_addr
;
2058 struct ath5k_softc
*sc
= (void *)data
;
2059 struct ath5k_hw
*ah
= sc
->ah
;
2060 struct ath_common
*common
= ath5k_hw_common(ah
);
2061 struct ath5k_buf
*bf
;
2062 struct ath5k_desc
*ds
;
2065 spin_lock(&sc
->rxbuflock
);
2066 if (list_empty(&sc
->rxbuf
)) {
2067 ATH5K_WARN(sc
, "empty rx buf pool\n");
2071 bf
= list_first_entry(&sc
->rxbuf
, struct ath5k_buf
, list
);
2072 BUG_ON(bf
->skb
== NULL
);
2076 /* bail if HW is still using self-linked descriptor */
2077 if (ath5k_hw_get_rxdp(sc
->ah
) == bf
->daddr
)
2080 ret
= sc
->ah
->ah_proc_rx_desc(sc
->ah
, ds
, &rs
);
2081 if (unlikely(ret
== -EINPROGRESS
))
2083 else if (unlikely(ret
)) {
2084 ATH5K_ERR(sc
, "error in processing rx descriptor\n");
2085 sc
->stats
.rxerr_proc
++;
2089 if (ath5k_receive_frame_ok(sc
, &rs
)) {
2090 next_skb
= ath5k_rx_skb_alloc(sc
, &next_skb_addr
);
2093 * If we can't replace bf->skb with a new skb under
2094 * memory pressure, just skip this packet
2099 pci_unmap_single(sc
->pdev
, bf
->skbaddr
,
2101 PCI_DMA_FROMDEVICE
);
2103 skb_put(skb
, rs
.rs_datalen
);
2105 ath5k_receive_frame(sc
, skb
, &rs
);
2108 bf
->skbaddr
= next_skb_addr
;
2111 list_move_tail(&bf
->list
, &sc
->rxbuf
);
2112 } while (ath5k_rxbuf_setup(sc
, bf
) == 0);
2114 spin_unlock(&sc
->rxbuflock
);
2123 ath5k_tx_processq(struct ath5k_softc
*sc
, struct ath5k_txq
*txq
)
2125 struct ath5k_tx_status ts
= {};
2126 struct ath5k_buf
*bf
, *bf0
;
2127 struct ath5k_desc
*ds
;
2128 struct sk_buff
*skb
;
2129 struct ieee80211_tx_info
*info
;
2132 spin_lock(&txq
->lock
);
2133 list_for_each_entry_safe(bf
, bf0
, &txq
->q
, list
) {
2137 * It's possible that the hardware can say the buffer is
2138 * completed when it hasn't yet loaded the ds_link from
2139 * host memory and moved on. If there are more TX
2140 * descriptors in the queue, wait for TXDP to change
2141 * before processing this one.
2143 if (ath5k_hw_get_txdp(sc
->ah
, txq
->qnum
) == bf
->daddr
&&
2144 !list_is_last(&bf
->list
, &txq
->q
))
2147 ret
= sc
->ah
->ah_proc_tx_desc(sc
->ah
, ds
, &ts
);
2148 if (unlikely(ret
== -EINPROGRESS
))
2150 else if (unlikely(ret
)) {
2151 ATH5K_ERR(sc
, "error %d while processing queue %u\n",
2156 sc
->stats
.tx_all_count
++;
2158 info
= IEEE80211_SKB_CB(skb
);
2161 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
,
2164 ieee80211_tx_info_clear_status(info
);
2165 for (i
= 0; i
< 4; i
++) {
2166 struct ieee80211_tx_rate
*r
=
2167 &info
->status
.rates
[i
];
2169 if (ts
.ts_rate
[i
]) {
2170 r
->idx
= ath5k_hw_to_driver_rix(sc
, ts
.ts_rate
[i
]);
2171 r
->count
= ts
.ts_retry
[i
];
2178 /* count the successful attempt as well */
2179 info
->status
.rates
[ts
.ts_final_idx
].count
++;
2181 if (unlikely(ts
.ts_status
)) {
2182 sc
->stats
.ack_fail
++;
2183 if (ts
.ts_status
& AR5K_TXERR_FILT
) {
2184 info
->flags
|= IEEE80211_TX_STAT_TX_FILTERED
;
2185 sc
->stats
.txerr_filt
++;
2187 if (ts
.ts_status
& AR5K_TXERR_XRETRY
)
2188 sc
->stats
.txerr_retry
++;
2189 if (ts
.ts_status
& AR5K_TXERR_FIFO
)
2190 sc
->stats
.txerr_fifo
++;
2192 info
->flags
|= IEEE80211_TX_STAT_ACK
;
2193 info
->status
.ack_signal
= ts
.ts_rssi
;
2197 * Remove MAC header padding before giving the frame
2200 ath5k_remove_padding(skb
);
2202 if (ts
.ts_antenna
> 0 && ts
.ts_antenna
< 5)
2203 sc
->stats
.antenna_tx
[ts
.ts_antenna
]++;
2205 sc
->stats
.antenna_tx
[0]++; /* invalid */
2207 ieee80211_tx_status(sc
->hw
, skb
);
2209 spin_lock(&sc
->txbuflock
);
2210 list_move_tail(&bf
->list
, &sc
->txbuf
);
2212 spin_unlock(&sc
->txbuflock
);
2214 if (likely(list_empty(&txq
->q
)))
2216 spin_unlock(&txq
->lock
);
2217 if (sc
->txbuf_len
> ATH_TXBUF
/ 5)
2218 ieee80211_wake_queues(sc
->hw
);
2222 ath5k_tasklet_tx(unsigned long data
)
2225 struct ath5k_softc
*sc
= (void *)data
;
2227 for (i
=0; i
< AR5K_NUM_TX_QUEUES
; i
++)
2228 if (sc
->txqs
[i
].setup
&& (sc
->ah
->ah_txq_isr
& BIT(i
)))
2229 ath5k_tx_processq(sc
, &sc
->txqs
[i
]);
2238 * Setup the beacon frame for transmit.
2241 ath5k_beacon_setup(struct ath5k_softc
*sc
, struct ath5k_buf
*bf
)
2243 struct sk_buff
*skb
= bf
->skb
;
2244 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
2245 struct ath5k_hw
*ah
= sc
->ah
;
2246 struct ath5k_desc
*ds
;
2250 const int padsize
= 0;
2252 bf
->skbaddr
= pci_map_single(sc
->pdev
, skb
->data
, skb
->len
,
2254 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
, "skb %p [data %p len %u] "
2255 "skbaddr %llx\n", skb
, skb
->data
, skb
->len
,
2256 (unsigned long long)bf
->skbaddr
);
2257 if (pci_dma_mapping_error(sc
->pdev
, bf
->skbaddr
)) {
2258 ATH5K_ERR(sc
, "beacon DMA mapping failed\n");
2263 antenna
= ah
->ah_tx_ant
;
2265 flags
= AR5K_TXDESC_NOACK
;
2266 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
&& ath5k_hw_hasveol(ah
)) {
2267 ds
->ds_link
= bf
->daddr
; /* self-linked */
2268 flags
|= AR5K_TXDESC_VEOL
;
2273 * If we use multiple antennas on AP and use
2274 * the Sectored AP scenario, switch antenna every
2275 * 4 beacons to make sure everybody hears our AP.
2276 * When a client tries to associate, hw will keep
2277 * track of the tx antenna to be used for this client
2278 * automaticaly, based on ACKed packets.
2280 * Note: AP still listens and transmits RTS on the
2281 * default antenna which is supposed to be an omni.
2283 * Note2: On sectored scenarios it's possible to have
2284 * multiple antennas (1omni -the default- and 14 sectors)
2285 * so if we choose to actually support this mode we need
2286 * to allow user to set how many antennas we have and tweak
2287 * the code below to send beacons on all of them.
2289 if (ah
->ah_ant_mode
== AR5K_ANTMODE_SECTOR_AP
)
2290 antenna
= sc
->bsent
& 4 ? 2 : 1;
2293 /* FIXME: If we are in g mode and rate is a CCK rate
2294 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
2295 * from tx power (value is in dB units already) */
2296 ds
->ds_data
= bf
->skbaddr
;
2297 ret
= ah
->ah_setup_tx_desc(ah
, ds
, skb
->len
,
2298 ieee80211_get_hdrlen_from_skb(skb
), padsize
,
2299 AR5K_PKT_TYPE_BEACON
, (sc
->power_level
* 2),
2300 ieee80211_get_tx_rate(sc
->hw
, info
)->hw_value
,
2301 1, AR5K_TXKEYIX_INVALID
,
2302 antenna
, flags
, 0, 0);
2308 pci_unmap_single(sc
->pdev
, bf
->skbaddr
, skb
->len
, PCI_DMA_TODEVICE
);
2313 * Transmit a beacon frame at SWBA. Dynamic updates to the
2314 * frame contents are done as needed and the slot time is
2315 * also adjusted based on current state.
2317 * This is called from software irq context (beacontq tasklets)
2318 * or user context from ath5k_beacon_config.
2321 ath5k_beacon_send(struct ath5k_softc
*sc
)
2323 struct ath5k_buf
*bf
= sc
->bbuf
;
2324 struct ath5k_hw
*ah
= sc
->ah
;
2325 struct sk_buff
*skb
;
2327 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
, "in beacon_send\n");
2329 if (unlikely(bf
->skb
== NULL
|| sc
->opmode
== NL80211_IFTYPE_STATION
||
2330 sc
->opmode
== NL80211_IFTYPE_MONITOR
)) {
2331 ATH5K_WARN(sc
, "bf=%p bf_skb=%p\n", bf
, bf
? bf
->skb
: NULL
);
2335 * Check if the previous beacon has gone out. If
2336 * not don't don't try to post another, skip this
2337 * period and wait for the next. Missed beacons
2338 * indicate a problem and should not occur. If we
2339 * miss too many consecutive beacons reset the device.
2341 if (unlikely(ath5k_hw_num_tx_pending(ah
, sc
->bhalq
) != 0)) {
2343 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
2344 "missed %u consecutive beacons\n", sc
->bmisscount
);
2345 if (sc
->bmisscount
> 10) { /* NB: 10 is a guess */
2346 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
2347 "stuck beacon time (%u missed)\n",
2349 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
,
2350 "stuck beacon, resetting\n");
2351 ieee80211_queue_work(sc
->hw
, &sc
->reset_work
);
2355 if (unlikely(sc
->bmisscount
!= 0)) {
2356 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
2357 "resume beacon xmit after %u misses\n",
2363 * Stop any current dma and put the new frame on the queue.
2364 * This should never fail since we check above that no frames
2365 * are still pending on the queue.
2367 if (unlikely(ath5k_hw_stop_tx_dma(ah
, sc
->bhalq
))) {
2368 ATH5K_WARN(sc
, "beacon queue %u didn't start/stop ?\n", sc
->bhalq
);
2369 /* NB: hw still stops DMA, so proceed */
2372 /* refresh the beacon for AP mode */
2373 if (sc
->opmode
== NL80211_IFTYPE_AP
)
2374 ath5k_beacon_update(sc
->hw
, sc
->vif
);
2376 ath5k_hw_set_txdp(ah
, sc
->bhalq
, bf
->daddr
);
2377 ath5k_hw_start_tx_dma(ah
, sc
->bhalq
);
2378 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
, "TXDP[%u] = %llx (%p)\n",
2379 sc
->bhalq
, (unsigned long long)bf
->daddr
, bf
->desc
);
2381 skb
= ieee80211_get_buffered_bc(sc
->hw
, sc
->vif
);
2383 ath5k_tx_queue(sc
->hw
, skb
, sc
->cabq
);
2384 skb
= ieee80211_get_buffered_bc(sc
->hw
, sc
->vif
);
2392 * ath5k_beacon_update_timers - update beacon timers
2394 * @sc: struct ath5k_softc pointer we are operating on
2395 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2396 * beacon timer update based on the current HW TSF.
2398 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2399 * of a received beacon or the current local hardware TSF and write it to the
2400 * beacon timer registers.
2402 * This is called in a variety of situations, e.g. when a beacon is received,
2403 * when a TSF update has been detected, but also when an new IBSS is created or
2404 * when we otherwise know we have to update the timers, but we keep it in this
2405 * function to have it all together in one place.
2408 ath5k_beacon_update_timers(struct ath5k_softc
*sc
, u64 bc_tsf
)
2410 struct ath5k_hw
*ah
= sc
->ah
;
2411 u32 nexttbtt
, intval
, hw_tu
, bc_tu
;
2414 intval
= sc
->bintval
& AR5K_BEACON_PERIOD
;
2415 if (WARN_ON(!intval
))
2418 /* beacon TSF converted to TU */
2419 bc_tu
= TSF_TO_TU(bc_tsf
);
2421 /* current TSF converted to TU */
2422 hw_tsf
= ath5k_hw_get_tsf64(ah
);
2423 hw_tu
= TSF_TO_TU(hw_tsf
);
2426 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2429 * no beacons received, called internally.
2430 * just need to refresh timers based on HW TSF.
2432 nexttbtt
= roundup(hw_tu
+ FUDGE
, intval
);
2433 } else if (bc_tsf
== 0) {
2435 * no beacon received, probably called by ath5k_reset_tsf().
2436 * reset TSF to start with 0.
2439 intval
|= AR5K_BEACON_RESET_TSF
;
2440 } else if (bc_tsf
> hw_tsf
) {
2442 * beacon received, SW merge happend but HW TSF not yet updated.
2443 * not possible to reconfigure timers yet, but next time we
2444 * receive a beacon with the same BSSID, the hardware will
2445 * automatically update the TSF and then we need to reconfigure
2448 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2449 "need to wait for HW TSF sync\n");
2453 * most important case for beacon synchronization between STA.
2455 * beacon received and HW TSF has been already updated by HW.
2456 * update next TBTT based on the TSF of the beacon, but make
2457 * sure it is ahead of our local TSF timer.
2459 nexttbtt
= bc_tu
+ roundup(hw_tu
+ FUDGE
- bc_tu
, intval
);
2463 sc
->nexttbtt
= nexttbtt
;
2465 intval
|= AR5K_BEACON_ENA
;
2466 ath5k_hw_init_beacon(ah
, nexttbtt
, intval
);
2469 * debugging output last in order to preserve the time critical aspect
2473 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2474 "reconfigured timers based on HW TSF\n");
2475 else if (bc_tsf
== 0)
2476 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2477 "reset HW TSF and timers\n");
2479 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2480 "updated timers based on beacon TSF\n");
2482 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
,
2483 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2484 (unsigned long long) bc_tsf
,
2485 (unsigned long long) hw_tsf
, bc_tu
, hw_tu
, nexttbtt
);
2486 ATH5K_DBG_UNLIMIT(sc
, ATH5K_DEBUG_BEACON
, "intval %u %s %s\n",
2487 intval
& AR5K_BEACON_PERIOD
,
2488 intval
& AR5K_BEACON_ENA
? "AR5K_BEACON_ENA" : "",
2489 intval
& AR5K_BEACON_RESET_TSF
? "AR5K_BEACON_RESET_TSF" : "");
2494 * ath5k_beacon_config - Configure the beacon queues and interrupts
2496 * @sc: struct ath5k_softc pointer we are operating on
2498 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2499 * interrupts to detect TSF updates only.
2502 ath5k_beacon_config(struct ath5k_softc
*sc
)
2504 struct ath5k_hw
*ah
= sc
->ah
;
2505 unsigned long flags
;
2507 spin_lock_irqsave(&sc
->block
, flags
);
2509 sc
->imask
&= ~(AR5K_INT_BMISS
| AR5K_INT_SWBA
);
2511 if (sc
->enable_beacon
) {
2513 * In IBSS mode we use a self-linked tx descriptor and let the
2514 * hardware send the beacons automatically. We have to load it
2516 * We use the SWBA interrupt only to keep track of the beacon
2517 * timers in order to detect automatic TSF updates.
2519 ath5k_beaconq_config(sc
);
2521 sc
->imask
|= AR5K_INT_SWBA
;
2523 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
) {
2524 if (ath5k_hw_hasveol(ah
))
2525 ath5k_beacon_send(sc
);
2527 ath5k_beacon_update_timers(sc
, -1);
2529 ath5k_hw_stop_tx_dma(sc
->ah
, sc
->bhalq
);
2532 ath5k_hw_set_imr(ah
, sc
->imask
);
2534 spin_unlock_irqrestore(&sc
->block
, flags
);
2537 static void ath5k_tasklet_beacon(unsigned long data
)
2539 struct ath5k_softc
*sc
= (struct ath5k_softc
*) data
;
2542 * Software beacon alert--time to send a beacon.
2544 * In IBSS mode we use this interrupt just to
2545 * keep track of the next TBTT (target beacon
2546 * transmission time) in order to detect wether
2547 * automatic TSF updates happened.
2549 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
) {
2550 /* XXX: only if VEOL suppported */
2551 u64 tsf
= ath5k_hw_get_tsf64(sc
->ah
);
2552 sc
->nexttbtt
+= sc
->bintval
;
2553 ATH5K_DBG(sc
, ATH5K_DEBUG_BEACON
,
2554 "SWBA nexttbtt: %x hw_tu: %x "
2558 (unsigned long long) tsf
);
2560 spin_lock(&sc
->block
);
2561 ath5k_beacon_send(sc
);
2562 spin_unlock(&sc
->block
);
2567 /********************\
2568 * Interrupt handling *
2569 \********************/
2572 ath5k_init(struct ath5k_softc
*sc
)
2574 struct ath5k_hw
*ah
= sc
->ah
;
2577 mutex_lock(&sc
->lock
);
2579 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "mode %d\n", sc
->opmode
);
2582 * Stop anything previously setup. This is safe
2583 * no matter this is the first time through or not.
2585 ath5k_stop_locked(sc
);
2588 * The basic interface to setting the hardware in a good
2589 * state is ``reset''. On return the hardware is known to
2590 * be powered up and with interrupts disabled. This must
2591 * be followed by initialization of the appropriate bits
2592 * and then setup of the interrupt mask.
2594 sc
->curchan
= sc
->hw
->conf
.channel
;
2595 sc
->curband
= &sc
->sbands
[sc
->curchan
->band
];
2596 sc
->imask
= AR5K_INT_RXOK
| AR5K_INT_RXERR
| AR5K_INT_RXEOL
|
2597 AR5K_INT_RXORN
| AR5K_INT_TXDESC
| AR5K_INT_TXEOL
|
2598 AR5K_INT_FATAL
| AR5K_INT_GLOBAL
| AR5K_INT_MIB
;
2600 ret
= ath5k_reset(sc
, NULL
);
2604 ath5k_rfkill_hw_start(ah
);
2607 * Reset the key cache since some parts do not reset the
2608 * contents on initial power up or resume from suspend.
2610 for (i
= 0; i
< AR5K_KEYTABLE_SIZE
; i
++)
2611 ath5k_hw_reset_key(ah
, i
);
2613 ath5k_hw_set_ack_bitrate_high(ah
, true);
2617 mutex_unlock(&sc
->lock
);
2622 ath5k_stop_locked(struct ath5k_softc
*sc
)
2624 struct ath5k_hw
*ah
= sc
->ah
;
2626 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "invalid %u\n",
2627 test_bit(ATH_STAT_INVALID
, sc
->status
));
2630 * Shutdown the hardware and driver:
2631 * stop output from above
2632 * disable interrupts
2634 * turn off the radio
2635 * clear transmit machinery
2636 * clear receive machinery
2637 * drain and release tx queues
2638 * reclaim beacon resources
2639 * power down hardware
2641 * Note that some of this work is not possible if the
2642 * hardware is gone (invalid).
2644 ieee80211_stop_queues(sc
->hw
);
2646 if (!test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2648 ath5k_hw_set_imr(ah
, 0);
2649 synchronize_irq(sc
->pdev
->irq
);
2651 ath5k_txq_cleanup(sc
);
2652 if (!test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2654 ath5k_hw_phy_disable(ah
);
2660 static void stop_tasklets(struct ath5k_softc
*sc
)
2662 tasklet_kill(&sc
->rxtq
);
2663 tasklet_kill(&sc
->txtq
);
2664 tasklet_kill(&sc
->calib
);
2665 tasklet_kill(&sc
->beacontq
);
2666 tasklet_kill(&sc
->ani_tasklet
);
2670 * Stop the device, grabbing the top-level lock to protect
2671 * against concurrent entry through ath5k_init (which can happen
2672 * if another thread does a system call and the thread doing the
2673 * stop is preempted).
2676 ath5k_stop_hw(struct ath5k_softc
*sc
)
2680 mutex_lock(&sc
->lock
);
2681 ret
= ath5k_stop_locked(sc
);
2682 if (ret
== 0 && !test_bit(ATH_STAT_INVALID
, sc
->status
)) {
2684 * Don't set the card in full sleep mode!
2686 * a) When the device is in this state it must be carefully
2687 * woken up or references to registers in the PCI clock
2688 * domain may freeze the bus (and system). This varies
2689 * by chip and is mostly an issue with newer parts
2690 * (madwifi sources mentioned srev >= 0x78) that go to
2691 * sleep more quickly.
2693 * b) On older chips full sleep results a weird behaviour
2694 * during wakeup. I tested various cards with srev < 0x78
2695 * and they don't wake up after module reload, a second
2696 * module reload is needed to bring the card up again.
2698 * Until we figure out what's going on don't enable
2699 * full chip reset on any chip (this is what Legacy HAL
2700 * and Sam's HAL do anyway). Instead Perform a full reset
2701 * on the device (same as initial state after attach) and
2702 * leave it idle (keep MAC/BB on warm reset) */
2703 ret
= ath5k_hw_on_hold(sc
->ah
);
2705 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
,
2706 "putting device to sleep\n");
2708 ath5k_txbuf_free_skb(sc
, sc
->bbuf
);
2711 mutex_unlock(&sc
->lock
);
2715 ath5k_rfkill_hw_stop(sc
->ah
);
2721 ath5k_intr_calibration_poll(struct ath5k_hw
*ah
)
2723 if (time_is_before_eq_jiffies(ah
->ah_cal_next_ani
) &&
2724 !(ah
->ah_cal_mask
& AR5K_CALIBRATION_FULL
)) {
2725 /* run ANI only when full calibration is not active */
2726 ah
->ah_cal_next_ani
= jiffies
+
2727 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI
);
2728 tasklet_schedule(&ah
->ah_sc
->ani_tasklet
);
2730 } else if (time_is_before_eq_jiffies(ah
->ah_cal_next_full
)) {
2731 ah
->ah_cal_next_full
= jiffies
+
2732 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL
);
2733 tasklet_schedule(&ah
->ah_sc
->calib
);
2735 /* we could use SWI to generate enough interrupts to meet our
2736 * calibration interval requirements, if necessary:
2737 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2741 ath5k_intr(int irq
, void *dev_id
)
2743 struct ath5k_softc
*sc
= dev_id
;
2744 struct ath5k_hw
*ah
= sc
->ah
;
2745 enum ath5k_int status
;
2746 unsigned int counter
= 1000;
2748 if (unlikely(test_bit(ATH_STAT_INVALID
, sc
->status
) ||
2749 !ath5k_hw_is_intr_pending(ah
)))
2753 ath5k_hw_get_isr(ah
, &status
); /* NB: clears IRQ too */
2754 ATH5K_DBG(sc
, ATH5K_DEBUG_INTR
, "status 0x%x/0x%x\n",
2756 if (unlikely(status
& AR5K_INT_FATAL
)) {
2758 * Fatal errors are unrecoverable.
2759 * Typically these are caused by DMA errors.
2761 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
,
2762 "fatal int, resetting\n");
2763 ieee80211_queue_work(sc
->hw
, &sc
->reset_work
);
2764 } else if (unlikely(status
& AR5K_INT_RXORN
)) {
2766 * Receive buffers are full. Either the bus is busy or
2767 * the CPU is not fast enough to process all received
2769 * Older chipsets need a reset to come out of this
2770 * condition, but we treat it as RX for newer chips.
2771 * We don't know exactly which versions need a reset -
2772 * this guess is copied from the HAL.
2774 sc
->stats
.rxorn_intr
++;
2775 if (ah
->ah_mac_srev
< AR5K_SREV_AR5212
) {
2776 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
,
2777 "rx overrun, resetting\n");
2778 ieee80211_queue_work(sc
->hw
, &sc
->reset_work
);
2781 tasklet_schedule(&sc
->rxtq
);
2783 if (status
& AR5K_INT_SWBA
) {
2784 tasklet_hi_schedule(&sc
->beacontq
);
2786 if (status
& AR5K_INT_RXEOL
) {
2788 * NB: the hardware should re-read the link when
2789 * RXE bit is written, but it doesn't work at
2790 * least on older hardware revs.
2792 sc
->stats
.rxeol_intr
++;
2794 if (status
& AR5K_INT_TXURN
) {
2795 /* bump tx trigger level */
2796 ath5k_hw_update_tx_triglevel(ah
, true);
2798 if (status
& (AR5K_INT_RXOK
| AR5K_INT_RXERR
))
2799 tasklet_schedule(&sc
->rxtq
);
2800 if (status
& (AR5K_INT_TXOK
| AR5K_INT_TXDESC
2801 | AR5K_INT_TXERR
| AR5K_INT_TXEOL
))
2802 tasklet_schedule(&sc
->txtq
);
2803 if (status
& AR5K_INT_BMISS
) {
2806 if (status
& AR5K_INT_MIB
) {
2807 sc
->stats
.mib_intr
++;
2808 ath5k_hw_update_mib_counters(ah
);
2809 ath5k_ani_mib_intr(ah
);
2811 if (status
& AR5K_INT_GPIO
)
2812 tasklet_schedule(&sc
->rf_kill
.toggleq
);
2815 } while (ath5k_hw_is_intr_pending(ah
) && --counter
> 0);
2817 if (unlikely(!counter
))
2818 ATH5K_WARN(sc
, "too many interrupts, giving up for now\n");
2820 ath5k_intr_calibration_poll(ah
);
2826 * Periodically recalibrate the PHY to account
2827 * for temperature/environment changes.
2830 ath5k_tasklet_calibrate(unsigned long data
)
2832 struct ath5k_softc
*sc
= (void *)data
;
2833 struct ath5k_hw
*ah
= sc
->ah
;
2835 /* Only full calibration for now */
2836 ah
->ah_cal_mask
|= AR5K_CALIBRATION_FULL
;
2838 ATH5K_DBG(sc
, ATH5K_DEBUG_CALIBRATE
, "channel %u/%x\n",
2839 ieee80211_frequency_to_channel(sc
->curchan
->center_freq
),
2840 sc
->curchan
->hw_value
);
2842 if (ath5k_hw_gainf_calibrate(ah
) == AR5K_RFGAIN_NEED_CHANGE
) {
2844 * Rfgain is out of bounds, reset the chip
2845 * to load new gain values.
2847 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "calibration, resetting\n");
2848 ieee80211_queue_work(sc
->hw
, &sc
->reset_work
);
2850 if (ath5k_hw_phy_calibrate(ah
, sc
->curchan
))
2851 ATH5K_ERR(sc
, "calibration of channel %u failed\n",
2852 ieee80211_frequency_to_channel(
2853 sc
->curchan
->center_freq
));
2855 /* Noise floor calibration interrupts rx/tx path while I/Q calibration
2856 * doesn't. We stop the queues so that calibration doesn't interfere
2857 * with TX and don't run it as often */
2858 if (time_is_before_eq_jiffies(ah
->ah_cal_next_nf
)) {
2859 ah
->ah_cal_next_nf
= jiffies
+
2860 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF
);
2861 ieee80211_stop_queues(sc
->hw
);
2862 ath5k_hw_update_noise_floor(ah
);
2863 ieee80211_wake_queues(sc
->hw
);
2866 ah
->ah_cal_mask
&= ~AR5K_CALIBRATION_FULL
;
2871 ath5k_tasklet_ani(unsigned long data
)
2873 struct ath5k_softc
*sc
= (void *)data
;
2874 struct ath5k_hw
*ah
= sc
->ah
;
2876 ah
->ah_cal_mask
|= AR5K_CALIBRATION_ANI
;
2877 ath5k_ani_calibration(ah
);
2878 ah
->ah_cal_mask
&= ~AR5K_CALIBRATION_ANI
;
2882 /********************\
2883 * Mac80211 functions *
2884 \********************/
2887 ath5k_tx(struct ieee80211_hw
*hw
, struct sk_buff
*skb
)
2889 struct ath5k_softc
*sc
= hw
->priv
;
2891 return ath5k_tx_queue(hw
, skb
, sc
->txq
);
2894 static int ath5k_tx_queue(struct ieee80211_hw
*hw
, struct sk_buff
*skb
,
2895 struct ath5k_txq
*txq
)
2897 struct ath5k_softc
*sc
= hw
->priv
;
2898 struct ath5k_buf
*bf
;
2899 unsigned long flags
;
2902 ath5k_debug_dump_skb(sc
, skb
, "TX ", 1);
2904 if (sc
->opmode
== NL80211_IFTYPE_MONITOR
)
2905 ATH5K_DBG(sc
, ATH5K_DEBUG_XMIT
, "tx in monitor (scan?)\n");
2908 * the hardware expects the header padded to 4 byte boundaries
2909 * if this is not the case we add the padding after the header
2911 padsize
= ath5k_add_padding(skb
);
2913 ATH5K_ERR(sc
, "tx hdrlen not %%4: not enough"
2914 " headroom to pad");
2918 spin_lock_irqsave(&sc
->txbuflock
, flags
);
2919 if (list_empty(&sc
->txbuf
)) {
2920 ATH5K_ERR(sc
, "no further txbuf available, dropping packet\n");
2921 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
2922 ieee80211_stop_queue(hw
, skb_get_queue_mapping(skb
));
2925 bf
= list_first_entry(&sc
->txbuf
, struct ath5k_buf
, list
);
2926 list_del(&bf
->list
);
2928 if (list_empty(&sc
->txbuf
))
2929 ieee80211_stop_queues(hw
);
2930 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
2934 if (ath5k_txbuf_setup(sc
, bf
, txq
, padsize
)) {
2936 spin_lock_irqsave(&sc
->txbuflock
, flags
);
2937 list_add_tail(&bf
->list
, &sc
->txbuf
);
2939 spin_unlock_irqrestore(&sc
->txbuflock
, flags
);
2942 return NETDEV_TX_OK
;
2945 dev_kfree_skb_any(skb
);
2946 return NETDEV_TX_OK
;
2950 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2951 * and change to the given channel.
2953 * This should be called with sc->lock.
2956 ath5k_reset(struct ath5k_softc
*sc
, struct ieee80211_channel
*chan
)
2958 struct ath5k_hw
*ah
= sc
->ah
;
2961 ATH5K_DBG(sc
, ATH5K_DEBUG_RESET
, "resetting\n");
2963 ath5k_hw_set_imr(ah
, 0);
2964 synchronize_irq(sc
->pdev
->irq
);
2968 ath5k_txq_cleanup(sc
);
2972 sc
->curband
= &sc
->sbands
[chan
->band
];
2974 ret
= ath5k_hw_reset(ah
, sc
->opmode
, sc
->curchan
, chan
!= NULL
);
2976 ATH5K_ERR(sc
, "can't reset hardware (%d)\n", ret
);
2980 ret
= ath5k_rx_start(sc
);
2982 ATH5K_ERR(sc
, "can't start recv logic\n");
2986 ath5k_ani_init(ah
, ah
->ah_sc
->ani_state
.ani_mode
);
2988 ah
->ah_cal_next_full
= jiffies
;
2989 ah
->ah_cal_next_ani
= jiffies
;
2990 ah
->ah_cal_next_nf
= jiffies
;
2993 * Change channels and update the h/w rate map if we're switching;
2994 * e.g. 11a to 11b/g.
2996 * We may be doing a reset in response to an ioctl that changes the
2997 * channel so update any state that might change as a result.
3001 /* ath5k_chan_change(sc, c); */
3003 ath5k_beacon_config(sc
);
3004 /* intrs are enabled by ath5k_beacon_config */
3006 ieee80211_wake_queues(sc
->hw
);
3013 static void ath5k_reset_work(struct work_struct
*work
)
3015 struct ath5k_softc
*sc
= container_of(work
, struct ath5k_softc
,
3018 mutex_lock(&sc
->lock
);
3019 ath5k_reset(sc
, sc
->curchan
);
3020 mutex_unlock(&sc
->lock
);
3023 static int ath5k_start(struct ieee80211_hw
*hw
)
3025 return ath5k_init(hw
->priv
);
3028 static void ath5k_stop(struct ieee80211_hw
*hw
)
3030 ath5k_stop_hw(hw
->priv
);
3033 static int ath5k_add_interface(struct ieee80211_hw
*hw
,
3034 struct ieee80211_vif
*vif
)
3036 struct ath5k_softc
*sc
= hw
->priv
;
3039 mutex_lock(&sc
->lock
);
3047 switch (vif
->type
) {
3048 case NL80211_IFTYPE_AP
:
3049 case NL80211_IFTYPE_STATION
:
3050 case NL80211_IFTYPE_ADHOC
:
3051 case NL80211_IFTYPE_MESH_POINT
:
3052 case NL80211_IFTYPE_MONITOR
:
3053 sc
->opmode
= vif
->type
;
3060 ATH5K_DBG(sc
, ATH5K_DEBUG_MODE
, "add interface mode %d\n", sc
->opmode
);
3062 ath5k_hw_set_lladdr(sc
->ah
, vif
->addr
);
3063 ath5k_mode_setup(sc
);
3067 mutex_unlock(&sc
->lock
);
3072 ath5k_remove_interface(struct ieee80211_hw
*hw
,
3073 struct ieee80211_vif
*vif
)
3075 struct ath5k_softc
*sc
= hw
->priv
;
3076 u8 mac
[ETH_ALEN
] = {};
3078 mutex_lock(&sc
->lock
);
3082 ath5k_hw_set_lladdr(sc
->ah
, mac
);
3085 mutex_unlock(&sc
->lock
);
3089 * TODO: Phy disable/diversity etc
3092 ath5k_config(struct ieee80211_hw
*hw
, u32 changed
)
3094 struct ath5k_softc
*sc
= hw
->priv
;
3095 struct ath5k_hw
*ah
= sc
->ah
;
3096 struct ieee80211_conf
*conf
= &hw
->conf
;
3099 mutex_lock(&sc
->lock
);
3101 if (changed
& IEEE80211_CONF_CHANGE_CHANNEL
) {
3102 ret
= ath5k_chan_set(sc
, conf
->channel
);
3107 if ((changed
& IEEE80211_CONF_CHANGE_POWER
) &&
3108 (sc
->power_level
!= conf
->power_level
)) {
3109 sc
->power_level
= conf
->power_level
;
3112 ath5k_hw_set_txpower_limit(ah
, (conf
->power_level
* 2));
3116 * 1) Move this on config_interface and handle each case
3117 * separately eg. when we have only one STA vif, use
3118 * AR5K_ANTMODE_SINGLE_AP
3120 * 2) Allow the user to change antenna mode eg. when only
3121 * one antenna is present
3123 * 3) Allow the user to set default/tx antenna when possible
3125 * 4) Default mode should handle 90% of the cases, together
3126 * with fixed a/b and single AP modes we should be able to
3127 * handle 99%. Sectored modes are extreme cases and i still
3128 * haven't found a usage for them. If we decide to support them,
3129 * then we must allow the user to set how many tx antennas we
3132 ath5k_hw_set_antenna_mode(ah
, ah
->ah_ant_mode
);
3135 mutex_unlock(&sc
->lock
);
3139 static u64
ath5k_prepare_multicast(struct ieee80211_hw
*hw
,
3140 struct netdev_hw_addr_list
*mc_list
)
3144 struct netdev_hw_addr
*ha
;
3149 netdev_hw_addr_list_for_each(ha
, mc_list
) {
3150 /* calculate XOR of eight 6-bit values */
3151 val
= get_unaligned_le32(ha
->addr
+ 0);
3152 pos
= (val
>> 18) ^ (val
>> 12) ^ (val
>> 6) ^ val
;
3153 val
= get_unaligned_le32(ha
->addr
+ 3);
3154 pos
^= (val
>> 18) ^ (val
>> 12) ^ (val
>> 6) ^ val
;
3156 mfilt
[pos
/ 32] |= (1 << (pos
% 32));
3157 /* XXX: we might be able to just do this instead,
3158 * but not sure, needs testing, if we do use this we'd
3159 * neet to inform below to not reset the mcast */
3160 /* ath5k_hw_set_mcast_filterindex(ah,
3164 return ((u64
)(mfilt
[1]) << 32) | mfilt
[0];
3167 #define SUPPORTED_FIF_FLAGS \
3168 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
3169 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
3170 FIF_BCN_PRBRESP_PROMISC
3172 * o always accept unicast, broadcast, and multicast traffic
3173 * o multicast traffic for all BSSIDs will be enabled if mac80211
3175 * o maintain current state of phy ofdm or phy cck error reception.
3176 * If the hardware detects any of these type of errors then
3177 * ath5k_hw_get_rx_filter() will pass to us the respective
3178 * hardware filters to be able to receive these type of frames.
3179 * o probe request frames are accepted only when operating in
3180 * hostap, adhoc, or monitor modes
3181 * o enable promiscuous mode according to the interface state
3183 * - when operating in adhoc mode so the 802.11 layer creates
3184 * node table entries for peers,
3185 * - when operating in station mode for collecting rssi data when
3186 * the station is otherwise quiet, or
3189 static void ath5k_configure_filter(struct ieee80211_hw
*hw
,
3190 unsigned int changed_flags
,
3191 unsigned int *new_flags
,
3194 struct ath5k_softc
*sc
= hw
->priv
;
3195 struct ath5k_hw
*ah
= sc
->ah
;
3196 u32 mfilt
[2], rfilt
;
3198 mutex_lock(&sc
->lock
);
3200 mfilt
[0] = multicast
;
3201 mfilt
[1] = multicast
>> 32;
3203 /* Only deal with supported flags */
3204 changed_flags
&= SUPPORTED_FIF_FLAGS
;
3205 *new_flags
&= SUPPORTED_FIF_FLAGS
;
3207 /* If HW detects any phy or radar errors, leave those filters on.
3208 * Also, always enable Unicast, Broadcasts and Multicast
3209 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
3210 rfilt
= (ath5k_hw_get_rx_filter(ah
) & (AR5K_RX_FILTER_PHYERR
)) |
3211 (AR5K_RX_FILTER_UCAST
| AR5K_RX_FILTER_BCAST
|
3212 AR5K_RX_FILTER_MCAST
);
3214 if (changed_flags
& (FIF_PROMISC_IN_BSS
| FIF_OTHER_BSS
)) {
3215 if (*new_flags
& FIF_PROMISC_IN_BSS
) {
3216 __set_bit(ATH_STAT_PROMISC
, sc
->status
);
3218 __clear_bit(ATH_STAT_PROMISC
, sc
->status
);
3222 if (test_bit(ATH_STAT_PROMISC
, sc
->status
))
3223 rfilt
|= AR5K_RX_FILTER_PROM
;
3225 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
3226 if (*new_flags
& FIF_ALLMULTI
) {
3231 /* This is the best we can do */
3232 if (*new_flags
& (FIF_FCSFAIL
| FIF_PLCPFAIL
))
3233 rfilt
|= AR5K_RX_FILTER_PHYERR
;
3235 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
3236 * and probes for any BSSID, this needs testing */
3237 if (*new_flags
& FIF_BCN_PRBRESP_PROMISC
)
3238 rfilt
|= AR5K_RX_FILTER_BEACON
| AR5K_RX_FILTER_PROBEREQ
;
3240 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
3241 * set we should only pass on control frames for this
3242 * station. This needs testing. I believe right now this
3243 * enables *all* control frames, which is OK.. but
3244 * but we should see if we can improve on granularity */
3245 if (*new_flags
& FIF_CONTROL
)
3246 rfilt
|= AR5K_RX_FILTER_CONTROL
;
3248 /* Additional settings per mode -- this is per ath5k */
3250 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
3252 switch (sc
->opmode
) {
3253 case NL80211_IFTYPE_MESH_POINT
:
3254 case NL80211_IFTYPE_MONITOR
:
3255 rfilt
|= AR5K_RX_FILTER_CONTROL
|
3256 AR5K_RX_FILTER_BEACON
|
3257 AR5K_RX_FILTER_PROBEREQ
|
3258 AR5K_RX_FILTER_PROM
;
3260 case NL80211_IFTYPE_AP
:
3261 case NL80211_IFTYPE_ADHOC
:
3262 rfilt
|= AR5K_RX_FILTER_PROBEREQ
|
3263 AR5K_RX_FILTER_BEACON
;
3265 case NL80211_IFTYPE_STATION
:
3267 rfilt
|= AR5K_RX_FILTER_BEACON
;
3273 ath5k_hw_set_rx_filter(ah
, rfilt
);
3275 /* Set multicast bits */
3276 ath5k_hw_set_mcast_filter(ah
, mfilt
[0], mfilt
[1]);
3277 /* Set the cached hw filter flags, this will alter actually
3279 sc
->filter_flags
= rfilt
;
3281 mutex_unlock(&sc
->lock
);
3285 ath5k_set_key(struct ieee80211_hw
*hw
, enum set_key_cmd cmd
,
3286 struct ieee80211_vif
*vif
, struct ieee80211_sta
*sta
,
3287 struct ieee80211_key_conf
*key
)
3289 struct ath5k_softc
*sc
= hw
->priv
;
3290 struct ath5k_hw
*ah
= sc
->ah
;
3291 struct ath_common
*common
= ath5k_hw_common(ah
);
3294 if (modparam_nohwcrypt
)
3297 if (sc
->opmode
== NL80211_IFTYPE_AP
)
3300 switch (key
->cipher
) {
3301 case WLAN_CIPHER_SUITE_WEP40
:
3302 case WLAN_CIPHER_SUITE_WEP104
:
3303 case WLAN_CIPHER_SUITE_TKIP
:
3305 case WLAN_CIPHER_SUITE_CCMP
:
3306 if (sc
->ah
->ah_aes_support
)
3315 mutex_lock(&sc
->lock
);
3319 ret
= ath5k_hw_set_key(sc
->ah
, key
->keyidx
, key
,
3320 sta
? sta
->addr
: NULL
);
3322 ATH5K_ERR(sc
, "can't set the key\n");
3325 __set_bit(key
->keyidx
, common
->keymap
);
3326 key
->hw_key_idx
= key
->keyidx
;
3327 key
->flags
|= (IEEE80211_KEY_FLAG_GENERATE_IV
|
3328 IEEE80211_KEY_FLAG_GENERATE_MMIC
);
3331 ath5k_hw_reset_key(sc
->ah
, key
->keyidx
);
3332 __clear_bit(key
->keyidx
, common
->keymap
);
3341 mutex_unlock(&sc
->lock
);
3346 ath5k_get_stats(struct ieee80211_hw
*hw
,
3347 struct ieee80211_low_level_stats
*stats
)
3349 struct ath5k_softc
*sc
= hw
->priv
;
3352 ath5k_hw_update_mib_counters(sc
->ah
);
3354 stats
->dot11ACKFailureCount
= sc
->stats
.ack_fail
;
3355 stats
->dot11RTSFailureCount
= sc
->stats
.rts_fail
;
3356 stats
->dot11RTSSuccessCount
= sc
->stats
.rts_ok
;
3357 stats
->dot11FCSErrorCount
= sc
->stats
.fcs_error
;
3362 static int ath5k_get_survey(struct ieee80211_hw
*hw
, int idx
,
3363 struct survey_info
*survey
)
3365 struct ath5k_softc
*sc
= hw
->priv
;
3366 struct ieee80211_conf
*conf
= &hw
->conf
;
3371 survey
->channel
= conf
->channel
;
3372 survey
->filled
= SURVEY_INFO_NOISE_DBM
;
3373 survey
->noise
= sc
->ah
->ah_noise_floor
;
3379 ath5k_get_tsf(struct ieee80211_hw
*hw
)
3381 struct ath5k_softc
*sc
= hw
->priv
;
3383 return ath5k_hw_get_tsf64(sc
->ah
);
3387 ath5k_set_tsf(struct ieee80211_hw
*hw
, u64 tsf
)
3389 struct ath5k_softc
*sc
= hw
->priv
;
3391 ath5k_hw_set_tsf64(sc
->ah
, tsf
);
3395 ath5k_reset_tsf(struct ieee80211_hw
*hw
)
3397 struct ath5k_softc
*sc
= hw
->priv
;
3400 * in IBSS mode we need to update the beacon timers too.
3401 * this will also reset the TSF if we call it with 0
3403 if (sc
->opmode
== NL80211_IFTYPE_ADHOC
)
3404 ath5k_beacon_update_timers(sc
, 0);
3406 ath5k_hw_reset_tsf(sc
->ah
);
3410 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
3411 * this is called only once at config_bss time, for AP we do it every
3412 * SWBA interrupt so that the TIM will reflect buffered frames.
3414 * Called with the beacon lock.
3417 ath5k_beacon_update(struct ieee80211_hw
*hw
, struct ieee80211_vif
*vif
)
3420 struct ath5k_softc
*sc
= hw
->priv
;
3421 struct sk_buff
*skb
;
3423 if (WARN_ON(!vif
)) {
3428 skb
= ieee80211_beacon_get(hw
, vif
);
3435 ath5k_debug_dump_skb(sc
, skb
, "BC ", 1);
3437 ath5k_txbuf_free_skb(sc
, sc
->bbuf
);
3438 sc
->bbuf
->skb
= skb
;
3439 ret
= ath5k_beacon_setup(sc
, sc
->bbuf
);
3441 sc
->bbuf
->skb
= NULL
;
3447 set_beacon_filter(struct ieee80211_hw
*hw
, bool enable
)
3449 struct ath5k_softc
*sc
= hw
->priv
;
3450 struct ath5k_hw
*ah
= sc
->ah
;
3452 rfilt
= ath5k_hw_get_rx_filter(ah
);
3454 rfilt
|= AR5K_RX_FILTER_BEACON
;
3456 rfilt
&= ~AR5K_RX_FILTER_BEACON
;
3457 ath5k_hw_set_rx_filter(ah
, rfilt
);
3458 sc
->filter_flags
= rfilt
;
3461 static void ath5k_bss_info_changed(struct ieee80211_hw
*hw
,
3462 struct ieee80211_vif
*vif
,
3463 struct ieee80211_bss_conf
*bss_conf
,
3466 struct ath5k_softc
*sc
= hw
->priv
;
3467 struct ath5k_hw
*ah
= sc
->ah
;
3468 struct ath_common
*common
= ath5k_hw_common(ah
);
3469 unsigned long flags
;
3471 mutex_lock(&sc
->lock
);
3472 if (WARN_ON(sc
->vif
!= vif
))
3475 if (changes
& BSS_CHANGED_BSSID
) {
3476 /* Cache for later use during resets */
3477 memcpy(common
->curbssid
, bss_conf
->bssid
, ETH_ALEN
);
3479 ath5k_hw_set_associd(ah
);
3483 if (changes
& BSS_CHANGED_BEACON_INT
)
3484 sc
->bintval
= bss_conf
->beacon_int
;
3486 if (changes
& BSS_CHANGED_ASSOC
) {
3487 sc
->assoc
= bss_conf
->assoc
;
3488 if (sc
->opmode
== NL80211_IFTYPE_STATION
)
3489 set_beacon_filter(hw
, sc
->assoc
);
3490 ath5k_hw_set_ledstate(sc
->ah
, sc
->assoc
?
3491 AR5K_LED_ASSOC
: AR5K_LED_INIT
);
3492 if (bss_conf
->assoc
) {
3493 ATH5K_DBG(sc
, ATH5K_DEBUG_ANY
,
3494 "Bss Info ASSOC %d, bssid: %pM\n",
3495 bss_conf
->aid
, common
->curbssid
);
3496 common
->curaid
= bss_conf
->aid
;
3497 ath5k_hw_set_associd(ah
);
3498 /* Once ANI is available you would start it here */
3502 if (changes
& BSS_CHANGED_BEACON
) {
3503 spin_lock_irqsave(&sc
->block
, flags
);
3504 ath5k_beacon_update(hw
, vif
);
3505 spin_unlock_irqrestore(&sc
->block
, flags
);
3508 if (changes
& BSS_CHANGED_BEACON_ENABLED
)
3509 sc
->enable_beacon
= bss_conf
->enable_beacon
;
3511 if (changes
& (BSS_CHANGED_BEACON
| BSS_CHANGED_BEACON_ENABLED
|
3512 BSS_CHANGED_BEACON_INT
))
3513 ath5k_beacon_config(sc
);
3516 mutex_unlock(&sc
->lock
);
3519 static void ath5k_sw_scan_start(struct ieee80211_hw
*hw
)
3521 struct ath5k_softc
*sc
= hw
->priv
;
3523 ath5k_hw_set_ledstate(sc
->ah
, AR5K_LED_SCAN
);
3526 static void ath5k_sw_scan_complete(struct ieee80211_hw
*hw
)
3528 struct ath5k_softc
*sc
= hw
->priv
;
3529 ath5k_hw_set_ledstate(sc
->ah
, sc
->assoc
?
3530 AR5K_LED_ASSOC
: AR5K_LED_INIT
);
3534 * ath5k_set_coverage_class - Set IEEE 802.11 coverage class
3536 * @hw: struct ieee80211_hw pointer
3537 * @coverage_class: IEEE 802.11 coverage class number
3539 * Mac80211 callback. Sets slot time, ACK timeout and CTS timeout for given
3540 * coverage class. The values are persistent, they are restored after device
3543 static void ath5k_set_coverage_class(struct ieee80211_hw
*hw
, u8 coverage_class
)
3545 struct ath5k_softc
*sc
= hw
->priv
;
3547 mutex_lock(&sc
->lock
);
3548 ath5k_hw_set_coverage_class(sc
->ah
, coverage_class
);
3549 mutex_unlock(&sc
->lock
);