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Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / ath / ath5k / base.c
1 /*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
46 #include <linux/if.h>
47 #include <linux/io.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/ethtool.h>
52 #include <linux/uaccess.h>
53
54 #include <net/ieee80211_radiotap.h>
55
56 #include <asm/unaligned.h>
57
58 #include "base.h"
59 #include "reg.h"
60 #include "debug.h"
61
62 static u8 ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
63 static int modparam_nohwcrypt;
64 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
65 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
66
67 static int modparam_all_channels;
68 module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
69 MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
70
71
72 /******************\
73 * Internal defines *
74 \******************/
75
76 /* Module info */
77 MODULE_AUTHOR("Jiri Slaby");
78 MODULE_AUTHOR("Nick Kossifidis");
79 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
80 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
81 MODULE_LICENSE("Dual BSD/GPL");
82 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
83
84
85 /* Known PCI ids */
86 static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = {
87 { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
88 { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
89 { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
90 { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
91 { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
92 { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */
93 { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */
94 { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
95 { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */
96 { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
102 { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
103 { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
104 { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
105 { 0 }
106 };
107 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
108
109 /* Known SREVs */
110 static const struct ath5k_srev_name srev_names[] = {
111 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
112 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
113 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
114 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
115 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
116 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
117 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
118 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
119 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
120 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
121 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
122 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
123 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
124 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
125 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
126 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
127 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
128 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
129 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
130 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
131 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
132 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
133 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
134 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
135 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
136 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
137 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
138 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
139 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
140 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
141 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
142 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
143 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
144 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
145 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
146 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
147 };
148
149 static const struct ieee80211_rate ath5k_rates[] = {
150 { .bitrate = 10,
151 .hw_value = ATH5K_RATE_CODE_1M, },
152 { .bitrate = 20,
153 .hw_value = ATH5K_RATE_CODE_2M,
154 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
155 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
156 { .bitrate = 55,
157 .hw_value = ATH5K_RATE_CODE_5_5M,
158 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
159 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
160 { .bitrate = 110,
161 .hw_value = ATH5K_RATE_CODE_11M,
162 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
163 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
164 { .bitrate = 60,
165 .hw_value = ATH5K_RATE_CODE_6M,
166 .flags = 0 },
167 { .bitrate = 90,
168 .hw_value = ATH5K_RATE_CODE_9M,
169 .flags = 0 },
170 { .bitrate = 120,
171 .hw_value = ATH5K_RATE_CODE_12M,
172 .flags = 0 },
173 { .bitrate = 180,
174 .hw_value = ATH5K_RATE_CODE_18M,
175 .flags = 0 },
176 { .bitrate = 240,
177 .hw_value = ATH5K_RATE_CODE_24M,
178 .flags = 0 },
179 { .bitrate = 360,
180 .hw_value = ATH5K_RATE_CODE_36M,
181 .flags = 0 },
182 { .bitrate = 480,
183 .hw_value = ATH5K_RATE_CODE_48M,
184 .flags = 0 },
185 { .bitrate = 540,
186 .hw_value = ATH5K_RATE_CODE_54M,
187 .flags = 0 },
188 /* XR missing */
189 };
190
191 /*
192 * Prototypes - PCI stack related functions
193 */
194 static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
195 const struct pci_device_id *id);
196 static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
197 #ifdef CONFIG_PM
198 static int ath5k_pci_suspend(struct device *dev);
199 static int ath5k_pci_resume(struct device *dev);
200
201 SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume);
202 #define ATH5K_PM_OPS (&ath5k_pm_ops)
203 #else
204 #define ATH5K_PM_OPS NULL
205 #endif /* CONFIG_PM */
206
207 static struct pci_driver ath5k_pci_driver = {
208 .name = KBUILD_MODNAME,
209 .id_table = ath5k_pci_id_table,
210 .probe = ath5k_pci_probe,
211 .remove = __devexit_p(ath5k_pci_remove),
212 .driver.pm = ATH5K_PM_OPS,
213 };
214
215
216
217 /*
218 * Prototypes - MAC 802.11 stack related functions
219 */
220 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
221 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
222 struct ath5k_txq *txq);
223 static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan);
224 static int ath5k_reset_wake(struct ath5k_softc *sc);
225 static int ath5k_start(struct ieee80211_hw *hw);
226 static void ath5k_stop(struct ieee80211_hw *hw);
227 static int ath5k_add_interface(struct ieee80211_hw *hw,
228 struct ieee80211_vif *vif);
229 static void ath5k_remove_interface(struct ieee80211_hw *hw,
230 struct ieee80211_vif *vif);
231 static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
232 static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
233 int mc_count, struct dev_addr_list *mc_list);
234 static void ath5k_configure_filter(struct ieee80211_hw *hw,
235 unsigned int changed_flags,
236 unsigned int *new_flags,
237 u64 multicast);
238 static int ath5k_set_key(struct ieee80211_hw *hw,
239 enum set_key_cmd cmd,
240 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
241 struct ieee80211_key_conf *key);
242 static int ath5k_get_stats(struct ieee80211_hw *hw,
243 struct ieee80211_low_level_stats *stats);
244 static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
245 struct ieee80211_tx_queue_stats *stats);
246 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
247 static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
248 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
249 static int ath5k_beacon_update(struct ieee80211_hw *hw,
250 struct ieee80211_vif *vif);
251 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
252 struct ieee80211_vif *vif,
253 struct ieee80211_bss_conf *bss_conf,
254 u32 changes);
255 static void ath5k_sw_scan_start(struct ieee80211_hw *hw);
256 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw);
257 static void ath5k_set_coverage_class(struct ieee80211_hw *hw,
258 u8 coverage_class);
259
260 static const struct ieee80211_ops ath5k_hw_ops = {
261 .tx = ath5k_tx,
262 .start = ath5k_start,
263 .stop = ath5k_stop,
264 .add_interface = ath5k_add_interface,
265 .remove_interface = ath5k_remove_interface,
266 .config = ath5k_config,
267 .prepare_multicast = ath5k_prepare_multicast,
268 .configure_filter = ath5k_configure_filter,
269 .set_key = ath5k_set_key,
270 .get_stats = ath5k_get_stats,
271 .conf_tx = NULL,
272 .get_tx_stats = ath5k_get_tx_stats,
273 .get_tsf = ath5k_get_tsf,
274 .set_tsf = ath5k_set_tsf,
275 .reset_tsf = ath5k_reset_tsf,
276 .bss_info_changed = ath5k_bss_info_changed,
277 .sw_scan_start = ath5k_sw_scan_start,
278 .sw_scan_complete = ath5k_sw_scan_complete,
279 .set_coverage_class = ath5k_set_coverage_class,
280 };
281
282 /*
283 * Prototypes - Internal functions
284 */
285 /* Attach detach */
286 static int ath5k_attach(struct pci_dev *pdev,
287 struct ieee80211_hw *hw);
288 static void ath5k_detach(struct pci_dev *pdev,
289 struct ieee80211_hw *hw);
290 /* Channel/mode setup */
291 static inline short ath5k_ieee2mhz(short chan);
292 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
293 struct ieee80211_channel *channels,
294 unsigned int mode,
295 unsigned int max);
296 static int ath5k_setup_bands(struct ieee80211_hw *hw);
297 static int ath5k_chan_set(struct ath5k_softc *sc,
298 struct ieee80211_channel *chan);
299 static void ath5k_setcurmode(struct ath5k_softc *sc,
300 unsigned int mode);
301 static void ath5k_mode_setup(struct ath5k_softc *sc);
302
303 /* Descriptor setup */
304 static int ath5k_desc_alloc(struct ath5k_softc *sc,
305 struct pci_dev *pdev);
306 static void ath5k_desc_free(struct ath5k_softc *sc,
307 struct pci_dev *pdev);
308 /* Buffers setup */
309 static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
310 struct ath5k_buf *bf);
311 static int ath5k_txbuf_setup(struct ath5k_softc *sc,
312 struct ath5k_buf *bf,
313 struct ath5k_txq *txq);
314 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
315 struct ath5k_buf *bf)
316 {
317 BUG_ON(!bf);
318 if (!bf->skb)
319 return;
320 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
321 PCI_DMA_TODEVICE);
322 dev_kfree_skb_any(bf->skb);
323 bf->skb = NULL;
324 }
325
326 static inline void ath5k_rxbuf_free(struct ath5k_softc *sc,
327 struct ath5k_buf *bf)
328 {
329 struct ath5k_hw *ah = sc->ah;
330 struct ath_common *common = ath5k_hw_common(ah);
331
332 BUG_ON(!bf);
333 if (!bf->skb)
334 return;
335 pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
336 PCI_DMA_FROMDEVICE);
337 dev_kfree_skb_any(bf->skb);
338 bf->skb = NULL;
339 }
340
341
342 /* Queues setup */
343 static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
344 int qtype, int subtype);
345 static int ath5k_beaconq_setup(struct ath5k_hw *ah);
346 static int ath5k_beaconq_config(struct ath5k_softc *sc);
347 static void ath5k_txq_drainq(struct ath5k_softc *sc,
348 struct ath5k_txq *txq);
349 static void ath5k_txq_cleanup(struct ath5k_softc *sc);
350 static void ath5k_txq_release(struct ath5k_softc *sc);
351 /* Rx handling */
352 static int ath5k_rx_start(struct ath5k_softc *sc);
353 static void ath5k_rx_stop(struct ath5k_softc *sc);
354 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
355 struct ath5k_desc *ds,
356 struct sk_buff *skb,
357 struct ath5k_rx_status *rs);
358 static void ath5k_tasklet_rx(unsigned long data);
359 /* Tx handling */
360 static void ath5k_tx_processq(struct ath5k_softc *sc,
361 struct ath5k_txq *txq);
362 static void ath5k_tasklet_tx(unsigned long data);
363 /* Beacon handling */
364 static int ath5k_beacon_setup(struct ath5k_softc *sc,
365 struct ath5k_buf *bf);
366 static void ath5k_beacon_send(struct ath5k_softc *sc);
367 static void ath5k_beacon_config(struct ath5k_softc *sc);
368 static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
369 static void ath5k_tasklet_beacon(unsigned long data);
370
371 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
372 {
373 u64 tsf = ath5k_hw_get_tsf64(ah);
374
375 if ((tsf & 0x7fff) < rstamp)
376 tsf -= 0x8000;
377
378 return (tsf & ~0x7fff) | rstamp;
379 }
380
381 /* Interrupt handling */
382 static int ath5k_init(struct ath5k_softc *sc);
383 static int ath5k_stop_locked(struct ath5k_softc *sc);
384 static int ath5k_stop_hw(struct ath5k_softc *sc);
385 static irqreturn_t ath5k_intr(int irq, void *dev_id);
386 static void ath5k_tasklet_reset(unsigned long data);
387
388 static void ath5k_tasklet_calibrate(unsigned long data);
389
390 /*
391 * Module init/exit functions
392 */
393 static int __init
394 init_ath5k_pci(void)
395 {
396 int ret;
397
398 ath5k_debug_init();
399
400 ret = pci_register_driver(&ath5k_pci_driver);
401 if (ret) {
402 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
403 return ret;
404 }
405
406 return 0;
407 }
408
409 static void __exit
410 exit_ath5k_pci(void)
411 {
412 pci_unregister_driver(&ath5k_pci_driver);
413
414 ath5k_debug_finish();
415 }
416
417 module_init(init_ath5k_pci);
418 module_exit(exit_ath5k_pci);
419
420
421 /********************\
422 * PCI Initialization *
423 \********************/
424
425 static const char *
426 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
427 {
428 const char *name = "xxxxx";
429 unsigned int i;
430
431 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
432 if (srev_names[i].sr_type != type)
433 continue;
434
435 if ((val & 0xf0) == srev_names[i].sr_val)
436 name = srev_names[i].sr_name;
437
438 if ((val & 0xff) == srev_names[i].sr_val) {
439 name = srev_names[i].sr_name;
440 break;
441 }
442 }
443
444 return name;
445 }
446 static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
447 {
448 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
449 return ath5k_hw_reg_read(ah, reg_offset);
450 }
451
452 static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
453 {
454 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
455 ath5k_hw_reg_write(ah, val, reg_offset);
456 }
457
458 static const struct ath_ops ath5k_common_ops = {
459 .read = ath5k_ioread32,
460 .write = ath5k_iowrite32,
461 };
462
463 static int __devinit
464 ath5k_pci_probe(struct pci_dev *pdev,
465 const struct pci_device_id *id)
466 {
467 void __iomem *mem;
468 struct ath5k_softc *sc;
469 struct ath_common *common;
470 struct ieee80211_hw *hw;
471 int ret;
472 u8 csz;
473
474 ret = pci_enable_device(pdev);
475 if (ret) {
476 dev_err(&pdev->dev, "can't enable device\n");
477 goto err;
478 }
479
480 /* XXX 32-bit addressing only */
481 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
482 if (ret) {
483 dev_err(&pdev->dev, "32-bit DMA not available\n");
484 goto err_dis;
485 }
486
487 /*
488 * Cache line size is used to size and align various
489 * structures used to communicate with the hardware.
490 */
491 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
492 if (csz == 0) {
493 /*
494 * Linux 2.4.18 (at least) writes the cache line size
495 * register as a 16-bit wide register which is wrong.
496 * We must have this setup properly for rx buffer
497 * DMA to work so force a reasonable value here if it
498 * comes up zero.
499 */
500 csz = L1_CACHE_BYTES >> 2;
501 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
502 }
503 /*
504 * The default setting of latency timer yields poor results,
505 * set it to the value used by other systems. It may be worth
506 * tweaking this setting more.
507 */
508 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
509
510 /* Enable bus mastering */
511 pci_set_master(pdev);
512
513 /*
514 * Disable the RETRY_TIMEOUT register (0x41) to keep
515 * PCI Tx retries from interfering with C3 CPU state.
516 */
517 pci_write_config_byte(pdev, 0x41, 0);
518
519 ret = pci_request_region(pdev, 0, "ath5k");
520 if (ret) {
521 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
522 goto err_dis;
523 }
524
525 mem = pci_iomap(pdev, 0, 0);
526 if (!mem) {
527 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
528 ret = -EIO;
529 goto err_reg;
530 }
531
532 /*
533 * Allocate hw (mac80211 main struct)
534 * and hw->priv (driver private data)
535 */
536 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
537 if (hw == NULL) {
538 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
539 ret = -ENOMEM;
540 goto err_map;
541 }
542
543 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
544
545 /* Initialize driver private data */
546 SET_IEEE80211_DEV(hw, &pdev->dev);
547 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
548 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
549 IEEE80211_HW_SIGNAL_DBM |
550 IEEE80211_HW_NOISE_DBM;
551
552 hw->wiphy->interface_modes =
553 BIT(NL80211_IFTYPE_AP) |
554 BIT(NL80211_IFTYPE_STATION) |
555 BIT(NL80211_IFTYPE_ADHOC) |
556 BIT(NL80211_IFTYPE_MESH_POINT);
557
558 hw->extra_tx_headroom = 2;
559 hw->channel_change_time = 5000;
560 sc = hw->priv;
561 sc->hw = hw;
562 sc->pdev = pdev;
563
564 ath5k_debug_init_device(sc);
565
566 /*
567 * Mark the device as detached to avoid processing
568 * interrupts until setup is complete.
569 */
570 __set_bit(ATH_STAT_INVALID, sc->status);
571
572 sc->iobase = mem; /* So we can unmap it on detach */
573 sc->opmode = NL80211_IFTYPE_STATION;
574 sc->bintval = 1000;
575 mutex_init(&sc->lock);
576 spin_lock_init(&sc->rxbuflock);
577 spin_lock_init(&sc->txbuflock);
578 spin_lock_init(&sc->block);
579
580 /* Set private data */
581 pci_set_drvdata(pdev, hw);
582
583 /* Setup interrupt handler */
584 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
585 if (ret) {
586 ATH5K_ERR(sc, "request_irq failed\n");
587 goto err_free;
588 }
589
590 /*If we passed the test malloc a ath5k_hw struct*/
591 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
592 if (!sc->ah) {
593 ret = -ENOMEM;
594 ATH5K_ERR(sc, "out of memory\n");
595 goto err_irq;
596 }
597
598 sc->ah->ah_sc = sc;
599 sc->ah->ah_iobase = sc->iobase;
600 common = ath5k_hw_common(sc->ah);
601 common->ops = &ath5k_common_ops;
602 common->ah = sc->ah;
603 common->hw = hw;
604 common->cachelsz = csz << 2; /* convert to bytes */
605
606 /* Initialize device */
607 ret = ath5k_hw_attach(sc);
608 if (ret) {
609 goto err_free_ah;
610 }
611
612 /* set up multi-rate retry capabilities */
613 if (sc->ah->ah_version == AR5K_AR5212) {
614 hw->max_rates = 4;
615 hw->max_rate_tries = 11;
616 }
617
618 /* Finish private driver data initialization */
619 ret = ath5k_attach(pdev, hw);
620 if (ret)
621 goto err_ah;
622
623 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
624 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
625 sc->ah->ah_mac_srev,
626 sc->ah->ah_phy_revision);
627
628 if (!sc->ah->ah_single_chip) {
629 /* Single chip radio (!RF5111) */
630 if (sc->ah->ah_radio_5ghz_revision &&
631 !sc->ah->ah_radio_2ghz_revision) {
632 /* No 5GHz support -> report 2GHz radio */
633 if (!test_bit(AR5K_MODE_11A,
634 sc->ah->ah_capabilities.cap_mode)) {
635 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
636 ath5k_chip_name(AR5K_VERSION_RAD,
637 sc->ah->ah_radio_5ghz_revision),
638 sc->ah->ah_radio_5ghz_revision);
639 /* No 2GHz support (5110 and some
640 * 5Ghz only cards) -> report 5Ghz radio */
641 } else if (!test_bit(AR5K_MODE_11B,
642 sc->ah->ah_capabilities.cap_mode)) {
643 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
644 ath5k_chip_name(AR5K_VERSION_RAD,
645 sc->ah->ah_radio_5ghz_revision),
646 sc->ah->ah_radio_5ghz_revision);
647 /* Multiband radio */
648 } else {
649 ATH5K_INFO(sc, "RF%s multiband radio found"
650 " (0x%x)\n",
651 ath5k_chip_name(AR5K_VERSION_RAD,
652 sc->ah->ah_radio_5ghz_revision),
653 sc->ah->ah_radio_5ghz_revision);
654 }
655 }
656 /* Multi chip radio (RF5111 - RF2111) ->
657 * report both 2GHz/5GHz radios */
658 else if (sc->ah->ah_radio_5ghz_revision &&
659 sc->ah->ah_radio_2ghz_revision){
660 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
661 ath5k_chip_name(AR5K_VERSION_RAD,
662 sc->ah->ah_radio_5ghz_revision),
663 sc->ah->ah_radio_5ghz_revision);
664 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
665 ath5k_chip_name(AR5K_VERSION_RAD,
666 sc->ah->ah_radio_2ghz_revision),
667 sc->ah->ah_radio_2ghz_revision);
668 }
669 }
670
671
672 /* ready to process interrupts */
673 __clear_bit(ATH_STAT_INVALID, sc->status);
674
675 return 0;
676 err_ah:
677 ath5k_hw_detach(sc->ah);
678 err_irq:
679 free_irq(pdev->irq, sc);
680 err_free_ah:
681 kfree(sc->ah);
682 err_free:
683 ieee80211_free_hw(hw);
684 err_map:
685 pci_iounmap(pdev, mem);
686 err_reg:
687 pci_release_region(pdev, 0);
688 err_dis:
689 pci_disable_device(pdev);
690 err:
691 return ret;
692 }
693
694 static void __devexit
695 ath5k_pci_remove(struct pci_dev *pdev)
696 {
697 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
698 struct ath5k_softc *sc = hw->priv;
699
700 ath5k_debug_finish_device(sc);
701 ath5k_detach(pdev, hw);
702 ath5k_hw_detach(sc->ah);
703 kfree(sc->ah);
704 free_irq(pdev->irq, sc);
705 pci_iounmap(pdev, sc->iobase);
706 pci_release_region(pdev, 0);
707 pci_disable_device(pdev);
708 ieee80211_free_hw(hw);
709 }
710
711 #ifdef CONFIG_PM
712 static int ath5k_pci_suspend(struct device *dev)
713 {
714 struct ieee80211_hw *hw = pci_get_drvdata(to_pci_dev(dev));
715 struct ath5k_softc *sc = hw->priv;
716
717 ath5k_led_off(sc);
718 return 0;
719 }
720
721 static int ath5k_pci_resume(struct device *dev)
722 {
723 struct pci_dev *pdev = to_pci_dev(dev);
724 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
725 struct ath5k_softc *sc = hw->priv;
726
727 /*
728 * Suspend/Resume resets the PCI configuration space, so we have to
729 * re-disable the RETRY_TIMEOUT register (0x41) to keep
730 * PCI Tx retries from interfering with C3 CPU state
731 */
732 pci_write_config_byte(pdev, 0x41, 0);
733
734 ath5k_led_enable(sc);
735 return 0;
736 }
737 #endif /* CONFIG_PM */
738
739
740 /***********************\
741 * Driver Initialization *
742 \***********************/
743
744 static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
745 {
746 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
747 struct ath5k_softc *sc = hw->priv;
748 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
749
750 return ath_reg_notifier_apply(wiphy, request, regulatory);
751 }
752
753 static int
754 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
755 {
756 struct ath5k_softc *sc = hw->priv;
757 struct ath5k_hw *ah = sc->ah;
758 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
759 u8 mac[ETH_ALEN] = {};
760 int ret;
761
762 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
763
764 /*
765 * Check if the MAC has multi-rate retry support.
766 * We do this by trying to setup a fake extended
767 * descriptor. MAC's that don't have support will
768 * return false w/o doing anything. MAC's that do
769 * support it will return true w/o doing anything.
770 */
771 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
772 if (ret < 0)
773 goto err;
774 if (ret > 0)
775 __set_bit(ATH_STAT_MRRETRY, sc->status);
776
777 /*
778 * Collect the channel list. The 802.11 layer
779 * is resposible for filtering this list based
780 * on settings like the phy mode and regulatory
781 * domain restrictions.
782 */
783 ret = ath5k_setup_bands(hw);
784 if (ret) {
785 ATH5K_ERR(sc, "can't get channels\n");
786 goto err;
787 }
788
789 /* NB: setup here so ath5k_rate_update is happy */
790 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
791 ath5k_setcurmode(sc, AR5K_MODE_11A);
792 else
793 ath5k_setcurmode(sc, AR5K_MODE_11B);
794
795 /*
796 * Allocate tx+rx descriptors and populate the lists.
797 */
798 ret = ath5k_desc_alloc(sc, pdev);
799 if (ret) {
800 ATH5K_ERR(sc, "can't allocate descriptors\n");
801 goto err;
802 }
803
804 /*
805 * Allocate hardware transmit queues: one queue for
806 * beacon frames and one data queue for each QoS
807 * priority. Note that hw functions handle reseting
808 * these queues at the needed time.
809 */
810 ret = ath5k_beaconq_setup(ah);
811 if (ret < 0) {
812 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
813 goto err_desc;
814 }
815 sc->bhalq = ret;
816 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
817 if (IS_ERR(sc->cabq)) {
818 ATH5K_ERR(sc, "can't setup cab queue\n");
819 ret = PTR_ERR(sc->cabq);
820 goto err_bhal;
821 }
822
823 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
824 if (IS_ERR(sc->txq)) {
825 ATH5K_ERR(sc, "can't setup xmit queue\n");
826 ret = PTR_ERR(sc->txq);
827 goto err_queues;
828 }
829
830 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
831 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
832 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
833 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
834 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
835
836 ret = ath5k_eeprom_read_mac(ah, mac);
837 if (ret) {
838 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
839 sc->pdev->device);
840 goto err_queues;
841 }
842
843 SET_IEEE80211_PERM_ADDR(hw, mac);
844 /* All MAC address bits matter for ACKs */
845 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
846 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
847
848 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
849 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
850 if (ret) {
851 ATH5K_ERR(sc, "can't initialize regulatory system\n");
852 goto err_queues;
853 }
854
855 ret = ieee80211_register_hw(hw);
856 if (ret) {
857 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
858 goto err_queues;
859 }
860
861 if (!ath_is_world_regd(regulatory))
862 regulatory_hint(hw->wiphy, regulatory->alpha2);
863
864 ath5k_init_leds(sc);
865
866 return 0;
867 err_queues:
868 ath5k_txq_release(sc);
869 err_bhal:
870 ath5k_hw_release_tx_queue(ah, sc->bhalq);
871 err_desc:
872 ath5k_desc_free(sc, pdev);
873 err:
874 return ret;
875 }
876
877 static void
878 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
879 {
880 struct ath5k_softc *sc = hw->priv;
881
882 /*
883 * NB: the order of these is important:
884 * o call the 802.11 layer before detaching ath5k_hw to
885 * insure callbacks into the driver to delete global
886 * key cache entries can be handled
887 * o reclaim the tx queue data structures after calling
888 * the 802.11 layer as we'll get called back to reclaim
889 * node state and potentially want to use them
890 * o to cleanup the tx queues the hal is called, so detach
891 * it last
892 * XXX: ??? detach ath5k_hw ???
893 * Other than that, it's straightforward...
894 */
895 ieee80211_unregister_hw(hw);
896 ath5k_desc_free(sc, pdev);
897 ath5k_txq_release(sc);
898 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
899 ath5k_unregister_leds(sc);
900
901 /*
902 * NB: can't reclaim these until after ieee80211_ifdetach
903 * returns because we'll get called back to reclaim node
904 * state and potentially want to use them.
905 */
906 }
907
908
909
910
911 /********************\
912 * Channel/mode setup *
913 \********************/
914
915 /*
916 * Convert IEEE channel number to MHz frequency.
917 */
918 static inline short
919 ath5k_ieee2mhz(short chan)
920 {
921 if (chan <= 14 || chan >= 27)
922 return ieee80211chan2mhz(chan);
923 else
924 return 2212 + chan * 20;
925 }
926
927 /*
928 * Returns true for the channel numbers used without all_channels modparam.
929 */
930 static bool ath5k_is_standard_channel(short chan)
931 {
932 return ((chan <= 14) ||
933 /* UNII 1,2 */
934 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
935 /* midband */
936 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
937 /* UNII-3 */
938 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
939 }
940
941 static unsigned int
942 ath5k_copy_channels(struct ath5k_hw *ah,
943 struct ieee80211_channel *channels,
944 unsigned int mode,
945 unsigned int max)
946 {
947 unsigned int i, count, size, chfreq, freq, ch;
948
949 if (!test_bit(mode, ah->ah_modes))
950 return 0;
951
952 switch (mode) {
953 case AR5K_MODE_11A:
954 case AR5K_MODE_11A_TURBO:
955 /* 1..220, but 2GHz frequencies are filtered by check_channel */
956 size = 220 ;
957 chfreq = CHANNEL_5GHZ;
958 break;
959 case AR5K_MODE_11B:
960 case AR5K_MODE_11G:
961 case AR5K_MODE_11G_TURBO:
962 size = 26;
963 chfreq = CHANNEL_2GHZ;
964 break;
965 default:
966 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
967 return 0;
968 }
969
970 for (i = 0, count = 0; i < size && max > 0; i++) {
971 ch = i + 1 ;
972 freq = ath5k_ieee2mhz(ch);
973
974 /* Check if channel is supported by the chipset */
975 if (!ath5k_channel_ok(ah, freq, chfreq))
976 continue;
977
978 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
979 continue;
980
981 /* Write channel info and increment counter */
982 channels[count].center_freq = freq;
983 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
984 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
985 switch (mode) {
986 case AR5K_MODE_11A:
987 case AR5K_MODE_11G:
988 channels[count].hw_value = chfreq | CHANNEL_OFDM;
989 break;
990 case AR5K_MODE_11A_TURBO:
991 case AR5K_MODE_11G_TURBO:
992 channels[count].hw_value = chfreq |
993 CHANNEL_OFDM | CHANNEL_TURBO;
994 break;
995 case AR5K_MODE_11B:
996 channels[count].hw_value = CHANNEL_B;
997 }
998
999 count++;
1000 max--;
1001 }
1002
1003 return count;
1004 }
1005
1006 static void
1007 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
1008 {
1009 u8 i;
1010
1011 for (i = 0; i < AR5K_MAX_RATES; i++)
1012 sc->rate_idx[b->band][i] = -1;
1013
1014 for (i = 0; i < b->n_bitrates; i++) {
1015 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
1016 if (b->bitrates[i].hw_value_short)
1017 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
1018 }
1019 }
1020
1021 static int
1022 ath5k_setup_bands(struct ieee80211_hw *hw)
1023 {
1024 struct ath5k_softc *sc = hw->priv;
1025 struct ath5k_hw *ah = sc->ah;
1026 struct ieee80211_supported_band *sband;
1027 int max_c, count_c = 0;
1028 int i;
1029
1030 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
1031 max_c = ARRAY_SIZE(sc->channels);
1032
1033 /* 2GHz band */
1034 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
1035 sband->band = IEEE80211_BAND_2GHZ;
1036 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
1037
1038 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
1039 /* G mode */
1040 memcpy(sband->bitrates, &ath5k_rates[0],
1041 sizeof(struct ieee80211_rate) * 12);
1042 sband->n_bitrates = 12;
1043
1044 sband->channels = sc->channels;
1045 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1046 AR5K_MODE_11G, max_c);
1047
1048 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1049 count_c = sband->n_channels;
1050 max_c -= count_c;
1051 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
1052 /* B mode */
1053 memcpy(sband->bitrates, &ath5k_rates[0],
1054 sizeof(struct ieee80211_rate) * 4);
1055 sband->n_bitrates = 4;
1056
1057 /* 5211 only supports B rates and uses 4bit rate codes
1058 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
1059 * fix them up here:
1060 */
1061 if (ah->ah_version == AR5K_AR5211) {
1062 for (i = 0; i < 4; i++) {
1063 sband->bitrates[i].hw_value =
1064 sband->bitrates[i].hw_value & 0xF;
1065 sband->bitrates[i].hw_value_short =
1066 sband->bitrates[i].hw_value_short & 0xF;
1067 }
1068 }
1069
1070 sband->channels = sc->channels;
1071 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1072 AR5K_MODE_11B, max_c);
1073
1074 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1075 count_c = sband->n_channels;
1076 max_c -= count_c;
1077 }
1078 ath5k_setup_rate_idx(sc, sband);
1079
1080 /* 5GHz band, A mode */
1081 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
1082 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1083 sband->band = IEEE80211_BAND_5GHZ;
1084 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
1085
1086 memcpy(sband->bitrates, &ath5k_rates[4],
1087 sizeof(struct ieee80211_rate) * 8);
1088 sband->n_bitrates = 8;
1089
1090 sband->channels = &sc->channels[count_c];
1091 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1092 AR5K_MODE_11A, max_c);
1093
1094 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1095 }
1096 ath5k_setup_rate_idx(sc, sband);
1097
1098 ath5k_debug_dump_bands(sc);
1099
1100 return 0;
1101 }
1102
1103 /*
1104 * Set/change channels. We always reset the chip.
1105 * To accomplish this we must first cleanup any pending DMA,
1106 * then restart stuff after a la ath5k_init.
1107 *
1108 * Called with sc->lock.
1109 */
1110 static int
1111 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1112 {
1113 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1114 sc->curchan->center_freq, chan->center_freq);
1115
1116 /*
1117 * To switch channels clear any pending DMA operations;
1118 * wait long enough for the RX fifo to drain, reset the
1119 * hardware at the new frequency, and then re-enable
1120 * the relevant bits of the h/w.
1121 */
1122 return ath5k_reset(sc, chan);
1123 }
1124
1125 static void
1126 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1127 {
1128 sc->curmode = mode;
1129
1130 if (mode == AR5K_MODE_11A) {
1131 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1132 } else {
1133 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1134 }
1135 }
1136
1137 static void
1138 ath5k_mode_setup(struct ath5k_softc *sc)
1139 {
1140 struct ath5k_hw *ah = sc->ah;
1141 u32 rfilt;
1142
1143 ah->ah_op_mode = sc->opmode;
1144
1145 /* configure rx filter */
1146 rfilt = sc->filter_flags;
1147 ath5k_hw_set_rx_filter(ah, rfilt);
1148
1149 if (ath5k_hw_hasbssidmask(ah))
1150 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1151
1152 /* configure operational mode */
1153 ath5k_hw_set_opmode(ah);
1154
1155 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1156 }
1157
1158 static inline int
1159 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1160 {
1161 int rix;
1162
1163 /* return base rate on errors */
1164 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
1165 "hw_rix out of bounds: %x\n", hw_rix))
1166 return 0;
1167
1168 rix = sc->rate_idx[sc->curband->band][hw_rix];
1169 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
1170 rix = 0;
1171
1172 return rix;
1173 }
1174
1175 /***************\
1176 * Buffers setup *
1177 \***************/
1178
1179 static
1180 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1181 {
1182 struct ath_common *common = ath5k_hw_common(sc->ah);
1183 struct sk_buff *skb;
1184
1185 /*
1186 * Allocate buffer with headroom_needed space for the
1187 * fake physical layer header at the start.
1188 */
1189 skb = ath_rxbuf_alloc(common,
1190 common->rx_bufsize,
1191 GFP_ATOMIC);
1192
1193 if (!skb) {
1194 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1195 common->rx_bufsize);
1196 return NULL;
1197 }
1198
1199 *skb_addr = pci_map_single(sc->pdev,
1200 skb->data, common->rx_bufsize,
1201 PCI_DMA_FROMDEVICE);
1202 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1203 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1204 dev_kfree_skb(skb);
1205 return NULL;
1206 }
1207 return skb;
1208 }
1209
1210 static int
1211 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1212 {
1213 struct ath5k_hw *ah = sc->ah;
1214 struct sk_buff *skb = bf->skb;
1215 struct ath5k_desc *ds;
1216
1217 if (!skb) {
1218 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1219 if (!skb)
1220 return -ENOMEM;
1221 bf->skb = skb;
1222 }
1223
1224 /*
1225 * Setup descriptors. For receive we always terminate
1226 * the descriptor list with a self-linked entry so we'll
1227 * not get overrun under high load (as can happen with a
1228 * 5212 when ANI processing enables PHY error frames).
1229 *
1230 * To insure the last descriptor is self-linked we create
1231 * each descriptor as self-linked and add it to the end. As
1232 * each additional descriptor is added the previous self-linked
1233 * entry is ``fixed'' naturally. This should be safe even
1234 * if DMA is happening. When processing RX interrupts we
1235 * never remove/process the last, self-linked, entry on the
1236 * descriptor list. This insures the hardware always has
1237 * someplace to write a new frame.
1238 */
1239 ds = bf->desc;
1240 ds->ds_link = bf->daddr; /* link to self */
1241 ds->ds_data = bf->skbaddr;
1242 ah->ah_setup_rx_desc(ah, ds,
1243 skb_tailroom(skb), /* buffer size */
1244 0);
1245
1246 if (sc->rxlink != NULL)
1247 *sc->rxlink = bf->daddr;
1248 sc->rxlink = &ds->ds_link;
1249 return 0;
1250 }
1251
1252 static int
1253 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1254 struct ath5k_txq *txq)
1255 {
1256 struct ath5k_hw *ah = sc->ah;
1257 struct ath5k_desc *ds = bf->desc;
1258 struct sk_buff *skb = bf->skb;
1259 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1260 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1261 struct ieee80211_rate *rate;
1262 unsigned int mrr_rate[3], mrr_tries[3];
1263 int i, ret;
1264 u16 hw_rate;
1265 u16 cts_rate = 0;
1266 u16 duration = 0;
1267 u8 rc_flags;
1268
1269 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1270
1271 /* XXX endianness */
1272 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1273 PCI_DMA_TODEVICE);
1274
1275 rate = ieee80211_get_tx_rate(sc->hw, info);
1276
1277 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
1278 flags |= AR5K_TXDESC_NOACK;
1279
1280 rc_flags = info->control.rates[0].flags;
1281 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
1282 rate->hw_value_short : rate->hw_value;
1283
1284 pktlen = skb->len;
1285
1286 /* FIXME: If we are in g mode and rate is a CCK rate
1287 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1288 * from tx power (value is in dB units already) */
1289 if (info->control.hw_key) {
1290 keyidx = info->control.hw_key->hw_key_idx;
1291 pktlen += info->control.hw_key->icv_len;
1292 }
1293 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1294 flags |= AR5K_TXDESC_RTSENA;
1295 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1296 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
1297 sc->vif, pktlen, info));
1298 }
1299 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1300 flags |= AR5K_TXDESC_CTSENA;
1301 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1302 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
1303 sc->vif, pktlen, info));
1304 }
1305 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1306 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
1307 (sc->power_level * 2),
1308 hw_rate,
1309 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
1310 cts_rate, duration);
1311 if (ret)
1312 goto err_unmap;
1313
1314 memset(mrr_rate, 0, sizeof(mrr_rate));
1315 memset(mrr_tries, 0, sizeof(mrr_tries));
1316 for (i = 0; i < 3; i++) {
1317 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1318 if (!rate)
1319 break;
1320
1321 mrr_rate[i] = rate->hw_value;
1322 mrr_tries[i] = info->control.rates[i + 1].count;
1323 }
1324
1325 ah->ah_setup_mrr_tx_desc(ah, ds,
1326 mrr_rate[0], mrr_tries[0],
1327 mrr_rate[1], mrr_tries[1],
1328 mrr_rate[2], mrr_tries[2]);
1329
1330 ds->ds_link = 0;
1331 ds->ds_data = bf->skbaddr;
1332
1333 spin_lock_bh(&txq->lock);
1334 list_add_tail(&bf->list, &txq->q);
1335 sc->tx_stats[txq->qnum].len++;
1336 if (txq->link == NULL) /* is this first packet? */
1337 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
1338 else /* no, so only link it */
1339 *txq->link = bf->daddr;
1340
1341 txq->link = &ds->ds_link;
1342 ath5k_hw_start_tx_dma(ah, txq->qnum);
1343 mmiowb();
1344 spin_unlock_bh(&txq->lock);
1345
1346 return 0;
1347 err_unmap:
1348 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1349 return ret;
1350 }
1351
1352 /*******************\
1353 * Descriptors setup *
1354 \*******************/
1355
1356 static int
1357 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1358 {
1359 struct ath5k_desc *ds;
1360 struct ath5k_buf *bf;
1361 dma_addr_t da;
1362 unsigned int i;
1363 int ret;
1364
1365 /* allocate descriptors */
1366 sc->desc_len = sizeof(struct ath5k_desc) *
1367 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1368 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1369 if (sc->desc == NULL) {
1370 ATH5K_ERR(sc, "can't allocate descriptors\n");
1371 ret = -ENOMEM;
1372 goto err;
1373 }
1374 ds = sc->desc;
1375 da = sc->desc_daddr;
1376 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1377 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1378
1379 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1380 sizeof(struct ath5k_buf), GFP_KERNEL);
1381 if (bf == NULL) {
1382 ATH5K_ERR(sc, "can't allocate bufptr\n");
1383 ret = -ENOMEM;
1384 goto err_free;
1385 }
1386 sc->bufptr = bf;
1387
1388 INIT_LIST_HEAD(&sc->rxbuf);
1389 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1390 bf->desc = ds;
1391 bf->daddr = da;
1392 list_add_tail(&bf->list, &sc->rxbuf);
1393 }
1394
1395 INIT_LIST_HEAD(&sc->txbuf);
1396 sc->txbuf_len = ATH_TXBUF;
1397 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1398 da += sizeof(*ds)) {
1399 bf->desc = ds;
1400 bf->daddr = da;
1401 list_add_tail(&bf->list, &sc->txbuf);
1402 }
1403
1404 /* beacon buffer */
1405 bf->desc = ds;
1406 bf->daddr = da;
1407 sc->bbuf = bf;
1408
1409 return 0;
1410 err_free:
1411 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1412 err:
1413 sc->desc = NULL;
1414 return ret;
1415 }
1416
1417 static void
1418 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1419 {
1420 struct ath5k_buf *bf;
1421
1422 ath5k_txbuf_free(sc, sc->bbuf);
1423 list_for_each_entry(bf, &sc->txbuf, list)
1424 ath5k_txbuf_free(sc, bf);
1425 list_for_each_entry(bf, &sc->rxbuf, list)
1426 ath5k_rxbuf_free(sc, bf);
1427
1428 /* Free memory associated with all descriptors */
1429 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1430
1431 kfree(sc->bufptr);
1432 sc->bufptr = NULL;
1433 }
1434
1435
1436
1437
1438
1439 /**************\
1440 * Queues setup *
1441 \**************/
1442
1443 static struct ath5k_txq *
1444 ath5k_txq_setup(struct ath5k_softc *sc,
1445 int qtype, int subtype)
1446 {
1447 struct ath5k_hw *ah = sc->ah;
1448 struct ath5k_txq *txq;
1449 struct ath5k_txq_info qi = {
1450 .tqi_subtype = subtype,
1451 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1452 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1453 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1454 };
1455 int qnum;
1456
1457 /*
1458 * Enable interrupts only for EOL and DESC conditions.
1459 * We mark tx descriptors to receive a DESC interrupt
1460 * when a tx queue gets deep; otherwise waiting for the
1461 * EOL to reap descriptors. Note that this is done to
1462 * reduce interrupt load and this only defers reaping
1463 * descriptors, never transmitting frames. Aside from
1464 * reducing interrupts this also permits more concurrency.
1465 * The only potential downside is if the tx queue backs
1466 * up in which case the top half of the kernel may backup
1467 * due to a lack of tx descriptors.
1468 */
1469 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1470 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1471 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1472 if (qnum < 0) {
1473 /*
1474 * NB: don't print a message, this happens
1475 * normally on parts with too few tx queues
1476 */
1477 return ERR_PTR(qnum);
1478 }
1479 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1480 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1481 qnum, ARRAY_SIZE(sc->txqs));
1482 ath5k_hw_release_tx_queue(ah, qnum);
1483 return ERR_PTR(-EINVAL);
1484 }
1485 txq = &sc->txqs[qnum];
1486 if (!txq->setup) {
1487 txq->qnum = qnum;
1488 txq->link = NULL;
1489 INIT_LIST_HEAD(&txq->q);
1490 spin_lock_init(&txq->lock);
1491 txq->setup = true;
1492 }
1493 return &sc->txqs[qnum];
1494 }
1495
1496 static int
1497 ath5k_beaconq_setup(struct ath5k_hw *ah)
1498 {
1499 struct ath5k_txq_info qi = {
1500 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1501 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1502 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1503 /* NB: for dynamic turbo, don't enable any other interrupts */
1504 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1505 };
1506
1507 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1508 }
1509
1510 static int
1511 ath5k_beaconq_config(struct ath5k_softc *sc)
1512 {
1513 struct ath5k_hw *ah = sc->ah;
1514 struct ath5k_txq_info qi;
1515 int ret;
1516
1517 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1518 if (ret)
1519 goto err;
1520
1521 if (sc->opmode == NL80211_IFTYPE_AP ||
1522 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1523 /*
1524 * Always burst out beacon and CAB traffic
1525 * (aifs = cwmin = cwmax = 0)
1526 */
1527 qi.tqi_aifs = 0;
1528 qi.tqi_cw_min = 0;
1529 qi.tqi_cw_max = 0;
1530 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1531 /*
1532 * Adhoc mode; backoff between 0 and (2 * cw_min).
1533 */
1534 qi.tqi_aifs = 0;
1535 qi.tqi_cw_min = 0;
1536 qi.tqi_cw_max = 2 * ah->ah_cw_min;
1537 }
1538
1539 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1540 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1541 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1542
1543 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1544 if (ret) {
1545 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1546 "hardware queue!\n", __func__);
1547 goto err;
1548 }
1549 ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */
1550 if (ret)
1551 goto err;
1552
1553 /* reconfigure cabq with ready time to 80% of beacon_interval */
1554 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1555 if (ret)
1556 goto err;
1557
1558 qi.tqi_ready_time = (sc->bintval * 80) / 100;
1559 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1560 if (ret)
1561 goto err;
1562
1563 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1564 err:
1565 return ret;
1566 }
1567
1568 static void
1569 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1570 {
1571 struct ath5k_buf *bf, *bf0;
1572
1573 /*
1574 * NB: this assumes output has been stopped and
1575 * we do not need to block ath5k_tx_tasklet
1576 */
1577 spin_lock_bh(&txq->lock);
1578 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1579 ath5k_debug_printtxbuf(sc, bf);
1580
1581 ath5k_txbuf_free(sc, bf);
1582
1583 spin_lock_bh(&sc->txbuflock);
1584 sc->tx_stats[txq->qnum].len--;
1585 list_move_tail(&bf->list, &sc->txbuf);
1586 sc->txbuf_len++;
1587 spin_unlock_bh(&sc->txbuflock);
1588 }
1589 txq->link = NULL;
1590 spin_unlock_bh(&txq->lock);
1591 }
1592
1593 /*
1594 * Drain the transmit queues and reclaim resources.
1595 */
1596 static void
1597 ath5k_txq_cleanup(struct ath5k_softc *sc)
1598 {
1599 struct ath5k_hw *ah = sc->ah;
1600 unsigned int i;
1601
1602 /* XXX return value */
1603 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1604 /* don't touch the hardware if marked invalid */
1605 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1606 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1607 ath5k_hw_get_txdp(ah, sc->bhalq));
1608 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1609 if (sc->txqs[i].setup) {
1610 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1611 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1612 "link %p\n",
1613 sc->txqs[i].qnum,
1614 ath5k_hw_get_txdp(ah,
1615 sc->txqs[i].qnum),
1616 sc->txqs[i].link);
1617 }
1618 }
1619 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
1620
1621 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1622 if (sc->txqs[i].setup)
1623 ath5k_txq_drainq(sc, &sc->txqs[i]);
1624 }
1625
1626 static void
1627 ath5k_txq_release(struct ath5k_softc *sc)
1628 {
1629 struct ath5k_txq *txq = sc->txqs;
1630 unsigned int i;
1631
1632 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1633 if (txq->setup) {
1634 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1635 txq->setup = false;
1636 }
1637 }
1638
1639
1640
1641
1642 /*************\
1643 * RX Handling *
1644 \*************/
1645
1646 /*
1647 * Enable the receive h/w following a reset.
1648 */
1649 static int
1650 ath5k_rx_start(struct ath5k_softc *sc)
1651 {
1652 struct ath5k_hw *ah = sc->ah;
1653 struct ath_common *common = ath5k_hw_common(ah);
1654 struct ath5k_buf *bf;
1655 int ret;
1656
1657 common->rx_bufsize = roundup(IEEE80211_MAX_LEN, common->cachelsz);
1658
1659 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1660 common->cachelsz, common->rx_bufsize);
1661
1662 spin_lock_bh(&sc->rxbuflock);
1663 sc->rxlink = NULL;
1664 list_for_each_entry(bf, &sc->rxbuf, list) {
1665 ret = ath5k_rxbuf_setup(sc, bf);
1666 if (ret != 0) {
1667 spin_unlock_bh(&sc->rxbuflock);
1668 goto err;
1669 }
1670 }
1671 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1672 ath5k_hw_set_rxdp(ah, bf->daddr);
1673 spin_unlock_bh(&sc->rxbuflock);
1674
1675 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
1676 ath5k_mode_setup(sc); /* set filters, etc. */
1677 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1678
1679 return 0;
1680 err:
1681 return ret;
1682 }
1683
1684 /*
1685 * Disable the receive h/w in preparation for a reset.
1686 */
1687 static void
1688 ath5k_rx_stop(struct ath5k_softc *sc)
1689 {
1690 struct ath5k_hw *ah = sc->ah;
1691
1692 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
1693 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1694 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1695
1696 ath5k_debug_printrxbuffs(sc, ah);
1697
1698 sc->rxlink = NULL; /* just in case */
1699 }
1700
1701 static unsigned int
1702 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1703 struct sk_buff *skb, struct ath5k_rx_status *rs)
1704 {
1705 struct ath5k_hw *ah = sc->ah;
1706 struct ath_common *common = ath5k_hw_common(ah);
1707 struct ieee80211_hdr *hdr = (void *)skb->data;
1708 unsigned int keyix, hlen;
1709
1710 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1711 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1712 return RX_FLAG_DECRYPTED;
1713
1714 /* Apparently when a default key is used to decrypt the packet
1715 the hw does not set the index used to decrypt. In such cases
1716 get the index from the packet. */
1717 hlen = ieee80211_hdrlen(hdr->frame_control);
1718 if (ieee80211_has_protected(hdr->frame_control) &&
1719 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1720 skb->len >= hlen + 4) {
1721 keyix = skb->data[hlen + 3] >> 6;
1722
1723 if (test_bit(keyix, common->keymap))
1724 return RX_FLAG_DECRYPTED;
1725 }
1726
1727 return 0;
1728 }
1729
1730
1731 static void
1732 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1733 struct ieee80211_rx_status *rxs)
1734 {
1735 struct ath_common *common = ath5k_hw_common(sc->ah);
1736 u64 tsf, bc_tstamp;
1737 u32 hw_tu;
1738 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1739
1740 if (ieee80211_is_beacon(mgmt->frame_control) &&
1741 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1742 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
1743 /*
1744 * Received an IBSS beacon with the same BSSID. Hardware *must*
1745 * have updated the local TSF. We have to work around various
1746 * hardware bugs, though...
1747 */
1748 tsf = ath5k_hw_get_tsf64(sc->ah);
1749 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1750 hw_tu = TSF_TO_TU(tsf);
1751
1752 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1753 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1754 (unsigned long long)bc_tstamp,
1755 (unsigned long long)rxs->mactime,
1756 (unsigned long long)(rxs->mactime - bc_tstamp),
1757 (unsigned long long)tsf);
1758
1759 /*
1760 * Sometimes the HW will give us a wrong tstamp in the rx
1761 * status, causing the timestamp extension to go wrong.
1762 * (This seems to happen especially with beacon frames bigger
1763 * than 78 byte (incl. FCS))
1764 * But we know that the receive timestamp must be later than the
1765 * timestamp of the beacon since HW must have synced to that.
1766 *
1767 * NOTE: here we assume mactime to be after the frame was
1768 * received, not like mac80211 which defines it at the start.
1769 */
1770 if (bc_tstamp > rxs->mactime) {
1771 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1772 "fixing mactime from %llx to %llx\n",
1773 (unsigned long long)rxs->mactime,
1774 (unsigned long long)tsf);
1775 rxs->mactime = tsf;
1776 }
1777
1778 /*
1779 * Local TSF might have moved higher than our beacon timers,
1780 * in that case we have to update them to continue sending
1781 * beacons. This also takes care of synchronizing beacon sending
1782 * times with other stations.
1783 */
1784 if (hw_tu >= sc->nexttbtt)
1785 ath5k_beacon_update_timers(sc, bc_tstamp);
1786 }
1787 }
1788
1789 static void
1790 ath5k_tasklet_rx(unsigned long data)
1791 {
1792 struct ieee80211_rx_status *rxs;
1793 struct ath5k_rx_status rs = {};
1794 struct sk_buff *skb, *next_skb;
1795 dma_addr_t next_skb_addr;
1796 struct ath5k_softc *sc = (void *)data;
1797 struct ath5k_hw *ah = sc->ah;
1798 struct ath_common *common = ath5k_hw_common(ah);
1799 struct ath5k_buf *bf;
1800 struct ath5k_desc *ds;
1801 int ret;
1802 int hdrlen;
1803 int padsize;
1804 int rx_flag;
1805
1806 spin_lock(&sc->rxbuflock);
1807 if (list_empty(&sc->rxbuf)) {
1808 ATH5K_WARN(sc, "empty rx buf pool\n");
1809 goto unlock;
1810 }
1811 do {
1812 rx_flag = 0;
1813
1814 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1815 BUG_ON(bf->skb == NULL);
1816 skb = bf->skb;
1817 ds = bf->desc;
1818
1819 /* bail if HW is still using self-linked descriptor */
1820 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1821 break;
1822
1823 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1824 if (unlikely(ret == -EINPROGRESS))
1825 break;
1826 else if (unlikely(ret)) {
1827 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1828 spin_unlock(&sc->rxbuflock);
1829 return;
1830 }
1831
1832 if (unlikely(rs.rs_more)) {
1833 ATH5K_WARN(sc, "unsupported jumbo\n");
1834 goto next;
1835 }
1836
1837 if (unlikely(rs.rs_status)) {
1838 if (rs.rs_status & AR5K_RXERR_PHY)
1839 goto next;
1840 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
1841 /*
1842 * Decrypt error. If the error occurred
1843 * because there was no hardware key, then
1844 * let the frame through so the upper layers
1845 * can process it. This is necessary for 5210
1846 * parts which have no way to setup a ``clear''
1847 * key cache entry.
1848 *
1849 * XXX do key cache faulting
1850 */
1851 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1852 !(rs.rs_status & AR5K_RXERR_CRC))
1853 goto accept;
1854 }
1855 if (rs.rs_status & AR5K_RXERR_MIC) {
1856 rx_flag |= RX_FLAG_MMIC_ERROR;
1857 goto accept;
1858 }
1859
1860 /* let crypto-error packets fall through in MNTR */
1861 if ((rs.rs_status &
1862 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1863 sc->opmode != NL80211_IFTYPE_MONITOR)
1864 goto next;
1865 }
1866 accept:
1867 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1868
1869 /*
1870 * If we can't replace bf->skb with a new skb under memory
1871 * pressure, just skip this packet
1872 */
1873 if (!next_skb)
1874 goto next;
1875
1876 pci_unmap_single(sc->pdev, bf->skbaddr, common->rx_bufsize,
1877 PCI_DMA_FROMDEVICE);
1878 skb_put(skb, rs.rs_datalen);
1879
1880 /* The MAC header is padded to have 32-bit boundary if the
1881 * packet payload is non-zero. The general calculation for
1882 * padsize would take into account odd header lengths:
1883 * padsize = (4 - hdrlen % 4) % 4; However, since only
1884 * even-length headers are used, padding can only be 0 or 2
1885 * bytes and we can optimize this a bit. In addition, we must
1886 * not try to remove padding from short control frames that do
1887 * not have payload. */
1888 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1889 padsize = ath5k_pad_size(hdrlen);
1890 if (padsize) {
1891 memmove(skb->data + padsize, skb->data, hdrlen);
1892 skb_pull(skb, padsize);
1893 }
1894 rxs = IEEE80211_SKB_RXCB(skb);
1895
1896 /*
1897 * always extend the mac timestamp, since this information is
1898 * also needed for proper IBSS merging.
1899 *
1900 * XXX: it might be too late to do it here, since rs_tstamp is
1901 * 15bit only. that means TSF extension has to be done within
1902 * 32768usec (about 32ms). it might be necessary to move this to
1903 * the interrupt handler, like it is done in madwifi.
1904 *
1905 * Unfortunately we don't know when the hardware takes the rx
1906 * timestamp (beginning of phy frame, data frame, end of rx?).
1907 * The only thing we know is that it is hardware specific...
1908 * On AR5213 it seems the rx timestamp is at the end of the
1909 * frame, but i'm not sure.
1910 *
1911 * NOTE: mac80211 defines mactime at the beginning of the first
1912 * data symbol. Since we don't have any time references it's
1913 * impossible to comply to that. This affects IBSS merge only
1914 * right now, so it's not too bad...
1915 */
1916 rxs->mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
1917 rxs->flag = rx_flag | RX_FLAG_TSFT;
1918
1919 rxs->freq = sc->curchan->center_freq;
1920 rxs->band = sc->curband->band;
1921
1922 rxs->noise = sc->ah->ah_noise_floor;
1923 rxs->signal = rxs->noise + rs.rs_rssi;
1924
1925 rxs->antenna = rs.rs_antenna;
1926 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1927 rxs->flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
1928
1929 if (rxs->rate_idx >= 0 && rs.rs_rate ==
1930 sc->curband->bitrates[rxs->rate_idx].hw_value_short)
1931 rxs->flag |= RX_FLAG_SHORTPRE;
1932
1933 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1934
1935 /* check beacons in IBSS mode */
1936 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1937 ath5k_check_ibss_tsf(sc, skb, rxs);
1938
1939 ieee80211_rx(sc->hw, skb);
1940
1941 bf->skb = next_skb;
1942 bf->skbaddr = next_skb_addr;
1943 next:
1944 list_move_tail(&bf->list, &sc->rxbuf);
1945 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1946 unlock:
1947 spin_unlock(&sc->rxbuflock);
1948 }
1949
1950
1951
1952
1953 /*************\
1954 * TX Handling *
1955 \*************/
1956
1957 static void
1958 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1959 {
1960 struct ath5k_tx_status ts = {};
1961 struct ath5k_buf *bf, *bf0;
1962 struct ath5k_desc *ds;
1963 struct sk_buff *skb;
1964 struct ieee80211_tx_info *info;
1965 int i, ret;
1966
1967 spin_lock(&txq->lock);
1968 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1969 ds = bf->desc;
1970
1971 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1972 if (unlikely(ret == -EINPROGRESS))
1973 break;
1974 else if (unlikely(ret)) {
1975 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1976 ret, txq->qnum);
1977 break;
1978 }
1979
1980 skb = bf->skb;
1981 info = IEEE80211_SKB_CB(skb);
1982 bf->skb = NULL;
1983
1984 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1985 PCI_DMA_TODEVICE);
1986
1987 ieee80211_tx_info_clear_status(info);
1988 for (i = 0; i < 4; i++) {
1989 struct ieee80211_tx_rate *r =
1990 &info->status.rates[i];
1991
1992 if (ts.ts_rate[i]) {
1993 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
1994 r->count = ts.ts_retry[i];
1995 } else {
1996 r->idx = -1;
1997 r->count = 0;
1998 }
1999 }
2000
2001 /* count the successful attempt as well */
2002 info->status.rates[ts.ts_final_idx].count++;
2003
2004 if (unlikely(ts.ts_status)) {
2005 sc->ll_stats.dot11ACKFailureCount++;
2006 if (ts.ts_status & AR5K_TXERR_FILT)
2007 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2008 } else {
2009 info->flags |= IEEE80211_TX_STAT_ACK;
2010 info->status.ack_signal = ts.ts_rssi;
2011 }
2012
2013 ieee80211_tx_status(sc->hw, skb);
2014 sc->tx_stats[txq->qnum].count++;
2015
2016 spin_lock(&sc->txbuflock);
2017 sc->tx_stats[txq->qnum].len--;
2018 list_move_tail(&bf->list, &sc->txbuf);
2019 sc->txbuf_len++;
2020 spin_unlock(&sc->txbuflock);
2021 }
2022 if (likely(list_empty(&txq->q)))
2023 txq->link = NULL;
2024 spin_unlock(&txq->lock);
2025 if (sc->txbuf_len > ATH_TXBUF / 5)
2026 ieee80211_wake_queues(sc->hw);
2027 }
2028
2029 static void
2030 ath5k_tasklet_tx(unsigned long data)
2031 {
2032 int i;
2033 struct ath5k_softc *sc = (void *)data;
2034
2035 for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
2036 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
2037 ath5k_tx_processq(sc, &sc->txqs[i]);
2038 }
2039
2040
2041 /*****************\
2042 * Beacon handling *
2043 \*****************/
2044
2045 /*
2046 * Setup the beacon frame for transmit.
2047 */
2048 static int
2049 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
2050 {
2051 struct sk_buff *skb = bf->skb;
2052 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2053 struct ath5k_hw *ah = sc->ah;
2054 struct ath5k_desc *ds;
2055 int ret = 0;
2056 u8 antenna;
2057 u32 flags;
2058
2059 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
2060 PCI_DMA_TODEVICE);
2061 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
2062 "skbaddr %llx\n", skb, skb->data, skb->len,
2063 (unsigned long long)bf->skbaddr);
2064 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
2065 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
2066 return -EIO;
2067 }
2068
2069 ds = bf->desc;
2070 antenna = ah->ah_tx_ant;
2071
2072 flags = AR5K_TXDESC_NOACK;
2073 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
2074 ds->ds_link = bf->daddr; /* self-linked */
2075 flags |= AR5K_TXDESC_VEOL;
2076 } else
2077 ds->ds_link = 0;
2078
2079 /*
2080 * If we use multiple antennas on AP and use
2081 * the Sectored AP scenario, switch antenna every
2082 * 4 beacons to make sure everybody hears our AP.
2083 * When a client tries to associate, hw will keep
2084 * track of the tx antenna to be used for this client
2085 * automaticaly, based on ACKed packets.
2086 *
2087 * Note: AP still listens and transmits RTS on the
2088 * default antenna which is supposed to be an omni.
2089 *
2090 * Note2: On sectored scenarios it's possible to have
2091 * multiple antennas (1omni -the default- and 14 sectors)
2092 * so if we choose to actually support this mode we need
2093 * to allow user to set how many antennas we have and tweak
2094 * the code below to send beacons on all of them.
2095 */
2096 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
2097 antenna = sc->bsent & 4 ? 2 : 1;
2098
2099
2100 /* FIXME: If we are in g mode and rate is a CCK rate
2101 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
2102 * from tx power (value is in dB units already) */
2103 ds->ds_data = bf->skbaddr;
2104 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
2105 ieee80211_get_hdrlen_from_skb(skb),
2106 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
2107 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2108 1, AR5K_TXKEYIX_INVALID,
2109 antenna, flags, 0, 0);
2110 if (ret)
2111 goto err_unmap;
2112
2113 return 0;
2114 err_unmap:
2115 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2116 return ret;
2117 }
2118
2119 /*
2120 * Transmit a beacon frame at SWBA. Dynamic updates to the
2121 * frame contents are done as needed and the slot time is
2122 * also adjusted based on current state.
2123 *
2124 * This is called from software irq context (beacontq or restq
2125 * tasklets) or user context from ath5k_beacon_config.
2126 */
2127 static void
2128 ath5k_beacon_send(struct ath5k_softc *sc)
2129 {
2130 struct ath5k_buf *bf = sc->bbuf;
2131 struct ath5k_hw *ah = sc->ah;
2132 struct sk_buff *skb;
2133
2134 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
2135
2136 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2137 sc->opmode == NL80211_IFTYPE_MONITOR)) {
2138 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2139 return;
2140 }
2141 /*
2142 * Check if the previous beacon has gone out. If
2143 * not don't don't try to post another, skip this
2144 * period and wait for the next. Missed beacons
2145 * indicate a problem and should not occur. If we
2146 * miss too many consecutive beacons reset the device.
2147 */
2148 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2149 sc->bmisscount++;
2150 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2151 "missed %u consecutive beacons\n", sc->bmisscount);
2152 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
2153 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2154 "stuck beacon time (%u missed)\n",
2155 sc->bmisscount);
2156 tasklet_schedule(&sc->restq);
2157 }
2158 return;
2159 }
2160 if (unlikely(sc->bmisscount != 0)) {
2161 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2162 "resume beacon xmit after %u misses\n",
2163 sc->bmisscount);
2164 sc->bmisscount = 0;
2165 }
2166
2167 /*
2168 * Stop any current dma and put the new frame on the queue.
2169 * This should never fail since we check above that no frames
2170 * are still pending on the queue.
2171 */
2172 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2173 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
2174 /* NB: hw still stops DMA, so proceed */
2175 }
2176
2177 /* refresh the beacon for AP mode */
2178 if (sc->opmode == NL80211_IFTYPE_AP)
2179 ath5k_beacon_update(sc->hw, sc->vif);
2180
2181 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2182 ath5k_hw_start_tx_dma(ah, sc->bhalq);
2183 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
2184 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2185
2186 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2187 while (skb) {
2188 ath5k_tx_queue(sc->hw, skb, sc->cabq);
2189 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2190 }
2191
2192 sc->bsent++;
2193 }
2194
2195
2196 /**
2197 * ath5k_beacon_update_timers - update beacon timers
2198 *
2199 * @sc: struct ath5k_softc pointer we are operating on
2200 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2201 * beacon timer update based on the current HW TSF.
2202 *
2203 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2204 * of a received beacon or the current local hardware TSF and write it to the
2205 * beacon timer registers.
2206 *
2207 * This is called in a variety of situations, e.g. when a beacon is received,
2208 * when a TSF update has been detected, but also when an new IBSS is created or
2209 * when we otherwise know we have to update the timers, but we keep it in this
2210 * function to have it all together in one place.
2211 */
2212 static void
2213 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2214 {
2215 struct ath5k_hw *ah = sc->ah;
2216 u32 nexttbtt, intval, hw_tu, bc_tu;
2217 u64 hw_tsf;
2218
2219 intval = sc->bintval & AR5K_BEACON_PERIOD;
2220 if (WARN_ON(!intval))
2221 return;
2222
2223 /* beacon TSF converted to TU */
2224 bc_tu = TSF_TO_TU(bc_tsf);
2225
2226 /* current TSF converted to TU */
2227 hw_tsf = ath5k_hw_get_tsf64(ah);
2228 hw_tu = TSF_TO_TU(hw_tsf);
2229
2230 #define FUDGE 3
2231 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2232 if (bc_tsf == -1) {
2233 /*
2234 * no beacons received, called internally.
2235 * just need to refresh timers based on HW TSF.
2236 */
2237 nexttbtt = roundup(hw_tu + FUDGE, intval);
2238 } else if (bc_tsf == 0) {
2239 /*
2240 * no beacon received, probably called by ath5k_reset_tsf().
2241 * reset TSF to start with 0.
2242 */
2243 nexttbtt = intval;
2244 intval |= AR5K_BEACON_RESET_TSF;
2245 } else if (bc_tsf > hw_tsf) {
2246 /*
2247 * beacon received, SW merge happend but HW TSF not yet updated.
2248 * not possible to reconfigure timers yet, but next time we
2249 * receive a beacon with the same BSSID, the hardware will
2250 * automatically update the TSF and then we need to reconfigure
2251 * the timers.
2252 */
2253 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2254 "need to wait for HW TSF sync\n");
2255 return;
2256 } else {
2257 /*
2258 * most important case for beacon synchronization between STA.
2259 *
2260 * beacon received and HW TSF has been already updated by HW.
2261 * update next TBTT based on the TSF of the beacon, but make
2262 * sure it is ahead of our local TSF timer.
2263 */
2264 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2265 }
2266 #undef FUDGE
2267
2268 sc->nexttbtt = nexttbtt;
2269
2270 intval |= AR5K_BEACON_ENA;
2271 ath5k_hw_init_beacon(ah, nexttbtt, intval);
2272
2273 /*
2274 * debugging output last in order to preserve the time critical aspect
2275 * of this function
2276 */
2277 if (bc_tsf == -1)
2278 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2279 "reconfigured timers based on HW TSF\n");
2280 else if (bc_tsf == 0)
2281 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2282 "reset HW TSF and timers\n");
2283 else
2284 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2285 "updated timers based on beacon TSF\n");
2286
2287 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2288 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2289 (unsigned long long) bc_tsf,
2290 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2291 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2292 intval & AR5K_BEACON_PERIOD,
2293 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2294 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2295 }
2296
2297
2298 /**
2299 * ath5k_beacon_config - Configure the beacon queues and interrupts
2300 *
2301 * @sc: struct ath5k_softc pointer we are operating on
2302 *
2303 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2304 * interrupts to detect TSF updates only.
2305 */
2306 static void
2307 ath5k_beacon_config(struct ath5k_softc *sc)
2308 {
2309 struct ath5k_hw *ah = sc->ah;
2310 unsigned long flags;
2311
2312 spin_lock_irqsave(&sc->block, flags);
2313 sc->bmisscount = 0;
2314 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2315
2316 if (sc->enable_beacon) {
2317 /*
2318 * In IBSS mode we use a self-linked tx descriptor and let the
2319 * hardware send the beacons automatically. We have to load it
2320 * only once here.
2321 * We use the SWBA interrupt only to keep track of the beacon
2322 * timers in order to detect automatic TSF updates.
2323 */
2324 ath5k_beaconq_config(sc);
2325
2326 sc->imask |= AR5K_INT_SWBA;
2327
2328 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2329 if (ath5k_hw_hasveol(ah))
2330 ath5k_beacon_send(sc);
2331 } else
2332 ath5k_beacon_update_timers(sc, -1);
2333 } else {
2334 ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq);
2335 }
2336
2337 ath5k_hw_set_imr(ah, sc->imask);
2338 mmiowb();
2339 spin_unlock_irqrestore(&sc->block, flags);
2340 }
2341
2342 static void ath5k_tasklet_beacon(unsigned long data)
2343 {
2344 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2345
2346 /*
2347 * Software beacon alert--time to send a beacon.
2348 *
2349 * In IBSS mode we use this interrupt just to
2350 * keep track of the next TBTT (target beacon
2351 * transmission time) in order to detect wether
2352 * automatic TSF updates happened.
2353 */
2354 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2355 /* XXX: only if VEOL suppported */
2356 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2357 sc->nexttbtt += sc->bintval;
2358 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2359 "SWBA nexttbtt: %x hw_tu: %x "
2360 "TSF: %llx\n",
2361 sc->nexttbtt,
2362 TSF_TO_TU(tsf),
2363 (unsigned long long) tsf);
2364 } else {
2365 spin_lock(&sc->block);
2366 ath5k_beacon_send(sc);
2367 spin_unlock(&sc->block);
2368 }
2369 }
2370
2371
2372 /********************\
2373 * Interrupt handling *
2374 \********************/
2375
2376 static int
2377 ath5k_init(struct ath5k_softc *sc)
2378 {
2379 struct ath5k_hw *ah = sc->ah;
2380 int ret, i;
2381
2382 mutex_lock(&sc->lock);
2383
2384 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2385
2386 /*
2387 * Stop anything previously setup. This is safe
2388 * no matter this is the first time through or not.
2389 */
2390 ath5k_stop_locked(sc);
2391
2392 /* Set PHY calibration interval */
2393 ah->ah_cal_intval = ath5k_calinterval;
2394
2395 /*
2396 * The basic interface to setting the hardware in a good
2397 * state is ``reset''. On return the hardware is known to
2398 * be powered up and with interrupts disabled. This must
2399 * be followed by initialization of the appropriate bits
2400 * and then setup of the interrupt mask.
2401 */
2402 sc->curchan = sc->hw->conf.channel;
2403 sc->curband = &sc->sbands[sc->curchan->band];
2404 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2405 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2406 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_SWI;
2407 ret = ath5k_reset(sc, NULL);
2408 if (ret)
2409 goto done;
2410
2411 ath5k_rfkill_hw_start(ah);
2412
2413 /*
2414 * Reset the key cache since some parts do not reset the
2415 * contents on initial power up or resume from suspend.
2416 */
2417 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2418 ath5k_hw_reset_key(ah, i);
2419
2420 /* Set ack to be sent at low bit-rates */
2421 ath5k_hw_set_ack_bitrate_high(ah, false);
2422 ret = 0;
2423 done:
2424 mmiowb();
2425 mutex_unlock(&sc->lock);
2426 return ret;
2427 }
2428
2429 static int
2430 ath5k_stop_locked(struct ath5k_softc *sc)
2431 {
2432 struct ath5k_hw *ah = sc->ah;
2433
2434 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2435 test_bit(ATH_STAT_INVALID, sc->status));
2436
2437 /*
2438 * Shutdown the hardware and driver:
2439 * stop output from above
2440 * disable interrupts
2441 * turn off timers
2442 * turn off the radio
2443 * clear transmit machinery
2444 * clear receive machinery
2445 * drain and release tx queues
2446 * reclaim beacon resources
2447 * power down hardware
2448 *
2449 * Note that some of this work is not possible if the
2450 * hardware is gone (invalid).
2451 */
2452 ieee80211_stop_queues(sc->hw);
2453
2454 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2455 ath5k_led_off(sc);
2456 ath5k_hw_set_imr(ah, 0);
2457 synchronize_irq(sc->pdev->irq);
2458 }
2459 ath5k_txq_cleanup(sc);
2460 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2461 ath5k_rx_stop(sc);
2462 ath5k_hw_phy_disable(ah);
2463 } else
2464 sc->rxlink = NULL;
2465
2466 return 0;
2467 }
2468
2469 /*
2470 * Stop the device, grabbing the top-level lock to protect
2471 * against concurrent entry through ath5k_init (which can happen
2472 * if another thread does a system call and the thread doing the
2473 * stop is preempted).
2474 */
2475 static int
2476 ath5k_stop_hw(struct ath5k_softc *sc)
2477 {
2478 int ret;
2479
2480 mutex_lock(&sc->lock);
2481 ret = ath5k_stop_locked(sc);
2482 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2483 /*
2484 * Don't set the card in full sleep mode!
2485 *
2486 * a) When the device is in this state it must be carefully
2487 * woken up or references to registers in the PCI clock
2488 * domain may freeze the bus (and system). This varies
2489 * by chip and is mostly an issue with newer parts
2490 * (madwifi sources mentioned srev >= 0x78) that go to
2491 * sleep more quickly.
2492 *
2493 * b) On older chips full sleep results a weird behaviour
2494 * during wakeup. I tested various cards with srev < 0x78
2495 * and they don't wake up after module reload, a second
2496 * module reload is needed to bring the card up again.
2497 *
2498 * Until we figure out what's going on don't enable
2499 * full chip reset on any chip (this is what Legacy HAL
2500 * and Sam's HAL do anyway). Instead Perform a full reset
2501 * on the device (same as initial state after attach) and
2502 * leave it idle (keep MAC/BB on warm reset) */
2503 ret = ath5k_hw_on_hold(sc->ah);
2504
2505 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2506 "putting device to sleep\n");
2507 }
2508 ath5k_txbuf_free(sc, sc->bbuf);
2509
2510 mmiowb();
2511 mutex_unlock(&sc->lock);
2512
2513 tasklet_kill(&sc->rxtq);
2514 tasklet_kill(&sc->txtq);
2515 tasklet_kill(&sc->restq);
2516 tasklet_kill(&sc->calib);
2517 tasklet_kill(&sc->beacontq);
2518
2519 ath5k_rfkill_hw_stop(sc->ah);
2520
2521 return ret;
2522 }
2523
2524 static irqreturn_t
2525 ath5k_intr(int irq, void *dev_id)
2526 {
2527 struct ath5k_softc *sc = dev_id;
2528 struct ath5k_hw *ah = sc->ah;
2529 enum ath5k_int status;
2530 unsigned int counter = 1000;
2531
2532 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2533 !ath5k_hw_is_intr_pending(ah)))
2534 return IRQ_NONE;
2535
2536 do {
2537 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2538 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2539 status, sc->imask);
2540 if (unlikely(status & AR5K_INT_FATAL)) {
2541 /*
2542 * Fatal errors are unrecoverable.
2543 * Typically these are caused by DMA errors.
2544 */
2545 tasklet_schedule(&sc->restq);
2546 } else if (unlikely(status & AR5K_INT_RXORN)) {
2547 tasklet_schedule(&sc->restq);
2548 } else {
2549 if (status & AR5K_INT_SWBA) {
2550 tasklet_hi_schedule(&sc->beacontq);
2551 }
2552 if (status & AR5K_INT_RXEOL) {
2553 /*
2554 * NB: the hardware should re-read the link when
2555 * RXE bit is written, but it doesn't work at
2556 * least on older hardware revs.
2557 */
2558 sc->rxlink = NULL;
2559 }
2560 if (status & AR5K_INT_TXURN) {
2561 /* bump tx trigger level */
2562 ath5k_hw_update_tx_triglevel(ah, true);
2563 }
2564 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2565 tasklet_schedule(&sc->rxtq);
2566 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2567 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
2568 tasklet_schedule(&sc->txtq);
2569 if (status & AR5K_INT_BMISS) {
2570 /* TODO */
2571 }
2572 if (status & AR5K_INT_SWI) {
2573 tasklet_schedule(&sc->calib);
2574 }
2575 if (status & AR5K_INT_MIB) {
2576 /*
2577 * These stats are also used for ANI i think
2578 * so how about updating them more often ?
2579 */
2580 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
2581 }
2582 if (status & AR5K_INT_GPIO)
2583 tasklet_schedule(&sc->rf_kill.toggleq);
2584
2585 }
2586 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
2587
2588 if (unlikely(!counter))
2589 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2590
2591 ath5k_hw_calibration_poll(ah);
2592
2593 return IRQ_HANDLED;
2594 }
2595
2596 static void
2597 ath5k_tasklet_reset(unsigned long data)
2598 {
2599 struct ath5k_softc *sc = (void *)data;
2600
2601 ath5k_reset_wake(sc);
2602 }
2603
2604 /*
2605 * Periodically recalibrate the PHY to account
2606 * for temperature/environment changes.
2607 */
2608 static void
2609 ath5k_tasklet_calibrate(unsigned long data)
2610 {
2611 struct ath5k_softc *sc = (void *)data;
2612 struct ath5k_hw *ah = sc->ah;
2613
2614 /* Only full calibration for now */
2615 if (ah->ah_swi_mask != AR5K_SWI_FULL_CALIBRATION)
2616 return;
2617
2618 /* Stop queues so that calibration
2619 * doesn't interfere with tx */
2620 ieee80211_stop_queues(sc->hw);
2621
2622 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2623 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2624 sc->curchan->hw_value);
2625
2626 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2627 /*
2628 * Rfgain is out of bounds, reset the chip
2629 * to load new gain values.
2630 */
2631 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2632 ath5k_reset_wake(sc);
2633 }
2634 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2635 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2636 ieee80211_frequency_to_channel(
2637 sc->curchan->center_freq));
2638
2639 ah->ah_swi_mask = 0;
2640
2641 /* Wake queues */
2642 ieee80211_wake_queues(sc->hw);
2643
2644 }
2645
2646
2647 /********************\
2648 * Mac80211 functions *
2649 \********************/
2650
2651 static int
2652 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2653 {
2654 struct ath5k_softc *sc = hw->priv;
2655
2656 return ath5k_tx_queue(hw, skb, sc->txq);
2657 }
2658
2659 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
2660 struct ath5k_txq *txq)
2661 {
2662 struct ath5k_softc *sc = hw->priv;
2663 struct ath5k_buf *bf;
2664 unsigned long flags;
2665 int hdrlen;
2666 int padsize;
2667
2668 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2669
2670 if (sc->opmode == NL80211_IFTYPE_MONITOR)
2671 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2672
2673 /*
2674 * the hardware expects the header padded to 4 byte boundaries
2675 * if this is not the case we add the padding after the header
2676 */
2677 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2678 padsize = ath5k_pad_size(hdrlen);
2679 if (padsize) {
2680
2681 if (skb_headroom(skb) < padsize) {
2682 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2683 " headroom to pad %d\n", hdrlen, padsize);
2684 goto drop_packet;
2685 }
2686 skb_push(skb, padsize);
2687 memmove(skb->data, skb->data+padsize, hdrlen);
2688 }
2689
2690 spin_lock_irqsave(&sc->txbuflock, flags);
2691 if (list_empty(&sc->txbuf)) {
2692 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2693 spin_unlock_irqrestore(&sc->txbuflock, flags);
2694 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
2695 goto drop_packet;
2696 }
2697 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2698 list_del(&bf->list);
2699 sc->txbuf_len--;
2700 if (list_empty(&sc->txbuf))
2701 ieee80211_stop_queues(hw);
2702 spin_unlock_irqrestore(&sc->txbuflock, flags);
2703
2704 bf->skb = skb;
2705
2706 if (ath5k_txbuf_setup(sc, bf, txq)) {
2707 bf->skb = NULL;
2708 spin_lock_irqsave(&sc->txbuflock, flags);
2709 list_add_tail(&bf->list, &sc->txbuf);
2710 sc->txbuf_len++;
2711 spin_unlock_irqrestore(&sc->txbuflock, flags);
2712 goto drop_packet;
2713 }
2714 return NETDEV_TX_OK;
2715
2716 drop_packet:
2717 dev_kfree_skb_any(skb);
2718 return NETDEV_TX_OK;
2719 }
2720
2721 /*
2722 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2723 * and change to the given channel.
2724 */
2725 static int
2726 ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
2727 {
2728 struct ath5k_hw *ah = sc->ah;
2729 int ret;
2730
2731 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2732
2733 if (chan) {
2734 ath5k_hw_set_imr(ah, 0);
2735 ath5k_txq_cleanup(sc);
2736 ath5k_rx_stop(sc);
2737
2738 sc->curchan = chan;
2739 sc->curband = &sc->sbands[chan->band];
2740 }
2741 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL);
2742 if (ret) {
2743 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2744 goto err;
2745 }
2746
2747 ret = ath5k_rx_start(sc);
2748 if (ret) {
2749 ATH5K_ERR(sc, "can't start recv logic\n");
2750 goto err;
2751 }
2752
2753 /*
2754 * Change channels and update the h/w rate map if we're switching;
2755 * e.g. 11a to 11b/g.
2756 *
2757 * We may be doing a reset in response to an ioctl that changes the
2758 * channel so update any state that might change as a result.
2759 *
2760 * XXX needed?
2761 */
2762 /* ath5k_chan_change(sc, c); */
2763
2764 ath5k_beacon_config(sc);
2765 /* intrs are enabled by ath5k_beacon_config */
2766
2767 return 0;
2768 err:
2769 return ret;
2770 }
2771
2772 static int
2773 ath5k_reset_wake(struct ath5k_softc *sc)
2774 {
2775 int ret;
2776
2777 ret = ath5k_reset(sc, sc->curchan);
2778 if (!ret)
2779 ieee80211_wake_queues(sc->hw);
2780
2781 return ret;
2782 }
2783
2784 static int ath5k_start(struct ieee80211_hw *hw)
2785 {
2786 return ath5k_init(hw->priv);
2787 }
2788
2789 static void ath5k_stop(struct ieee80211_hw *hw)
2790 {
2791 ath5k_stop_hw(hw->priv);
2792 }
2793
2794 static int ath5k_add_interface(struct ieee80211_hw *hw,
2795 struct ieee80211_vif *vif)
2796 {
2797 struct ath5k_softc *sc = hw->priv;
2798 int ret;
2799
2800 mutex_lock(&sc->lock);
2801 if (sc->vif) {
2802 ret = 0;
2803 goto end;
2804 }
2805
2806 sc->vif = vif;
2807
2808 switch (vif->type) {
2809 case NL80211_IFTYPE_AP:
2810 case NL80211_IFTYPE_STATION:
2811 case NL80211_IFTYPE_ADHOC:
2812 case NL80211_IFTYPE_MESH_POINT:
2813 case NL80211_IFTYPE_MONITOR:
2814 sc->opmode = vif->type;
2815 break;
2816 default:
2817 ret = -EOPNOTSUPP;
2818 goto end;
2819 }
2820
2821 ath5k_hw_set_lladdr(sc->ah, vif->addr);
2822 ath5k_mode_setup(sc);
2823
2824 ret = 0;
2825 end:
2826 mutex_unlock(&sc->lock);
2827 return ret;
2828 }
2829
2830 static void
2831 ath5k_remove_interface(struct ieee80211_hw *hw,
2832 struct ieee80211_vif *vif)
2833 {
2834 struct ath5k_softc *sc = hw->priv;
2835 u8 mac[ETH_ALEN] = {};
2836
2837 mutex_lock(&sc->lock);
2838 if (sc->vif != vif)
2839 goto end;
2840
2841 ath5k_hw_set_lladdr(sc->ah, mac);
2842 sc->vif = NULL;
2843 end:
2844 mutex_unlock(&sc->lock);
2845 }
2846
2847 /*
2848 * TODO: Phy disable/diversity etc
2849 */
2850 static int
2851 ath5k_config(struct ieee80211_hw *hw, u32 changed)
2852 {
2853 struct ath5k_softc *sc = hw->priv;
2854 struct ath5k_hw *ah = sc->ah;
2855 struct ieee80211_conf *conf = &hw->conf;
2856 int ret = 0;
2857
2858 mutex_lock(&sc->lock);
2859
2860 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2861 ret = ath5k_chan_set(sc, conf->channel);
2862 if (ret < 0)
2863 goto unlock;
2864 }
2865
2866 if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
2867 (sc->power_level != conf->power_level)) {
2868 sc->power_level = conf->power_level;
2869
2870 /* Half dB steps */
2871 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
2872 }
2873
2874 /* TODO:
2875 * 1) Move this on config_interface and handle each case
2876 * separately eg. when we have only one STA vif, use
2877 * AR5K_ANTMODE_SINGLE_AP
2878 *
2879 * 2) Allow the user to change antenna mode eg. when only
2880 * one antenna is present
2881 *
2882 * 3) Allow the user to set default/tx antenna when possible
2883 *
2884 * 4) Default mode should handle 90% of the cases, together
2885 * with fixed a/b and single AP modes we should be able to
2886 * handle 99%. Sectored modes are extreme cases and i still
2887 * haven't found a usage for them. If we decide to support them,
2888 * then we must allow the user to set how many tx antennas we
2889 * have available
2890 */
2891 ath5k_hw_set_antenna_mode(ah, AR5K_ANTMODE_DEFAULT);
2892
2893 unlock:
2894 mutex_unlock(&sc->lock);
2895 return ret;
2896 }
2897
2898 static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
2899 int mc_count, struct dev_addr_list *mclist)
2900 {
2901 u32 mfilt[2], val;
2902 int i;
2903 u8 pos;
2904
2905 mfilt[0] = 0;
2906 mfilt[1] = 1;
2907
2908 for (i = 0; i < mc_count; i++) {
2909 if (!mclist)
2910 break;
2911 /* calculate XOR of eight 6-bit values */
2912 val = get_unaligned_le32(mclist->dmi_addr + 0);
2913 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2914 val = get_unaligned_le32(mclist->dmi_addr + 3);
2915 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2916 pos &= 0x3f;
2917 mfilt[pos / 32] |= (1 << (pos % 32));
2918 /* XXX: we might be able to just do this instead,
2919 * but not sure, needs testing, if we do use this we'd
2920 * neet to inform below to not reset the mcast */
2921 /* ath5k_hw_set_mcast_filterindex(ah,
2922 * mclist->dmi_addr[5]); */
2923 mclist = mclist->next;
2924 }
2925
2926 return ((u64)(mfilt[1]) << 32) | mfilt[0];
2927 }
2928
2929 #define SUPPORTED_FIF_FLAGS \
2930 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2931 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2932 FIF_BCN_PRBRESP_PROMISC
2933 /*
2934 * o always accept unicast, broadcast, and multicast traffic
2935 * o multicast traffic for all BSSIDs will be enabled if mac80211
2936 * says it should be
2937 * o maintain current state of phy ofdm or phy cck error reception.
2938 * If the hardware detects any of these type of errors then
2939 * ath5k_hw_get_rx_filter() will pass to us the respective
2940 * hardware filters to be able to receive these type of frames.
2941 * o probe request frames are accepted only when operating in
2942 * hostap, adhoc, or monitor modes
2943 * o enable promiscuous mode according to the interface state
2944 * o accept beacons:
2945 * - when operating in adhoc mode so the 802.11 layer creates
2946 * node table entries for peers,
2947 * - when operating in station mode for collecting rssi data when
2948 * the station is otherwise quiet, or
2949 * - when scanning
2950 */
2951 static void ath5k_configure_filter(struct ieee80211_hw *hw,
2952 unsigned int changed_flags,
2953 unsigned int *new_flags,
2954 u64 multicast)
2955 {
2956 struct ath5k_softc *sc = hw->priv;
2957 struct ath5k_hw *ah = sc->ah;
2958 u32 mfilt[2], rfilt;
2959
2960 mutex_lock(&sc->lock);
2961
2962 mfilt[0] = multicast;
2963 mfilt[1] = multicast >> 32;
2964
2965 /* Only deal with supported flags */
2966 changed_flags &= SUPPORTED_FIF_FLAGS;
2967 *new_flags &= SUPPORTED_FIF_FLAGS;
2968
2969 /* If HW detects any phy or radar errors, leave those filters on.
2970 * Also, always enable Unicast, Broadcasts and Multicast
2971 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2972 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2973 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2974 AR5K_RX_FILTER_MCAST);
2975
2976 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2977 if (*new_flags & FIF_PROMISC_IN_BSS) {
2978 rfilt |= AR5K_RX_FILTER_PROM;
2979 __set_bit(ATH_STAT_PROMISC, sc->status);
2980 } else {
2981 __clear_bit(ATH_STAT_PROMISC, sc->status);
2982 }
2983 }
2984
2985 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2986 if (*new_flags & FIF_ALLMULTI) {
2987 mfilt[0] = ~0;
2988 mfilt[1] = ~0;
2989 }
2990
2991 /* This is the best we can do */
2992 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2993 rfilt |= AR5K_RX_FILTER_PHYERR;
2994
2995 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2996 * and probes for any BSSID, this needs testing */
2997 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2998 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2999
3000 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
3001 * set we should only pass on control frames for this
3002 * station. This needs testing. I believe right now this
3003 * enables *all* control frames, which is OK.. but
3004 * but we should see if we can improve on granularity */
3005 if (*new_flags & FIF_CONTROL)
3006 rfilt |= AR5K_RX_FILTER_CONTROL;
3007
3008 /* Additional settings per mode -- this is per ath5k */
3009
3010 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
3011
3012 switch (sc->opmode) {
3013 case NL80211_IFTYPE_MESH_POINT:
3014 case NL80211_IFTYPE_MONITOR:
3015 rfilt |= AR5K_RX_FILTER_CONTROL |
3016 AR5K_RX_FILTER_BEACON |
3017 AR5K_RX_FILTER_PROBEREQ |
3018 AR5K_RX_FILTER_PROM;
3019 break;
3020 case NL80211_IFTYPE_AP:
3021 case NL80211_IFTYPE_ADHOC:
3022 rfilt |= AR5K_RX_FILTER_PROBEREQ |
3023 AR5K_RX_FILTER_BEACON;
3024 break;
3025 case NL80211_IFTYPE_STATION:
3026 if (sc->assoc)
3027 rfilt |= AR5K_RX_FILTER_BEACON;
3028 default:
3029 break;
3030 }
3031
3032 /* Set filters */
3033 ath5k_hw_set_rx_filter(ah, rfilt);
3034
3035 /* Set multicast bits */
3036 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
3037 /* Set the cached hw filter flags, this will alter actually
3038 * be set in HW */
3039 sc->filter_flags = rfilt;
3040
3041 mutex_unlock(&sc->lock);
3042 }
3043
3044 static int
3045 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3046 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3047 struct ieee80211_key_conf *key)
3048 {
3049 struct ath5k_softc *sc = hw->priv;
3050 struct ath5k_hw *ah = sc->ah;
3051 struct ath_common *common = ath5k_hw_common(ah);
3052 int ret = 0;
3053
3054 if (modparam_nohwcrypt)
3055 return -EOPNOTSUPP;
3056
3057 if (sc->opmode == NL80211_IFTYPE_AP)
3058 return -EOPNOTSUPP;
3059
3060 switch (key->alg) {
3061 case ALG_WEP:
3062 case ALG_TKIP:
3063 break;
3064 case ALG_CCMP:
3065 if (sc->ah->ah_aes_support)
3066 break;
3067
3068 return -EOPNOTSUPP;
3069 default:
3070 WARN_ON(1);
3071 return -EINVAL;
3072 }
3073
3074 mutex_lock(&sc->lock);
3075
3076 switch (cmd) {
3077 case SET_KEY:
3078 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
3079 sta ? sta->addr : NULL);
3080 if (ret) {
3081 ATH5K_ERR(sc, "can't set the key\n");
3082 goto unlock;
3083 }
3084 __set_bit(key->keyidx, common->keymap);
3085 key->hw_key_idx = key->keyidx;
3086 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
3087 IEEE80211_KEY_FLAG_GENERATE_MMIC);
3088 break;
3089 case DISABLE_KEY:
3090 ath5k_hw_reset_key(sc->ah, key->keyidx);
3091 __clear_bit(key->keyidx, common->keymap);
3092 break;
3093 default:
3094 ret = -EINVAL;
3095 goto unlock;
3096 }
3097
3098 unlock:
3099 mmiowb();
3100 mutex_unlock(&sc->lock);
3101 return ret;
3102 }
3103
3104 static int
3105 ath5k_get_stats(struct ieee80211_hw *hw,
3106 struct ieee80211_low_level_stats *stats)
3107 {
3108 struct ath5k_softc *sc = hw->priv;
3109 struct ath5k_hw *ah = sc->ah;
3110
3111 /* Force update */
3112 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
3113
3114 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3115
3116 return 0;
3117 }
3118
3119 static int
3120 ath5k_get_tx_stats(struct ieee80211_hw *hw,
3121 struct ieee80211_tx_queue_stats *stats)
3122 {
3123 struct ath5k_softc *sc = hw->priv;
3124
3125 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
3126
3127 return 0;
3128 }
3129
3130 static u64
3131 ath5k_get_tsf(struct ieee80211_hw *hw)
3132 {
3133 struct ath5k_softc *sc = hw->priv;
3134
3135 return ath5k_hw_get_tsf64(sc->ah);
3136 }
3137
3138 static void
3139 ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3140 {
3141 struct ath5k_softc *sc = hw->priv;
3142
3143 ath5k_hw_set_tsf64(sc->ah, tsf);
3144 }
3145
3146 static void
3147 ath5k_reset_tsf(struct ieee80211_hw *hw)
3148 {
3149 struct ath5k_softc *sc = hw->priv;
3150
3151 /*
3152 * in IBSS mode we need to update the beacon timers too.
3153 * this will also reset the TSF if we call it with 0
3154 */
3155 if (sc->opmode == NL80211_IFTYPE_ADHOC)
3156 ath5k_beacon_update_timers(sc, 0);
3157 else
3158 ath5k_hw_reset_tsf(sc->ah);
3159 }
3160
3161 /*
3162 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
3163 * this is called only once at config_bss time, for AP we do it every
3164 * SWBA interrupt so that the TIM will reflect buffered frames.
3165 *
3166 * Called with the beacon lock.
3167 */
3168 static int
3169 ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
3170 {
3171 int ret;
3172 struct ath5k_softc *sc = hw->priv;
3173 struct sk_buff *skb;
3174
3175 if (WARN_ON(!vif)) {
3176 ret = -EINVAL;
3177 goto out;
3178 }
3179
3180 skb = ieee80211_beacon_get(hw, vif);
3181
3182 if (!skb) {
3183 ret = -ENOMEM;
3184 goto out;
3185 }
3186
3187 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3188
3189 ath5k_txbuf_free(sc, sc->bbuf);
3190 sc->bbuf->skb = skb;
3191 ret = ath5k_beacon_setup(sc, sc->bbuf);
3192 if (ret)
3193 sc->bbuf->skb = NULL;
3194 out:
3195 return ret;
3196 }
3197
3198 static void
3199 set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3200 {
3201 struct ath5k_softc *sc = hw->priv;
3202 struct ath5k_hw *ah = sc->ah;
3203 u32 rfilt;
3204 rfilt = ath5k_hw_get_rx_filter(ah);
3205 if (enable)
3206 rfilt |= AR5K_RX_FILTER_BEACON;
3207 else
3208 rfilt &= ~AR5K_RX_FILTER_BEACON;
3209 ath5k_hw_set_rx_filter(ah, rfilt);
3210 sc->filter_flags = rfilt;
3211 }
3212
3213 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3214 struct ieee80211_vif *vif,
3215 struct ieee80211_bss_conf *bss_conf,
3216 u32 changes)
3217 {
3218 struct ath5k_softc *sc = hw->priv;
3219 struct ath5k_hw *ah = sc->ah;
3220 struct ath_common *common = ath5k_hw_common(ah);
3221 unsigned long flags;
3222
3223 mutex_lock(&sc->lock);
3224 if (WARN_ON(sc->vif != vif))
3225 goto unlock;
3226
3227 if (changes & BSS_CHANGED_BSSID) {
3228 /* Cache for later use during resets */
3229 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
3230 common->curaid = 0;
3231 ath5k_hw_set_associd(ah);
3232 mmiowb();
3233 }
3234
3235 if (changes & BSS_CHANGED_BEACON_INT)
3236 sc->bintval = bss_conf->beacon_int;
3237
3238 if (changes & BSS_CHANGED_ASSOC) {
3239 sc->assoc = bss_conf->assoc;
3240 if (sc->opmode == NL80211_IFTYPE_STATION)
3241 set_beacon_filter(hw, sc->assoc);
3242 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3243 AR5K_LED_ASSOC : AR5K_LED_INIT);
3244 if (bss_conf->assoc) {
3245 ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
3246 "Bss Info ASSOC %d, bssid: %pM\n",
3247 bss_conf->aid, common->curbssid);
3248 common->curaid = bss_conf->aid;
3249 ath5k_hw_set_associd(ah);
3250 /* Once ANI is available you would start it here */
3251 }
3252 }
3253
3254 if (changes & BSS_CHANGED_BEACON) {
3255 spin_lock_irqsave(&sc->block, flags);
3256 ath5k_beacon_update(hw, vif);
3257 spin_unlock_irqrestore(&sc->block, flags);
3258 }
3259
3260 if (changes & BSS_CHANGED_BEACON_ENABLED)
3261 sc->enable_beacon = bss_conf->enable_beacon;
3262
3263 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
3264 BSS_CHANGED_BEACON_INT))
3265 ath5k_beacon_config(sc);
3266
3267 unlock:
3268 mutex_unlock(&sc->lock);
3269 }
3270
3271 static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
3272 {
3273 struct ath5k_softc *sc = hw->priv;
3274 if (!sc->assoc)
3275 ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
3276 }
3277
3278 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
3279 {
3280 struct ath5k_softc *sc = hw->priv;
3281 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3282 AR5K_LED_ASSOC : AR5K_LED_INIT);
3283 }
3284
3285 /**
3286 * ath5k_set_coverage_class - Set IEEE 802.11 coverage class
3287 *
3288 * @hw: struct ieee80211_hw pointer
3289 * @coverage_class: IEEE 802.11 coverage class number
3290 *
3291 * Mac80211 callback. Sets slot time, ACK timeout and CTS timeout for given
3292 * coverage class. The values are persistent, they are restored after device
3293 * reset.
3294 */
3295 static void ath5k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
3296 {
3297 struct ath5k_softc *sc = hw->priv;
3298
3299 mutex_lock(&sc->lock);
3300 ath5k_hw_set_coverage_class(sc->ah, coverage_class);
3301 mutex_unlock(&sc->lock);
3302 }
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