2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <linux/slab.h>
19 #include <asm/unaligned.h>
24 #include "ar9003_mac.h"
26 static bool ath9k_hw_set_reset_reg(struct ath_hw
*ah
, u32 type
);
28 MODULE_AUTHOR("Atheros Communications");
29 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
30 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
31 MODULE_LICENSE("Dual BSD/GPL");
33 static int __init
ath9k_init(void)
37 module_init(ath9k_init
);
39 static void __exit
ath9k_exit(void)
43 module_exit(ath9k_exit
);
45 /* Private hardware callbacks */
47 static void ath9k_hw_init_cal_settings(struct ath_hw
*ah
)
49 ath9k_hw_private_ops(ah
)->init_cal_settings(ah
);
52 static void ath9k_hw_init_mode_regs(struct ath_hw
*ah
)
54 ath9k_hw_private_ops(ah
)->init_mode_regs(ah
);
57 static u32
ath9k_hw_compute_pll_control(struct ath_hw
*ah
,
58 struct ath9k_channel
*chan
)
60 return ath9k_hw_private_ops(ah
)->compute_pll_control(ah
, chan
);
63 static void ath9k_hw_init_mode_gain_regs(struct ath_hw
*ah
)
65 if (!ath9k_hw_private_ops(ah
)->init_mode_gain_regs
)
68 ath9k_hw_private_ops(ah
)->init_mode_gain_regs(ah
);
71 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw
*ah
)
73 /* You will not have this callback if using the old ANI */
74 if (!ath9k_hw_private_ops(ah
)->ani_cache_ini_regs
)
77 ath9k_hw_private_ops(ah
)->ani_cache_ini_regs(ah
);
80 /********************/
81 /* Helper Functions */
82 /********************/
84 static void ath9k_hw_set_clockrate(struct ath_hw
*ah
)
86 struct ieee80211_conf
*conf
= &ath9k_hw_common(ah
)->hw
->conf
;
87 struct ath_common
*common
= ath9k_hw_common(ah
);
88 unsigned int clockrate
;
90 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
91 if (AR_SREV_9287(ah
) && AR_SREV_9287_13_OR_LATER(ah
))
93 else if (!ah
->curchan
) /* should really check for CCK instead */
94 clockrate
= ATH9K_CLOCK_RATE_CCK
;
95 else if (conf
->channel
->band
== IEEE80211_BAND_2GHZ
)
96 clockrate
= ATH9K_CLOCK_RATE_2GHZ_OFDM
;
97 else if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_FASTCLOCK
)
98 clockrate
= ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM
;
100 clockrate
= ATH9K_CLOCK_RATE_5GHZ_OFDM
;
102 if (conf_is_ht40(conf
))
106 if (IS_CHAN_HALF_RATE(ah
->curchan
))
108 if (IS_CHAN_QUARTER_RATE(ah
->curchan
))
112 common
->clockrate
= clockrate
;
115 static u32
ath9k_hw_mac_to_clks(struct ath_hw
*ah
, u32 usecs
)
117 struct ath_common
*common
= ath9k_hw_common(ah
);
119 return usecs
* common
->clockrate
;
122 bool ath9k_hw_wait(struct ath_hw
*ah
, u32 reg
, u32 mask
, u32 val
, u32 timeout
)
126 BUG_ON(timeout
< AH_TIME_QUANTUM
);
128 for (i
= 0; i
< (timeout
/ AH_TIME_QUANTUM
); i
++) {
129 if ((REG_READ(ah
, reg
) & mask
) == val
)
132 udelay(AH_TIME_QUANTUM
);
135 ath_dbg(ath9k_hw_common(ah
), ATH_DBG_ANY
,
136 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
137 timeout
, reg
, REG_READ(ah
, reg
), mask
, val
);
141 EXPORT_SYMBOL(ath9k_hw_wait
);
143 void ath9k_hw_write_array(struct ath_hw
*ah
, struct ar5416IniArray
*array
,
144 int column
, unsigned int *writecnt
)
148 ENABLE_REGWRITE_BUFFER(ah
);
149 for (r
= 0; r
< array
->ia_rows
; r
++) {
150 REG_WRITE(ah
, INI_RA(array
, r
, 0),
151 INI_RA(array
, r
, column
));
154 REGWRITE_BUFFER_FLUSH(ah
);
157 u32
ath9k_hw_reverse_bits(u32 val
, u32 n
)
162 for (i
= 0, retval
= 0; i
< n
; i
++) {
163 retval
= (retval
<< 1) | (val
& 1);
169 u16
ath9k_hw_computetxtime(struct ath_hw
*ah
,
171 u32 frameLen
, u16 rateix
,
174 u32 bitsPerSymbol
, numBits
, numSymbols
, phyTime
, txTime
;
180 case WLAN_RC_PHY_CCK
:
181 phyTime
= CCK_PREAMBLE_BITS
+ CCK_PLCP_BITS
;
184 numBits
= frameLen
<< 3;
185 txTime
= CCK_SIFS_TIME
+ phyTime
+ ((numBits
* 1000) / kbps
);
187 case WLAN_RC_PHY_OFDM
:
188 if (ah
->curchan
&& IS_CHAN_QUARTER_RATE(ah
->curchan
)) {
189 bitsPerSymbol
= (kbps
* OFDM_SYMBOL_TIME_QUARTER
) / 1000;
190 numBits
= OFDM_PLCP_BITS
+ (frameLen
<< 3);
191 numSymbols
= DIV_ROUND_UP(numBits
, bitsPerSymbol
);
192 txTime
= OFDM_SIFS_TIME_QUARTER
193 + OFDM_PREAMBLE_TIME_QUARTER
194 + (numSymbols
* OFDM_SYMBOL_TIME_QUARTER
);
195 } else if (ah
->curchan
&&
196 IS_CHAN_HALF_RATE(ah
->curchan
)) {
197 bitsPerSymbol
= (kbps
* OFDM_SYMBOL_TIME_HALF
) / 1000;
198 numBits
= OFDM_PLCP_BITS
+ (frameLen
<< 3);
199 numSymbols
= DIV_ROUND_UP(numBits
, bitsPerSymbol
);
200 txTime
= OFDM_SIFS_TIME_HALF
+
201 OFDM_PREAMBLE_TIME_HALF
202 + (numSymbols
* OFDM_SYMBOL_TIME_HALF
);
204 bitsPerSymbol
= (kbps
* OFDM_SYMBOL_TIME
) / 1000;
205 numBits
= OFDM_PLCP_BITS
+ (frameLen
<< 3);
206 numSymbols
= DIV_ROUND_UP(numBits
, bitsPerSymbol
);
207 txTime
= OFDM_SIFS_TIME
+ OFDM_PREAMBLE_TIME
208 + (numSymbols
* OFDM_SYMBOL_TIME
);
212 ath_err(ath9k_hw_common(ah
),
213 "Unknown phy %u (rate ix %u)\n", phy
, rateix
);
220 EXPORT_SYMBOL(ath9k_hw_computetxtime
);
222 void ath9k_hw_get_channel_centers(struct ath_hw
*ah
,
223 struct ath9k_channel
*chan
,
224 struct chan_centers
*centers
)
228 if (!IS_CHAN_HT40(chan
)) {
229 centers
->ctl_center
= centers
->ext_center
=
230 centers
->synth_center
= chan
->channel
;
234 if ((chan
->chanmode
== CHANNEL_A_HT40PLUS
) ||
235 (chan
->chanmode
== CHANNEL_G_HT40PLUS
)) {
236 centers
->synth_center
=
237 chan
->channel
+ HT40_CHANNEL_CENTER_SHIFT
;
240 centers
->synth_center
=
241 chan
->channel
- HT40_CHANNEL_CENTER_SHIFT
;
245 centers
->ctl_center
=
246 centers
->synth_center
- (extoff
* HT40_CHANNEL_CENTER_SHIFT
);
247 /* 25 MHz spacing is supported by hw but not on upper layers */
248 centers
->ext_center
=
249 centers
->synth_center
+ (extoff
* HT40_CHANNEL_CENTER_SHIFT
);
256 static void ath9k_hw_read_revisions(struct ath_hw
*ah
)
260 switch (ah
->hw_version
.devid
) {
261 case AR5416_AR9100_DEVID
:
262 ah
->hw_version
.macVersion
= AR_SREV_VERSION_9100
;
264 case AR9300_DEVID_AR9330
:
265 ah
->hw_version
.macVersion
= AR_SREV_VERSION_9330
;
266 if (ah
->get_mac_revision
) {
267 ah
->hw_version
.macRev
= ah
->get_mac_revision();
269 val
= REG_READ(ah
, AR_SREV
);
270 ah
->hw_version
.macRev
= MS(val
, AR_SREV_REVISION2
);
273 case AR9300_DEVID_AR9340
:
274 ah
->hw_version
.macVersion
= AR_SREV_VERSION_9340
;
275 val
= REG_READ(ah
, AR_SREV
);
276 ah
->hw_version
.macRev
= MS(val
, AR_SREV_REVISION2
);
280 val
= REG_READ(ah
, AR_SREV
) & AR_SREV_ID
;
283 val
= REG_READ(ah
, AR_SREV
);
284 ah
->hw_version
.macVersion
=
285 (val
& AR_SREV_VERSION2
) >> AR_SREV_TYPE2_S
;
286 ah
->hw_version
.macRev
= MS(val
, AR_SREV_REVISION2
);
288 if (AR_SREV_9462(ah
))
289 ah
->is_pciexpress
= true;
291 ah
->is_pciexpress
= (val
&
292 AR_SREV_TYPE2_HOST_MODE
) ? 0 : 1;
294 if (!AR_SREV_9100(ah
))
295 ah
->hw_version
.macVersion
= MS(val
, AR_SREV_VERSION
);
297 ah
->hw_version
.macRev
= val
& AR_SREV_REVISION
;
299 if (ah
->hw_version
.macVersion
== AR_SREV_VERSION_5416_PCIE
)
300 ah
->is_pciexpress
= true;
304 /************************************/
305 /* HW Attach, Detach, Init Routines */
306 /************************************/
308 static void ath9k_hw_disablepcie(struct ath_hw
*ah
)
310 if (!AR_SREV_5416(ah
))
313 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x9248fc00);
314 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x24924924);
315 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x28000029);
316 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x57160824);
317 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x25980579);
318 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x00000000);
319 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x1aaabe40);
320 REG_WRITE(ah
, AR_PCIE_SERDES
, 0xbe105554);
321 REG_WRITE(ah
, AR_PCIE_SERDES
, 0x000e1007);
323 REG_WRITE(ah
, AR_PCIE_SERDES2
, 0x00000000);
326 static void ath9k_hw_aspm_init(struct ath_hw
*ah
)
328 struct ath_common
*common
= ath9k_hw_common(ah
);
330 if (common
->bus_ops
->aspm_init
)
331 common
->bus_ops
->aspm_init(common
);
334 /* This should work for all families including legacy */
335 static bool ath9k_hw_chip_test(struct ath_hw
*ah
)
337 struct ath_common
*common
= ath9k_hw_common(ah
);
338 u32 regAddr
[2] = { AR_STA_ID0
};
340 static const u32 patternData
[4] = {
341 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
345 if (!AR_SREV_9300_20_OR_LATER(ah
)) {
347 regAddr
[1] = AR_PHY_BASE
+ (8 << 2);
351 for (i
= 0; i
< loop_max
; i
++) {
352 u32 addr
= regAddr
[i
];
355 regHold
[i
] = REG_READ(ah
, addr
);
356 for (j
= 0; j
< 0x100; j
++) {
357 wrData
= (j
<< 16) | j
;
358 REG_WRITE(ah
, addr
, wrData
);
359 rdData
= REG_READ(ah
, addr
);
360 if (rdData
!= wrData
) {
362 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
363 addr
, wrData
, rdData
);
367 for (j
= 0; j
< 4; j
++) {
368 wrData
= patternData
[j
];
369 REG_WRITE(ah
, addr
, wrData
);
370 rdData
= REG_READ(ah
, addr
);
371 if (wrData
!= rdData
) {
373 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
374 addr
, wrData
, rdData
);
378 REG_WRITE(ah
, regAddr
[i
], regHold
[i
]);
385 static void ath9k_hw_init_config(struct ath_hw
*ah
)
389 ah
->config
.dma_beacon_response_time
= 2;
390 ah
->config
.sw_beacon_response_time
= 10;
391 ah
->config
.additional_swba_backoff
= 0;
392 ah
->config
.ack_6mb
= 0x0;
393 ah
->config
.cwm_ignore_extcca
= 0;
394 ah
->config
.pcie_clock_req
= 0;
395 ah
->config
.pcie_waen
= 0;
396 ah
->config
.analog_shiftreg
= 1;
397 ah
->config
.enable_ani
= true;
399 for (i
= 0; i
< AR_EEPROM_MODAL_SPURS
; i
++) {
400 ah
->config
.spurchans
[i
][0] = AR_NO_SPUR
;
401 ah
->config
.spurchans
[i
][1] = AR_NO_SPUR
;
404 /* PAPRD needs some more work to be enabled */
405 ah
->config
.paprd_disable
= 1;
407 ah
->config
.rx_intr_mitigation
= true;
408 ah
->config
.pcieSerDesWrite
= true;
411 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
412 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
413 * This means we use it for all AR5416 devices, and the few
414 * minor PCI AR9280 devices out there.
416 * Serialization is required because these devices do not handle
417 * well the case of two concurrent reads/writes due to the latency
418 * involved. During one read/write another read/write can be issued
419 * on another CPU while the previous read/write may still be working
420 * on our hardware, if we hit this case the hardware poops in a loop.
421 * We prevent this by serializing reads and writes.
423 * This issue is not present on PCI-Express devices or pre-AR5416
424 * devices (legacy, 802.11abg).
426 if (num_possible_cpus() > 1)
427 ah
->config
.serialize_regmode
= SER_REG_MODE_AUTO
;
430 static void ath9k_hw_init_defaults(struct ath_hw
*ah
)
432 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
434 regulatory
->country_code
= CTRY_DEFAULT
;
435 regulatory
->power_limit
= MAX_RATE_POWER
;
437 ah
->hw_version
.magic
= AR5416_MAGIC
;
438 ah
->hw_version
.subvendorid
= 0;
441 ah
->sta_id1_defaults
=
442 AR_STA_ID1_CRPT_MIC_ENABLE
|
443 AR_STA_ID1_MCAST_KSRCH
;
444 if (AR_SREV_9100(ah
))
445 ah
->sta_id1_defaults
|= AR_STA_ID1_AR9100_BA_FIX
;
446 ah
->enable_32kHz_clock
= DONT_USE_32KHZ
;
447 ah
->slottime
= ATH9K_SLOT_TIME_9
;
448 ah
->globaltxtimeout
= (u32
) -1;
449 ah
->power_mode
= ATH9K_PM_UNDEFINED
;
452 static int ath9k_hw_init_macaddr(struct ath_hw
*ah
)
454 struct ath_common
*common
= ath9k_hw_common(ah
);
458 static const u32 EEP_MAC
[] = { EEP_MAC_LSW
, EEP_MAC_MID
, EEP_MAC_MSW
};
461 for (i
= 0; i
< 3; i
++) {
462 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_MAC
[i
]);
464 common
->macaddr
[2 * i
] = eeval
>> 8;
465 common
->macaddr
[2 * i
+ 1] = eeval
& 0xff;
467 if (sum
== 0 || sum
== 0xffff * 3)
468 return -EADDRNOTAVAIL
;
473 static int ath9k_hw_post_init(struct ath_hw
*ah
)
475 struct ath_common
*common
= ath9k_hw_common(ah
);
478 if (common
->bus_ops
->ath_bus_type
!= ATH_USB
) {
479 if (!ath9k_hw_chip_test(ah
))
483 if (!AR_SREV_9300_20_OR_LATER(ah
)) {
484 ecode
= ar9002_hw_rf_claim(ah
);
489 ecode
= ath9k_hw_eeprom_init(ah
);
493 ath_dbg(ath9k_hw_common(ah
), ATH_DBG_CONFIG
,
494 "Eeprom VER: %d, REV: %d\n",
495 ah
->eep_ops
->get_eeprom_ver(ah
),
496 ah
->eep_ops
->get_eeprom_rev(ah
));
498 ecode
= ath9k_hw_rf_alloc_ext_banks(ah
);
500 ath_err(ath9k_hw_common(ah
),
501 "Failed allocating banks for external radio\n");
502 ath9k_hw_rf_free_ext_banks(ah
);
506 if (!AR_SREV_9100(ah
) && !AR_SREV_9340(ah
)) {
507 ath9k_hw_ani_setup(ah
);
508 ath9k_hw_ani_init(ah
);
514 static void ath9k_hw_attach_ops(struct ath_hw
*ah
)
516 if (AR_SREV_9300_20_OR_LATER(ah
))
517 ar9003_hw_attach_ops(ah
);
519 ar9002_hw_attach_ops(ah
);
522 /* Called for all hardware families */
523 static int __ath9k_hw_init(struct ath_hw
*ah
)
525 struct ath_common
*common
= ath9k_hw_common(ah
);
528 ath9k_hw_read_revisions(ah
);
531 * Read back AR_WA into a permanent copy and set bits 14 and 17.
532 * We need to do this to avoid RMW of this register. We cannot
533 * read the reg when chip is asleep.
535 ah
->WARegVal
= REG_READ(ah
, AR_WA
);
536 ah
->WARegVal
|= (AR_WA_D3_L1_DISABLE
|
537 AR_WA_ASPM_TIMER_BASED_DISABLE
);
539 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_POWER_ON
)) {
540 ath_err(common
, "Couldn't reset chip\n");
544 if (AR_SREV_9462(ah
))
545 ah
->WARegVal
&= ~AR_WA_D3_L1_DISABLE
;
547 ath9k_hw_init_defaults(ah
);
548 ath9k_hw_init_config(ah
);
550 ath9k_hw_attach_ops(ah
);
552 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
)) {
553 ath_err(common
, "Couldn't wakeup chip\n");
557 if (ah
->config
.serialize_regmode
== SER_REG_MODE_AUTO
) {
558 if (ah
->hw_version
.macVersion
== AR_SREV_VERSION_5416_PCI
||
559 ((AR_SREV_9160(ah
) || AR_SREV_9280(ah
)) &&
560 !ah
->is_pciexpress
)) {
561 ah
->config
.serialize_regmode
=
564 ah
->config
.serialize_regmode
=
569 ath_dbg(common
, ATH_DBG_RESET
, "serialize_regmode is %d\n",
570 ah
->config
.serialize_regmode
);
572 if (AR_SREV_9285(ah
) || AR_SREV_9271(ah
))
573 ah
->config
.max_txtrig_level
= MAX_TX_FIFO_THRESHOLD
>> 1;
575 ah
->config
.max_txtrig_level
= MAX_TX_FIFO_THRESHOLD
;
577 switch (ah
->hw_version
.macVersion
) {
578 case AR_SREV_VERSION_5416_PCI
:
579 case AR_SREV_VERSION_5416_PCIE
:
580 case AR_SREV_VERSION_9160
:
581 case AR_SREV_VERSION_9100
:
582 case AR_SREV_VERSION_9280
:
583 case AR_SREV_VERSION_9285
:
584 case AR_SREV_VERSION_9287
:
585 case AR_SREV_VERSION_9271
:
586 case AR_SREV_VERSION_9300
:
587 case AR_SREV_VERSION_9330
:
588 case AR_SREV_VERSION_9485
:
589 case AR_SREV_VERSION_9340
:
590 case AR_SREV_VERSION_9462
:
594 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
595 ah
->hw_version
.macVersion
, ah
->hw_version
.macRev
);
599 if (AR_SREV_9271(ah
) || AR_SREV_9100(ah
) || AR_SREV_9340(ah
) ||
601 ah
->is_pciexpress
= false;
603 ah
->hw_version
.phyRev
= REG_READ(ah
, AR_PHY_CHIP_ID
);
604 ath9k_hw_init_cal_settings(ah
);
606 ah
->ani_function
= ATH9K_ANI_ALL
;
607 if (AR_SREV_9280_20_OR_LATER(ah
) && !AR_SREV_9300_20_OR_LATER(ah
))
608 ah
->ani_function
&= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL
;
609 if (!AR_SREV_9300_20_OR_LATER(ah
))
610 ah
->ani_function
&= ~ATH9K_ANI_MRC_CCK
;
612 ath9k_hw_init_mode_regs(ah
);
614 if (!ah
->is_pciexpress
)
615 ath9k_hw_disablepcie(ah
);
617 if (!AR_SREV_9300_20_OR_LATER(ah
))
618 ar9002_hw_cck_chan14_spread(ah
);
620 r
= ath9k_hw_post_init(ah
);
624 ath9k_hw_init_mode_gain_regs(ah
);
625 r
= ath9k_hw_fill_cap_info(ah
);
629 if (ah
->is_pciexpress
)
630 ath9k_hw_aspm_init(ah
);
632 r
= ath9k_hw_init_macaddr(ah
);
634 ath_err(common
, "Failed to initialize MAC address\n");
638 if (AR_SREV_9285(ah
) || AR_SREV_9271(ah
))
639 ah
->tx_trig_level
= (AR_FTRIG_256B
>> AR_FTRIG_S
);
641 ah
->tx_trig_level
= (AR_FTRIG_512B
>> AR_FTRIG_S
);
643 if (AR_SREV_9330(ah
))
644 ah
->bb_watchdog_timeout_ms
= 85;
646 ah
->bb_watchdog_timeout_ms
= 25;
648 common
->state
= ATH_HW_INITIALIZED
;
653 int ath9k_hw_init(struct ath_hw
*ah
)
656 struct ath_common
*common
= ath9k_hw_common(ah
);
658 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
659 switch (ah
->hw_version
.devid
) {
660 case AR5416_DEVID_PCI
:
661 case AR5416_DEVID_PCIE
:
662 case AR5416_AR9100_DEVID
:
663 case AR9160_DEVID_PCI
:
664 case AR9280_DEVID_PCI
:
665 case AR9280_DEVID_PCIE
:
666 case AR9285_DEVID_PCIE
:
667 case AR9287_DEVID_PCI
:
668 case AR9287_DEVID_PCIE
:
669 case AR2427_DEVID_PCIE
:
670 case AR9300_DEVID_PCIE
:
671 case AR9300_DEVID_AR9485_PCIE
:
672 case AR9300_DEVID_AR9330
:
673 case AR9300_DEVID_AR9340
:
674 case AR9300_DEVID_AR9580
:
675 case AR9300_DEVID_AR9462
:
678 if (common
->bus_ops
->ath_bus_type
== ATH_USB
)
680 ath_err(common
, "Hardware device ID 0x%04x not supported\n",
681 ah
->hw_version
.devid
);
685 ret
= __ath9k_hw_init(ah
);
688 "Unable to initialize hardware; initialization status: %d\n",
695 EXPORT_SYMBOL(ath9k_hw_init
);
697 static void ath9k_hw_init_qos(struct ath_hw
*ah
)
699 ENABLE_REGWRITE_BUFFER(ah
);
701 REG_WRITE(ah
, AR_MIC_QOS_CONTROL
, 0x100aa);
702 REG_WRITE(ah
, AR_MIC_QOS_SELECT
, 0x3210);
704 REG_WRITE(ah
, AR_QOS_NO_ACK
,
705 SM(2, AR_QOS_NO_ACK_TWO_BIT
) |
706 SM(5, AR_QOS_NO_ACK_BIT_OFF
) |
707 SM(0, AR_QOS_NO_ACK_BYTE_OFF
));
709 REG_WRITE(ah
, AR_TXOP_X
, AR_TXOP_X_VAL
);
710 REG_WRITE(ah
, AR_TXOP_0_3
, 0xFFFFFFFF);
711 REG_WRITE(ah
, AR_TXOP_4_7
, 0xFFFFFFFF);
712 REG_WRITE(ah
, AR_TXOP_8_11
, 0xFFFFFFFF);
713 REG_WRITE(ah
, AR_TXOP_12_15
, 0xFFFFFFFF);
715 REGWRITE_BUFFER_FLUSH(ah
);
718 u32
ar9003_get_pll_sqsum_dvc(struct ath_hw
*ah
)
720 REG_CLR_BIT(ah
, PLL3
, PLL3_DO_MEAS_MASK
);
722 REG_SET_BIT(ah
, PLL3
, PLL3_DO_MEAS_MASK
);
724 while ((REG_READ(ah
, PLL4
) & PLL4_MEAS_DONE
) == 0)
727 return (REG_READ(ah
, PLL3
) & SQSUM_DVC_MASK
) >> 3;
729 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc
);
731 static void ath9k_hw_init_pll(struct ath_hw
*ah
,
732 struct ath9k_channel
*chan
)
736 if (AR_SREV_9485(ah
)) {
738 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
739 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL2
,
740 AR_CH0_BB_DPLL2_PLL_PWD
, 0x1);
741 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL2
,
742 AR_CH0_DPLL2_KD
, 0x40);
743 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL2
,
744 AR_CH0_DPLL2_KI
, 0x4);
746 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL1
,
747 AR_CH0_BB_DPLL1_REFDIV
, 0x5);
748 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL1
,
749 AR_CH0_BB_DPLL1_NINI
, 0x58);
750 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL1
,
751 AR_CH0_BB_DPLL1_NFRAC
, 0x0);
753 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL2
,
754 AR_CH0_BB_DPLL2_OUTDIV
, 0x1);
755 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL2
,
756 AR_CH0_BB_DPLL2_LOCAL_PLL
, 0x1);
757 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL2
,
758 AR_CH0_BB_DPLL2_EN_NEGTRIG
, 0x1);
760 /* program BB PLL phase_shift to 0x6 */
761 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL3
,
762 AR_CH0_BB_DPLL3_PHASE_SHIFT
, 0x6);
764 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL2
,
765 AR_CH0_BB_DPLL2_PLL_PWD
, 0x0);
767 } else if (AR_SREV_9330(ah
)) {
768 u32 ddr_dpll2
, pll_control2
, kd
;
770 if (ah
->is_clk_25mhz
) {
771 ddr_dpll2
= 0x18e82f01;
772 pll_control2
= 0xe04a3d;
775 ddr_dpll2
= 0x19e82f01;
776 pll_control2
= 0x886666;
780 /* program DDR PLL ki and kd value */
781 REG_WRITE(ah
, AR_CH0_DDR_DPLL2
, ddr_dpll2
);
783 /* program DDR PLL phase_shift */
784 REG_RMW_FIELD(ah
, AR_CH0_DDR_DPLL3
,
785 AR_CH0_DPLL3_PHASE_SHIFT
, 0x1);
787 REG_WRITE(ah
, AR_RTC_PLL_CONTROL
, 0x1142c);
790 /* program refdiv, nint, frac to RTC register */
791 REG_WRITE(ah
, AR_RTC_PLL_CONTROL2
, pll_control2
);
793 /* program BB PLL kd and ki value */
794 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL2
, AR_CH0_DPLL2_KD
, kd
);
795 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL2
, AR_CH0_DPLL2_KI
, 0x06);
797 /* program BB PLL phase_shift */
798 REG_RMW_FIELD(ah
, AR_CH0_BB_DPLL3
,
799 AR_CH0_BB_DPLL3_PHASE_SHIFT
, 0x1);
800 } else if (AR_SREV_9340(ah
)) {
801 u32 regval
, pll2_divint
, pll2_divfrac
, refdiv
;
803 REG_WRITE(ah
, AR_RTC_PLL_CONTROL
, 0x1142c);
806 REG_SET_BIT(ah
, AR_PHY_PLL_MODE
, 0x1 << 16);
809 if (ah
->is_clk_25mhz
) {
811 pll2_divfrac
= 0x1eb85;
819 regval
= REG_READ(ah
, AR_PHY_PLL_MODE
);
820 regval
|= (0x1 << 16);
821 REG_WRITE(ah
, AR_PHY_PLL_MODE
, regval
);
824 REG_WRITE(ah
, AR_PHY_PLL_CONTROL
, (refdiv
<< 27) |
825 (pll2_divint
<< 18) | pll2_divfrac
);
828 regval
= REG_READ(ah
, AR_PHY_PLL_MODE
);
829 regval
= (regval
& 0x80071fff) | (0x1 << 30) | (0x1 << 13) |
830 (0x4 << 26) | (0x18 << 19);
831 REG_WRITE(ah
, AR_PHY_PLL_MODE
, regval
);
832 REG_WRITE(ah
, AR_PHY_PLL_MODE
,
833 REG_READ(ah
, AR_PHY_PLL_MODE
) & 0xfffeffff);
837 pll
= ath9k_hw_compute_pll_control(ah
, chan
);
839 REG_WRITE(ah
, AR_RTC_PLL_CONTROL
, pll
);
841 if (AR_SREV_9485(ah
) || AR_SREV_9340(ah
) || AR_SREV_9330(ah
))
844 /* Switch the core clock for ar9271 to 117Mhz */
845 if (AR_SREV_9271(ah
)) {
847 REG_WRITE(ah
, 0x50040, 0x304);
850 udelay(RTC_PLL_SETTLE_DELAY
);
852 REG_WRITE(ah
, AR_RTC_SLEEP_CLK
, AR_RTC_FORCE_DERIVED_CLK
);
854 if (AR_SREV_9340(ah
)) {
855 if (ah
->is_clk_25mhz
) {
856 REG_WRITE(ah
, AR_RTC_DERIVED_CLK
, 0x17c << 1);
857 REG_WRITE(ah
, AR_SLP32_MODE
, 0x0010f3d7);
858 REG_WRITE(ah
, AR_SLP32_INC
, 0x0001e7ae);
860 REG_WRITE(ah
, AR_RTC_DERIVED_CLK
, 0x261 << 1);
861 REG_WRITE(ah
, AR_SLP32_MODE
, 0x0010f400);
862 REG_WRITE(ah
, AR_SLP32_INC
, 0x0001e800);
868 static void ath9k_hw_init_interrupt_masks(struct ath_hw
*ah
,
869 enum nl80211_iftype opmode
)
871 u32 sync_default
= AR_INTR_SYNC_DEFAULT
;
872 u32 imr_reg
= AR_IMR_TXERR
|
878 if (AR_SREV_9340(ah
))
879 sync_default
&= ~AR_INTR_SYNC_HOST1_FATAL
;
881 if (AR_SREV_9300_20_OR_LATER(ah
)) {
882 imr_reg
|= AR_IMR_RXOK_HP
;
883 if (ah
->config
.rx_intr_mitigation
)
884 imr_reg
|= AR_IMR_RXINTM
| AR_IMR_RXMINTR
;
886 imr_reg
|= AR_IMR_RXOK_LP
;
889 if (ah
->config
.rx_intr_mitigation
)
890 imr_reg
|= AR_IMR_RXINTM
| AR_IMR_RXMINTR
;
892 imr_reg
|= AR_IMR_RXOK
;
895 if (ah
->config
.tx_intr_mitigation
)
896 imr_reg
|= AR_IMR_TXINTM
| AR_IMR_TXMINTR
;
898 imr_reg
|= AR_IMR_TXOK
;
900 if (opmode
== NL80211_IFTYPE_AP
)
901 imr_reg
|= AR_IMR_MIB
;
903 ENABLE_REGWRITE_BUFFER(ah
);
905 REG_WRITE(ah
, AR_IMR
, imr_reg
);
906 ah
->imrs2_reg
|= AR_IMR_S2_GTT
;
907 REG_WRITE(ah
, AR_IMR_S2
, ah
->imrs2_reg
);
909 if (!AR_SREV_9100(ah
)) {
910 REG_WRITE(ah
, AR_INTR_SYNC_CAUSE
, 0xFFFFFFFF);
911 REG_WRITE(ah
, AR_INTR_SYNC_ENABLE
, sync_default
);
912 REG_WRITE(ah
, AR_INTR_SYNC_MASK
, 0);
915 REGWRITE_BUFFER_FLUSH(ah
);
917 if (AR_SREV_9300_20_OR_LATER(ah
)) {
918 REG_WRITE(ah
, AR_INTR_PRIO_ASYNC_ENABLE
, 0);
919 REG_WRITE(ah
, AR_INTR_PRIO_ASYNC_MASK
, 0);
920 REG_WRITE(ah
, AR_INTR_PRIO_SYNC_ENABLE
, 0);
921 REG_WRITE(ah
, AR_INTR_PRIO_SYNC_MASK
, 0);
925 static void ath9k_hw_set_sifs_time(struct ath_hw
*ah
, u32 us
)
927 u32 val
= ath9k_hw_mac_to_clks(ah
, us
- 2);
928 val
= min(val
, (u32
) 0xFFFF);
929 REG_WRITE(ah
, AR_D_GBL_IFS_SIFS
, val
);
932 static void ath9k_hw_setslottime(struct ath_hw
*ah
, u32 us
)
934 u32 val
= ath9k_hw_mac_to_clks(ah
, us
);
935 val
= min(val
, (u32
) 0xFFFF);
936 REG_WRITE(ah
, AR_D_GBL_IFS_SLOT
, val
);
939 static void ath9k_hw_set_ack_timeout(struct ath_hw
*ah
, u32 us
)
941 u32 val
= ath9k_hw_mac_to_clks(ah
, us
);
942 val
= min(val
, (u32
) MS(0xFFFFFFFF, AR_TIME_OUT_ACK
));
943 REG_RMW_FIELD(ah
, AR_TIME_OUT
, AR_TIME_OUT_ACK
, val
);
946 static void ath9k_hw_set_cts_timeout(struct ath_hw
*ah
, u32 us
)
948 u32 val
= ath9k_hw_mac_to_clks(ah
, us
);
949 val
= min(val
, (u32
) MS(0xFFFFFFFF, AR_TIME_OUT_CTS
));
950 REG_RMW_FIELD(ah
, AR_TIME_OUT
, AR_TIME_OUT_CTS
, val
);
953 static bool ath9k_hw_set_global_txtimeout(struct ath_hw
*ah
, u32 tu
)
956 ath_dbg(ath9k_hw_common(ah
), ATH_DBG_XMIT
,
957 "bad global tx timeout %u\n", tu
);
958 ah
->globaltxtimeout
= (u32
) -1;
961 REG_RMW_FIELD(ah
, AR_GTXTO
, AR_GTXTO_TIMEOUT_LIMIT
, tu
);
962 ah
->globaltxtimeout
= tu
;
967 void ath9k_hw_init_global_settings(struct ath_hw
*ah
)
969 struct ath_common
*common
= ath9k_hw_common(ah
);
970 struct ieee80211_conf
*conf
= &common
->hw
->conf
;
971 const struct ath9k_channel
*chan
= ah
->curchan
;
972 int acktimeout
, ctstimeout
;
975 int rx_lat
= 0, tx_lat
= 0, eifs
= 0;
978 ath_dbg(ath9k_hw_common(ah
), ATH_DBG_RESET
, "ah->misc_mode 0x%x\n",
984 if (ah
->misc_mode
!= 0)
985 REG_SET_BIT(ah
, AR_PCU_MISC
, ah
->misc_mode
);
987 if (IS_CHAN_A_FAST_CLOCK(ah
, chan
))
993 if (IS_CHAN_HALF_RATE(chan
)) {
997 if (IS_CHAN_A_FAST_CLOCK(ah
, chan
))
1002 } else if (IS_CHAN_QUARTER_RATE(chan
)) {
1004 rx_lat
= (rx_lat
* 4) - 1;
1006 if (IS_CHAN_A_FAST_CLOCK(ah
, chan
))
1012 if (AR_SREV_9287(ah
) && AR_SREV_9287_13_OR_LATER(ah
)) {
1013 eifs
= AR_D_GBL_IFS_EIFS_ASYNC_FIFO
;
1014 reg
= AR_USEC_ASYNC_FIFO
;
1016 eifs
= REG_READ(ah
, AR_D_GBL_IFS_EIFS
)/
1018 reg
= REG_READ(ah
, AR_USEC
);
1020 rx_lat
= MS(reg
, AR_USEC_RX_LAT
);
1021 tx_lat
= MS(reg
, AR_USEC_TX_LAT
);
1023 slottime
= ah
->slottime
;
1024 if (IS_CHAN_5GHZ(chan
))
1030 /* As defined by IEEE 802.11-2007 17.3.8.6 */
1031 acktimeout
= slottime
+ sifstime
+ 3 * ah
->coverage_class
;
1032 ctstimeout
= acktimeout
;
1035 * Workaround for early ACK timeouts, add an offset to match the
1036 * initval's 64us ack timeout value.
1037 * This was initially only meant to work around an issue with delayed
1038 * BA frames in some implementations, but it has been found to fix ACK
1039 * timeout issues in other cases as well.
1041 if (conf
->channel
&& conf
->channel
->band
== IEEE80211_BAND_2GHZ
)
1042 acktimeout
+= 64 - sifstime
- ah
->slottime
;
1044 ath9k_hw_set_sifs_time(ah
, sifstime
);
1045 ath9k_hw_setslottime(ah
, slottime
);
1046 ath9k_hw_set_ack_timeout(ah
, acktimeout
);
1047 ath9k_hw_set_cts_timeout(ah
, ctstimeout
);
1048 if (ah
->globaltxtimeout
!= (u32
) -1)
1049 ath9k_hw_set_global_txtimeout(ah
, ah
->globaltxtimeout
);
1051 REG_WRITE(ah
, AR_D_GBL_IFS_EIFS
, ath9k_hw_mac_to_clks(ah
, eifs
));
1052 REG_RMW(ah
, AR_USEC
,
1053 (common
->clockrate
- 1) |
1054 SM(rx_lat
, AR_USEC_RX_LAT
) |
1055 SM(tx_lat
, AR_USEC_TX_LAT
),
1056 AR_USEC_TX_LAT
| AR_USEC_RX_LAT
| AR_USEC_USEC
);
1059 EXPORT_SYMBOL(ath9k_hw_init_global_settings
);
1061 void ath9k_hw_deinit(struct ath_hw
*ah
)
1063 struct ath_common
*common
= ath9k_hw_common(ah
);
1065 if (common
->state
< ATH_HW_INITIALIZED
)
1068 ath9k_hw_setpower(ah
, ATH9K_PM_FULL_SLEEP
);
1071 ath9k_hw_rf_free_ext_banks(ah
);
1073 EXPORT_SYMBOL(ath9k_hw_deinit
);
1079 u32
ath9k_regd_get_ctl(struct ath_regulatory
*reg
, struct ath9k_channel
*chan
)
1081 u32 ctl
= ath_regd_get_band_ctl(reg
, chan
->chan
->band
);
1083 if (IS_CHAN_B(chan
))
1085 else if (IS_CHAN_G(chan
))
1093 /****************************************/
1094 /* Reset and Channel Switching Routines */
1095 /****************************************/
1097 static inline void ath9k_hw_set_dma(struct ath_hw
*ah
)
1099 struct ath_common
*common
= ath9k_hw_common(ah
);
1101 ENABLE_REGWRITE_BUFFER(ah
);
1104 * set AHB_MODE not to do cacheline prefetches
1106 if (!AR_SREV_9300_20_OR_LATER(ah
))
1107 REG_SET_BIT(ah
, AR_AHB_MODE
, AR_AHB_PREFETCH_RD_EN
);
1110 * let mac dma reads be in 128 byte chunks
1112 REG_RMW(ah
, AR_TXCFG
, AR_TXCFG_DMASZ_128B
, AR_TXCFG_DMASZ_MASK
);
1114 REGWRITE_BUFFER_FLUSH(ah
);
1117 * Restore TX Trigger Level to its pre-reset value.
1118 * The initial value depends on whether aggregation is enabled, and is
1119 * adjusted whenever underruns are detected.
1121 if (!AR_SREV_9300_20_OR_LATER(ah
))
1122 REG_RMW_FIELD(ah
, AR_TXCFG
, AR_FTRIG
, ah
->tx_trig_level
);
1124 ENABLE_REGWRITE_BUFFER(ah
);
1127 * let mac dma writes be in 128 byte chunks
1129 REG_RMW(ah
, AR_RXCFG
, AR_RXCFG_DMASZ_128B
, AR_RXCFG_DMASZ_MASK
);
1132 * Setup receive FIFO threshold to hold off TX activities
1134 REG_WRITE(ah
, AR_RXFIFO_CFG
, 0x200);
1136 if (AR_SREV_9300_20_OR_LATER(ah
)) {
1137 REG_RMW_FIELD(ah
, AR_RXBP_THRESH
, AR_RXBP_THRESH_HP
, 0x1);
1138 REG_RMW_FIELD(ah
, AR_RXBP_THRESH
, AR_RXBP_THRESH_LP
, 0x1);
1140 ath9k_hw_set_rx_bufsize(ah
, common
->rx_bufsize
-
1141 ah
->caps
.rx_status_len
);
1145 * reduce the number of usable entries in PCU TXBUF to avoid
1146 * wrap around issues.
1148 if (AR_SREV_9285(ah
)) {
1149 /* For AR9285 the number of Fifos are reduced to half.
1150 * So set the usable tx buf size also to half to
1151 * avoid data/delimiter underruns
1153 REG_WRITE(ah
, AR_PCU_TXBUF_CTRL
,
1154 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE
);
1155 } else if (!AR_SREV_9271(ah
)) {
1156 REG_WRITE(ah
, AR_PCU_TXBUF_CTRL
,
1157 AR_PCU_TXBUF_CTRL_USABLE_SIZE
);
1160 REGWRITE_BUFFER_FLUSH(ah
);
1162 if (AR_SREV_9300_20_OR_LATER(ah
))
1163 ath9k_hw_reset_txstatus_ring(ah
);
1166 static void ath9k_hw_set_operating_mode(struct ath_hw
*ah
, int opmode
)
1168 u32 mask
= AR_STA_ID1_STA_AP
| AR_STA_ID1_ADHOC
;
1169 u32 set
= AR_STA_ID1_KSRCH_MODE
;
1172 case NL80211_IFTYPE_ADHOC
:
1173 case NL80211_IFTYPE_MESH_POINT
:
1174 set
|= AR_STA_ID1_ADHOC
;
1175 REG_SET_BIT(ah
, AR_CFG
, AR_CFG_AP_ADHOC_INDICATION
);
1177 case NL80211_IFTYPE_AP
:
1178 set
|= AR_STA_ID1_STA_AP
;
1180 case NL80211_IFTYPE_STATION
:
1181 REG_CLR_BIT(ah
, AR_CFG
, AR_CFG_AP_ADHOC_INDICATION
);
1184 if (!ah
->is_monitoring
)
1188 REG_RMW(ah
, AR_STA_ID1
, set
, mask
);
1191 void ath9k_hw_get_delta_slope_vals(struct ath_hw
*ah
, u32 coef_scaled
,
1192 u32
*coef_mantissa
, u32
*coef_exponent
)
1194 u32 coef_exp
, coef_man
;
1196 for (coef_exp
= 31; coef_exp
> 0; coef_exp
--)
1197 if ((coef_scaled
>> coef_exp
) & 0x1)
1200 coef_exp
= 14 - (coef_exp
- COEF_SCALE_S
);
1202 coef_man
= coef_scaled
+ (1 << (COEF_SCALE_S
- coef_exp
- 1));
1204 *coef_mantissa
= coef_man
>> (COEF_SCALE_S
- coef_exp
);
1205 *coef_exponent
= coef_exp
- 16;
1208 static bool ath9k_hw_set_reset(struct ath_hw
*ah
, int type
)
1213 if (AR_SREV_9100(ah
)) {
1214 REG_RMW_FIELD(ah
, AR_RTC_DERIVED_CLK
,
1215 AR_RTC_DERIVED_CLK_PERIOD
, 1);
1216 (void)REG_READ(ah
, AR_RTC_DERIVED_CLK
);
1219 ENABLE_REGWRITE_BUFFER(ah
);
1221 if (AR_SREV_9300_20_OR_LATER(ah
)) {
1222 REG_WRITE(ah
, AR_WA
, ah
->WARegVal
);
1226 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
, AR_RTC_FORCE_WAKE_EN
|
1227 AR_RTC_FORCE_WAKE_ON_INT
);
1229 if (AR_SREV_9100(ah
)) {
1230 rst_flags
= AR_RTC_RC_MAC_WARM
| AR_RTC_RC_MAC_COLD
|
1231 AR_RTC_RC_COLD_RESET
| AR_RTC_RC_WARM_RESET
;
1233 tmpReg
= REG_READ(ah
, AR_INTR_SYNC_CAUSE
);
1235 (AR_INTR_SYNC_LOCAL_TIMEOUT
|
1236 AR_INTR_SYNC_RADM_CPL_TIMEOUT
)) {
1238 REG_WRITE(ah
, AR_INTR_SYNC_ENABLE
, 0);
1241 if (!AR_SREV_9300_20_OR_LATER(ah
))
1243 REG_WRITE(ah
, AR_RC
, val
);
1245 } else if (!AR_SREV_9300_20_OR_LATER(ah
))
1246 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
);
1248 rst_flags
= AR_RTC_RC_MAC_WARM
;
1249 if (type
== ATH9K_RESET_COLD
)
1250 rst_flags
|= AR_RTC_RC_MAC_COLD
;
1253 if (AR_SREV_9330(ah
)) {
1258 * call external reset function to reset WMAC if:
1259 * - doing a cold reset
1260 * - we have pending frames in the TX queues
1263 for (i
= 0; i
< AR_NUM_QCU
; i
++) {
1264 npend
= ath9k_hw_numtxpending(ah
, i
);
1269 if (ah
->external_reset
&&
1270 (npend
|| type
== ATH9K_RESET_COLD
)) {
1273 ath_dbg(ath9k_hw_common(ah
), ATH_DBG_RESET
,
1274 "reset MAC via external reset\n");
1276 reset_err
= ah
->external_reset();
1278 ath_err(ath9k_hw_common(ah
),
1279 "External reset failed, err=%d\n",
1284 REG_WRITE(ah
, AR_RTC_RESET
, 1);
1288 REG_WRITE(ah
, AR_RTC_RC
, rst_flags
);
1290 REGWRITE_BUFFER_FLUSH(ah
);
1294 REG_WRITE(ah
, AR_RTC_RC
, 0);
1295 if (!ath9k_hw_wait(ah
, AR_RTC_RC
, AR_RTC_RC_M
, 0, AH_WAIT_TIMEOUT
)) {
1296 ath_dbg(ath9k_hw_common(ah
), ATH_DBG_RESET
,
1297 "RTC stuck in MAC reset\n");
1301 if (!AR_SREV_9100(ah
))
1302 REG_WRITE(ah
, AR_RC
, 0);
1304 if (AR_SREV_9100(ah
))
1310 static bool ath9k_hw_set_reset_power_on(struct ath_hw
*ah
)
1312 ENABLE_REGWRITE_BUFFER(ah
);
1314 if (AR_SREV_9300_20_OR_LATER(ah
)) {
1315 REG_WRITE(ah
, AR_WA
, ah
->WARegVal
);
1319 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
, AR_RTC_FORCE_WAKE_EN
|
1320 AR_RTC_FORCE_WAKE_ON_INT
);
1322 if (!AR_SREV_9100(ah
) && !AR_SREV_9300_20_OR_LATER(ah
))
1323 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
);
1325 REG_WRITE(ah
, AR_RTC_RESET
, 0);
1327 REGWRITE_BUFFER_FLUSH(ah
);
1329 if (!AR_SREV_9300_20_OR_LATER(ah
))
1332 if (!AR_SREV_9100(ah
) && !AR_SREV_9300_20_OR_LATER(ah
))
1333 REG_WRITE(ah
, AR_RC
, 0);
1335 REG_WRITE(ah
, AR_RTC_RESET
, 1);
1337 if (!ath9k_hw_wait(ah
,
1342 ath_dbg(ath9k_hw_common(ah
), ATH_DBG_RESET
,
1343 "RTC not waking up\n");
1347 return ath9k_hw_set_reset(ah
, ATH9K_RESET_WARM
);
1350 static bool ath9k_hw_set_reset_reg(struct ath_hw
*ah
, u32 type
)
1353 if (AR_SREV_9300_20_OR_LATER(ah
)) {
1354 REG_WRITE(ah
, AR_WA
, ah
->WARegVal
);
1358 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
,
1359 AR_RTC_FORCE_WAKE_EN
| AR_RTC_FORCE_WAKE_ON_INT
);
1362 case ATH9K_RESET_POWER_ON
:
1363 return ath9k_hw_set_reset_power_on(ah
);
1364 case ATH9K_RESET_WARM
:
1365 case ATH9K_RESET_COLD
:
1366 return ath9k_hw_set_reset(ah
, type
);
1372 static bool ath9k_hw_chip_reset(struct ath_hw
*ah
,
1373 struct ath9k_channel
*chan
)
1375 if (AR_SREV_9280(ah
) && ah
->eep_ops
->get_eeprom(ah
, EEP_OL_PWRCTRL
)) {
1376 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_POWER_ON
))
1378 } else if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_WARM
))
1381 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
))
1384 ah
->chip_fullsleep
= false;
1385 ath9k_hw_init_pll(ah
, chan
);
1386 ath9k_hw_set_rfmode(ah
, chan
);
1391 static bool ath9k_hw_channel_change(struct ath_hw
*ah
,
1392 struct ath9k_channel
*chan
)
1394 struct ath_common
*common
= ath9k_hw_common(ah
);
1397 bool edma
= !!(ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
);
1398 bool band_switch
, mode_diff
;
1401 band_switch
= (chan
->channelFlags
& (CHANNEL_2GHZ
| CHANNEL_5GHZ
)) !=
1402 (ah
->curchan
->channelFlags
& (CHANNEL_2GHZ
|
1404 mode_diff
= (chan
->chanmode
!= ah
->curchan
->chanmode
);
1406 for (qnum
= 0; qnum
< AR_NUM_QCU
; qnum
++) {
1407 if (ath9k_hw_numtxpending(ah
, qnum
)) {
1408 ath_dbg(common
, ATH_DBG_QUEUE
,
1409 "Transmit frames pending on queue %d\n", qnum
);
1414 if (!ath9k_hw_rfbus_req(ah
)) {
1415 ath_err(common
, "Could not kill baseband RX\n");
1419 if (edma
&& (band_switch
|| mode_diff
)) {
1420 ath9k_hw_mark_phy_inactive(ah
);
1423 ath9k_hw_init_pll(ah
, NULL
);
1425 if (ath9k_hw_fast_chan_change(ah
, chan
, &ini_reloaded
)) {
1426 ath_err(common
, "Failed to do fast channel change\n");
1431 ath9k_hw_set_channel_regs(ah
, chan
);
1433 r
= ath9k_hw_rf_set_freq(ah
, chan
);
1435 ath_err(common
, "Failed to set channel\n");
1438 ath9k_hw_set_clockrate(ah
);
1439 ath9k_hw_apply_txpower(ah
, chan
);
1440 ath9k_hw_rfbus_done(ah
);
1442 if (IS_CHAN_OFDM(chan
) || IS_CHAN_HT(chan
))
1443 ath9k_hw_set_delta_slope(ah
, chan
);
1445 ath9k_hw_spur_mitigate_freq(ah
, chan
);
1447 if (edma
&& (band_switch
|| mode_diff
)) {
1448 ah
->ah_flags
|= AH_FASTCC
;
1449 if (band_switch
|| ini_reloaded
)
1450 ah
->eep_ops
->set_board_values(ah
, chan
);
1452 ath9k_hw_init_bb(ah
, chan
);
1454 if (band_switch
|| ini_reloaded
)
1455 ath9k_hw_init_cal(ah
, chan
);
1456 ah
->ah_flags
&= ~AH_FASTCC
;
1462 static void ath9k_hw_apply_gpio_override(struct ath_hw
*ah
)
1464 u32 gpio_mask
= ah
->gpio_mask
;
1467 for (i
= 0; gpio_mask
; i
++, gpio_mask
>>= 1) {
1468 if (!(gpio_mask
& 1))
1471 ath9k_hw_cfg_output(ah
, i
, AR_GPIO_OUTPUT_MUX_AS_OUTPUT
);
1472 ath9k_hw_set_gpio(ah
, i
, !!(ah
->gpio_val
& BIT(i
)));
1476 bool ath9k_hw_check_alive(struct ath_hw
*ah
)
1481 if (AR_SREV_9285_12_OR_LATER(ah
))
1485 reg
= REG_READ(ah
, AR_OBS_BUS_1
);
1487 if ((reg
& 0x7E7FFFEF) == 0x00702400)
1490 switch (reg
& 0x7E000B00) {
1498 } while (count
-- > 0);
1502 EXPORT_SYMBOL(ath9k_hw_check_alive
);
1504 int ath9k_hw_reset(struct ath_hw
*ah
, struct ath9k_channel
*chan
,
1505 struct ath9k_hw_cal_data
*caldata
, bool bChannelChange
)
1507 struct ath_common
*common
= ath9k_hw_common(ah
);
1509 struct ath9k_channel
*curchan
= ah
->curchan
;
1514 bool allow_fbs
= false;
1516 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
))
1519 if (curchan
&& !ah
->chip_fullsleep
)
1520 ath9k_hw_getnf(ah
, curchan
);
1522 ah
->caldata
= caldata
;
1524 (chan
->channel
!= caldata
->channel
||
1525 (chan
->channelFlags
& ~CHANNEL_CW_INT
) !=
1526 (caldata
->channelFlags
& ~CHANNEL_CW_INT
))) {
1527 /* Operating channel changed, reset channel calibration data */
1528 memset(caldata
, 0, sizeof(*caldata
));
1529 ath9k_init_nfcal_hist_buffer(ah
, chan
);
1531 ah
->noise
= ath9k_hw_getchan_noise(ah
, chan
);
1533 if (AR_SREV_9280(ah
) && common
->bus_ops
->ath_bus_type
== ATH_PCI
)
1534 bChannelChange
= false;
1537 caldata
->done_txiqcal_once
&&
1538 caldata
->done_txclcal_once
&&
1539 caldata
->rtt_hist
.num_readings
)
1542 if (bChannelChange
&&
1543 (ah
->chip_fullsleep
!= true) &&
1544 (ah
->curchan
!= NULL
) &&
1545 (chan
->channel
!= ah
->curchan
->channel
) &&
1547 ((chan
->channelFlags
& CHANNEL_ALL
) ==
1548 (ah
->curchan
->channelFlags
& CHANNEL_ALL
)))) {
1549 if (ath9k_hw_channel_change(ah
, chan
)) {
1550 ath9k_hw_loadnf(ah
, ah
->curchan
);
1551 ath9k_hw_start_nfcal(ah
, true);
1552 if (AR_SREV_9271(ah
))
1553 ar9002_hw_load_ani_reg(ah
, chan
);
1558 saveDefAntenna
= REG_READ(ah
, AR_DEF_ANTENNA
);
1559 if (saveDefAntenna
== 0)
1562 macStaId1
= REG_READ(ah
, AR_STA_ID1
) & AR_STA_ID1_BASE_RATE_11B
;
1564 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1565 if (AR_SREV_9100(ah
) ||
1566 (AR_SREV_9280(ah
) && ah
->eep_ops
->get_eeprom(ah
, EEP_OL_PWRCTRL
)))
1567 tsf
= ath9k_hw_gettsf64(ah
);
1569 saveLedState
= REG_READ(ah
, AR_CFG_LED
) &
1570 (AR_CFG_LED_ASSOC_CTL
| AR_CFG_LED_MODE_SEL
|
1571 AR_CFG_LED_BLINK_THRESH_SEL
| AR_CFG_LED_BLINK_SLOW
);
1573 ath9k_hw_mark_phy_inactive(ah
);
1575 ah
->paprd_table_write_done
= false;
1577 /* Only required on the first reset */
1578 if (AR_SREV_9271(ah
) && ah
->htc_reset_init
) {
1580 AR9271_RESET_POWER_DOWN_CONTROL
,
1581 AR9271_RADIO_RF_RST
);
1585 if (!ath9k_hw_chip_reset(ah
, chan
)) {
1586 ath_err(common
, "Chip reset failed\n");
1590 /* Only required on the first reset */
1591 if (AR_SREV_9271(ah
) && ah
->htc_reset_init
) {
1592 ah
->htc_reset_init
= false;
1594 AR9271_RESET_POWER_DOWN_CONTROL
,
1595 AR9271_GATE_MAC_CTL
);
1601 ath9k_hw_settsf64(ah
, tsf
);
1603 if (AR_SREV_9280_20_OR_LATER(ah
))
1604 REG_SET_BIT(ah
, AR_GPIO_INPUT_EN_VAL
, AR_GPIO_JTAG_DISABLE
);
1606 if (!AR_SREV_9300_20_OR_LATER(ah
))
1607 ar9002_hw_enable_async_fifo(ah
);
1609 r
= ath9k_hw_process_ini(ah
, chan
);
1614 * Some AR91xx SoC devices frequently fail to accept TSF writes
1615 * right after the chip reset. When that happens, write a new
1616 * value after the initvals have been applied, with an offset
1617 * based on measured time difference
1619 if (AR_SREV_9100(ah
) && (ath9k_hw_gettsf64(ah
) < tsf
)) {
1621 ath9k_hw_settsf64(ah
, tsf
);
1624 /* Setup MFP options for CCMP */
1625 if (AR_SREV_9280_20_OR_LATER(ah
)) {
1626 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1627 * frames when constructing CCMP AAD. */
1628 REG_RMW_FIELD(ah
, AR_AES_MUTE_MASK1
, AR_AES_MUTE_MASK1_FC_MGMT
,
1630 ah
->sw_mgmt_crypto
= false;
1631 } else if (AR_SREV_9160_10_OR_LATER(ah
)) {
1632 /* Disable hardware crypto for management frames */
1633 REG_CLR_BIT(ah
, AR_PCU_MISC_MODE2
,
1634 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE
);
1635 REG_SET_BIT(ah
, AR_PCU_MISC_MODE2
,
1636 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT
);
1637 ah
->sw_mgmt_crypto
= true;
1639 ah
->sw_mgmt_crypto
= true;
1641 if (IS_CHAN_OFDM(chan
) || IS_CHAN_HT(chan
))
1642 ath9k_hw_set_delta_slope(ah
, chan
);
1644 ath9k_hw_spur_mitigate_freq(ah
, chan
);
1645 ah
->eep_ops
->set_board_values(ah
, chan
);
1647 ENABLE_REGWRITE_BUFFER(ah
);
1649 REG_WRITE(ah
, AR_STA_ID0
, get_unaligned_le32(common
->macaddr
));
1650 REG_WRITE(ah
, AR_STA_ID1
, get_unaligned_le16(common
->macaddr
+ 4)
1652 | AR_STA_ID1_RTS_USE_DEF
1654 ack_6mb
? AR_STA_ID1_ACKCTS_6MB
: 0)
1655 | ah
->sta_id1_defaults
);
1656 ath_hw_setbssidmask(common
);
1657 REG_WRITE(ah
, AR_DEF_ANTENNA
, saveDefAntenna
);
1658 ath9k_hw_write_associd(ah
);
1659 REG_WRITE(ah
, AR_ISR
, ~0);
1660 REG_WRITE(ah
, AR_RSSI_THR
, INIT_RSSI_THR
);
1662 REGWRITE_BUFFER_FLUSH(ah
);
1664 ath9k_hw_set_operating_mode(ah
, ah
->opmode
);
1666 r
= ath9k_hw_rf_set_freq(ah
, chan
);
1670 ath9k_hw_set_clockrate(ah
);
1672 ENABLE_REGWRITE_BUFFER(ah
);
1674 for (i
= 0; i
< AR_NUM_DCU
; i
++)
1675 REG_WRITE(ah
, AR_DQCUMASK(i
), 1 << i
);
1677 REGWRITE_BUFFER_FLUSH(ah
);
1680 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++)
1681 ath9k_hw_resettxqueue(ah
, i
);
1683 ath9k_hw_init_interrupt_masks(ah
, ah
->opmode
);
1684 ath9k_hw_ani_cache_ini_regs(ah
);
1685 ath9k_hw_init_qos(ah
);
1687 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_RFSILENT
)
1688 ath9k_hw_cfg_gpio_input(ah
, ah
->rfkill_gpio
);
1690 ath9k_hw_init_global_settings(ah
);
1692 if (AR_SREV_9287(ah
) && AR_SREV_9287_13_OR_LATER(ah
)) {
1693 REG_SET_BIT(ah
, AR_MAC_PCU_LOGIC_ANALYZER
,
1694 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768
);
1695 REG_RMW_FIELD(ah
, AR_AHB_MODE
, AR_AHB_CUSTOM_BURST_EN
,
1696 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL
);
1697 REG_SET_BIT(ah
, AR_PCU_MISC_MODE2
,
1698 AR_PCU_MISC_MODE2_ENABLE_AGGWEP
);
1701 REG_SET_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PRESERVE_SEQNUM
);
1703 ath9k_hw_set_dma(ah
);
1705 REG_WRITE(ah
, AR_OBS
, 8);
1707 if (ah
->config
.rx_intr_mitigation
) {
1708 REG_RMW_FIELD(ah
, AR_RIMT
, AR_RIMT_LAST
, 500);
1709 REG_RMW_FIELD(ah
, AR_RIMT
, AR_RIMT_FIRST
, 2000);
1712 if (ah
->config
.tx_intr_mitigation
) {
1713 REG_RMW_FIELD(ah
, AR_TIMT
, AR_TIMT_LAST
, 300);
1714 REG_RMW_FIELD(ah
, AR_TIMT
, AR_TIMT_FIRST
, 750);
1717 ath9k_hw_init_bb(ah
, chan
);
1720 caldata
->done_txiqcal_once
= false;
1721 caldata
->done_txclcal_once
= false;
1722 caldata
->rtt_hist
.num_readings
= 0;
1724 if (!ath9k_hw_init_cal(ah
, chan
))
1727 ENABLE_REGWRITE_BUFFER(ah
);
1729 ath9k_hw_restore_chainmask(ah
);
1730 REG_WRITE(ah
, AR_CFG_LED
, saveLedState
| AR_CFG_SCLK_32KHZ
);
1732 REGWRITE_BUFFER_FLUSH(ah
);
1735 * For big endian systems turn on swapping for descriptors
1737 if (AR_SREV_9100(ah
)) {
1739 mask
= REG_READ(ah
, AR_CFG
);
1740 if (mask
& (AR_CFG_SWRB
| AR_CFG_SWTB
| AR_CFG_SWRG
)) {
1741 ath_dbg(common
, ATH_DBG_RESET
,
1742 "CFG Byte Swap Set 0x%x\n", mask
);
1745 INIT_CONFIG_STATUS
| AR_CFG_SWRB
| AR_CFG_SWTB
;
1746 REG_WRITE(ah
, AR_CFG
, mask
);
1747 ath_dbg(common
, ATH_DBG_RESET
,
1748 "Setting CFG 0x%x\n", REG_READ(ah
, AR_CFG
));
1751 if (common
->bus_ops
->ath_bus_type
== ATH_USB
) {
1752 /* Configure AR9271 target WLAN */
1753 if (AR_SREV_9271(ah
))
1754 REG_WRITE(ah
, AR_CFG
, AR_CFG_SWRB
| AR_CFG_SWTB
);
1756 REG_WRITE(ah
, AR_CFG
, AR_CFG_SWTD
| AR_CFG_SWRD
);
1759 else if (AR_SREV_9330(ah
) || AR_SREV_9340(ah
))
1760 REG_RMW(ah
, AR_CFG
, AR_CFG_SWRB
| AR_CFG_SWTB
, 0);
1762 REG_WRITE(ah
, AR_CFG
, AR_CFG_SWTD
| AR_CFG_SWRD
);
1766 if (ah
->btcoex_hw
.enabled
)
1767 ath9k_hw_btcoex_enable(ah
);
1769 if (AR_SREV_9300_20_OR_LATER(ah
)) {
1770 ar9003_hw_bb_watchdog_config(ah
);
1772 ar9003_hw_disable_phy_restart(ah
);
1775 ath9k_hw_apply_gpio_override(ah
);
1779 EXPORT_SYMBOL(ath9k_hw_reset
);
1781 /******************************/
1782 /* Power Management (Chipset) */
1783 /******************************/
1786 * Notify Power Mgt is disabled in self-generated frames.
1787 * If requested, force chip to sleep.
1789 static void ath9k_set_power_sleep(struct ath_hw
*ah
, int setChip
)
1791 REG_SET_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PWR_SAV
);
1793 if (AR_SREV_9462(ah
)) {
1794 REG_WRITE(ah
, AR_TIMER_MODE
,
1795 REG_READ(ah
, AR_TIMER_MODE
) & 0xFFFFFF00);
1796 REG_WRITE(ah
, AR_NDP2_TIMER_MODE
, REG_READ(ah
,
1797 AR_NDP2_TIMER_MODE
) & 0xFFFFFF00);
1798 REG_WRITE(ah
, AR_SLP32_INC
,
1799 REG_READ(ah
, AR_SLP32_INC
) & 0xFFF00000);
1800 /* xxx Required for WLAN only case ? */
1801 REG_WRITE(ah
, AR_MCI_INTERRUPT_RX_MSG_EN
, 0);
1806 * Clear the RTC force wake bit to allow the
1807 * mac to go to sleep.
1809 REG_CLR_BIT(ah
, AR_RTC_FORCE_WAKE
, AR_RTC_FORCE_WAKE_EN
);
1811 if (AR_SREV_9462(ah
))
1814 if (!AR_SREV_9100(ah
) && !AR_SREV_9300_20_OR_LATER(ah
))
1815 REG_WRITE(ah
, AR_RC
, AR_RC_AHB
| AR_RC_HOSTIF
);
1817 /* Shutdown chip. Active low */
1818 if (!AR_SREV_5416(ah
) &&
1819 !AR_SREV_9271(ah
) && !AR_SREV_9462_10(ah
)) {
1820 REG_CLR_BIT(ah
, AR_RTC_RESET
, AR_RTC_RESET_EN
);
1825 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
1826 REG_WRITE(ah
, AR_WA
, ah
->WARegVal
& ~AR_WA_D3_L1_DISABLE
);
1830 * Notify Power Management is enabled in self-generating
1831 * frames. If request, set power mode of chip to
1832 * auto/normal. Duration in units of 128us (1/8 TU).
1834 static void ath9k_set_power_network_sleep(struct ath_hw
*ah
, int setChip
)
1838 REG_SET_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PWR_SAV
);
1840 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
1842 if (!(pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
)) {
1843 /* Set WakeOnInterrupt bit; clear ForceWake bit */
1844 REG_WRITE(ah
, AR_RTC_FORCE_WAKE
,
1845 AR_RTC_FORCE_WAKE_ON_INT
);
1848 /* When chip goes into network sleep, it could be waken
1849 * up by MCI_INT interrupt caused by BT's HW messages
1850 * (LNA_xxx, CONT_xxx) which chould be in a very fast
1851 * rate (~100us). This will cause chip to leave and
1852 * re-enter network sleep mode frequently, which in
1853 * consequence will have WLAN MCI HW to generate lots of
1854 * SYS_WAKING and SYS_SLEEPING messages which will make
1855 * BT CPU to busy to process.
1857 if (AR_SREV_9462(ah
)) {
1858 val
= REG_READ(ah
, AR_MCI_INTERRUPT_RX_MSG_EN
) &
1859 ~AR_MCI_INTERRUPT_RX_HW_MSG_MASK
;
1860 REG_WRITE(ah
, AR_MCI_INTERRUPT_RX_MSG_EN
, val
);
1863 * Clear the RTC force wake bit to allow the
1864 * mac to go to sleep.
1866 REG_CLR_BIT(ah
, AR_RTC_FORCE_WAKE
,
1867 AR_RTC_FORCE_WAKE_EN
);
1869 if (AR_SREV_9462(ah
))
1874 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
1875 if (AR_SREV_9300_20_OR_LATER(ah
))
1876 REG_WRITE(ah
, AR_WA
, ah
->WARegVal
& ~AR_WA_D3_L1_DISABLE
);
1879 static bool ath9k_hw_set_power_awake(struct ath_hw
*ah
, int setChip
)
1884 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
1885 if (AR_SREV_9300_20_OR_LATER(ah
)) {
1886 REG_WRITE(ah
, AR_WA
, ah
->WARegVal
);
1891 if ((REG_READ(ah
, AR_RTC_STATUS
) &
1892 AR_RTC_STATUS_M
) == AR_RTC_STATUS_SHUTDOWN
) {
1893 if (ath9k_hw_set_reset_reg(ah
,
1894 ATH9K_RESET_POWER_ON
) != true) {
1897 if (!AR_SREV_9300_20_OR_LATER(ah
))
1898 ath9k_hw_init_pll(ah
, NULL
);
1900 if (AR_SREV_9100(ah
))
1901 REG_SET_BIT(ah
, AR_RTC_RESET
,
1904 REG_SET_BIT(ah
, AR_RTC_FORCE_WAKE
,
1905 AR_RTC_FORCE_WAKE_EN
);
1908 for (i
= POWER_UP_TIME
/ 50; i
> 0; i
--) {
1909 val
= REG_READ(ah
, AR_RTC_STATUS
) & AR_RTC_STATUS_M
;
1910 if (val
== AR_RTC_STATUS_ON
)
1913 REG_SET_BIT(ah
, AR_RTC_FORCE_WAKE
,
1914 AR_RTC_FORCE_WAKE_EN
);
1917 ath_err(ath9k_hw_common(ah
),
1918 "Failed to wakeup in %uus\n",
1919 POWER_UP_TIME
/ 20);
1924 REG_CLR_BIT(ah
, AR_STA_ID1
, AR_STA_ID1_PWR_SAV
);
1929 bool ath9k_hw_setpower(struct ath_hw
*ah
, enum ath9k_power_mode mode
)
1931 struct ath_common
*common
= ath9k_hw_common(ah
);
1932 int status
= true, setChip
= true;
1933 static const char *modes
[] = {
1940 if (ah
->power_mode
== mode
)
1943 ath_dbg(common
, ATH_DBG_RESET
, "%s -> %s\n",
1944 modes
[ah
->power_mode
], modes
[mode
]);
1947 case ATH9K_PM_AWAKE
:
1948 status
= ath9k_hw_set_power_awake(ah
, setChip
);
1950 case ATH9K_PM_FULL_SLEEP
:
1951 ath9k_set_power_sleep(ah
, setChip
);
1952 ah
->chip_fullsleep
= true;
1954 case ATH9K_PM_NETWORK_SLEEP
:
1955 ath9k_set_power_network_sleep(ah
, setChip
);
1958 ath_err(common
, "Unknown power mode %u\n", mode
);
1961 ah
->power_mode
= mode
;
1964 * XXX: If this warning never comes up after a while then
1965 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
1966 * ath9k_hw_setpower() return type void.
1969 if (!(ah
->ah_flags
& AH_UNPLUGGED
))
1970 ATH_DBG_WARN_ON_ONCE(!status
);
1974 EXPORT_SYMBOL(ath9k_hw_setpower
);
1976 /*******************/
1977 /* Beacon Handling */
1978 /*******************/
1980 void ath9k_hw_beaconinit(struct ath_hw
*ah
, u32 next_beacon
, u32 beacon_period
)
1984 ENABLE_REGWRITE_BUFFER(ah
);
1986 switch (ah
->opmode
) {
1987 case NL80211_IFTYPE_ADHOC
:
1988 case NL80211_IFTYPE_MESH_POINT
:
1989 REG_SET_BIT(ah
, AR_TXCFG
,
1990 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY
);
1991 REG_WRITE(ah
, AR_NEXT_NDP_TIMER
, next_beacon
+
1992 TU_TO_USEC(ah
->atim_window
? ah
->atim_window
: 1));
1993 flags
|= AR_NDP_TIMER_EN
;
1994 case NL80211_IFTYPE_AP
:
1995 REG_WRITE(ah
, AR_NEXT_TBTT_TIMER
, next_beacon
);
1996 REG_WRITE(ah
, AR_NEXT_DMA_BEACON_ALERT
, next_beacon
-
1997 TU_TO_USEC(ah
->config
.dma_beacon_response_time
));
1998 REG_WRITE(ah
, AR_NEXT_SWBA
, next_beacon
-
1999 TU_TO_USEC(ah
->config
.sw_beacon_response_time
));
2001 AR_TBTT_TIMER_EN
| AR_DBA_TIMER_EN
| AR_SWBA_TIMER_EN
;
2004 ath_dbg(ath9k_hw_common(ah
), ATH_DBG_BEACON
,
2005 "%s: unsupported opmode: %d\n",
2006 __func__
, ah
->opmode
);
2011 REG_WRITE(ah
, AR_BEACON_PERIOD
, beacon_period
);
2012 REG_WRITE(ah
, AR_DMA_BEACON_PERIOD
, beacon_period
);
2013 REG_WRITE(ah
, AR_SWBA_PERIOD
, beacon_period
);
2014 REG_WRITE(ah
, AR_NDP_PERIOD
, beacon_period
);
2016 REGWRITE_BUFFER_FLUSH(ah
);
2018 REG_SET_BIT(ah
, AR_TIMER_MODE
, flags
);
2020 EXPORT_SYMBOL(ath9k_hw_beaconinit
);
2022 void ath9k_hw_set_sta_beacon_timers(struct ath_hw
*ah
,
2023 const struct ath9k_beacon_state
*bs
)
2025 u32 nextTbtt
, beaconintval
, dtimperiod
, beacontimeout
;
2026 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
2027 struct ath_common
*common
= ath9k_hw_common(ah
);
2029 ENABLE_REGWRITE_BUFFER(ah
);
2031 REG_WRITE(ah
, AR_NEXT_TBTT_TIMER
, TU_TO_USEC(bs
->bs_nexttbtt
));
2033 REG_WRITE(ah
, AR_BEACON_PERIOD
,
2034 TU_TO_USEC(bs
->bs_intval
));
2035 REG_WRITE(ah
, AR_DMA_BEACON_PERIOD
,
2036 TU_TO_USEC(bs
->bs_intval
));
2038 REGWRITE_BUFFER_FLUSH(ah
);
2040 REG_RMW_FIELD(ah
, AR_RSSI_THR
,
2041 AR_RSSI_THR_BM_THR
, bs
->bs_bmissthreshold
);
2043 beaconintval
= bs
->bs_intval
;
2045 if (bs
->bs_sleepduration
> beaconintval
)
2046 beaconintval
= bs
->bs_sleepduration
;
2048 dtimperiod
= bs
->bs_dtimperiod
;
2049 if (bs
->bs_sleepduration
> dtimperiod
)
2050 dtimperiod
= bs
->bs_sleepduration
;
2052 if (beaconintval
== dtimperiod
)
2053 nextTbtt
= bs
->bs_nextdtim
;
2055 nextTbtt
= bs
->bs_nexttbtt
;
2057 ath_dbg(common
, ATH_DBG_BEACON
, "next DTIM %d\n", bs
->bs_nextdtim
);
2058 ath_dbg(common
, ATH_DBG_BEACON
, "next beacon %d\n", nextTbtt
);
2059 ath_dbg(common
, ATH_DBG_BEACON
, "beacon period %d\n", beaconintval
);
2060 ath_dbg(common
, ATH_DBG_BEACON
, "DTIM period %d\n", dtimperiod
);
2062 ENABLE_REGWRITE_BUFFER(ah
);
2064 REG_WRITE(ah
, AR_NEXT_DTIM
,
2065 TU_TO_USEC(bs
->bs_nextdtim
- SLEEP_SLOP
));
2066 REG_WRITE(ah
, AR_NEXT_TIM
, TU_TO_USEC(nextTbtt
- SLEEP_SLOP
));
2068 REG_WRITE(ah
, AR_SLEEP1
,
2069 SM((CAB_TIMEOUT_VAL
<< 3), AR_SLEEP1_CAB_TIMEOUT
)
2070 | AR_SLEEP1_ASSUME_DTIM
);
2072 if (pCap
->hw_caps
& ATH9K_HW_CAP_AUTOSLEEP
)
2073 beacontimeout
= (BEACON_TIMEOUT_VAL
<< 3);
2075 beacontimeout
= MIN_BEACON_TIMEOUT_VAL
;
2077 REG_WRITE(ah
, AR_SLEEP2
,
2078 SM(beacontimeout
, AR_SLEEP2_BEACON_TIMEOUT
));
2080 REG_WRITE(ah
, AR_TIM_PERIOD
, TU_TO_USEC(beaconintval
));
2081 REG_WRITE(ah
, AR_DTIM_PERIOD
, TU_TO_USEC(dtimperiod
));
2083 REGWRITE_BUFFER_FLUSH(ah
);
2085 REG_SET_BIT(ah
, AR_TIMER_MODE
,
2086 AR_TBTT_TIMER_EN
| AR_TIM_TIMER_EN
|
2089 /* TSF Out of Range Threshold */
2090 REG_WRITE(ah
, AR_TSFOOR_THRESHOLD
, bs
->bs_tsfoor_threshold
);
2092 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers
);
2094 /*******************/
2095 /* HW Capabilities */
2096 /*******************/
2098 static u8
fixup_chainmask(u8 chip_chainmask
, u8 eeprom_chainmask
)
2100 eeprom_chainmask
&= chip_chainmask
;
2101 if (eeprom_chainmask
)
2102 return eeprom_chainmask
;
2104 return chip_chainmask
;
2107 int ath9k_hw_fill_cap_info(struct ath_hw
*ah
)
2109 struct ath9k_hw_capabilities
*pCap
= &ah
->caps
;
2110 struct ath_regulatory
*regulatory
= ath9k_hw_regulatory(ah
);
2111 struct ath_common
*common
= ath9k_hw_common(ah
);
2112 struct ath_btcoex_hw
*btcoex_hw
= &ah
->btcoex_hw
;
2113 unsigned int chip_chainmask
;
2116 u8 ant_div_ctl1
, tx_chainmask
, rx_chainmask
;
2118 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_REG_0
);
2119 regulatory
->current_rd
= eeval
;
2121 if (ah
->opmode
!= NL80211_IFTYPE_AP
&&
2122 ah
->hw_version
.subvendorid
== AR_SUBVENDOR_ID_NEW_A
) {
2123 if (regulatory
->current_rd
== 0x64 ||
2124 regulatory
->current_rd
== 0x65)
2125 regulatory
->current_rd
+= 5;
2126 else if (regulatory
->current_rd
== 0x41)
2127 regulatory
->current_rd
= 0x43;
2128 ath_dbg(common
, ATH_DBG_REGULATORY
,
2129 "regdomain mapped to 0x%x\n", regulatory
->current_rd
);
2132 eeval
= ah
->eep_ops
->get_eeprom(ah
, EEP_OP_MODE
);
2133 if ((eeval
& (AR5416_OPFLAGS_11G
| AR5416_OPFLAGS_11A
)) == 0) {
2135 "no band has been marked as supported in EEPROM\n");
2139 if (eeval
& AR5416_OPFLAGS_11A
)
2140 pCap
->hw_caps
|= ATH9K_HW_CAP_5GHZ
;
2142 if (eeval
& AR5416_OPFLAGS_11G
)
2143 pCap
->hw_caps
|= ATH9K_HW_CAP_2GHZ
;
2145 if (AR_SREV_9485(ah
) || AR_SREV_9285(ah
) || AR_SREV_9330(ah
))
2147 else if (!AR_SREV_9280_20_OR_LATER(ah
))
2149 else if (!AR_SREV_9300_20_OR_LATER(ah
) || AR_SREV_9340(ah
))
2154 pCap
->tx_chainmask
= ah
->eep_ops
->get_eeprom(ah
, EEP_TX_MASK
);
2156 * For AR9271 we will temporarilly uses the rx chainmax as read from
2159 if ((ah
->hw_version
.devid
== AR5416_DEVID_PCI
) &&
2160 !(eeval
& AR5416_OPFLAGS_11A
) &&
2161 !(AR_SREV_9271(ah
)))
2162 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2163 pCap
->rx_chainmask
= ath9k_hw_gpio_get(ah
, 0) ? 0x5 : 0x7;
2164 else if (AR_SREV_9100(ah
))
2165 pCap
->rx_chainmask
= 0x7;
2167 /* Use rx_chainmask from EEPROM. */
2168 pCap
->rx_chainmask
= ah
->eep_ops
->get_eeprom(ah
, EEP_RX_MASK
);
2170 pCap
->tx_chainmask
= fixup_chainmask(chip_chainmask
, pCap
->tx_chainmask
);
2171 pCap
->rx_chainmask
= fixup_chainmask(chip_chainmask
, pCap
->rx_chainmask
);
2172 ah
->txchainmask
= pCap
->tx_chainmask
;
2173 ah
->rxchainmask
= pCap
->rx_chainmask
;
2175 ah
->misc_mode
|= AR_PCU_MIC_NEW_LOC_ENA
;
2177 /* enable key search for every frame in an aggregate */
2178 if (AR_SREV_9300_20_OR_LATER(ah
))
2179 ah
->misc_mode
|= AR_PCU_ALWAYS_PERFORM_KEYSEARCH
;
2181 common
->crypt_caps
|= ATH_CRYPT_CAP_CIPHER_AESCCM
;
2183 if (ah
->hw_version
.devid
!= AR2427_DEVID_PCIE
)
2184 pCap
->hw_caps
|= ATH9K_HW_CAP_HT
;
2186 pCap
->hw_caps
&= ~ATH9K_HW_CAP_HT
;
2188 if (AR_SREV_9271(ah
))
2189 pCap
->num_gpio_pins
= AR9271_NUM_GPIO
;
2190 else if (AR_DEVID_7010(ah
))
2191 pCap
->num_gpio_pins
= AR7010_NUM_GPIO
;
2192 else if (AR_SREV_9300_20_OR_LATER(ah
))
2193 pCap
->num_gpio_pins
= AR9300_NUM_GPIO
;
2194 else if (AR_SREV_9287_11_OR_LATER(ah
))
2195 pCap
->num_gpio_pins
= AR9287_NUM_GPIO
;
2196 else if (AR_SREV_9285_12_OR_LATER(ah
))
2197 pCap
->num_gpio_pins
= AR9285_NUM_GPIO
;
2198 else if (AR_SREV_9280_20_OR_LATER(ah
))
2199 pCap
->num_gpio_pins
= AR928X_NUM_GPIO
;
2201 pCap
->num_gpio_pins
= AR_NUM_GPIO
;
2203 if (AR_SREV_9160_10_OR_LATER(ah
) || AR_SREV_9100(ah
)) {
2204 pCap
->hw_caps
|= ATH9K_HW_CAP_CST
;
2205 pCap
->rts_aggr_limit
= ATH_AMPDU_LIMIT_MAX
;
2207 pCap
->rts_aggr_limit
= (8 * 1024);
2210 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2211 ah
->rfsilent
= ah
->eep_ops
->get_eeprom(ah
, EEP_RF_SILENT
);
2212 if (ah
->rfsilent
& EEP_RFSILENT_ENABLED
) {
2214 MS(ah
->rfsilent
, EEP_RFSILENT_GPIO_SEL
);
2215 ah
->rfkill_polarity
=
2216 MS(ah
->rfsilent
, EEP_RFSILENT_POLARITY
);
2218 pCap
->hw_caps
|= ATH9K_HW_CAP_RFSILENT
;
2221 if (AR_SREV_9271(ah
) || AR_SREV_9300_20_OR_LATER(ah
))
2222 pCap
->hw_caps
|= ATH9K_HW_CAP_AUTOSLEEP
;
2224 pCap
->hw_caps
&= ~ATH9K_HW_CAP_AUTOSLEEP
;
2226 if (AR_SREV_9280(ah
) || AR_SREV_9285(ah
))
2227 pCap
->hw_caps
&= ~ATH9K_HW_CAP_4KB_SPLITTRANS
;
2229 pCap
->hw_caps
|= ATH9K_HW_CAP_4KB_SPLITTRANS
;
2231 if (common
->btcoex_enabled
) {
2232 if (AR_SREV_9300_20_OR_LATER(ah
)) {
2233 btcoex_hw
->scheme
= ATH_BTCOEX_CFG_3WIRE
;
2234 btcoex_hw
->btactive_gpio
= ATH_BTACTIVE_GPIO_9300
;
2235 btcoex_hw
->wlanactive_gpio
= ATH_WLANACTIVE_GPIO_9300
;
2236 btcoex_hw
->btpriority_gpio
= ATH_BTPRIORITY_GPIO_9300
;
2237 } else if (AR_SREV_9280_20_OR_LATER(ah
)) {
2238 btcoex_hw
->btactive_gpio
= ATH_BTACTIVE_GPIO_9280
;
2239 btcoex_hw
->wlanactive_gpio
= ATH_WLANACTIVE_GPIO_9280
;
2241 if (AR_SREV_9285(ah
)) {
2242 btcoex_hw
->scheme
= ATH_BTCOEX_CFG_3WIRE
;
2243 btcoex_hw
->btpriority_gpio
=
2244 ATH_BTPRIORITY_GPIO_9285
;
2246 btcoex_hw
->scheme
= ATH_BTCOEX_CFG_2WIRE
;
2250 btcoex_hw
->scheme
= ATH_BTCOEX_CFG_NONE
;
2253 if (AR_SREV_9300_20_OR_LATER(ah
)) {
2254 pCap
->hw_caps
|= ATH9K_HW_CAP_EDMA
| ATH9K_HW_CAP_FASTCLOCK
;
2255 if (!AR_SREV_9330(ah
) && !AR_SREV_9485(ah
))
2256 pCap
->hw_caps
|= ATH9K_HW_CAP_LDPC
;
2258 pCap
->rx_hp_qdepth
= ATH9K_HW_RX_HP_QDEPTH
;
2259 pCap
->rx_lp_qdepth
= ATH9K_HW_RX_LP_QDEPTH
;
2260 pCap
->rx_status_len
= sizeof(struct ar9003_rxs
);
2261 pCap
->tx_desc_len
= sizeof(struct ar9003_txc
);
2262 pCap
->txs_len
= sizeof(struct ar9003_txs
);
2263 if (!ah
->config
.paprd_disable
&&
2264 ah
->eep_ops
->get_eeprom(ah
, EEP_PAPRD
))
2265 pCap
->hw_caps
|= ATH9K_HW_CAP_PAPRD
;
2267 pCap
->tx_desc_len
= sizeof(struct ath_desc
);
2268 if (AR_SREV_9280_20(ah
))
2269 pCap
->hw_caps
|= ATH9K_HW_CAP_FASTCLOCK
;
2272 if (AR_SREV_9300_20_OR_LATER(ah
))
2273 pCap
->hw_caps
|= ATH9K_HW_CAP_RAC_SUPPORTED
;
2275 if (AR_SREV_9300_20_OR_LATER(ah
))
2276 ah
->ent_mode
= REG_READ(ah
, AR_ENT_OTP
);
2278 if (AR_SREV_9287_11_OR_LATER(ah
) || AR_SREV_9271(ah
))
2279 pCap
->hw_caps
|= ATH9K_HW_CAP_SGI_20
;
2281 if (AR_SREV_9285(ah
))
2282 if (ah
->eep_ops
->get_eeprom(ah
, EEP_MODAL_VER
) >= 3) {
2284 ah
->eep_ops
->get_eeprom(ah
, EEP_ANT_DIV_CTL1
);
2285 if ((ant_div_ctl1
& 0x1) && ((ant_div_ctl1
>> 3) & 0x1))
2286 pCap
->hw_caps
|= ATH9K_HW_CAP_ANT_DIV_COMB
;
2288 if (AR_SREV_9300_20_OR_LATER(ah
)) {
2289 if (ah
->eep_ops
->get_eeprom(ah
, EEP_CHAIN_MASK_REDUCE
))
2290 pCap
->hw_caps
|= ATH9K_HW_CAP_APM
;
2294 if (AR_SREV_9330(ah
) || AR_SREV_9485(ah
)) {
2295 ant_div_ctl1
= ah
->eep_ops
->get_eeprom(ah
, EEP_ANT_DIV_CTL1
);
2297 * enable the diversity-combining algorithm only when
2298 * both enable_lna_div and enable_fast_div are set
2299 * Table for Diversity
2300 * ant_div_alt_lnaconf bit 0-1
2301 * ant_div_main_lnaconf bit 2-3
2302 * ant_div_alt_gaintb bit 4
2303 * ant_div_main_gaintb bit 5
2304 * enable_ant_div_lnadiv bit 6
2305 * enable_ant_fast_div bit 7
2307 if ((ant_div_ctl1
>> 0x6) == 0x3)
2308 pCap
->hw_caps
|= ATH9K_HW_CAP_ANT_DIV_COMB
;
2311 if (AR_SREV_9485_10(ah
)) {
2312 pCap
->pcie_lcr_extsync_en
= true;
2313 pCap
->pcie_lcr_offset
= 0x80;
2316 tx_chainmask
= pCap
->tx_chainmask
;
2317 rx_chainmask
= pCap
->rx_chainmask
;
2318 while (tx_chainmask
|| rx_chainmask
) {
2319 if (tx_chainmask
& BIT(0))
2320 pCap
->max_txchains
++;
2321 if (rx_chainmask
& BIT(0))
2322 pCap
->max_rxchains
++;
2328 if (AR_SREV_9300_20_OR_LATER(ah
)) {
2329 ah
->enabled_cals
|= TX_IQ_CAL
;
2330 if (!AR_SREV_9330(ah
))
2331 ah
->enabled_cals
|= TX_IQ_ON_AGC_CAL
;
2333 if (AR_SREV_9462(ah
))
2334 pCap
->hw_caps
|= ATH9K_HW_CAP_RTT
;
2339 /****************************/
2340 /* GPIO / RFKILL / Antennae */
2341 /****************************/
2343 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw
*ah
,
2347 u32 gpio_shift
, tmp
;
2350 addr
= AR_GPIO_OUTPUT_MUX3
;
2352 addr
= AR_GPIO_OUTPUT_MUX2
;
2354 addr
= AR_GPIO_OUTPUT_MUX1
;
2356 gpio_shift
= (gpio
% 6) * 5;
2358 if (AR_SREV_9280_20_OR_LATER(ah
)
2359 || (addr
!= AR_GPIO_OUTPUT_MUX1
)) {
2360 REG_RMW(ah
, addr
, (type
<< gpio_shift
),
2361 (0x1f << gpio_shift
));
2363 tmp
= REG_READ(ah
, addr
);
2364 tmp
= ((tmp
& 0x1F0) << 1) | (tmp
& ~0x1F0);
2365 tmp
&= ~(0x1f << gpio_shift
);
2366 tmp
|= (type
<< gpio_shift
);
2367 REG_WRITE(ah
, addr
, tmp
);
2371 void ath9k_hw_cfg_gpio_input(struct ath_hw
*ah
, u32 gpio
)
2375 BUG_ON(gpio
>= ah
->caps
.num_gpio_pins
);
2377 if (AR_DEVID_7010(ah
)) {
2379 REG_RMW(ah
, AR7010_GPIO_OE
,
2380 (AR7010_GPIO_OE_AS_INPUT
<< gpio_shift
),
2381 (AR7010_GPIO_OE_MASK
<< gpio_shift
));
2385 gpio_shift
= gpio
<< 1;
2388 (AR_GPIO_OE_OUT_DRV_NO
<< gpio_shift
),
2389 (AR_GPIO_OE_OUT_DRV
<< gpio_shift
));
2391 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input
);
2393 u32
ath9k_hw_gpio_get(struct ath_hw
*ah
, u32 gpio
)
2395 #define MS_REG_READ(x, y) \
2396 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2398 if (gpio
>= ah
->caps
.num_gpio_pins
)
2401 if (AR_DEVID_7010(ah
)) {
2403 val
= REG_READ(ah
, AR7010_GPIO_IN
);
2404 return (MS(val
, AR7010_GPIO_IN_VAL
) & AR_GPIO_BIT(gpio
)) == 0;
2405 } else if (AR_SREV_9300_20_OR_LATER(ah
))
2406 return (MS(REG_READ(ah
, AR_GPIO_IN
), AR9300_GPIO_IN_VAL
) &
2407 AR_GPIO_BIT(gpio
)) != 0;
2408 else if (AR_SREV_9271(ah
))
2409 return MS_REG_READ(AR9271
, gpio
) != 0;
2410 else if (AR_SREV_9287_11_OR_LATER(ah
))
2411 return MS_REG_READ(AR9287
, gpio
) != 0;
2412 else if (AR_SREV_9285_12_OR_LATER(ah
))
2413 return MS_REG_READ(AR9285
, gpio
) != 0;
2414 else if (AR_SREV_9280_20_OR_LATER(ah
))
2415 return MS_REG_READ(AR928X
, gpio
) != 0;
2417 return MS_REG_READ(AR
, gpio
) != 0;
2419 EXPORT_SYMBOL(ath9k_hw_gpio_get
);
2421 void ath9k_hw_cfg_output(struct ath_hw
*ah
, u32 gpio
,
2426 if (AR_DEVID_7010(ah
)) {
2428 REG_RMW(ah
, AR7010_GPIO_OE
,
2429 (AR7010_GPIO_OE_AS_OUTPUT
<< gpio_shift
),
2430 (AR7010_GPIO_OE_MASK
<< gpio_shift
));
2434 ath9k_hw_gpio_cfg_output_mux(ah
, gpio
, ah_signal_type
);
2435 gpio_shift
= 2 * gpio
;
2438 (AR_GPIO_OE_OUT_DRV_ALL
<< gpio_shift
),
2439 (AR_GPIO_OE_OUT_DRV
<< gpio_shift
));
2441 EXPORT_SYMBOL(ath9k_hw_cfg_output
);
2443 void ath9k_hw_set_gpio(struct ath_hw
*ah
, u32 gpio
, u32 val
)
2445 if (AR_DEVID_7010(ah
)) {
2447 REG_RMW(ah
, AR7010_GPIO_OUT
, ((val
&1) << gpio
),
2452 if (AR_SREV_9271(ah
))
2455 REG_RMW(ah
, AR_GPIO_IN_OUT
, ((val
& 1) << gpio
),
2458 EXPORT_SYMBOL(ath9k_hw_set_gpio
);
2460 u32
ath9k_hw_getdefantenna(struct ath_hw
*ah
)
2462 return REG_READ(ah
, AR_DEF_ANTENNA
) & 0x7;
2464 EXPORT_SYMBOL(ath9k_hw_getdefantenna
);
2466 void ath9k_hw_setantenna(struct ath_hw
*ah
, u32 antenna
)
2468 REG_WRITE(ah
, AR_DEF_ANTENNA
, (antenna
& 0x7));
2470 EXPORT_SYMBOL(ath9k_hw_setantenna
);
2472 /*********************/
2473 /* General Operation */
2474 /*********************/
2476 u32
ath9k_hw_getrxfilter(struct ath_hw
*ah
)
2478 u32 bits
= REG_READ(ah
, AR_RX_FILTER
);
2479 u32 phybits
= REG_READ(ah
, AR_PHY_ERR
);
2481 if (phybits
& AR_PHY_ERR_RADAR
)
2482 bits
|= ATH9K_RX_FILTER_PHYRADAR
;
2483 if (phybits
& (AR_PHY_ERR_OFDM_TIMING
| AR_PHY_ERR_CCK_TIMING
))
2484 bits
|= ATH9K_RX_FILTER_PHYERR
;
2488 EXPORT_SYMBOL(ath9k_hw_getrxfilter
);
2490 void ath9k_hw_setrxfilter(struct ath_hw
*ah
, u32 bits
)
2494 ENABLE_REGWRITE_BUFFER(ah
);
2496 if (AR_SREV_9462(ah
))
2497 bits
|= ATH9K_RX_FILTER_CONTROL_WRAPPER
;
2499 REG_WRITE(ah
, AR_RX_FILTER
, bits
);
2502 if (bits
& ATH9K_RX_FILTER_PHYRADAR
)
2503 phybits
|= AR_PHY_ERR_RADAR
;
2504 if (bits
& ATH9K_RX_FILTER_PHYERR
)
2505 phybits
|= AR_PHY_ERR_OFDM_TIMING
| AR_PHY_ERR_CCK_TIMING
;
2506 REG_WRITE(ah
, AR_PHY_ERR
, phybits
);
2509 REG_SET_BIT(ah
, AR_RXCFG
, AR_RXCFG_ZLFDMA
);
2511 REG_CLR_BIT(ah
, AR_RXCFG
, AR_RXCFG_ZLFDMA
);
2513 REGWRITE_BUFFER_FLUSH(ah
);
2515 EXPORT_SYMBOL(ath9k_hw_setrxfilter
);
2517 bool ath9k_hw_phy_disable(struct ath_hw
*ah
)
2519 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_WARM
))
2522 ath9k_hw_init_pll(ah
, NULL
);
2525 EXPORT_SYMBOL(ath9k_hw_phy_disable
);
2527 bool ath9k_hw_disable(struct ath_hw
*ah
)
2529 if (!ath9k_hw_setpower(ah
, ATH9K_PM_AWAKE
))
2532 if (!ath9k_hw_set_reset_reg(ah
, ATH9K_RESET_COLD
))
2535 ath9k_hw_init_pll(ah
, NULL
);
2538 EXPORT_SYMBOL(ath9k_hw_disable
);
2540 static int get_antenna_gain(struct ath_hw
*ah
, struct ath9k_channel
*chan
)
2542 enum eeprom_param gain_param
;
2544 if (IS_CHAN_2GHZ(chan
))
2545 gain_param
= EEP_ANTENNA_GAIN_2G
;
2547 gain_param
= EEP_ANTENNA_GAIN_5G
;
2549 return ah
->eep_ops
->get_eeprom(ah
, gain_param
);
2552 void ath9k_hw_apply_txpower(struct ath_hw
*ah
, struct ath9k_channel
*chan
)
2554 struct ath_regulatory
*reg
= ath9k_hw_regulatory(ah
);
2555 struct ieee80211_channel
*channel
;
2556 int chan_pwr
, new_pwr
, max_gain
;
2557 int ant_gain
, ant_reduction
= 0;
2562 channel
= chan
->chan
;
2563 chan_pwr
= min_t(int, channel
->max_power
* 2, MAX_RATE_POWER
);
2564 new_pwr
= min_t(int, chan_pwr
, reg
->power_limit
);
2565 max_gain
= chan_pwr
- new_pwr
+ channel
->max_antenna_gain
* 2;
2567 ant_gain
= get_antenna_gain(ah
, chan
);
2568 if (ant_gain
> max_gain
)
2569 ant_reduction
= ant_gain
- max_gain
;
2571 ah
->eep_ops
->set_txpower(ah
, chan
,
2572 ath9k_regd_get_ctl(reg
, chan
),
2573 ant_reduction
, new_pwr
, false);
2576 void ath9k_hw_set_txpowerlimit(struct ath_hw
*ah
, u32 limit
, bool test
)
2578 struct ath_regulatory
*reg
= ath9k_hw_regulatory(ah
);
2579 struct ath9k_channel
*chan
= ah
->curchan
;
2580 struct ieee80211_channel
*channel
= chan
->chan
;
2582 reg
->power_limit
= min_t(int, limit
, MAX_RATE_POWER
);
2584 channel
->max_power
= MAX_RATE_POWER
/ 2;
2586 ath9k_hw_apply_txpower(ah
, chan
);
2589 channel
->max_power
= DIV_ROUND_UP(reg
->max_power_level
, 2);
2591 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit
);
2593 void ath9k_hw_setopmode(struct ath_hw
*ah
)
2595 ath9k_hw_set_operating_mode(ah
, ah
->opmode
);
2597 EXPORT_SYMBOL(ath9k_hw_setopmode
);
2599 void ath9k_hw_setmcastfilter(struct ath_hw
*ah
, u32 filter0
, u32 filter1
)
2601 REG_WRITE(ah
, AR_MCAST_FIL0
, filter0
);
2602 REG_WRITE(ah
, AR_MCAST_FIL1
, filter1
);
2604 EXPORT_SYMBOL(ath9k_hw_setmcastfilter
);
2606 void ath9k_hw_write_associd(struct ath_hw
*ah
)
2608 struct ath_common
*common
= ath9k_hw_common(ah
);
2610 REG_WRITE(ah
, AR_BSS_ID0
, get_unaligned_le32(common
->curbssid
));
2611 REG_WRITE(ah
, AR_BSS_ID1
, get_unaligned_le16(common
->curbssid
+ 4) |
2612 ((common
->curaid
& 0x3fff) << AR_BSS_ID1_AID_S
));
2614 EXPORT_SYMBOL(ath9k_hw_write_associd
);
2616 #define ATH9K_MAX_TSF_READ 10
2618 u64
ath9k_hw_gettsf64(struct ath_hw
*ah
)
2620 u32 tsf_lower
, tsf_upper1
, tsf_upper2
;
2623 tsf_upper1
= REG_READ(ah
, AR_TSF_U32
);
2624 for (i
= 0; i
< ATH9K_MAX_TSF_READ
; i
++) {
2625 tsf_lower
= REG_READ(ah
, AR_TSF_L32
);
2626 tsf_upper2
= REG_READ(ah
, AR_TSF_U32
);
2627 if (tsf_upper2
== tsf_upper1
)
2629 tsf_upper1
= tsf_upper2
;
2632 WARN_ON( i
== ATH9K_MAX_TSF_READ
);
2634 return (((u64
)tsf_upper1
<< 32) | tsf_lower
);
2636 EXPORT_SYMBOL(ath9k_hw_gettsf64
);
2638 void ath9k_hw_settsf64(struct ath_hw
*ah
, u64 tsf64
)
2640 REG_WRITE(ah
, AR_TSF_L32
, tsf64
& 0xffffffff);
2641 REG_WRITE(ah
, AR_TSF_U32
, (tsf64
>> 32) & 0xffffffff);
2643 EXPORT_SYMBOL(ath9k_hw_settsf64
);
2645 void ath9k_hw_reset_tsf(struct ath_hw
*ah
)
2647 if (!ath9k_hw_wait(ah
, AR_SLP32_MODE
, AR_SLP32_TSF_WRITE_STATUS
, 0,
2648 AH_TSF_WRITE_TIMEOUT
))
2649 ath_dbg(ath9k_hw_common(ah
), ATH_DBG_RESET
,
2650 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2652 REG_WRITE(ah
, AR_RESET_TSF
, AR_RESET_TSF_ONCE
);
2654 EXPORT_SYMBOL(ath9k_hw_reset_tsf
);
2656 void ath9k_hw_set_tsfadjust(struct ath_hw
*ah
, u32 setting
)
2659 ah
->misc_mode
|= AR_PCU_TX_ADD_TSF
;
2661 ah
->misc_mode
&= ~AR_PCU_TX_ADD_TSF
;
2663 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust
);
2665 void ath9k_hw_set11nmac2040(struct ath_hw
*ah
)
2667 struct ieee80211_conf
*conf
= &ath9k_hw_common(ah
)->hw
->conf
;
2670 if (conf_is_ht40(conf
) && !ah
->config
.cwm_ignore_extcca
)
2671 macmode
= AR_2040_JOINED_RX_CLEAR
;
2675 REG_WRITE(ah
, AR_2040_MODE
, macmode
);
2678 /* HW Generic timers configuration */
2680 static const struct ath_gen_timer_configuration gen_tmr_configuration
[] =
2682 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2683 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2684 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2685 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2686 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2687 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2688 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2689 {AR_NEXT_NDP_TIMER
, AR_NDP_PERIOD
, AR_TIMER_MODE
, 0x0080},
2690 {AR_NEXT_NDP2_TIMER
, AR_NDP2_PERIOD
, AR_NDP2_TIMER_MODE
, 0x0001},
2691 {AR_NEXT_NDP2_TIMER
+ 1*4, AR_NDP2_PERIOD
+ 1*4,
2692 AR_NDP2_TIMER_MODE
, 0x0002},
2693 {AR_NEXT_NDP2_TIMER
+ 2*4, AR_NDP2_PERIOD
+ 2*4,
2694 AR_NDP2_TIMER_MODE
, 0x0004},
2695 {AR_NEXT_NDP2_TIMER
+ 3*4, AR_NDP2_PERIOD
+ 3*4,
2696 AR_NDP2_TIMER_MODE
, 0x0008},
2697 {AR_NEXT_NDP2_TIMER
+ 4*4, AR_NDP2_PERIOD
+ 4*4,
2698 AR_NDP2_TIMER_MODE
, 0x0010},
2699 {AR_NEXT_NDP2_TIMER
+ 5*4, AR_NDP2_PERIOD
+ 5*4,
2700 AR_NDP2_TIMER_MODE
, 0x0020},
2701 {AR_NEXT_NDP2_TIMER
+ 6*4, AR_NDP2_PERIOD
+ 6*4,
2702 AR_NDP2_TIMER_MODE
, 0x0040},
2703 {AR_NEXT_NDP2_TIMER
+ 7*4, AR_NDP2_PERIOD
+ 7*4,
2704 AR_NDP2_TIMER_MODE
, 0x0080}
2707 /* HW generic timer primitives */
2709 /* compute and clear index of rightmost 1 */
2710 static u32
rightmost_index(struct ath_gen_timer_table
*timer_table
, u32
*mask
)
2720 return timer_table
->gen_timer_index
[b
];
2723 u32
ath9k_hw_gettsf32(struct ath_hw
*ah
)
2725 return REG_READ(ah
, AR_TSF_L32
);
2727 EXPORT_SYMBOL(ath9k_hw_gettsf32
);
2729 struct ath_gen_timer
*ath_gen_timer_alloc(struct ath_hw
*ah
,
2730 void (*trigger
)(void *),
2731 void (*overflow
)(void *),
2735 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
2736 struct ath_gen_timer
*timer
;
2738 timer
= kzalloc(sizeof(struct ath_gen_timer
), GFP_KERNEL
);
2740 if (timer
== NULL
) {
2741 ath_err(ath9k_hw_common(ah
),
2742 "Failed to allocate memory for hw timer[%d]\n",
2747 /* allocate a hardware generic timer slot */
2748 timer_table
->timers
[timer_index
] = timer
;
2749 timer
->index
= timer_index
;
2750 timer
->trigger
= trigger
;
2751 timer
->overflow
= overflow
;
2756 EXPORT_SYMBOL(ath_gen_timer_alloc
);
2758 void ath9k_hw_gen_timer_start(struct ath_hw
*ah
,
2759 struct ath_gen_timer
*timer
,
2763 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
2764 u32 tsf
, timer_next
;
2766 BUG_ON(!timer_period
);
2768 set_bit(timer
->index
, &timer_table
->timer_mask
.timer_bits
);
2770 tsf
= ath9k_hw_gettsf32(ah
);
2772 timer_next
= tsf
+ trig_timeout
;
2774 ath_dbg(ath9k_hw_common(ah
), ATH_DBG_HWTIMER
,
2775 "current tsf %x period %x timer_next %x\n",
2776 tsf
, timer_period
, timer_next
);
2779 * Program generic timer registers
2781 REG_WRITE(ah
, gen_tmr_configuration
[timer
->index
].next_addr
,
2783 REG_WRITE(ah
, gen_tmr_configuration
[timer
->index
].period_addr
,
2785 REG_SET_BIT(ah
, gen_tmr_configuration
[timer
->index
].mode_addr
,
2786 gen_tmr_configuration
[timer
->index
].mode_mask
);
2788 if (AR_SREV_9462(ah
)) {
2790 * Starting from AR9462, each generic timer can select which tsf
2791 * to use. But we still follow the old rule, 0 - 7 use tsf and
2794 if ((timer
->index
< AR_GEN_TIMER_BANK_1_LEN
))
2795 REG_CLR_BIT(ah
, AR_MAC_PCU_GEN_TIMER_TSF_SEL
,
2796 (1 << timer
->index
));
2798 REG_SET_BIT(ah
, AR_MAC_PCU_GEN_TIMER_TSF_SEL
,
2799 (1 << timer
->index
));
2802 /* Enable both trigger and thresh interrupt masks */
2803 REG_SET_BIT(ah
, AR_IMR_S5
,
2804 (SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_THRESH
) |
2805 SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_TRIG
)));
2807 EXPORT_SYMBOL(ath9k_hw_gen_timer_start
);
2809 void ath9k_hw_gen_timer_stop(struct ath_hw
*ah
, struct ath_gen_timer
*timer
)
2811 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
2813 if ((timer
->index
< AR_FIRST_NDP_TIMER
) ||
2814 (timer
->index
>= ATH_MAX_GEN_TIMER
)) {
2818 /* Clear generic timer enable bits. */
2819 REG_CLR_BIT(ah
, gen_tmr_configuration
[timer
->index
].mode_addr
,
2820 gen_tmr_configuration
[timer
->index
].mode_mask
);
2822 /* Disable both trigger and thresh interrupt masks */
2823 REG_CLR_BIT(ah
, AR_IMR_S5
,
2824 (SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_THRESH
) |
2825 SM(AR_GENTMR_BIT(timer
->index
), AR_IMR_S5_GENTIMER_TRIG
)));
2827 clear_bit(timer
->index
, &timer_table
->timer_mask
.timer_bits
);
2829 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop
);
2831 void ath_gen_timer_free(struct ath_hw
*ah
, struct ath_gen_timer
*timer
)
2833 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
2835 /* free the hardware generic timer slot */
2836 timer_table
->timers
[timer
->index
] = NULL
;
2839 EXPORT_SYMBOL(ath_gen_timer_free
);
2842 * Generic Timer Interrupts handling
2844 void ath_gen_timer_isr(struct ath_hw
*ah
)
2846 struct ath_gen_timer_table
*timer_table
= &ah
->hw_gen_timers
;
2847 struct ath_gen_timer
*timer
;
2848 struct ath_common
*common
= ath9k_hw_common(ah
);
2849 u32 trigger_mask
, thresh_mask
, index
;
2851 /* get hardware generic timer interrupt status */
2852 trigger_mask
= ah
->intr_gen_timer_trigger
;
2853 thresh_mask
= ah
->intr_gen_timer_thresh
;
2854 trigger_mask
&= timer_table
->timer_mask
.val
;
2855 thresh_mask
&= timer_table
->timer_mask
.val
;
2857 trigger_mask
&= ~thresh_mask
;
2859 while (thresh_mask
) {
2860 index
= rightmost_index(timer_table
, &thresh_mask
);
2861 timer
= timer_table
->timers
[index
];
2863 ath_dbg(common
, ATH_DBG_HWTIMER
,
2864 "TSF overflow for Gen timer %d\n", index
);
2865 timer
->overflow(timer
->arg
);
2868 while (trigger_mask
) {
2869 index
= rightmost_index(timer_table
, &trigger_mask
);
2870 timer
= timer_table
->timers
[index
];
2872 ath_dbg(common
, ATH_DBG_HWTIMER
,
2873 "Gen timer[%d] trigger\n", index
);
2874 timer
->trigger(timer
->arg
);
2877 EXPORT_SYMBOL(ath_gen_timer_isr
);
2883 void ath9k_hw_htc_resetinit(struct ath_hw
*ah
)
2885 ah
->htc_reset_init
= true;
2887 EXPORT_SYMBOL(ath9k_hw_htc_resetinit
);
2892 } ath_mac_bb_names
[] = {
2893 /* Devices with external radios */
2894 { AR_SREV_VERSION_5416_PCI
, "5416" },
2895 { AR_SREV_VERSION_5416_PCIE
, "5418" },
2896 { AR_SREV_VERSION_9100
, "9100" },
2897 { AR_SREV_VERSION_9160
, "9160" },
2898 /* Single-chip solutions */
2899 { AR_SREV_VERSION_9280
, "9280" },
2900 { AR_SREV_VERSION_9285
, "9285" },
2901 { AR_SREV_VERSION_9287
, "9287" },
2902 { AR_SREV_VERSION_9271
, "9271" },
2903 { AR_SREV_VERSION_9300
, "9300" },
2904 { AR_SREV_VERSION_9330
, "9330" },
2905 { AR_SREV_VERSION_9340
, "9340" },
2906 { AR_SREV_VERSION_9485
, "9485" },
2907 { AR_SREV_VERSION_9462
, "9462" },
2910 /* For devices with external radios */
2914 } ath_rf_names
[] = {
2916 { AR_RAD5133_SREV_MAJOR
, "5133" },
2917 { AR_RAD5122_SREV_MAJOR
, "5122" },
2918 { AR_RAD2133_SREV_MAJOR
, "2133" },
2919 { AR_RAD2122_SREV_MAJOR
, "2122" }
2923 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2925 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version
)
2929 for (i
=0; i
<ARRAY_SIZE(ath_mac_bb_names
); i
++) {
2930 if (ath_mac_bb_names
[i
].version
== mac_bb_version
) {
2931 return ath_mac_bb_names
[i
].name
;
2939 * Return the RF name. "????" is returned if the RF is unknown.
2940 * Used for devices with external radios.
2942 static const char *ath9k_hw_rf_name(u16 rf_version
)
2946 for (i
=0; i
<ARRAY_SIZE(ath_rf_names
); i
++) {
2947 if (ath_rf_names
[i
].version
== rf_version
) {
2948 return ath_rf_names
[i
].name
;
2955 void ath9k_hw_name(struct ath_hw
*ah
, char *hw_name
, size_t len
)
2959 /* chipsets >= AR9280 are single-chip */
2960 if (AR_SREV_9280_20_OR_LATER(ah
)) {
2961 used
= snprintf(hw_name
, len
,
2962 "Atheros AR%s Rev:%x",
2963 ath9k_hw_mac_bb_name(ah
->hw_version
.macVersion
),
2964 ah
->hw_version
.macRev
);
2967 used
= snprintf(hw_name
, len
,
2968 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2969 ath9k_hw_mac_bb_name(ah
->hw_version
.macVersion
),
2970 ah
->hw_version
.macRev
,
2971 ath9k_hw_rf_name((ah
->hw_version
.analog5GhzRev
&
2972 AR_RADIO_SREV_MAJOR
)),
2973 ah
->hw_version
.phyRev
);
2976 hw_name
[used
] = '\0';
2978 EXPORT_SYMBOL(ath9k_hw_name
);