3 Broadcom B43 wireless driver
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/moduleparam.h>
34 #include <linux/if_arp.h>
35 #include <linux/etherdevice.h>
36 #include <linux/version.h>
37 #include <linux/firmware.h>
38 #include <linux/wireless.h>
39 #include <linux/workqueue.h>
40 #include <linux/skbuff.h>
42 #include <linux/dma-mapping.h>
43 #include <asm/unaligned.h>
57 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
58 MODULE_AUTHOR("Martin Langer");
59 MODULE_AUTHOR("Stefano Brivio");
60 MODULE_AUTHOR("Michael Buesch");
61 MODULE_LICENSE("GPL");
63 MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID
);
66 static int modparam_bad_frames_preempt
;
67 module_param_named(bad_frames_preempt
, modparam_bad_frames_preempt
, int, 0444);
68 MODULE_PARM_DESC(bad_frames_preempt
,
69 "enable(1) / disable(0) Bad Frames Preemption");
71 static char modparam_fwpostfix
[16];
72 module_param_string(fwpostfix
, modparam_fwpostfix
, 16, 0444);
73 MODULE_PARM_DESC(fwpostfix
, "Postfix for the .fw files to load.");
75 static int modparam_hwpctl
;
76 module_param_named(hwpctl
, modparam_hwpctl
, int, 0444);
77 MODULE_PARM_DESC(hwpctl
, "Enable hardware-side power control (default off)");
79 static int modparam_nohwcrypt
;
80 module_param_named(nohwcrypt
, modparam_nohwcrypt
, int, 0444);
81 MODULE_PARM_DESC(nohwcrypt
, "Disable hardware encryption.");
83 int b43_modparam_qos
= 1;
84 module_param_named(qos
, b43_modparam_qos
, int, 0444);
85 MODULE_PARM_DESC(qos
, "Enable QOS support (default on)");
87 static int modparam_btcoex
= 1;
88 module_param_named(btcoex
, modparam_btcoex
, int, 0444);
89 MODULE_PARM_DESC(btcoex
, "Enable Bluetooth coexistance (default on)");
92 static const struct ssb_device_id b43_ssb_tbl
[] = {
93 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 5),
94 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 6),
95 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 7),
96 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 9),
97 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 10),
98 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 11),
99 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, 13),
103 MODULE_DEVICE_TABLE(ssb
, b43_ssb_tbl
);
105 /* Channel and ratetables are shared for all devices.
106 * They can't be const, because ieee80211 puts some precalculated
107 * data in there. This data is the same for all devices, so we don't
108 * get concurrency issues */
109 #define RATETAB_ENT(_rateid, _flags) \
111 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
112 .hw_value = (_rateid), \
117 * NOTE: When changing this, sync with xmit.c's
118 * b43_plcp_get_bitrate_idx_* functions!
120 static struct ieee80211_rate __b43_ratetable
[] = {
121 RATETAB_ENT(B43_CCK_RATE_1MB
, 0),
122 RATETAB_ENT(B43_CCK_RATE_2MB
, IEEE80211_RATE_SHORT_PREAMBLE
),
123 RATETAB_ENT(B43_CCK_RATE_5MB
, IEEE80211_RATE_SHORT_PREAMBLE
),
124 RATETAB_ENT(B43_CCK_RATE_11MB
, IEEE80211_RATE_SHORT_PREAMBLE
),
125 RATETAB_ENT(B43_OFDM_RATE_6MB
, 0),
126 RATETAB_ENT(B43_OFDM_RATE_9MB
, 0),
127 RATETAB_ENT(B43_OFDM_RATE_12MB
, 0),
128 RATETAB_ENT(B43_OFDM_RATE_18MB
, 0),
129 RATETAB_ENT(B43_OFDM_RATE_24MB
, 0),
130 RATETAB_ENT(B43_OFDM_RATE_36MB
, 0),
131 RATETAB_ENT(B43_OFDM_RATE_48MB
, 0),
132 RATETAB_ENT(B43_OFDM_RATE_54MB
, 0),
135 #define b43_a_ratetable (__b43_ratetable + 4)
136 #define b43_a_ratetable_size 8
137 #define b43_b_ratetable (__b43_ratetable + 0)
138 #define b43_b_ratetable_size 4
139 #define b43_g_ratetable (__b43_ratetable + 0)
140 #define b43_g_ratetable_size 12
142 #define CHAN4G(_channel, _freq, _flags) { \
143 .band = IEEE80211_BAND_2GHZ, \
144 .center_freq = (_freq), \
145 .hw_value = (_channel), \
147 .max_antenna_gain = 0, \
150 static struct ieee80211_channel b43_2ghz_chantable
[] = {
168 #define CHAN5G(_channel, _flags) { \
169 .band = IEEE80211_BAND_5GHZ, \
170 .center_freq = 5000 + (5 * (_channel)), \
171 .hw_value = (_channel), \
173 .max_antenna_gain = 0, \
176 static struct ieee80211_channel b43_5ghz_nphy_chantable
[] = {
177 CHAN5G(32, 0), CHAN5G(34, 0),
178 CHAN5G(36, 0), CHAN5G(38, 0),
179 CHAN5G(40, 0), CHAN5G(42, 0),
180 CHAN5G(44, 0), CHAN5G(46, 0),
181 CHAN5G(48, 0), CHAN5G(50, 0),
182 CHAN5G(52, 0), CHAN5G(54, 0),
183 CHAN5G(56, 0), CHAN5G(58, 0),
184 CHAN5G(60, 0), CHAN5G(62, 0),
185 CHAN5G(64, 0), CHAN5G(66, 0),
186 CHAN5G(68, 0), CHAN5G(70, 0),
187 CHAN5G(72, 0), CHAN5G(74, 0),
188 CHAN5G(76, 0), CHAN5G(78, 0),
189 CHAN5G(80, 0), CHAN5G(82, 0),
190 CHAN5G(84, 0), CHAN5G(86, 0),
191 CHAN5G(88, 0), CHAN5G(90, 0),
192 CHAN5G(92, 0), CHAN5G(94, 0),
193 CHAN5G(96, 0), CHAN5G(98, 0),
194 CHAN5G(100, 0), CHAN5G(102, 0),
195 CHAN5G(104, 0), CHAN5G(106, 0),
196 CHAN5G(108, 0), CHAN5G(110, 0),
197 CHAN5G(112, 0), CHAN5G(114, 0),
198 CHAN5G(116, 0), CHAN5G(118, 0),
199 CHAN5G(120, 0), CHAN5G(122, 0),
200 CHAN5G(124, 0), CHAN5G(126, 0),
201 CHAN5G(128, 0), CHAN5G(130, 0),
202 CHAN5G(132, 0), CHAN5G(134, 0),
203 CHAN5G(136, 0), CHAN5G(138, 0),
204 CHAN5G(140, 0), CHAN5G(142, 0),
205 CHAN5G(144, 0), CHAN5G(145, 0),
206 CHAN5G(146, 0), CHAN5G(147, 0),
207 CHAN5G(148, 0), CHAN5G(149, 0),
208 CHAN5G(150, 0), CHAN5G(151, 0),
209 CHAN5G(152, 0), CHAN5G(153, 0),
210 CHAN5G(154, 0), CHAN5G(155, 0),
211 CHAN5G(156, 0), CHAN5G(157, 0),
212 CHAN5G(158, 0), CHAN5G(159, 0),
213 CHAN5G(160, 0), CHAN5G(161, 0),
214 CHAN5G(162, 0), CHAN5G(163, 0),
215 CHAN5G(164, 0), CHAN5G(165, 0),
216 CHAN5G(166, 0), CHAN5G(168, 0),
217 CHAN5G(170, 0), CHAN5G(172, 0),
218 CHAN5G(174, 0), CHAN5G(176, 0),
219 CHAN5G(178, 0), CHAN5G(180, 0),
220 CHAN5G(182, 0), CHAN5G(184, 0),
221 CHAN5G(186, 0), CHAN5G(188, 0),
222 CHAN5G(190, 0), CHAN5G(192, 0),
223 CHAN5G(194, 0), CHAN5G(196, 0),
224 CHAN5G(198, 0), CHAN5G(200, 0),
225 CHAN5G(202, 0), CHAN5G(204, 0),
226 CHAN5G(206, 0), CHAN5G(208, 0),
227 CHAN5G(210, 0), CHAN5G(212, 0),
228 CHAN5G(214, 0), CHAN5G(216, 0),
229 CHAN5G(218, 0), CHAN5G(220, 0),
230 CHAN5G(222, 0), CHAN5G(224, 0),
231 CHAN5G(226, 0), CHAN5G(228, 0),
234 static struct ieee80211_channel b43_5ghz_aphy_chantable
[] = {
235 CHAN5G(34, 0), CHAN5G(36, 0),
236 CHAN5G(38, 0), CHAN5G(40, 0),
237 CHAN5G(42, 0), CHAN5G(44, 0),
238 CHAN5G(46, 0), CHAN5G(48, 0),
239 CHAN5G(52, 0), CHAN5G(56, 0),
240 CHAN5G(60, 0), CHAN5G(64, 0),
241 CHAN5G(100, 0), CHAN5G(104, 0),
242 CHAN5G(108, 0), CHAN5G(112, 0),
243 CHAN5G(116, 0), CHAN5G(120, 0),
244 CHAN5G(124, 0), CHAN5G(128, 0),
245 CHAN5G(132, 0), CHAN5G(136, 0),
246 CHAN5G(140, 0), CHAN5G(149, 0),
247 CHAN5G(153, 0), CHAN5G(157, 0),
248 CHAN5G(161, 0), CHAN5G(165, 0),
249 CHAN5G(184, 0), CHAN5G(188, 0),
250 CHAN5G(192, 0), CHAN5G(196, 0),
251 CHAN5G(200, 0), CHAN5G(204, 0),
252 CHAN5G(208, 0), CHAN5G(212, 0),
257 static struct ieee80211_supported_band b43_band_5GHz_nphy
= {
258 .band
= IEEE80211_BAND_5GHZ
,
259 .channels
= b43_5ghz_nphy_chantable
,
260 .n_channels
= ARRAY_SIZE(b43_5ghz_nphy_chantable
),
261 .bitrates
= b43_a_ratetable
,
262 .n_bitrates
= b43_a_ratetable_size
,
265 static struct ieee80211_supported_band b43_band_5GHz_aphy
= {
266 .band
= IEEE80211_BAND_5GHZ
,
267 .channels
= b43_5ghz_aphy_chantable
,
268 .n_channels
= ARRAY_SIZE(b43_5ghz_aphy_chantable
),
269 .bitrates
= b43_a_ratetable
,
270 .n_bitrates
= b43_a_ratetable_size
,
273 static struct ieee80211_supported_band b43_band_2GHz
= {
274 .band
= IEEE80211_BAND_2GHZ
,
275 .channels
= b43_2ghz_chantable
,
276 .n_channels
= ARRAY_SIZE(b43_2ghz_chantable
),
277 .bitrates
= b43_g_ratetable
,
278 .n_bitrates
= b43_g_ratetable_size
,
281 static void b43_wireless_core_exit(struct b43_wldev
*dev
);
282 static int b43_wireless_core_init(struct b43_wldev
*dev
);
283 static void b43_wireless_core_stop(struct b43_wldev
*dev
);
284 static int b43_wireless_core_start(struct b43_wldev
*dev
);
286 static int b43_ratelimit(struct b43_wl
*wl
)
288 if (!wl
|| !wl
->current_dev
)
290 if (b43_status(wl
->current_dev
) < B43_STAT_STARTED
)
292 /* We are up and running.
293 * Ratelimit the messages to avoid DoS over the net. */
294 return net_ratelimit();
297 void b43info(struct b43_wl
*wl
, const char *fmt
, ...)
301 if (!b43_ratelimit(wl
))
304 printk(KERN_INFO
"b43-%s: ",
305 (wl
&& wl
->hw
) ? wiphy_name(wl
->hw
->wiphy
) : "wlan");
310 void b43err(struct b43_wl
*wl
, const char *fmt
, ...)
314 if (!b43_ratelimit(wl
))
317 printk(KERN_ERR
"b43-%s ERROR: ",
318 (wl
&& wl
->hw
) ? wiphy_name(wl
->hw
->wiphy
) : "wlan");
323 void b43warn(struct b43_wl
*wl
, const char *fmt
, ...)
327 if (!b43_ratelimit(wl
))
330 printk(KERN_WARNING
"b43-%s warning: ",
331 (wl
&& wl
->hw
) ? wiphy_name(wl
->hw
->wiphy
) : "wlan");
337 void b43dbg(struct b43_wl
*wl
, const char *fmt
, ...)
342 printk(KERN_DEBUG
"b43-%s debug: ",
343 (wl
&& wl
->hw
) ? wiphy_name(wl
->hw
->wiphy
) : "wlan");
349 static void b43_ram_write(struct b43_wldev
*dev
, u16 offset
, u32 val
)
353 B43_WARN_ON(offset
% 4 != 0);
355 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
356 if (macctl
& B43_MACCTL_BE
)
359 b43_write32(dev
, B43_MMIO_RAM_CONTROL
, offset
);
361 b43_write32(dev
, B43_MMIO_RAM_DATA
, val
);
364 static inline void b43_shm_control_word(struct b43_wldev
*dev
,
365 u16 routing
, u16 offset
)
369 /* "offset" is the WORD offset. */
373 b43_write32(dev
, B43_MMIO_SHM_CONTROL
, control
);
376 u32
b43_shm_read32(struct b43_wldev
*dev
, u16 routing
, u16 offset
)
378 struct b43_wl
*wl
= dev
->wl
;
382 spin_lock_irqsave(&wl
->shm_lock
, flags
);
383 if (routing
== B43_SHM_SHARED
) {
384 B43_WARN_ON(offset
& 0x0001);
385 if (offset
& 0x0003) {
386 /* Unaligned access */
387 b43_shm_control_word(dev
, routing
, offset
>> 2);
388 ret
= b43_read16(dev
, B43_MMIO_SHM_DATA_UNALIGNED
);
390 b43_shm_control_word(dev
, routing
, (offset
>> 2) + 1);
391 ret
|= b43_read16(dev
, B43_MMIO_SHM_DATA
);
397 b43_shm_control_word(dev
, routing
, offset
);
398 ret
= b43_read32(dev
, B43_MMIO_SHM_DATA
);
400 spin_unlock_irqrestore(&wl
->shm_lock
, flags
);
405 u16
b43_shm_read16(struct b43_wldev
* dev
, u16 routing
, u16 offset
)
407 struct b43_wl
*wl
= dev
->wl
;
411 spin_lock_irqsave(&wl
->shm_lock
, flags
);
412 if (routing
== B43_SHM_SHARED
) {
413 B43_WARN_ON(offset
& 0x0001);
414 if (offset
& 0x0003) {
415 /* Unaligned access */
416 b43_shm_control_word(dev
, routing
, offset
>> 2);
417 ret
= b43_read16(dev
, B43_MMIO_SHM_DATA_UNALIGNED
);
423 b43_shm_control_word(dev
, routing
, offset
);
424 ret
= b43_read16(dev
, B43_MMIO_SHM_DATA
);
426 spin_unlock_irqrestore(&wl
->shm_lock
, flags
);
431 void b43_shm_write32(struct b43_wldev
*dev
, u16 routing
, u16 offset
, u32 value
)
433 struct b43_wl
*wl
= dev
->wl
;
436 spin_lock_irqsave(&wl
->shm_lock
, flags
);
437 if (routing
== B43_SHM_SHARED
) {
438 B43_WARN_ON(offset
& 0x0001);
439 if (offset
& 0x0003) {
440 /* Unaligned access */
441 b43_shm_control_word(dev
, routing
, offset
>> 2);
442 b43_write16(dev
, B43_MMIO_SHM_DATA_UNALIGNED
,
443 (value
>> 16) & 0xffff);
444 b43_shm_control_word(dev
, routing
, (offset
>> 2) + 1);
445 b43_write16(dev
, B43_MMIO_SHM_DATA
, value
& 0xffff);
450 b43_shm_control_word(dev
, routing
, offset
);
451 b43_write32(dev
, B43_MMIO_SHM_DATA
, value
);
453 spin_unlock_irqrestore(&wl
->shm_lock
, flags
);
456 void b43_shm_write16(struct b43_wldev
*dev
, u16 routing
, u16 offset
, u16 value
)
458 struct b43_wl
*wl
= dev
->wl
;
461 spin_lock_irqsave(&wl
->shm_lock
, flags
);
462 if (routing
== B43_SHM_SHARED
) {
463 B43_WARN_ON(offset
& 0x0001);
464 if (offset
& 0x0003) {
465 /* Unaligned access */
466 b43_shm_control_word(dev
, routing
, offset
>> 2);
467 b43_write16(dev
, B43_MMIO_SHM_DATA_UNALIGNED
, value
);
472 b43_shm_control_word(dev
, routing
, offset
);
473 b43_write16(dev
, B43_MMIO_SHM_DATA
, value
);
475 spin_unlock_irqrestore(&wl
->shm_lock
, flags
);
479 u64
b43_hf_read(struct b43_wldev
* dev
)
483 ret
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_HOSTFHI
);
485 ret
|= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_HOSTFMI
);
487 ret
|= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_HOSTFLO
);
492 /* Write HostFlags */
493 void b43_hf_write(struct b43_wldev
*dev
, u64 value
)
497 lo
= (value
& 0x00000000FFFFULL
);
498 mi
= (value
& 0x0000FFFF0000ULL
) >> 16;
499 hi
= (value
& 0xFFFF00000000ULL
) >> 32;
500 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_HOSTFLO
, lo
);
501 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_HOSTFMI
, mi
);
502 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_HOSTFHI
, hi
);
505 void b43_tsf_read(struct b43_wldev
*dev
, u64
* tsf
)
507 /* We need to be careful. As we read the TSF from multiple
508 * registers, we should take care of register overflows.
509 * In theory, the whole tsf read process should be atomic.
510 * We try to be atomic here, by restaring the read process,
511 * if any of the high registers changed (overflew).
513 if (dev
->dev
->id
.revision
>= 3) {
514 u32 low
, high
, high2
;
517 high
= b43_read32(dev
, B43_MMIO_REV3PLUS_TSF_HIGH
);
518 low
= b43_read32(dev
, B43_MMIO_REV3PLUS_TSF_LOW
);
519 high2
= b43_read32(dev
, B43_MMIO_REV3PLUS_TSF_HIGH
);
520 } while (unlikely(high
!= high2
));
528 u16 test1
, test2
, test3
;
531 v3
= b43_read16(dev
, B43_MMIO_TSF_3
);
532 v2
= b43_read16(dev
, B43_MMIO_TSF_2
);
533 v1
= b43_read16(dev
, B43_MMIO_TSF_1
);
534 v0
= b43_read16(dev
, B43_MMIO_TSF_0
);
536 test3
= b43_read16(dev
, B43_MMIO_TSF_3
);
537 test2
= b43_read16(dev
, B43_MMIO_TSF_2
);
538 test1
= b43_read16(dev
, B43_MMIO_TSF_1
);
539 } while (v3
!= test3
|| v2
!= test2
|| v1
!= test1
);
553 static void b43_time_lock(struct b43_wldev
*dev
)
557 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
558 macctl
|= B43_MACCTL_TBTTHOLD
;
559 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
560 /* Commit the write */
561 b43_read32(dev
, B43_MMIO_MACCTL
);
564 static void b43_time_unlock(struct b43_wldev
*dev
)
568 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
569 macctl
&= ~B43_MACCTL_TBTTHOLD
;
570 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
571 /* Commit the write */
572 b43_read32(dev
, B43_MMIO_MACCTL
);
575 static void b43_tsf_write_locked(struct b43_wldev
*dev
, u64 tsf
)
577 /* Be careful with the in-progress timer.
578 * First zero out the low register, so we have a full
579 * register-overflow duration to complete the operation.
581 if (dev
->dev
->id
.revision
>= 3) {
582 u32 lo
= (tsf
& 0x00000000FFFFFFFFULL
);
583 u32 hi
= (tsf
& 0xFFFFFFFF00000000ULL
) >> 32;
585 b43_write32(dev
, B43_MMIO_REV3PLUS_TSF_LOW
, 0);
587 b43_write32(dev
, B43_MMIO_REV3PLUS_TSF_HIGH
, hi
);
589 b43_write32(dev
, B43_MMIO_REV3PLUS_TSF_LOW
, lo
);
591 u16 v0
= (tsf
& 0x000000000000FFFFULL
);
592 u16 v1
= (tsf
& 0x00000000FFFF0000ULL
) >> 16;
593 u16 v2
= (tsf
& 0x0000FFFF00000000ULL
) >> 32;
594 u16 v3
= (tsf
& 0xFFFF000000000000ULL
) >> 48;
596 b43_write16(dev
, B43_MMIO_TSF_0
, 0);
598 b43_write16(dev
, B43_MMIO_TSF_3
, v3
);
600 b43_write16(dev
, B43_MMIO_TSF_2
, v2
);
602 b43_write16(dev
, B43_MMIO_TSF_1
, v1
);
604 b43_write16(dev
, B43_MMIO_TSF_0
, v0
);
608 void b43_tsf_write(struct b43_wldev
*dev
, u64 tsf
)
611 b43_tsf_write_locked(dev
, tsf
);
612 b43_time_unlock(dev
);
616 void b43_macfilter_set(struct b43_wldev
*dev
, u16 offset
, const u8
* mac
)
618 static const u8 zero_addr
[ETH_ALEN
] = { 0 };
625 b43_write16(dev
, B43_MMIO_MACFILTER_CONTROL
, offset
);
629 b43_write16(dev
, B43_MMIO_MACFILTER_DATA
, data
);
632 b43_write16(dev
, B43_MMIO_MACFILTER_DATA
, data
);
635 b43_write16(dev
, B43_MMIO_MACFILTER_DATA
, data
);
638 static void b43_write_mac_bssid_templates(struct b43_wldev
*dev
)
642 u8 mac_bssid
[ETH_ALEN
* 2];
646 bssid
= dev
->wl
->bssid
;
647 mac
= dev
->wl
->mac_addr
;
649 b43_macfilter_set(dev
, B43_MACFILTER_BSSID
, bssid
);
651 memcpy(mac_bssid
, mac
, ETH_ALEN
);
652 memcpy(mac_bssid
+ ETH_ALEN
, bssid
, ETH_ALEN
);
654 /* Write our MAC address and BSSID to template ram */
655 for (i
= 0; i
< ARRAY_SIZE(mac_bssid
); i
+= sizeof(u32
)) {
656 tmp
= (u32
) (mac_bssid
[i
+ 0]);
657 tmp
|= (u32
) (mac_bssid
[i
+ 1]) << 8;
658 tmp
|= (u32
) (mac_bssid
[i
+ 2]) << 16;
659 tmp
|= (u32
) (mac_bssid
[i
+ 3]) << 24;
660 b43_ram_write(dev
, 0x20 + i
, tmp
);
664 static void b43_upload_card_macaddress(struct b43_wldev
*dev
)
666 b43_write_mac_bssid_templates(dev
);
667 b43_macfilter_set(dev
, B43_MACFILTER_SELF
, dev
->wl
->mac_addr
);
670 static void b43_set_slot_time(struct b43_wldev
*dev
, u16 slot_time
)
672 /* slot_time is in usec. */
673 if (dev
->phy
.type
!= B43_PHYTYPE_G
)
675 b43_write16(dev
, 0x684, 510 + slot_time
);
676 b43_shm_write16(dev
, B43_SHM_SHARED
, 0x0010, slot_time
);
679 static void b43_short_slot_timing_enable(struct b43_wldev
*dev
)
681 b43_set_slot_time(dev
, 9);
685 static void b43_short_slot_timing_disable(struct b43_wldev
*dev
)
687 b43_set_slot_time(dev
, 20);
691 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
692 * Returns the _previously_ enabled IRQ mask.
694 static inline u32
b43_interrupt_enable(struct b43_wldev
*dev
, u32 mask
)
698 old_mask
= b43_read32(dev
, B43_MMIO_GEN_IRQ_MASK
);
699 b43_write32(dev
, B43_MMIO_GEN_IRQ_MASK
, old_mask
| mask
);
704 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
705 * Returns the _previously_ enabled IRQ mask.
707 static inline u32
b43_interrupt_disable(struct b43_wldev
*dev
, u32 mask
)
711 old_mask
= b43_read32(dev
, B43_MMIO_GEN_IRQ_MASK
);
712 b43_write32(dev
, B43_MMIO_GEN_IRQ_MASK
, old_mask
& ~mask
);
717 /* Synchronize IRQ top- and bottom-half.
718 * IRQs must be masked before calling this.
719 * This must not be called with the irq_lock held.
721 static void b43_synchronize_irq(struct b43_wldev
*dev
)
723 synchronize_irq(dev
->dev
->irq
);
724 tasklet_kill(&dev
->isr_tasklet
);
727 /* DummyTransmission function, as documented on
728 * http://bcm-specs.sipsolutions.net/DummyTransmission
730 void b43_dummy_transmission(struct b43_wldev
*dev
)
732 struct b43_wl
*wl
= dev
->wl
;
733 struct b43_phy
*phy
= &dev
->phy
;
734 unsigned int i
, max_loop
;
747 buffer
[0] = 0x000201CC;
752 buffer
[0] = 0x000B846E;
759 spin_lock_irq(&wl
->irq_lock
);
760 write_lock(&wl
->tx_lock
);
762 for (i
= 0; i
< 5; i
++)
763 b43_ram_write(dev
, i
* 4, buffer
[i
]);
766 b43_read32(dev
, B43_MMIO_MACCTL
);
768 b43_write16(dev
, 0x0568, 0x0000);
769 b43_write16(dev
, 0x07C0, 0x0000);
770 value
= ((phy
->type
== B43_PHYTYPE_A
) ? 1 : 0);
771 b43_write16(dev
, 0x050C, value
);
772 b43_write16(dev
, 0x0508, 0x0000);
773 b43_write16(dev
, 0x050A, 0x0000);
774 b43_write16(dev
, 0x054C, 0x0000);
775 b43_write16(dev
, 0x056A, 0x0014);
776 b43_write16(dev
, 0x0568, 0x0826);
777 b43_write16(dev
, 0x0500, 0x0000);
778 b43_write16(dev
, 0x0502, 0x0030);
780 if (phy
->radio_ver
== 0x2050 && phy
->radio_rev
<= 0x5)
781 b43_radio_write16(dev
, 0x0051, 0x0017);
782 for (i
= 0x00; i
< max_loop
; i
++) {
783 value
= b43_read16(dev
, 0x050E);
788 for (i
= 0x00; i
< 0x0A; i
++) {
789 value
= b43_read16(dev
, 0x050E);
794 for (i
= 0x00; i
< 0x0A; i
++) {
795 value
= b43_read16(dev
, 0x0690);
796 if (!(value
& 0x0100))
800 if (phy
->radio_ver
== 0x2050 && phy
->radio_rev
<= 0x5)
801 b43_radio_write16(dev
, 0x0051, 0x0037);
803 write_unlock(&wl
->tx_lock
);
804 spin_unlock_irq(&wl
->irq_lock
);
807 static void key_write(struct b43_wldev
*dev
,
808 u8 index
, u8 algorithm
, const u8
* key
)
815 /* Key index/algo block */
816 kidx
= b43_kidx_to_fw(dev
, index
);
817 value
= ((kidx
<< 4) | algorithm
);
818 b43_shm_write16(dev
, B43_SHM_SHARED
,
819 B43_SHM_SH_KEYIDXBLOCK
+ (kidx
* 2), value
);
821 /* Write the key to the Key Table Pointer offset */
822 offset
= dev
->ktp
+ (index
* B43_SEC_KEYSIZE
);
823 for (i
= 0; i
< B43_SEC_KEYSIZE
; i
+= 2) {
825 value
|= (u16
) (key
[i
+ 1]) << 8;
826 b43_shm_write16(dev
, B43_SHM_SHARED
, offset
+ i
, value
);
830 static void keymac_write(struct b43_wldev
*dev
, u8 index
, const u8
* addr
)
832 u32 addrtmp
[2] = { 0, 0, };
833 u8 per_sta_keys_start
= 8;
835 if (b43_new_kidx_api(dev
))
836 per_sta_keys_start
= 4;
838 B43_WARN_ON(index
< per_sta_keys_start
);
839 /* We have two default TX keys and possibly two default RX keys.
840 * Physical mac 0 is mapped to physical key 4 or 8, depending
841 * on the firmware version.
842 * So we must adjust the index here.
844 index
-= per_sta_keys_start
;
847 addrtmp
[0] = addr
[0];
848 addrtmp
[0] |= ((u32
) (addr
[1]) << 8);
849 addrtmp
[0] |= ((u32
) (addr
[2]) << 16);
850 addrtmp
[0] |= ((u32
) (addr
[3]) << 24);
851 addrtmp
[1] = addr
[4];
852 addrtmp
[1] |= ((u32
) (addr
[5]) << 8);
855 if (dev
->dev
->id
.revision
>= 5) {
856 /* Receive match transmitter address mechanism */
857 b43_shm_write32(dev
, B43_SHM_RCMTA
,
858 (index
* 2) + 0, addrtmp
[0]);
859 b43_shm_write16(dev
, B43_SHM_RCMTA
,
860 (index
* 2) + 1, addrtmp
[1]);
862 /* RXE (Receive Engine) and
863 * PSM (Programmable State Machine) mechanism
866 /* TODO write to RCM 16, 19, 22 and 25 */
868 b43_shm_write32(dev
, B43_SHM_SHARED
,
869 B43_SHM_SH_PSM
+ (index
* 6) + 0,
871 b43_shm_write16(dev
, B43_SHM_SHARED
,
872 B43_SHM_SH_PSM
+ (index
* 6) + 4,
878 static void do_key_write(struct b43_wldev
*dev
,
879 u8 index
, u8 algorithm
,
880 const u8
* key
, size_t key_len
, const u8
* mac_addr
)
882 u8 buf
[B43_SEC_KEYSIZE
] = { 0, };
883 u8 per_sta_keys_start
= 8;
885 if (b43_new_kidx_api(dev
))
886 per_sta_keys_start
= 4;
888 B43_WARN_ON(index
>= dev
->max_nr_keys
);
889 B43_WARN_ON(key_len
> B43_SEC_KEYSIZE
);
891 if (index
>= per_sta_keys_start
)
892 keymac_write(dev
, index
, NULL
); /* First zero out mac. */
894 memcpy(buf
, key
, key_len
);
895 key_write(dev
, index
, algorithm
, buf
);
896 if (index
>= per_sta_keys_start
)
897 keymac_write(dev
, index
, mac_addr
);
899 dev
->key
[index
].algorithm
= algorithm
;
902 static int b43_key_write(struct b43_wldev
*dev
,
903 int index
, u8 algorithm
,
904 const u8
* key
, size_t key_len
,
906 struct ieee80211_key_conf
*keyconf
)
911 if (key_len
> B43_SEC_KEYSIZE
)
913 for (i
= 0; i
< dev
->max_nr_keys
; i
++) {
914 /* Check that we don't already have this key. */
915 B43_WARN_ON(dev
->key
[i
].keyconf
== keyconf
);
918 /* Either pairwise key or address is 00:00:00:00:00:00
919 * for transmit-only keys. Search the index. */
920 if (b43_new_kidx_api(dev
))
924 for (i
= sta_keys_start
; i
< dev
->max_nr_keys
; i
++) {
925 if (!dev
->key
[i
].keyconf
) {
932 b43err(dev
->wl
, "Out of hardware key memory\n");
936 B43_WARN_ON(index
> 3);
938 do_key_write(dev
, index
, algorithm
, key
, key_len
, mac_addr
);
939 if ((index
<= 3) && !b43_new_kidx_api(dev
)) {
941 B43_WARN_ON(mac_addr
);
942 do_key_write(dev
, index
+ 4, algorithm
, key
, key_len
, NULL
);
944 keyconf
->hw_key_idx
= index
;
945 dev
->key
[index
].keyconf
= keyconf
;
950 static int b43_key_clear(struct b43_wldev
*dev
, int index
)
952 if (B43_WARN_ON((index
< 0) || (index
>= dev
->max_nr_keys
)))
954 do_key_write(dev
, index
, B43_SEC_ALGO_NONE
,
955 NULL
, B43_SEC_KEYSIZE
, NULL
);
956 if ((index
<= 3) && !b43_new_kidx_api(dev
)) {
957 do_key_write(dev
, index
+ 4, B43_SEC_ALGO_NONE
,
958 NULL
, B43_SEC_KEYSIZE
, NULL
);
960 dev
->key
[index
].keyconf
= NULL
;
965 static void b43_clear_keys(struct b43_wldev
*dev
)
969 for (i
= 0; i
< dev
->max_nr_keys
; i
++)
970 b43_key_clear(dev
, i
);
973 void b43_power_saving_ctl_bits(struct b43_wldev
*dev
, unsigned int ps_flags
)
981 B43_WARN_ON((ps_flags
& B43_PS_ENABLED
) &&
982 (ps_flags
& B43_PS_DISABLED
));
983 B43_WARN_ON((ps_flags
& B43_PS_AWAKE
) && (ps_flags
& B43_PS_ASLEEP
));
985 if (ps_flags
& B43_PS_ENABLED
) {
987 } else if (ps_flags
& B43_PS_DISABLED
) {
990 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
991 // and thus is not an AP and we are associated, set bit 25
993 if (ps_flags
& B43_PS_AWAKE
) {
995 } else if (ps_flags
& B43_PS_ASLEEP
) {
998 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
999 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1000 // successful, set bit26
1003 /* FIXME: For now we force awake-on and hwps-off */
1007 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
1009 macctl
|= B43_MACCTL_HWPS
;
1011 macctl
&= ~B43_MACCTL_HWPS
;
1013 macctl
|= B43_MACCTL_AWAKE
;
1015 macctl
&= ~B43_MACCTL_AWAKE
;
1016 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
1018 b43_read32(dev
, B43_MMIO_MACCTL
);
1019 if (awake
&& dev
->dev
->id
.revision
>= 5) {
1020 /* Wait for the microcode to wake up. */
1021 for (i
= 0; i
< 100; i
++) {
1022 ucstat
= b43_shm_read16(dev
, B43_SHM_SHARED
,
1023 B43_SHM_SH_UCODESTAT
);
1024 if (ucstat
!= B43_SHM_SH_UCODESTAT_SLEEP
)
1031 /* Turn the Analog ON/OFF */
1032 static void b43_switch_analog(struct b43_wldev
*dev
, int on
)
1034 switch (dev
->phy
.type
) {
1037 b43_write16(dev
, B43_MMIO_PHY0
, on
? 0 : 0xF4);
1040 b43_phy_write(dev
, B43_NPHY_AFECTL_OVER
,
1048 void b43_wireless_core_reset(struct b43_wldev
*dev
, u32 flags
)
1053 flags
|= B43_TMSLOW_PHYCLKEN
;
1054 flags
|= B43_TMSLOW_PHYRESET
;
1055 ssb_device_enable(dev
->dev
, flags
);
1056 msleep(2); /* Wait for the PLL to turn on. */
1058 /* Now take the PHY out of Reset again */
1059 tmslow
= ssb_read32(dev
->dev
, SSB_TMSLOW
);
1060 tmslow
|= SSB_TMSLOW_FGC
;
1061 tmslow
&= ~B43_TMSLOW_PHYRESET
;
1062 ssb_write32(dev
->dev
, SSB_TMSLOW
, tmslow
);
1063 ssb_read32(dev
->dev
, SSB_TMSLOW
); /* flush */
1065 tmslow
&= ~SSB_TMSLOW_FGC
;
1066 ssb_write32(dev
->dev
, SSB_TMSLOW
, tmslow
);
1067 ssb_read32(dev
->dev
, SSB_TMSLOW
); /* flush */
1070 /* Turn Analog ON */
1071 b43_switch_analog(dev
, 1);
1073 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
1074 macctl
&= ~B43_MACCTL_GMODE
;
1075 if (flags
& B43_TMSLOW_GMODE
)
1076 macctl
|= B43_MACCTL_GMODE
;
1077 macctl
|= B43_MACCTL_IHR_ENABLED
;
1078 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
1081 static void handle_irq_transmit_status(struct b43_wldev
*dev
)
1085 struct b43_txstatus stat
;
1088 v0
= b43_read32(dev
, B43_MMIO_XMITSTAT_0
);
1089 if (!(v0
& 0x00000001))
1091 v1
= b43_read32(dev
, B43_MMIO_XMITSTAT_1
);
1093 stat
.cookie
= (v0
>> 16);
1094 stat
.seq
= (v1
& 0x0000FFFF);
1095 stat
.phy_stat
= ((v1
& 0x00FF0000) >> 16);
1096 tmp
= (v0
& 0x0000FFFF);
1097 stat
.frame_count
= ((tmp
& 0xF000) >> 12);
1098 stat
.rts_count
= ((tmp
& 0x0F00) >> 8);
1099 stat
.supp_reason
= ((tmp
& 0x001C) >> 2);
1100 stat
.pm_indicated
= !!(tmp
& 0x0080);
1101 stat
.intermediate
= !!(tmp
& 0x0040);
1102 stat
.for_ampdu
= !!(tmp
& 0x0020);
1103 stat
.acked
= !!(tmp
& 0x0002);
1105 b43_handle_txstatus(dev
, &stat
);
1109 static void drain_txstatus_queue(struct b43_wldev
*dev
)
1113 if (dev
->dev
->id
.revision
< 5)
1115 /* Read all entries from the microcode TXstatus FIFO
1116 * and throw them away.
1119 dummy
= b43_read32(dev
, B43_MMIO_XMITSTAT_0
);
1120 if (!(dummy
& 0x00000001))
1122 dummy
= b43_read32(dev
, B43_MMIO_XMITSTAT_1
);
1126 static u32
b43_jssi_read(struct b43_wldev
*dev
)
1130 val
= b43_shm_read16(dev
, B43_SHM_SHARED
, 0x08A);
1132 val
|= b43_shm_read16(dev
, B43_SHM_SHARED
, 0x088);
1137 static void b43_jssi_write(struct b43_wldev
*dev
, u32 jssi
)
1139 b43_shm_write16(dev
, B43_SHM_SHARED
, 0x088, (jssi
& 0x0000FFFF));
1140 b43_shm_write16(dev
, B43_SHM_SHARED
, 0x08A, (jssi
& 0xFFFF0000) >> 16);
1143 static void b43_generate_noise_sample(struct b43_wldev
*dev
)
1145 b43_jssi_write(dev
, 0x7F7F7F7F);
1146 b43_write32(dev
, B43_MMIO_MACCMD
,
1147 b43_read32(dev
, B43_MMIO_MACCMD
) | B43_MACCMD_BGNOISE
);
1148 B43_WARN_ON(dev
->noisecalc
.channel_at_start
!= dev
->phy
.channel
);
1151 static void b43_calculate_link_quality(struct b43_wldev
*dev
)
1153 /* Top half of Link Quality calculation. */
1155 if (dev
->noisecalc
.calculation_running
)
1157 dev
->noisecalc
.channel_at_start
= dev
->phy
.channel
;
1158 dev
->noisecalc
.calculation_running
= 1;
1159 dev
->noisecalc
.nr_samples
= 0;
1161 b43_generate_noise_sample(dev
);
1164 static void handle_irq_noise(struct b43_wldev
*dev
)
1166 struct b43_phy
*phy
= &dev
->phy
;
1172 /* Bottom half of Link Quality calculation. */
1174 B43_WARN_ON(!dev
->noisecalc
.calculation_running
);
1175 if (dev
->noisecalc
.channel_at_start
!= phy
->channel
)
1176 goto drop_calculation
;
1177 *((__le32
*)noise
) = cpu_to_le32(b43_jssi_read(dev
));
1178 if (noise
[0] == 0x7F || noise
[1] == 0x7F ||
1179 noise
[2] == 0x7F || noise
[3] == 0x7F)
1182 /* Get the noise samples. */
1183 B43_WARN_ON(dev
->noisecalc
.nr_samples
>= 8);
1184 i
= dev
->noisecalc
.nr_samples
;
1185 noise
[0] = clamp_val(noise
[0], 0, ARRAY_SIZE(phy
->nrssi_lt
) - 1);
1186 noise
[1] = clamp_val(noise
[1], 0, ARRAY_SIZE(phy
->nrssi_lt
) - 1);
1187 noise
[2] = clamp_val(noise
[2], 0, ARRAY_SIZE(phy
->nrssi_lt
) - 1);
1188 noise
[3] = clamp_val(noise
[3], 0, ARRAY_SIZE(phy
->nrssi_lt
) - 1);
1189 dev
->noisecalc
.samples
[i
][0] = phy
->nrssi_lt
[noise
[0]];
1190 dev
->noisecalc
.samples
[i
][1] = phy
->nrssi_lt
[noise
[1]];
1191 dev
->noisecalc
.samples
[i
][2] = phy
->nrssi_lt
[noise
[2]];
1192 dev
->noisecalc
.samples
[i
][3] = phy
->nrssi_lt
[noise
[3]];
1193 dev
->noisecalc
.nr_samples
++;
1194 if (dev
->noisecalc
.nr_samples
== 8) {
1195 /* Calculate the Link Quality by the noise samples. */
1197 for (i
= 0; i
< 8; i
++) {
1198 for (j
= 0; j
< 4; j
++)
1199 average
+= dev
->noisecalc
.samples
[i
][j
];
1205 tmp
= b43_shm_read16(dev
, B43_SHM_SHARED
, 0x40C);
1206 tmp
= (tmp
/ 128) & 0x1F;
1216 dev
->stats
.link_noise
= average
;
1218 dev
->noisecalc
.calculation_running
= 0;
1222 b43_generate_noise_sample(dev
);
1225 static void handle_irq_tbtt_indication(struct b43_wldev
*dev
)
1227 if (b43_is_mode(dev
->wl
, IEEE80211_IF_TYPE_AP
)) {
1230 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1231 b43_power_saving_ctl_bits(dev
, 0);
1233 if (b43_is_mode(dev
->wl
, IEEE80211_IF_TYPE_IBSS
))
1237 static void handle_irq_atim_end(struct b43_wldev
*dev
)
1239 if (dev
->dfq_valid
) {
1240 b43_write32(dev
, B43_MMIO_MACCMD
,
1241 b43_read32(dev
, B43_MMIO_MACCMD
)
1242 | B43_MACCMD_DFQ_VALID
);
1247 static void handle_irq_pmq(struct b43_wldev
*dev
)
1254 tmp
= b43_read32(dev
, B43_MMIO_PS_STATUS
);
1255 if (!(tmp
& 0x00000008))
1258 /* 16bit write is odd, but correct. */
1259 b43_write16(dev
, B43_MMIO_PS_STATUS
, 0x0002);
1262 static void b43_write_template_common(struct b43_wldev
*dev
,
1263 const u8
* data
, u16 size
,
1265 u16 shm_size_offset
, u8 rate
)
1268 struct b43_plcp_hdr4 plcp
;
1271 b43_generate_plcp_hdr(&plcp
, size
+ FCS_LEN
, rate
);
1272 b43_ram_write(dev
, ram_offset
, le32_to_cpu(plcp
.data
));
1273 ram_offset
+= sizeof(u32
);
1274 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1275 * So leave the first two bytes of the next write blank.
1277 tmp
= (u32
) (data
[0]) << 16;
1278 tmp
|= (u32
) (data
[1]) << 24;
1279 b43_ram_write(dev
, ram_offset
, tmp
);
1280 ram_offset
+= sizeof(u32
);
1281 for (i
= 2; i
< size
; i
+= sizeof(u32
)) {
1282 tmp
= (u32
) (data
[i
+ 0]);
1284 tmp
|= (u32
) (data
[i
+ 1]) << 8;
1286 tmp
|= (u32
) (data
[i
+ 2]) << 16;
1288 tmp
|= (u32
) (data
[i
+ 3]) << 24;
1289 b43_ram_write(dev
, ram_offset
+ i
- 2, tmp
);
1291 b43_shm_write16(dev
, B43_SHM_SHARED
, shm_size_offset
,
1292 size
+ sizeof(struct b43_plcp_hdr6
));
1295 /* Check if the use of the antenna that ieee80211 told us to
1296 * use is possible. This will fall back to DEFAULT.
1297 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1298 u8
b43_ieee80211_antenna_sanitize(struct b43_wldev
*dev
,
1303 if (antenna_nr
== 0) {
1304 /* Zero means "use default antenna". That's always OK. */
1308 /* Get the mask of available antennas. */
1310 antenna_mask
= dev
->dev
->bus
->sprom
.ant_available_bg
;
1312 antenna_mask
= dev
->dev
->bus
->sprom
.ant_available_a
;
1314 if (!(antenna_mask
& (1 << (antenna_nr
- 1)))) {
1315 /* This antenna is not available. Fall back to default. */
1322 static int b43_antenna_from_ieee80211(struct b43_wldev
*dev
, u8 antenna
)
1324 antenna
= b43_ieee80211_antenna_sanitize(dev
, antenna
);
1326 case 0: /* default/diversity */
1327 return B43_ANTENNA_DEFAULT
;
1328 case 1: /* Antenna 0 */
1329 return B43_ANTENNA0
;
1330 case 2: /* Antenna 1 */
1331 return B43_ANTENNA1
;
1332 case 3: /* Antenna 2 */
1333 return B43_ANTENNA2
;
1334 case 4: /* Antenna 3 */
1335 return B43_ANTENNA3
;
1337 return B43_ANTENNA_DEFAULT
;
1341 /* Convert a b43 antenna number value to the PHY TX control value. */
1342 static u16
b43_antenna_to_phyctl(int antenna
)
1346 return B43_TXH_PHY_ANT0
;
1348 return B43_TXH_PHY_ANT1
;
1350 return B43_TXH_PHY_ANT2
;
1352 return B43_TXH_PHY_ANT3
;
1353 case B43_ANTENNA_AUTO
:
1354 return B43_TXH_PHY_ANT01AUTO
;
1360 static void b43_write_beacon_template(struct b43_wldev
*dev
,
1362 u16 shm_size_offset
)
1364 unsigned int i
, len
, variable_len
;
1365 const struct ieee80211_mgmt
*bcn
;
1371 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(dev
->wl
->current_beacon
);
1373 bcn
= (const struct ieee80211_mgmt
*)(dev
->wl
->current_beacon
->data
);
1374 len
= min((size_t) dev
->wl
->current_beacon
->len
,
1375 0x200 - sizeof(struct b43_plcp_hdr6
));
1376 rate
= ieee80211_get_tx_rate(dev
->wl
->hw
, info
)->hw_value
;
1378 b43_write_template_common(dev
, (const u8
*)bcn
,
1379 len
, ram_offset
, shm_size_offset
, rate
);
1381 /* Write the PHY TX control parameters. */
1382 antenna
= b43_antenna_from_ieee80211(dev
, info
->antenna_sel_tx
);
1383 antenna
= b43_antenna_to_phyctl(antenna
);
1384 ctl
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_BEACPHYCTL
);
1385 /* We can't send beacons with short preamble. Would get PHY errors. */
1386 ctl
&= ~B43_TXH_PHY_SHORTPRMBL
;
1387 ctl
&= ~B43_TXH_PHY_ANT
;
1388 ctl
&= ~B43_TXH_PHY_ENC
;
1390 if (b43_is_cck_rate(rate
))
1391 ctl
|= B43_TXH_PHY_ENC_CCK
;
1393 ctl
|= B43_TXH_PHY_ENC_OFDM
;
1394 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_BEACPHYCTL
, ctl
);
1396 /* Find the position of the TIM and the DTIM_period value
1397 * and write them to SHM. */
1398 ie
= bcn
->u
.beacon
.variable
;
1399 variable_len
= len
- offsetof(struct ieee80211_mgmt
, u
.beacon
.variable
);
1400 for (i
= 0; i
< variable_len
- 2; ) {
1401 uint8_t ie_id
, ie_len
;
1408 /* This is the TIM Information Element */
1410 /* Check whether the ie_len is in the beacon data range. */
1411 if (variable_len
< ie_len
+ 2 + i
)
1413 /* A valid TIM is at least 4 bytes long. */
1418 tim_position
= sizeof(struct b43_plcp_hdr6
);
1419 tim_position
+= offsetof(struct ieee80211_mgmt
, u
.beacon
.variable
);
1422 dtim_period
= ie
[i
+ 3];
1424 b43_shm_write16(dev
, B43_SHM_SHARED
,
1425 B43_SHM_SH_TIMBPOS
, tim_position
);
1426 b43_shm_write16(dev
, B43_SHM_SHARED
,
1427 B43_SHM_SH_DTIMPER
, dtim_period
);
1433 b43warn(dev
->wl
, "Did not find a valid TIM IE in "
1434 "the beacon template packet. AP or IBSS operation "
1435 "may be broken.\n");
1437 b43dbg(dev
->wl
, "Updated beacon template\n");
1440 static void b43_write_probe_resp_plcp(struct b43_wldev
*dev
,
1441 u16 shm_offset
, u16 size
,
1442 struct ieee80211_rate
*rate
)
1444 struct b43_plcp_hdr4 plcp
;
1449 b43_generate_plcp_hdr(&plcp
, size
+ FCS_LEN
, rate
->hw_value
);
1450 dur
= ieee80211_generic_frame_duration(dev
->wl
->hw
,
1453 /* Write PLCP in two parts and timing for packet transfer */
1454 tmp
= le32_to_cpu(plcp
.data
);
1455 b43_shm_write16(dev
, B43_SHM_SHARED
, shm_offset
, tmp
& 0xFFFF);
1456 b43_shm_write16(dev
, B43_SHM_SHARED
, shm_offset
+ 2, tmp
>> 16);
1457 b43_shm_write16(dev
, B43_SHM_SHARED
, shm_offset
+ 6, le16_to_cpu(dur
));
1460 /* Instead of using custom probe response template, this function
1461 * just patches custom beacon template by:
1462 * 1) Changing packet type
1463 * 2) Patching duration field
1466 static const u8
* b43_generate_probe_resp(struct b43_wldev
*dev
,
1468 struct ieee80211_rate
*rate
)
1472 u16 src_size
, elem_size
, src_pos
, dest_pos
;
1474 struct ieee80211_hdr
*hdr
;
1477 src_size
= dev
->wl
->current_beacon
->len
;
1478 src_data
= (const u8
*)dev
->wl
->current_beacon
->data
;
1480 /* Get the start offset of the variable IEs in the packet. */
1481 ie_start
= offsetof(struct ieee80211_mgmt
, u
.probe_resp
.variable
);
1482 B43_WARN_ON(ie_start
!= offsetof(struct ieee80211_mgmt
, u
.beacon
.variable
));
1484 if (B43_WARN_ON(src_size
< ie_start
))
1487 dest_data
= kmalloc(src_size
, GFP_ATOMIC
);
1488 if (unlikely(!dest_data
))
1491 /* Copy the static data and all Information Elements, except the TIM. */
1492 memcpy(dest_data
, src_data
, ie_start
);
1494 dest_pos
= ie_start
;
1495 for ( ; src_pos
< src_size
- 2; src_pos
+= elem_size
) {
1496 elem_size
= src_data
[src_pos
+ 1] + 2;
1497 if (src_data
[src_pos
] == 5) {
1498 /* This is the TIM. */
1501 memcpy(dest_data
+ dest_pos
, src_data
+ src_pos
,
1503 dest_pos
+= elem_size
;
1505 *dest_size
= dest_pos
;
1506 hdr
= (struct ieee80211_hdr
*)dest_data
;
1508 /* Set the frame control. */
1509 hdr
->frame_control
= cpu_to_le16(IEEE80211_FTYPE_MGMT
|
1510 IEEE80211_STYPE_PROBE_RESP
);
1511 dur
= ieee80211_generic_frame_duration(dev
->wl
->hw
,
1512 dev
->wl
->vif
, *dest_size
,
1514 hdr
->duration_id
= dur
;
1519 static void b43_write_probe_resp_template(struct b43_wldev
*dev
,
1521 u16 shm_size_offset
,
1522 struct ieee80211_rate
*rate
)
1524 const u8
*probe_resp_data
;
1527 size
= dev
->wl
->current_beacon
->len
;
1528 probe_resp_data
= b43_generate_probe_resp(dev
, &size
, rate
);
1529 if (unlikely(!probe_resp_data
))
1532 /* Looks like PLCP headers plus packet timings are stored for
1533 * all possible basic rates
1535 b43_write_probe_resp_plcp(dev
, 0x31A, size
, &b43_b_ratetable
[0]);
1536 b43_write_probe_resp_plcp(dev
, 0x32C, size
, &b43_b_ratetable
[1]);
1537 b43_write_probe_resp_plcp(dev
, 0x33E, size
, &b43_b_ratetable
[2]);
1538 b43_write_probe_resp_plcp(dev
, 0x350, size
, &b43_b_ratetable
[3]);
1540 size
= min((size_t) size
, 0x200 - sizeof(struct b43_plcp_hdr6
));
1541 b43_write_template_common(dev
, probe_resp_data
,
1542 size
, ram_offset
, shm_size_offset
,
1544 kfree(probe_resp_data
);
1547 static void handle_irq_beacon(struct b43_wldev
*dev
)
1549 struct b43_wl
*wl
= dev
->wl
;
1550 u32 cmd
, beacon0_valid
, beacon1_valid
;
1552 if (!b43_is_mode(wl
, IEEE80211_IF_TYPE_AP
))
1555 /* This is the bottom half of the asynchronous beacon update. */
1557 /* Ignore interrupt in the future. */
1558 dev
->irq_savedstate
&= ~B43_IRQ_BEACON
;
1560 cmd
= b43_read32(dev
, B43_MMIO_MACCMD
);
1561 beacon0_valid
= (cmd
& B43_MACCMD_BEACON0_VALID
);
1562 beacon1_valid
= (cmd
& B43_MACCMD_BEACON1_VALID
);
1564 /* Schedule interrupt manually, if busy. */
1565 if (beacon0_valid
&& beacon1_valid
) {
1566 b43_write32(dev
, B43_MMIO_GEN_IRQ_REASON
, B43_IRQ_BEACON
);
1567 dev
->irq_savedstate
|= B43_IRQ_BEACON
;
1571 if (!beacon0_valid
) {
1572 if (!wl
->beacon0_uploaded
) {
1573 b43_write_beacon_template(dev
, 0x68, 0x18);
1574 b43_write_probe_resp_template(dev
, 0x268, 0x4A,
1575 &__b43_ratetable
[3]);
1576 wl
->beacon0_uploaded
= 1;
1578 cmd
= b43_read32(dev
, B43_MMIO_MACCMD
);
1579 cmd
|= B43_MACCMD_BEACON0_VALID
;
1580 b43_write32(dev
, B43_MMIO_MACCMD
, cmd
);
1581 } else if (!beacon1_valid
) {
1582 if (!wl
->beacon1_uploaded
) {
1583 b43_write_beacon_template(dev
, 0x468, 0x1A);
1584 wl
->beacon1_uploaded
= 1;
1586 cmd
= b43_read32(dev
, B43_MMIO_MACCMD
);
1587 cmd
|= B43_MACCMD_BEACON1_VALID
;
1588 b43_write32(dev
, B43_MMIO_MACCMD
, cmd
);
1592 static void b43_beacon_update_trigger_work(struct work_struct
*work
)
1594 struct b43_wl
*wl
= container_of(work
, struct b43_wl
,
1595 beacon_update_trigger
);
1596 struct b43_wldev
*dev
;
1598 mutex_lock(&wl
->mutex
);
1599 dev
= wl
->current_dev
;
1600 if (likely(dev
&& (b43_status(dev
) >= B43_STAT_INITIALIZED
))) {
1601 spin_lock_irq(&wl
->irq_lock
);
1602 /* update beacon right away or defer to irq */
1603 dev
->irq_savedstate
= b43_read32(dev
, B43_MMIO_GEN_IRQ_MASK
);
1604 handle_irq_beacon(dev
);
1605 /* The handler might have updated the IRQ mask. */
1606 b43_write32(dev
, B43_MMIO_GEN_IRQ_MASK
,
1607 dev
->irq_savedstate
);
1609 spin_unlock_irq(&wl
->irq_lock
);
1611 mutex_unlock(&wl
->mutex
);
1614 /* Asynchronously update the packet templates in template RAM.
1615 * Locking: Requires wl->irq_lock to be locked. */
1616 static void b43_update_templates(struct b43_wl
*wl
, struct sk_buff
*beacon
)
1618 /* This is the top half of the ansynchronous beacon update.
1619 * The bottom half is the beacon IRQ.
1620 * Beacon update must be asynchronous to avoid sending an
1621 * invalid beacon. This can happen for example, if the firmware
1622 * transmits a beacon while we are updating it. */
1624 if (wl
->current_beacon
)
1625 dev_kfree_skb_any(wl
->current_beacon
);
1626 wl
->current_beacon
= beacon
;
1627 wl
->beacon0_uploaded
= 0;
1628 wl
->beacon1_uploaded
= 0;
1629 queue_work(wl
->hw
->workqueue
, &wl
->beacon_update_trigger
);
1632 static void b43_set_ssid(struct b43_wldev
*dev
, const u8
* ssid
, u8 ssid_len
)
1637 len
= min((u16
) ssid_len
, (u16
) 0x100);
1638 for (i
= 0; i
< len
; i
+= sizeof(u32
)) {
1639 tmp
= (u32
) (ssid
[i
+ 0]);
1641 tmp
|= (u32
) (ssid
[i
+ 1]) << 8;
1643 tmp
|= (u32
) (ssid
[i
+ 2]) << 16;
1645 tmp
|= (u32
) (ssid
[i
+ 3]) << 24;
1646 b43_shm_write32(dev
, B43_SHM_SHARED
, 0x380 + i
, tmp
);
1648 b43_shm_write16(dev
, B43_SHM_SHARED
, 0x48, len
);
1651 static void b43_set_beacon_int(struct b43_wldev
*dev
, u16 beacon_int
)
1654 if (dev
->dev
->id
.revision
>= 3) {
1655 b43_write32(dev
, B43_MMIO_TSF_CFP_REP
, (beacon_int
<< 16));
1656 b43_write32(dev
, B43_MMIO_TSF_CFP_START
, (beacon_int
<< 10));
1658 b43_write16(dev
, 0x606, (beacon_int
>> 6));
1659 b43_write16(dev
, 0x610, beacon_int
);
1661 b43_time_unlock(dev
);
1662 b43dbg(dev
->wl
, "Set beacon interval to %u\n", beacon_int
);
1665 static void handle_irq_ucode_debug(struct b43_wldev
*dev
)
1667 unsigned int i
, cnt
;
1671 /* The proprietary firmware doesn't have this IRQ. */
1672 if (!dev
->fw
.opensource
)
1675 /* Microcode register 63 contains the debug-IRQ reason. */
1676 reason
= b43_shm_read16(dev
, B43_SHM_SCRATCH
, 63);
1678 case B43_DEBUGIRQ_PANIC
:
1679 /* The reason for the panic is in register 3. */
1680 reason
= b43_shm_read16(dev
, B43_SHM_SCRATCH
, 3);
1681 b43err(dev
->wl
, "Whoopsy, the microcode panic'ed! Reason: %u\n",
1683 b43_controller_restart(dev
, "Microcode panic");
1685 case B43_DEBUGIRQ_DUMP_SHM
:
1687 break; /* Only with driver debugging enabled. */
1688 buf
= kmalloc(4096, GFP_ATOMIC
);
1690 b43dbg(dev
->wl
, "SHM-dump: Failed to allocate memory\n");
1693 for (i
= 0; i
< 4096; i
+= 2) {
1694 u16 tmp
= b43_shm_read16(dev
, B43_SHM_SHARED
, i
);
1695 buf
[i
/ 2] = cpu_to_le16(tmp
);
1697 b43info(dev
->wl
, "Shared memory dump:\n");
1698 print_hex_dump(KERN_INFO
, "", DUMP_PREFIX_OFFSET
,
1699 16, 2, buf
, 4096, 1);
1702 case B43_DEBUGIRQ_DUMP_REGS
:
1704 break; /* Only with driver debugging enabled. */
1705 b43info(dev
->wl
, "Microcode register dump:\n");
1706 for (i
= 0, cnt
= 0; i
< 64; i
++) {
1707 u16 tmp
= b43_shm_read16(dev
, B43_SHM_SCRATCH
, i
);
1710 printk("r%02u: 0x%04X ", i
, tmp
);
1720 b43dbg(dev
->wl
, "Debug-IRQ triggered for unknown reason: %u\n",
1724 b43_shm_write16(dev
, B43_SHM_SCRATCH
, 63, B43_DEBUGIRQ_ACK
);
1727 /* Interrupt handler bottom-half */
1728 static void b43_interrupt_tasklet(struct b43_wldev
*dev
)
1731 u32 dma_reason
[ARRAY_SIZE(dev
->dma_reason
)];
1732 u32 merged_dma_reason
= 0;
1734 unsigned long flags
;
1736 spin_lock_irqsave(&dev
->wl
->irq_lock
, flags
);
1738 B43_WARN_ON(b43_status(dev
) != B43_STAT_STARTED
);
1740 reason
= dev
->irq_reason
;
1741 for (i
= 0; i
< ARRAY_SIZE(dma_reason
); i
++) {
1742 dma_reason
[i
] = dev
->dma_reason
[i
];
1743 merged_dma_reason
|= dma_reason
[i
];
1746 if (unlikely(reason
& B43_IRQ_MAC_TXERR
))
1747 b43err(dev
->wl
, "MAC transmission error\n");
1749 if (unlikely(reason
& B43_IRQ_PHY_TXERR
)) {
1750 b43err(dev
->wl
, "PHY transmission error\n");
1752 if (unlikely(atomic_dec_and_test(&dev
->phy
.txerr_cnt
))) {
1753 atomic_set(&dev
->phy
.txerr_cnt
,
1754 B43_PHY_TX_BADNESS_LIMIT
);
1755 b43err(dev
->wl
, "Too many PHY TX errors, "
1756 "restarting the controller\n");
1757 b43_controller_restart(dev
, "PHY TX errors");
1761 if (unlikely(merged_dma_reason
& (B43_DMAIRQ_FATALMASK
|
1762 B43_DMAIRQ_NONFATALMASK
))) {
1763 if (merged_dma_reason
& B43_DMAIRQ_FATALMASK
) {
1764 b43err(dev
->wl
, "Fatal DMA error: "
1765 "0x%08X, 0x%08X, 0x%08X, "
1766 "0x%08X, 0x%08X, 0x%08X\n",
1767 dma_reason
[0], dma_reason
[1],
1768 dma_reason
[2], dma_reason
[3],
1769 dma_reason
[4], dma_reason
[5]);
1770 b43_controller_restart(dev
, "DMA error");
1772 spin_unlock_irqrestore(&dev
->wl
->irq_lock
, flags
);
1775 if (merged_dma_reason
& B43_DMAIRQ_NONFATALMASK
) {
1776 b43err(dev
->wl
, "DMA error: "
1777 "0x%08X, 0x%08X, 0x%08X, "
1778 "0x%08X, 0x%08X, 0x%08X\n",
1779 dma_reason
[0], dma_reason
[1],
1780 dma_reason
[2], dma_reason
[3],
1781 dma_reason
[4], dma_reason
[5]);
1785 if (unlikely(reason
& B43_IRQ_UCODE_DEBUG
))
1786 handle_irq_ucode_debug(dev
);
1787 if (reason
& B43_IRQ_TBTT_INDI
)
1788 handle_irq_tbtt_indication(dev
);
1789 if (reason
& B43_IRQ_ATIM_END
)
1790 handle_irq_atim_end(dev
);
1791 if (reason
& B43_IRQ_BEACON
)
1792 handle_irq_beacon(dev
);
1793 if (reason
& B43_IRQ_PMQ
)
1794 handle_irq_pmq(dev
);
1795 if (reason
& B43_IRQ_TXFIFO_FLUSH_OK
)
1797 if (reason
& B43_IRQ_NOISESAMPLE_OK
)
1798 handle_irq_noise(dev
);
1800 /* Check the DMA reason registers for received data. */
1801 if (dma_reason
[0] & B43_DMAIRQ_RX_DONE
) {
1802 if (b43_using_pio_transfers(dev
))
1803 b43_pio_rx(dev
->pio
.rx_queue
);
1805 b43_dma_rx(dev
->dma
.rx_ring
);
1807 B43_WARN_ON(dma_reason
[1] & B43_DMAIRQ_RX_DONE
);
1808 B43_WARN_ON(dma_reason
[2] & B43_DMAIRQ_RX_DONE
);
1809 B43_WARN_ON(dma_reason
[3] & B43_DMAIRQ_RX_DONE
);
1810 B43_WARN_ON(dma_reason
[4] & B43_DMAIRQ_RX_DONE
);
1811 B43_WARN_ON(dma_reason
[5] & B43_DMAIRQ_RX_DONE
);
1813 if (reason
& B43_IRQ_TX_OK
)
1814 handle_irq_transmit_status(dev
);
1816 b43_interrupt_enable(dev
, dev
->irq_savedstate
);
1818 spin_unlock_irqrestore(&dev
->wl
->irq_lock
, flags
);
1821 static void b43_interrupt_ack(struct b43_wldev
*dev
, u32 reason
)
1823 b43_write32(dev
, B43_MMIO_GEN_IRQ_REASON
, reason
);
1825 b43_write32(dev
, B43_MMIO_DMA0_REASON
, dev
->dma_reason
[0]);
1826 b43_write32(dev
, B43_MMIO_DMA1_REASON
, dev
->dma_reason
[1]);
1827 b43_write32(dev
, B43_MMIO_DMA2_REASON
, dev
->dma_reason
[2]);
1828 b43_write32(dev
, B43_MMIO_DMA3_REASON
, dev
->dma_reason
[3]);
1829 b43_write32(dev
, B43_MMIO_DMA4_REASON
, dev
->dma_reason
[4]);
1830 b43_write32(dev
, B43_MMIO_DMA5_REASON
, dev
->dma_reason
[5]);
1833 /* Interrupt handler top-half */
1834 static irqreturn_t
b43_interrupt_handler(int irq
, void *dev_id
)
1836 irqreturn_t ret
= IRQ_NONE
;
1837 struct b43_wldev
*dev
= dev_id
;
1843 spin_lock(&dev
->wl
->irq_lock
);
1845 if (b43_status(dev
) < B43_STAT_STARTED
)
1847 reason
= b43_read32(dev
, B43_MMIO_GEN_IRQ_REASON
);
1848 if (reason
== 0xffffffff) /* shared IRQ */
1851 reason
&= b43_read32(dev
, B43_MMIO_GEN_IRQ_MASK
);
1855 dev
->dma_reason
[0] = b43_read32(dev
, B43_MMIO_DMA0_REASON
)
1857 dev
->dma_reason
[1] = b43_read32(dev
, B43_MMIO_DMA1_REASON
)
1859 dev
->dma_reason
[2] = b43_read32(dev
, B43_MMIO_DMA2_REASON
)
1861 dev
->dma_reason
[3] = b43_read32(dev
, B43_MMIO_DMA3_REASON
)
1863 dev
->dma_reason
[4] = b43_read32(dev
, B43_MMIO_DMA4_REASON
)
1865 dev
->dma_reason
[5] = b43_read32(dev
, B43_MMIO_DMA5_REASON
)
1868 b43_interrupt_ack(dev
, reason
);
1869 /* disable all IRQs. They are enabled again in the bottom half. */
1870 dev
->irq_savedstate
= b43_interrupt_disable(dev
, B43_IRQ_ALL
);
1871 /* save the reason code and call our bottom half. */
1872 dev
->irq_reason
= reason
;
1873 tasklet_schedule(&dev
->isr_tasklet
);
1876 spin_unlock(&dev
->wl
->irq_lock
);
1881 static void do_release_fw(struct b43_firmware_file
*fw
)
1883 release_firmware(fw
->data
);
1885 fw
->filename
= NULL
;
1888 static void b43_release_firmware(struct b43_wldev
*dev
)
1890 do_release_fw(&dev
->fw
.ucode
);
1891 do_release_fw(&dev
->fw
.pcm
);
1892 do_release_fw(&dev
->fw
.initvals
);
1893 do_release_fw(&dev
->fw
.initvals_band
);
1896 static void b43_print_fw_helptext(struct b43_wl
*wl
, bool error
)
1900 text
= "You must go to "
1901 "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware "
1902 "and download the latest firmware (version 4).\n";
1909 static int do_request_fw(struct b43_wldev
*dev
,
1911 struct b43_firmware_file
*fw
)
1913 char path
[sizeof(modparam_fwpostfix
) + 32];
1914 const struct firmware
*blob
;
1915 struct b43_fw_header
*hdr
;
1920 /* Don't fetch anything. Free possibly cached firmware. */
1925 if (strcmp(fw
->filename
, name
) == 0)
1926 return 0; /* Already have this fw. */
1927 /* Free the cached firmware first. */
1931 snprintf(path
, ARRAY_SIZE(path
),
1933 modparam_fwpostfix
, name
);
1934 err
= request_firmware(&blob
, path
, dev
->dev
->dev
);
1936 b43err(dev
->wl
, "Firmware file \"%s\" not found "
1937 "or load failed.\n", path
);
1940 if (blob
->size
< sizeof(struct b43_fw_header
))
1942 hdr
= (struct b43_fw_header
*)(blob
->data
);
1943 switch (hdr
->type
) {
1944 case B43_FW_TYPE_UCODE
:
1945 case B43_FW_TYPE_PCM
:
1946 size
= be32_to_cpu(hdr
->size
);
1947 if (size
!= blob
->size
- sizeof(struct b43_fw_header
))
1950 case B43_FW_TYPE_IV
:
1959 fw
->filename
= name
;
1964 b43err(dev
->wl
, "Firmware file \"%s\" format error.\n", path
);
1965 release_firmware(blob
);
1970 static int b43_request_firmware(struct b43_wldev
*dev
)
1972 struct b43_firmware
*fw
= &dev
->fw
;
1973 const u8 rev
= dev
->dev
->id
.revision
;
1974 const char *filename
;
1979 tmshigh
= ssb_read32(dev
->dev
, SSB_TMSHIGH
);
1980 if ((rev
>= 5) && (rev
<= 10))
1981 filename
= "ucode5";
1982 else if ((rev
>= 11) && (rev
<= 12))
1983 filename
= "ucode11";
1985 filename
= "ucode13";
1988 err
= do_request_fw(dev
, filename
, &fw
->ucode
);
1993 if ((rev
>= 5) && (rev
<= 10))
1999 err
= do_request_fw(dev
, filename
, &fw
->pcm
);
2004 switch (dev
->phy
.type
) {
2006 if ((rev
>= 5) && (rev
<= 10)) {
2007 if (tmshigh
& B43_TMSHIGH_HAVE_2GHZ_PHY
)
2008 filename
= "a0g1initvals5";
2010 filename
= "a0g0initvals5";
2012 goto err_no_initvals
;
2015 if ((rev
>= 5) && (rev
<= 10))
2016 filename
= "b0g0initvals5";
2018 filename
= "b0g0initvals13";
2020 goto err_no_initvals
;
2023 if ((rev
>= 11) && (rev
<= 12))
2024 filename
= "n0initvals11";
2026 goto err_no_initvals
;
2029 goto err_no_initvals
;
2031 err
= do_request_fw(dev
, filename
, &fw
->initvals
);
2035 /* Get bandswitch initvals */
2036 switch (dev
->phy
.type
) {
2038 if ((rev
>= 5) && (rev
<= 10)) {
2039 if (tmshigh
& B43_TMSHIGH_HAVE_2GHZ_PHY
)
2040 filename
= "a0g1bsinitvals5";
2042 filename
= "a0g0bsinitvals5";
2043 } else if (rev
>= 11)
2046 goto err_no_initvals
;
2049 if ((rev
>= 5) && (rev
<= 10))
2050 filename
= "b0g0bsinitvals5";
2054 goto err_no_initvals
;
2057 if ((rev
>= 11) && (rev
<= 12))
2058 filename
= "n0bsinitvals11";
2060 goto err_no_initvals
;
2063 goto err_no_initvals
;
2065 err
= do_request_fw(dev
, filename
, &fw
->initvals_band
);
2072 b43_print_fw_helptext(dev
->wl
, 1);
2077 b43err(dev
->wl
, "No microcode available for core rev %u\n", rev
);
2082 b43err(dev
->wl
, "No PCM available for core rev %u\n", rev
);
2087 b43err(dev
->wl
, "No Initial Values firmware file for PHY %u, "
2088 "core rev %u\n", dev
->phy
.type
, rev
);
2092 b43_release_firmware(dev
);
2096 static int b43_upload_microcode(struct b43_wldev
*dev
)
2098 const size_t hdr_len
= sizeof(struct b43_fw_header
);
2100 unsigned int i
, len
;
2101 u16 fwrev
, fwpatch
, fwdate
, fwtime
;
2105 /* Jump the microcode PSM to offset 0 */
2106 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
2107 B43_WARN_ON(macctl
& B43_MACCTL_PSM_RUN
);
2108 macctl
|= B43_MACCTL_PSM_JMP0
;
2109 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
2110 /* Zero out all microcode PSM registers and shared memory. */
2111 for (i
= 0; i
< 64; i
++)
2112 b43_shm_write16(dev
, B43_SHM_SCRATCH
, i
, 0);
2113 for (i
= 0; i
< 4096; i
+= 2)
2114 b43_shm_write16(dev
, B43_SHM_SHARED
, i
, 0);
2116 /* Upload Microcode. */
2117 data
= (__be32
*) (dev
->fw
.ucode
.data
->data
+ hdr_len
);
2118 len
= (dev
->fw
.ucode
.data
->size
- hdr_len
) / sizeof(__be32
);
2119 b43_shm_control_word(dev
, B43_SHM_UCODE
| B43_SHM_AUTOINC_W
, 0x0000);
2120 for (i
= 0; i
< len
; i
++) {
2121 b43_write32(dev
, B43_MMIO_SHM_DATA
, be32_to_cpu(data
[i
]));
2125 if (dev
->fw
.pcm
.data
) {
2126 /* Upload PCM data. */
2127 data
= (__be32
*) (dev
->fw
.pcm
.data
->data
+ hdr_len
);
2128 len
= (dev
->fw
.pcm
.data
->size
- hdr_len
) / sizeof(__be32
);
2129 b43_shm_control_word(dev
, B43_SHM_HW
, 0x01EA);
2130 b43_write32(dev
, B43_MMIO_SHM_DATA
, 0x00004000);
2131 /* No need for autoinc bit in SHM_HW */
2132 b43_shm_control_word(dev
, B43_SHM_HW
, 0x01EB);
2133 for (i
= 0; i
< len
; i
++) {
2134 b43_write32(dev
, B43_MMIO_SHM_DATA
, be32_to_cpu(data
[i
]));
2139 b43_write32(dev
, B43_MMIO_GEN_IRQ_REASON
, B43_IRQ_ALL
);
2141 /* Start the microcode PSM */
2142 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
2143 macctl
&= ~B43_MACCTL_PSM_JMP0
;
2144 macctl
|= B43_MACCTL_PSM_RUN
;
2145 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
2147 /* Wait for the microcode to load and respond */
2150 tmp
= b43_read32(dev
, B43_MMIO_GEN_IRQ_REASON
);
2151 if (tmp
== B43_IRQ_MAC_SUSPENDED
)
2155 b43err(dev
->wl
, "Microcode not responding\n");
2156 b43_print_fw_helptext(dev
->wl
, 1);
2160 msleep_interruptible(50);
2161 if (signal_pending(current
)) {
2166 b43_read32(dev
, B43_MMIO_GEN_IRQ_REASON
); /* dummy read */
2168 /* Get and check the revisions. */
2169 fwrev
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_UCODEREV
);
2170 fwpatch
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_UCODEPATCH
);
2171 fwdate
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_UCODEDATE
);
2172 fwtime
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_UCODETIME
);
2174 if (fwrev
<= 0x128) {
2175 b43err(dev
->wl
, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2176 "binary drivers older than version 4.x is unsupported. "
2177 "You must upgrade your firmware files.\n");
2178 b43_print_fw_helptext(dev
->wl
, 1);
2182 dev
->fw
.rev
= fwrev
;
2183 dev
->fw
.patch
= fwpatch
;
2184 dev
->fw
.opensource
= (fwdate
== 0xFFFF);
2186 if (dev
->fw
.opensource
) {
2187 /* Patchlevel info is encoded in the "time" field. */
2188 dev
->fw
.patch
= fwtime
;
2189 b43info(dev
->wl
, "Loading OpenSource firmware version %u.%u\n",
2190 dev
->fw
.rev
, dev
->fw
.patch
);
2192 b43info(dev
->wl
, "Loading firmware version %u.%u "
2193 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2195 (fwdate
>> 12) & 0xF, (fwdate
>> 8) & 0xF, fwdate
& 0xFF,
2196 (fwtime
>> 11) & 0x1F, (fwtime
>> 5) & 0x3F, fwtime
& 0x1F);
2199 if (b43_is_old_txhdr_format(dev
)) {
2200 b43warn(dev
->wl
, "You are using an old firmware image. "
2201 "Support for old firmware will be removed in July 2008.\n");
2202 b43_print_fw_helptext(dev
->wl
, 0);
2208 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
2209 macctl
&= ~B43_MACCTL_PSM_RUN
;
2210 macctl
|= B43_MACCTL_PSM_JMP0
;
2211 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
2216 static int b43_write_initvals(struct b43_wldev
*dev
,
2217 const struct b43_iv
*ivals
,
2221 const struct b43_iv
*iv
;
2226 BUILD_BUG_ON(sizeof(struct b43_iv
) != 6);
2228 for (i
= 0; i
< count
; i
++) {
2229 if (array_size
< sizeof(iv
->offset_size
))
2231 array_size
-= sizeof(iv
->offset_size
);
2232 offset
= be16_to_cpu(iv
->offset_size
);
2233 bit32
= !!(offset
& B43_IV_32BIT
);
2234 offset
&= B43_IV_OFFSET_MASK
;
2235 if (offset
>= 0x1000)
2240 if (array_size
< sizeof(iv
->data
.d32
))
2242 array_size
-= sizeof(iv
->data
.d32
);
2244 value
= get_unaligned_be32(&iv
->data
.d32
);
2245 b43_write32(dev
, offset
, value
);
2247 iv
= (const struct b43_iv
*)((const uint8_t *)iv
+
2253 if (array_size
< sizeof(iv
->data
.d16
))
2255 array_size
-= sizeof(iv
->data
.d16
);
2257 value
= be16_to_cpu(iv
->data
.d16
);
2258 b43_write16(dev
, offset
, value
);
2260 iv
= (const struct b43_iv
*)((const uint8_t *)iv
+
2271 b43err(dev
->wl
, "Initial Values Firmware file-format error.\n");
2272 b43_print_fw_helptext(dev
->wl
, 1);
2277 static int b43_upload_initvals(struct b43_wldev
*dev
)
2279 const size_t hdr_len
= sizeof(struct b43_fw_header
);
2280 const struct b43_fw_header
*hdr
;
2281 struct b43_firmware
*fw
= &dev
->fw
;
2282 const struct b43_iv
*ivals
;
2286 hdr
= (const struct b43_fw_header
*)(fw
->initvals
.data
->data
);
2287 ivals
= (const struct b43_iv
*)(fw
->initvals
.data
->data
+ hdr_len
);
2288 count
= be32_to_cpu(hdr
->size
);
2289 err
= b43_write_initvals(dev
, ivals
, count
,
2290 fw
->initvals
.data
->size
- hdr_len
);
2293 if (fw
->initvals_band
.data
) {
2294 hdr
= (const struct b43_fw_header
*)(fw
->initvals_band
.data
->data
);
2295 ivals
= (const struct b43_iv
*)(fw
->initvals_band
.data
->data
+ hdr_len
);
2296 count
= be32_to_cpu(hdr
->size
);
2297 err
= b43_write_initvals(dev
, ivals
, count
,
2298 fw
->initvals_band
.data
->size
- hdr_len
);
2307 /* Initialize the GPIOs
2308 * http://bcm-specs.sipsolutions.net/GPIO
2310 static int b43_gpio_init(struct b43_wldev
*dev
)
2312 struct ssb_bus
*bus
= dev
->dev
->bus
;
2313 struct ssb_device
*gpiodev
, *pcidev
= NULL
;
2316 b43_write32(dev
, B43_MMIO_MACCTL
, b43_read32(dev
, B43_MMIO_MACCTL
)
2317 & ~B43_MACCTL_GPOUTSMSK
);
2319 b43_write16(dev
, B43_MMIO_GPIO_MASK
, b43_read16(dev
, B43_MMIO_GPIO_MASK
)
2324 if (dev
->dev
->bus
->chip_id
== 0x4301) {
2328 if (0 /* FIXME: conditional unknown */ ) {
2329 b43_write16(dev
, B43_MMIO_GPIO_MASK
,
2330 b43_read16(dev
, B43_MMIO_GPIO_MASK
)
2335 if (dev
->dev
->bus
->sprom
.boardflags_lo
& B43_BFL_PACTRL
) {
2336 b43_write16(dev
, B43_MMIO_GPIO_MASK
,
2337 b43_read16(dev
, B43_MMIO_GPIO_MASK
)
2342 if (dev
->dev
->id
.revision
>= 2)
2343 mask
|= 0x0010; /* FIXME: This is redundant. */
2345 #ifdef CONFIG_SSB_DRIVER_PCICORE
2346 pcidev
= bus
->pcicore
.dev
;
2348 gpiodev
= bus
->chipco
.dev
? : pcidev
;
2351 ssb_write32(gpiodev
, B43_GPIO_CONTROL
,
2352 (ssb_read32(gpiodev
, B43_GPIO_CONTROL
)
2358 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2359 static void b43_gpio_cleanup(struct b43_wldev
*dev
)
2361 struct ssb_bus
*bus
= dev
->dev
->bus
;
2362 struct ssb_device
*gpiodev
, *pcidev
= NULL
;
2364 #ifdef CONFIG_SSB_DRIVER_PCICORE
2365 pcidev
= bus
->pcicore
.dev
;
2367 gpiodev
= bus
->chipco
.dev
? : pcidev
;
2370 ssb_write32(gpiodev
, B43_GPIO_CONTROL
, 0);
2373 /* http://bcm-specs.sipsolutions.net/EnableMac */
2374 void b43_mac_enable(struct b43_wldev
*dev
)
2376 dev
->mac_suspended
--;
2377 B43_WARN_ON(dev
->mac_suspended
< 0);
2378 if (dev
->mac_suspended
== 0) {
2379 b43_write32(dev
, B43_MMIO_MACCTL
,
2380 b43_read32(dev
, B43_MMIO_MACCTL
)
2381 | B43_MACCTL_ENABLED
);
2382 b43_write32(dev
, B43_MMIO_GEN_IRQ_REASON
,
2383 B43_IRQ_MAC_SUSPENDED
);
2385 b43_read32(dev
, B43_MMIO_MACCTL
);
2386 b43_read32(dev
, B43_MMIO_GEN_IRQ_REASON
);
2387 b43_power_saving_ctl_bits(dev
, 0);
2391 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2392 void b43_mac_suspend(struct b43_wldev
*dev
)
2398 B43_WARN_ON(dev
->mac_suspended
< 0);
2400 if (dev
->mac_suspended
== 0) {
2401 b43_power_saving_ctl_bits(dev
, B43_PS_AWAKE
);
2402 b43_write32(dev
, B43_MMIO_MACCTL
,
2403 b43_read32(dev
, B43_MMIO_MACCTL
)
2404 & ~B43_MACCTL_ENABLED
);
2405 /* force pci to flush the write */
2406 b43_read32(dev
, B43_MMIO_MACCTL
);
2407 for (i
= 35; i
; i
--) {
2408 tmp
= b43_read32(dev
, B43_MMIO_GEN_IRQ_REASON
);
2409 if (tmp
& B43_IRQ_MAC_SUSPENDED
)
2413 /* Hm, it seems this will take some time. Use msleep(). */
2414 for (i
= 40; i
; i
--) {
2415 tmp
= b43_read32(dev
, B43_MMIO_GEN_IRQ_REASON
);
2416 if (tmp
& B43_IRQ_MAC_SUSPENDED
)
2420 b43err(dev
->wl
, "MAC suspend failed\n");
2423 dev
->mac_suspended
++;
2426 static void b43_adjust_opmode(struct b43_wldev
*dev
)
2428 struct b43_wl
*wl
= dev
->wl
;
2432 ctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
2433 /* Reset status to STA infrastructure mode. */
2434 ctl
&= ~B43_MACCTL_AP
;
2435 ctl
&= ~B43_MACCTL_KEEP_CTL
;
2436 ctl
&= ~B43_MACCTL_KEEP_BADPLCP
;
2437 ctl
&= ~B43_MACCTL_KEEP_BAD
;
2438 ctl
&= ~B43_MACCTL_PROMISC
;
2439 ctl
&= ~B43_MACCTL_BEACPROMISC
;
2440 ctl
|= B43_MACCTL_INFRA
;
2442 if (b43_is_mode(wl
, IEEE80211_IF_TYPE_AP
))
2443 ctl
|= B43_MACCTL_AP
;
2444 else if (b43_is_mode(wl
, IEEE80211_IF_TYPE_IBSS
))
2445 ctl
&= ~B43_MACCTL_INFRA
;
2447 if (wl
->filter_flags
& FIF_CONTROL
)
2448 ctl
|= B43_MACCTL_KEEP_CTL
;
2449 if (wl
->filter_flags
& FIF_FCSFAIL
)
2450 ctl
|= B43_MACCTL_KEEP_BAD
;
2451 if (wl
->filter_flags
& FIF_PLCPFAIL
)
2452 ctl
|= B43_MACCTL_KEEP_BADPLCP
;
2453 if (wl
->filter_flags
& FIF_PROMISC_IN_BSS
)
2454 ctl
|= B43_MACCTL_PROMISC
;
2455 if (wl
->filter_flags
& FIF_BCN_PRBRESP_PROMISC
)
2456 ctl
|= B43_MACCTL_BEACPROMISC
;
2458 /* Workaround: On old hardware the HW-MAC-address-filter
2459 * doesn't work properly, so always run promisc in filter
2460 * it in software. */
2461 if (dev
->dev
->id
.revision
<= 4)
2462 ctl
|= B43_MACCTL_PROMISC
;
2464 b43_write32(dev
, B43_MMIO_MACCTL
, ctl
);
2467 if ((ctl
& B43_MACCTL_INFRA
) && !(ctl
& B43_MACCTL_AP
)) {
2468 if (dev
->dev
->bus
->chip_id
== 0x4306 &&
2469 dev
->dev
->bus
->chip_rev
== 3)
2474 b43_write16(dev
, 0x612, cfp_pretbtt
);
2477 static void b43_rate_memory_write(struct b43_wldev
*dev
, u16 rate
, int is_ofdm
)
2483 offset
+= (b43_plcp_get_ratecode_ofdm(rate
) & 0x000F) * 2;
2486 offset
+= (b43_plcp_get_ratecode_cck(rate
) & 0x000F) * 2;
2488 b43_shm_write16(dev
, B43_SHM_SHARED
, offset
+ 0x20,
2489 b43_shm_read16(dev
, B43_SHM_SHARED
, offset
));
2492 static void b43_rate_memory_init(struct b43_wldev
*dev
)
2494 switch (dev
->phy
.type
) {
2498 b43_rate_memory_write(dev
, B43_OFDM_RATE_6MB
, 1);
2499 b43_rate_memory_write(dev
, B43_OFDM_RATE_12MB
, 1);
2500 b43_rate_memory_write(dev
, B43_OFDM_RATE_18MB
, 1);
2501 b43_rate_memory_write(dev
, B43_OFDM_RATE_24MB
, 1);
2502 b43_rate_memory_write(dev
, B43_OFDM_RATE_36MB
, 1);
2503 b43_rate_memory_write(dev
, B43_OFDM_RATE_48MB
, 1);
2504 b43_rate_memory_write(dev
, B43_OFDM_RATE_54MB
, 1);
2505 if (dev
->phy
.type
== B43_PHYTYPE_A
)
2509 b43_rate_memory_write(dev
, B43_CCK_RATE_1MB
, 0);
2510 b43_rate_memory_write(dev
, B43_CCK_RATE_2MB
, 0);
2511 b43_rate_memory_write(dev
, B43_CCK_RATE_5MB
, 0);
2512 b43_rate_memory_write(dev
, B43_CCK_RATE_11MB
, 0);
2519 /* Set the default values for the PHY TX Control Words. */
2520 static void b43_set_phytxctl_defaults(struct b43_wldev
*dev
)
2524 ctl
|= B43_TXH_PHY_ENC_CCK
;
2525 ctl
|= B43_TXH_PHY_ANT01AUTO
;
2526 ctl
|= B43_TXH_PHY_TXPWR
;
2528 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_BEACPHYCTL
, ctl
);
2529 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_ACKCTSPHYCTL
, ctl
);
2530 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_PRPHYCTL
, ctl
);
2533 /* Set the TX-Antenna for management frames sent by firmware. */
2534 static void b43_mgmtframe_txantenna(struct b43_wldev
*dev
, int antenna
)
2539 ant
= b43_antenna_to_phyctl(antenna
);
2542 tmp
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_ACKCTSPHYCTL
);
2543 tmp
= (tmp
& ~B43_TXH_PHY_ANT
) | ant
;
2544 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_ACKCTSPHYCTL
, tmp
);
2545 /* For Probe Resposes */
2546 tmp
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_PRPHYCTL
);
2547 tmp
= (tmp
& ~B43_TXH_PHY_ANT
) | ant
;
2548 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_PRPHYCTL
, tmp
);
2551 /* This is the opposite of b43_chip_init() */
2552 static void b43_chip_exit(struct b43_wldev
*dev
)
2554 b43_radio_turn_off(dev
, 1);
2555 b43_gpio_cleanup(dev
);
2556 b43_lo_g_cleanup(dev
);
2557 /* firmware is released later */
2560 /* Initialize the chip
2561 * http://bcm-specs.sipsolutions.net/ChipInit
2563 static int b43_chip_init(struct b43_wldev
*dev
)
2565 struct b43_phy
*phy
= &dev
->phy
;
2567 u32 value32
, macctl
;
2570 /* Initialize the MAC control */
2571 macctl
= B43_MACCTL_IHR_ENABLED
| B43_MACCTL_SHM_ENABLED
;
2573 macctl
|= B43_MACCTL_GMODE
;
2574 macctl
|= B43_MACCTL_INFRA
;
2575 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
2577 err
= b43_request_firmware(dev
);
2580 err
= b43_upload_microcode(dev
);
2582 goto out
; /* firmware is released later */
2584 err
= b43_gpio_init(dev
);
2586 goto out
; /* firmware is released later */
2588 err
= b43_upload_initvals(dev
);
2590 goto err_gpio_clean
;
2591 b43_radio_turn_on(dev
);
2593 b43_write16(dev
, 0x03E6, 0x0000);
2594 err
= b43_phy_init(dev
);
2598 /* Select initial Interference Mitigation. */
2599 tmp
= phy
->interfmode
;
2600 phy
->interfmode
= B43_INTERFMODE_NONE
;
2601 b43_radio_set_interference_mitigation(dev
, tmp
);
2603 b43_set_rx_antenna(dev
, B43_ANTENNA_DEFAULT
);
2604 b43_mgmtframe_txantenna(dev
, B43_ANTENNA_DEFAULT
);
2606 if (phy
->type
== B43_PHYTYPE_B
) {
2607 value16
= b43_read16(dev
, 0x005E);
2609 b43_write16(dev
, 0x005E, value16
);
2611 b43_write32(dev
, 0x0100, 0x01000000);
2612 if (dev
->dev
->id
.revision
< 5)
2613 b43_write32(dev
, 0x010C, 0x01000000);
2615 b43_write32(dev
, B43_MMIO_MACCTL
, b43_read32(dev
, B43_MMIO_MACCTL
)
2616 & ~B43_MACCTL_INFRA
);
2617 b43_write32(dev
, B43_MMIO_MACCTL
, b43_read32(dev
, B43_MMIO_MACCTL
)
2618 | B43_MACCTL_INFRA
);
2620 /* Probe Response Timeout value */
2621 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2622 b43_shm_write16(dev
, B43_SHM_SHARED
, 0x0074, 0x0000);
2624 /* Initially set the wireless operation mode. */
2625 b43_adjust_opmode(dev
);
2627 if (dev
->dev
->id
.revision
< 3) {
2628 b43_write16(dev
, 0x060E, 0x0000);
2629 b43_write16(dev
, 0x0610, 0x8000);
2630 b43_write16(dev
, 0x0604, 0x0000);
2631 b43_write16(dev
, 0x0606, 0x0200);
2633 b43_write32(dev
, 0x0188, 0x80000000);
2634 b43_write32(dev
, 0x018C, 0x02000000);
2636 b43_write32(dev
, B43_MMIO_GEN_IRQ_REASON
, 0x00004000);
2637 b43_write32(dev
, B43_MMIO_DMA0_IRQ_MASK
, 0x0001DC00);
2638 b43_write32(dev
, B43_MMIO_DMA1_IRQ_MASK
, 0x0000DC00);
2639 b43_write32(dev
, B43_MMIO_DMA2_IRQ_MASK
, 0x0000DC00);
2640 b43_write32(dev
, B43_MMIO_DMA3_IRQ_MASK
, 0x0001DC00);
2641 b43_write32(dev
, B43_MMIO_DMA4_IRQ_MASK
, 0x0000DC00);
2642 b43_write32(dev
, B43_MMIO_DMA5_IRQ_MASK
, 0x0000DC00);
2644 value32
= ssb_read32(dev
->dev
, SSB_TMSLOW
);
2645 value32
|= 0x00100000;
2646 ssb_write32(dev
->dev
, SSB_TMSLOW
, value32
);
2648 b43_write16(dev
, B43_MMIO_POWERUP_DELAY
,
2649 dev
->dev
->bus
->chipco
.fast_pwrup_delay
);
2652 b43dbg(dev
->wl
, "Chip initialized\n");
2657 b43_radio_turn_off(dev
, 1);
2659 b43_gpio_cleanup(dev
);
2663 static void b43_periodic_every60sec(struct b43_wldev
*dev
)
2665 struct b43_phy
*phy
= &dev
->phy
;
2667 if (phy
->type
!= B43_PHYTYPE_G
)
2669 if (dev
->dev
->bus
->sprom
.boardflags_lo
& B43_BFL_RSSI
) {
2670 b43_mac_suspend(dev
);
2671 b43_calc_nrssi_slope(dev
);
2672 if ((phy
->radio_ver
== 0x2050) && (phy
->radio_rev
== 8)) {
2673 u8 old_chan
= phy
->channel
;
2675 /* VCO Calibration */
2677 b43_radio_selectchannel(dev
, 1, 0);
2679 b43_radio_selectchannel(dev
, 13, 0);
2680 b43_radio_selectchannel(dev
, old_chan
, 0);
2682 b43_mac_enable(dev
);
2686 static void b43_periodic_every30sec(struct b43_wldev
*dev
)
2688 /* Update device statistics. */
2689 b43_calculate_link_quality(dev
);
2692 static void b43_periodic_every15sec(struct b43_wldev
*dev
)
2694 struct b43_phy
*phy
= &dev
->phy
;
2696 if (phy
->type
== B43_PHYTYPE_G
) {
2697 //TODO: update_aci_moving_average
2698 if (phy
->aci_enable
&& phy
->aci_wlan_automatic
) {
2699 b43_mac_suspend(dev
);
2700 if (!phy
->aci_enable
&& 1 /*TODO: not scanning? */ ) {
2701 if (0 /*TODO: bunch of conditions */ ) {
2702 b43_radio_set_interference_mitigation
2703 (dev
, B43_INTERFMODE_MANUALWLAN
);
2705 } else if (1 /*TODO*/) {
2707 if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) {
2708 b43_radio_set_interference_mitigation(dev,
2709 B43_INTERFMODE_NONE);
2713 b43_mac_enable(dev
);
2714 } else if (phy
->interfmode
== B43_INTERFMODE_NONWLAN
&&
2716 //TODO: implement rev1 workaround
2719 b43_phy_xmitpower(dev
); //FIXME: unless scanning?
2720 b43_lo_g_maintanance_work(dev
);
2721 //TODO for APHY (temperature?)
2723 atomic_set(&phy
->txerr_cnt
, B43_PHY_TX_BADNESS_LIMIT
);
2727 static void do_periodic_work(struct b43_wldev
*dev
)
2731 state
= dev
->periodic_state
;
2733 b43_periodic_every60sec(dev
);
2735 b43_periodic_every30sec(dev
);
2736 b43_periodic_every15sec(dev
);
2739 /* Periodic work locking policy:
2740 * The whole periodic work handler is protected by
2741 * wl->mutex. If another lock is needed somewhere in the
2742 * pwork callchain, it's aquired in-place, where it's needed.
2744 static void b43_periodic_work_handler(struct work_struct
*work
)
2746 struct b43_wldev
*dev
= container_of(work
, struct b43_wldev
,
2747 periodic_work
.work
);
2748 struct b43_wl
*wl
= dev
->wl
;
2749 unsigned long delay
;
2751 mutex_lock(&wl
->mutex
);
2753 if (unlikely(b43_status(dev
) != B43_STAT_STARTED
))
2755 if (b43_debug(dev
, B43_DBG_PWORK_STOP
))
2758 do_periodic_work(dev
);
2760 dev
->periodic_state
++;
2762 if (b43_debug(dev
, B43_DBG_PWORK_FAST
))
2763 delay
= msecs_to_jiffies(50);
2765 delay
= round_jiffies_relative(HZ
* 15);
2766 queue_delayed_work(wl
->hw
->workqueue
, &dev
->periodic_work
, delay
);
2768 mutex_unlock(&wl
->mutex
);
2771 static void b43_periodic_tasks_setup(struct b43_wldev
*dev
)
2773 struct delayed_work
*work
= &dev
->periodic_work
;
2775 dev
->periodic_state
= 0;
2776 INIT_DELAYED_WORK(work
, b43_periodic_work_handler
);
2777 queue_delayed_work(dev
->wl
->hw
->workqueue
, work
, 0);
2780 /* Check if communication with the device works correctly. */
2781 static int b43_validate_chipaccess(struct b43_wldev
*dev
)
2785 backup
= b43_shm_read32(dev
, B43_SHM_SHARED
, 0);
2787 /* Check for read/write and endianness problems. */
2788 b43_shm_write32(dev
, B43_SHM_SHARED
, 0, 0x55AAAA55);
2789 if (b43_shm_read32(dev
, B43_SHM_SHARED
, 0) != 0x55AAAA55)
2791 b43_shm_write32(dev
, B43_SHM_SHARED
, 0, 0xAA5555AA);
2792 if (b43_shm_read32(dev
, B43_SHM_SHARED
, 0) != 0xAA5555AA)
2795 b43_shm_write32(dev
, B43_SHM_SHARED
, 0, backup
);
2797 if ((dev
->dev
->id
.revision
>= 3) && (dev
->dev
->id
.revision
<= 10)) {
2798 /* The 32bit register shadows the two 16bit registers
2799 * with update sideeffects. Validate this. */
2800 b43_write16(dev
, B43_MMIO_TSF_CFP_START
, 0xAAAA);
2801 b43_write32(dev
, B43_MMIO_TSF_CFP_START
, 0xCCCCBBBB);
2802 if (b43_read16(dev
, B43_MMIO_TSF_CFP_START_LOW
) != 0xBBBB)
2804 if (b43_read16(dev
, B43_MMIO_TSF_CFP_START_HIGH
) != 0xCCCC)
2807 b43_write32(dev
, B43_MMIO_TSF_CFP_START
, 0);
2809 v
= b43_read32(dev
, B43_MMIO_MACCTL
);
2810 v
|= B43_MACCTL_GMODE
;
2811 if (v
!= (B43_MACCTL_GMODE
| B43_MACCTL_IHR_ENABLED
))
2816 b43err(dev
->wl
, "Failed to validate the chipaccess\n");
2820 static void b43_security_init(struct b43_wldev
*dev
)
2822 dev
->max_nr_keys
= (dev
->dev
->id
.revision
>= 5) ? 58 : 20;
2823 B43_WARN_ON(dev
->max_nr_keys
> ARRAY_SIZE(dev
->key
));
2824 dev
->ktp
= b43_shm_read16(dev
, B43_SHM_SHARED
, B43_SHM_SH_KTP
);
2825 /* KTP is a word address, but we address SHM bytewise.
2826 * So multiply by two.
2829 if (dev
->dev
->id
.revision
>= 5) {
2830 /* Number of RCMTA address slots */
2831 b43_write16(dev
, B43_MMIO_RCMTA_COUNT
, dev
->max_nr_keys
- 8);
2833 b43_clear_keys(dev
);
2836 static int b43_rng_read(struct hwrng
*rng
, u32
* data
)
2838 struct b43_wl
*wl
= (struct b43_wl
*)rng
->priv
;
2839 unsigned long flags
;
2841 /* Don't take wl->mutex here, as it could deadlock with
2842 * hwrng internal locking. It's not needed to take
2843 * wl->mutex here, anyway. */
2845 spin_lock_irqsave(&wl
->irq_lock
, flags
);
2846 *data
= b43_read16(wl
->current_dev
, B43_MMIO_RNG
);
2847 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
2849 return (sizeof(u16
));
2852 static void b43_rng_exit(struct b43_wl
*wl
)
2854 if (wl
->rng_initialized
)
2855 hwrng_unregister(&wl
->rng
);
2858 static int b43_rng_init(struct b43_wl
*wl
)
2862 snprintf(wl
->rng_name
, ARRAY_SIZE(wl
->rng_name
),
2863 "%s_%s", KBUILD_MODNAME
, wiphy_name(wl
->hw
->wiphy
));
2864 wl
->rng
.name
= wl
->rng_name
;
2865 wl
->rng
.data_read
= b43_rng_read
;
2866 wl
->rng
.priv
= (unsigned long)wl
;
2867 wl
->rng_initialized
= 1;
2868 err
= hwrng_register(&wl
->rng
);
2870 wl
->rng_initialized
= 0;
2871 b43err(wl
, "Failed to register the random "
2872 "number generator (%d)\n", err
);
2878 static int b43_op_tx(struct ieee80211_hw
*hw
,
2879 struct sk_buff
*skb
)
2881 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
2882 struct b43_wldev
*dev
= wl
->current_dev
;
2883 unsigned long flags
;
2886 if (unlikely(skb
->len
< 2 + 2 + 6)) {
2887 /* Too short, this can't be a valid frame. */
2888 dev_kfree_skb_any(skb
);
2889 return NETDEV_TX_OK
;
2891 B43_WARN_ON(skb_shinfo(skb
)->nr_frags
);
2893 return NETDEV_TX_BUSY
;
2895 /* Transmissions on seperate queues can run concurrently. */
2896 read_lock_irqsave(&wl
->tx_lock
, flags
);
2899 if (likely(b43_status(dev
) >= B43_STAT_STARTED
)) {
2900 if (b43_using_pio_transfers(dev
))
2901 err
= b43_pio_tx(dev
, skb
);
2903 err
= b43_dma_tx(dev
, skb
);
2906 read_unlock_irqrestore(&wl
->tx_lock
, flags
);
2909 return NETDEV_TX_BUSY
;
2910 return NETDEV_TX_OK
;
2913 /* Locking: wl->irq_lock */
2914 static void b43_qos_params_upload(struct b43_wldev
*dev
,
2915 const struct ieee80211_tx_queue_params
*p
,
2918 u16 params
[B43_NR_QOSPARAMS
];
2919 int cw_min
, cw_max
, aifs
, bslots
, tmp
;
2922 const u16 aCWmin
= 0x0001;
2923 const u16 aCWmax
= 0x03FF;
2925 /* Calculate the default values for the parameters, if needed. */
2926 switch (shm_offset
) {
2928 aifs
= (p
->aifs
== -1) ? 2 : p
->aifs
;
2929 cw_min
= (p
->cw_min
== 0) ? ((aCWmin
+ 1) / 4 - 1) : p
->cw_min
;
2930 cw_max
= (p
->cw_max
== 0) ? ((aCWmin
+ 1) / 2 - 1) : p
->cw_max
;
2933 aifs
= (p
->aifs
== -1) ? 2 : p
->aifs
;
2934 cw_min
= (p
->cw_min
== 0) ? ((aCWmin
+ 1) / 2 - 1) : p
->cw_min
;
2935 cw_max
= (p
->cw_max
== 0) ? aCWmin
: p
->cw_max
;
2937 case B43_QOS_BESTEFFORT
:
2938 aifs
= (p
->aifs
== -1) ? 3 : p
->aifs
;
2939 cw_min
= (p
->cw_min
== 0) ? aCWmin
: p
->cw_min
;
2940 cw_max
= (p
->cw_max
== 0) ? aCWmax
: p
->cw_max
;
2942 case B43_QOS_BACKGROUND
:
2943 aifs
= (p
->aifs
== -1) ? 7 : p
->aifs
;
2944 cw_min
= (p
->cw_min
== 0) ? aCWmin
: p
->cw_min
;
2945 cw_max
= (p
->cw_max
== 0) ? aCWmax
: p
->cw_max
;
2955 bslots
= b43_read16(dev
, B43_MMIO_RNG
) % cw_min
;
2957 memset(¶ms
, 0, sizeof(params
));
2959 params
[B43_QOSPARAM_TXOP
] = p
->txop
* 32;
2960 params
[B43_QOSPARAM_CWMIN
] = cw_min
;
2961 params
[B43_QOSPARAM_CWMAX
] = cw_max
;
2962 params
[B43_QOSPARAM_CWCUR
] = cw_min
;
2963 params
[B43_QOSPARAM_AIFS
] = aifs
;
2964 params
[B43_QOSPARAM_BSLOTS
] = bslots
;
2965 params
[B43_QOSPARAM_REGGAP
] = bslots
+ aifs
;
2967 for (i
= 0; i
< ARRAY_SIZE(params
); i
++) {
2968 if (i
== B43_QOSPARAM_STATUS
) {
2969 tmp
= b43_shm_read16(dev
, B43_SHM_SHARED
,
2970 shm_offset
+ (i
* 2));
2971 /* Mark the parameters as updated. */
2973 b43_shm_write16(dev
, B43_SHM_SHARED
,
2974 shm_offset
+ (i
* 2),
2977 b43_shm_write16(dev
, B43_SHM_SHARED
,
2978 shm_offset
+ (i
* 2),
2984 /* Update the QOS parameters in hardware. */
2985 static void b43_qos_update(struct b43_wldev
*dev
)
2987 struct b43_wl
*wl
= dev
->wl
;
2988 struct b43_qos_params
*params
;
2989 unsigned long flags
;
2992 /* Mapping of mac80211 queues to b43 SHM offsets. */
2993 static const u16 qos_shm_offsets
[] = {
2994 [0] = B43_QOS_VOICE
,
2995 [1] = B43_QOS_VIDEO
,
2996 [2] = B43_QOS_BESTEFFORT
,
2997 [3] = B43_QOS_BACKGROUND
,
2999 BUILD_BUG_ON(ARRAY_SIZE(qos_shm_offsets
) != ARRAY_SIZE(wl
->qos_params
));
3001 b43_mac_suspend(dev
);
3002 spin_lock_irqsave(&wl
->irq_lock
, flags
);
3004 for (i
= 0; i
< ARRAY_SIZE(wl
->qos_params
); i
++) {
3005 params
= &(wl
->qos_params
[i
]);
3006 if (params
->need_hw_update
) {
3007 b43_qos_params_upload(dev
, &(params
->p
),
3008 qos_shm_offsets
[i
]);
3009 params
->need_hw_update
= 0;
3013 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
3014 b43_mac_enable(dev
);
3017 static void b43_qos_clear(struct b43_wl
*wl
)
3019 struct b43_qos_params
*params
;
3022 for (i
= 0; i
< ARRAY_SIZE(wl
->qos_params
); i
++) {
3023 params
= &(wl
->qos_params
[i
]);
3025 memset(&(params
->p
), 0, sizeof(params
->p
));
3026 params
->p
.aifs
= -1;
3027 params
->need_hw_update
= 1;
3031 /* Initialize the core's QOS capabilities */
3032 static void b43_qos_init(struct b43_wldev
*dev
)
3034 struct b43_wl
*wl
= dev
->wl
;
3037 /* Upload the current QOS parameters. */
3038 for (i
= 0; i
< ARRAY_SIZE(wl
->qos_params
); i
++)
3039 wl
->qos_params
[i
].need_hw_update
= 1;
3040 b43_qos_update(dev
);
3042 /* Enable QOS support. */
3043 b43_hf_write(dev
, b43_hf_read(dev
) | B43_HF_EDCF
);
3044 b43_write16(dev
, B43_MMIO_IFSCTL
,
3045 b43_read16(dev
, B43_MMIO_IFSCTL
)
3046 | B43_MMIO_IFSCTL_USE_EDCF
);
3049 static void b43_qos_update_work(struct work_struct
*work
)
3051 struct b43_wl
*wl
= container_of(work
, struct b43_wl
, qos_update_work
);
3052 struct b43_wldev
*dev
;
3054 mutex_lock(&wl
->mutex
);
3055 dev
= wl
->current_dev
;
3056 if (likely(dev
&& (b43_status(dev
) >= B43_STAT_INITIALIZED
)))
3057 b43_qos_update(dev
);
3058 mutex_unlock(&wl
->mutex
);
3061 static int b43_op_conf_tx(struct ieee80211_hw
*hw
, u16 _queue
,
3062 const struct ieee80211_tx_queue_params
*params
)
3064 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3065 unsigned long flags
;
3066 unsigned int queue
= (unsigned int)_queue
;
3067 struct b43_qos_params
*p
;
3069 if (queue
>= ARRAY_SIZE(wl
->qos_params
)) {
3070 /* Queue not available or don't support setting
3071 * params on this queue. Return success to not
3072 * confuse mac80211. */
3076 spin_lock_irqsave(&wl
->irq_lock
, flags
);
3077 p
= &(wl
->qos_params
[queue
]);
3078 memcpy(&(p
->p
), params
, sizeof(p
->p
));
3079 p
->need_hw_update
= 1;
3080 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
3082 queue_work(hw
->workqueue
, &wl
->qos_update_work
);
3087 static int b43_op_get_tx_stats(struct ieee80211_hw
*hw
,
3088 struct ieee80211_tx_queue_stats
*stats
)
3090 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3091 struct b43_wldev
*dev
= wl
->current_dev
;
3092 unsigned long flags
;
3097 spin_lock_irqsave(&wl
->irq_lock
, flags
);
3098 if (likely(b43_status(dev
) >= B43_STAT_STARTED
)) {
3099 if (b43_using_pio_transfers(dev
))
3100 b43_pio_get_tx_stats(dev
, stats
);
3102 b43_dma_get_tx_stats(dev
, stats
);
3105 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
3110 static int b43_op_get_stats(struct ieee80211_hw
*hw
,
3111 struct ieee80211_low_level_stats
*stats
)
3113 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3114 unsigned long flags
;
3116 spin_lock_irqsave(&wl
->irq_lock
, flags
);
3117 memcpy(stats
, &wl
->ieee_stats
, sizeof(*stats
));
3118 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
3123 static void b43_put_phy_into_reset(struct b43_wldev
*dev
)
3125 struct ssb_device
*sdev
= dev
->dev
;
3128 tmslow
= ssb_read32(sdev
, SSB_TMSLOW
);
3129 tmslow
&= ~B43_TMSLOW_GMODE
;
3130 tmslow
|= B43_TMSLOW_PHYRESET
;
3131 tmslow
|= SSB_TMSLOW_FGC
;
3132 ssb_write32(sdev
, SSB_TMSLOW
, tmslow
);
3135 tmslow
= ssb_read32(sdev
, SSB_TMSLOW
);
3136 tmslow
&= ~SSB_TMSLOW_FGC
;
3137 tmslow
|= B43_TMSLOW_PHYRESET
;
3138 ssb_write32(sdev
, SSB_TMSLOW
, tmslow
);
3142 static const char * band_to_string(enum ieee80211_band band
)
3145 case IEEE80211_BAND_5GHZ
:
3147 case IEEE80211_BAND_2GHZ
:
3156 /* Expects wl->mutex locked */
3157 static int b43_switch_band(struct b43_wl
*wl
, struct ieee80211_channel
*chan
)
3159 struct b43_wldev
*up_dev
= NULL
;
3160 struct b43_wldev
*down_dev
;
3161 struct b43_wldev
*d
;
3166 /* Find a device and PHY which supports the band. */
3167 list_for_each_entry(d
, &wl
->devlist
, list
) {
3168 switch (chan
->band
) {
3169 case IEEE80211_BAND_5GHZ
:
3170 if (d
->phy
.supports_5ghz
) {
3175 case IEEE80211_BAND_2GHZ
:
3176 if (d
->phy
.supports_2ghz
) {
3189 b43err(wl
, "Could not find a device for %s-GHz band operation\n",
3190 band_to_string(chan
->band
));
3193 if ((up_dev
== wl
->current_dev
) &&
3194 (!!wl
->current_dev
->phy
.gmode
== !!gmode
)) {
3195 /* This device is already running. */
3198 b43dbg(wl
, "Switching to %s-GHz band\n",
3199 band_to_string(chan
->band
));
3200 down_dev
= wl
->current_dev
;
3202 prev_status
= b43_status(down_dev
);
3203 /* Shutdown the currently running core. */
3204 if (prev_status
>= B43_STAT_STARTED
)
3205 b43_wireless_core_stop(down_dev
);
3206 if (prev_status
>= B43_STAT_INITIALIZED
)
3207 b43_wireless_core_exit(down_dev
);
3209 if (down_dev
!= up_dev
) {
3210 /* We switch to a different core, so we put PHY into
3211 * RESET on the old core. */
3212 b43_put_phy_into_reset(down_dev
);
3215 /* Now start the new core. */
3216 up_dev
->phy
.gmode
= gmode
;
3217 if (prev_status
>= B43_STAT_INITIALIZED
) {
3218 err
= b43_wireless_core_init(up_dev
);
3220 b43err(wl
, "Fatal: Could not initialize device for "
3221 "selected %s-GHz band\n",
3222 band_to_string(chan
->band
));
3226 if (prev_status
>= B43_STAT_STARTED
) {
3227 err
= b43_wireless_core_start(up_dev
);
3229 b43err(wl
, "Fatal: Coult not start device for "
3230 "selected %s-GHz band\n",
3231 band_to_string(chan
->band
));
3232 b43_wireless_core_exit(up_dev
);
3236 B43_WARN_ON(b43_status(up_dev
) != prev_status
);
3238 wl
->current_dev
= up_dev
;
3242 /* Whoops, failed to init the new core. No core is operating now. */
3243 wl
->current_dev
= NULL
;
3247 static int b43_op_config(struct ieee80211_hw
*hw
, struct ieee80211_conf
*conf
)
3249 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3250 struct b43_wldev
*dev
;
3251 struct b43_phy
*phy
;
3252 unsigned long flags
;
3257 mutex_lock(&wl
->mutex
);
3259 /* Switch the band (if necessary). This might change the active core. */
3260 err
= b43_switch_band(wl
, conf
->channel
);
3262 goto out_unlock_mutex
;
3263 dev
= wl
->current_dev
;
3266 /* Disable IRQs while reconfiguring the device.
3267 * This makes it possible to drop the spinlock throughout
3268 * the reconfiguration process. */
3269 spin_lock_irqsave(&wl
->irq_lock
, flags
);
3270 if (b43_status(dev
) < B43_STAT_STARTED
) {
3271 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
3272 goto out_unlock_mutex
;
3274 savedirqs
= b43_interrupt_disable(dev
, B43_IRQ_ALL
);
3275 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
3276 b43_synchronize_irq(dev
);
3278 /* Switch to the requested channel.
3279 * The firmware takes care of races with the TX handler. */
3280 if (conf
->channel
->hw_value
!= phy
->channel
)
3281 b43_radio_selectchannel(dev
, conf
->channel
->hw_value
, 0);
3283 /* Enable/Disable ShortSlot timing. */
3284 if ((!!(conf
->flags
& IEEE80211_CONF_SHORT_SLOT_TIME
)) !=
3286 B43_WARN_ON(phy
->type
!= B43_PHYTYPE_G
);
3287 if (conf
->flags
& IEEE80211_CONF_SHORT_SLOT_TIME
)
3288 b43_short_slot_timing_enable(dev
);
3290 b43_short_slot_timing_disable(dev
);
3293 dev
->wl
->radiotap_enabled
= !!(conf
->flags
& IEEE80211_CONF_RADIOTAP
);
3295 /* Adjust the desired TX power level. */
3296 if (conf
->power_level
!= 0) {
3297 if (conf
->power_level
!= phy
->power_level
) {
3298 phy
->power_level
= conf
->power_level
;
3299 b43_phy_xmitpower(dev
);
3303 /* Antennas for RX and management frame TX. */
3304 antenna
= b43_antenna_from_ieee80211(dev
, conf
->antenna_sel_tx
);
3305 b43_mgmtframe_txantenna(dev
, antenna
);
3306 antenna
= b43_antenna_from_ieee80211(dev
, conf
->antenna_sel_rx
);
3307 b43_set_rx_antenna(dev
, antenna
);
3309 /* Update templates for AP mode. */
3310 if (b43_is_mode(wl
, IEEE80211_IF_TYPE_AP
))
3311 b43_set_beacon_int(dev
, conf
->beacon_int
);
3313 if (!!conf
->radio_enabled
!= phy
->radio_on
) {
3314 if (conf
->radio_enabled
) {
3315 b43_radio_turn_on(dev
);
3316 b43info(dev
->wl
, "Radio turned on by software\n");
3317 if (!dev
->radio_hw_enable
) {
3318 b43info(dev
->wl
, "The hardware RF-kill button "
3319 "still turns the radio physically off. "
3320 "Press the button to turn it on.\n");
3323 b43_radio_turn_off(dev
, 0);
3324 b43info(dev
->wl
, "Radio turned off by software\n");
3328 spin_lock_irqsave(&wl
->irq_lock
, flags
);
3329 b43_interrupt_enable(dev
, savedirqs
);
3331 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
3333 mutex_unlock(&wl
->mutex
);
3338 static int b43_op_set_key(struct ieee80211_hw
*hw
, enum set_key_cmd cmd
,
3339 const u8
*local_addr
, const u8
*addr
,
3340 struct ieee80211_key_conf
*key
)
3342 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3343 struct b43_wldev
*dev
;
3344 unsigned long flags
;
3348 DECLARE_MAC_BUF(mac
);
3350 if (modparam_nohwcrypt
)
3351 return -ENOSPC
; /* User disabled HW-crypto */
3353 mutex_lock(&wl
->mutex
);
3354 spin_lock_irqsave(&wl
->irq_lock
, flags
);
3356 dev
= wl
->current_dev
;
3358 if (!dev
|| b43_status(dev
) < B43_STAT_INITIALIZED
)
3364 if (key
->keylen
== 5)
3365 algorithm
= B43_SEC_ALGO_WEP40
;
3367 algorithm
= B43_SEC_ALGO_WEP104
;
3370 algorithm
= B43_SEC_ALGO_TKIP
;
3373 algorithm
= B43_SEC_ALGO_AES
;
3379 index
= (u8
) (key
->keyidx
);
3385 if (algorithm
== B43_SEC_ALGO_TKIP
) {
3386 /* FIXME: No TKIP hardware encryption for now. */
3391 if (is_broadcast_ether_addr(addr
)) {
3392 /* addr is FF:FF:FF:FF:FF:FF for default keys */
3393 err
= b43_key_write(dev
, index
, algorithm
,
3394 key
->key
, key
->keylen
, NULL
, key
);
3397 * either pairwise key or address is 00:00:00:00:00:00
3398 * for transmit-only keys
3400 err
= b43_key_write(dev
, -1, algorithm
,
3401 key
->key
, key
->keylen
, addr
, key
);
3406 if (algorithm
== B43_SEC_ALGO_WEP40
||
3407 algorithm
== B43_SEC_ALGO_WEP104
) {
3408 b43_hf_write(dev
, b43_hf_read(dev
) | B43_HF_USEDEFKEYS
);
3411 b43_hf_read(dev
) & ~B43_HF_USEDEFKEYS
);
3413 key
->flags
|= IEEE80211_KEY_FLAG_GENERATE_IV
;
3416 err
= b43_key_clear(dev
, key
->hw_key_idx
);
3425 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
3426 mutex_unlock(&wl
->mutex
);
3428 b43dbg(wl
, "%s hardware based encryption for keyidx: %d, "
3430 cmd
== SET_KEY
? "Using" : "Disabling", key
->keyidx
,
3431 print_mac(mac
, addr
));
3436 static void b43_op_configure_filter(struct ieee80211_hw
*hw
,
3437 unsigned int changed
, unsigned int *fflags
,
3438 int mc_count
, struct dev_addr_list
*mc_list
)
3440 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3441 struct b43_wldev
*dev
= wl
->current_dev
;
3442 unsigned long flags
;
3449 spin_lock_irqsave(&wl
->irq_lock
, flags
);
3450 *fflags
&= FIF_PROMISC_IN_BSS
|
3456 FIF_BCN_PRBRESP_PROMISC
;
3458 changed
&= FIF_PROMISC_IN_BSS
|
3464 FIF_BCN_PRBRESP_PROMISC
;
3466 wl
->filter_flags
= *fflags
;
3468 if (changed
&& b43_status(dev
) >= B43_STAT_INITIALIZED
)
3469 b43_adjust_opmode(dev
);
3470 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
3473 static int b43_op_config_interface(struct ieee80211_hw
*hw
,
3474 struct ieee80211_vif
*vif
,
3475 struct ieee80211_if_conf
*conf
)
3477 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
3478 struct b43_wldev
*dev
= wl
->current_dev
;
3479 unsigned long flags
;
3483 mutex_lock(&wl
->mutex
);
3484 spin_lock_irqsave(&wl
->irq_lock
, flags
);
3485 B43_WARN_ON(wl
->vif
!= vif
);
3487 memcpy(wl
->bssid
, conf
->bssid
, ETH_ALEN
);
3489 memset(wl
->bssid
, 0, ETH_ALEN
);
3490 if (b43_status(dev
) >= B43_STAT_INITIALIZED
) {
3491 if (b43_is_mode(wl
, IEEE80211_IF_TYPE_AP
)) {
3492 B43_WARN_ON(conf
->type
!= IEEE80211_IF_TYPE_AP
);
3493 b43_set_ssid(dev
, conf
->ssid
, conf
->ssid_len
);
3495 b43_update_templates(wl
, conf
->beacon
);
3497 b43_write_mac_bssid_templates(dev
);
3499 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
3500 mutex_unlock(&wl
->mutex
);
3505 /* Locking: wl->mutex */
3506 static void b43_wireless_core_stop(struct b43_wldev
*dev
)
3508 struct b43_wl
*wl
= dev
->wl
;
3509 unsigned long flags
;
3511 if (b43_status(dev
) < B43_STAT_STARTED
)
3514 /* Disable and sync interrupts. We must do this before than
3515 * setting the status to INITIALIZED, as the interrupt handler
3516 * won't care about IRQs then. */
3517 spin_lock_irqsave(&wl
->irq_lock
, flags
);
3518 dev
->irq_savedstate
= b43_interrupt_disable(dev
, B43_IRQ_ALL
);
3519 b43_read32(dev
, B43_MMIO_GEN_IRQ_MASK
); /* flush */
3520 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
3521 b43_synchronize_irq(dev
);
3523 write_lock_irqsave(&wl
->tx_lock
, flags
);
3524 b43_set_status(dev
, B43_STAT_INITIALIZED
);
3525 write_unlock_irqrestore(&wl
->tx_lock
, flags
);
3528 mutex_unlock(&wl
->mutex
);
3529 /* Must unlock as it would otherwise deadlock. No races here.
3530 * Cancel the possibly running self-rearming periodic work. */
3531 cancel_delayed_work_sync(&dev
->periodic_work
);
3532 mutex_lock(&wl
->mutex
);
3534 b43_mac_suspend(dev
);
3535 free_irq(dev
->dev
->irq
, dev
);
3536 b43dbg(wl
, "Wireless interface stopped\n");
3539 /* Locking: wl->mutex */
3540 static int b43_wireless_core_start(struct b43_wldev
*dev
)
3544 B43_WARN_ON(b43_status(dev
) != B43_STAT_INITIALIZED
);
3546 drain_txstatus_queue(dev
);
3547 err
= request_irq(dev
->dev
->irq
, b43_interrupt_handler
,
3548 IRQF_SHARED
, KBUILD_MODNAME
, dev
);
3550 b43err(dev
->wl
, "Cannot request IRQ-%d\n", dev
->dev
->irq
);
3554 /* We are ready to run. */
3555 b43_set_status(dev
, B43_STAT_STARTED
);
3557 /* Start data flow (TX/RX). */
3558 b43_mac_enable(dev
);
3559 b43_interrupt_enable(dev
, dev
->irq_savedstate
);
3561 /* Start maintainance work */
3562 b43_periodic_tasks_setup(dev
);
3564 b43dbg(dev
->wl
, "Wireless interface started\n");
3569 /* Get PHY and RADIO versioning numbers */
3570 static int b43_phy_versioning(struct b43_wldev
*dev
)
3572 struct b43_phy
*phy
= &dev
->phy
;
3580 int unsupported
= 0;
3582 /* Get PHY versioning */
3583 tmp
= b43_read16(dev
, B43_MMIO_PHY_VER
);
3584 analog_type
= (tmp
& B43_PHYVER_ANALOG
) >> B43_PHYVER_ANALOG_SHIFT
;
3585 phy_type
= (tmp
& B43_PHYVER_TYPE
) >> B43_PHYVER_TYPE_SHIFT
;
3586 phy_rev
= (tmp
& B43_PHYVER_VERSION
);
3593 if (phy_rev
!= 2 && phy_rev
!= 4 && phy_rev
!= 6
3601 #ifdef CONFIG_B43_NPHY
3611 b43err(dev
->wl
, "FOUND UNSUPPORTED PHY "
3612 "(Analog %u, Type %u, Revision %u)\n",
3613 analog_type
, phy_type
, phy_rev
);
3616 b43dbg(dev
->wl
, "Found PHY: Analog %u, Type %u, Revision %u\n",
3617 analog_type
, phy_type
, phy_rev
);
3619 /* Get RADIO versioning */
3620 if (dev
->dev
->bus
->chip_id
== 0x4317) {
3621 if (dev
->dev
->bus
->chip_rev
== 0)
3623 else if (dev
->dev
->bus
->chip_rev
== 1)
3628 b43_write16(dev
, B43_MMIO_RADIO_CONTROL
, B43_RADIOCTL_ID
);
3629 tmp
= b43_read16(dev
, B43_MMIO_RADIO_DATA_LOW
);
3630 b43_write16(dev
, B43_MMIO_RADIO_CONTROL
, B43_RADIOCTL_ID
);
3631 tmp
|= (u32
)b43_read16(dev
, B43_MMIO_RADIO_DATA_HIGH
) << 16;
3633 radio_manuf
= (tmp
& 0x00000FFF);
3634 radio_ver
= (tmp
& 0x0FFFF000) >> 12;
3635 radio_rev
= (tmp
& 0xF0000000) >> 28;
3636 if (radio_manuf
!= 0x17F /* Broadcom */)
3640 if (radio_ver
!= 0x2060)
3644 if (radio_manuf
!= 0x17F)
3648 if ((radio_ver
& 0xFFF0) != 0x2050)
3652 if (radio_ver
!= 0x2050)
3656 if (radio_ver
!= 0x2055)
3663 b43err(dev
->wl
, "FOUND UNSUPPORTED RADIO "
3664 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3665 radio_manuf
, radio_ver
, radio_rev
);
3668 b43dbg(dev
->wl
, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3669 radio_manuf
, radio_ver
, radio_rev
);
3671 phy
->radio_manuf
= radio_manuf
;
3672 phy
->radio_ver
= radio_ver
;
3673 phy
->radio_rev
= radio_rev
;
3675 phy
->analog
= analog_type
;
3676 phy
->type
= phy_type
;
3682 static void setup_struct_phy_for_init(struct b43_wldev
*dev
,
3683 struct b43_phy
*phy
)
3685 struct b43_txpower_lo_control
*lo
;
3688 memset(phy
->minlowsig
, 0xFF, sizeof(phy
->minlowsig
));
3689 memset(phy
->minlowsigpos
, 0, sizeof(phy
->minlowsigpos
));
3691 phy
->aci_enable
= 0;
3692 phy
->aci_wlan_automatic
= 0;
3693 phy
->aci_hw_rssi
= 0;
3695 phy
->radio_off_context
.valid
= 0;
3697 lo
= phy
->lo_control
;
3699 memset(lo
, 0, sizeof(*(phy
->lo_control
)));
3701 INIT_LIST_HEAD(&lo
->calib_list
);
3703 phy
->max_lb_gain
= 0;
3704 phy
->trsw_rx_gain
= 0;
3705 phy
->txpwr_offset
= 0;
3708 phy
->nrssislope
= 0;
3709 for (i
= 0; i
< ARRAY_SIZE(phy
->nrssi
); i
++)
3710 phy
->nrssi
[i
] = -1000;
3711 for (i
= 0; i
< ARRAY_SIZE(phy
->nrssi_lt
); i
++)
3712 phy
->nrssi_lt
[i
] = i
;
3714 phy
->lofcal
= 0xFFFF;
3715 phy
->initval
= 0xFFFF;
3717 phy
->interfmode
= B43_INTERFMODE_NONE
;
3718 phy
->channel
= 0xFF;
3720 phy
->hardware_power_control
= !!modparam_hwpctl
;
3722 /* PHY TX errors counter. */
3723 atomic_set(&phy
->txerr_cnt
, B43_PHY_TX_BADNESS_LIMIT
);
3725 /* OFDM-table address caching. */
3726 phy
->ofdmtab_addr_direction
= B43_OFDMTAB_DIRECTION_UNKNOWN
;
3729 static void setup_struct_wldev_for_init(struct b43_wldev
*dev
)
3733 /* Assume the radio is enabled. If it's not enabled, the state will
3734 * immediately get fixed on the first periodic work run. */
3735 dev
->radio_hw_enable
= 1;
3738 memset(&dev
->stats
, 0, sizeof(dev
->stats
));
3740 setup_struct_phy_for_init(dev
, &dev
->phy
);
3742 /* IRQ related flags */
3743 dev
->irq_reason
= 0;
3744 memset(dev
->dma_reason
, 0, sizeof(dev
->dma_reason
));
3745 dev
->irq_savedstate
= B43_IRQ_MASKTEMPLATE
;
3747 dev
->mac_suspended
= 1;
3749 /* Noise calculation context */
3750 memset(&dev
->noisecalc
, 0, sizeof(dev
->noisecalc
));
3753 static void b43_bluetooth_coext_enable(struct b43_wldev
*dev
)
3755 struct ssb_sprom
*sprom
= &dev
->dev
->bus
->sprom
;
3758 if (!modparam_btcoex
)
3760 if (!(sprom
->boardflags_lo
& B43_BFL_BTCOEXIST
))
3762 if (dev
->phy
.type
!= B43_PHYTYPE_B
&& !dev
->phy
.gmode
)
3765 hf
= b43_hf_read(dev
);
3766 if (sprom
->boardflags_lo
& B43_BFL_BTCMOD
)
3767 hf
|= B43_HF_BTCOEXALT
;
3769 hf
|= B43_HF_BTCOEX
;
3770 b43_hf_write(dev
, hf
);
3773 static void b43_bluetooth_coext_disable(struct b43_wldev
*dev
)
3775 if (!modparam_btcoex
)
3780 static void b43_imcfglo_timeouts_workaround(struct b43_wldev
*dev
)
3782 #ifdef CONFIG_SSB_DRIVER_PCICORE
3783 struct ssb_bus
*bus
= dev
->dev
->bus
;
3786 if (bus
->pcicore
.dev
&&
3787 bus
->pcicore
.dev
->id
.coreid
== SSB_DEV_PCI
&&
3788 bus
->pcicore
.dev
->id
.revision
<= 5) {
3789 /* IMCFGLO timeouts workaround. */
3790 tmp
= ssb_read32(dev
->dev
, SSB_IMCFGLO
);
3791 tmp
&= ~SSB_IMCFGLO_REQTO
;
3792 tmp
&= ~SSB_IMCFGLO_SERTO
;
3793 switch (bus
->bustype
) {
3794 case SSB_BUSTYPE_PCI
:
3795 case SSB_BUSTYPE_PCMCIA
:
3798 case SSB_BUSTYPE_SSB
:
3802 ssb_write32(dev
->dev
, SSB_IMCFGLO
, tmp
);
3804 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3807 /* Write the short and long frame retry limit values. */
3808 static void b43_set_retry_limits(struct b43_wldev
*dev
,
3809 unsigned int short_retry
,
3810 unsigned int long_retry
)
3812 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3813 * the chip-internal counter. */
3814 short_retry
= min(short_retry
, (unsigned int)0xF);
3815 long_retry
= min(long_retry
, (unsigned int)0xF);
3817 b43_shm_write16(dev
, B43_SHM_SCRATCH
, B43_SHM_SC_SRLIMIT
,
3819 b43_shm_write16(dev
, B43_SHM_SCRATCH
, B43_SHM_SC_LRLIMIT
,
3823 static void b43_set_synth_pu_delay(struct b43_wldev
*dev
, bool idle
)
3827 /* The time value is in microseconds. */
3828 if (dev
->phy
.type
== B43_PHYTYPE_A
)
3832 if (b43_is_mode(dev
->wl
, IEEE80211_IF_TYPE_IBSS
) || idle
)
3834 if ((dev
->phy
.radio_ver
== 0x2050) && (dev
->phy
.radio_rev
== 8))
3835 pu_delay
= max(pu_delay
, (u16
)2400);
3837 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_SPUWKUP
, pu_delay
);
3840 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
3841 static void b43_set_pretbtt(struct b43_wldev
*dev
)
3845 /* The time value is in microseconds. */
3846 if (b43_is_mode(dev
->wl
, IEEE80211_IF_TYPE_IBSS
)) {
3849 if (dev
->phy
.type
== B43_PHYTYPE_A
)
3854 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_PRETBTT
, pretbtt
);
3855 b43_write16(dev
, B43_MMIO_TSF_CFP_PRETBTT
, pretbtt
);
3858 /* Shutdown a wireless core */
3859 /* Locking: wl->mutex */
3860 static void b43_wireless_core_exit(struct b43_wldev
*dev
)
3862 struct b43_phy
*phy
= &dev
->phy
;
3865 B43_WARN_ON(b43_status(dev
) > B43_STAT_INITIALIZED
);
3866 if (b43_status(dev
) != B43_STAT_INITIALIZED
)
3868 b43_set_status(dev
, B43_STAT_UNINIT
);
3870 /* Stop the microcode PSM. */
3871 macctl
= b43_read32(dev
, B43_MMIO_MACCTL
);
3872 macctl
&= ~B43_MACCTL_PSM_RUN
;
3873 macctl
|= B43_MACCTL_PSM_JMP0
;
3874 b43_write32(dev
, B43_MMIO_MACCTL
, macctl
);
3876 if (!dev
->suspend_in_progress
) {
3878 b43_rng_exit(dev
->wl
);
3883 b43_radio_turn_off(dev
, 1);
3884 b43_switch_analog(dev
, 0);
3885 if (phy
->dyn_tssi_tbl
)
3886 kfree(phy
->tssi2dbm
);
3887 kfree(phy
->lo_control
);
3888 phy
->lo_control
= NULL
;
3889 if (dev
->wl
->current_beacon
) {
3890 dev_kfree_skb_any(dev
->wl
->current_beacon
);
3891 dev
->wl
->current_beacon
= NULL
;
3894 ssb_device_disable(dev
->dev
, 0);
3895 ssb_bus_may_powerdown(dev
->dev
->bus
);
3898 /* Initialize a wireless core */
3899 static int b43_wireless_core_init(struct b43_wldev
*dev
)
3901 struct b43_wl
*wl
= dev
->wl
;
3902 struct ssb_bus
*bus
= dev
->dev
->bus
;
3903 struct ssb_sprom
*sprom
= &bus
->sprom
;
3904 struct b43_phy
*phy
= &dev
->phy
;
3909 B43_WARN_ON(b43_status(dev
) != B43_STAT_UNINIT
);
3911 err
= ssb_bus_powerup(bus
, 0);
3914 if (!ssb_device_is_enabled(dev
->dev
)) {
3915 tmp
= phy
->gmode
? B43_TMSLOW_GMODE
: 0;
3916 b43_wireless_core_reset(dev
, tmp
);
3919 if ((phy
->type
== B43_PHYTYPE_B
) || (phy
->type
== B43_PHYTYPE_G
)) {
3921 kzalloc(sizeof(*(phy
->lo_control
)), GFP_KERNEL
);
3922 if (!phy
->lo_control
) {
3927 setup_struct_wldev_for_init(dev
);
3929 err
= b43_phy_init_tssi2dbm_table(dev
);
3931 goto err_kfree_lo_control
;
3933 /* Enable IRQ routing to this device. */
3934 ssb_pcicore_dev_irqvecs_enable(&bus
->pcicore
, dev
->dev
);
3936 b43_imcfglo_timeouts_workaround(dev
);
3937 b43_bluetooth_coext_disable(dev
);
3938 b43_phy_early_init(dev
);
3939 err
= b43_chip_init(dev
);
3941 goto err_kfree_tssitbl
;
3942 b43_shm_write16(dev
, B43_SHM_SHARED
,
3943 B43_SHM_SH_WLCOREREV
, dev
->dev
->id
.revision
);
3944 hf
= b43_hf_read(dev
);
3945 if (phy
->type
== B43_PHYTYPE_G
) {
3949 if (sprom
->boardflags_lo
& B43_BFL_PACTRL
)
3950 hf
|= B43_HF_OFDMPABOOST
;
3951 } else if (phy
->type
== B43_PHYTYPE_B
) {
3953 if (phy
->rev
>= 2 && phy
->radio_ver
== 0x2050)
3956 b43_hf_write(dev
, hf
);
3958 b43_set_retry_limits(dev
, B43_DEFAULT_SHORT_RETRY_LIMIT
,
3959 B43_DEFAULT_LONG_RETRY_LIMIT
);
3960 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_SFFBLIM
, 3);
3961 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_LFFBLIM
, 2);
3963 /* Disable sending probe responses from firmware.
3964 * Setting the MaxTime to one usec will always trigger
3965 * a timeout, so we never send any probe resp.
3966 * A timeout of zero is infinite. */
3967 b43_shm_write16(dev
, B43_SHM_SHARED
, B43_SHM_SH_PRMAXTIME
, 1);
3969 b43_rate_memory_init(dev
);
3970 b43_set_phytxctl_defaults(dev
);
3972 /* Minimum Contention Window */
3973 if (phy
->type
== B43_PHYTYPE_B
) {
3974 b43_shm_write16(dev
, B43_SHM_SCRATCH
, B43_SHM_SC_MINCONT
, 0x1F);
3976 b43_shm_write16(dev
, B43_SHM_SCRATCH
, B43_SHM_SC_MINCONT
, 0xF);
3978 /* Maximum Contention Window */
3979 b43_shm_write16(dev
, B43_SHM_SCRATCH
, B43_SHM_SC_MAXCONT
, 0x3FF);
3981 if ((dev
->dev
->bus
->bustype
== SSB_BUSTYPE_PCMCIA
) || B43_FORCE_PIO
) {
3982 dev
->__using_pio_transfers
= 1;
3983 err
= b43_pio_init(dev
);
3985 dev
->__using_pio_transfers
= 0;
3986 err
= b43_dma_init(dev
);
3991 b43_set_synth_pu_delay(dev
, 1);
3992 b43_bluetooth_coext_enable(dev
);
3994 ssb_bus_powerup(bus
, 1); /* Enable dynamic PCTL */
3995 b43_upload_card_macaddress(dev
);
3996 b43_security_init(dev
);
3997 if (!dev
->suspend_in_progress
)
4000 b43_set_status(dev
, B43_STAT_INITIALIZED
);
4002 if (!dev
->suspend_in_progress
)
4010 if (phy
->dyn_tssi_tbl
)
4011 kfree(phy
->tssi2dbm
);
4012 err_kfree_lo_control
:
4013 kfree(phy
->lo_control
);
4014 phy
->lo_control
= NULL
;
4016 ssb_bus_may_powerdown(bus
);
4017 B43_WARN_ON(b43_status(dev
) != B43_STAT_UNINIT
);
4021 static int b43_op_add_interface(struct ieee80211_hw
*hw
,
4022 struct ieee80211_if_init_conf
*conf
)
4024 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
4025 struct b43_wldev
*dev
;
4026 unsigned long flags
;
4027 int err
= -EOPNOTSUPP
;
4029 /* TODO: allow WDS/AP devices to coexist */
4031 if (conf
->type
!= IEEE80211_IF_TYPE_AP
&&
4032 conf
->type
!= IEEE80211_IF_TYPE_STA
&&
4033 conf
->type
!= IEEE80211_IF_TYPE_WDS
&&
4034 conf
->type
!= IEEE80211_IF_TYPE_IBSS
)
4037 mutex_lock(&wl
->mutex
);
4039 goto out_mutex_unlock
;
4041 b43dbg(wl
, "Adding Interface type %d\n", conf
->type
);
4043 dev
= wl
->current_dev
;
4045 wl
->vif
= conf
->vif
;
4046 wl
->if_type
= conf
->type
;
4047 memcpy(wl
->mac_addr
, conf
->mac_addr
, ETH_ALEN
);
4049 spin_lock_irqsave(&wl
->irq_lock
, flags
);
4050 b43_adjust_opmode(dev
);
4051 b43_set_pretbtt(dev
);
4052 b43_set_synth_pu_delay(dev
, 0);
4053 b43_upload_card_macaddress(dev
);
4054 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
4058 mutex_unlock(&wl
->mutex
);
4063 static void b43_op_remove_interface(struct ieee80211_hw
*hw
,
4064 struct ieee80211_if_init_conf
*conf
)
4066 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
4067 struct b43_wldev
*dev
= wl
->current_dev
;
4068 unsigned long flags
;
4070 b43dbg(wl
, "Removing Interface type %d\n", conf
->type
);
4072 mutex_lock(&wl
->mutex
);
4074 B43_WARN_ON(!wl
->operating
);
4075 B43_WARN_ON(wl
->vif
!= conf
->vif
);
4080 spin_lock_irqsave(&wl
->irq_lock
, flags
);
4081 b43_adjust_opmode(dev
);
4082 memset(wl
->mac_addr
, 0, ETH_ALEN
);
4083 b43_upload_card_macaddress(dev
);
4084 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
4086 mutex_unlock(&wl
->mutex
);
4089 static int b43_op_start(struct ieee80211_hw
*hw
)
4091 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
4092 struct b43_wldev
*dev
= wl
->current_dev
;
4095 bool do_rfkill_exit
= 0;
4097 /* Kill all old instance specific information to make sure
4098 * the card won't use it in the short timeframe between start
4099 * and mac80211 reconfiguring it. */
4100 memset(wl
->bssid
, 0, ETH_ALEN
);
4101 memset(wl
->mac_addr
, 0, ETH_ALEN
);
4102 wl
->filter_flags
= 0;
4103 wl
->radiotap_enabled
= 0;
4106 /* First register RFkill.
4107 * LEDs that are registered later depend on it. */
4108 b43_rfkill_init(dev
);
4110 mutex_lock(&wl
->mutex
);
4112 if (b43_status(dev
) < B43_STAT_INITIALIZED
) {
4113 err
= b43_wireless_core_init(dev
);
4116 goto out_mutex_unlock
;
4121 if (b43_status(dev
) < B43_STAT_STARTED
) {
4122 err
= b43_wireless_core_start(dev
);
4125 b43_wireless_core_exit(dev
);
4127 goto out_mutex_unlock
;
4132 mutex_unlock(&wl
->mutex
);
4135 b43_rfkill_exit(dev
);
4140 static void b43_op_stop(struct ieee80211_hw
*hw
)
4142 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
4143 struct b43_wldev
*dev
= wl
->current_dev
;
4145 b43_rfkill_exit(dev
);
4146 cancel_work_sync(&(wl
->qos_update_work
));
4147 cancel_work_sync(&(wl
->beacon_update_trigger
));
4149 mutex_lock(&wl
->mutex
);
4150 if (b43_status(dev
) >= B43_STAT_STARTED
)
4151 b43_wireless_core_stop(dev
);
4152 b43_wireless_core_exit(dev
);
4153 mutex_unlock(&wl
->mutex
);
4156 static int b43_op_set_retry_limit(struct ieee80211_hw
*hw
,
4157 u32 short_retry_limit
, u32 long_retry_limit
)
4159 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
4160 struct b43_wldev
*dev
;
4163 mutex_lock(&wl
->mutex
);
4164 dev
= wl
->current_dev
;
4165 if (unlikely(!dev
|| (b43_status(dev
) < B43_STAT_INITIALIZED
))) {
4169 b43_set_retry_limits(dev
, short_retry_limit
, long_retry_limit
);
4171 mutex_unlock(&wl
->mutex
);
4176 static int b43_op_beacon_set_tim(struct ieee80211_hw
*hw
, int aid
, int set
)
4178 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
4179 struct sk_buff
*beacon
;
4180 unsigned long flags
;
4182 /* We could modify the existing beacon and set the aid bit in
4183 * the TIM field, but that would probably require resizing and
4184 * moving of data within the beacon template.
4185 * Simply request a new beacon and let mac80211 do the hard work. */
4186 beacon
= ieee80211_beacon_get(hw
, wl
->vif
);
4187 if (unlikely(!beacon
))
4189 spin_lock_irqsave(&wl
->irq_lock
, flags
);
4190 b43_update_templates(wl
, beacon
);
4191 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
4196 static int b43_op_ibss_beacon_update(struct ieee80211_hw
*hw
,
4197 struct sk_buff
*beacon
)
4199 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
4200 unsigned long flags
;
4202 spin_lock_irqsave(&wl
->irq_lock
, flags
);
4203 b43_update_templates(wl
, beacon
);
4204 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
4209 static void b43_op_sta_notify(struct ieee80211_hw
*hw
,
4210 struct ieee80211_vif
*vif
,
4211 enum sta_notify_cmd notify_cmd
,
4214 struct b43_wl
*wl
= hw_to_b43_wl(hw
);
4216 B43_WARN_ON(!vif
|| wl
->vif
!= vif
);
4219 static const struct ieee80211_ops b43_hw_ops
= {
4221 .conf_tx
= b43_op_conf_tx
,
4222 .add_interface
= b43_op_add_interface
,
4223 .remove_interface
= b43_op_remove_interface
,
4224 .config
= b43_op_config
,
4225 .config_interface
= b43_op_config_interface
,
4226 .configure_filter
= b43_op_configure_filter
,
4227 .set_key
= b43_op_set_key
,
4228 .get_stats
= b43_op_get_stats
,
4229 .get_tx_stats
= b43_op_get_tx_stats
,
4230 .start
= b43_op_start
,
4231 .stop
= b43_op_stop
,
4232 .set_retry_limit
= b43_op_set_retry_limit
,
4233 .set_tim
= b43_op_beacon_set_tim
,
4234 .beacon_update
= b43_op_ibss_beacon_update
,
4235 .sta_notify
= b43_op_sta_notify
,
4238 /* Hard-reset the chip. Do not call this directly.
4239 * Use b43_controller_restart()
4241 static void b43_chip_reset(struct work_struct
*work
)
4243 struct b43_wldev
*dev
=
4244 container_of(work
, struct b43_wldev
, restart_work
);
4245 struct b43_wl
*wl
= dev
->wl
;
4249 mutex_lock(&wl
->mutex
);
4251 prev_status
= b43_status(dev
);
4252 /* Bring the device down... */
4253 if (prev_status
>= B43_STAT_STARTED
)
4254 b43_wireless_core_stop(dev
);
4255 if (prev_status
>= B43_STAT_INITIALIZED
)
4256 b43_wireless_core_exit(dev
);
4258 /* ...and up again. */
4259 if (prev_status
>= B43_STAT_INITIALIZED
) {
4260 err
= b43_wireless_core_init(dev
);
4264 if (prev_status
>= B43_STAT_STARTED
) {
4265 err
= b43_wireless_core_start(dev
);
4267 b43_wireless_core_exit(dev
);
4272 mutex_unlock(&wl
->mutex
);
4274 b43err(wl
, "Controller restart FAILED\n");
4276 b43info(wl
, "Controller restarted\n");
4279 static int b43_setup_bands(struct b43_wldev
*dev
,
4280 bool have_2ghz_phy
, bool have_5ghz_phy
)
4282 struct ieee80211_hw
*hw
= dev
->wl
->hw
;
4285 hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] = &b43_band_2GHz
;
4286 if (dev
->phy
.type
== B43_PHYTYPE_N
) {
4288 hw
->wiphy
->bands
[IEEE80211_BAND_5GHZ
] = &b43_band_5GHz_nphy
;
4291 hw
->wiphy
->bands
[IEEE80211_BAND_5GHZ
] = &b43_band_5GHz_aphy
;
4294 dev
->phy
.supports_2ghz
= have_2ghz_phy
;
4295 dev
->phy
.supports_5ghz
= have_5ghz_phy
;
4300 static void b43_wireless_core_detach(struct b43_wldev
*dev
)
4302 /* We release firmware that late to not be required to re-request
4303 * is all the time when we reinit the core. */
4304 b43_release_firmware(dev
);
4307 static int b43_wireless_core_attach(struct b43_wldev
*dev
)
4309 struct b43_wl
*wl
= dev
->wl
;
4310 struct ssb_bus
*bus
= dev
->dev
->bus
;
4311 struct pci_dev
*pdev
= bus
->host_pci
;
4313 bool have_2ghz_phy
= 0, have_5ghz_phy
= 0;
4316 /* Do NOT do any device initialization here.
4317 * Do it in wireless_core_init() instead.
4318 * This function is for gathering basic information about the HW, only.
4319 * Also some structs may be set up here. But most likely you want to have
4320 * that in core_init(), too.
4323 err
= ssb_bus_powerup(bus
, 0);
4325 b43err(wl
, "Bus powerup failed\n");
4328 /* Get the PHY type. */
4329 if (dev
->dev
->id
.revision
>= 5) {
4332 tmshigh
= ssb_read32(dev
->dev
, SSB_TMSHIGH
);
4333 have_2ghz_phy
= !!(tmshigh
& B43_TMSHIGH_HAVE_2GHZ_PHY
);
4334 have_5ghz_phy
= !!(tmshigh
& B43_TMSHIGH_HAVE_5GHZ_PHY
);
4338 dev
->phy
.gmode
= have_2ghz_phy
;
4339 tmp
= dev
->phy
.gmode
? B43_TMSLOW_GMODE
: 0;
4340 b43_wireless_core_reset(dev
, tmp
);
4342 err
= b43_phy_versioning(dev
);
4345 /* Check if this device supports multiband. */
4347 (pdev
->device
!= 0x4312 &&
4348 pdev
->device
!= 0x4319 && pdev
->device
!= 0x4324)) {
4349 /* No multiband support. */
4352 switch (dev
->phy
.type
) {
4364 if (dev
->phy
.type
== B43_PHYTYPE_A
) {
4366 b43err(wl
, "IEEE 802.11a devices are unsupported\n");
4370 if (1 /* disable A-PHY */) {
4371 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
4372 if (dev
->phy
.type
!= B43_PHYTYPE_N
) {
4378 dev
->phy
.gmode
= have_2ghz_phy
;
4379 tmp
= dev
->phy
.gmode
? B43_TMSLOW_GMODE
: 0;
4380 b43_wireless_core_reset(dev
, tmp
);
4382 err
= b43_validate_chipaccess(dev
);
4385 err
= b43_setup_bands(dev
, have_2ghz_phy
, have_5ghz_phy
);
4389 /* Now set some default "current_dev" */
4390 if (!wl
->current_dev
)
4391 wl
->current_dev
= dev
;
4392 INIT_WORK(&dev
->restart_work
, b43_chip_reset
);
4394 b43_radio_turn_off(dev
, 1);
4395 b43_switch_analog(dev
, 0);
4396 ssb_device_disable(dev
->dev
, 0);
4397 ssb_bus_may_powerdown(bus
);
4403 ssb_bus_may_powerdown(bus
);
4407 static void b43_one_core_detach(struct ssb_device
*dev
)
4409 struct b43_wldev
*wldev
;
4412 wldev
= ssb_get_drvdata(dev
);
4414 cancel_work_sync(&wldev
->restart_work
);
4415 b43_debugfs_remove_device(wldev
);
4416 b43_wireless_core_detach(wldev
);
4417 list_del(&wldev
->list
);
4419 ssb_set_drvdata(dev
, NULL
);
4423 static int b43_one_core_attach(struct ssb_device
*dev
, struct b43_wl
*wl
)
4425 struct b43_wldev
*wldev
;
4426 struct pci_dev
*pdev
;
4429 if (!list_empty(&wl
->devlist
)) {
4430 /* We are not the first core on this chip. */
4431 pdev
= dev
->bus
->host_pci
;
4432 /* Only special chips support more than one wireless
4433 * core, although some of the other chips have more than
4434 * one wireless core as well. Check for this and
4438 ((pdev
->device
!= 0x4321) &&
4439 (pdev
->device
!= 0x4313) && (pdev
->device
!= 0x431A))) {
4440 b43dbg(wl
, "Ignoring unconnected 802.11 core\n");
4445 wldev
= kzalloc(sizeof(*wldev
), GFP_KERNEL
);
4451 b43_set_status(wldev
, B43_STAT_UNINIT
);
4452 wldev
->bad_frames_preempt
= modparam_bad_frames_preempt
;
4453 tasklet_init(&wldev
->isr_tasklet
,
4454 (void (*)(unsigned long))b43_interrupt_tasklet
,
4455 (unsigned long)wldev
);
4456 INIT_LIST_HEAD(&wldev
->list
);
4458 err
= b43_wireless_core_attach(wldev
);
4460 goto err_kfree_wldev
;
4462 list_add(&wldev
->list
, &wl
->devlist
);
4464 ssb_set_drvdata(dev
, wldev
);
4465 b43_debugfs_add_device(wldev
);
4475 #define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
4476 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
4477 (pdev->device == _device) && \
4478 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
4479 (pdev->subsystem_device == _subdevice) )
4481 static void b43_sprom_fixup(struct ssb_bus
*bus
)
4483 struct pci_dev
*pdev
;
4485 /* boardflags workarounds */
4486 if (bus
->boardinfo
.vendor
== SSB_BOARDVENDOR_DELL
&&
4487 bus
->chip_id
== 0x4301 && bus
->boardinfo
.rev
== 0x74)
4488 bus
->sprom
.boardflags_lo
|= B43_BFL_BTCOEXIST
;
4489 if (bus
->boardinfo
.vendor
== PCI_VENDOR_ID_APPLE
&&
4490 bus
->boardinfo
.type
== 0x4E && bus
->boardinfo
.rev
> 0x40)
4491 bus
->sprom
.boardflags_lo
|= B43_BFL_PACTRL
;
4492 if (bus
->bustype
== SSB_BUSTYPE_PCI
) {
4493 pdev
= bus
->host_pci
;
4494 if (IS_PDEV(pdev
, BROADCOM
, 0x4318, ASUSTEK
, 0x100F) ||
4495 IS_PDEV(pdev
, BROADCOM
, 0x4320, LINKSYS
, 0x0015) ||
4496 IS_PDEV(pdev
, BROADCOM
, 0x4320, LINKSYS
, 0x0013))
4497 bus
->sprom
.boardflags_lo
&= ~B43_BFL_BTCOEXIST
;
4501 static void b43_wireless_exit(struct ssb_device
*dev
, struct b43_wl
*wl
)
4503 struct ieee80211_hw
*hw
= wl
->hw
;
4505 ssb_set_devtypedata(dev
, NULL
);
4506 ieee80211_free_hw(hw
);
4509 static int b43_wireless_init(struct ssb_device
*dev
)
4511 struct ssb_sprom
*sprom
= &dev
->bus
->sprom
;
4512 struct ieee80211_hw
*hw
;
4516 b43_sprom_fixup(dev
->bus
);
4518 hw
= ieee80211_alloc_hw(sizeof(*wl
), &b43_hw_ops
);
4520 b43err(NULL
, "Could not allocate ieee80211 device\n");
4525 hw
->flags
= IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE
|
4526 IEEE80211_HW_RX_INCLUDES_FCS
|
4527 IEEE80211_HW_SIGNAL_DBM
|
4528 IEEE80211_HW_NOISE_DBM
;
4530 hw
->queues
= b43_modparam_qos
? 4 : 1;
4531 SET_IEEE80211_DEV(hw
, dev
->dev
);
4532 if (is_valid_ether_addr(sprom
->et1mac
))
4533 SET_IEEE80211_PERM_ADDR(hw
, sprom
->et1mac
);
4535 SET_IEEE80211_PERM_ADDR(hw
, sprom
->il0mac
);
4537 /* Get and initialize struct b43_wl */
4538 wl
= hw_to_b43_wl(hw
);
4539 memset(wl
, 0, sizeof(*wl
));
4541 spin_lock_init(&wl
->irq_lock
);
4542 rwlock_init(&wl
->tx_lock
);
4543 spin_lock_init(&wl
->leds_lock
);
4544 spin_lock_init(&wl
->shm_lock
);
4545 mutex_init(&wl
->mutex
);
4546 INIT_LIST_HEAD(&wl
->devlist
);
4547 INIT_WORK(&wl
->qos_update_work
, b43_qos_update_work
);
4548 INIT_WORK(&wl
->beacon_update_trigger
, b43_beacon_update_trigger_work
);
4550 ssb_set_devtypedata(dev
, wl
);
4551 b43info(wl
, "Broadcom %04X WLAN found\n", dev
->bus
->chip_id
);
4557 static int b43_probe(struct ssb_device
*dev
, const struct ssb_device_id
*id
)
4563 wl
= ssb_get_devtypedata(dev
);
4565 /* Probing the first core. Must setup common struct b43_wl */
4567 err
= b43_wireless_init(dev
);
4570 wl
= ssb_get_devtypedata(dev
);
4573 err
= b43_one_core_attach(dev
, wl
);
4575 goto err_wireless_exit
;
4578 err
= ieee80211_register_hw(wl
->hw
);
4580 goto err_one_core_detach
;
4586 err_one_core_detach
:
4587 b43_one_core_detach(dev
);
4590 b43_wireless_exit(dev
, wl
);
4594 static void b43_remove(struct ssb_device
*dev
)
4596 struct b43_wl
*wl
= ssb_get_devtypedata(dev
);
4597 struct b43_wldev
*wldev
= ssb_get_drvdata(dev
);
4600 if (wl
->current_dev
== wldev
)
4601 ieee80211_unregister_hw(wl
->hw
);
4603 b43_one_core_detach(dev
);
4605 if (list_empty(&wl
->devlist
)) {
4606 /* Last core on the chip unregistered.
4607 * We can destroy common struct b43_wl.
4609 b43_wireless_exit(dev
, wl
);
4613 /* Perform a hardware reset. This can be called from any context. */
4614 void b43_controller_restart(struct b43_wldev
*dev
, const char *reason
)
4616 /* Must avoid requeueing, if we are in shutdown. */
4617 if (b43_status(dev
) < B43_STAT_INITIALIZED
)
4619 b43info(dev
->wl
, "Controller RESET (%s) ...\n", reason
);
4620 queue_work(dev
->wl
->hw
->workqueue
, &dev
->restart_work
);
4625 static int b43_suspend(struct ssb_device
*dev
, pm_message_t state
)
4627 struct b43_wldev
*wldev
= ssb_get_drvdata(dev
);
4628 struct b43_wl
*wl
= wldev
->wl
;
4630 b43dbg(wl
, "Suspending...\n");
4632 mutex_lock(&wl
->mutex
);
4633 wldev
->suspend_in_progress
= true;
4634 wldev
->suspend_init_status
= b43_status(wldev
);
4635 if (wldev
->suspend_init_status
>= B43_STAT_STARTED
)
4636 b43_wireless_core_stop(wldev
);
4637 if (wldev
->suspend_init_status
>= B43_STAT_INITIALIZED
)
4638 b43_wireless_core_exit(wldev
);
4639 mutex_unlock(&wl
->mutex
);
4641 b43dbg(wl
, "Device suspended.\n");
4646 static int b43_resume(struct ssb_device
*dev
)
4648 struct b43_wldev
*wldev
= ssb_get_drvdata(dev
);
4649 struct b43_wl
*wl
= wldev
->wl
;
4652 b43dbg(wl
, "Resuming...\n");
4654 mutex_lock(&wl
->mutex
);
4655 if (wldev
->suspend_init_status
>= B43_STAT_INITIALIZED
) {
4656 err
= b43_wireless_core_init(wldev
);
4658 b43err(wl
, "Resume failed at core init\n");
4662 if (wldev
->suspend_init_status
>= B43_STAT_STARTED
) {
4663 err
= b43_wireless_core_start(wldev
);
4665 b43_leds_exit(wldev
);
4666 b43_rng_exit(wldev
->wl
);
4667 b43_wireless_core_exit(wldev
);
4668 b43err(wl
, "Resume failed at core start\n");
4672 b43dbg(wl
, "Device resumed.\n");
4674 wldev
->suspend_in_progress
= false;
4675 mutex_unlock(&wl
->mutex
);
4679 #else /* CONFIG_PM */
4680 # define b43_suspend NULL
4681 # define b43_resume NULL
4682 #endif /* CONFIG_PM */
4684 static struct ssb_driver b43_ssb_driver
= {
4685 .name
= KBUILD_MODNAME
,
4686 .id_table
= b43_ssb_tbl
,
4688 .remove
= b43_remove
,
4689 .suspend
= b43_suspend
,
4690 .resume
= b43_resume
,
4693 static void b43_print_driverinfo(void)
4695 const char *feat_pci
= "", *feat_pcmcia
= "", *feat_nphy
= "",
4696 *feat_leds
= "", *feat_rfkill
= "";
4698 #ifdef CONFIG_B43_PCI_AUTOSELECT
4701 #ifdef CONFIG_B43_PCMCIA
4704 #ifdef CONFIG_B43_NPHY
4707 #ifdef CONFIG_B43_LEDS
4710 #ifdef CONFIG_B43_RFKILL
4713 printk(KERN_INFO
"Broadcom 43xx driver loaded "
4714 "[ Features: %s%s%s%s%s, Firmware-ID: "
4715 B43_SUPPORTED_FIRMWARE_ID
" ]\n",
4716 feat_pci
, feat_pcmcia
, feat_nphy
,
4717 feat_leds
, feat_rfkill
);
4720 static int __init
b43_init(void)
4725 err
= b43_pcmcia_init();
4728 err
= ssb_driver_register(&b43_ssb_driver
);
4730 goto err_pcmcia_exit
;
4731 b43_print_driverinfo();
4742 static void __exit
b43_exit(void)
4744 ssb_driver_unregister(&b43_ssb_driver
);
4749 module_init(b43_init
)
4750 module_exit(b43_exit
)