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brcmsmac: Use IEEE 802.11 AC levels for pktq precedence levels
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1 /*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
19 #include <linux/pci_ids.h>
20 #include <linux/if_ether.h>
21 #include <net/cfg80211.h>
22 #include <net/mac80211.h>
23 #include <brcm_hw_ids.h>
24 #include <aiutils.h>
25 #include <chipcommon.h>
26 #include "rate.h"
27 #include "scb.h"
28 #include "phy/phy_hal.h"
29 #include "channel.h"
30 #include "antsel.h"
31 #include "stf.h"
32 #include "ampdu.h"
33 #include "mac80211_if.h"
34 #include "ucode_loader.h"
35 #include "main.h"
36 #include "soc.h"
37
38 /* watchdog timer, in unit of ms */
39 #define TIMER_INTERVAL_WATCHDOG 1000
40 /* radio monitor timer, in unit of ms */
41 #define TIMER_INTERVAL_RADIOCHK 800
42
43 /* beacon interval, in unit of 1024TU */
44 #define BEACON_INTERVAL_DEFAULT 100
45
46 /* n-mode support capability */
47 /* 2x2 includes both 1x1 & 2x2 devices
48 * reserved #define 2 for future when we want to separate 1x1 & 2x2 and
49 * control it independently
50 */
51 #define WL_11N_2x2 1
52 #define WL_11N_3x3 3
53 #define WL_11N_4x4 4
54
55 #define EDCF_ACI_MASK 0x60
56 #define EDCF_ACI_SHIFT 5
57 #define EDCF_ECWMIN_MASK 0x0f
58 #define EDCF_ECWMAX_SHIFT 4
59 #define EDCF_AIFSN_MASK 0x0f
60 #define EDCF_AIFSN_MAX 15
61 #define EDCF_ECWMAX_MASK 0xf0
62
63 #define EDCF_AC_BE_TXOP_STA 0x0000
64 #define EDCF_AC_BK_TXOP_STA 0x0000
65 #define EDCF_AC_VO_ACI_STA 0x62
66 #define EDCF_AC_VO_ECW_STA 0x32
67 #define EDCF_AC_VI_ACI_STA 0x42
68 #define EDCF_AC_VI_ECW_STA 0x43
69 #define EDCF_AC_BK_ECW_STA 0xA4
70 #define EDCF_AC_VI_TXOP_STA 0x005e
71 #define EDCF_AC_VO_TXOP_STA 0x002f
72 #define EDCF_AC_BE_ACI_STA 0x03
73 #define EDCF_AC_BE_ECW_STA 0xA4
74 #define EDCF_AC_BK_ACI_STA 0x27
75 #define EDCF_AC_VO_TXOP_AP 0x002f
76
77 #define EDCF_TXOP2USEC(txop) ((txop) << 5)
78 #define EDCF_ECW2CW(exp) ((1 << (exp)) - 1)
79
80 #define APHY_SYMBOL_TIME 4
81 #define APHY_PREAMBLE_TIME 16
82 #define APHY_SIGNAL_TIME 4
83 #define APHY_SIFS_TIME 16
84 #define APHY_SERVICE_NBITS 16
85 #define APHY_TAIL_NBITS 6
86 #define BPHY_SIFS_TIME 10
87 #define BPHY_PLCP_SHORT_TIME 96
88
89 #define PREN_PREAMBLE 24
90 #define PREN_MM_EXT 12
91 #define PREN_PREAMBLE_EXT 4
92
93 #define DOT11_MAC_HDR_LEN 24
94 #define DOT11_ACK_LEN 10
95 #define DOT11_BA_LEN 4
96 #define DOT11_OFDM_SIGNAL_EXTENSION 6
97 #define DOT11_MIN_FRAG_LEN 256
98 #define DOT11_RTS_LEN 16
99 #define DOT11_CTS_LEN 10
100 #define DOT11_BA_BITMAP_LEN 128
101 #define DOT11_MIN_BEACON_PERIOD 1
102 #define DOT11_MAX_BEACON_PERIOD 0xFFFF
103 #define DOT11_MAXNUMFRAGS 16
104 #define DOT11_MAX_FRAG_LEN 2346
105
106 #define BPHY_PLCP_TIME 192
107 #define RIFS_11N_TIME 2
108
109 /* length of the BCN template area */
110 #define BCN_TMPL_LEN 512
111
112 /* brcms_bss_info flag bit values */
113 #define BRCMS_BSS_HT 0x0020 /* BSS is HT (MIMO) capable */
114
115 /* chip rx buffer offset */
116 #define BRCMS_HWRXOFF 38
117
118 /* rfdisable delay timer 500 ms, runs of ALP clock */
119 #define RFDISABLE_DEFAULT 10000000
120
121 #define BRCMS_TEMPSENSE_PERIOD 10 /* 10 second timeout */
122
123 /* precedences numbers for wlc queues. These are twice as may levels as
124 * 802.1D priorities.
125 * Odd numbers are used for HI priority traffic at same precedence levels
126 * These constants are used ONLY by wlc_prio2prec_map. Do not use them
127 * elsewhere.
128 */
129 #define _BRCMS_PREC_NONE 0 /* None = - */
130 #define _BRCMS_PREC_BK 2 /* BK - Background */
131 #define _BRCMS_PREC_BE 4 /* BE - Best-effort */
132 #define _BRCMS_PREC_EE 6 /* EE - Excellent-effort */
133 #define _BRCMS_PREC_CL 8 /* CL - Controlled Load */
134 #define _BRCMS_PREC_VI 10 /* Vi - Video */
135 #define _BRCMS_PREC_VO 12 /* Vo - Voice */
136 #define _BRCMS_PREC_NC 14 /* NC - Network Control */
137
138 /* synthpu_dly times in us */
139 #define SYNTHPU_DLY_APHY_US 3700
140 #define SYNTHPU_DLY_BPHY_US 1050
141 #define SYNTHPU_DLY_NPHY_US 2048
142 #define SYNTHPU_DLY_LPPHY_US 300
143
144 #define ANTCNT 10 /* vanilla M_MAX_ANTCNT val */
145
146 /* Per-AC retry limit register definitions; uses defs.h bitfield macros */
147 #define EDCF_SHORT_S 0
148 #define EDCF_SFB_S 4
149 #define EDCF_LONG_S 8
150 #define EDCF_LFB_S 12
151 #define EDCF_SHORT_M BITFIELD_MASK(4)
152 #define EDCF_SFB_M BITFIELD_MASK(4)
153 #define EDCF_LONG_M BITFIELD_MASK(4)
154 #define EDCF_LFB_M BITFIELD_MASK(4)
155
156 #define RETRY_SHORT_DEF 7 /* Default Short retry Limit */
157 #define RETRY_SHORT_MAX 255 /* Maximum Short retry Limit */
158 #define RETRY_LONG_DEF 4 /* Default Long retry count */
159 #define RETRY_SHORT_FB 3 /* Short count for fb rate */
160 #define RETRY_LONG_FB 2 /* Long count for fb rate */
161
162 #define APHY_CWMIN 15
163 #define PHY_CWMAX 1023
164
165 #define EDCF_AIFSN_MIN 1
166
167 #define FRAGNUM_MASK 0xF
168
169 #define APHY_SLOT_TIME 9
170 #define BPHY_SLOT_TIME 20
171
172 #define WL_SPURAVOID_OFF 0
173 #define WL_SPURAVOID_ON1 1
174 #define WL_SPURAVOID_ON2 2
175
176 /* invalid core flags, use the saved coreflags */
177 #define BRCMS_USE_COREFLAGS 0xffffffff
178
179 /* values for PLCPHdr_override */
180 #define BRCMS_PLCP_AUTO -1
181 #define BRCMS_PLCP_SHORT 0
182 #define BRCMS_PLCP_LONG 1
183
184 /* values for g_protection_override and n_protection_override */
185 #define BRCMS_PROTECTION_AUTO -1
186 #define BRCMS_PROTECTION_OFF 0
187 #define BRCMS_PROTECTION_ON 1
188 #define BRCMS_PROTECTION_MMHDR_ONLY 2
189 #define BRCMS_PROTECTION_CTS_ONLY 3
190
191 /* values for g_protection_control and n_protection_control */
192 #define BRCMS_PROTECTION_CTL_OFF 0
193 #define BRCMS_PROTECTION_CTL_LOCAL 1
194 #define BRCMS_PROTECTION_CTL_OVERLAP 2
195
196 /* values for n_protection */
197 #define BRCMS_N_PROTECTION_OFF 0
198 #define BRCMS_N_PROTECTION_OPTIONAL 1
199 #define BRCMS_N_PROTECTION_20IN40 2
200 #define BRCMS_N_PROTECTION_MIXEDMODE 3
201
202 /* values for band specific 40MHz capabilities */
203 #define BRCMS_N_BW_20ALL 0
204 #define BRCMS_N_BW_40ALL 1
205 #define BRCMS_N_BW_20IN2G_40IN5G 2
206
207 /* bitflags for SGI support (sgi_rx iovar) */
208 #define BRCMS_N_SGI_20 0x01
209 #define BRCMS_N_SGI_40 0x02
210
211 /* defines used by the nrate iovar */
212 /* MSC in use,indicates b0-6 holds an mcs */
213 #define NRATE_MCS_INUSE 0x00000080
214 /* rate/mcs value */
215 #define NRATE_RATE_MASK 0x0000007f
216 /* stf mode mask: siso, cdd, stbc, sdm */
217 #define NRATE_STF_MASK 0x0000ff00
218 /* stf mode shift */
219 #define NRATE_STF_SHIFT 8
220 /* bit indicate to override mcs only */
221 #define NRATE_OVERRIDE_MCS_ONLY 0x40000000
222 #define NRATE_SGI_MASK 0x00800000 /* sgi mode */
223 #define NRATE_SGI_SHIFT 23 /* sgi mode */
224 #define NRATE_LDPC_CODING 0x00400000 /* adv coding in use */
225 #define NRATE_LDPC_SHIFT 22 /* ldpc shift */
226
227 #define NRATE_STF_SISO 0 /* stf mode SISO */
228 #define NRATE_STF_CDD 1 /* stf mode CDD */
229 #define NRATE_STF_STBC 2 /* stf mode STBC */
230 #define NRATE_STF_SDM 3 /* stf mode SDM */
231
232 #define MAX_DMA_SEGS 4
233
234 /* Max # of entries in Tx FIFO based on 4kb page size */
235 #define NTXD 256
236 /* Max # of entries in Rx FIFO based on 4kb page size */
237 #define NRXD 256
238
239 /* try to keep this # rbufs posted to the chip */
240 #define NRXBUFPOST 32
241
242 /* data msg txq hiwat mark */
243 #define BRCMS_DATAHIWAT 50
244
245 /* max # frames to process in brcms_c_recv() */
246 #define RXBND 8
247 /* max # tx status to process in wlc_txstatus() */
248 #define TXSBND 8
249
250 /* brcmu_format_flags() bit description structure */
251 struct brcms_c_bit_desc {
252 u32 bit;
253 const char *name;
254 };
255
256 /*
257 * The following table lists the buffer memory allocated to xmt fifos in HW.
258 * the size is in units of 256bytes(one block), total size is HW dependent
259 * ucode has default fifo partition, sw can overwrite if necessary
260 *
261 * This is documented in twiki under the topic UcodeTxFifo. Please ensure
262 * the twiki is updated before making changes.
263 */
264
265 /* Starting corerev for the fifo size table */
266 #define XMTFIFOTBL_STARTREV 17
267
268 struct d11init {
269 __le16 addr;
270 __le16 size;
271 __le32 value;
272 };
273
274 struct edcf_acparam {
275 u8 ACI;
276 u8 ECW;
277 u16 TXOP;
278 } __packed;
279
280 /* debug/trace */
281 uint brcm_msg_level =
282 #if defined(DEBUG)
283 LOG_ERROR_VAL;
284 #else
285 0;
286 #endif /* DEBUG */
287
288 /* TX FIFO number to WME/802.1E Access Category */
289 static const u8 wme_fifo2ac[] = {
290 IEEE80211_AC_BK,
291 IEEE80211_AC_BE,
292 IEEE80211_AC_VI,
293 IEEE80211_AC_VO,
294 IEEE80211_AC_BE,
295 IEEE80211_AC_BE
296 };
297
298 /* ieee80211 Access Category to TX FIFO number */
299 static const u8 wme_ac2fifo[] = {
300 TX_AC_VO_FIFO,
301 TX_AC_VI_FIFO,
302 TX_AC_BE_FIFO,
303 TX_AC_BK_FIFO
304 };
305
306 static const u16 xmtfifo_sz[][NFIFO] = {
307 /* corerev 17: 5120, 49152, 49152, 5376, 4352, 1280 */
308 {20, 192, 192, 21, 17, 5},
309 /* corerev 18: */
310 {0, 0, 0, 0, 0, 0},
311 /* corerev 19: */
312 {0, 0, 0, 0, 0, 0},
313 /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
314 {20, 192, 192, 21, 17, 5},
315 /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
316 {9, 58, 22, 14, 14, 5},
317 /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
318 {20, 192, 192, 21, 17, 5},
319 /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
320 {20, 192, 192, 21, 17, 5},
321 /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
322 {9, 58, 22, 14, 14, 5},
323 /* corerev 25: */
324 {0, 0, 0, 0, 0, 0},
325 /* corerev 26: */
326 {0, 0, 0, 0, 0, 0},
327 /* corerev 27: */
328 {0, 0, 0, 0, 0, 0},
329 /* corerev 28: 2304, 14848, 5632, 3584, 3584, 1280 */
330 {9, 58, 22, 14, 14, 5},
331 };
332
333 #ifdef DEBUG
334 static const char * const fifo_names[] = {
335 "AC_BK", "AC_BE", "AC_VI", "AC_VO", "BCMC", "ATIM" };
336 #else
337 static const char fifo_names[6][0];
338 #endif
339
340 #ifdef DEBUG
341 /* pointer to most recently allocated wl/wlc */
342 static struct brcms_c_info *wlc_info_dbg = (struct brcms_c_info *) (NULL);
343 #endif
344
345 /* Mapping of ieee80211 AC numbers to tx fifos */
346 static const u8 ac_to_fifo_mapping[IEEE80211_NUM_ACS] = {
347 [IEEE80211_AC_VO] = TX_AC_VO_FIFO,
348 [IEEE80211_AC_VI] = TX_AC_VI_FIFO,
349 [IEEE80211_AC_BE] = TX_AC_BE_FIFO,
350 [IEEE80211_AC_BK] = TX_AC_BK_FIFO,
351 };
352
353 static u8 brcms_ac_to_fifo(u8 ac)
354 {
355 if (ac >= ARRAY_SIZE(ac_to_fifo_mapping))
356 return TX_AC_BE_FIFO;
357 return ac_to_fifo_mapping[ac];
358 }
359
360 /* Find basic rate for a given rate */
361 static u8 brcms_basic_rate(struct brcms_c_info *wlc, u32 rspec)
362 {
363 if (is_mcs_rate(rspec))
364 return wlc->band->basic_rate[mcs_table[rspec & RSPEC_RATE_MASK]
365 .leg_ofdm];
366 return wlc->band->basic_rate[rspec & RSPEC_RATE_MASK];
367 }
368
369 static u16 frametype(u32 rspec, u8 mimoframe)
370 {
371 if (is_mcs_rate(rspec))
372 return mimoframe;
373 return is_cck_rate(rspec) ? FT_CCK : FT_OFDM;
374 }
375
376 /* currently the best mechanism for determining SIFS is the band in use */
377 static u16 get_sifs(struct brcms_band *band)
378 {
379 return band->bandtype == BRCM_BAND_5G ? APHY_SIFS_TIME :
380 BPHY_SIFS_TIME;
381 }
382
383 /*
384 * Detect Card removed.
385 * Even checking an sbconfig register read will not false trigger when the core
386 * is in reset it breaks CF address mechanism. Accessing gphy phyversion will
387 * cause SB error if aphy is in reset on 4306B0-DB. Need a simple accessible
388 * reg with fixed 0/1 pattern (some platforms return all 0).
389 * If clocks are present, call the sb routine which will figure out if the
390 * device is removed.
391 */
392 static bool brcms_deviceremoved(struct brcms_c_info *wlc)
393 {
394 u32 macctrl;
395
396 if (!wlc->hw->clk)
397 return ai_deviceremoved(wlc->hw->sih);
398 macctrl = bcma_read32(wlc->hw->d11core,
399 D11REGOFFS(maccontrol));
400 return (macctrl & (MCTL_PSM_JMP_0 | MCTL_IHR_EN)) != MCTL_IHR_EN;
401 }
402
403 /* sum the individual fifo tx pending packet counts */
404 static s16 brcms_txpktpendtot(struct brcms_c_info *wlc)
405 {
406 return wlc->core->txpktpend[0] + wlc->core->txpktpend[1] +
407 wlc->core->txpktpend[2] + wlc->core->txpktpend[3];
408 }
409
410 static bool brcms_is_mband_unlocked(struct brcms_c_info *wlc)
411 {
412 return wlc->pub->_nbands > 1 && !wlc->bandlocked;
413 }
414
415 static int brcms_chspec_bw(u16 chanspec)
416 {
417 if (CHSPEC_IS40(chanspec))
418 return BRCMS_40_MHZ;
419 if (CHSPEC_IS20(chanspec))
420 return BRCMS_20_MHZ;
421
422 return BRCMS_10_MHZ;
423 }
424
425 static void brcms_c_bsscfg_mfree(struct brcms_bss_cfg *cfg)
426 {
427 if (cfg == NULL)
428 return;
429
430 kfree(cfg->current_bss);
431 kfree(cfg);
432 }
433
434 static void brcms_c_detach_mfree(struct brcms_c_info *wlc)
435 {
436 if (wlc == NULL)
437 return;
438
439 brcms_c_bsscfg_mfree(wlc->bsscfg);
440 kfree(wlc->pub);
441 kfree(wlc->modulecb);
442 kfree(wlc->default_bss);
443 kfree(wlc->protection);
444 kfree(wlc->stf);
445 kfree(wlc->bandstate[0]);
446 kfree(wlc->corestate->macstat_snapshot);
447 kfree(wlc->corestate);
448 kfree(wlc->hw->bandstate[0]);
449 kfree(wlc->hw);
450
451 /* free the wlc */
452 kfree(wlc);
453 wlc = NULL;
454 }
455
456 static struct brcms_bss_cfg *brcms_c_bsscfg_malloc(uint unit)
457 {
458 struct brcms_bss_cfg *cfg;
459
460 cfg = kzalloc(sizeof(struct brcms_bss_cfg), GFP_ATOMIC);
461 if (cfg == NULL)
462 goto fail;
463
464 cfg->current_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC);
465 if (cfg->current_bss == NULL)
466 goto fail;
467
468 return cfg;
469
470 fail:
471 brcms_c_bsscfg_mfree(cfg);
472 return NULL;
473 }
474
475 static struct brcms_c_info *
476 brcms_c_attach_malloc(uint unit, uint *err, uint devid)
477 {
478 struct brcms_c_info *wlc;
479
480 wlc = kzalloc(sizeof(struct brcms_c_info), GFP_ATOMIC);
481 if (wlc == NULL) {
482 *err = 1002;
483 goto fail;
484 }
485
486 /* allocate struct brcms_c_pub state structure */
487 wlc->pub = kzalloc(sizeof(struct brcms_pub), GFP_ATOMIC);
488 if (wlc->pub == NULL) {
489 *err = 1003;
490 goto fail;
491 }
492 wlc->pub->wlc = wlc;
493
494 /* allocate struct brcms_hardware state structure */
495
496 wlc->hw = kzalloc(sizeof(struct brcms_hardware), GFP_ATOMIC);
497 if (wlc->hw == NULL) {
498 *err = 1005;
499 goto fail;
500 }
501 wlc->hw->wlc = wlc;
502
503 wlc->hw->bandstate[0] =
504 kzalloc(sizeof(struct brcms_hw_band) * MAXBANDS, GFP_ATOMIC);
505 if (wlc->hw->bandstate[0] == NULL) {
506 *err = 1006;
507 goto fail;
508 } else {
509 int i;
510
511 for (i = 1; i < MAXBANDS; i++)
512 wlc->hw->bandstate[i] = (struct brcms_hw_band *)
513 ((unsigned long)wlc->hw->bandstate[0] +
514 (sizeof(struct brcms_hw_band) * i));
515 }
516
517 wlc->modulecb =
518 kzalloc(sizeof(struct modulecb) * BRCMS_MAXMODULES, GFP_ATOMIC);
519 if (wlc->modulecb == NULL) {
520 *err = 1009;
521 goto fail;
522 }
523
524 wlc->default_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC);
525 if (wlc->default_bss == NULL) {
526 *err = 1010;
527 goto fail;
528 }
529
530 wlc->bsscfg = brcms_c_bsscfg_malloc(unit);
531 if (wlc->bsscfg == NULL) {
532 *err = 1011;
533 goto fail;
534 }
535
536 wlc->protection = kzalloc(sizeof(struct brcms_protection),
537 GFP_ATOMIC);
538 if (wlc->protection == NULL) {
539 *err = 1016;
540 goto fail;
541 }
542
543 wlc->stf = kzalloc(sizeof(struct brcms_stf), GFP_ATOMIC);
544 if (wlc->stf == NULL) {
545 *err = 1017;
546 goto fail;
547 }
548
549 wlc->bandstate[0] =
550 kzalloc(sizeof(struct brcms_band)*MAXBANDS, GFP_ATOMIC);
551 if (wlc->bandstate[0] == NULL) {
552 *err = 1025;
553 goto fail;
554 } else {
555 int i;
556
557 for (i = 1; i < MAXBANDS; i++)
558 wlc->bandstate[i] = (struct brcms_band *)
559 ((unsigned long)wlc->bandstate[0]
560 + (sizeof(struct brcms_band)*i));
561 }
562
563 wlc->corestate = kzalloc(sizeof(struct brcms_core), GFP_ATOMIC);
564 if (wlc->corestate == NULL) {
565 *err = 1026;
566 goto fail;
567 }
568
569 wlc->corestate->macstat_snapshot =
570 kzalloc(sizeof(struct macstat), GFP_ATOMIC);
571 if (wlc->corestate->macstat_snapshot == NULL) {
572 *err = 1027;
573 goto fail;
574 }
575
576 return wlc;
577
578 fail:
579 brcms_c_detach_mfree(wlc);
580 return NULL;
581 }
582
583 /*
584 * Update the slot timing for standard 11b/g (20us slots)
585 * or shortslot 11g (9us slots)
586 * The PSM needs to be suspended for this call.
587 */
588 static void brcms_b_update_slot_timing(struct brcms_hardware *wlc_hw,
589 bool shortslot)
590 {
591 struct bcma_device *core = wlc_hw->d11core;
592
593 if (shortslot) {
594 /* 11g short slot: 11a timing */
595 bcma_write16(core, D11REGOFFS(ifs_slot), 0x0207);
596 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
597 } else {
598 /* 11g long slot: 11b timing */
599 bcma_write16(core, D11REGOFFS(ifs_slot), 0x0212);
600 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
601 }
602 }
603
604 /*
605 * calculate frame duration of a given rate and length, return
606 * time in usec unit
607 */
608 static uint brcms_c_calc_frame_time(struct brcms_c_info *wlc, u32 ratespec,
609 u8 preamble_type, uint mac_len)
610 {
611 uint nsyms, dur = 0, Ndps, kNdps;
612 uint rate = rspec2rate(ratespec);
613
614 if (rate == 0) {
615 wiphy_err(wlc->wiphy, "wl%d: WAR: using rate of 1 mbps\n",
616 wlc->pub->unit);
617 rate = BRCM_RATE_1M;
618 }
619
620 BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, preamble_type %d, len%d\n",
621 wlc->pub->unit, ratespec, preamble_type, mac_len);
622
623 if (is_mcs_rate(ratespec)) {
624 uint mcs = ratespec & RSPEC_RATE_MASK;
625 int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec);
626
627 dur = PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
628 if (preamble_type == BRCMS_MM_PREAMBLE)
629 dur += PREN_MM_EXT;
630 /* 1000Ndbps = kbps * 4 */
631 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
632 rspec_issgi(ratespec)) * 4;
633
634 if (rspec_stc(ratespec) == 0)
635 nsyms =
636 CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
637 APHY_TAIL_NBITS) * 1000, kNdps);
638 else
639 /* STBC needs to have even number of symbols */
640 nsyms =
641 2 *
642 CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
643 APHY_TAIL_NBITS) * 1000, 2 * kNdps);
644
645 dur += APHY_SYMBOL_TIME * nsyms;
646 if (wlc->band->bandtype == BRCM_BAND_2G)
647 dur += DOT11_OFDM_SIGNAL_EXTENSION;
648 } else if (is_ofdm_rate(rate)) {
649 dur = APHY_PREAMBLE_TIME;
650 dur += APHY_SIGNAL_TIME;
651 /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
652 Ndps = rate * 2;
653 /* NSyms = CEILING((SERVICE + 8*NBytes + TAIL) / Ndbps) */
654 nsyms =
655 CEIL((APHY_SERVICE_NBITS + 8 * mac_len + APHY_TAIL_NBITS),
656 Ndps);
657 dur += APHY_SYMBOL_TIME * nsyms;
658 if (wlc->band->bandtype == BRCM_BAND_2G)
659 dur += DOT11_OFDM_SIGNAL_EXTENSION;
660 } else {
661 /*
662 * calc # bits * 2 so factor of 2 in rate (1/2 mbps)
663 * will divide out
664 */
665 mac_len = mac_len * 8 * 2;
666 /* calc ceiling of bits/rate = microseconds of air time */
667 dur = (mac_len + rate - 1) / rate;
668 if (preamble_type & BRCMS_SHORT_PREAMBLE)
669 dur += BPHY_PLCP_SHORT_TIME;
670 else
671 dur += BPHY_PLCP_TIME;
672 }
673 return dur;
674 }
675
676 static void brcms_c_write_inits(struct brcms_hardware *wlc_hw,
677 const struct d11init *inits)
678 {
679 struct bcma_device *core = wlc_hw->d11core;
680 int i;
681 uint offset;
682 u16 size;
683 u32 value;
684
685 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
686
687 for (i = 0; inits[i].addr != cpu_to_le16(0xffff); i++) {
688 size = le16_to_cpu(inits[i].size);
689 offset = le16_to_cpu(inits[i].addr);
690 value = le32_to_cpu(inits[i].value);
691 if (size == 2)
692 bcma_write16(core, offset, value);
693 else if (size == 4)
694 bcma_write32(core, offset, value);
695 else
696 break;
697 }
698 }
699
700 static void brcms_c_write_mhf(struct brcms_hardware *wlc_hw, u16 *mhfs)
701 {
702 u8 idx;
703 u16 addr[] = {
704 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
705 M_HOST_FLAGS5
706 };
707
708 for (idx = 0; idx < MHFMAX; idx++)
709 brcms_b_write_shm(wlc_hw, addr[idx], mhfs[idx]);
710 }
711
712 static void brcms_c_ucode_bsinit(struct brcms_hardware *wlc_hw)
713 {
714 struct wiphy *wiphy = wlc_hw->wlc->wiphy;
715 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
716
717 /* init microcode host flags */
718 brcms_c_write_mhf(wlc_hw, wlc_hw->band->mhfs);
719
720 /* do band-specific ucode IHR, SHM, and SCR inits */
721 if (D11REV_IS(wlc_hw->corerev, 23)) {
722 if (BRCMS_ISNPHY(wlc_hw->band))
723 brcms_c_write_inits(wlc_hw, ucode->d11n0bsinitvals16);
724 else
725 wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
726 " %d\n", __func__, wlc_hw->unit,
727 wlc_hw->corerev);
728 } else {
729 if (D11REV_IS(wlc_hw->corerev, 24)) {
730 if (BRCMS_ISLCNPHY(wlc_hw->band))
731 brcms_c_write_inits(wlc_hw,
732 ucode->d11lcn0bsinitvals24);
733 else
734 wiphy_err(wiphy, "%s: wl%d: unsupported phy in"
735 " core rev %d\n", __func__,
736 wlc_hw->unit, wlc_hw->corerev);
737 } else {
738 wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n",
739 __func__, wlc_hw->unit, wlc_hw->corerev);
740 }
741 }
742 }
743
744 static void brcms_b_core_ioctl(struct brcms_hardware *wlc_hw, u32 m, u32 v)
745 {
746 struct bcma_device *core = wlc_hw->d11core;
747 u32 ioctl = bcma_aread32(core, BCMA_IOCTL) & ~m;
748
749 bcma_awrite32(core, BCMA_IOCTL, ioctl | v);
750 }
751
752 static void brcms_b_core_phy_clk(struct brcms_hardware *wlc_hw, bool clk)
753 {
754 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: clk %d\n", wlc_hw->unit, clk);
755
756 wlc_hw->phyclk = clk;
757
758 if (OFF == clk) { /* clear gmode bit, put phy into reset */
759
760 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC | SICF_GMODE),
761 (SICF_PRST | SICF_FGC));
762 udelay(1);
763 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_PRST);
764 udelay(1);
765
766 } else { /* take phy out of reset */
767
768 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_FGC);
769 udelay(1);
770 brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0);
771 udelay(1);
772
773 }
774 }
775
776 /* low-level band switch utility routine */
777 static void brcms_c_setxband(struct brcms_hardware *wlc_hw, uint bandunit)
778 {
779 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
780 bandunit);
781
782 wlc_hw->band = wlc_hw->bandstate[bandunit];
783
784 /*
785 * BMAC_NOTE:
786 * until we eliminate need for wlc->band refs in low level code
787 */
788 wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
789
790 /* set gmode core flag */
791 if (wlc_hw->sbclk && !wlc_hw->noreset) {
792 u32 gmode = 0;
793
794 if (bandunit == 0)
795 gmode = SICF_GMODE;
796
797 brcms_b_core_ioctl(wlc_hw, SICF_GMODE, gmode);
798 }
799 }
800
801 /* switch to new band but leave it inactive */
802 static u32 brcms_c_setband_inact(struct brcms_c_info *wlc, uint bandunit)
803 {
804 struct brcms_hardware *wlc_hw = wlc->hw;
805 u32 macintmask;
806 u32 macctrl;
807
808 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
809 macctrl = bcma_read32(wlc_hw->d11core,
810 D11REGOFFS(maccontrol));
811 WARN_ON((macctrl & MCTL_EN_MAC) != 0);
812
813 /* disable interrupts */
814 macintmask = brcms_intrsoff(wlc->wl);
815
816 /* radio off */
817 wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
818
819 brcms_b_core_phy_clk(wlc_hw, OFF);
820
821 brcms_c_setxband(wlc_hw, bandunit);
822
823 return macintmask;
824 }
825
826 /* process an individual struct tx_status */
827 static bool
828 brcms_c_dotxstatus(struct brcms_c_info *wlc, struct tx_status *txs)
829 {
830 struct sk_buff *p;
831 uint queue;
832 struct d11txh *txh;
833 struct scb *scb = NULL;
834 bool free_pdu;
835 int tx_rts, tx_frame_count, tx_rts_count;
836 uint totlen, supr_status;
837 bool lastframe;
838 struct ieee80211_hdr *h;
839 u16 mcl;
840 struct ieee80211_tx_info *tx_info;
841 struct ieee80211_tx_rate *txrate;
842 int i;
843
844 /* discard intermediate indications for ucode with one legitimate case:
845 * e.g. if "useRTS" is set. ucode did a successful rts/cts exchange,
846 * but the subsequent tx of DATA failed. so it will start rts/cts
847 * from the beginning (resetting the rts transmission count)
848 */
849 if (!(txs->status & TX_STATUS_AMPDU)
850 && (txs->status & TX_STATUS_INTERMEDIATE)) {
851 BCMMSG(wlc->wiphy, "INTERMEDIATE but not AMPDU\n");
852 return false;
853 }
854
855 queue = txs->frameid & TXFID_QUEUE_MASK;
856 if (queue >= NFIFO) {
857 p = NULL;
858 goto fatal;
859 }
860
861 p = dma_getnexttxp(wlc->hw->di[queue], DMA_RANGE_TRANSMITTED);
862 if (p == NULL)
863 goto fatal;
864
865 txh = (struct d11txh *) (p->data);
866 mcl = le16_to_cpu(txh->MacTxControlLow);
867
868 if (txs->phyerr) {
869 if (brcm_msg_level & LOG_ERROR_VAL) {
870 wiphy_err(wlc->wiphy, "phyerr 0x%x, rate 0x%x\n",
871 txs->phyerr, txh->MainRates);
872 brcms_c_print_txdesc(txh);
873 }
874 brcms_c_print_txstatus(txs);
875 }
876
877 if (txs->frameid != le16_to_cpu(txh->TxFrameID))
878 goto fatal;
879 tx_info = IEEE80211_SKB_CB(p);
880 h = (struct ieee80211_hdr *)((u8 *) (txh + 1) + D11_PHY_HDR_LEN);
881
882 if (tx_info->rate_driver_data[0])
883 scb = &wlc->pri_scb;
884
885 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
886 brcms_c_ampdu_dotxstatus(wlc->ampdu, scb, p, txs);
887 return false;
888 }
889
890 supr_status = txs->status & TX_STATUS_SUPR_MASK;
891 if (supr_status == TX_STATUS_SUPR_BADCH)
892 BCMMSG(wlc->wiphy,
893 "%s: Pkt tx suppressed, possibly channel %d\n",
894 __func__, CHSPEC_CHANNEL(wlc->default_bss->chanspec));
895
896 tx_rts = le16_to_cpu(txh->MacTxControlLow) & TXC_SENDRTS;
897 tx_frame_count =
898 (txs->status & TX_STATUS_FRM_RTX_MASK) >> TX_STATUS_FRM_RTX_SHIFT;
899 tx_rts_count =
900 (txs->status & TX_STATUS_RTS_RTX_MASK) >> TX_STATUS_RTS_RTX_SHIFT;
901
902 lastframe = !ieee80211_has_morefrags(h->frame_control);
903
904 if (!lastframe) {
905 wiphy_err(wlc->wiphy, "Not last frame!\n");
906 } else {
907 /*
908 * Set information to be consumed by Minstrel ht.
909 *
910 * The "fallback limit" is the number of tx attempts a given
911 * MPDU is sent at the "primary" rate. Tx attempts beyond that
912 * limit are sent at the "secondary" rate.
913 * A 'short frame' does not exceed RTS treshold.
914 */
915 u16 sfbl, /* Short Frame Rate Fallback Limit */
916 lfbl, /* Long Frame Rate Fallback Limit */
917 fbl;
918
919 if (queue < IEEE80211_NUM_ACS) {
920 sfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
921 EDCF_SFB);
922 lfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
923 EDCF_LFB);
924 } else {
925 sfbl = wlc->SFBL;
926 lfbl = wlc->LFBL;
927 }
928
929 txrate = tx_info->status.rates;
930 if (txrate[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
931 fbl = lfbl;
932 else
933 fbl = sfbl;
934
935 ieee80211_tx_info_clear_status(tx_info);
936
937 if ((tx_frame_count > fbl) && (txrate[1].idx >= 0)) {
938 /*
939 * rate selection requested a fallback rate
940 * and we used it
941 */
942 txrate[0].count = fbl;
943 txrate[1].count = tx_frame_count - fbl;
944 } else {
945 /*
946 * rate selection did not request fallback rate, or
947 * we didn't need it
948 */
949 txrate[0].count = tx_frame_count;
950 /*
951 * rc80211_minstrel.c:minstrel_tx_status() expects
952 * unused rates to be marked with idx = -1
953 */
954 txrate[1].idx = -1;
955 txrate[1].count = 0;
956 }
957
958 /* clear the rest of the rates */
959 for (i = 2; i < IEEE80211_TX_MAX_RATES; i++) {
960 txrate[i].idx = -1;
961 txrate[i].count = 0;
962 }
963
964 if (txs->status & TX_STATUS_ACK_RCV)
965 tx_info->flags |= IEEE80211_TX_STAT_ACK;
966 }
967
968 totlen = p->len;
969 free_pdu = true;
970
971 brcms_c_txfifo_complete(wlc, queue);
972
973 if (lastframe) {
974 /* remove PLCP & Broadcom tx descriptor header */
975 skb_pull(p, D11_PHY_HDR_LEN);
976 skb_pull(p, D11_TXH_LEN);
977 ieee80211_tx_status_irqsafe(wlc->pub->ieee_hw, p);
978 } else {
979 wiphy_err(wlc->wiphy, "%s: Not last frame => not calling "
980 "tx_status\n", __func__);
981 }
982
983 return false;
984
985 fatal:
986 if (p)
987 brcmu_pkt_buf_free_skb(p);
988
989 return true;
990
991 }
992
993 /* process tx completion events in BMAC
994 * Return true if more tx status need to be processed. false otherwise.
995 */
996 static bool
997 brcms_b_txstatus(struct brcms_hardware *wlc_hw, bool bound, bool *fatal)
998 {
999 bool morepending = false;
1000 struct brcms_c_info *wlc = wlc_hw->wlc;
1001 struct bcma_device *core;
1002 struct tx_status txstatus, *txs;
1003 u32 s1, s2;
1004 uint n = 0;
1005 /*
1006 * Param 'max_tx_num' indicates max. # tx status to process before
1007 * break out.
1008 */
1009 uint max_tx_num = bound ? TXSBND : -1;
1010
1011 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
1012
1013 txs = &txstatus;
1014 core = wlc_hw->d11core;
1015 *fatal = false;
1016 s1 = bcma_read32(core, D11REGOFFS(frmtxstatus));
1017 while (!(*fatal)
1018 && (s1 & TXS_V)) {
1019
1020 if (s1 == 0xffffffff) {
1021 wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n",
1022 wlc_hw->unit, __func__);
1023 return morepending;
1024 }
1025 s2 = bcma_read32(core, D11REGOFFS(frmtxstatus2));
1026
1027 txs->status = s1 & TXS_STATUS_MASK;
1028 txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
1029 txs->sequence = s2 & TXS_SEQ_MASK;
1030 txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
1031 txs->lasttxtime = 0;
1032
1033 *fatal = brcms_c_dotxstatus(wlc_hw->wlc, txs);
1034
1035 /* !give others some time to run! */
1036 if (++n >= max_tx_num)
1037 break;
1038 s1 = bcma_read32(core, D11REGOFFS(frmtxstatus));
1039 }
1040
1041 if (*fatal)
1042 return 0;
1043
1044 if (n >= max_tx_num)
1045 morepending = true;
1046
1047 if (!pktq_empty(&wlc->pkt_queue->q))
1048 brcms_c_send_q(wlc);
1049
1050 return morepending;
1051 }
1052
1053 static void brcms_c_tbtt(struct brcms_c_info *wlc)
1054 {
1055 if (!wlc->bsscfg->BSS)
1056 /*
1057 * DirFrmQ is now valid...defer setting until end
1058 * of ATIM window
1059 */
1060 wlc->qvalid |= MCMD_DIRFRMQVAL;
1061 }
1062
1063 /* set initial host flags value */
1064 static void
1065 brcms_c_mhfdef(struct brcms_c_info *wlc, u16 *mhfs, u16 mhf2_init)
1066 {
1067 struct brcms_hardware *wlc_hw = wlc->hw;
1068
1069 memset(mhfs, 0, MHFMAX * sizeof(u16));
1070
1071 mhfs[MHF2] |= mhf2_init;
1072
1073 /* prohibit use of slowclock on multifunction boards */
1074 if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1075 mhfs[MHF1] |= MHF1_FORCEFASTCLK;
1076
1077 if (BRCMS_ISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
1078 mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
1079 mhfs[MHF1] |= MHF1_IQSWAP_WAR;
1080 }
1081 }
1082
1083 static uint
1084 dmareg(uint direction, uint fifonum)
1085 {
1086 if (direction == DMA_TX)
1087 return offsetof(struct d11regs, fifo64regs[fifonum].dmaxmt);
1088 return offsetof(struct d11regs, fifo64regs[fifonum].dmarcv);
1089 }
1090
1091 static bool brcms_b_attach_dmapio(struct brcms_c_info *wlc, uint j, bool wme)
1092 {
1093 uint i;
1094 char name[8];
1095 /*
1096 * ucode host flag 2 needed for pio mode, independent of band and fifo
1097 */
1098 u16 pio_mhf2 = 0;
1099 struct brcms_hardware *wlc_hw = wlc->hw;
1100 uint unit = wlc_hw->unit;
1101 struct wiphy *wiphy = wlc->wiphy;
1102
1103 /* name and offsets for dma_attach */
1104 snprintf(name, sizeof(name), "wl%d", unit);
1105
1106 if (wlc_hw->di[0] == NULL) { /* Init FIFOs */
1107 int dma_attach_err = 0;
1108
1109 /*
1110 * FIFO 0
1111 * TX: TX_AC_BK_FIFO (TX AC Background data packets)
1112 * RX: RX_FIFO (RX data packets)
1113 */
1114 wlc_hw->di[0] = dma_attach(name, wlc_hw->sih, wlc_hw->d11core,
1115 (wme ? dmareg(DMA_TX, 0) : 0),
1116 dmareg(DMA_RX, 0),
1117 (wme ? NTXD : 0), NRXD,
1118 RXBUFSZ, -1, NRXBUFPOST,
1119 BRCMS_HWRXOFF, &brcm_msg_level);
1120 dma_attach_err |= (NULL == wlc_hw->di[0]);
1121
1122 /*
1123 * FIFO 1
1124 * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
1125 * (legacy) TX_DATA_FIFO (TX data packets)
1126 * RX: UNUSED
1127 */
1128 wlc_hw->di[1] = dma_attach(name, wlc_hw->sih, wlc_hw->d11core,
1129 dmareg(DMA_TX, 1), 0,
1130 NTXD, 0, 0, -1, 0, 0,
1131 &brcm_msg_level);
1132 dma_attach_err |= (NULL == wlc_hw->di[1]);
1133
1134 /*
1135 * FIFO 2
1136 * TX: TX_AC_VI_FIFO (TX AC Video data packets)
1137 * RX: UNUSED
1138 */
1139 wlc_hw->di[2] = dma_attach(name, wlc_hw->sih, wlc_hw->d11core,
1140 dmareg(DMA_TX, 2), 0,
1141 NTXD, 0, 0, -1, 0, 0,
1142 &brcm_msg_level);
1143 dma_attach_err |= (NULL == wlc_hw->di[2]);
1144 /*
1145 * FIFO 3
1146 * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
1147 * (legacy) TX_CTL_FIFO (TX control & mgmt packets)
1148 */
1149 wlc_hw->di[3] = dma_attach(name, wlc_hw->sih, wlc_hw->d11core,
1150 dmareg(DMA_TX, 3),
1151 0, NTXD, 0, 0, -1,
1152 0, 0, &brcm_msg_level);
1153 dma_attach_err |= (NULL == wlc_hw->di[3]);
1154 /* Cleaner to leave this as if with AP defined */
1155
1156 if (dma_attach_err) {
1157 wiphy_err(wiphy, "wl%d: wlc_attach: dma_attach failed"
1158 "\n", unit);
1159 return false;
1160 }
1161
1162 /* get pointer to dma engine tx flow control variable */
1163 for (i = 0; i < NFIFO; i++)
1164 if (wlc_hw->di[i])
1165 wlc_hw->txavail[i] =
1166 (uint *) dma_getvar(wlc_hw->di[i],
1167 "&txavail");
1168 }
1169
1170 /* initial ucode host flags */
1171 brcms_c_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
1172
1173 return true;
1174 }
1175
1176 static void brcms_b_detach_dmapio(struct brcms_hardware *wlc_hw)
1177 {
1178 uint j;
1179
1180 for (j = 0; j < NFIFO; j++) {
1181 if (wlc_hw->di[j]) {
1182 dma_detach(wlc_hw->di[j]);
1183 wlc_hw->di[j] = NULL;
1184 }
1185 }
1186 }
1187
1188 /*
1189 * Initialize brcms_c_info default values ...
1190 * may get overrides later in this function
1191 * BMAC_NOTES, move low out and resolve the dangling ones
1192 */
1193 static void brcms_b_info_init(struct brcms_hardware *wlc_hw)
1194 {
1195 struct brcms_c_info *wlc = wlc_hw->wlc;
1196
1197 /* set default sw macintmask value */
1198 wlc->defmacintmask = DEF_MACINTMASK;
1199
1200 /* various 802.11g modes */
1201 wlc_hw->shortslot = false;
1202
1203 wlc_hw->SFBL = RETRY_SHORT_FB;
1204 wlc_hw->LFBL = RETRY_LONG_FB;
1205
1206 /* default mac retry limits */
1207 wlc_hw->SRL = RETRY_SHORT_DEF;
1208 wlc_hw->LRL = RETRY_LONG_DEF;
1209 wlc_hw->chanspec = ch20mhz_chspec(1);
1210 }
1211
1212 static void brcms_b_wait_for_wake(struct brcms_hardware *wlc_hw)
1213 {
1214 /* delay before first read of ucode state */
1215 udelay(40);
1216
1217 /* wait until ucode is no longer asleep */
1218 SPINWAIT((brcms_b_read_shm(wlc_hw, M_UCODE_DBGST) ==
1219 DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
1220 }
1221
1222 /* control chip clock to save power, enable dynamic clock or force fast clock */
1223 static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, enum bcma_clkmode mode)
1224 {
1225 if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU) {
1226 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock
1227 * on backplane, but mac core will still run on ALP(not HT) when
1228 * it enters powersave mode, which means the FCA bit may not be
1229 * set. Should wakeup mac if driver wants it to run on HT.
1230 */
1231
1232 if (wlc_hw->clk) {
1233 if (mode == BCMA_CLKMODE_FAST) {
1234 bcma_set32(wlc_hw->d11core,
1235 D11REGOFFS(clk_ctl_st),
1236 CCS_FORCEHT);
1237
1238 udelay(64);
1239
1240 SPINWAIT(
1241 ((bcma_read32(wlc_hw->d11core,
1242 D11REGOFFS(clk_ctl_st)) &
1243 CCS_HTAVAIL) == 0),
1244 PMU_MAX_TRANSITION_DLY);
1245 WARN_ON(!(bcma_read32(wlc_hw->d11core,
1246 D11REGOFFS(clk_ctl_st)) &
1247 CCS_HTAVAIL));
1248 } else {
1249 if ((ai_get_pmurev(wlc_hw->sih) == 0) &&
1250 (bcma_read32(wlc_hw->d11core,
1251 D11REGOFFS(clk_ctl_st)) &
1252 (CCS_FORCEHT | CCS_HTAREQ)))
1253 SPINWAIT(
1254 ((bcma_read32(wlc_hw->d11core,
1255 offsetof(struct d11regs,
1256 clk_ctl_st)) &
1257 CCS_HTAVAIL) == 0),
1258 PMU_MAX_TRANSITION_DLY);
1259 bcma_mask32(wlc_hw->d11core,
1260 D11REGOFFS(clk_ctl_st),
1261 ~CCS_FORCEHT);
1262 }
1263 }
1264 wlc_hw->forcefastclk = (mode == BCMA_CLKMODE_FAST);
1265 } else {
1266
1267 /* old chips w/o PMU, force HT through cc,
1268 * then use FCA to verify mac is running fast clock
1269 */
1270
1271 wlc_hw->forcefastclk = ai_clkctl_cc(wlc_hw->sih, mode);
1272
1273 /* check fast clock is available (if core is not in reset) */
1274 if (wlc_hw->forcefastclk && wlc_hw->clk)
1275 WARN_ON(!(bcma_aread32(wlc_hw->d11core, BCMA_IOST) &
1276 SISF_FCLKA));
1277
1278 /*
1279 * keep the ucode wake bit on if forcefastclk is on since we
1280 * do not want ucode to put us back to slow clock when it dozes
1281 * for PM mode. Code below matches the wake override bit with
1282 * current forcefastclk state. Only setting bit in wake_override
1283 * instead of waking ucode immediately since old code had this
1284 * behavior. Older code set wlc->forcefastclk but only had the
1285 * wake happen if the wakup_ucode work (protected by an up
1286 * check) was executed just below.
1287 */
1288 if (wlc_hw->forcefastclk)
1289 mboolset(wlc_hw->wake_override,
1290 BRCMS_WAKE_OVERRIDE_FORCEFAST);
1291 else
1292 mboolclr(wlc_hw->wake_override,
1293 BRCMS_WAKE_OVERRIDE_FORCEFAST);
1294 }
1295 }
1296
1297 /* set or clear ucode host flag bits
1298 * it has an optimization for no-change write
1299 * it only writes through shared memory when the core has clock;
1300 * pre-CLK changes should use wlc_write_mhf to get around the optimization
1301 *
1302 *
1303 * bands values are: BRCM_BAND_AUTO <--- Current band only
1304 * BRCM_BAND_5G <--- 5G band only
1305 * BRCM_BAND_2G <--- 2G band only
1306 * BRCM_BAND_ALL <--- All bands
1307 */
1308 void
1309 brcms_b_mhf(struct brcms_hardware *wlc_hw, u8 idx, u16 mask, u16 val,
1310 int bands)
1311 {
1312 u16 save;
1313 u16 addr[MHFMAX] = {
1314 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1315 M_HOST_FLAGS5
1316 };
1317 struct brcms_hw_band *band;
1318
1319 if ((val & ~mask) || idx >= MHFMAX)
1320 return; /* error condition */
1321
1322 switch (bands) {
1323 /* Current band only or all bands,
1324 * then set the band to current band
1325 */
1326 case BRCM_BAND_AUTO:
1327 case BRCM_BAND_ALL:
1328 band = wlc_hw->band;
1329 break;
1330 case BRCM_BAND_5G:
1331 band = wlc_hw->bandstate[BAND_5G_INDEX];
1332 break;
1333 case BRCM_BAND_2G:
1334 band = wlc_hw->bandstate[BAND_2G_INDEX];
1335 break;
1336 default:
1337 band = NULL; /* error condition */
1338 }
1339
1340 if (band) {
1341 save = band->mhfs[idx];
1342 band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
1343
1344 /* optimization: only write through if changed, and
1345 * changed band is the current band
1346 */
1347 if (wlc_hw->clk && (band->mhfs[idx] != save)
1348 && (band == wlc_hw->band))
1349 brcms_b_write_shm(wlc_hw, addr[idx],
1350 (u16) band->mhfs[idx]);
1351 }
1352
1353 if (bands == BRCM_BAND_ALL) {
1354 wlc_hw->bandstate[0]->mhfs[idx] =
1355 (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
1356 wlc_hw->bandstate[1]->mhfs[idx] =
1357 (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
1358 }
1359 }
1360
1361 /* set the maccontrol register to desired reset state and
1362 * initialize the sw cache of the register
1363 */
1364 static void brcms_c_mctrl_reset(struct brcms_hardware *wlc_hw)
1365 {
1366 /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1367 wlc_hw->maccontrol = 0;
1368 wlc_hw->suspended_fifos = 0;
1369 wlc_hw->wake_override = 0;
1370 wlc_hw->mute_override = 0;
1371 brcms_b_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
1372 }
1373
1374 /*
1375 * write the software state of maccontrol and
1376 * overrides to the maccontrol register
1377 */
1378 static void brcms_c_mctrl_write(struct brcms_hardware *wlc_hw)
1379 {
1380 u32 maccontrol = wlc_hw->maccontrol;
1381
1382 /* OR in the wake bit if overridden */
1383 if (wlc_hw->wake_override)
1384 maccontrol |= MCTL_WAKE;
1385
1386 /* set AP and INFRA bits for mute if needed */
1387 if (wlc_hw->mute_override) {
1388 maccontrol &= ~(MCTL_AP);
1389 maccontrol |= MCTL_INFRA;
1390 }
1391
1392 bcma_write32(wlc_hw->d11core, D11REGOFFS(maccontrol),
1393 maccontrol);
1394 }
1395
1396 /* set or clear maccontrol bits */
1397 void brcms_b_mctrl(struct brcms_hardware *wlc_hw, u32 mask, u32 val)
1398 {
1399 u32 maccontrol;
1400 u32 new_maccontrol;
1401
1402 if (val & ~mask)
1403 return; /* error condition */
1404 maccontrol = wlc_hw->maccontrol;
1405 new_maccontrol = (maccontrol & ~mask) | val;
1406
1407 /* if the new maccontrol value is the same as the old, nothing to do */
1408 if (new_maccontrol == maccontrol)
1409 return;
1410
1411 /* something changed, cache the new value */
1412 wlc_hw->maccontrol = new_maccontrol;
1413
1414 /* write the new values with overrides applied */
1415 brcms_c_mctrl_write(wlc_hw);
1416 }
1417
1418 void brcms_c_ucode_wake_override_set(struct brcms_hardware *wlc_hw,
1419 u32 override_bit)
1420 {
1421 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
1422 mboolset(wlc_hw->wake_override, override_bit);
1423 return;
1424 }
1425
1426 mboolset(wlc_hw->wake_override, override_bit);
1427
1428 brcms_c_mctrl_write(wlc_hw);
1429 brcms_b_wait_for_wake(wlc_hw);
1430 }
1431
1432 void brcms_c_ucode_wake_override_clear(struct brcms_hardware *wlc_hw,
1433 u32 override_bit)
1434 {
1435 mboolclr(wlc_hw->wake_override, override_bit);
1436
1437 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
1438 return;
1439
1440 brcms_c_mctrl_write(wlc_hw);
1441 }
1442
1443 /* When driver needs ucode to stop beaconing, it has to make sure that
1444 * MCTL_AP is clear and MCTL_INFRA is set
1445 * Mode MCTL_AP MCTL_INFRA
1446 * AP 1 1
1447 * STA 0 1 <--- This will ensure no beacons
1448 * IBSS 0 0
1449 */
1450 static void brcms_c_ucode_mute_override_set(struct brcms_hardware *wlc_hw)
1451 {
1452 wlc_hw->mute_override = 1;
1453
1454 /* if maccontrol already has AP == 0 and INFRA == 1 without this
1455 * override, then there is no change to write
1456 */
1457 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1458 return;
1459
1460 brcms_c_mctrl_write(wlc_hw);
1461 }
1462
1463 /* Clear the override on AP and INFRA bits */
1464 static void brcms_c_ucode_mute_override_clear(struct brcms_hardware *wlc_hw)
1465 {
1466 if (wlc_hw->mute_override == 0)
1467 return;
1468
1469 wlc_hw->mute_override = 0;
1470
1471 /* if maccontrol already has AP == 0 and INFRA == 1 without this
1472 * override, then there is no change to write
1473 */
1474 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1475 return;
1476
1477 brcms_c_mctrl_write(wlc_hw);
1478 }
1479
1480 /*
1481 * Write a MAC address to the given match reg offset in the RXE match engine.
1482 */
1483 static void
1484 brcms_b_set_addrmatch(struct brcms_hardware *wlc_hw, int match_reg_offset,
1485 const u8 *addr)
1486 {
1487 struct bcma_device *core = wlc_hw->d11core;
1488 u16 mac_l;
1489 u16 mac_m;
1490 u16 mac_h;
1491
1492 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: brcms_b_set_addrmatch\n",
1493 wlc_hw->unit);
1494
1495 mac_l = addr[0] | (addr[1] << 8);
1496 mac_m = addr[2] | (addr[3] << 8);
1497 mac_h = addr[4] | (addr[5] << 8);
1498
1499 /* enter the MAC addr into the RXE match registers */
1500 bcma_write16(core, D11REGOFFS(rcm_ctl),
1501 RCM_INC_DATA | match_reg_offset);
1502 bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_l);
1503 bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_m);
1504 bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_h);
1505 }
1506
1507 void
1508 brcms_b_write_template_ram(struct brcms_hardware *wlc_hw, int offset, int len,
1509 void *buf)
1510 {
1511 struct bcma_device *core = wlc_hw->d11core;
1512 u32 word;
1513 __le32 word_le;
1514 __be32 word_be;
1515 bool be_bit;
1516 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1517
1518 bcma_write32(core, D11REGOFFS(tplatewrptr), offset);
1519
1520 /* if MCTL_BIGEND bit set in mac control register,
1521 * the chip swaps data in fifo, as well as data in
1522 * template ram
1523 */
1524 be_bit = (bcma_read32(core, D11REGOFFS(maccontrol)) & MCTL_BIGEND) != 0;
1525
1526 while (len > 0) {
1527 memcpy(&word, buf, sizeof(u32));
1528
1529 if (be_bit) {
1530 word_be = cpu_to_be32(word);
1531 word = *(u32 *)&word_be;
1532 } else {
1533 word_le = cpu_to_le32(word);
1534 word = *(u32 *)&word_le;
1535 }
1536
1537 bcma_write32(core, D11REGOFFS(tplatewrdata), word);
1538
1539 buf = (u8 *) buf + sizeof(u32);
1540 len -= sizeof(u32);
1541 }
1542 }
1543
1544 static void brcms_b_set_cwmin(struct brcms_hardware *wlc_hw, u16 newmin)
1545 {
1546 wlc_hw->band->CWmin = newmin;
1547
1548 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
1549 OBJADDR_SCR_SEL | S_DOT11_CWMIN);
1550 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
1551 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmin);
1552 }
1553
1554 static void brcms_b_set_cwmax(struct brcms_hardware *wlc_hw, u16 newmax)
1555 {
1556 wlc_hw->band->CWmax = newmax;
1557
1558 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
1559 OBJADDR_SCR_SEL | S_DOT11_CWMAX);
1560 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
1561 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmax);
1562 }
1563
1564 void brcms_b_bw_set(struct brcms_hardware *wlc_hw, u16 bw)
1565 {
1566 bool fastclk;
1567
1568 /* request FAST clock if not on */
1569 fastclk = wlc_hw->forcefastclk;
1570 if (!fastclk)
1571 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
1572
1573 wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1574
1575 brcms_b_phy_reset(wlc_hw);
1576 wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
1577
1578 /* restore the clk */
1579 if (!fastclk)
1580 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
1581 }
1582
1583 static void brcms_b_upd_synthpu(struct brcms_hardware *wlc_hw)
1584 {
1585 u16 v;
1586 struct brcms_c_info *wlc = wlc_hw->wlc;
1587 /* update SYNTHPU_DLY */
1588
1589 if (BRCMS_ISLCNPHY(wlc->band))
1590 v = SYNTHPU_DLY_LPPHY_US;
1591 else if (BRCMS_ISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3)))
1592 v = SYNTHPU_DLY_NPHY_US;
1593 else
1594 v = SYNTHPU_DLY_BPHY_US;
1595
1596 brcms_b_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
1597 }
1598
1599 static void brcms_c_ucode_txant_set(struct brcms_hardware *wlc_hw)
1600 {
1601 u16 phyctl;
1602 u16 phytxant = wlc_hw->bmac_phytxant;
1603 u16 mask = PHY_TXC_ANT_MASK;
1604
1605 /* set the Probe Response frame phy control word */
1606 phyctl = brcms_b_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
1607 phyctl = (phyctl & ~mask) | phytxant;
1608 brcms_b_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
1609
1610 /* set the Response (ACK/CTS) frame phy control word */
1611 phyctl = brcms_b_read_shm(wlc_hw, M_RSP_PCTLWD);
1612 phyctl = (phyctl & ~mask) | phytxant;
1613 brcms_b_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
1614 }
1615
1616 static u16 brcms_b_ofdm_ratetable_offset(struct brcms_hardware *wlc_hw,
1617 u8 rate)
1618 {
1619 uint i;
1620 u8 plcp_rate = 0;
1621 struct plcp_signal_rate_lookup {
1622 u8 rate;
1623 u8 signal_rate;
1624 };
1625 /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
1626 const struct plcp_signal_rate_lookup rate_lookup[] = {
1627 {BRCM_RATE_6M, 0xB},
1628 {BRCM_RATE_9M, 0xF},
1629 {BRCM_RATE_12M, 0xA},
1630 {BRCM_RATE_18M, 0xE},
1631 {BRCM_RATE_24M, 0x9},
1632 {BRCM_RATE_36M, 0xD},
1633 {BRCM_RATE_48M, 0x8},
1634 {BRCM_RATE_54M, 0xC}
1635 };
1636
1637 for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
1638 if (rate == rate_lookup[i].rate) {
1639 plcp_rate = rate_lookup[i].signal_rate;
1640 break;
1641 }
1642 }
1643
1644 /* Find the SHM pointer to the rate table entry by looking in the
1645 * Direct-map Table
1646 */
1647 return 2 * brcms_b_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
1648 }
1649
1650 static void brcms_upd_ofdm_pctl1_table(struct brcms_hardware *wlc_hw)
1651 {
1652 u8 rate;
1653 u8 rates[8] = {
1654 BRCM_RATE_6M, BRCM_RATE_9M, BRCM_RATE_12M, BRCM_RATE_18M,
1655 BRCM_RATE_24M, BRCM_RATE_36M, BRCM_RATE_48M, BRCM_RATE_54M
1656 };
1657 u16 entry_ptr;
1658 u16 pctl1;
1659 uint i;
1660
1661 if (!BRCMS_PHY_11N_CAP(wlc_hw->band))
1662 return;
1663
1664 /* walk the phy rate table and update the entries */
1665 for (i = 0; i < ARRAY_SIZE(rates); i++) {
1666 rate = rates[i];
1667
1668 entry_ptr = brcms_b_ofdm_ratetable_offset(wlc_hw, rate);
1669
1670 /* read the SHM Rate Table entry OFDM PCTL1 values */
1671 pctl1 =
1672 brcms_b_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
1673
1674 /* modify the value */
1675 pctl1 &= ~PHY_TXC1_MODE_MASK;
1676 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
1677
1678 /* Update the SHM Rate Table entry OFDM PCTL1 values */
1679 brcms_b_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
1680 pctl1);
1681 }
1682 }
1683
1684 /* band-specific init */
1685 static void brcms_b_bsinit(struct brcms_c_info *wlc, u16 chanspec)
1686 {
1687 struct brcms_hardware *wlc_hw = wlc->hw;
1688
1689 BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
1690 wlc_hw->band->bandunit);
1691
1692 brcms_c_ucode_bsinit(wlc_hw);
1693
1694 wlc_phy_init(wlc_hw->band->pi, chanspec);
1695
1696 brcms_c_ucode_txant_set(wlc_hw);
1697
1698 /*
1699 * cwmin is band-specific, update hardware
1700 * with value for current band
1701 */
1702 brcms_b_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
1703 brcms_b_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
1704
1705 brcms_b_update_slot_timing(wlc_hw,
1706 wlc_hw->band->bandtype == BRCM_BAND_5G ?
1707 true : wlc_hw->shortslot);
1708
1709 /* write phytype and phyvers */
1710 brcms_b_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
1711 brcms_b_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
1712
1713 /*
1714 * initialize the txphyctl1 rate table since
1715 * shmem is shared between bands
1716 */
1717 brcms_upd_ofdm_pctl1_table(wlc_hw);
1718
1719 brcms_b_upd_synthpu(wlc_hw);
1720 }
1721
1722 /* Perform a soft reset of the PHY PLL */
1723 void brcms_b_core_phypll_reset(struct brcms_hardware *wlc_hw)
1724 {
1725 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1726
1727 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_addr),
1728 ~0, 0);
1729 udelay(1);
1730 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1731 0x4, 0);
1732 udelay(1);
1733 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1734 0x4, 4);
1735 udelay(1);
1736 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1737 0x4, 0);
1738 udelay(1);
1739 }
1740
1741 /* light way to turn on phy clock without reset for NPHY only
1742 * refer to brcms_b_core_phy_clk for full version
1743 */
1744 void brcms_b_phyclk_fgc(struct brcms_hardware *wlc_hw, bool clk)
1745 {
1746 /* support(necessary for NPHY and HYPHY) only */
1747 if (!BRCMS_ISNPHY(wlc_hw->band))
1748 return;
1749
1750 if (ON == clk)
1751 brcms_b_core_ioctl(wlc_hw, SICF_FGC, SICF_FGC);
1752 else
1753 brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0);
1754
1755 }
1756
1757 void brcms_b_macphyclk_set(struct brcms_hardware *wlc_hw, bool clk)
1758 {
1759 if (ON == clk)
1760 brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, SICF_MPCLKE);
1761 else
1762 brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, 0);
1763 }
1764
1765 void brcms_b_phy_reset(struct brcms_hardware *wlc_hw)
1766 {
1767 struct brcms_phy_pub *pih = wlc_hw->band->pi;
1768 u32 phy_bw_clkbits;
1769 bool phy_in_reset = false;
1770
1771 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1772
1773 if (pih == NULL)
1774 return;
1775
1776 phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
1777
1778 /* Specific reset sequence required for NPHY rev 3 and 4 */
1779 if (BRCMS_ISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
1780 NREV_LE(wlc_hw->band->phyrev, 4)) {
1781 /* Set the PHY bandwidth */
1782 brcms_b_core_ioctl(wlc_hw, SICF_BWMASK, phy_bw_clkbits);
1783
1784 udelay(1);
1785
1786 /* Perform a soft reset of the PHY PLL */
1787 brcms_b_core_phypll_reset(wlc_hw);
1788
1789 /* reset the PHY */
1790 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_PCLKE),
1791 (SICF_PRST | SICF_PCLKE));
1792 phy_in_reset = true;
1793 } else {
1794 brcms_b_core_ioctl(wlc_hw,
1795 (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
1796 (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
1797 }
1798
1799 udelay(2);
1800 brcms_b_core_phy_clk(wlc_hw, ON);
1801
1802 if (pih)
1803 wlc_phy_anacore(pih, ON);
1804 }
1805
1806 /* switch to and initialize new band */
1807 static void brcms_b_setband(struct brcms_hardware *wlc_hw, uint bandunit,
1808 u16 chanspec) {
1809 struct brcms_c_info *wlc = wlc_hw->wlc;
1810 u32 macintmask;
1811
1812 /* Enable the d11 core before accessing it */
1813 if (!bcma_core_is_enabled(wlc_hw->d11core)) {
1814 bcma_core_enable(wlc_hw->d11core, 0);
1815 brcms_c_mctrl_reset(wlc_hw);
1816 }
1817
1818 macintmask = brcms_c_setband_inact(wlc, bandunit);
1819
1820 if (!wlc_hw->up)
1821 return;
1822
1823 brcms_b_core_phy_clk(wlc_hw, ON);
1824
1825 /* band-specific initializations */
1826 brcms_b_bsinit(wlc, chanspec);
1827
1828 /*
1829 * If there are any pending software interrupt bits,
1830 * then replace these with a harmless nonzero value
1831 * so brcms_c_dpc() will re-enable interrupts when done.
1832 */
1833 if (wlc->macintstatus)
1834 wlc->macintstatus = MI_DMAINT;
1835
1836 /* restore macintmask */
1837 brcms_intrsrestore(wlc->wl, macintmask);
1838
1839 /* ucode should still be suspended.. */
1840 WARN_ON((bcma_read32(wlc_hw->d11core, D11REGOFFS(maccontrol)) &
1841 MCTL_EN_MAC) != 0);
1842 }
1843
1844 static bool brcms_c_isgoodchip(struct brcms_hardware *wlc_hw)
1845 {
1846
1847 /* reject unsupported corerev */
1848 if (!CONF_HAS(D11CONF, wlc_hw->corerev)) {
1849 wiphy_err(wlc_hw->wlc->wiphy, "unsupported core rev %d\n",
1850 wlc_hw->corerev);
1851 return false;
1852 }
1853
1854 return true;
1855 }
1856
1857 /* Validate some board info parameters */
1858 static bool brcms_c_validboardtype(struct brcms_hardware *wlc_hw)
1859 {
1860 uint boardrev = wlc_hw->boardrev;
1861
1862 /* 4 bits each for board type, major, minor, and tiny version */
1863 uint brt = (boardrev & 0xf000) >> 12;
1864 uint b0 = (boardrev & 0xf00) >> 8;
1865 uint b1 = (boardrev & 0xf0) >> 4;
1866 uint b2 = boardrev & 0xf;
1867
1868 /* voards from other vendors are always considered valid */
1869 if (ai_get_boardvendor(wlc_hw->sih) != PCI_VENDOR_ID_BROADCOM)
1870 return true;
1871
1872 /* do some boardrev sanity checks when boardvendor is Broadcom */
1873 if (boardrev == 0)
1874 return false;
1875
1876 if (boardrev <= 0xff)
1877 return true;
1878
1879 if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
1880 || (b2 > 9))
1881 return false;
1882
1883 return true;
1884 }
1885
1886 static void brcms_c_get_macaddr(struct brcms_hardware *wlc_hw, u8 etheraddr[ETH_ALEN])
1887 {
1888 struct ssb_sprom *sprom = &wlc_hw->d11core->bus->sprom;
1889
1890 /* If macaddr exists, use it (Sromrev4, CIS, ...). */
1891 if (!is_zero_ether_addr(sprom->il0mac)) {
1892 memcpy(etheraddr, sprom->il0mac, 6);
1893 return;
1894 }
1895
1896 if (wlc_hw->_nbands > 1)
1897 memcpy(etheraddr, sprom->et1mac, 6);
1898 else
1899 memcpy(etheraddr, sprom->il0mac, 6);
1900 }
1901
1902 /* power both the pll and external oscillator on/off */
1903 static void brcms_b_xtal(struct brcms_hardware *wlc_hw, bool want)
1904 {
1905 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: want %d\n", wlc_hw->unit, want);
1906
1907 /*
1908 * dont power down if plldown is false or
1909 * we must poll hw radio disable
1910 */
1911 if (!want && wlc_hw->pllreq)
1912 return;
1913
1914 wlc_hw->sbclk = want;
1915 if (!wlc_hw->sbclk) {
1916 wlc_hw->clk = false;
1917 if (wlc_hw->band && wlc_hw->band->pi)
1918 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
1919 }
1920 }
1921
1922 /*
1923 * Return true if radio is disabled, otherwise false.
1924 * hw radio disable signal is an external pin, users activate it asynchronously
1925 * this function could be called when driver is down and w/o clock
1926 * it operates on different registers depending on corerev and boardflag.
1927 */
1928 static bool brcms_b_radio_read_hwdisabled(struct brcms_hardware *wlc_hw)
1929 {
1930 bool v, clk, xtal;
1931 u32 flags = 0;
1932
1933 xtal = wlc_hw->sbclk;
1934 if (!xtal)
1935 brcms_b_xtal(wlc_hw, ON);
1936
1937 /* may need to take core out of reset first */
1938 clk = wlc_hw->clk;
1939 if (!clk) {
1940 /*
1941 * mac no longer enables phyclk automatically when driver
1942 * accesses phyreg throughput mac. This can be skipped since
1943 * only mac reg is accessed below
1944 */
1945 if (D11REV_GE(wlc_hw->corerev, 18))
1946 flags |= SICF_PCLKE;
1947
1948 /*
1949 * TODO: test suspend/resume
1950 *
1951 * AI chip doesn't restore bar0win2 on
1952 * hibernation/resume, need sw fixup
1953 */
1954
1955 bcma_core_enable(wlc_hw->d11core, flags);
1956 brcms_c_mctrl_reset(wlc_hw);
1957 }
1958
1959 v = ((bcma_read32(wlc_hw->d11core,
1960 D11REGOFFS(phydebug)) & PDBG_RFD) != 0);
1961
1962 /* put core back into reset */
1963 if (!clk)
1964 bcma_core_disable(wlc_hw->d11core, 0);
1965
1966 if (!xtal)
1967 brcms_b_xtal(wlc_hw, OFF);
1968
1969 return v;
1970 }
1971
1972 static bool wlc_dma_rxreset(struct brcms_hardware *wlc_hw, uint fifo)
1973 {
1974 struct dma_pub *di = wlc_hw->di[fifo];
1975 return dma_rxreset(di);
1976 }
1977
1978 /* d11 core reset
1979 * ensure fask clock during reset
1980 * reset dma
1981 * reset d11(out of reset)
1982 * reset phy(out of reset)
1983 * clear software macintstatus for fresh new start
1984 * one testing hack wlc_hw->noreset will bypass the d11/phy reset
1985 */
1986 void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags)
1987 {
1988 uint i;
1989 bool fastclk;
1990
1991 if (flags == BRCMS_USE_COREFLAGS)
1992 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
1993
1994 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
1995
1996 /* request FAST clock if not on */
1997 fastclk = wlc_hw->forcefastclk;
1998 if (!fastclk)
1999 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
2000
2001 /* reset the dma engines except first time thru */
2002 if (bcma_core_is_enabled(wlc_hw->d11core)) {
2003 for (i = 0; i < NFIFO; i++)
2004 if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i])))
2005 wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: "
2006 "dma_txreset[%d]: cannot stop dma\n",
2007 wlc_hw->unit, __func__, i);
2008
2009 if ((wlc_hw->di[RX_FIFO])
2010 && (!wlc_dma_rxreset(wlc_hw, RX_FIFO)))
2011 wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: dma_rxreset"
2012 "[%d]: cannot stop dma\n",
2013 wlc_hw->unit, __func__, RX_FIFO);
2014 }
2015 /* if noreset, just stop the psm and return */
2016 if (wlc_hw->noreset) {
2017 wlc_hw->wlc->macintstatus = 0; /* skip wl_dpc after down */
2018 brcms_b_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
2019 return;
2020 }
2021
2022 /*
2023 * mac no longer enables phyclk automatically when driver accesses
2024 * phyreg throughput mac, AND phy_reset is skipped at early stage when
2025 * band->pi is invalid. need to enable PHY CLK
2026 */
2027 if (D11REV_GE(wlc_hw->corerev, 18))
2028 flags |= SICF_PCLKE;
2029
2030 /*
2031 * reset the core
2032 * In chips with PMU, the fastclk request goes through d11 core
2033 * reg 0x1e0, which is cleared by the core_reset. have to re-request it.
2034 *
2035 * This adds some delay and we can optimize it by also requesting
2036 * fastclk through chipcommon during this period if necessary. But
2037 * that has to work coordinate with other driver like mips/arm since
2038 * they may touch chipcommon as well.
2039 */
2040 wlc_hw->clk = false;
2041 bcma_core_enable(wlc_hw->d11core, flags);
2042 wlc_hw->clk = true;
2043 if (wlc_hw->band && wlc_hw->band->pi)
2044 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
2045
2046 brcms_c_mctrl_reset(wlc_hw);
2047
2048 if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU)
2049 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
2050
2051 brcms_b_phy_reset(wlc_hw);
2052
2053 /* turn on PHY_PLL */
2054 brcms_b_core_phypll_ctl(wlc_hw, true);
2055
2056 /* clear sw intstatus */
2057 wlc_hw->wlc->macintstatus = 0;
2058
2059 /* restore the clk setting */
2060 if (!fastclk)
2061 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
2062 }
2063
2064 /* txfifo sizes needs to be modified(increased) since the newer cores
2065 * have more memory.
2066 */
2067 static void brcms_b_corerev_fifofixup(struct brcms_hardware *wlc_hw)
2068 {
2069 struct bcma_device *core = wlc_hw->d11core;
2070 u16 fifo_nu;
2071 u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
2072 u16 txfifo_def, txfifo_def1;
2073 u16 txfifo_cmd;
2074
2075 /* tx fifos start at TXFIFO_START_BLK from the Base address */
2076 txfifo_startblk = TXFIFO_START_BLK;
2077
2078 /* sequence of operations: reset fifo, set fifo size, reset fifo */
2079 for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
2080
2081 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
2082 txfifo_def = (txfifo_startblk & 0xff) |
2083 (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
2084 txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
2085 ((((txfifo_endblk -
2086 1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
2087 txfifo_cmd =
2088 TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
2089
2090 bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd);
2091 bcma_write16(core, D11REGOFFS(xmtfifodef), txfifo_def);
2092 bcma_write16(core, D11REGOFFS(xmtfifodef1), txfifo_def1);
2093
2094 bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd);
2095
2096 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2097 }
2098 /*
2099 * need to propagate to shm location to be in sync since ucode/hw won't
2100 * do this
2101 */
2102 brcms_b_write_shm(wlc_hw, M_FIFOSIZE0,
2103 wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
2104 brcms_b_write_shm(wlc_hw, M_FIFOSIZE1,
2105 wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
2106 brcms_b_write_shm(wlc_hw, M_FIFOSIZE2,
2107 ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
2108 xmtfifo_sz[TX_AC_BK_FIFO]));
2109 brcms_b_write_shm(wlc_hw, M_FIFOSIZE3,
2110 ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
2111 xmtfifo_sz[TX_BCMC_FIFO]));
2112 }
2113
2114 /* This function is used for changing the tsf frac register
2115 * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2116 * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2117 * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2118 * HTPHY Formula is 2^26/freq(MHz) e.g.
2119 * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2120 * - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2121 * For spuron: 123MHz -> 2^26/123 = 545600.5
2122 * - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2123 * For spur off: 120MHz -> 2^26/120 = 559240.5
2124 * - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2125 */
2126
2127 void brcms_b_switch_macfreq(struct brcms_hardware *wlc_hw, u8 spurmode)
2128 {
2129 struct bcma_device *core = wlc_hw->d11core;
2130
2131 if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43224) ||
2132 (ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43225)) {
2133 if (spurmode == WL_SPURAVOID_ON2) { /* 126Mhz */
2134 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x2082);
2135 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2136 } else if (spurmode == WL_SPURAVOID_ON1) { /* 123Mhz */
2137 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x5341);
2138 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2139 } else { /* 120Mhz */
2140 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x8889);
2141 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2142 }
2143 } else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
2144 if (spurmode == WL_SPURAVOID_ON1) { /* 82Mhz */
2145 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x7CE0);
2146 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC);
2147 } else { /* 80Mhz */
2148 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0xCCCD);
2149 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC);
2150 }
2151 }
2152 }
2153
2154 /* Initialize GPIOs that are controlled by D11 core */
2155 static void brcms_c_gpio_init(struct brcms_c_info *wlc)
2156 {
2157 struct brcms_hardware *wlc_hw = wlc->hw;
2158 u32 gc, gm;
2159
2160 /* use GPIO select 0 to get all gpio signals from the gpio out reg */
2161 brcms_b_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2162
2163 /*
2164 * Common GPIO setup:
2165 * G0 = LED 0 = WLAN Activity
2166 * G1 = LED 1 = WLAN 2.4 GHz Radio State
2167 * G2 = LED 2 = WLAN 5 GHz Radio State
2168 * G4 = radio disable input (HI enabled, LO disabled)
2169 */
2170
2171 gc = gm = 0;
2172
2173 /* Allocate GPIOs for mimo antenna diversity feature */
2174 if (wlc_hw->antsel_type == ANTSEL_2x3) {
2175 /* Enable antenna diversity, use 2x3 mode */
2176 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2177 MHF3_ANTSEL_EN, BRCM_BAND_ALL);
2178 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
2179 MHF3_ANTSEL_MODE, BRCM_BAND_ALL);
2180
2181 /* init superswitch control */
2182 wlc_phy_antsel_init(wlc_hw->band->pi, false);
2183
2184 } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
2185 gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
2186 /*
2187 * The board itself is powered by these GPIOs
2188 * (when not sending pattern) so set them high
2189 */
2190 bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_oe),
2191 (BOARD_GPIO_12 | BOARD_GPIO_13));
2192 bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_out),
2193 (BOARD_GPIO_12 | BOARD_GPIO_13));
2194
2195 /* Enable antenna diversity, use 2x4 mode */
2196 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2197 MHF3_ANTSEL_EN, BRCM_BAND_ALL);
2198 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
2199 BRCM_BAND_ALL);
2200
2201 /* Configure the desired clock to be 4Mhz */
2202 brcms_b_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
2203 ANTSEL_CLKDIV_4MHZ);
2204 }
2205
2206 /*
2207 * gpio 9 controls the PA. ucode is responsible
2208 * for wiggling out and oe
2209 */
2210 if (wlc_hw->boardflags & BFL_PACTRL)
2211 gm |= gc |= BOARD_GPIO_PACTRL;
2212
2213 /* apply to gpiocontrol register */
2214 bcma_chipco_gpio_control(&wlc_hw->d11core->bus->drv_cc, gm, gc);
2215 }
2216
2217 static void brcms_ucode_write(struct brcms_hardware *wlc_hw,
2218 const __le32 ucode[], const size_t nbytes)
2219 {
2220 struct bcma_device *core = wlc_hw->d11core;
2221 uint i;
2222 uint count;
2223
2224 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2225
2226 count = (nbytes / sizeof(u32));
2227
2228 bcma_write32(core, D11REGOFFS(objaddr),
2229 OBJADDR_AUTO_INC | OBJADDR_UCM_SEL);
2230 (void)bcma_read32(core, D11REGOFFS(objaddr));
2231 for (i = 0; i < count; i++)
2232 bcma_write32(core, D11REGOFFS(objdata), le32_to_cpu(ucode[i]));
2233
2234 }
2235
2236 static void brcms_ucode_download(struct brcms_hardware *wlc_hw)
2237 {
2238 struct brcms_c_info *wlc;
2239 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
2240
2241 wlc = wlc_hw->wlc;
2242
2243 if (wlc_hw->ucode_loaded)
2244 return;
2245
2246 if (D11REV_IS(wlc_hw->corerev, 23)) {
2247 if (BRCMS_ISNPHY(wlc_hw->band)) {
2248 brcms_ucode_write(wlc_hw, ucode->bcm43xx_16_mimo,
2249 ucode->bcm43xx_16_mimosz);
2250 wlc_hw->ucode_loaded = true;
2251 } else
2252 wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in "
2253 "corerev %d\n",
2254 __func__, wlc_hw->unit, wlc_hw->corerev);
2255 } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2256 if (BRCMS_ISLCNPHY(wlc_hw->band)) {
2257 brcms_ucode_write(wlc_hw, ucode->bcm43xx_24_lcn,
2258 ucode->bcm43xx_24_lcnsz);
2259 wlc_hw->ucode_loaded = true;
2260 } else {
2261 wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in "
2262 "corerev %d\n",
2263 __func__, wlc_hw->unit, wlc_hw->corerev);
2264 }
2265 }
2266 }
2267
2268 void brcms_b_txant_set(struct brcms_hardware *wlc_hw, u16 phytxant)
2269 {
2270 /* update sw state */
2271 wlc_hw->bmac_phytxant = phytxant;
2272
2273 /* push to ucode if up */
2274 if (!wlc_hw->up)
2275 return;
2276 brcms_c_ucode_txant_set(wlc_hw);
2277
2278 }
2279
2280 u16 brcms_b_get_txant(struct brcms_hardware *wlc_hw)
2281 {
2282 return (u16) wlc_hw->wlc->stf->txant;
2283 }
2284
2285 void brcms_b_antsel_type_set(struct brcms_hardware *wlc_hw, u8 antsel_type)
2286 {
2287 wlc_hw->antsel_type = antsel_type;
2288
2289 /* Update the antsel type for phy module to use */
2290 wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2291 }
2292
2293 static void brcms_b_fifoerrors(struct brcms_hardware *wlc_hw)
2294 {
2295 bool fatal = false;
2296 uint unit;
2297 uint intstatus, idx;
2298 struct bcma_device *core = wlc_hw->d11core;
2299 struct wiphy *wiphy = wlc_hw->wlc->wiphy;
2300
2301 unit = wlc_hw->unit;
2302
2303 for (idx = 0; idx < NFIFO; idx++) {
2304 /* read intstatus register and ignore any non-error bits */
2305 intstatus =
2306 bcma_read32(core,
2307 D11REGOFFS(intctrlregs[idx].intstatus)) &
2308 I_ERRORS;
2309 if (!intstatus)
2310 continue;
2311
2312 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: intstatus%d 0x%x\n",
2313 unit, idx, intstatus);
2314
2315 if (intstatus & I_RO) {
2316 wiphy_err(wiphy, "wl%d: fifo %d: receive fifo "
2317 "overflow\n", unit, idx);
2318 fatal = true;
2319 }
2320
2321 if (intstatus & I_PC) {
2322 wiphy_err(wiphy, "wl%d: fifo %d: descriptor error\n",
2323 unit, idx);
2324 fatal = true;
2325 }
2326
2327 if (intstatus & I_PD) {
2328 wiphy_err(wiphy, "wl%d: fifo %d: data error\n", unit,
2329 idx);
2330 fatal = true;
2331 }
2332
2333 if (intstatus & I_DE) {
2334 wiphy_err(wiphy, "wl%d: fifo %d: descriptor protocol "
2335 "error\n", unit, idx);
2336 fatal = true;
2337 }
2338
2339 if (intstatus & I_RU)
2340 wiphy_err(wiphy, "wl%d: fifo %d: receive descriptor "
2341 "underflow\n", idx, unit);
2342
2343 if (intstatus & I_XU) {
2344 wiphy_err(wiphy, "wl%d: fifo %d: transmit fifo "
2345 "underflow\n", idx, unit);
2346 fatal = true;
2347 }
2348
2349 if (fatal) {
2350 brcms_fatal_error(wlc_hw->wlc->wl); /* big hammer */
2351 break;
2352 } else
2353 bcma_write32(core,
2354 D11REGOFFS(intctrlregs[idx].intstatus),
2355 intstatus);
2356 }
2357 }
2358
2359 void brcms_c_intrson(struct brcms_c_info *wlc)
2360 {
2361 struct brcms_hardware *wlc_hw = wlc->hw;
2362 wlc->macintmask = wlc->defmacintmask;
2363 bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask);
2364 }
2365
2366 u32 brcms_c_intrsoff(struct brcms_c_info *wlc)
2367 {
2368 struct brcms_hardware *wlc_hw = wlc->hw;
2369 u32 macintmask;
2370
2371 if (!wlc_hw->clk)
2372 return 0;
2373
2374 macintmask = wlc->macintmask; /* isr can still happen */
2375
2376 bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), 0);
2377 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(macintmask));
2378 udelay(1); /* ensure int line is no longer driven */
2379 wlc->macintmask = 0;
2380
2381 /* return previous macintmask; resolve race between us and our isr */
2382 return wlc->macintstatus ? 0 : macintmask;
2383 }
2384
2385 void brcms_c_intrsrestore(struct brcms_c_info *wlc, u32 macintmask)
2386 {
2387 struct brcms_hardware *wlc_hw = wlc->hw;
2388 if (!wlc_hw->clk)
2389 return;
2390
2391 wlc->macintmask = macintmask;
2392 bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask);
2393 }
2394
2395 /* assumes that the d11 MAC is enabled */
2396 static void brcms_b_tx_fifo_suspend(struct brcms_hardware *wlc_hw,
2397 uint tx_fifo)
2398 {
2399 u8 fifo = 1 << tx_fifo;
2400
2401 /* Two clients of this code, 11h Quiet period and scanning. */
2402
2403 /* only suspend if not already suspended */
2404 if ((wlc_hw->suspended_fifos & fifo) == fifo)
2405 return;
2406
2407 /* force the core awake only if not already */
2408 if (wlc_hw->suspended_fifos == 0)
2409 brcms_c_ucode_wake_override_set(wlc_hw,
2410 BRCMS_WAKE_OVERRIDE_TXFIFO);
2411
2412 wlc_hw->suspended_fifos |= fifo;
2413
2414 if (wlc_hw->di[tx_fifo]) {
2415 /*
2416 * Suspending AMPDU transmissions in the middle can cause
2417 * underflow which may result in mismatch between ucode and
2418 * driver so suspend the mac before suspending the FIFO
2419 */
2420 if (BRCMS_PHY_11N_CAP(wlc_hw->band))
2421 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
2422
2423 dma_txsuspend(wlc_hw->di[tx_fifo]);
2424
2425 if (BRCMS_PHY_11N_CAP(wlc_hw->band))
2426 brcms_c_enable_mac(wlc_hw->wlc);
2427 }
2428 }
2429
2430 static void brcms_b_tx_fifo_resume(struct brcms_hardware *wlc_hw,
2431 uint tx_fifo)
2432 {
2433 /* BMAC_NOTE: BRCMS_TX_FIFO_ENAB is done in brcms_c_dpc() for DMA case
2434 * but need to be done here for PIO otherwise the watchdog will catch
2435 * the inconsistency and fire
2436 */
2437 /* Two clients of this code, 11h Quiet period and scanning. */
2438 if (wlc_hw->di[tx_fifo])
2439 dma_txresume(wlc_hw->di[tx_fifo]);
2440
2441 /* allow core to sleep again */
2442 if (wlc_hw->suspended_fifos == 0)
2443 return;
2444 else {
2445 wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
2446 if (wlc_hw->suspended_fifos == 0)
2447 brcms_c_ucode_wake_override_clear(wlc_hw,
2448 BRCMS_WAKE_OVERRIDE_TXFIFO);
2449 }
2450 }
2451
2452 /* precondition: requires the mac core to be enabled */
2453 static void brcms_b_mute(struct brcms_hardware *wlc_hw, bool mute_tx)
2454 {
2455 static const u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
2456
2457 if (mute_tx) {
2458 /* suspend tx fifos */
2459 brcms_b_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
2460 brcms_b_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
2461 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
2462 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
2463
2464 /* zero the address match register so we do not send ACKs */
2465 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2466 null_ether_addr);
2467 } else {
2468 /* resume tx fifos */
2469 brcms_b_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
2470 brcms_b_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
2471 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
2472 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
2473
2474 /* Restore address */
2475 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
2476 wlc_hw->etheraddr);
2477 }
2478
2479 wlc_phy_mute_upd(wlc_hw->band->pi, mute_tx, 0);
2480
2481 if (mute_tx)
2482 brcms_c_ucode_mute_override_set(wlc_hw);
2483 else
2484 brcms_c_ucode_mute_override_clear(wlc_hw);
2485 }
2486
2487 void
2488 brcms_c_mute(struct brcms_c_info *wlc, bool mute_tx)
2489 {
2490 brcms_b_mute(wlc->hw, mute_tx);
2491 }
2492
2493 /*
2494 * Read and clear macintmask and macintstatus and intstatus registers.
2495 * This routine should be called with interrupts off
2496 * Return:
2497 * -1 if brcms_deviceremoved(wlc) evaluates to true;
2498 * 0 if the interrupt is not for us, or we are in some special cases;
2499 * device interrupt status bits otherwise.
2500 */
2501 static inline u32 wlc_intstatus(struct brcms_c_info *wlc, bool in_isr)
2502 {
2503 struct brcms_hardware *wlc_hw = wlc->hw;
2504 struct bcma_device *core = wlc_hw->d11core;
2505 u32 macintstatus;
2506
2507 /* macintstatus includes a DMA interrupt summary bit */
2508 macintstatus = bcma_read32(core, D11REGOFFS(macintstatus));
2509
2510 BCMMSG(wlc->wiphy, "wl%d: macintstatus: 0x%x\n", wlc_hw->unit,
2511 macintstatus);
2512
2513 /* detect cardbus removed, in power down(suspend) and in reset */
2514 if (brcms_deviceremoved(wlc))
2515 return -1;
2516
2517 /* brcms_deviceremoved() succeeds even when the core is still resetting,
2518 * handle that case here.
2519 */
2520 if (macintstatus == 0xffffffff)
2521 return 0;
2522
2523 /* defer unsolicited interrupts */
2524 macintstatus &= (in_isr ? wlc->macintmask : wlc->defmacintmask);
2525
2526 /* if not for us */
2527 if (macintstatus == 0)
2528 return 0;
2529
2530 /* interrupts are already turned off for CFE build
2531 * Caution: For CFE Turning off the interrupts again has some undesired
2532 * consequences
2533 */
2534 /* turn off the interrupts */
2535 bcma_write32(core, D11REGOFFS(macintmask), 0);
2536 (void)bcma_read32(core, D11REGOFFS(macintmask));
2537 wlc->macintmask = 0;
2538
2539 /* clear device interrupts */
2540 bcma_write32(core, D11REGOFFS(macintstatus), macintstatus);
2541
2542 /* MI_DMAINT is indication of non-zero intstatus */
2543 if (macintstatus & MI_DMAINT)
2544 /*
2545 * only fifo interrupt enabled is I_RI in
2546 * RX_FIFO. If MI_DMAINT is set, assume it
2547 * is set and clear the interrupt.
2548 */
2549 bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intstatus),
2550 DEF_RXINTMASK);
2551
2552 return macintstatus;
2553 }
2554
2555 /* Update wlc->macintstatus and wlc->intstatus[]. */
2556 /* Return true if they are updated successfully. false otherwise */
2557 bool brcms_c_intrsupd(struct brcms_c_info *wlc)
2558 {
2559 u32 macintstatus;
2560
2561 /* read and clear macintstatus and intstatus registers */
2562 macintstatus = wlc_intstatus(wlc, false);
2563
2564 /* device is removed */
2565 if (macintstatus == 0xffffffff)
2566 return false;
2567
2568 /* update interrupt status in software */
2569 wlc->macintstatus |= macintstatus;
2570
2571 return true;
2572 }
2573
2574 /*
2575 * First-level interrupt processing.
2576 * Return true if this was our interrupt, false otherwise.
2577 * *wantdpc will be set to true if further brcms_c_dpc() processing is required,
2578 * false otherwise.
2579 */
2580 bool brcms_c_isr(struct brcms_c_info *wlc, bool *wantdpc)
2581 {
2582 struct brcms_hardware *wlc_hw = wlc->hw;
2583 u32 macintstatus;
2584
2585 *wantdpc = false;
2586
2587 if (!wlc_hw->up || !wlc->macintmask)
2588 return false;
2589
2590 /* read and clear macintstatus and intstatus registers */
2591 macintstatus = wlc_intstatus(wlc, true);
2592
2593 if (macintstatus == 0xffffffff)
2594 wiphy_err(wlc->wiphy, "DEVICEREMOVED detected in the ISR code"
2595 " path\n");
2596
2597 /* it is not for us */
2598 if (macintstatus == 0)
2599 return false;
2600
2601 *wantdpc = true;
2602
2603 /* save interrupt status bits */
2604 wlc->macintstatus = macintstatus;
2605
2606 return true;
2607
2608 }
2609
2610 void brcms_c_suspend_mac_and_wait(struct brcms_c_info *wlc)
2611 {
2612 struct brcms_hardware *wlc_hw = wlc->hw;
2613 struct bcma_device *core = wlc_hw->d11core;
2614 u32 mc, mi;
2615 struct wiphy *wiphy = wlc->wiphy;
2616
2617 BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
2618 wlc_hw->band->bandunit);
2619
2620 /*
2621 * Track overlapping suspend requests
2622 */
2623 wlc_hw->mac_suspend_depth++;
2624 if (wlc_hw->mac_suspend_depth > 1)
2625 return;
2626
2627 /* force the core awake */
2628 brcms_c_ucode_wake_override_set(wlc_hw, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
2629
2630 mc = bcma_read32(core, D11REGOFFS(maccontrol));
2631
2632 if (mc == 0xffffffff) {
2633 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
2634 __func__);
2635 brcms_down(wlc->wl);
2636 return;
2637 }
2638 WARN_ON(mc & MCTL_PSM_JMP_0);
2639 WARN_ON(!(mc & MCTL_PSM_RUN));
2640 WARN_ON(!(mc & MCTL_EN_MAC));
2641
2642 mi = bcma_read32(core, D11REGOFFS(macintstatus));
2643 if (mi == 0xffffffff) {
2644 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
2645 __func__);
2646 brcms_down(wlc->wl);
2647 return;
2648 }
2649 WARN_ON(mi & MI_MACSSPNDD);
2650
2651 brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, 0);
2652
2653 SPINWAIT(!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD),
2654 BRCMS_MAX_MAC_SUSPEND);
2655
2656 if (!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD)) {
2657 wiphy_err(wiphy, "wl%d: wlc_suspend_mac_and_wait: waited %d uS"
2658 " and MI_MACSSPNDD is still not on.\n",
2659 wlc_hw->unit, BRCMS_MAX_MAC_SUSPEND);
2660 wiphy_err(wiphy, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, "
2661 "psm_brc 0x%04x\n", wlc_hw->unit,
2662 bcma_read32(core, D11REGOFFS(psmdebug)),
2663 bcma_read32(core, D11REGOFFS(phydebug)),
2664 bcma_read16(core, D11REGOFFS(psm_brc)));
2665 }
2666
2667 mc = bcma_read32(core, D11REGOFFS(maccontrol));
2668 if (mc == 0xffffffff) {
2669 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
2670 __func__);
2671 brcms_down(wlc->wl);
2672 return;
2673 }
2674 WARN_ON(mc & MCTL_PSM_JMP_0);
2675 WARN_ON(!(mc & MCTL_PSM_RUN));
2676 WARN_ON(mc & MCTL_EN_MAC);
2677 }
2678
2679 void brcms_c_enable_mac(struct brcms_c_info *wlc)
2680 {
2681 struct brcms_hardware *wlc_hw = wlc->hw;
2682 struct bcma_device *core = wlc_hw->d11core;
2683 u32 mc, mi;
2684
2685 BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
2686 wlc->band->bandunit);
2687
2688 /*
2689 * Track overlapping suspend requests
2690 */
2691 wlc_hw->mac_suspend_depth--;
2692 if (wlc_hw->mac_suspend_depth > 0)
2693 return;
2694
2695 mc = bcma_read32(core, D11REGOFFS(maccontrol));
2696 WARN_ON(mc & MCTL_PSM_JMP_0);
2697 WARN_ON(mc & MCTL_EN_MAC);
2698 WARN_ON(!(mc & MCTL_PSM_RUN));
2699
2700 brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
2701 bcma_write32(core, D11REGOFFS(macintstatus), MI_MACSSPNDD);
2702
2703 mc = bcma_read32(core, D11REGOFFS(maccontrol));
2704 WARN_ON(mc & MCTL_PSM_JMP_0);
2705 WARN_ON(!(mc & MCTL_EN_MAC));
2706 WARN_ON(!(mc & MCTL_PSM_RUN));
2707
2708 mi = bcma_read32(core, D11REGOFFS(macintstatus));
2709 WARN_ON(mi & MI_MACSSPNDD);
2710
2711 brcms_c_ucode_wake_override_clear(wlc_hw,
2712 BRCMS_WAKE_OVERRIDE_MACSUSPEND);
2713 }
2714
2715 void brcms_b_band_stf_ss_set(struct brcms_hardware *wlc_hw, u8 stf_mode)
2716 {
2717 wlc_hw->hw_stf_ss_opmode = stf_mode;
2718
2719 if (wlc_hw->clk)
2720 brcms_upd_ofdm_pctl1_table(wlc_hw);
2721 }
2722
2723 static bool brcms_b_validate_chip_access(struct brcms_hardware *wlc_hw)
2724 {
2725 struct bcma_device *core = wlc_hw->d11core;
2726 u32 w, val;
2727 struct wiphy *wiphy = wlc_hw->wlc->wiphy;
2728
2729 BCMMSG(wiphy, "wl%d\n", wlc_hw->unit);
2730
2731 /* Validate dchip register access */
2732
2733 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2734 (void)bcma_read32(core, D11REGOFFS(objaddr));
2735 w = bcma_read32(core, D11REGOFFS(objdata));
2736
2737 /* Can we write and read back a 32bit register? */
2738 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2739 (void)bcma_read32(core, D11REGOFFS(objaddr));
2740 bcma_write32(core, D11REGOFFS(objdata), (u32) 0xaa5555aa);
2741
2742 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2743 (void)bcma_read32(core, D11REGOFFS(objaddr));
2744 val = bcma_read32(core, D11REGOFFS(objdata));
2745 if (val != (u32) 0xaa5555aa) {
2746 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
2747 "expected 0xaa5555aa\n", wlc_hw->unit, val);
2748 return false;
2749 }
2750
2751 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2752 (void)bcma_read32(core, D11REGOFFS(objaddr));
2753 bcma_write32(core, D11REGOFFS(objdata), (u32) 0x55aaaa55);
2754
2755 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2756 (void)bcma_read32(core, D11REGOFFS(objaddr));
2757 val = bcma_read32(core, D11REGOFFS(objdata));
2758 if (val != (u32) 0x55aaaa55) {
2759 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
2760 "expected 0x55aaaa55\n", wlc_hw->unit, val);
2761 return false;
2762 }
2763
2764 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2765 (void)bcma_read32(core, D11REGOFFS(objaddr));
2766 bcma_write32(core, D11REGOFFS(objdata), w);
2767
2768 /* clear CFPStart */
2769 bcma_write32(core, D11REGOFFS(tsf_cfpstart), 0);
2770
2771 w = bcma_read32(core, D11REGOFFS(maccontrol));
2772 if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
2773 (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
2774 wiphy_err(wiphy, "wl%d: validate_chip_access: maccontrol = "
2775 "0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w,
2776 (MCTL_IHR_EN | MCTL_WAKE),
2777 (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
2778 return false;
2779 }
2780
2781 return true;
2782 }
2783
2784 #define PHYPLL_WAIT_US 100000
2785
2786 void brcms_b_core_phypll_ctl(struct brcms_hardware *wlc_hw, bool on)
2787 {
2788 struct bcma_device *core = wlc_hw->d11core;
2789 u32 tmp;
2790
2791 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2792
2793 tmp = 0;
2794
2795 if (on) {
2796 if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM4313)) {
2797 bcma_set32(core, D11REGOFFS(clk_ctl_st),
2798 CCS_ERSRC_REQ_HT |
2799 CCS_ERSRC_REQ_D11PLL |
2800 CCS_ERSRC_REQ_PHYPLL);
2801 SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) &
2802 CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT,
2803 PHYPLL_WAIT_US);
2804
2805 tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st));
2806 if ((tmp & CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT)
2807 wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on PHY"
2808 " PLL failed\n", __func__);
2809 } else {
2810 bcma_set32(core, D11REGOFFS(clk_ctl_st),
2811 tmp | CCS_ERSRC_REQ_D11PLL |
2812 CCS_ERSRC_REQ_PHYPLL);
2813 SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) &
2814 (CCS_ERSRC_AVAIL_D11PLL |
2815 CCS_ERSRC_AVAIL_PHYPLL)) !=
2816 (CCS_ERSRC_AVAIL_D11PLL |
2817 CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
2818
2819 tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st));
2820 if ((tmp &
2821 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
2822 !=
2823 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
2824 wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on "
2825 "PHY PLL failed\n", __func__);
2826 }
2827 } else {
2828 /*
2829 * Since the PLL may be shared, other cores can still
2830 * be requesting it; so we'll deassert the request but
2831 * not wait for status to comply.
2832 */
2833 bcma_mask32(core, D11REGOFFS(clk_ctl_st),
2834 ~CCS_ERSRC_REQ_PHYPLL);
2835 (void)bcma_read32(core, D11REGOFFS(clk_ctl_st));
2836 }
2837 }
2838
2839 static void brcms_c_coredisable(struct brcms_hardware *wlc_hw)
2840 {
2841 bool dev_gone;
2842
2843 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
2844
2845 dev_gone = brcms_deviceremoved(wlc_hw->wlc);
2846
2847 if (dev_gone)
2848 return;
2849
2850 if (wlc_hw->noreset)
2851 return;
2852
2853 /* radio off */
2854 wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
2855
2856 /* turn off analog core */
2857 wlc_phy_anacore(wlc_hw->band->pi, OFF);
2858
2859 /* turn off PHYPLL to save power */
2860 brcms_b_core_phypll_ctl(wlc_hw, false);
2861
2862 wlc_hw->clk = false;
2863 bcma_core_disable(wlc_hw->d11core, 0);
2864 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
2865 }
2866
2867 static void brcms_c_flushqueues(struct brcms_c_info *wlc)
2868 {
2869 struct brcms_hardware *wlc_hw = wlc->hw;
2870 uint i;
2871
2872 /* free any posted tx packets */
2873 for (i = 0; i < NFIFO; i++)
2874 if (wlc_hw->di[i]) {
2875 dma_txreclaim(wlc_hw->di[i], DMA_RANGE_ALL);
2876 wlc->core->txpktpend[i] = 0;
2877 BCMMSG(wlc->wiphy, "pktpend fifo %d clrd\n", i);
2878 }
2879
2880 /* free any posted rx packets */
2881 dma_rxreclaim(wlc_hw->di[RX_FIFO]);
2882 }
2883
2884 static u16
2885 brcms_b_read_objmem(struct brcms_hardware *wlc_hw, uint offset, u32 sel)
2886 {
2887 struct bcma_device *core = wlc_hw->d11core;
2888 u16 objoff = D11REGOFFS(objdata);
2889
2890 bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2));
2891 (void)bcma_read32(core, D11REGOFFS(objaddr));
2892 if (offset & 2)
2893 objoff += 2;
2894
2895 return bcma_read16(core, objoff);
2896 }
2897
2898 static void
2899 brcms_b_write_objmem(struct brcms_hardware *wlc_hw, uint offset, u16 v,
2900 u32 sel)
2901 {
2902 struct bcma_device *core = wlc_hw->d11core;
2903 u16 objoff = D11REGOFFS(objdata);
2904
2905 bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2));
2906 (void)bcma_read32(core, D11REGOFFS(objaddr));
2907 if (offset & 2)
2908 objoff += 2;
2909
2910 bcma_write16(core, objoff, v);
2911 }
2912
2913 /*
2914 * Read a single u16 from shared memory.
2915 * SHM 'offset' needs to be an even address
2916 */
2917 u16 brcms_b_read_shm(struct brcms_hardware *wlc_hw, uint offset)
2918 {
2919 return brcms_b_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
2920 }
2921
2922 /*
2923 * Write a single u16 to shared memory.
2924 * SHM 'offset' needs to be an even address
2925 */
2926 void brcms_b_write_shm(struct brcms_hardware *wlc_hw, uint offset, u16 v)
2927 {
2928 brcms_b_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
2929 }
2930
2931 /*
2932 * Copy a buffer to shared memory of specified type .
2933 * SHM 'offset' needs to be an even address and
2934 * Buffer length 'len' must be an even number of bytes
2935 * 'sel' selects the type of memory
2936 */
2937 void
2938 brcms_b_copyto_objmem(struct brcms_hardware *wlc_hw, uint offset,
2939 const void *buf, int len, u32 sel)
2940 {
2941 u16 v;
2942 const u8 *p = (const u8 *)buf;
2943 int i;
2944
2945 if (len <= 0 || (offset & 1) || (len & 1))
2946 return;
2947
2948 for (i = 0; i < len; i += 2) {
2949 v = p[i] | (p[i + 1] << 8);
2950 brcms_b_write_objmem(wlc_hw, offset + i, v, sel);
2951 }
2952 }
2953
2954 /*
2955 * Copy a piece of shared memory of specified type to a buffer .
2956 * SHM 'offset' needs to be an even address and
2957 * Buffer length 'len' must be an even number of bytes
2958 * 'sel' selects the type of memory
2959 */
2960 void
2961 brcms_b_copyfrom_objmem(struct brcms_hardware *wlc_hw, uint offset, void *buf,
2962 int len, u32 sel)
2963 {
2964 u16 v;
2965 u8 *p = (u8 *) buf;
2966 int i;
2967
2968 if (len <= 0 || (offset & 1) || (len & 1))
2969 return;
2970
2971 for (i = 0; i < len; i += 2) {
2972 v = brcms_b_read_objmem(wlc_hw, offset + i, sel);
2973 p[i] = v & 0xFF;
2974 p[i + 1] = (v >> 8) & 0xFF;
2975 }
2976 }
2977
2978 /* Copy a buffer to shared memory.
2979 * SHM 'offset' needs to be an even address and
2980 * Buffer length 'len' must be an even number of bytes
2981 */
2982 static void brcms_c_copyto_shm(struct brcms_c_info *wlc, uint offset,
2983 const void *buf, int len)
2984 {
2985 brcms_b_copyto_objmem(wlc->hw, offset, buf, len, OBJADDR_SHM_SEL);
2986 }
2987
2988 static void brcms_b_retrylimit_upd(struct brcms_hardware *wlc_hw,
2989 u16 SRL, u16 LRL)
2990 {
2991 wlc_hw->SRL = SRL;
2992 wlc_hw->LRL = LRL;
2993
2994 /* write retry limit to SCR, shouldn't need to suspend */
2995 if (wlc_hw->up) {
2996 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
2997 OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
2998 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
2999 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->SRL);
3000 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
3001 OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3002 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
3003 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->LRL);
3004 }
3005 }
3006
3007 static void brcms_b_pllreq(struct brcms_hardware *wlc_hw, bool set, u32 req_bit)
3008 {
3009 if (set) {
3010 if (mboolisset(wlc_hw->pllreq, req_bit))
3011 return;
3012
3013 mboolset(wlc_hw->pllreq, req_bit);
3014
3015 if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
3016 if (!wlc_hw->sbclk)
3017 brcms_b_xtal(wlc_hw, ON);
3018 }
3019 } else {
3020 if (!mboolisset(wlc_hw->pllreq, req_bit))
3021 return;
3022
3023 mboolclr(wlc_hw->pllreq, req_bit);
3024
3025 if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
3026 if (wlc_hw->sbclk)
3027 brcms_b_xtal(wlc_hw, OFF);
3028 }
3029 }
3030 }
3031
3032 static void brcms_b_antsel_set(struct brcms_hardware *wlc_hw, u32 antsel_avail)
3033 {
3034 wlc_hw->antsel_avail = antsel_avail;
3035 }
3036
3037 /*
3038 * conditions under which the PM bit should be set in outgoing frames
3039 * and STAY_AWAKE is meaningful
3040 */
3041 static bool brcms_c_ps_allowed(struct brcms_c_info *wlc)
3042 {
3043 struct brcms_bss_cfg *cfg = wlc->bsscfg;
3044
3045 /* disallow PS when one of the following global conditions meets */
3046 if (!wlc->pub->associated)
3047 return false;
3048
3049 /* disallow PS when one of these meets when not scanning */
3050 if (wlc->filter_flags & FIF_PROMISC_IN_BSS)
3051 return false;
3052
3053 if (cfg->associated) {
3054 /*
3055 * disallow PS when one of the following
3056 * bsscfg specific conditions meets
3057 */
3058 if (!cfg->BSS)
3059 return false;
3060
3061 return false;
3062 }
3063
3064 return true;
3065 }
3066
3067 static void brcms_c_statsupd(struct brcms_c_info *wlc)
3068 {
3069 int i;
3070 struct macstat macstats;
3071 #ifdef DEBUG
3072 u16 delta;
3073 u16 rxf0ovfl;
3074 u16 txfunfl[NFIFO];
3075 #endif /* DEBUG */
3076
3077 /* if driver down, make no sense to update stats */
3078 if (!wlc->pub->up)
3079 return;
3080
3081 #ifdef DEBUG
3082 /* save last rx fifo 0 overflow count */
3083 rxf0ovfl = wlc->core->macstat_snapshot->rxf0ovfl;
3084
3085 /* save last tx fifo underflow count */
3086 for (i = 0; i < NFIFO; i++)
3087 txfunfl[i] = wlc->core->macstat_snapshot->txfunfl[i];
3088 #endif /* DEBUG */
3089
3090 /* Read mac stats from contiguous shared memory */
3091 brcms_b_copyfrom_objmem(wlc->hw, M_UCODE_MACSTAT, &macstats,
3092 sizeof(struct macstat), OBJADDR_SHM_SEL);
3093
3094 #ifdef DEBUG
3095 /* check for rx fifo 0 overflow */
3096 delta = (u16) (wlc->core->macstat_snapshot->rxf0ovfl - rxf0ovfl);
3097 if (delta)
3098 wiphy_err(wlc->wiphy, "wl%d: %u rx fifo 0 overflows!\n",
3099 wlc->pub->unit, delta);
3100
3101 /* check for tx fifo underflows */
3102 for (i = 0; i < NFIFO; i++) {
3103 delta =
3104 (u16) (wlc->core->macstat_snapshot->txfunfl[i] -
3105 txfunfl[i]);
3106 if (delta)
3107 wiphy_err(wlc->wiphy, "wl%d: %u tx fifo %d underflows!"
3108 "\n", wlc->pub->unit, delta, i);
3109 }
3110 #endif /* DEBUG */
3111
3112 /* merge counters from dma module */
3113 for (i = 0; i < NFIFO; i++) {
3114 if (wlc->hw->di[i])
3115 dma_counterreset(wlc->hw->di[i]);
3116 }
3117 }
3118
3119 static void brcms_b_reset(struct brcms_hardware *wlc_hw)
3120 {
3121 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
3122
3123 /* reset the core */
3124 if (!brcms_deviceremoved(wlc_hw->wlc))
3125 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
3126
3127 /* purge the dma rings */
3128 brcms_c_flushqueues(wlc_hw->wlc);
3129 }
3130
3131 void brcms_c_reset(struct brcms_c_info *wlc)
3132 {
3133 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
3134
3135 /* slurp up hw mac counters before core reset */
3136 brcms_c_statsupd(wlc);
3137
3138 /* reset our snapshot of macstat counters */
3139 memset((char *)wlc->core->macstat_snapshot, 0,
3140 sizeof(struct macstat));
3141
3142 brcms_b_reset(wlc->hw);
3143 }
3144
3145 void brcms_c_init_scb(struct scb *scb)
3146 {
3147 int i;
3148
3149 memset(scb, 0, sizeof(struct scb));
3150 scb->flags = SCB_WMECAP | SCB_HTCAP;
3151 for (i = 0; i < NUMPRIO; i++) {
3152 scb->seqnum[i] = 0;
3153 scb->seqctl[i] = 0xFFFF;
3154 }
3155
3156 scb->seqctl_nonqos = 0xFFFF;
3157 scb->magic = SCB_MAGIC;
3158 }
3159
3160 /* d11 core init
3161 * reset PSM
3162 * download ucode/PCM
3163 * let ucode run to suspended
3164 * download ucode inits
3165 * config other core registers
3166 * init dma
3167 */
3168 static void brcms_b_coreinit(struct brcms_c_info *wlc)
3169 {
3170 struct brcms_hardware *wlc_hw = wlc->hw;
3171 struct bcma_device *core = wlc_hw->d11core;
3172 u32 sflags;
3173 u32 bcnint_us;
3174 uint i = 0;
3175 bool fifosz_fixup = false;
3176 int err = 0;
3177 u16 buf[NFIFO];
3178 struct wiphy *wiphy = wlc->wiphy;
3179 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
3180
3181 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
3182
3183 /* reset PSM */
3184 brcms_b_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
3185
3186 brcms_ucode_download(wlc_hw);
3187 /*
3188 * FIFOSZ fixup. driver wants to controls the fifo allocation.
3189 */
3190 fifosz_fixup = true;
3191
3192 /* let the PSM run to the suspended state, set mode to BSS STA */
3193 bcma_write32(core, D11REGOFFS(macintstatus), -1);
3194 brcms_b_mctrl(wlc_hw, ~0,
3195 (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
3196
3197 /* wait for ucode to self-suspend after auto-init */
3198 SPINWAIT(((bcma_read32(core, D11REGOFFS(macintstatus)) &
3199 MI_MACSSPNDD) == 0), 1000 * 1000);
3200 if ((bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD) == 0)
3201 wiphy_err(wiphy, "wl%d: wlc_coreinit: ucode did not self-"
3202 "suspend!\n", wlc_hw->unit);
3203
3204 brcms_c_gpio_init(wlc);
3205
3206 sflags = bcma_aread32(core, BCMA_IOST);
3207
3208 if (D11REV_IS(wlc_hw->corerev, 23)) {
3209 if (BRCMS_ISNPHY(wlc_hw->band))
3210 brcms_c_write_inits(wlc_hw, ucode->d11n0initvals16);
3211 else
3212 wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
3213 " %d\n", __func__, wlc_hw->unit,
3214 wlc_hw->corerev);
3215 } else if (D11REV_IS(wlc_hw->corerev, 24)) {
3216 if (BRCMS_ISLCNPHY(wlc_hw->band))
3217 brcms_c_write_inits(wlc_hw, ucode->d11lcn0initvals24);
3218 else
3219 wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
3220 " %d\n", __func__, wlc_hw->unit,
3221 wlc_hw->corerev);
3222 } else {
3223 wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n",
3224 __func__, wlc_hw->unit, wlc_hw->corerev);
3225 }
3226
3227 /* For old ucode, txfifo sizes needs to be modified(increased) */
3228 if (fifosz_fixup)
3229 brcms_b_corerev_fifofixup(wlc_hw);
3230
3231 /* check txfifo allocations match between ucode and driver */
3232 buf[TX_AC_BE_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE0);
3233 if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
3234 i = TX_AC_BE_FIFO;
3235 err = -1;
3236 }
3237 buf[TX_AC_VI_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE1);
3238 if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
3239 i = TX_AC_VI_FIFO;
3240 err = -1;
3241 }
3242 buf[TX_AC_BK_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE2);
3243 buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
3244 buf[TX_AC_BK_FIFO] &= 0xff;
3245 if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
3246 i = TX_AC_BK_FIFO;
3247 err = -1;
3248 }
3249 if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
3250 i = TX_AC_VO_FIFO;
3251 err = -1;
3252 }
3253 buf[TX_BCMC_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE3);
3254 buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
3255 buf[TX_BCMC_FIFO] &= 0xff;
3256 if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
3257 i = TX_BCMC_FIFO;
3258 err = -1;
3259 }
3260 if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
3261 i = TX_ATIM_FIFO;
3262 err = -1;
3263 }
3264 if (err != 0)
3265 wiphy_err(wiphy, "wlc_coreinit: txfifo mismatch: ucode size %d"
3266 " driver size %d index %d\n", buf[i],
3267 wlc_hw->xmtfifo_sz[i], i);
3268
3269 /* make sure we can still talk to the mac */
3270 WARN_ON(bcma_read32(core, D11REGOFFS(maccontrol)) == 0xffffffff);
3271
3272 /* band-specific inits done by wlc_bsinit() */
3273
3274 /* Set up frame burst size and antenna swap threshold init values */
3275 brcms_b_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
3276 brcms_b_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
3277
3278 /* enable one rx interrupt per received frame */
3279 bcma_write32(core, D11REGOFFS(intrcvlazy[0]), (1 << IRL_FC_SHIFT));
3280
3281 /* set the station mode (BSS STA) */
3282 brcms_b_mctrl(wlc_hw,
3283 (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
3284 (MCTL_INFRA | MCTL_DISCARD_PMQ));
3285
3286 /* set up Beacon interval */
3287 bcnint_us = 0x8000 << 10;
3288 bcma_write32(core, D11REGOFFS(tsf_cfprep),
3289 (bcnint_us << CFPREP_CBI_SHIFT));
3290 bcma_write32(core, D11REGOFFS(tsf_cfpstart), bcnint_us);
3291 bcma_write32(core, D11REGOFFS(macintstatus), MI_GP1);
3292
3293 /* write interrupt mask */
3294 bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intmask),
3295 DEF_RXINTMASK);
3296
3297 /* allow the MAC to control the PHY clock (dynamic on/off) */
3298 brcms_b_macphyclk_set(wlc_hw, ON);
3299
3300 /* program dynamic clock control fast powerup delay register */
3301 wlc->fastpwrup_dly = ai_clkctl_fast_pwrup_delay(wlc_hw->sih);
3302 bcma_write16(core, D11REGOFFS(scc_fastpwrup_dly), wlc->fastpwrup_dly);
3303
3304 /* tell the ucode the corerev */
3305 brcms_b_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
3306
3307 /* tell the ucode MAC capabilities */
3308 brcms_b_write_shm(wlc_hw, M_MACHW_CAP_L,
3309 (u16) (wlc_hw->machwcap & 0xffff));
3310 brcms_b_write_shm(wlc_hw, M_MACHW_CAP_H,
3311 (u16) ((wlc_hw->
3312 machwcap >> 16) & 0xffff));
3313
3314 /* write retry limits to SCR, this done after PSM init */
3315 bcma_write32(core, D11REGOFFS(objaddr),
3316 OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3317 (void)bcma_read32(core, D11REGOFFS(objaddr));
3318 bcma_write32(core, D11REGOFFS(objdata), wlc_hw->SRL);
3319 bcma_write32(core, D11REGOFFS(objaddr),
3320 OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3321 (void)bcma_read32(core, D11REGOFFS(objaddr));
3322 bcma_write32(core, D11REGOFFS(objdata), wlc_hw->LRL);
3323
3324 /* write rate fallback retry limits */
3325 brcms_b_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
3326 brcms_b_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
3327
3328 bcma_mask16(core, D11REGOFFS(ifs_ctl), 0x0FFF);
3329 bcma_write16(core, D11REGOFFS(ifs_aifsn), EDCF_AIFSN_MIN);
3330
3331 /* init the tx dma engines */
3332 for (i = 0; i < NFIFO; i++) {
3333 if (wlc_hw->di[i])
3334 dma_txinit(wlc_hw->di[i]);
3335 }
3336
3337 /* init the rx dma engine(s) and post receive buffers */
3338 dma_rxinit(wlc_hw->di[RX_FIFO]);
3339 dma_rxfill(wlc_hw->di[RX_FIFO]);
3340 }
3341
3342 void
3343 static brcms_b_init(struct brcms_hardware *wlc_hw, u16 chanspec) {
3344 u32 macintmask;
3345 bool fastclk;
3346 struct brcms_c_info *wlc = wlc_hw->wlc;
3347
3348 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
3349
3350 /* request FAST clock if not on */
3351 fastclk = wlc_hw->forcefastclk;
3352 if (!fastclk)
3353 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
3354
3355 /* disable interrupts */
3356 macintmask = brcms_intrsoff(wlc->wl);
3357
3358 /* set up the specified band and chanspec */
3359 brcms_c_setxband(wlc_hw, chspec_bandunit(chanspec));
3360 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
3361
3362 /* do one-time phy inits and calibration */
3363 wlc_phy_cal_init(wlc_hw->band->pi);
3364
3365 /* core-specific initialization */
3366 brcms_b_coreinit(wlc);
3367
3368 /* band-specific inits */
3369 brcms_b_bsinit(wlc, chanspec);
3370
3371 /* restore macintmask */
3372 brcms_intrsrestore(wlc->wl, macintmask);
3373
3374 /* seed wake_override with BRCMS_WAKE_OVERRIDE_MACSUSPEND since the mac
3375 * is suspended and brcms_c_enable_mac() will clear this override bit.
3376 */
3377 mboolset(wlc_hw->wake_override, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
3378
3379 /*
3380 * initialize mac_suspend_depth to 1 to match ucode
3381 * initial suspended state
3382 */
3383 wlc_hw->mac_suspend_depth = 1;
3384
3385 /* restore the clk */
3386 if (!fastclk)
3387 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
3388 }
3389
3390 static void brcms_c_set_phy_chanspec(struct brcms_c_info *wlc,
3391 u16 chanspec)
3392 {
3393 /* Save our copy of the chanspec */
3394 wlc->chanspec = chanspec;
3395
3396 /* Set the chanspec and power limits for this locale */
3397 brcms_c_channel_set_chanspec(wlc->cmi, chanspec, BRCMS_TXPWR_MAX);
3398
3399 if (wlc->stf->ss_algosel_auto)
3400 brcms_c_stf_ss_algo_channel_get(wlc, &wlc->stf->ss_algo_channel,
3401 chanspec);
3402
3403 brcms_c_stf_ss_update(wlc, wlc->band);
3404 }
3405
3406 static void
3407 brcms_default_rateset(struct brcms_c_info *wlc, struct brcms_c_rateset *rs)
3408 {
3409 brcms_c_rateset_default(rs, NULL, wlc->band->phytype,
3410 wlc->band->bandtype, false, BRCMS_RATE_MASK_FULL,
3411 (bool) (wlc->pub->_n_enab & SUPPORT_11N),
3412 brcms_chspec_bw(wlc->default_bss->chanspec),
3413 wlc->stf->txstreams);
3414 }
3415
3416 /* derive wlc->band->basic_rate[] table from 'rateset' */
3417 static void brcms_c_rate_lookup_init(struct brcms_c_info *wlc,
3418 struct brcms_c_rateset *rateset)
3419 {
3420 u8 rate;
3421 u8 mandatory;
3422 u8 cck_basic = 0;
3423 u8 ofdm_basic = 0;
3424 u8 *br = wlc->band->basic_rate;
3425 uint i;
3426
3427 /* incoming rates are in 500kbps units as in 802.11 Supported Rates */
3428 memset(br, 0, BRCM_MAXRATE + 1);
3429
3430 /* For each basic rate in the rates list, make an entry in the
3431 * best basic lookup.
3432 */
3433 for (i = 0; i < rateset->count; i++) {
3434 /* only make an entry for a basic rate */
3435 if (!(rateset->rates[i] & BRCMS_RATE_FLAG))
3436 continue;
3437
3438 /* mask off basic bit */
3439 rate = (rateset->rates[i] & BRCMS_RATE_MASK);
3440
3441 if (rate > BRCM_MAXRATE) {
3442 wiphy_err(wlc->wiphy, "brcms_c_rate_lookup_init: "
3443 "invalid rate 0x%X in rate set\n",
3444 rateset->rates[i]);
3445 continue;
3446 }
3447
3448 br[rate] = rate;
3449 }
3450
3451 /* The rate lookup table now has non-zero entries for each
3452 * basic rate, equal to the basic rate: br[basicN] = basicN
3453 *
3454 * To look up the best basic rate corresponding to any
3455 * particular rate, code can use the basic_rate table
3456 * like this
3457 *
3458 * basic_rate = wlc->band->basic_rate[tx_rate]
3459 *
3460 * Make sure there is a best basic rate entry for
3461 * every rate by walking up the table from low rates
3462 * to high, filling in holes in the lookup table
3463 */
3464
3465 for (i = 0; i < wlc->band->hw_rateset.count; i++) {
3466 rate = wlc->band->hw_rateset.rates[i];
3467
3468 if (br[rate] != 0) {
3469 /* This rate is a basic rate.
3470 * Keep track of the best basic rate so far by
3471 * modulation type.
3472 */
3473 if (is_ofdm_rate(rate))
3474 ofdm_basic = rate;
3475 else
3476 cck_basic = rate;
3477
3478 continue;
3479 }
3480
3481 /* This rate is not a basic rate so figure out the
3482 * best basic rate less than this rate and fill in
3483 * the hole in the table
3484 */
3485
3486 br[rate] = is_ofdm_rate(rate) ? ofdm_basic : cck_basic;
3487
3488 if (br[rate] != 0)
3489 continue;
3490
3491 if (is_ofdm_rate(rate)) {
3492 /*
3493 * In 11g and 11a, the OFDM mandatory rates
3494 * are 6, 12, and 24 Mbps
3495 */
3496 if (rate >= BRCM_RATE_24M)
3497 mandatory = BRCM_RATE_24M;
3498 else if (rate >= BRCM_RATE_12M)
3499 mandatory = BRCM_RATE_12M;
3500 else
3501 mandatory = BRCM_RATE_6M;
3502 } else {
3503 /* In 11b, all CCK rates are mandatory 1 - 11 Mbps */
3504 mandatory = rate;
3505 }
3506
3507 br[rate] = mandatory;
3508 }
3509 }
3510
3511 static void brcms_c_bandinit_ordered(struct brcms_c_info *wlc,
3512 u16 chanspec)
3513 {
3514 struct brcms_c_rateset default_rateset;
3515 uint parkband;
3516 uint i, band_order[2];
3517
3518 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
3519 /*
3520 * We might have been bandlocked during down and the chip
3521 * power-cycled (hibernate). Figure out the right band to park on
3522 */
3523 if (wlc->bandlocked || wlc->pub->_nbands == 1) {
3524 /* updated in brcms_c_bandlock() */
3525 parkband = wlc->band->bandunit;
3526 band_order[0] = band_order[1] = parkband;
3527 } else {
3528 /* park on the band of the specified chanspec */
3529 parkband = chspec_bandunit(chanspec);
3530
3531 /* order so that parkband initialize last */
3532 band_order[0] = parkband ^ 1;
3533 band_order[1] = parkband;
3534 }
3535
3536 /* make each band operational, software state init */
3537 for (i = 0; i < wlc->pub->_nbands; i++) {
3538 uint j = band_order[i];
3539
3540 wlc->band = wlc->bandstate[j];
3541
3542 brcms_default_rateset(wlc, &default_rateset);
3543
3544 /* fill in hw_rate */
3545 brcms_c_rateset_filter(&default_rateset, &wlc->band->hw_rateset,
3546 false, BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK,
3547 (bool) (wlc->pub->_n_enab & SUPPORT_11N));
3548
3549 /* init basic rate lookup */
3550 brcms_c_rate_lookup_init(wlc, &default_rateset);
3551 }
3552
3553 /* sync up phy/radio chanspec */
3554 brcms_c_set_phy_chanspec(wlc, chanspec);
3555 }
3556
3557 /*
3558 * Set or clear filtering related maccontrol bits based on
3559 * specified filter flags
3560 */
3561 void brcms_c_mac_promisc(struct brcms_c_info *wlc, uint filter_flags)
3562 {
3563 u32 promisc_bits = 0;
3564
3565 wlc->filter_flags = filter_flags;
3566
3567 if (filter_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS))
3568 promisc_bits |= MCTL_PROMISC;
3569
3570 if (filter_flags & FIF_BCN_PRBRESP_PROMISC)
3571 promisc_bits |= MCTL_BCNS_PROMISC;
3572
3573 if (filter_flags & FIF_FCSFAIL)
3574 promisc_bits |= MCTL_KEEPBADFCS;
3575
3576 if (filter_flags & (FIF_CONTROL | FIF_PSPOLL))
3577 promisc_bits |= MCTL_KEEPCONTROL;
3578
3579 brcms_b_mctrl(wlc->hw,
3580 MCTL_PROMISC | MCTL_BCNS_PROMISC |
3581 MCTL_KEEPCONTROL | MCTL_KEEPBADFCS,
3582 promisc_bits);
3583 }
3584
3585 /*
3586 * ucode, hwmac update
3587 * Channel dependent updates for ucode and hw
3588 */
3589 static void brcms_c_ucode_mac_upd(struct brcms_c_info *wlc)
3590 {
3591 /* enable or disable any active IBSSs depending on whether or not
3592 * we are on the home channel
3593 */
3594 if (wlc->home_chanspec == wlc_phy_chanspec_get(wlc->band->pi)) {
3595 if (wlc->pub->associated) {
3596 /*
3597 * BMAC_NOTE: This is something that should be fixed
3598 * in ucode inits. I think that the ucode inits set
3599 * up the bcn templates and shm values with a bogus
3600 * beacon. This should not be done in the inits. If
3601 * ucode needs to set up a beacon for testing, the
3602 * test routines should write it down, not expect the
3603 * inits to populate a bogus beacon.
3604 */
3605 if (BRCMS_PHY_11N_CAP(wlc->band))
3606 brcms_b_write_shm(wlc->hw,
3607 M_BCN_TXTSF_OFFSET, 0);
3608 }
3609 } else {
3610 /* disable an active IBSS if we are not on the home channel */
3611 }
3612 }
3613
3614 static void brcms_c_write_rate_shm(struct brcms_c_info *wlc, u8 rate,
3615 u8 basic_rate)
3616 {
3617 u8 phy_rate, index;
3618 u8 basic_phy_rate, basic_index;
3619 u16 dir_table, basic_table;
3620 u16 basic_ptr;
3621
3622 /* Shared memory address for the table we are reading */
3623 dir_table = is_ofdm_rate(basic_rate) ? M_RT_DIRMAP_A : M_RT_DIRMAP_B;
3624
3625 /* Shared memory address for the table we are writing */
3626 basic_table = is_ofdm_rate(rate) ? M_RT_BBRSMAP_A : M_RT_BBRSMAP_B;
3627
3628 /*
3629 * for a given rate, the LS-nibble of the PLCP SIGNAL field is
3630 * the index into the rate table.
3631 */
3632 phy_rate = rate_info[rate] & BRCMS_RATE_MASK;
3633 basic_phy_rate = rate_info[basic_rate] & BRCMS_RATE_MASK;
3634 index = phy_rate & 0xf;
3635 basic_index = basic_phy_rate & 0xf;
3636
3637 /* Find the SHM pointer to the ACK rate entry by looking in the
3638 * Direct-map Table
3639 */
3640 basic_ptr = brcms_b_read_shm(wlc->hw, (dir_table + basic_index * 2));
3641
3642 /* Update the SHM BSS-basic-rate-set mapping table with the pointer
3643 * to the correct basic rate for the given incoming rate
3644 */
3645 brcms_b_write_shm(wlc->hw, (basic_table + index * 2), basic_ptr);
3646 }
3647
3648 static const struct brcms_c_rateset *
3649 brcms_c_rateset_get_hwrs(struct brcms_c_info *wlc)
3650 {
3651 const struct brcms_c_rateset *rs_dflt;
3652
3653 if (BRCMS_PHY_11N_CAP(wlc->band)) {
3654 if (wlc->band->bandtype == BRCM_BAND_5G)
3655 rs_dflt = &ofdm_mimo_rates;
3656 else
3657 rs_dflt = &cck_ofdm_mimo_rates;
3658 } else if (wlc->band->gmode)
3659 rs_dflt = &cck_ofdm_rates;
3660 else
3661 rs_dflt = &cck_rates;
3662
3663 return rs_dflt;
3664 }
3665
3666 static void brcms_c_set_ratetable(struct brcms_c_info *wlc)
3667 {
3668 const struct brcms_c_rateset *rs_dflt;
3669 struct brcms_c_rateset rs;
3670 u8 rate, basic_rate;
3671 uint i;
3672
3673 rs_dflt = brcms_c_rateset_get_hwrs(wlc);
3674
3675 brcms_c_rateset_copy(rs_dflt, &rs);
3676 brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams);
3677
3678 /* walk the phy rate table and update SHM basic rate lookup table */
3679 for (i = 0; i < rs.count; i++) {
3680 rate = rs.rates[i] & BRCMS_RATE_MASK;
3681
3682 /* for a given rate brcms_basic_rate returns the rate at
3683 * which a response ACK/CTS should be sent.
3684 */
3685 basic_rate = brcms_basic_rate(wlc, rate);
3686 if (basic_rate == 0)
3687 /* This should only happen if we are using a
3688 * restricted rateset.
3689 */
3690 basic_rate = rs.rates[0] & BRCMS_RATE_MASK;
3691
3692 brcms_c_write_rate_shm(wlc, rate, basic_rate);
3693 }
3694 }
3695
3696 /* band-specific init */
3697 static void brcms_c_bsinit(struct brcms_c_info *wlc)
3698 {
3699 BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n",
3700 wlc->pub->unit, wlc->band->bandunit);
3701
3702 /* write ucode ACK/CTS rate table */
3703 brcms_c_set_ratetable(wlc);
3704
3705 /* update some band specific mac configuration */
3706 brcms_c_ucode_mac_upd(wlc);
3707
3708 /* init antenna selection */
3709 brcms_c_antsel_init(wlc->asi);
3710
3711 }
3712
3713 /* formula: IDLE_BUSY_RATIO_X_16 = (100-duty_cycle)/duty_cycle*16 */
3714 static int
3715 brcms_c_duty_cycle_set(struct brcms_c_info *wlc, int duty_cycle, bool isOFDM,
3716 bool writeToShm)
3717 {
3718 int idle_busy_ratio_x_16 = 0;
3719 uint offset =
3720 isOFDM ? M_TX_IDLE_BUSY_RATIO_X_16_OFDM :
3721 M_TX_IDLE_BUSY_RATIO_X_16_CCK;
3722 if (duty_cycle > 100 || duty_cycle < 0) {
3723 wiphy_err(wlc->wiphy, "wl%d: duty cycle value off limit\n",
3724 wlc->pub->unit);
3725 return -EINVAL;
3726 }
3727 if (duty_cycle)
3728 idle_busy_ratio_x_16 = (100 - duty_cycle) * 16 / duty_cycle;
3729 /* Only write to shared memory when wl is up */
3730 if (writeToShm)
3731 brcms_b_write_shm(wlc->hw, offset, (u16) idle_busy_ratio_x_16);
3732
3733 if (isOFDM)
3734 wlc->tx_duty_cycle_ofdm = (u16) duty_cycle;
3735 else
3736 wlc->tx_duty_cycle_cck = (u16) duty_cycle;
3737
3738 return 0;
3739 }
3740
3741 /*
3742 * Initialize the base precedence map for dequeueing
3743 * from txq based on WME settings
3744 */
3745 static void brcms_c_tx_prec_map_init(struct brcms_c_info *wlc)
3746 {
3747 wlc->tx_prec_map = BRCMS_PREC_BMP_ALL;
3748 }
3749
3750 /* push sw hps and wake state through hardware */
3751 static void brcms_c_set_ps_ctrl(struct brcms_c_info *wlc)
3752 {
3753 u32 v1, v2;
3754 bool hps;
3755 bool awake_before;
3756
3757 hps = brcms_c_ps_allowed(wlc);
3758
3759 BCMMSG(wlc->wiphy, "wl%d: hps %d\n", wlc->pub->unit, hps);
3760
3761 v1 = bcma_read32(wlc->hw->d11core, D11REGOFFS(maccontrol));
3762 v2 = MCTL_WAKE;
3763 if (hps)
3764 v2 |= MCTL_HPS;
3765
3766 brcms_b_mctrl(wlc->hw, MCTL_WAKE | MCTL_HPS, v2);
3767
3768 awake_before = ((v1 & MCTL_WAKE) || ((v1 & MCTL_HPS) == 0));
3769
3770 if (!awake_before)
3771 brcms_b_wait_for_wake(wlc->hw);
3772 }
3773
3774 /*
3775 * Write this BSS config's MAC address to core.
3776 * Updates RXE match engine.
3777 */
3778 static int brcms_c_set_mac(struct brcms_bss_cfg *bsscfg)
3779 {
3780 int err = 0;
3781 struct brcms_c_info *wlc = bsscfg->wlc;
3782
3783 /* enter the MAC addr into the RXE match registers */
3784 brcms_c_set_addrmatch(wlc, RCM_MAC_OFFSET, bsscfg->cur_etheraddr);
3785
3786 brcms_c_ampdu_macaddr_upd(wlc);
3787
3788 return err;
3789 }
3790
3791 /* Write the BSS config's BSSID address to core (set_bssid in d11procs.tcl).
3792 * Updates RXE match engine.
3793 */
3794 static void brcms_c_set_bssid(struct brcms_bss_cfg *bsscfg)
3795 {
3796 /* we need to update BSSID in RXE match registers */
3797 brcms_c_set_addrmatch(bsscfg->wlc, RCM_BSSID_OFFSET, bsscfg->BSSID);
3798 }
3799
3800 static void brcms_b_set_shortslot(struct brcms_hardware *wlc_hw, bool shortslot)
3801 {
3802 wlc_hw->shortslot = shortslot;
3803
3804 if (wlc_hw->band->bandtype == BRCM_BAND_2G && wlc_hw->up) {
3805 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
3806 brcms_b_update_slot_timing(wlc_hw, shortslot);
3807 brcms_c_enable_mac(wlc_hw->wlc);
3808 }
3809 }
3810
3811 /*
3812 * Suspend the the MAC and update the slot timing
3813 * for standard 11b/g (20us slots) or shortslot 11g (9us slots).
3814 */
3815 static void brcms_c_switch_shortslot(struct brcms_c_info *wlc, bool shortslot)
3816 {
3817 /* use the override if it is set */
3818 if (wlc->shortslot_override != BRCMS_SHORTSLOT_AUTO)
3819 shortslot = (wlc->shortslot_override == BRCMS_SHORTSLOT_ON);
3820
3821 if (wlc->shortslot == shortslot)
3822 return;
3823
3824 wlc->shortslot = shortslot;
3825
3826 brcms_b_set_shortslot(wlc->hw, shortslot);
3827 }
3828
3829 static void brcms_c_set_home_chanspec(struct brcms_c_info *wlc, u16 chanspec)
3830 {
3831 if (wlc->home_chanspec != chanspec) {
3832 wlc->home_chanspec = chanspec;
3833
3834 if (wlc->bsscfg->associated)
3835 wlc->bsscfg->current_bss->chanspec = chanspec;
3836 }
3837 }
3838
3839 void
3840 brcms_b_set_chanspec(struct brcms_hardware *wlc_hw, u16 chanspec,
3841 bool mute_tx, struct txpwr_limits *txpwr)
3842 {
3843 uint bandunit;
3844
3845 BCMMSG(wlc_hw->wlc->wiphy, "wl%d: 0x%x\n", wlc_hw->unit, chanspec);
3846
3847 wlc_hw->chanspec = chanspec;
3848
3849 /* Switch bands if necessary */
3850 if (wlc_hw->_nbands > 1) {
3851 bandunit = chspec_bandunit(chanspec);
3852 if (wlc_hw->band->bandunit != bandunit) {
3853 /* brcms_b_setband disables other bandunit,
3854 * use light band switch if not up yet
3855 */
3856 if (wlc_hw->up) {
3857 wlc_phy_chanspec_radio_set(wlc_hw->
3858 bandstate[bandunit]->
3859 pi, chanspec);
3860 brcms_b_setband(wlc_hw, bandunit, chanspec);
3861 } else {
3862 brcms_c_setxband(wlc_hw, bandunit);
3863 }
3864 }
3865 }
3866
3867 wlc_phy_initcal_enable(wlc_hw->band->pi, !mute_tx);
3868
3869 if (!wlc_hw->up) {
3870 if (wlc_hw->clk)
3871 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
3872 chanspec);
3873 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
3874 } else {
3875 wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
3876 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
3877
3878 /* Update muting of the channel */
3879 brcms_b_mute(wlc_hw, mute_tx);
3880 }
3881 }
3882
3883 /* switch to and initialize new band */
3884 static void brcms_c_setband(struct brcms_c_info *wlc,
3885 uint bandunit)
3886 {
3887 wlc->band = wlc->bandstate[bandunit];
3888
3889 if (!wlc->pub->up)
3890 return;
3891
3892 /* wait for at least one beacon before entering sleeping state */
3893 brcms_c_set_ps_ctrl(wlc);
3894
3895 /* band-specific initializations */
3896 brcms_c_bsinit(wlc);
3897 }
3898
3899 static void brcms_c_set_chanspec(struct brcms_c_info *wlc, u16 chanspec)
3900 {
3901 uint bandunit;
3902 bool switchband = false;
3903 u16 old_chanspec = wlc->chanspec;
3904
3905 if (!brcms_c_valid_chanspec_db(wlc->cmi, chanspec)) {
3906 wiphy_err(wlc->wiphy, "wl%d: %s: Bad channel %d\n",
3907 wlc->pub->unit, __func__, CHSPEC_CHANNEL(chanspec));
3908 return;
3909 }
3910
3911 /* Switch bands if necessary */
3912 if (wlc->pub->_nbands > 1) {
3913 bandunit = chspec_bandunit(chanspec);
3914 if (wlc->band->bandunit != bandunit || wlc->bandinit_pending) {
3915 switchband = true;
3916 if (wlc->bandlocked) {
3917 wiphy_err(wlc->wiphy, "wl%d: %s: chspec %d "
3918 "band is locked!\n",
3919 wlc->pub->unit, __func__,
3920 CHSPEC_CHANNEL(chanspec));
3921 return;
3922 }
3923 /*
3924 * should the setband call come after the
3925 * brcms_b_chanspec() ? if the setband updates
3926 * (brcms_c_bsinit) use low level calls to inspect and
3927 * set state, the state inspected may be from the wrong
3928 * band, or the following brcms_b_set_chanspec() may
3929 * undo the work.
3930 */
3931 brcms_c_setband(wlc, bandunit);
3932 }
3933 }
3934
3935 /* sync up phy/radio chanspec */
3936 brcms_c_set_phy_chanspec(wlc, chanspec);
3937
3938 /* init antenna selection */
3939 if (brcms_chspec_bw(old_chanspec) != brcms_chspec_bw(chanspec)) {
3940 brcms_c_antsel_init(wlc->asi);
3941
3942 /* Fix the hardware rateset based on bw.
3943 * Mainly add MCS32 for 40Mhz, remove MCS 32 for 20Mhz
3944 */
3945 brcms_c_rateset_bw_mcs_filter(&wlc->band->hw_rateset,
3946 wlc->band->mimo_cap_40 ? brcms_chspec_bw(chanspec) : 0);
3947 }
3948
3949 /* update some mac configuration since chanspec changed */
3950 brcms_c_ucode_mac_upd(wlc);
3951 }
3952
3953 /*
3954 * This function changes the phytxctl for beacon based on current
3955 * beacon ratespec AND txant setting as per this table:
3956 * ratespec CCK ant = wlc->stf->txant
3957 * OFDM ant = 3
3958 */
3959 void brcms_c_beacon_phytxctl_txant_upd(struct brcms_c_info *wlc,
3960 u32 bcn_rspec)
3961 {
3962 u16 phyctl;
3963 u16 phytxant = wlc->stf->phytxant;
3964 u16 mask = PHY_TXC_ANT_MASK;
3965
3966 /* for non-siso rates or default setting, use the available chains */
3967 if (BRCMS_PHY_11N_CAP(wlc->band))
3968 phytxant = brcms_c_stf_phytxchain_sel(wlc, bcn_rspec);
3969
3970 phyctl = brcms_b_read_shm(wlc->hw, M_BCN_PCTLWD);
3971 phyctl = (phyctl & ~mask) | phytxant;
3972 brcms_b_write_shm(wlc->hw, M_BCN_PCTLWD, phyctl);
3973 }
3974
3975 /*
3976 * centralized protection config change function to simplify debugging, no
3977 * consistency checking this should be called only on changes to avoid overhead
3978 * in periodic function
3979 */
3980 void brcms_c_protection_upd(struct brcms_c_info *wlc, uint idx, int val)
3981 {
3982 BCMMSG(wlc->wiphy, "idx %d, val %d\n", idx, val);
3983
3984 switch (idx) {
3985 case BRCMS_PROT_G_SPEC:
3986 wlc->protection->_g = (bool) val;
3987 break;
3988 case BRCMS_PROT_G_OVR:
3989 wlc->protection->g_override = (s8) val;
3990 break;
3991 case BRCMS_PROT_G_USER:
3992 wlc->protection->gmode_user = (u8) val;
3993 break;
3994 case BRCMS_PROT_OVERLAP:
3995 wlc->protection->overlap = (s8) val;
3996 break;
3997 case BRCMS_PROT_N_USER:
3998 wlc->protection->nmode_user = (s8) val;
3999 break;
4000 case BRCMS_PROT_N_CFG:
4001 wlc->protection->n_cfg = (s8) val;
4002 break;
4003 case BRCMS_PROT_N_CFG_OVR:
4004 wlc->protection->n_cfg_override = (s8) val;
4005 break;
4006 case BRCMS_PROT_N_NONGF:
4007 wlc->protection->nongf = (bool) val;
4008 break;
4009 case BRCMS_PROT_N_NONGF_OVR:
4010 wlc->protection->nongf_override = (s8) val;
4011 break;
4012 case BRCMS_PROT_N_PAM_OVR:
4013 wlc->protection->n_pam_override = (s8) val;
4014 break;
4015 case BRCMS_PROT_N_OBSS:
4016 wlc->protection->n_obss = (bool) val;
4017 break;
4018
4019 default:
4020 break;
4021 }
4022
4023 }
4024
4025 static void brcms_c_ht_update_sgi_rx(struct brcms_c_info *wlc, int val)
4026 {
4027 if (wlc->pub->up) {
4028 brcms_c_update_beacon(wlc);
4029 brcms_c_update_probe_resp(wlc, true);
4030 }
4031 }
4032
4033 static void brcms_c_ht_update_ldpc(struct brcms_c_info *wlc, s8 val)
4034 {
4035 wlc->stf->ldpc = val;
4036
4037 if (wlc->pub->up) {
4038 brcms_c_update_beacon(wlc);
4039 brcms_c_update_probe_resp(wlc, true);
4040 wlc_phy_ldpc_override_set(wlc->band->pi, (val ? true : false));
4041 }
4042 }
4043
4044 void brcms_c_wme_setparams(struct brcms_c_info *wlc, u16 aci,
4045 const struct ieee80211_tx_queue_params *params,
4046 bool suspend)
4047 {
4048 int i;
4049 struct shm_acparams acp_shm;
4050 u16 *shm_entry;
4051
4052 /* Only apply params if the core is out of reset and has clocks */
4053 if (!wlc->clk) {
4054 wiphy_err(wlc->wiphy, "wl%d: %s : no-clock\n", wlc->pub->unit,
4055 __func__);
4056 return;
4057 }
4058
4059 memset((char *)&acp_shm, 0, sizeof(struct shm_acparams));
4060 /* fill in shm ac params struct */
4061 acp_shm.txop = params->txop;
4062 /* convert from units of 32us to us for ucode */
4063 wlc->edcf_txop[aci & 0x3] = acp_shm.txop =
4064 EDCF_TXOP2USEC(acp_shm.txop);
4065 acp_shm.aifs = (params->aifs & EDCF_AIFSN_MASK);
4066
4067 if (aci == IEEE80211_AC_VI && acp_shm.txop == 0
4068 && acp_shm.aifs < EDCF_AIFSN_MAX)
4069 acp_shm.aifs++;
4070
4071 if (acp_shm.aifs < EDCF_AIFSN_MIN
4072 || acp_shm.aifs > EDCF_AIFSN_MAX) {
4073 wiphy_err(wlc->wiphy, "wl%d: edcf_setparams: bad "
4074 "aifs %d\n", wlc->pub->unit, acp_shm.aifs);
4075 } else {
4076 acp_shm.cwmin = params->cw_min;
4077 acp_shm.cwmax = params->cw_max;
4078 acp_shm.cwcur = acp_shm.cwmin;
4079 acp_shm.bslots =
4080 bcma_read16(wlc->hw->d11core, D11REGOFFS(tsf_random)) &
4081 acp_shm.cwcur;
4082 acp_shm.reggap = acp_shm.bslots + acp_shm.aifs;
4083 /* Indicate the new params to the ucode */
4084 acp_shm.status = brcms_b_read_shm(wlc->hw, (M_EDCF_QINFO +
4085 wme_ac2fifo[aci] *
4086 M_EDCF_QLEN +
4087 M_EDCF_STATUS_OFF));
4088 acp_shm.status |= WME_STATUS_NEWAC;
4089
4090 /* Fill in shm acparam table */
4091 shm_entry = (u16 *) &acp_shm;
4092 for (i = 0; i < (int)sizeof(struct shm_acparams); i += 2)
4093 brcms_b_write_shm(wlc->hw,
4094 M_EDCF_QINFO +
4095 wme_ac2fifo[aci] * M_EDCF_QLEN + i,
4096 *shm_entry++);
4097 }
4098
4099 if (suspend) {
4100 brcms_c_suspend_mac_and_wait(wlc);
4101 brcms_c_enable_mac(wlc);
4102 }
4103 }
4104
4105 static void brcms_c_edcf_setparams(struct brcms_c_info *wlc, bool suspend)
4106 {
4107 u16 aci;
4108 int i_ac;
4109 struct ieee80211_tx_queue_params txq_pars;
4110 static const struct edcf_acparam default_edcf_acparams[] = {
4111 {EDCF_AC_BE_ACI_STA, EDCF_AC_BE_ECW_STA, EDCF_AC_BE_TXOP_STA},
4112 {EDCF_AC_BK_ACI_STA, EDCF_AC_BK_ECW_STA, EDCF_AC_BK_TXOP_STA},
4113 {EDCF_AC_VI_ACI_STA, EDCF_AC_VI_ECW_STA, EDCF_AC_VI_TXOP_STA},
4114 {EDCF_AC_VO_ACI_STA, EDCF_AC_VO_ECW_STA, EDCF_AC_VO_TXOP_STA}
4115 }; /* ucode needs these parameters during its initialization */
4116 const struct edcf_acparam *edcf_acp = &default_edcf_acparams[0];
4117
4118 for (i_ac = 0; i_ac < IEEE80211_NUM_ACS; i_ac++, edcf_acp++) {
4119 /* find out which ac this set of params applies to */
4120 aci = (edcf_acp->ACI & EDCF_ACI_MASK) >> EDCF_ACI_SHIFT;
4121
4122 /* fill in shm ac params struct */
4123 txq_pars.txop = edcf_acp->TXOP;
4124 txq_pars.aifs = edcf_acp->ACI;
4125
4126 /* CWmin = 2^(ECWmin) - 1 */
4127 txq_pars.cw_min = EDCF_ECW2CW(edcf_acp->ECW & EDCF_ECWMIN_MASK);
4128 /* CWmax = 2^(ECWmax) - 1 */
4129 txq_pars.cw_max = EDCF_ECW2CW((edcf_acp->ECW & EDCF_ECWMAX_MASK)
4130 >> EDCF_ECWMAX_SHIFT);
4131 brcms_c_wme_setparams(wlc, aci, &txq_pars, suspend);
4132 }
4133
4134 if (suspend) {
4135 brcms_c_suspend_mac_and_wait(wlc);
4136 brcms_c_enable_mac(wlc);
4137 }
4138 }
4139
4140 static void brcms_c_radio_monitor_start(struct brcms_c_info *wlc)
4141 {
4142 /* Don't start the timer if HWRADIO feature is disabled */
4143 if (wlc->radio_monitor)
4144 return;
4145
4146 wlc->radio_monitor = true;
4147 brcms_b_pllreq(wlc->hw, true, BRCMS_PLLREQ_RADIO_MON);
4148 brcms_add_timer(wlc->radio_timer, TIMER_INTERVAL_RADIOCHK, true);
4149 }
4150
4151 static bool brcms_c_radio_monitor_stop(struct brcms_c_info *wlc)
4152 {
4153 if (!wlc->radio_monitor)
4154 return true;
4155
4156 wlc->radio_monitor = false;
4157 brcms_b_pllreq(wlc->hw, false, BRCMS_PLLREQ_RADIO_MON);
4158 return brcms_del_timer(wlc->radio_timer);
4159 }
4160
4161 /* read hwdisable state and propagate to wlc flag */
4162 static void brcms_c_radio_hwdisable_upd(struct brcms_c_info *wlc)
4163 {
4164 if (wlc->pub->hw_off)
4165 return;
4166
4167 if (brcms_b_radio_read_hwdisabled(wlc->hw))
4168 mboolset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
4169 else
4170 mboolclr(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE);
4171 }
4172
4173 /* update hwradio status and return it */
4174 bool brcms_c_check_radio_disabled(struct brcms_c_info *wlc)
4175 {
4176 brcms_c_radio_hwdisable_upd(wlc);
4177
4178 return mboolisset(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE) ?
4179 true : false;
4180 }
4181
4182 /* periodical query hw radio button while driver is "down" */
4183 static void brcms_c_radio_timer(void *arg)
4184 {
4185 struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
4186
4187 if (brcms_deviceremoved(wlc)) {
4188 wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n", wlc->pub->unit,
4189 __func__);
4190 brcms_down(wlc->wl);
4191 return;
4192 }
4193
4194 brcms_c_radio_hwdisable_upd(wlc);
4195 }
4196
4197 /* common low-level watchdog code */
4198 static void brcms_b_watchdog(struct brcms_c_info *wlc)
4199 {
4200 struct brcms_hardware *wlc_hw = wlc->hw;
4201
4202 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
4203
4204 if (!wlc_hw->up)
4205 return;
4206
4207 /* increment second count */
4208 wlc_hw->now++;
4209
4210 /* Check for FIFO error interrupts */
4211 brcms_b_fifoerrors(wlc_hw);
4212
4213 /* make sure RX dma has buffers */
4214 dma_rxfill(wlc->hw->di[RX_FIFO]);
4215
4216 wlc_phy_watchdog(wlc_hw->band->pi);
4217 }
4218
4219 /* common watchdog code */
4220 static void brcms_c_watchdog(struct brcms_c_info *wlc)
4221 {
4222 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
4223
4224 if (!wlc->pub->up)
4225 return;
4226
4227 if (brcms_deviceremoved(wlc)) {
4228 wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n", wlc->pub->unit,
4229 __func__);
4230 brcms_down(wlc->wl);
4231 return;
4232 }
4233
4234 /* increment second count */
4235 wlc->pub->now++;
4236
4237 brcms_c_radio_hwdisable_upd(wlc);
4238 /* if radio is disable, driver may be down, quit here */
4239 if (wlc->pub->radio_disabled)
4240 return;
4241
4242 brcms_b_watchdog(wlc);
4243
4244 /*
4245 * occasionally sample mac stat counters to
4246 * detect 16-bit counter wrap
4247 */
4248 if ((wlc->pub->now % SW_TIMER_MAC_STAT_UPD) == 0)
4249 brcms_c_statsupd(wlc);
4250
4251 if (BRCMS_ISNPHY(wlc->band) &&
4252 ((wlc->pub->now - wlc->tempsense_lasttime) >=
4253 BRCMS_TEMPSENSE_PERIOD)) {
4254 wlc->tempsense_lasttime = wlc->pub->now;
4255 brcms_c_tempsense_upd(wlc);
4256 }
4257 }
4258
4259 static void brcms_c_watchdog_by_timer(void *arg)
4260 {
4261 struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
4262
4263 brcms_c_watchdog(wlc);
4264 }
4265
4266 static bool brcms_c_timers_init(struct brcms_c_info *wlc, int unit)
4267 {
4268 wlc->wdtimer = brcms_init_timer(wlc->wl, brcms_c_watchdog_by_timer,
4269 wlc, "watchdog");
4270 if (!wlc->wdtimer) {
4271 wiphy_err(wlc->wiphy, "wl%d: wl_init_timer for wdtimer "
4272 "failed\n", unit);
4273 goto fail;
4274 }
4275
4276 wlc->radio_timer = brcms_init_timer(wlc->wl, brcms_c_radio_timer,
4277 wlc, "radio");
4278 if (!wlc->radio_timer) {
4279 wiphy_err(wlc->wiphy, "wl%d: wl_init_timer for radio_timer "
4280 "failed\n", unit);
4281 goto fail;
4282 }
4283
4284 return true;
4285
4286 fail:
4287 return false;
4288 }
4289
4290 /*
4291 * Initialize brcms_c_info default values ...
4292 * may get overrides later in this function
4293 */
4294 static void brcms_c_info_init(struct brcms_c_info *wlc, int unit)
4295 {
4296 int i;
4297
4298 /* Save our copy of the chanspec */
4299 wlc->chanspec = ch20mhz_chspec(1);
4300
4301 /* various 802.11g modes */
4302 wlc->shortslot = false;
4303 wlc->shortslot_override = BRCMS_SHORTSLOT_AUTO;
4304
4305 brcms_c_protection_upd(wlc, BRCMS_PROT_G_OVR, BRCMS_PROTECTION_AUTO);
4306 brcms_c_protection_upd(wlc, BRCMS_PROT_G_SPEC, false);
4307
4308 brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG_OVR,
4309 BRCMS_PROTECTION_AUTO);
4310 brcms_c_protection_upd(wlc, BRCMS_PROT_N_CFG, BRCMS_N_PROTECTION_OFF);
4311 brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF_OVR,
4312 BRCMS_PROTECTION_AUTO);
4313 brcms_c_protection_upd(wlc, BRCMS_PROT_N_NONGF, false);
4314 brcms_c_protection_upd(wlc, BRCMS_PROT_N_PAM_OVR, AUTO);
4315
4316 brcms_c_protection_upd(wlc, BRCMS_PROT_OVERLAP,
4317 BRCMS_PROTECTION_CTL_OVERLAP);
4318
4319 /* 802.11g draft 4.0 NonERP elt advertisement */
4320 wlc->include_legacy_erp = true;
4321
4322 wlc->stf->ant_rx_ovr = ANT_RX_DIV_DEF;
4323 wlc->stf->txant = ANT_TX_DEF;
4324
4325 wlc->prb_resp_timeout = BRCMS_PRB_RESP_TIMEOUT;
4326
4327 wlc->usr_fragthresh = DOT11_DEFAULT_FRAG_LEN;
4328 for (i = 0; i < NFIFO; i++)
4329 wlc->fragthresh[i] = DOT11_DEFAULT_FRAG_LEN;
4330 wlc->RTSThresh = DOT11_DEFAULT_RTS_LEN;
4331
4332 /* default rate fallback retry limits */
4333 wlc->SFBL = RETRY_SHORT_FB;
4334 wlc->LFBL = RETRY_LONG_FB;
4335
4336 /* default mac retry limits */
4337 wlc->SRL = RETRY_SHORT_DEF;
4338 wlc->LRL = RETRY_LONG_DEF;
4339
4340 /* WME QoS mode is Auto by default */
4341 wlc->pub->_ampdu = AMPDU_AGG_HOST;
4342 wlc->pub->bcmerror = 0;
4343 }
4344
4345 static uint brcms_c_attach_module(struct brcms_c_info *wlc)
4346 {
4347 uint err = 0;
4348 uint unit;
4349 unit = wlc->pub->unit;
4350
4351 wlc->asi = brcms_c_antsel_attach(wlc);
4352 if (wlc->asi == NULL) {
4353 wiphy_err(wlc->wiphy, "wl%d: attach: antsel_attach "
4354 "failed\n", unit);
4355 err = 44;
4356 goto fail;
4357 }
4358
4359 wlc->ampdu = brcms_c_ampdu_attach(wlc);
4360 if (wlc->ampdu == NULL) {
4361 wiphy_err(wlc->wiphy, "wl%d: attach: ampdu_attach "
4362 "failed\n", unit);
4363 err = 50;
4364 goto fail;
4365 }
4366
4367 if ((brcms_c_stf_attach(wlc) != 0)) {
4368 wiphy_err(wlc->wiphy, "wl%d: attach: stf_attach "
4369 "failed\n", unit);
4370 err = 68;
4371 goto fail;
4372 }
4373 fail:
4374 return err;
4375 }
4376
4377 struct brcms_pub *brcms_c_pub(struct brcms_c_info *wlc)
4378 {
4379 return wlc->pub;
4380 }
4381
4382 /* low level attach
4383 * run backplane attach, init nvram
4384 * run phy attach
4385 * initialize software state for each core and band
4386 * put the whole chip in reset(driver down state), no clock
4387 */
4388 static int brcms_b_attach(struct brcms_c_info *wlc, struct bcma_device *core,
4389 uint unit, bool piomode)
4390 {
4391 struct brcms_hardware *wlc_hw;
4392 uint err = 0;
4393 uint j;
4394 bool wme = false;
4395 struct shared_phy_params sha_params;
4396 struct wiphy *wiphy = wlc->wiphy;
4397 struct pci_dev *pcidev = core->bus->host_pci;
4398 struct ssb_sprom *sprom = &core->bus->sprom;
4399
4400 if (core->bus->hosttype == BCMA_HOSTTYPE_PCI)
4401 BCMMSG(wlc->wiphy, "wl%d: vendor 0x%x device 0x%x\n", unit,
4402 pcidev->vendor,
4403 pcidev->device);
4404 else
4405 BCMMSG(wlc->wiphy, "wl%d: vendor 0x%x device 0x%x\n", unit,
4406 core->bus->boardinfo.vendor,
4407 core->bus->boardinfo.type);
4408
4409 wme = true;
4410
4411 wlc_hw = wlc->hw;
4412 wlc_hw->wlc = wlc;
4413 wlc_hw->unit = unit;
4414 wlc_hw->band = wlc_hw->bandstate[0];
4415 wlc_hw->_piomode = piomode;
4416
4417 /* populate struct brcms_hardware with default values */
4418 brcms_b_info_init(wlc_hw);
4419
4420 /*
4421 * Do the hardware portion of the attach. Also initialize software
4422 * state that depends on the particular hardware we are running.
4423 */
4424 wlc_hw->sih = ai_attach(core->bus);
4425 if (wlc_hw->sih == NULL) {
4426 wiphy_err(wiphy, "wl%d: brcms_b_attach: si_attach failed\n",
4427 unit);
4428 err = 11;
4429 goto fail;
4430 }
4431
4432 /* verify again the device is supported */
4433 if (!brcms_c_chipmatch(core)) {
4434 wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported device\n",
4435 unit);
4436 err = 12;
4437 goto fail;
4438 }
4439
4440 if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) {
4441 wlc_hw->vendorid = pcidev->vendor;
4442 wlc_hw->deviceid = pcidev->device;
4443 } else {
4444 wlc_hw->vendorid = core->bus->boardinfo.vendor;
4445 wlc_hw->deviceid = core->bus->boardinfo.type;
4446 }
4447
4448 wlc_hw->d11core = core;
4449 wlc_hw->corerev = core->id.rev;
4450
4451 /* validate chip, chiprev and corerev */
4452 if (!brcms_c_isgoodchip(wlc_hw)) {
4453 err = 13;
4454 goto fail;
4455 }
4456
4457 /* initialize power control registers */
4458 ai_clkctl_init(wlc_hw->sih);
4459
4460 /* request fastclock and force fastclock for the rest of attach
4461 * bring the d11 core out of reset.
4462 * For PMU chips, the first wlc_clkctl_clk is no-op since core-clk
4463 * is still false; But it will be called again inside wlc_corereset,
4464 * after d11 is out of reset.
4465 */
4466 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
4467 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
4468
4469 if (!brcms_b_validate_chip_access(wlc_hw)) {
4470 wiphy_err(wiphy, "wl%d: brcms_b_attach: validate_chip_access "
4471 "failed\n", unit);
4472 err = 14;
4473 goto fail;
4474 }
4475
4476 /* get the board rev, used just below */
4477 j = sprom->board_rev;
4478 /* promote srom boardrev of 0xFF to 1 */
4479 if (j == BOARDREV_PROMOTABLE)
4480 j = BOARDREV_PROMOTED;
4481 wlc_hw->boardrev = (u16) j;
4482 if (!brcms_c_validboardtype(wlc_hw)) {
4483 wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported Broadcom "
4484 "board type (0x%x)" " or revision level (0x%x)\n",
4485 unit, ai_get_boardtype(wlc_hw->sih),
4486 wlc_hw->boardrev);
4487 err = 15;
4488 goto fail;
4489 }
4490 wlc_hw->sromrev = sprom->revision;
4491 wlc_hw->boardflags = sprom->boardflags_lo + (sprom->boardflags_hi << 16);
4492 wlc_hw->boardflags2 = sprom->boardflags2_lo + (sprom->boardflags2_hi << 16);
4493
4494 if (wlc_hw->boardflags & BFL_NOPLLDOWN)
4495 brcms_b_pllreq(wlc_hw, true, BRCMS_PLLREQ_SHARED);
4496
4497 /* check device id(srom, nvram etc.) to set bands */
4498 if (wlc_hw->deviceid == BCM43224_D11N_ID ||
4499 wlc_hw->deviceid == BCM43224_D11N_ID_VEN1)
4500 /* Dualband boards */
4501 wlc_hw->_nbands = 2;
4502 else
4503 wlc_hw->_nbands = 1;
4504
4505 if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43225))
4506 wlc_hw->_nbands = 1;
4507
4508 /* BMAC_NOTE: remove init of pub values when brcms_c_attach()
4509 * unconditionally does the init of these values
4510 */
4511 wlc->vendorid = wlc_hw->vendorid;
4512 wlc->deviceid = wlc_hw->deviceid;
4513 wlc->pub->sih = wlc_hw->sih;
4514 wlc->pub->corerev = wlc_hw->corerev;
4515 wlc->pub->sromrev = wlc_hw->sromrev;
4516 wlc->pub->boardrev = wlc_hw->boardrev;
4517 wlc->pub->boardflags = wlc_hw->boardflags;
4518 wlc->pub->boardflags2 = wlc_hw->boardflags2;
4519 wlc->pub->_nbands = wlc_hw->_nbands;
4520
4521 wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
4522
4523 if (wlc_hw->physhim == NULL) {
4524 wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_shim_attach "
4525 "failed\n", unit);
4526 err = 25;
4527 goto fail;
4528 }
4529
4530 /* pass all the parameters to wlc_phy_shared_attach in one struct */
4531 sha_params.sih = wlc_hw->sih;
4532 sha_params.physhim = wlc_hw->physhim;
4533 sha_params.unit = unit;
4534 sha_params.corerev = wlc_hw->corerev;
4535 sha_params.vid = wlc_hw->vendorid;
4536 sha_params.did = wlc_hw->deviceid;
4537 sha_params.chip = ai_get_chip_id(wlc_hw->sih);
4538 sha_params.chiprev = ai_get_chiprev(wlc_hw->sih);
4539 sha_params.chippkg = ai_get_chippkg(wlc_hw->sih);
4540 sha_params.sromrev = wlc_hw->sromrev;
4541 sha_params.boardtype = ai_get_boardtype(wlc_hw->sih);
4542 sha_params.boardrev = wlc_hw->boardrev;
4543 sha_params.boardflags = wlc_hw->boardflags;
4544 sha_params.boardflags2 = wlc_hw->boardflags2;
4545
4546 /* alloc and save pointer to shared phy state area */
4547 wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
4548 if (!wlc_hw->phy_sh) {
4549 err = 16;
4550 goto fail;
4551 }
4552
4553 /* initialize software state for each core and band */
4554 for (j = 0; j < wlc_hw->_nbands; j++) {
4555 /*
4556 * band0 is always 2.4Ghz
4557 * band1, if present, is 5Ghz
4558 */
4559
4560 brcms_c_setxband(wlc_hw, j);
4561
4562 wlc_hw->band->bandunit = j;
4563 wlc_hw->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G;
4564 wlc->band->bandunit = j;
4565 wlc->band->bandtype = j ? BRCM_BAND_5G : BRCM_BAND_2G;
4566 wlc->core->coreidx = core->core_index;
4567
4568 wlc_hw->machwcap = bcma_read32(core, D11REGOFFS(machwcap));
4569 wlc_hw->machwcap_backup = wlc_hw->machwcap;
4570
4571 /* init tx fifo size */
4572 WARN_ON((wlc_hw->corerev - XMTFIFOTBL_STARTREV) < 0 ||
4573 (wlc_hw->corerev - XMTFIFOTBL_STARTREV) >
4574 ARRAY_SIZE(xmtfifo_sz));
4575 wlc_hw->xmtfifo_sz =
4576 xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
4577 WARN_ON(!wlc_hw->xmtfifo_sz[0]);
4578
4579 /* Get a phy for this band */
4580 wlc_hw->band->pi =
4581 wlc_phy_attach(wlc_hw->phy_sh, core,
4582 wlc_hw->band->bandtype,
4583 wlc->wiphy);
4584 if (wlc_hw->band->pi == NULL) {
4585 wiphy_err(wiphy, "wl%d: brcms_b_attach: wlc_phy_"
4586 "attach failed\n", unit);
4587 err = 17;
4588 goto fail;
4589 }
4590
4591 wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
4592
4593 wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
4594 &wlc_hw->band->phyrev,
4595 &wlc_hw->band->radioid,
4596 &wlc_hw->band->radiorev);
4597 wlc_hw->band->abgphy_encore =
4598 wlc_phy_get_encore(wlc_hw->band->pi);
4599 wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
4600 wlc_hw->band->core_flags =
4601 wlc_phy_get_coreflags(wlc_hw->band->pi);
4602
4603 /* verify good phy_type & supported phy revision */
4604 if (BRCMS_ISNPHY(wlc_hw->band)) {
4605 if (NCONF_HAS(wlc_hw->band->phyrev))
4606 goto good_phy;
4607 else
4608 goto bad_phy;
4609 } else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
4610 if (LCNCONF_HAS(wlc_hw->band->phyrev))
4611 goto good_phy;
4612 else
4613 goto bad_phy;
4614 } else {
4615 bad_phy:
4616 wiphy_err(wiphy, "wl%d: brcms_b_attach: unsupported "
4617 "phy type/rev (%d/%d)\n", unit,
4618 wlc_hw->band->phytype, wlc_hw->band->phyrev);
4619 err = 18;
4620 goto fail;
4621 }
4622
4623 good_phy:
4624 /*
4625 * BMAC_NOTE: wlc->band->pi should not be set below and should
4626 * be done in the high level attach. However we can not make
4627 * that change until all low level access is changed to
4628 * wlc_hw->band->pi. Instead do the wlc->band->pi init below,
4629 * keeping wlc_hw->band->pi as well for incremental update of
4630 * low level fns, and cut over low only init when all fns
4631 * updated.
4632 */
4633 wlc->band->pi = wlc_hw->band->pi;
4634 wlc->band->phytype = wlc_hw->band->phytype;
4635 wlc->band->phyrev = wlc_hw->band->phyrev;
4636 wlc->band->radioid = wlc_hw->band->radioid;
4637 wlc->band->radiorev = wlc_hw->band->radiorev;
4638
4639 /* default contention windows size limits */
4640 wlc_hw->band->CWmin = APHY_CWMIN;
4641 wlc_hw->band->CWmax = PHY_CWMAX;
4642
4643 if (!brcms_b_attach_dmapio(wlc, j, wme)) {
4644 err = 19;
4645 goto fail;
4646 }
4647 }
4648
4649 /* disable core to match driver "down" state */
4650 brcms_c_coredisable(wlc_hw);
4651
4652 /* Match driver "down" state */
4653 ai_pci_down(wlc_hw->sih);
4654
4655 /* turn off pll and xtal to match driver "down" state */
4656 brcms_b_xtal(wlc_hw, OFF);
4657
4658 /* *******************************************************************
4659 * The hardware is in the DOWN state at this point. D11 core
4660 * or cores are in reset with clocks off, and the board PLLs
4661 * are off if possible.
4662 *
4663 * Beyond this point, wlc->sbclk == false and chip registers
4664 * should not be touched.
4665 *********************************************************************
4666 */
4667
4668 /* init etheraddr state variables */
4669 brcms_c_get_macaddr(wlc_hw, wlc_hw->etheraddr);
4670
4671 if (is_broadcast_ether_addr(wlc_hw->etheraddr) ||
4672 is_zero_ether_addr(wlc_hw->etheraddr)) {
4673 wiphy_err(wiphy, "wl%d: brcms_b_attach: bad macaddr\n",
4674 unit);
4675 err = 22;
4676 goto fail;
4677 }
4678
4679 BCMMSG(wlc->wiphy, "deviceid 0x%x nbands %d board 0x%x\n",
4680 wlc_hw->deviceid, wlc_hw->_nbands, ai_get_boardtype(wlc_hw->sih));
4681
4682 return err;
4683
4684 fail:
4685 wiphy_err(wiphy, "wl%d: brcms_b_attach: failed with err %d\n", unit,
4686 err);
4687 return err;
4688 }
4689
4690 static void brcms_c_attach_antgain_init(struct brcms_c_info *wlc)
4691 {
4692 uint unit;
4693 unit = wlc->pub->unit;
4694
4695 if ((wlc->band->antgain == -1) && (wlc->pub->sromrev == 1)) {
4696 /* default antenna gain for srom rev 1 is 2 dBm (8 qdbm) */
4697 wlc->band->antgain = 8;
4698 } else if (wlc->band->antgain == -1) {
4699 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
4700 " srom, using 2dB\n", unit, __func__);
4701 wlc->band->antgain = 8;
4702 } else {
4703 s8 gain, fract;
4704 /* Older sroms specified gain in whole dbm only. In order
4705 * be able to specify qdbm granularity and remain backward
4706 * compatible the whole dbms are now encoded in only
4707 * low 6 bits and remaining qdbms are encoded in the hi 2 bits.
4708 * 6 bit signed number ranges from -32 - 31.
4709 *
4710 * Examples:
4711 * 0x1 = 1 db,
4712 * 0xc1 = 1.75 db (1 + 3 quarters),
4713 * 0x3f = -1 (-1 + 0 quarters),
4714 * 0x7f = -.75 (-1 + 1 quarters) = -3 qdbm.
4715 * 0xbf = -.50 (-1 + 2 quarters) = -2 qdbm.
4716 */
4717 gain = wlc->band->antgain & 0x3f;
4718 gain <<= 2; /* Sign extend */
4719 gain >>= 2;
4720 fract = (wlc->band->antgain & 0xc0) >> 6;
4721 wlc->band->antgain = 4 * gain + fract;
4722 }
4723 }
4724
4725 static bool brcms_c_attach_stf_ant_init(struct brcms_c_info *wlc)
4726 {
4727 int aa;
4728 uint unit;
4729 int bandtype;
4730 struct ssb_sprom *sprom = &wlc->hw->d11core->bus->sprom;
4731
4732 unit = wlc->pub->unit;
4733 bandtype = wlc->band->bandtype;
4734
4735 /* get antennas available */
4736 if (bandtype == BRCM_BAND_5G)
4737 aa = sprom->ant_available_a;
4738 else
4739 aa = sprom->ant_available_bg;
4740
4741 if ((aa < 1) || (aa > 15)) {
4742 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
4743 " srom (0x%x), using 3\n", unit, __func__, aa);
4744 aa = 3;
4745 }
4746
4747 /* reset the defaults if we have a single antenna */
4748 if (aa == 1) {
4749 wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_0;
4750 wlc->stf->txant = ANT_TX_FORCE_0;
4751 } else if (aa == 2) {
4752 wlc->stf->ant_rx_ovr = ANT_RX_DIV_FORCE_1;
4753 wlc->stf->txant = ANT_TX_FORCE_1;
4754 } else {
4755 }
4756
4757 /* Compute Antenna Gain */
4758 if (bandtype == BRCM_BAND_5G)
4759 wlc->band->antgain = sprom->antenna_gain.a1;
4760 else
4761 wlc->band->antgain = sprom->antenna_gain.a0;
4762
4763 brcms_c_attach_antgain_init(wlc);
4764
4765 return true;
4766 }
4767
4768 static void brcms_c_bss_default_init(struct brcms_c_info *wlc)
4769 {
4770 u16 chanspec;
4771 struct brcms_band *band;
4772 struct brcms_bss_info *bi = wlc->default_bss;
4773
4774 /* init default and target BSS with some sane initial values */
4775 memset((char *)(bi), 0, sizeof(struct brcms_bss_info));
4776 bi->beacon_period = BEACON_INTERVAL_DEFAULT;
4777
4778 /* fill the default channel as the first valid channel
4779 * starting from the 2G channels
4780 */
4781 chanspec = ch20mhz_chspec(1);
4782 wlc->home_chanspec = bi->chanspec = chanspec;
4783
4784 /* find the band of our default channel */
4785 band = wlc->band;
4786 if (wlc->pub->_nbands > 1 &&
4787 band->bandunit != chspec_bandunit(chanspec))
4788 band = wlc->bandstate[OTHERBANDUNIT(wlc)];
4789
4790 /* init bss rates to the band specific default rate set */
4791 brcms_c_rateset_default(&bi->rateset, NULL, band->phytype,
4792 band->bandtype, false, BRCMS_RATE_MASK_FULL,
4793 (bool) (wlc->pub->_n_enab & SUPPORT_11N),
4794 brcms_chspec_bw(chanspec), wlc->stf->txstreams);
4795
4796 if (wlc->pub->_n_enab & SUPPORT_11N)
4797 bi->flags |= BRCMS_BSS_HT;
4798 }
4799
4800 static struct brcms_txq_info *brcms_c_txq_alloc(struct brcms_c_info *wlc)
4801 {
4802 struct brcms_txq_info *qi, *p;
4803
4804 qi = kzalloc(sizeof(struct brcms_txq_info), GFP_ATOMIC);
4805 if (qi != NULL) {
4806 /*
4807 * Have enough room for control packets along with HI watermark
4808 * Also, add room to txq for total psq packets if all the SCBs
4809 * leave PS mode. The watermark for flowcontrol to OS packets
4810 * will remain the same
4811 */
4812 brcmu_pktq_init(&qi->q, BRCMS_PREC_COUNT,
4813 2 * BRCMS_DATAHIWAT + PKTQ_LEN_DEFAULT);
4814
4815 /* add this queue to the the global list */
4816 p = wlc->tx_queues;
4817 if (p == NULL) {
4818 wlc->tx_queues = qi;
4819 } else {
4820 while (p->next != NULL)
4821 p = p->next;
4822 p->next = qi;
4823 }
4824 }
4825 return qi;
4826 }
4827
4828 static void brcms_c_txq_free(struct brcms_c_info *wlc,
4829 struct brcms_txq_info *qi)
4830 {
4831 struct brcms_txq_info *p;
4832
4833 if (qi == NULL)
4834 return;
4835
4836 /* remove the queue from the linked list */
4837 p = wlc->tx_queues;
4838 if (p == qi)
4839 wlc->tx_queues = p->next;
4840 else {
4841 while (p != NULL && p->next != qi)
4842 p = p->next;
4843 if (p != NULL)
4844 p->next = p->next->next;
4845 }
4846
4847 kfree(qi);
4848 }
4849
4850 static void brcms_c_update_mimo_band_bwcap(struct brcms_c_info *wlc, u8 bwcap)
4851 {
4852 uint i;
4853 struct brcms_band *band;
4854
4855 for (i = 0; i < wlc->pub->_nbands; i++) {
4856 band = wlc->bandstate[i];
4857 if (band->bandtype == BRCM_BAND_5G) {
4858 if ((bwcap == BRCMS_N_BW_40ALL)
4859 || (bwcap == BRCMS_N_BW_20IN2G_40IN5G))
4860 band->mimo_cap_40 = true;
4861 else
4862 band->mimo_cap_40 = false;
4863 } else {
4864 if (bwcap == BRCMS_N_BW_40ALL)
4865 band->mimo_cap_40 = true;
4866 else
4867 band->mimo_cap_40 = false;
4868 }
4869 }
4870 }
4871
4872 static void brcms_c_timers_deinit(struct brcms_c_info *wlc)
4873 {
4874 /* free timer state */
4875 if (wlc->wdtimer) {
4876 brcms_free_timer(wlc->wdtimer);
4877 wlc->wdtimer = NULL;
4878 }
4879 if (wlc->radio_timer) {
4880 brcms_free_timer(wlc->radio_timer);
4881 wlc->radio_timer = NULL;
4882 }
4883 }
4884
4885 static void brcms_c_detach_module(struct brcms_c_info *wlc)
4886 {
4887 if (wlc->asi) {
4888 brcms_c_antsel_detach(wlc->asi);
4889 wlc->asi = NULL;
4890 }
4891
4892 if (wlc->ampdu) {
4893 brcms_c_ampdu_detach(wlc->ampdu);
4894 wlc->ampdu = NULL;
4895 }
4896
4897 brcms_c_stf_detach(wlc);
4898 }
4899
4900 /*
4901 * low level detach
4902 */
4903 static int brcms_b_detach(struct brcms_c_info *wlc)
4904 {
4905 uint i;
4906 struct brcms_hw_band *band;
4907 struct brcms_hardware *wlc_hw = wlc->hw;
4908 int callbacks;
4909
4910 callbacks = 0;
4911
4912 brcms_b_detach_dmapio(wlc_hw);
4913
4914 band = wlc_hw->band;
4915 for (i = 0; i < wlc_hw->_nbands; i++) {
4916 if (band->pi) {
4917 /* Detach this band's phy */
4918 wlc_phy_detach(band->pi);
4919 band->pi = NULL;
4920 }
4921 band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
4922 }
4923
4924 /* Free shared phy state */
4925 kfree(wlc_hw->phy_sh);
4926
4927 wlc_phy_shim_detach(wlc_hw->physhim);
4928
4929 if (wlc_hw->sih) {
4930 ai_detach(wlc_hw->sih);
4931 wlc_hw->sih = NULL;
4932 }
4933
4934 return callbacks;
4935
4936 }
4937
4938 /*
4939 * Return a count of the number of driver callbacks still pending.
4940 *
4941 * General policy is that brcms_c_detach can only dealloc/free software states.
4942 * It can NOT touch hardware registers since the d11core may be in reset and
4943 * clock may not be available.
4944 * One exception is sb register access, which is possible if crystal is turned
4945 * on after "down" state, driver should avoid software timer with the exception
4946 * of radio_monitor.
4947 */
4948 uint brcms_c_detach(struct brcms_c_info *wlc)
4949 {
4950 uint callbacks = 0;
4951
4952 if (wlc == NULL)
4953 return 0;
4954
4955 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
4956
4957 callbacks += brcms_b_detach(wlc);
4958
4959 /* delete software timers */
4960 if (!brcms_c_radio_monitor_stop(wlc))
4961 callbacks++;
4962
4963 brcms_c_channel_mgr_detach(wlc->cmi);
4964
4965 brcms_c_timers_deinit(wlc);
4966
4967 brcms_c_detach_module(wlc);
4968
4969
4970 while (wlc->tx_queues != NULL)
4971 brcms_c_txq_free(wlc, wlc->tx_queues);
4972
4973 brcms_c_detach_mfree(wlc);
4974 return callbacks;
4975 }
4976
4977 /* update state that depends on the current value of "ap" */
4978 static void brcms_c_ap_upd(struct brcms_c_info *wlc)
4979 {
4980 /* STA-BSS; short capable */
4981 wlc->PLCPHdr_override = BRCMS_PLCP_SHORT;
4982 }
4983
4984 /* Initialize just the hardware when coming out of POR or S3/S5 system states */
4985 static void brcms_b_hw_up(struct brcms_hardware *wlc_hw)
4986 {
4987 if (wlc_hw->wlc->pub->hw_up)
4988 return;
4989
4990 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
4991
4992 /*
4993 * Enable pll and xtal, initialize the power control registers,
4994 * and force fastclock for the remainder of brcms_c_up().
4995 */
4996 brcms_b_xtal(wlc_hw, ON);
4997 ai_clkctl_init(wlc_hw->sih);
4998 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
4999
5000 /*
5001 * TODO: test suspend/resume
5002 *
5003 * AI chip doesn't restore bar0win2 on
5004 * hibernation/resume, need sw fixup
5005 */
5006
5007 /*
5008 * Inform phy that a POR reset has occurred so
5009 * it does a complete phy init
5010 */
5011 wlc_phy_por_inform(wlc_hw->band->pi);
5012
5013 wlc_hw->ucode_loaded = false;
5014 wlc_hw->wlc->pub->hw_up = true;
5015
5016 if ((wlc_hw->boardflags & BFL_FEM)
5017 && (ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM4313)) {
5018 if (!
5019 (wlc_hw->boardrev >= 0x1250
5020 && (wlc_hw->boardflags & BFL_FEM_BT)))
5021 ai_epa_4313war(wlc_hw->sih);
5022 }
5023 }
5024
5025 static int brcms_b_up_prep(struct brcms_hardware *wlc_hw)
5026 {
5027 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
5028
5029 /*
5030 * Enable pll and xtal, initialize the power control registers,
5031 * and force fastclock for the remainder of brcms_c_up().
5032 */
5033 brcms_b_xtal(wlc_hw, ON);
5034 ai_clkctl_init(wlc_hw->sih);
5035 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
5036
5037 /*
5038 * Configure pci/pcmcia here instead of in brcms_c_attach()
5039 * to allow mfg hotswap: down, hotswap (chip power cycle), up.
5040 */
5041 bcma_core_pci_irq_ctl(&wlc_hw->d11core->bus->drv_pci[0], wlc_hw->d11core,
5042 true);
5043
5044 /*
5045 * Need to read the hwradio status here to cover the case where the
5046 * system is loaded with the hw radio disabled. We do not want to
5047 * bring the driver up in this case.
5048 */
5049 if (brcms_b_radio_read_hwdisabled(wlc_hw)) {
5050 /* put SB PCI in down state again */
5051 ai_pci_down(wlc_hw->sih);
5052 brcms_b_xtal(wlc_hw, OFF);
5053 return -ENOMEDIUM;
5054 }
5055
5056 ai_pci_up(wlc_hw->sih);
5057
5058 /* reset the d11 core */
5059 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
5060
5061 return 0;
5062 }
5063
5064 static int brcms_b_up_finish(struct brcms_hardware *wlc_hw)
5065 {
5066 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
5067
5068 wlc_hw->up = true;
5069 wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
5070
5071 /* FULLY enable dynamic power control and d11 core interrupt */
5072 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
5073 brcms_intrson(wlc_hw->wlc->wl);
5074 return 0;
5075 }
5076
5077 /*
5078 * Write WME tunable parameters for retransmit/max rate
5079 * from wlc struct to ucode
5080 */
5081 static void brcms_c_wme_retries_write(struct brcms_c_info *wlc)
5082 {
5083 int ac;
5084
5085 /* Need clock to do this */
5086 if (!wlc->clk)
5087 return;
5088
5089 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
5090 brcms_b_write_shm(wlc->hw, M_AC_TXLMT_ADDR(ac),
5091 wlc->wme_retries[ac]);
5092 }
5093
5094 /* make interface operational */
5095 int brcms_c_up(struct brcms_c_info *wlc)
5096 {
5097 struct ieee80211_channel *ch;
5098
5099 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
5100
5101 /* HW is turned off so don't try to access it */
5102 if (wlc->pub->hw_off || brcms_deviceremoved(wlc))
5103 return -ENOMEDIUM;
5104
5105 if (!wlc->pub->hw_up) {
5106 brcms_b_hw_up(wlc->hw);
5107 wlc->pub->hw_up = true;
5108 }
5109
5110 if ((wlc->pub->boardflags & BFL_FEM)
5111 && (ai_get_chip_id(wlc->hw->sih) == BCMA_CHIP_ID_BCM4313)) {
5112 if (wlc->pub->boardrev >= 0x1250
5113 && (wlc->pub->boardflags & BFL_FEM_BT))
5114 brcms_b_mhf(wlc->hw, MHF5, MHF5_4313_GPIOCTRL,
5115 MHF5_4313_GPIOCTRL, BRCM_BAND_ALL);
5116 else
5117 brcms_b_mhf(wlc->hw, MHF4, MHF4_EXTPA_ENABLE,
5118 MHF4_EXTPA_ENABLE, BRCM_BAND_ALL);
5119 }
5120
5121 /*
5122 * Need to read the hwradio status here to cover the case where the
5123 * system is loaded with the hw radio disabled. We do not want to bring
5124 * the driver up in this case. If radio is disabled, abort up, lower
5125 * power, start radio timer and return 0(for NDIS) don't call
5126 * radio_update to avoid looping brcms_c_up.
5127 *
5128 * brcms_b_up_prep() returns either 0 or -BCME_RADIOOFF only
5129 */
5130 if (!wlc->pub->radio_disabled) {
5131 int status = brcms_b_up_prep(wlc->hw);
5132 if (status == -ENOMEDIUM) {
5133 if (!mboolisset
5134 (wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE)) {
5135 struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
5136 mboolset(wlc->pub->radio_disabled,
5137 WL_RADIO_HW_DISABLE);
5138
5139 if (bsscfg->enable && bsscfg->BSS)
5140 wiphy_err(wlc->wiphy, "wl%d: up"
5141 ": rfdisable -> "
5142 "bsscfg_disable()\n",
5143 wlc->pub->unit);
5144 }
5145 }
5146 }
5147
5148 if (wlc->pub->radio_disabled) {
5149 brcms_c_radio_monitor_start(wlc);
5150 return 0;
5151 }
5152
5153 /* brcms_b_up_prep has done brcms_c_corereset(). so clk is on, set it */
5154 wlc->clk = true;
5155
5156 brcms_c_radio_monitor_stop(wlc);
5157
5158 /* Set EDCF hostflags */
5159 brcms_b_mhf(wlc->hw, MHF1, MHF1_EDCF, MHF1_EDCF, BRCM_BAND_ALL);
5160
5161 brcms_init(wlc->wl);
5162 wlc->pub->up = true;
5163
5164 if (wlc->bandinit_pending) {
5165 ch = wlc->pub->ieee_hw->conf.channel;
5166 brcms_c_suspend_mac_and_wait(wlc);
5167 brcms_c_set_chanspec(wlc, ch20mhz_chspec(ch->hw_value));
5168 wlc->bandinit_pending = false;
5169 brcms_c_enable_mac(wlc);
5170 }
5171
5172 brcms_b_up_finish(wlc->hw);
5173
5174 /* Program the TX wme params with the current settings */
5175 brcms_c_wme_retries_write(wlc);
5176
5177 /* start one second watchdog timer */
5178 brcms_add_timer(wlc->wdtimer, TIMER_INTERVAL_WATCHDOG, true);
5179 wlc->WDarmed = true;
5180
5181 /* ensure antenna config is up to date */
5182 brcms_c_stf_phy_txant_upd(wlc);
5183 /* ensure LDPC config is in sync */
5184 brcms_c_ht_update_ldpc(wlc, wlc->stf->ldpc);
5185
5186 return 0;
5187 }
5188
5189 static uint brcms_c_down_del_timer(struct brcms_c_info *wlc)
5190 {
5191 uint callbacks = 0;
5192
5193 return callbacks;
5194 }
5195
5196 static int brcms_b_bmac_down_prep(struct brcms_hardware *wlc_hw)
5197 {
5198 bool dev_gone;
5199 uint callbacks = 0;
5200
5201 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
5202
5203 if (!wlc_hw->up)
5204 return callbacks;
5205
5206 dev_gone = brcms_deviceremoved(wlc_hw->wlc);
5207
5208 /* disable interrupts */
5209 if (dev_gone)
5210 wlc_hw->wlc->macintmask = 0;
5211 else {
5212 /* now disable interrupts */
5213 brcms_intrsoff(wlc_hw->wlc->wl);
5214
5215 /* ensure we're running on the pll clock again */
5216 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
5217 }
5218 /* down phy at the last of this stage */
5219 callbacks += wlc_phy_down(wlc_hw->band->pi);
5220
5221 return callbacks;
5222 }
5223
5224 static int brcms_b_down_finish(struct brcms_hardware *wlc_hw)
5225 {
5226 uint callbacks = 0;
5227 bool dev_gone;
5228
5229 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
5230
5231 if (!wlc_hw->up)
5232 return callbacks;
5233
5234 wlc_hw->up = false;
5235 wlc_phy_hw_state_upd(wlc_hw->band->pi, false);
5236
5237 dev_gone = brcms_deviceremoved(wlc_hw->wlc);
5238
5239 if (dev_gone) {
5240 wlc_hw->sbclk = false;
5241 wlc_hw->clk = false;
5242 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
5243
5244 /* reclaim any posted packets */
5245 brcms_c_flushqueues(wlc_hw->wlc);
5246 } else {
5247
5248 /* Reset and disable the core */
5249 if (bcma_core_is_enabled(wlc_hw->d11core)) {
5250 if (bcma_read32(wlc_hw->d11core,
5251 D11REGOFFS(maccontrol)) & MCTL_EN_MAC)
5252 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
5253 callbacks += brcms_reset(wlc_hw->wlc->wl);
5254 brcms_c_coredisable(wlc_hw);
5255 }
5256
5257 /* turn off primary xtal and pll */
5258 if (!wlc_hw->noreset) {
5259 ai_pci_down(wlc_hw->sih);
5260 brcms_b_xtal(wlc_hw, OFF);
5261 }
5262 }
5263
5264 return callbacks;
5265 }
5266
5267 /*
5268 * Mark the interface nonoperational, stop the software mechanisms,
5269 * disable the hardware, free any transient buffer state.
5270 * Return a count of the number of driver callbacks still pending.
5271 */
5272 uint brcms_c_down(struct brcms_c_info *wlc)
5273 {
5274
5275 uint callbacks = 0;
5276 int i;
5277 bool dev_gone = false;
5278 struct brcms_txq_info *qi;
5279
5280 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
5281
5282 /* check if we are already in the going down path */
5283 if (wlc->going_down) {
5284 wiphy_err(wlc->wiphy, "wl%d: %s: Driver going down so return"
5285 "\n", wlc->pub->unit, __func__);
5286 return 0;
5287 }
5288 if (!wlc->pub->up)
5289 return callbacks;
5290
5291 wlc->going_down = true;
5292
5293 callbacks += brcms_b_bmac_down_prep(wlc->hw);
5294
5295 dev_gone = brcms_deviceremoved(wlc);
5296
5297 /* Call any registered down handlers */
5298 for (i = 0; i < BRCMS_MAXMODULES; i++) {
5299 if (wlc->modulecb[i].down_fn)
5300 callbacks +=
5301 wlc->modulecb[i].down_fn(wlc->modulecb[i].hdl);
5302 }
5303
5304 /* cancel the watchdog timer */
5305 if (wlc->WDarmed) {
5306 if (!brcms_del_timer(wlc->wdtimer))
5307 callbacks++;
5308 wlc->WDarmed = false;
5309 }
5310 /* cancel all other timers */
5311 callbacks += brcms_c_down_del_timer(wlc);
5312
5313 wlc->pub->up = false;
5314
5315 wlc_phy_mute_upd(wlc->band->pi, false, PHY_MUTE_ALL);
5316
5317 /* flush tx queues */
5318 for (qi = wlc->tx_queues; qi != NULL; qi = qi->next)
5319 brcmu_pktq_flush(&qi->q, true, NULL, NULL);
5320
5321 callbacks += brcms_b_down_finish(wlc->hw);
5322
5323 /* brcms_b_down_finish has done brcms_c_coredisable(). so clk is off */
5324 wlc->clk = false;
5325
5326 wlc->going_down = false;
5327 return callbacks;
5328 }
5329
5330 /* Set the current gmode configuration */
5331 int brcms_c_set_gmode(struct brcms_c_info *wlc, u8 gmode, bool config)
5332 {
5333 int ret = 0;
5334 uint i;
5335 struct brcms_c_rateset rs;
5336 /* Default to 54g Auto */
5337 /* Advertise and use shortslot (-1/0/1 Auto/Off/On) */
5338 s8 shortslot = BRCMS_SHORTSLOT_AUTO;
5339 bool shortslot_restrict = false; /* Restrict association to stations
5340 * that support shortslot
5341 */
5342 bool ofdm_basic = false; /* Make 6, 12, and 24 basic rates */
5343 /* Advertise and use short preambles (-1/0/1 Auto/Off/On) */
5344 int preamble = BRCMS_PLCP_LONG;
5345 bool preamble_restrict = false; /* Restrict association to stations
5346 * that support short preambles
5347 */
5348 struct brcms_band *band;
5349
5350 /* if N-support is enabled, allow Gmode set as long as requested
5351 * Gmode is not GMODE_LEGACY_B
5352 */
5353 if ((wlc->pub->_n_enab & SUPPORT_11N) && gmode == GMODE_LEGACY_B)
5354 return -ENOTSUPP;
5355
5356 /* verify that we are dealing with 2G band and grab the band pointer */
5357 if (wlc->band->bandtype == BRCM_BAND_2G)
5358 band = wlc->band;
5359 else if ((wlc->pub->_nbands > 1) &&
5360 (wlc->bandstate[OTHERBANDUNIT(wlc)]->bandtype == BRCM_BAND_2G))
5361 band = wlc->bandstate[OTHERBANDUNIT(wlc)];
5362 else
5363 return -EINVAL;
5364
5365 /* update configuration value */
5366 if (config)
5367 brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER, gmode);
5368
5369 /* Clear rateset override */
5370 memset(&rs, 0, sizeof(struct brcms_c_rateset));
5371
5372 switch (gmode) {
5373 case GMODE_LEGACY_B:
5374 shortslot = BRCMS_SHORTSLOT_OFF;
5375 brcms_c_rateset_copy(&gphy_legacy_rates, &rs);
5376
5377 break;
5378
5379 case GMODE_LRS:
5380 break;
5381
5382 case GMODE_AUTO:
5383 /* Accept defaults */
5384 break;
5385
5386 case GMODE_ONLY:
5387 ofdm_basic = true;
5388 preamble = BRCMS_PLCP_SHORT;
5389 preamble_restrict = true;
5390 break;
5391
5392 case GMODE_PERFORMANCE:
5393 shortslot = BRCMS_SHORTSLOT_ON;
5394 shortslot_restrict = true;
5395 ofdm_basic = true;
5396 preamble = BRCMS_PLCP_SHORT;
5397 preamble_restrict = true;
5398 break;
5399
5400 default:
5401 /* Error */
5402 wiphy_err(wlc->wiphy, "wl%d: %s: invalid gmode %d\n",
5403 wlc->pub->unit, __func__, gmode);
5404 return -ENOTSUPP;
5405 }
5406
5407 band->gmode = gmode;
5408
5409 wlc->shortslot_override = shortslot;
5410
5411 /* Use the default 11g rateset */
5412 if (!rs.count)
5413 brcms_c_rateset_copy(&cck_ofdm_rates, &rs);
5414
5415 if (ofdm_basic) {
5416 for (i = 0; i < rs.count; i++) {
5417 if (rs.rates[i] == BRCM_RATE_6M
5418 || rs.rates[i] == BRCM_RATE_12M
5419 || rs.rates[i] == BRCM_RATE_24M)
5420 rs.rates[i] |= BRCMS_RATE_FLAG;
5421 }
5422 }
5423
5424 /* Set default bss rateset */
5425 wlc->default_bss->rateset.count = rs.count;
5426 memcpy(wlc->default_bss->rateset.rates, rs.rates,
5427 sizeof(wlc->default_bss->rateset.rates));
5428
5429 return ret;
5430 }
5431
5432 int brcms_c_set_nmode(struct brcms_c_info *wlc)
5433 {
5434 uint i;
5435 s32 nmode = AUTO;
5436
5437 if (wlc->stf->txstreams == WL_11N_3x3)
5438 nmode = WL_11N_3x3;
5439 else
5440 nmode = WL_11N_2x2;
5441
5442 /* force GMODE_AUTO if NMODE is ON */
5443 brcms_c_set_gmode(wlc, GMODE_AUTO, true);
5444 if (nmode == WL_11N_3x3)
5445 wlc->pub->_n_enab = SUPPORT_HT;
5446 else
5447 wlc->pub->_n_enab = SUPPORT_11N;
5448 wlc->default_bss->flags |= BRCMS_BSS_HT;
5449 /* add the mcs rates to the default and hw ratesets */
5450 brcms_c_rateset_mcs_build(&wlc->default_bss->rateset,
5451 wlc->stf->txstreams);
5452 for (i = 0; i < wlc->pub->_nbands; i++)
5453 memcpy(wlc->bandstate[i]->hw_rateset.mcs,
5454 wlc->default_bss->rateset.mcs, MCSSET_LEN);
5455
5456 return 0;
5457 }
5458
5459 static int
5460 brcms_c_set_internal_rateset(struct brcms_c_info *wlc,
5461 struct brcms_c_rateset *rs_arg)
5462 {
5463 struct brcms_c_rateset rs, new;
5464 uint bandunit;
5465
5466 memcpy(&rs, rs_arg, sizeof(struct brcms_c_rateset));
5467
5468 /* check for bad count value */
5469 if ((rs.count == 0) || (rs.count > BRCMS_NUMRATES))
5470 return -EINVAL;
5471
5472 /* try the current band */
5473 bandunit = wlc->band->bandunit;
5474 memcpy(&new, &rs, sizeof(struct brcms_c_rateset));
5475 if (brcms_c_rate_hwrs_filter_sort_validate
5476 (&new, &wlc->bandstate[bandunit]->hw_rateset, true,
5477 wlc->stf->txstreams))
5478 goto good;
5479
5480 /* try the other band */
5481 if (brcms_is_mband_unlocked(wlc)) {
5482 bandunit = OTHERBANDUNIT(wlc);
5483 memcpy(&new, &rs, sizeof(struct brcms_c_rateset));
5484 if (brcms_c_rate_hwrs_filter_sort_validate(&new,
5485 &wlc->
5486 bandstate[bandunit]->
5487 hw_rateset, true,
5488 wlc->stf->txstreams))
5489 goto good;
5490 }
5491
5492 return -EBADE;
5493
5494 good:
5495 /* apply new rateset */
5496 memcpy(&wlc->default_bss->rateset, &new,
5497 sizeof(struct brcms_c_rateset));
5498 memcpy(&wlc->bandstate[bandunit]->defrateset, &new,
5499 sizeof(struct brcms_c_rateset));
5500 return 0;
5501 }
5502
5503 static void brcms_c_ofdm_rateset_war(struct brcms_c_info *wlc)
5504 {
5505 u8 r;
5506 bool war = false;
5507
5508 if (wlc->bsscfg->associated)
5509 r = wlc->bsscfg->current_bss->rateset.rates[0];
5510 else
5511 r = wlc->default_bss->rateset.rates[0];
5512
5513 wlc_phy_ofdm_rateset_war(wlc->band->pi, war);
5514 }
5515
5516 int brcms_c_set_channel(struct brcms_c_info *wlc, u16 channel)
5517 {
5518 u16 chspec = ch20mhz_chspec(channel);
5519
5520 if (channel < 0 || channel > MAXCHANNEL)
5521 return -EINVAL;
5522
5523 if (!brcms_c_valid_chanspec_db(wlc->cmi, chspec))
5524 return -EINVAL;
5525
5526
5527 if (!wlc->pub->up && brcms_is_mband_unlocked(wlc)) {
5528 if (wlc->band->bandunit != chspec_bandunit(chspec))
5529 wlc->bandinit_pending = true;
5530 else
5531 wlc->bandinit_pending = false;
5532 }
5533
5534 wlc->default_bss->chanspec = chspec;
5535 /* brcms_c_BSSinit() will sanitize the rateset before
5536 * using it.. */
5537 if (wlc->pub->up && (wlc_phy_chanspec_get(wlc->band->pi) != chspec)) {
5538 brcms_c_set_home_chanspec(wlc, chspec);
5539 brcms_c_suspend_mac_and_wait(wlc);
5540 brcms_c_set_chanspec(wlc, chspec);
5541 brcms_c_enable_mac(wlc);
5542 }
5543 return 0;
5544 }
5545
5546 int brcms_c_set_rate_limit(struct brcms_c_info *wlc, u16 srl, u16 lrl)
5547 {
5548 int ac;
5549
5550 if (srl < 1 || srl > RETRY_SHORT_MAX ||
5551 lrl < 1 || lrl > RETRY_SHORT_MAX)
5552 return -EINVAL;
5553
5554 wlc->SRL = srl;
5555 wlc->LRL = lrl;
5556
5557 brcms_b_retrylimit_upd(wlc->hw, wlc->SRL, wlc->LRL);
5558
5559 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) {
5560 wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac],
5561 EDCF_SHORT, wlc->SRL);
5562 wlc->wme_retries[ac] = SFIELD(wlc->wme_retries[ac],
5563 EDCF_LONG, wlc->LRL);
5564 }
5565 brcms_c_wme_retries_write(wlc);
5566
5567 return 0;
5568 }
5569
5570 void brcms_c_get_current_rateset(struct brcms_c_info *wlc,
5571 struct brcm_rateset *currs)
5572 {
5573 struct brcms_c_rateset *rs;
5574
5575 if (wlc->pub->associated)
5576 rs = &wlc->bsscfg->current_bss->rateset;
5577 else
5578 rs = &wlc->default_bss->rateset;
5579
5580 /* Copy only legacy rateset section */
5581 currs->count = rs->count;
5582 memcpy(&currs->rates, &rs->rates, rs->count);
5583 }
5584
5585 int brcms_c_set_rateset(struct brcms_c_info *wlc, struct brcm_rateset *rs)
5586 {
5587 struct brcms_c_rateset internal_rs;
5588 int bcmerror;
5589
5590 if (rs->count > BRCMS_NUMRATES)
5591 return -ENOBUFS;
5592
5593 memset(&internal_rs, 0, sizeof(struct brcms_c_rateset));
5594
5595 /* Copy only legacy rateset section */
5596 internal_rs.count = rs->count;
5597 memcpy(&internal_rs.rates, &rs->rates, internal_rs.count);
5598
5599 /* merge rateset coming in with the current mcsset */
5600 if (wlc->pub->_n_enab & SUPPORT_11N) {
5601 struct brcms_bss_info *mcsset_bss;
5602 if (wlc->bsscfg->associated)
5603 mcsset_bss = wlc->bsscfg->current_bss;
5604 else
5605 mcsset_bss = wlc->default_bss;
5606 memcpy(internal_rs.mcs, &mcsset_bss->rateset.mcs[0],
5607 MCSSET_LEN);
5608 }
5609
5610 bcmerror = brcms_c_set_internal_rateset(wlc, &internal_rs);
5611 if (!bcmerror)
5612 brcms_c_ofdm_rateset_war(wlc);
5613
5614 return bcmerror;
5615 }
5616
5617 int brcms_c_set_beacon_period(struct brcms_c_info *wlc, u16 period)
5618 {
5619 if (period < DOT11_MIN_BEACON_PERIOD ||
5620 period > DOT11_MAX_BEACON_PERIOD)
5621 return -EINVAL;
5622
5623 wlc->default_bss->beacon_period = period;
5624 return 0;
5625 }
5626
5627 u16 brcms_c_get_phy_type(struct brcms_c_info *wlc, int phyidx)
5628 {
5629 return wlc->band->phytype;
5630 }
5631
5632 void brcms_c_set_shortslot_override(struct brcms_c_info *wlc, s8 sslot_override)
5633 {
5634 wlc->shortslot_override = sslot_override;
5635
5636 /*
5637 * shortslot is an 11g feature, so no more work if we are
5638 * currently on the 5G band
5639 */
5640 if (wlc->band->bandtype == BRCM_BAND_5G)
5641 return;
5642
5643 if (wlc->pub->up && wlc->pub->associated) {
5644 /* let watchdog or beacon processing update shortslot */
5645 } else if (wlc->pub->up) {
5646 /* unassociated shortslot is off */
5647 brcms_c_switch_shortslot(wlc, false);
5648 } else {
5649 /* driver is down, so just update the brcms_c_info
5650 * value */
5651 if (wlc->shortslot_override == BRCMS_SHORTSLOT_AUTO)
5652 wlc->shortslot = false;
5653 else
5654 wlc->shortslot =
5655 (wlc->shortslot_override ==
5656 BRCMS_SHORTSLOT_ON);
5657 }
5658 }
5659
5660 /*
5661 * register watchdog and down handlers.
5662 */
5663 int brcms_c_module_register(struct brcms_pub *pub,
5664 const char *name, struct brcms_info *hdl,
5665 int (*d_fn)(void *handle))
5666 {
5667 struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc;
5668 int i;
5669
5670 /* find an empty entry and just add, no duplication check! */
5671 for (i = 0; i < BRCMS_MAXMODULES; i++) {
5672 if (wlc->modulecb[i].name[0] == '\0') {
5673 strncpy(wlc->modulecb[i].name, name,
5674 sizeof(wlc->modulecb[i].name) - 1);
5675 wlc->modulecb[i].hdl = hdl;
5676 wlc->modulecb[i].down_fn = d_fn;
5677 return 0;
5678 }
5679 }
5680
5681 return -ENOSR;
5682 }
5683
5684 /* unregister module callbacks */
5685 int brcms_c_module_unregister(struct brcms_pub *pub, const char *name,
5686 struct brcms_info *hdl)
5687 {
5688 struct brcms_c_info *wlc = (struct brcms_c_info *) pub->wlc;
5689 int i;
5690
5691 if (wlc == NULL)
5692 return -ENODATA;
5693
5694 for (i = 0; i < BRCMS_MAXMODULES; i++) {
5695 if (!strcmp(wlc->modulecb[i].name, name) &&
5696 (wlc->modulecb[i].hdl == hdl)) {
5697 memset(&wlc->modulecb[i], 0, sizeof(struct modulecb));
5698 return 0;
5699 }
5700 }
5701
5702 /* table not found! */
5703 return -ENODATA;
5704 }
5705
5706 void brcms_c_print_txstatus(struct tx_status *txs)
5707 {
5708 pr_debug("\ntxpkt (MPDU) Complete\n");
5709
5710 pr_debug("FrameID: %04x TxStatus: %04x\n", txs->frameid, txs->status);
5711
5712 pr_debug("[15:12] %d frame attempts\n",
5713 (txs->status & TX_STATUS_FRM_RTX_MASK) >>
5714 TX_STATUS_FRM_RTX_SHIFT);
5715 pr_debug(" [11:8] %d rts attempts\n",
5716 (txs->status & TX_STATUS_RTS_RTX_MASK) >>
5717 TX_STATUS_RTS_RTX_SHIFT);
5718 pr_debug(" [7] %d PM mode indicated\n",
5719 txs->status & TX_STATUS_PMINDCTD ? 1 : 0);
5720 pr_debug(" [6] %d intermediate status\n",
5721 txs->status & TX_STATUS_INTERMEDIATE ? 1 : 0);
5722 pr_debug(" [5] %d AMPDU\n",
5723 txs->status & TX_STATUS_AMPDU ? 1 : 0);
5724 pr_debug(" [4:2] %d Frame Suppressed Reason (%s)\n",
5725 (txs->status & TX_STATUS_SUPR_MASK) >> TX_STATUS_SUPR_SHIFT,
5726 (const char *[]) {
5727 "None",
5728 "PMQ Entry",
5729 "Flush request",
5730 "Previous frag failure",
5731 "Channel mismatch",
5732 "Lifetime Expiry",
5733 "Underflow"
5734 } [(txs->status & TX_STATUS_SUPR_MASK) >>
5735 TX_STATUS_SUPR_SHIFT]);
5736 pr_debug(" [1] %d acked\n",
5737 txs->status & TX_STATUS_ACK_RCV ? 1 : 0);
5738
5739 pr_debug("LastTxTime: %04x Seq: %04x PHYTxStatus: %04x RxAckRSSI: %04x RxAckSQ: %04x\n",
5740 txs->lasttxtime, txs->sequence, txs->phyerr,
5741 (txs->ackphyrxsh & PRXS1_JSSI_MASK) >> PRXS1_JSSI_SHIFT,
5742 (txs->ackphyrxsh & PRXS1_SQ_MASK) >> PRXS1_SQ_SHIFT);
5743 }
5744
5745 static bool brcms_c_chipmatch_pci(struct bcma_device *core)
5746 {
5747 struct pci_dev *pcidev = core->bus->host_pci;
5748 u16 vendor = pcidev->vendor;
5749 u16 device = pcidev->device;
5750
5751 if (vendor != PCI_VENDOR_ID_BROADCOM) {
5752 pr_err("unknown vendor id %04x\n", vendor);
5753 return false;
5754 }
5755
5756 if (device == BCM43224_D11N_ID_VEN1)
5757 return true;
5758 if ((device == BCM43224_D11N_ID) || (device == BCM43225_D11N2G_ID))
5759 return true;
5760 if (device == BCM4313_D11N2G_ID)
5761 return true;
5762 if ((device == BCM43236_D11N_ID) || (device == BCM43236_D11N2G_ID))
5763 return true;
5764
5765 pr_err("unknown device id %04x\n", device);
5766 return false;
5767 }
5768
5769 static bool brcms_c_chipmatch_soc(struct bcma_device *core)
5770 {
5771 struct bcma_chipinfo *chipinfo = &core->bus->chipinfo;
5772
5773 if (chipinfo->id == BCMA_CHIP_ID_BCM4716)
5774 return true;
5775
5776 pr_err("unknown chip id %04x\n", chipinfo->id);
5777 return false;
5778 }
5779
5780 bool brcms_c_chipmatch(struct bcma_device *core)
5781 {
5782 switch (core->bus->hosttype) {
5783 case BCMA_HOSTTYPE_PCI:
5784 return brcms_c_chipmatch_pci(core);
5785 case BCMA_HOSTTYPE_SOC:
5786 return brcms_c_chipmatch_soc(core);
5787 default:
5788 pr_err("unknown host type: %i\n", core->bus->hosttype);
5789 return false;
5790 }
5791 }
5792
5793 #if defined(DEBUG)
5794 void brcms_c_print_txdesc(struct d11txh *txh)
5795 {
5796 u16 mtcl = le16_to_cpu(txh->MacTxControlLow);
5797 u16 mtch = le16_to_cpu(txh->MacTxControlHigh);
5798 u16 mfc = le16_to_cpu(txh->MacFrameControl);
5799 u16 tfest = le16_to_cpu(txh->TxFesTimeNormal);
5800 u16 ptcw = le16_to_cpu(txh->PhyTxControlWord);
5801 u16 ptcw_1 = le16_to_cpu(txh->PhyTxControlWord_1);
5802 u16 ptcw_1_Fbr = le16_to_cpu(txh->PhyTxControlWord_1_Fbr);
5803 u16 ptcw_1_Rts = le16_to_cpu(txh->PhyTxControlWord_1_Rts);
5804 u16 ptcw_1_FbrRts = le16_to_cpu(txh->PhyTxControlWord_1_FbrRts);
5805 u16 mainrates = le16_to_cpu(txh->MainRates);
5806 u16 xtraft = le16_to_cpu(txh->XtraFrameTypes);
5807 u8 *iv = txh->IV;
5808 u8 *ra = txh->TxFrameRA;
5809 u16 tfestfb = le16_to_cpu(txh->TxFesTimeFallback);
5810 u8 *rtspfb = txh->RTSPLCPFallback;
5811 u16 rtsdfb = le16_to_cpu(txh->RTSDurFallback);
5812 u8 *fragpfb = txh->FragPLCPFallback;
5813 u16 fragdfb = le16_to_cpu(txh->FragDurFallback);
5814 u16 mmodelen = le16_to_cpu(txh->MModeLen);
5815 u16 mmodefbrlen = le16_to_cpu(txh->MModeFbrLen);
5816 u16 tfid = le16_to_cpu(txh->TxFrameID);
5817 u16 txs = le16_to_cpu(txh->TxStatus);
5818 u16 mnmpdu = le16_to_cpu(txh->MaxNMpdus);
5819 u16 mabyte = le16_to_cpu(txh->MaxABytes_MRT);
5820 u16 mabyte_f = le16_to_cpu(txh->MaxABytes_FBR);
5821 u16 mmbyte = le16_to_cpu(txh->MinMBytes);
5822
5823 u8 *rtsph = txh->RTSPhyHeader;
5824 struct ieee80211_rts rts = txh->rts_frame;
5825
5826 /* add plcp header along with txh descriptor */
5827 brcmu_dbg_hex_dump(txh, sizeof(struct d11txh) + 48,
5828 "Raw TxDesc + plcp header:\n");
5829
5830 pr_debug("TxCtlLow: %04x ", mtcl);
5831 pr_debug("TxCtlHigh: %04x ", mtch);
5832 pr_debug("FC: %04x ", mfc);
5833 pr_debug("FES Time: %04x\n", tfest);
5834 pr_debug("PhyCtl: %04x%s ", ptcw,
5835 (ptcw & PHY_TXC_SHORT_HDR) ? " short" : "");
5836 pr_debug("PhyCtl_1: %04x ", ptcw_1);
5837 pr_debug("PhyCtl_1_Fbr: %04x\n", ptcw_1_Fbr);
5838 pr_debug("PhyCtl_1_Rts: %04x ", ptcw_1_Rts);
5839 pr_debug("PhyCtl_1_Fbr_Rts: %04x\n", ptcw_1_FbrRts);
5840 pr_debug("MainRates: %04x ", mainrates);
5841 pr_debug("XtraFrameTypes: %04x ", xtraft);
5842 pr_debug("\n");
5843
5844 print_hex_dump_bytes("SecIV:", DUMP_PREFIX_OFFSET, iv, sizeof(txh->IV));
5845 print_hex_dump_bytes("RA:", DUMP_PREFIX_OFFSET,
5846 ra, sizeof(txh->TxFrameRA));
5847
5848 pr_debug("Fb FES Time: %04x ", tfestfb);
5849 print_hex_dump_bytes("Fb RTS PLCP:", DUMP_PREFIX_OFFSET,
5850 rtspfb, sizeof(txh->RTSPLCPFallback));
5851 pr_debug("RTS DUR: %04x ", rtsdfb);
5852 print_hex_dump_bytes("PLCP:", DUMP_PREFIX_OFFSET,
5853 fragpfb, sizeof(txh->FragPLCPFallback));
5854 pr_debug("DUR: %04x", fragdfb);
5855 pr_debug("\n");
5856
5857 pr_debug("MModeLen: %04x ", mmodelen);
5858 pr_debug("MModeFbrLen: %04x\n", mmodefbrlen);
5859
5860 pr_debug("FrameID: %04x\n", tfid);
5861 pr_debug("TxStatus: %04x\n", txs);
5862
5863 pr_debug("MaxNumMpdu: %04x\n", mnmpdu);
5864 pr_debug("MaxAggbyte: %04x\n", mabyte);
5865 pr_debug("MaxAggbyte_fb: %04x\n", mabyte_f);
5866 pr_debug("MinByte: %04x\n", mmbyte);
5867
5868 print_hex_dump_bytes("RTS PLCP:", DUMP_PREFIX_OFFSET,
5869 rtsph, sizeof(txh->RTSPhyHeader));
5870 print_hex_dump_bytes("RTS Frame:", DUMP_PREFIX_OFFSET,
5871 (u8 *)&rts, sizeof(txh->rts_frame));
5872 pr_debug("\n");
5873 }
5874 #endif /* defined(DEBUG) */
5875
5876 #if defined(DEBUG)
5877 static int
5878 brcms_c_format_flags(const struct brcms_c_bit_desc *bd, u32 flags, char *buf,
5879 int len)
5880 {
5881 int i;
5882 char *p = buf;
5883 char hexstr[16];
5884 int slen = 0, nlen = 0;
5885 u32 bit;
5886 const char *name;
5887
5888 if (len < 2 || !buf)
5889 return 0;
5890
5891 buf[0] = '\0';
5892
5893 for (i = 0; flags != 0; i++) {
5894 bit = bd[i].bit;
5895 name = bd[i].name;
5896 if (bit == 0 && flags != 0) {
5897 /* print any unnamed bits */
5898 snprintf(hexstr, 16, "0x%X", flags);
5899 name = hexstr;
5900 flags = 0; /* exit loop */
5901 } else if ((flags & bit) == 0)
5902 continue;
5903 flags &= ~bit;
5904 nlen = strlen(name);
5905 slen += nlen;
5906 /* count btwn flag space */
5907 if (flags != 0)
5908 slen += 1;
5909 /* need NULL char as well */
5910 if (len <= slen)
5911 break;
5912 /* copy NULL char but don't count it */
5913 strncpy(p, name, nlen + 1);
5914 p += nlen;
5915 /* copy btwn flag space and NULL char */
5916 if (flags != 0)
5917 p += snprintf(p, 2, " ");
5918 len -= slen;
5919 }
5920
5921 /* indicate the str was too short */
5922 if (flags != 0) {
5923 if (len < 2)
5924 p -= 2 - len; /* overwrite last char */
5925 p += snprintf(p, 2, ">");
5926 }
5927
5928 return (int)(p - buf);
5929 }
5930 #endif /* defined(DEBUG) */
5931
5932 #if defined(DEBUG)
5933 void brcms_c_print_rxh(struct d11rxhdr *rxh)
5934 {
5935 u16 len = rxh->RxFrameSize;
5936 u16 phystatus_0 = rxh->PhyRxStatus_0;
5937 u16 phystatus_1 = rxh->PhyRxStatus_1;
5938 u16 phystatus_2 = rxh->PhyRxStatus_2;
5939 u16 phystatus_3 = rxh->PhyRxStatus_3;
5940 u16 macstatus1 = rxh->RxStatus1;
5941 u16 macstatus2 = rxh->RxStatus2;
5942 char flagstr[64];
5943 char lenbuf[20];
5944 static const struct brcms_c_bit_desc macstat_flags[] = {
5945 {RXS_FCSERR, "FCSErr"},
5946 {RXS_RESPFRAMETX, "Reply"},
5947 {RXS_PBPRES, "PADDING"},
5948 {RXS_DECATMPT, "DeCr"},
5949 {RXS_DECERR, "DeCrErr"},
5950 {RXS_BCNSENT, "Bcn"},
5951 {0, NULL}
5952 };
5953
5954 brcmu_dbg_hex_dump(rxh, sizeof(struct d11rxhdr), "Raw RxDesc:\n");
5955
5956 brcms_c_format_flags(macstat_flags, macstatus1, flagstr, 64);
5957
5958 snprintf(lenbuf, sizeof(lenbuf), "0x%x", len);
5959
5960 pr_debug("RxFrameSize: %6s (%d)%s\n", lenbuf, len,
5961 (rxh->PhyRxStatus_0 & PRXS0_SHORTH) ? " short preamble" : "");
5962 pr_debug("RxPHYStatus: %04x %04x %04x %04x\n",
5963 phystatus_0, phystatus_1, phystatus_2, phystatus_3);
5964 pr_debug("RxMACStatus: %x %s\n", macstatus1, flagstr);
5965 pr_debug("RXMACaggtype: %x\n",
5966 (macstatus2 & RXS_AGGTYPE_MASK));
5967 pr_debug("RxTSFTime: %04x\n", rxh->RxTSFTime);
5968 }
5969 #endif /* defined(DEBUG) */
5970
5971 u16 brcms_b_rate_shm_offset(struct brcms_hardware *wlc_hw, u8 rate)
5972 {
5973 u16 table_ptr;
5974 u8 phy_rate, index;
5975
5976 /* get the phy specific rate encoding for the PLCP SIGNAL field */
5977 if (is_ofdm_rate(rate))
5978 table_ptr = M_RT_DIRMAP_A;
5979 else
5980 table_ptr = M_RT_DIRMAP_B;
5981
5982 /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
5983 * the index into the rate table.
5984 */
5985 phy_rate = rate_info[rate] & BRCMS_RATE_MASK;
5986 index = phy_rate & 0xf;
5987
5988 /* Find the SHM pointer to the rate table entry by looking in the
5989 * Direct-map Table
5990 */
5991 return 2 * brcms_b_read_shm(wlc_hw, table_ptr + (index * 2));
5992 }
5993
5994 static bool
5995 brcms_c_prec_enq_head(struct brcms_c_info *wlc, struct pktq *q,
5996 struct sk_buff *pkt, int prec, bool head)
5997 {
5998 struct sk_buff *p;
5999 int eprec = -1; /* precedence to evict from */
6000
6001 /* Determine precedence from which to evict packet, if any */
6002 if (pktq_pfull(q, prec))
6003 eprec = prec;
6004 else if (pktq_full(q)) {
6005 p = brcmu_pktq_peek_tail(q, &eprec);
6006 if (eprec > prec) {
6007 wiphy_err(wlc->wiphy, "%s: Failing: eprec %d > prec %d"
6008 "\n", __func__, eprec, prec);
6009 return false;
6010 }
6011 }
6012
6013 /* Evict if needed */
6014 if (eprec >= 0) {
6015 bool discard_oldest;
6016
6017 discard_oldest = ac_bitmap_tst(0, eprec);
6018
6019 /* Refuse newer packet unless configured to discard oldest */
6020 if (eprec == prec && !discard_oldest) {
6021 wiphy_err(wlc->wiphy, "%s: No where to go, prec == %d"
6022 "\n", __func__, prec);
6023 return false;
6024 }
6025
6026 /* Evict packet according to discard policy */
6027 p = discard_oldest ? brcmu_pktq_pdeq(q, eprec) :
6028 brcmu_pktq_pdeq_tail(q, eprec);
6029 brcmu_pkt_buf_free_skb(p);
6030 }
6031
6032 /* Enqueue */
6033 if (head)
6034 p = brcmu_pktq_penq_head(q, prec, pkt);
6035 else
6036 p = brcmu_pktq_penq(q, prec, pkt);
6037
6038 return true;
6039 }
6040
6041 /*
6042 * Attempts to queue a packet onto a multiple-precedence queue,
6043 * if necessary evicting a lower precedence packet from the queue.
6044 *
6045 * 'prec' is the precedence number that has already been mapped
6046 * from the packet priority.
6047 *
6048 * Returns true if packet consumed (queued), false if not.
6049 */
6050 static bool brcms_c_prec_enq(struct brcms_c_info *wlc, struct pktq *q,
6051 struct sk_buff *pkt, int prec)
6052 {
6053 return brcms_c_prec_enq_head(wlc, q, pkt, prec, false);
6054 }
6055
6056 void brcms_c_txq_enq(struct brcms_c_info *wlc, struct scb *scb,
6057 struct sk_buff *sdu)
6058 {
6059 struct brcms_txq_info *qi = wlc->pkt_queue; /* Check me */
6060 struct pktq *q = &qi->q;
6061 uint prec;
6062
6063 prec = brcms_ac_to_fifo(skb_get_queue_mapping(sdu));
6064 if (!brcms_c_prec_enq(wlc, q, sdu, prec)) {
6065 /*
6066 * we might hit this condtion in case
6067 * packet flooding from mac80211 stack
6068 */
6069 brcmu_pkt_buf_free_skb(sdu);
6070 }
6071 }
6072
6073 /*
6074 * bcmc_fid_generate:
6075 * Generate frame ID for a BCMC packet. The frag field is not used
6076 * for MC frames so is used as part of the sequence number.
6077 */
6078 static inline u16
6079 bcmc_fid_generate(struct brcms_c_info *wlc, struct brcms_bss_cfg *bsscfg,
6080 struct d11txh *txh)
6081 {
6082 u16 frameid;
6083
6084 frameid = le16_to_cpu(txh->TxFrameID) & ~(TXFID_SEQ_MASK |
6085 TXFID_QUEUE_MASK);
6086 frameid |=
6087 (((wlc->
6088 mc_fid_counter++) << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) |
6089 TX_BCMC_FIFO;
6090
6091 return frameid;
6092 }
6093
6094 static uint
6095 brcms_c_calc_ack_time(struct brcms_c_info *wlc, u32 rspec,
6096 u8 preamble_type)
6097 {
6098 uint dur = 0;
6099
6100 BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, preamble_type %d\n",
6101 wlc->pub->unit, rspec, preamble_type);
6102 /*
6103 * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that
6104 * is less than or equal to the rate of the immediately previous
6105 * frame in the FES
6106 */
6107 rspec = brcms_basic_rate(wlc, rspec);
6108 /* ACK frame len == 14 == 2(fc) + 2(dur) + 6(ra) + 4(fcs) */
6109 dur =
6110 brcms_c_calc_frame_time(wlc, rspec, preamble_type,
6111 (DOT11_ACK_LEN + FCS_LEN));
6112 return dur;
6113 }
6114
6115 static uint
6116 brcms_c_calc_cts_time(struct brcms_c_info *wlc, u32 rspec,
6117 u8 preamble_type)
6118 {
6119 BCMMSG(wlc->wiphy, "wl%d: ratespec 0x%x, preamble_type %d\n",
6120 wlc->pub->unit, rspec, preamble_type);
6121 return brcms_c_calc_ack_time(wlc, rspec, preamble_type);
6122 }
6123
6124 static uint
6125 brcms_c_calc_ba_time(struct brcms_c_info *wlc, u32 rspec,
6126 u8 preamble_type)
6127 {
6128 BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, "
6129 "preamble_type %d\n", wlc->pub->unit, rspec, preamble_type);
6130 /*
6131 * Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that
6132 * is less than or equal to the rate of the immediately previous
6133 * frame in the FES
6134 */
6135 rspec = brcms_basic_rate(wlc, rspec);
6136 /* BA len == 32 == 16(ctl hdr) + 4(ba len) + 8(bitmap) + 4(fcs) */
6137 return brcms_c_calc_frame_time(wlc, rspec, preamble_type,
6138 (DOT11_BA_LEN + DOT11_BA_BITMAP_LEN +
6139 FCS_LEN));
6140 }
6141
6142 /* brcms_c_compute_frame_dur()
6143 *
6144 * Calculate the 802.11 MAC header DUR field for MPDU
6145 * DUR for a single frame = 1 SIFS + 1 ACK
6146 * DUR for a frame with following frags = 3 SIFS + 2 ACK + next frag time
6147 *
6148 * rate MPDU rate in unit of 500kbps
6149 * next_frag_len next MPDU length in bytes
6150 * preamble_type use short/GF or long/MM PLCP header
6151 */
6152 static u16
6153 brcms_c_compute_frame_dur(struct brcms_c_info *wlc, u32 rate,
6154 u8 preamble_type, uint next_frag_len)
6155 {
6156 u16 dur, sifs;
6157
6158 sifs = get_sifs(wlc->band);
6159
6160 dur = sifs;
6161 dur += (u16) brcms_c_calc_ack_time(wlc, rate, preamble_type);
6162
6163 if (next_frag_len) {
6164 /* Double the current DUR to get 2 SIFS + 2 ACKs */
6165 dur *= 2;
6166 /* add another SIFS and the frag time */
6167 dur += sifs;
6168 dur +=
6169 (u16) brcms_c_calc_frame_time(wlc, rate, preamble_type,
6170 next_frag_len);
6171 }
6172 return dur;
6173 }
6174
6175 /* The opposite of brcms_c_calc_frame_time */
6176 static uint
6177 brcms_c_calc_frame_len(struct brcms_c_info *wlc, u32 ratespec,
6178 u8 preamble_type, uint dur)
6179 {
6180 uint nsyms, mac_len, Ndps, kNdps;
6181 uint rate = rspec2rate(ratespec);
6182
6183 BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, preamble_type %d, dur %d\n",
6184 wlc->pub->unit, ratespec, preamble_type, dur);
6185
6186 if (is_mcs_rate(ratespec)) {
6187 uint mcs = ratespec & RSPEC_RATE_MASK;
6188 int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec);
6189 dur -= PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
6190 /* payload calculation matches that of regular ofdm */
6191 if (wlc->band->bandtype == BRCM_BAND_2G)
6192 dur -= DOT11_OFDM_SIGNAL_EXTENSION;
6193 /* kNdbps = kbps * 4 */
6194 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
6195 rspec_issgi(ratespec)) * 4;
6196 nsyms = dur / APHY_SYMBOL_TIME;
6197 mac_len =
6198 ((nsyms * kNdps) -
6199 ((APHY_SERVICE_NBITS + APHY_TAIL_NBITS) * 1000)) / 8000;
6200 } else if (is_ofdm_rate(ratespec)) {
6201 dur -= APHY_PREAMBLE_TIME;
6202 dur -= APHY_SIGNAL_TIME;
6203 /* Ndbps = Mbps * 4 = rate(500Kbps) * 2 */
6204 Ndps = rate * 2;
6205 nsyms = dur / APHY_SYMBOL_TIME;
6206 mac_len =
6207 ((nsyms * Ndps) -
6208 (APHY_SERVICE_NBITS + APHY_TAIL_NBITS)) / 8;
6209 } else {
6210 if (preamble_type & BRCMS_SHORT_PREAMBLE)
6211 dur -= BPHY_PLCP_SHORT_TIME;
6212 else
6213 dur -= BPHY_PLCP_TIME;
6214 mac_len = dur * rate;
6215 /* divide out factor of 2 in rate (1/2 mbps) */
6216 mac_len = mac_len / 8 / 2;
6217 }
6218 return mac_len;
6219 }
6220
6221 /*
6222 * Return true if the specified rate is supported by the specified band.
6223 * BRCM_BAND_AUTO indicates the current band.
6224 */
6225 static bool brcms_c_valid_rate(struct brcms_c_info *wlc, u32 rspec, int band,
6226 bool verbose)
6227 {
6228 struct brcms_c_rateset *hw_rateset;
6229 uint i;
6230
6231 if ((band == BRCM_BAND_AUTO) || (band == wlc->band->bandtype))
6232 hw_rateset = &wlc->band->hw_rateset;
6233 else if (wlc->pub->_nbands > 1)
6234 hw_rateset = &wlc->bandstate[OTHERBANDUNIT(wlc)]->hw_rateset;
6235 else
6236 /* other band specified and we are a single band device */
6237 return false;
6238
6239 /* check if this is a mimo rate */
6240 if (is_mcs_rate(rspec)) {
6241 if ((rspec & RSPEC_RATE_MASK) >= MCS_TABLE_SIZE)
6242 goto error;
6243
6244 return isset(hw_rateset->mcs, (rspec & RSPEC_RATE_MASK));
6245 }
6246
6247 for (i = 0; i < hw_rateset->count; i++)
6248 if (hw_rateset->rates[i] == rspec2rate(rspec))
6249 return true;
6250 error:
6251 if (verbose)
6252 wiphy_err(wlc->wiphy, "wl%d: valid_rate: rate spec 0x%x "
6253 "not in hw_rateset\n", wlc->pub->unit, rspec);
6254
6255 return false;
6256 }
6257
6258 static u32
6259 mac80211_wlc_set_nrate(struct brcms_c_info *wlc, struct brcms_band *cur_band,
6260 u32 int_val)
6261 {
6262 u8 stf = (int_val & NRATE_STF_MASK) >> NRATE_STF_SHIFT;
6263 u8 rate = int_val & NRATE_RATE_MASK;
6264 u32 rspec;
6265 bool ismcs = ((int_val & NRATE_MCS_INUSE) == NRATE_MCS_INUSE);
6266 bool issgi = ((int_val & NRATE_SGI_MASK) >> NRATE_SGI_SHIFT);
6267 bool override_mcs_only = ((int_val & NRATE_OVERRIDE_MCS_ONLY)
6268 == NRATE_OVERRIDE_MCS_ONLY);
6269 int bcmerror = 0;
6270
6271 if (!ismcs)
6272 return (u32) rate;
6273
6274 /* validate the combination of rate/mcs/stf is allowed */
6275 if ((wlc->pub->_n_enab & SUPPORT_11N) && ismcs) {
6276 /* mcs only allowed when nmode */
6277 if (stf > PHY_TXC1_MODE_SDM) {
6278 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid stf\n",
6279 wlc->pub->unit, __func__);
6280 bcmerror = -EINVAL;
6281 goto done;
6282 }
6283
6284 /* mcs 32 is a special case, DUP mode 40 only */
6285 if (rate == 32) {
6286 if (!CHSPEC_IS40(wlc->home_chanspec) ||
6287 ((stf != PHY_TXC1_MODE_SISO)
6288 && (stf != PHY_TXC1_MODE_CDD))) {
6289 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid mcs "
6290 "32\n", wlc->pub->unit, __func__);
6291 bcmerror = -EINVAL;
6292 goto done;
6293 }
6294 /* mcs > 7 must use stf SDM */
6295 } else if (rate > HIGHEST_SINGLE_STREAM_MCS) {
6296 /* mcs > 7 must use stf SDM */
6297 if (stf != PHY_TXC1_MODE_SDM) {
6298 BCMMSG(wlc->wiphy, "wl%d: enabling "
6299 "SDM mode for mcs %d\n",
6300 wlc->pub->unit, rate);
6301 stf = PHY_TXC1_MODE_SDM;
6302 }
6303 } else {
6304 /*
6305 * MCS 0-7 may use SISO, CDD, and for
6306 * phy_rev >= 3 STBC
6307 */
6308 if ((stf > PHY_TXC1_MODE_STBC) ||
6309 (!BRCMS_STBC_CAP_PHY(wlc)
6310 && (stf == PHY_TXC1_MODE_STBC))) {
6311 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid STBC"
6312 "\n", wlc->pub->unit, __func__);
6313 bcmerror = -EINVAL;
6314 goto done;
6315 }
6316 }
6317 } else if (is_ofdm_rate(rate)) {
6318 if ((stf != PHY_TXC1_MODE_CDD) && (stf != PHY_TXC1_MODE_SISO)) {
6319 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid OFDM\n",
6320 wlc->pub->unit, __func__);
6321 bcmerror = -EINVAL;
6322 goto done;
6323 }
6324 } else if (is_cck_rate(rate)) {
6325 if ((cur_band->bandtype != BRCM_BAND_2G)
6326 || (stf != PHY_TXC1_MODE_SISO)) {
6327 wiphy_err(wlc->wiphy, "wl%d: %s: Invalid CCK\n",
6328 wlc->pub->unit, __func__);
6329 bcmerror = -EINVAL;
6330 goto done;
6331 }
6332 } else {
6333 wiphy_err(wlc->wiphy, "wl%d: %s: Unknown rate type\n",
6334 wlc->pub->unit, __func__);
6335 bcmerror = -EINVAL;
6336 goto done;
6337 }
6338 /* make sure multiple antennae are available for non-siso rates */
6339 if ((stf != PHY_TXC1_MODE_SISO) && (wlc->stf->txstreams == 1)) {
6340 wiphy_err(wlc->wiphy, "wl%d: %s: SISO antenna but !SISO "
6341 "request\n", wlc->pub->unit, __func__);
6342 bcmerror = -EINVAL;
6343 goto done;
6344 }
6345
6346 rspec = rate;
6347 if (ismcs) {
6348 rspec |= RSPEC_MIMORATE;
6349 /* For STBC populate the STC field of the ratespec */
6350 if (stf == PHY_TXC1_MODE_STBC) {
6351 u8 stc;
6352 stc = 1; /* Nss for single stream is always 1 */
6353 rspec |= (stc << RSPEC_STC_SHIFT);
6354 }
6355 }
6356
6357 rspec |= (stf << RSPEC_STF_SHIFT);
6358
6359 if (override_mcs_only)
6360 rspec |= RSPEC_OVERRIDE_MCS_ONLY;
6361
6362 if (issgi)
6363 rspec |= RSPEC_SHORT_GI;
6364
6365 if ((rate != 0)
6366 && !brcms_c_valid_rate(wlc, rspec, cur_band->bandtype, true))
6367 return rate;
6368
6369 return rspec;
6370 done:
6371 return rate;
6372 }
6373
6374 /*
6375 * Compute PLCP, but only requires actual rate and length of pkt.
6376 * Rate is given in the driver standard multiple of 500 kbps.
6377 * le is set for 11 Mbps rate if necessary.
6378 * Broken out for PRQ.
6379 */
6380
6381 static void brcms_c_cck_plcp_set(struct brcms_c_info *wlc, int rate_500,
6382 uint length, u8 *plcp)
6383 {
6384 u16 usec = 0;
6385 u8 le = 0;
6386
6387 switch (rate_500) {
6388 case BRCM_RATE_1M:
6389 usec = length << 3;
6390 break;
6391 case BRCM_RATE_2M:
6392 usec = length << 2;
6393 break;
6394 case BRCM_RATE_5M5:
6395 usec = (length << 4) / 11;
6396 if ((length << 4) - (usec * 11) > 0)
6397 usec++;
6398 break;
6399 case BRCM_RATE_11M:
6400 usec = (length << 3) / 11;
6401 if ((length << 3) - (usec * 11) > 0) {
6402 usec++;
6403 if ((usec * 11) - (length << 3) >= 8)
6404 le = D11B_PLCP_SIGNAL_LE;
6405 }
6406 break;
6407
6408 default:
6409 wiphy_err(wlc->wiphy,
6410 "brcms_c_cck_plcp_set: unsupported rate %d\n",
6411 rate_500);
6412 rate_500 = BRCM_RATE_1M;
6413 usec = length << 3;
6414 break;
6415 }
6416 /* PLCP signal byte */
6417 plcp[0] = rate_500 * 5; /* r (500kbps) * 5 == r (100kbps) */
6418 /* PLCP service byte */
6419 plcp[1] = (u8) (le | D11B_PLCP_SIGNAL_LOCKED);
6420 /* PLCP length u16, little endian */
6421 plcp[2] = usec & 0xff;
6422 plcp[3] = (usec >> 8) & 0xff;
6423 /* PLCP CRC16 */
6424 plcp[4] = 0;
6425 plcp[5] = 0;
6426 }
6427
6428 /* Rate: 802.11 rate code, length: PSDU length in octets */
6429 static void brcms_c_compute_mimo_plcp(u32 rspec, uint length, u8 *plcp)
6430 {
6431 u8 mcs = (u8) (rspec & RSPEC_RATE_MASK);
6432 plcp[0] = mcs;
6433 if (rspec_is40mhz(rspec) || (mcs == 32))
6434 plcp[0] |= MIMO_PLCP_40MHZ;
6435 BRCMS_SET_MIMO_PLCP_LEN(plcp, length);
6436 plcp[3] = rspec_mimoplcp3(rspec); /* rspec already holds this byte */
6437 plcp[3] |= 0x7; /* set smoothing, not sounding ppdu & reserved */
6438 plcp[4] = 0; /* number of extension spatial streams bit 0 & 1 */
6439 plcp[5] = 0;
6440 }
6441
6442 /* Rate: 802.11 rate code, length: PSDU length in octets */
6443 static void
6444 brcms_c_compute_ofdm_plcp(u32 rspec, u32 length, u8 *plcp)
6445 {
6446 u8 rate_signal;
6447 u32 tmp = 0;
6448 int rate = rspec2rate(rspec);
6449
6450 /*
6451 * encode rate per 802.11a-1999 sec 17.3.4.1, with lsb
6452 * transmitted first
6453 */
6454 rate_signal = rate_info[rate] & BRCMS_RATE_MASK;
6455 memset(plcp, 0, D11_PHY_HDR_LEN);
6456 D11A_PHY_HDR_SRATE((struct ofdm_phy_hdr *) plcp, rate_signal);
6457
6458 tmp = (length & 0xfff) << 5;
6459 plcp[2] |= (tmp >> 16) & 0xff;
6460 plcp[1] |= (tmp >> 8) & 0xff;
6461 plcp[0] |= tmp & 0xff;
6462 }
6463
6464 /* Rate: 802.11 rate code, length: PSDU length in octets */
6465 static void brcms_c_compute_cck_plcp(struct brcms_c_info *wlc, u32 rspec,
6466 uint length, u8 *plcp)
6467 {
6468 int rate = rspec2rate(rspec);
6469
6470 brcms_c_cck_plcp_set(wlc, rate, length, plcp);
6471 }
6472
6473 static void
6474 brcms_c_compute_plcp(struct brcms_c_info *wlc, u32 rspec,
6475 uint length, u8 *plcp)
6476 {
6477 if (is_mcs_rate(rspec))
6478 brcms_c_compute_mimo_plcp(rspec, length, plcp);
6479 else if (is_ofdm_rate(rspec))
6480 brcms_c_compute_ofdm_plcp(rspec, length, plcp);
6481 else
6482 brcms_c_compute_cck_plcp(wlc, rspec, length, plcp);
6483 }
6484
6485 /* brcms_c_compute_rtscts_dur()
6486 *
6487 * Calculate the 802.11 MAC header DUR field for an RTS or CTS frame
6488 * DUR for normal RTS/CTS w/ frame = 3 SIFS + 1 CTS + next frame time + 1 ACK
6489 * DUR for CTS-TO-SELF w/ frame = 2 SIFS + next frame time + 1 ACK
6490 *
6491 * cts cts-to-self or rts/cts
6492 * rts_rate rts or cts rate in unit of 500kbps
6493 * rate next MPDU rate in unit of 500kbps
6494 * frame_len next MPDU frame length in bytes
6495 */
6496 u16
6497 brcms_c_compute_rtscts_dur(struct brcms_c_info *wlc, bool cts_only,
6498 u32 rts_rate,
6499 u32 frame_rate, u8 rts_preamble_type,
6500 u8 frame_preamble_type, uint frame_len, bool ba)
6501 {
6502 u16 dur, sifs;
6503
6504 sifs = get_sifs(wlc->band);
6505
6506 if (!cts_only) {
6507 /* RTS/CTS */
6508 dur = 3 * sifs;
6509 dur +=
6510 (u16) brcms_c_calc_cts_time(wlc, rts_rate,
6511 rts_preamble_type);
6512 } else {
6513 /* CTS-TO-SELF */
6514 dur = 2 * sifs;
6515 }
6516
6517 dur +=
6518 (u16) brcms_c_calc_frame_time(wlc, frame_rate, frame_preamble_type,
6519 frame_len);
6520 if (ba)
6521 dur +=
6522 (u16) brcms_c_calc_ba_time(wlc, frame_rate,
6523 BRCMS_SHORT_PREAMBLE);
6524 else
6525 dur +=
6526 (u16) brcms_c_calc_ack_time(wlc, frame_rate,
6527 frame_preamble_type);
6528 return dur;
6529 }
6530
6531 static u16 brcms_c_phytxctl1_calc(struct brcms_c_info *wlc, u32 rspec)
6532 {
6533 u16 phyctl1 = 0;
6534 u16 bw;
6535
6536 if (BRCMS_ISLCNPHY(wlc->band)) {
6537 bw = PHY_TXC1_BW_20MHZ;
6538 } else {
6539 bw = rspec_get_bw(rspec);
6540 /* 10Mhz is not supported yet */
6541 if (bw < PHY_TXC1_BW_20MHZ) {
6542 wiphy_err(wlc->wiphy, "phytxctl1_calc: bw %d is "
6543 "not supported yet, set to 20L\n", bw);
6544 bw = PHY_TXC1_BW_20MHZ;
6545 }
6546 }
6547
6548 if (is_mcs_rate(rspec)) {
6549 uint mcs = rspec & RSPEC_RATE_MASK;
6550
6551 /* bw, stf, coding-type is part of rspec_phytxbyte2 returns */
6552 phyctl1 = rspec_phytxbyte2(rspec);
6553 /* set the upper byte of phyctl1 */
6554 phyctl1 |= (mcs_table[mcs].tx_phy_ctl3 << 8);
6555 } else if (is_cck_rate(rspec) && !BRCMS_ISLCNPHY(wlc->band)
6556 && !BRCMS_ISSSLPNPHY(wlc->band)) {
6557 /*
6558 * In CCK mode LPPHY overloads OFDM Modulation bits with CCK
6559 * Data Rate. Eventually MIMOPHY would also be converted to
6560 * this format
6561 */
6562 /* 0 = 1Mbps; 1 = 2Mbps; 2 = 5.5Mbps; 3 = 11Mbps */
6563 phyctl1 = (bw | (rspec_stf(rspec) << PHY_TXC1_MODE_SHIFT));
6564 } else { /* legacy OFDM/CCK */
6565 s16 phycfg;
6566 /* get the phyctl byte from rate phycfg table */
6567 phycfg = brcms_c_rate_legacy_phyctl(rspec2rate(rspec));
6568 if (phycfg == -1) {
6569 wiphy_err(wlc->wiphy, "phytxctl1_calc: wrong "
6570 "legacy OFDM/CCK rate\n");
6571 phycfg = 0;
6572 }
6573 /* set the upper byte of phyctl1 */
6574 phyctl1 =
6575 (bw | (phycfg << 8) |
6576 (rspec_stf(rspec) << PHY_TXC1_MODE_SHIFT));
6577 }
6578 return phyctl1;
6579 }
6580
6581 /*
6582 * Add struct d11txh, struct cck_phy_hdr.
6583 *
6584 * 'p' data must start with 802.11 MAC header
6585 * 'p' must allow enough bytes of local headers to be "pushed" onto the packet
6586 *
6587 * headroom == D11_PHY_HDR_LEN + D11_TXH_LEN (D11_TXH_LEN is now 104 bytes)
6588 *
6589 */
6590 static u16
6591 brcms_c_d11hdrs_mac80211(struct brcms_c_info *wlc, struct ieee80211_hw *hw,
6592 struct sk_buff *p, struct scb *scb, uint frag,
6593 uint nfrags, uint queue, uint next_frag_len)
6594 {
6595 struct ieee80211_hdr *h;
6596 struct d11txh *txh;
6597 u8 *plcp, plcp_fallback[D11_PHY_HDR_LEN];
6598 int len, phylen, rts_phylen;
6599 u16 mch, phyctl, xfts, mainrates;
6600 u16 seq = 0, mcl = 0, status = 0, frameid = 0;
6601 u32 rspec[2] = { BRCM_RATE_1M, BRCM_RATE_1M };
6602 u32 rts_rspec[2] = { BRCM_RATE_1M, BRCM_RATE_1M };
6603 bool use_rts = false;
6604 bool use_cts = false;
6605 bool use_rifs = false;
6606 bool short_preamble[2] = { false, false };
6607 u8 preamble_type[2] = { BRCMS_LONG_PREAMBLE, BRCMS_LONG_PREAMBLE };
6608 u8 rts_preamble_type[2] = { BRCMS_LONG_PREAMBLE, BRCMS_LONG_PREAMBLE };
6609 u8 *rts_plcp, rts_plcp_fallback[D11_PHY_HDR_LEN];
6610 struct ieee80211_rts *rts = NULL;
6611 bool qos;
6612 uint ac;
6613 bool hwtkmic = false;
6614 u16 mimo_ctlchbw = PHY_TXC1_BW_20MHZ;
6615 #define ANTCFG_NONE 0xFF
6616 u8 antcfg = ANTCFG_NONE;
6617 u8 fbantcfg = ANTCFG_NONE;
6618 uint phyctl1_stf = 0;
6619 u16 durid = 0;
6620 struct ieee80211_tx_rate *txrate[2];
6621 int k;
6622 struct ieee80211_tx_info *tx_info;
6623 bool is_mcs;
6624 u16 mimo_txbw;
6625 u8 mimo_preamble_type;
6626
6627 /* locate 802.11 MAC header */
6628 h = (struct ieee80211_hdr *)(p->data);
6629 qos = ieee80211_is_data_qos(h->frame_control);
6630
6631 /* compute length of frame in bytes for use in PLCP computations */
6632 len = p->len;
6633 phylen = len + FCS_LEN;
6634
6635 /* Get tx_info */
6636 tx_info = IEEE80211_SKB_CB(p);
6637
6638 /* add PLCP */
6639 plcp = skb_push(p, D11_PHY_HDR_LEN);
6640
6641 /* add Broadcom tx descriptor header */
6642 txh = (struct d11txh *) skb_push(p, D11_TXH_LEN);
6643 memset(txh, 0, D11_TXH_LEN);
6644
6645 /* setup frameid */
6646 if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
6647 /* non-AP STA should never use BCMC queue */
6648 if (queue == TX_BCMC_FIFO) {
6649 wiphy_err(wlc->wiphy, "wl%d: %s: ASSERT queue == "
6650 "TX_BCMC!\n", wlc->pub->unit, __func__);
6651 frameid = bcmc_fid_generate(wlc, NULL, txh);
6652 } else {
6653 /* Increment the counter for first fragment */
6654 if (tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
6655 scb->seqnum[p->priority]++;
6656
6657 /* extract fragment number from frame first */
6658 seq = le16_to_cpu(h->seq_ctrl) & FRAGNUM_MASK;
6659 seq |= (scb->seqnum[p->priority] << SEQNUM_SHIFT);
6660 h->seq_ctrl = cpu_to_le16(seq);
6661
6662 frameid = ((seq << TXFID_SEQ_SHIFT) & TXFID_SEQ_MASK) |
6663 (queue & TXFID_QUEUE_MASK);
6664 }
6665 }
6666 frameid |= queue & TXFID_QUEUE_MASK;
6667
6668 /* set the ignpmq bit for all pkts tx'd in PS mode and for beacons */
6669 if (ieee80211_is_beacon(h->frame_control))
6670 mcl |= TXC_IGNOREPMQ;
6671
6672 txrate[0] = tx_info->control.rates;
6673 txrate[1] = txrate[0] + 1;
6674
6675 /*
6676 * if rate control algorithm didn't give us a fallback
6677 * rate, use the primary rate
6678 */
6679 if (txrate[1]->idx < 0)
6680 txrate[1] = txrate[0];
6681
6682 for (k = 0; k < hw->max_rates; k++) {
6683 is_mcs = txrate[k]->flags & IEEE80211_TX_RC_MCS ? true : false;
6684 if (!is_mcs) {
6685 if ((txrate[k]->idx >= 0)
6686 && (txrate[k]->idx <
6687 hw->wiphy->bands[tx_info->band]->n_bitrates)) {
6688 rspec[k] =
6689 hw->wiphy->bands[tx_info->band]->
6690 bitrates[txrate[k]->idx].hw_value;
6691 short_preamble[k] =
6692 txrate[k]->
6693 flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ?
6694 true : false;
6695 } else {
6696 rspec[k] = BRCM_RATE_1M;
6697 }
6698 } else {
6699 rspec[k] = mac80211_wlc_set_nrate(wlc, wlc->band,
6700 NRATE_MCS_INUSE | txrate[k]->idx);
6701 }
6702
6703 /*
6704 * Currently only support same setting for primay and
6705 * fallback rates. Unify flags for each rate into a
6706 * single value for the frame
6707 */
6708 use_rts |=
6709 txrate[k]->
6710 flags & IEEE80211_TX_RC_USE_RTS_CTS ? true : false;
6711 use_cts |=
6712 txrate[k]->
6713 flags & IEEE80211_TX_RC_USE_CTS_PROTECT ? true : false;
6714
6715
6716 /*
6717 * (1) RATE:
6718 * determine and validate primary rate
6719 * and fallback rates
6720 */
6721 if (!rspec_active(rspec[k])) {
6722 rspec[k] = BRCM_RATE_1M;
6723 } else {
6724 if (!is_multicast_ether_addr(h->addr1)) {
6725 /* set tx antenna config */
6726 brcms_c_antsel_antcfg_get(wlc->asi, false,
6727 false, 0, 0, &antcfg, &fbantcfg);
6728 }
6729 }
6730 }
6731
6732 phyctl1_stf = wlc->stf->ss_opmode;
6733
6734 if (wlc->pub->_n_enab & SUPPORT_11N) {
6735 for (k = 0; k < hw->max_rates; k++) {
6736 /*
6737 * apply siso/cdd to single stream mcs's or ofdm
6738 * if rspec is auto selected
6739 */
6740 if (((is_mcs_rate(rspec[k]) &&
6741 is_single_stream(rspec[k] & RSPEC_RATE_MASK)) ||
6742 is_ofdm_rate(rspec[k]))
6743 && ((rspec[k] & RSPEC_OVERRIDE_MCS_ONLY)
6744 || !(rspec[k] & RSPEC_OVERRIDE))) {
6745 rspec[k] &= ~(RSPEC_STF_MASK | RSPEC_STC_MASK);
6746
6747 /* For SISO MCS use STBC if possible */
6748 if (is_mcs_rate(rspec[k])
6749 && BRCMS_STF_SS_STBC_TX(wlc, scb)) {
6750 u8 stc;
6751
6752 /* Nss for single stream is always 1 */
6753 stc = 1;
6754 rspec[k] |= (PHY_TXC1_MODE_STBC <<
6755 RSPEC_STF_SHIFT) |
6756 (stc << RSPEC_STC_SHIFT);
6757 } else
6758 rspec[k] |=
6759 (phyctl1_stf << RSPEC_STF_SHIFT);
6760 }
6761
6762 /*
6763 * Is the phy configured to use 40MHZ frames? If
6764 * so then pick the desired txbw
6765 */
6766 if (brcms_chspec_bw(wlc->chanspec) == BRCMS_40_MHZ) {
6767 /* default txbw is 20in40 SB */
6768 mimo_ctlchbw = mimo_txbw =
6769 CHSPEC_SB_UPPER(wlc_phy_chanspec_get(
6770 wlc->band->pi))
6771 ? PHY_TXC1_BW_20MHZ_UP : PHY_TXC1_BW_20MHZ;
6772
6773 if (is_mcs_rate(rspec[k])) {
6774 /* mcs 32 must be 40b/w DUP */
6775 if ((rspec[k] & RSPEC_RATE_MASK)
6776 == 32) {
6777 mimo_txbw =
6778 PHY_TXC1_BW_40MHZ_DUP;
6779 /* use override */
6780 } else if (wlc->mimo_40txbw != AUTO)
6781 mimo_txbw = wlc->mimo_40txbw;
6782 /* else check if dst is using 40 Mhz */
6783 else if (scb->flags & SCB_IS40)
6784 mimo_txbw = PHY_TXC1_BW_40MHZ;
6785 } else if (is_ofdm_rate(rspec[k])) {
6786 if (wlc->ofdm_40txbw != AUTO)
6787 mimo_txbw = wlc->ofdm_40txbw;
6788 } else if (wlc->cck_40txbw != AUTO) {
6789 mimo_txbw = wlc->cck_40txbw;
6790 }
6791 } else {
6792 /*
6793 * mcs32 is 40 b/w only.
6794 * This is possible for probe packets on
6795 * a STA during SCAN
6796 */
6797 if ((rspec[k] & RSPEC_RATE_MASK) == 32)
6798 /* mcs 0 */
6799 rspec[k] = RSPEC_MIMORATE;
6800
6801 mimo_txbw = PHY_TXC1_BW_20MHZ;
6802 }
6803
6804 /* Set channel width */
6805 rspec[k] &= ~RSPEC_BW_MASK;
6806 if ((k == 0) || ((k > 0) && is_mcs_rate(rspec[k])))
6807 rspec[k] |= (mimo_txbw << RSPEC_BW_SHIFT);
6808 else
6809 rspec[k] |= (mimo_ctlchbw << RSPEC_BW_SHIFT);
6810
6811 /* Disable short GI, not supported yet */
6812 rspec[k] &= ~RSPEC_SHORT_GI;
6813
6814 mimo_preamble_type = BRCMS_MM_PREAMBLE;
6815 if (txrate[k]->flags & IEEE80211_TX_RC_GREEN_FIELD)
6816 mimo_preamble_type = BRCMS_GF_PREAMBLE;
6817
6818 if ((txrate[k]->flags & IEEE80211_TX_RC_MCS)
6819 && (!is_mcs_rate(rspec[k]))) {
6820 wiphy_err(wlc->wiphy, "wl%d: %s: IEEE80211_TX_"
6821 "RC_MCS != is_mcs_rate(rspec)\n",
6822 wlc->pub->unit, __func__);
6823 }
6824
6825 if (is_mcs_rate(rspec[k])) {
6826 preamble_type[k] = mimo_preamble_type;
6827
6828 /*
6829 * if SGI is selected, then forced mm
6830 * for single stream
6831 */
6832 if ((rspec[k] & RSPEC_SHORT_GI)
6833 && is_single_stream(rspec[k] &
6834 RSPEC_RATE_MASK))
6835 preamble_type[k] = BRCMS_MM_PREAMBLE;
6836 }
6837
6838 /* should be better conditionalized */
6839 if (!is_mcs_rate(rspec[0])
6840 && (tx_info->control.rates[0].
6841 flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE))
6842 preamble_type[k] = BRCMS_SHORT_PREAMBLE;
6843 }
6844 } else {
6845 for (k = 0; k < hw->max_rates; k++) {
6846 /* Set ctrlchbw as 20Mhz */
6847 rspec[k] &= ~RSPEC_BW_MASK;
6848 rspec[k] |= (PHY_TXC1_BW_20MHZ << RSPEC_BW_SHIFT);
6849
6850 /* for nphy, stf of ofdm frames must follow policies */
6851 if (BRCMS_ISNPHY(wlc->band) && is_ofdm_rate(rspec[k])) {
6852 rspec[k] &= ~RSPEC_STF_MASK;
6853 rspec[k] |= phyctl1_stf << RSPEC_STF_SHIFT;
6854 }
6855 }
6856 }
6857
6858 /* Reset these for use with AMPDU's */
6859 txrate[0]->count = 0;
6860 txrate[1]->count = 0;
6861
6862 /* (2) PROTECTION, may change rspec */
6863 if ((ieee80211_is_data(h->frame_control) ||
6864 ieee80211_is_mgmt(h->frame_control)) &&
6865 (phylen > wlc->RTSThresh) && !is_multicast_ether_addr(h->addr1))
6866 use_rts = true;
6867
6868 /* (3) PLCP: determine PLCP header and MAC duration,
6869 * fill struct d11txh */
6870 brcms_c_compute_plcp(wlc, rspec[0], phylen, plcp);
6871 brcms_c_compute_plcp(wlc, rspec[1], phylen, plcp_fallback);
6872 memcpy(&txh->FragPLCPFallback,
6873 plcp_fallback, sizeof(txh->FragPLCPFallback));
6874
6875 /* Length field now put in CCK FBR CRC field */
6876 if (is_cck_rate(rspec[1])) {
6877 txh->FragPLCPFallback[4] = phylen & 0xff;
6878 txh->FragPLCPFallback[5] = (phylen & 0xff00) >> 8;
6879 }
6880
6881 /* MIMO-RATE: need validation ?? */
6882 mainrates = is_ofdm_rate(rspec[0]) ?
6883 D11A_PHY_HDR_GRATE((struct ofdm_phy_hdr *) plcp) :
6884 plcp[0];
6885
6886 /* DUR field for main rate */
6887 if (!ieee80211_is_pspoll(h->frame_control) &&
6888 !is_multicast_ether_addr(h->addr1) && !use_rifs) {
6889 durid =
6890 brcms_c_compute_frame_dur(wlc, rspec[0], preamble_type[0],
6891 next_frag_len);
6892 h->duration_id = cpu_to_le16(durid);
6893 } else if (use_rifs) {
6894 /* NAV protect to end of next max packet size */
6895 durid =
6896 (u16) brcms_c_calc_frame_time(wlc, rspec[0],
6897 preamble_type[0],
6898 DOT11_MAX_FRAG_LEN);
6899 durid += RIFS_11N_TIME;
6900 h->duration_id = cpu_to_le16(durid);
6901 }
6902
6903 /* DUR field for fallback rate */
6904 if (ieee80211_is_pspoll(h->frame_control))
6905 txh->FragDurFallback = h->duration_id;
6906 else if (is_multicast_ether_addr(h->addr1) || use_rifs)
6907 txh->FragDurFallback = 0;
6908 else {
6909 durid = brcms_c_compute_frame_dur(wlc, rspec[1],
6910 preamble_type[1], next_frag_len);
6911 txh->FragDurFallback = cpu_to_le16(durid);
6912 }
6913
6914 /* (4) MAC-HDR: MacTxControlLow */
6915 if (frag == 0)
6916 mcl |= TXC_STARTMSDU;
6917
6918 if (!is_multicast_ether_addr(h->addr1))
6919 mcl |= TXC_IMMEDACK;
6920
6921 if (wlc->band->bandtype == BRCM_BAND_5G)
6922 mcl |= TXC_FREQBAND_5G;
6923
6924 if (CHSPEC_IS40(wlc_phy_chanspec_get(wlc->band->pi)))
6925 mcl |= TXC_BW_40;
6926
6927 /* set AMIC bit if using hardware TKIP MIC */
6928 if (hwtkmic)
6929 mcl |= TXC_AMIC;
6930
6931 txh->MacTxControlLow = cpu_to_le16(mcl);
6932
6933 /* MacTxControlHigh */
6934 mch = 0;
6935
6936 /* Set fallback rate preamble type */
6937 if ((preamble_type[1] == BRCMS_SHORT_PREAMBLE) ||
6938 (preamble_type[1] == BRCMS_GF_PREAMBLE)) {
6939 if (rspec2rate(rspec[1]) != BRCM_RATE_1M)
6940 mch |= TXC_PREAMBLE_DATA_FB_SHORT;
6941 }
6942
6943 /* MacFrameControl */
6944 memcpy(&txh->MacFrameControl, &h->frame_control, sizeof(u16));
6945 txh->TxFesTimeNormal = cpu_to_le16(0);
6946
6947 txh->TxFesTimeFallback = cpu_to_le16(0);
6948
6949 /* TxFrameRA */
6950 memcpy(&txh->TxFrameRA, &h->addr1, ETH_ALEN);
6951
6952 /* TxFrameID */
6953 txh->TxFrameID = cpu_to_le16(frameid);
6954
6955 /*
6956 * TxStatus, Note the case of recreating the first frag of a suppressed
6957 * frame then we may need to reset the retry cnt's via the status reg
6958 */
6959 txh->TxStatus = cpu_to_le16(status);
6960
6961 /*
6962 * extra fields for ucode AMPDU aggregation, the new fields are added to
6963 * the END of previous structure so that it's compatible in driver.
6964 */
6965 txh->MaxNMpdus = cpu_to_le16(0);
6966 txh->MaxABytes_MRT = cpu_to_le16(0);
6967 txh->MaxABytes_FBR = cpu_to_le16(0);
6968 txh->MinMBytes = cpu_to_le16(0);
6969
6970 /* (5) RTS/CTS: determine RTS/CTS PLCP header and MAC duration,
6971 * furnish struct d11txh */
6972 /* RTS PLCP header and RTS frame */
6973 if (use_rts || use_cts) {
6974 if (use_rts && use_cts)
6975 use_cts = false;
6976
6977 for (k = 0; k < 2; k++) {
6978 rts_rspec[k] = brcms_c_rspec_to_rts_rspec(wlc, rspec[k],
6979 false,
6980 mimo_ctlchbw);
6981 }
6982
6983 if (!is_ofdm_rate(rts_rspec[0]) &&
6984 !((rspec2rate(rts_rspec[0]) == BRCM_RATE_1M) ||
6985 (wlc->PLCPHdr_override == BRCMS_PLCP_LONG))) {
6986 rts_preamble_type[0] = BRCMS_SHORT_PREAMBLE;
6987 mch |= TXC_PREAMBLE_RTS_MAIN_SHORT;
6988 }
6989
6990 if (!is_ofdm_rate(rts_rspec[1]) &&
6991 !((rspec2rate(rts_rspec[1]) == BRCM_RATE_1M) ||
6992 (wlc->PLCPHdr_override == BRCMS_PLCP_LONG))) {
6993 rts_preamble_type[1] = BRCMS_SHORT_PREAMBLE;
6994 mch |= TXC_PREAMBLE_RTS_FB_SHORT;
6995 }
6996
6997 /* RTS/CTS additions to MacTxControlLow */
6998 if (use_cts) {
6999 txh->MacTxControlLow |= cpu_to_le16(TXC_SENDCTS);
7000 } else {
7001 txh->MacTxControlLow |= cpu_to_le16(TXC_SENDRTS);
7002 txh->MacTxControlLow |= cpu_to_le16(TXC_LONGFRAME);
7003 }
7004
7005 /* RTS PLCP header */
7006 rts_plcp = txh->RTSPhyHeader;
7007 if (use_cts)
7008 rts_phylen = DOT11_CTS_LEN + FCS_LEN;
7009 else
7010 rts_phylen = DOT11_RTS_LEN + FCS_LEN;
7011
7012 brcms_c_compute_plcp(wlc, rts_rspec[0], rts_phylen, rts_plcp);
7013
7014 /* fallback rate version of RTS PLCP header */
7015 brcms_c_compute_plcp(wlc, rts_rspec[1], rts_phylen,
7016 rts_plcp_fallback);
7017 memcpy(&txh->RTSPLCPFallback, rts_plcp_fallback,
7018 sizeof(txh->RTSPLCPFallback));
7019
7020 /* RTS frame fields... */
7021 rts = (struct ieee80211_rts *)&txh->rts_frame;
7022
7023 durid = brcms_c_compute_rtscts_dur(wlc, use_cts, rts_rspec[0],
7024 rspec[0], rts_preamble_type[0],
7025 preamble_type[0], phylen, false);
7026 rts->duration = cpu_to_le16(durid);
7027 /* fallback rate version of RTS DUR field */
7028 durid = brcms_c_compute_rtscts_dur(wlc, use_cts,
7029 rts_rspec[1], rspec[1],
7030 rts_preamble_type[1],
7031 preamble_type[1], phylen, false);
7032 txh->RTSDurFallback = cpu_to_le16(durid);
7033
7034 if (use_cts) {
7035 rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL |
7036 IEEE80211_STYPE_CTS);
7037
7038 memcpy(&rts->ra, &h->addr2, ETH_ALEN);
7039 } else {
7040 rts->frame_control = cpu_to_le16(IEEE80211_FTYPE_CTL |
7041 IEEE80211_STYPE_RTS);
7042
7043 memcpy(&rts->ra, &h->addr1, 2 * ETH_ALEN);
7044 }
7045
7046 /* mainrate
7047 * low 8 bits: main frag rate/mcs,
7048 * high 8 bits: rts/cts rate/mcs
7049 */
7050 mainrates |= (is_ofdm_rate(rts_rspec[0]) ?
7051 D11A_PHY_HDR_GRATE(
7052 (struct ofdm_phy_hdr *) rts_plcp) :
7053 rts_plcp[0]) << 8;
7054 } else {
7055 memset((char *)txh->RTSPhyHeader, 0, D11_PHY_HDR_LEN);
7056 memset((char *)&txh->rts_frame, 0,
7057 sizeof(struct ieee80211_rts));
7058 memset((char *)txh->RTSPLCPFallback, 0,
7059 sizeof(txh->RTSPLCPFallback));
7060 txh->RTSDurFallback = 0;
7061 }
7062
7063 #ifdef SUPPORT_40MHZ
7064 /* add null delimiter count */
7065 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && is_mcs_rate(rspec))
7066 txh->RTSPLCPFallback[AMPDU_FBR_NULL_DELIM] =
7067 brcm_c_ampdu_null_delim_cnt(wlc->ampdu, scb, rspec, phylen);
7068
7069 #endif
7070
7071 /*
7072 * Now that RTS/RTS FB preamble types are updated, write
7073 * the final value
7074 */
7075 txh->MacTxControlHigh = cpu_to_le16(mch);
7076
7077 /*
7078 * MainRates (both the rts and frag plcp rates have
7079 * been calculated now)
7080 */
7081 txh->MainRates = cpu_to_le16(mainrates);
7082
7083 /* XtraFrameTypes */
7084 xfts = frametype(rspec[1], wlc->mimoft);
7085 xfts |= (frametype(rts_rspec[0], wlc->mimoft) << XFTS_RTS_FT_SHIFT);
7086 xfts |= (frametype(rts_rspec[1], wlc->mimoft) << XFTS_FBRRTS_FT_SHIFT);
7087 xfts |= CHSPEC_CHANNEL(wlc_phy_chanspec_get(wlc->band->pi)) <<
7088 XFTS_CHANNEL_SHIFT;
7089 txh->XtraFrameTypes = cpu_to_le16(xfts);
7090
7091 /* PhyTxControlWord */
7092 phyctl = frametype(rspec[0], wlc->mimoft);
7093 if ((preamble_type[0] == BRCMS_SHORT_PREAMBLE) ||
7094 (preamble_type[0] == BRCMS_GF_PREAMBLE)) {
7095 if (rspec2rate(rspec[0]) != BRCM_RATE_1M)
7096 phyctl |= PHY_TXC_SHORT_HDR;
7097 }
7098
7099 /* phytxant is properly bit shifted */
7100 phyctl |= brcms_c_stf_d11hdrs_phyctl_txant(wlc, rspec[0]);
7101 txh->PhyTxControlWord = cpu_to_le16(phyctl);
7102
7103 /* PhyTxControlWord_1 */
7104 if (BRCMS_PHY_11N_CAP(wlc->band)) {
7105 u16 phyctl1 = 0;
7106
7107 phyctl1 = brcms_c_phytxctl1_calc(wlc, rspec[0]);
7108 txh->PhyTxControlWord_1 = cpu_to_le16(phyctl1);
7109 phyctl1 = brcms_c_phytxctl1_calc(wlc, rspec[1]);
7110 txh->PhyTxControlWord_1_Fbr = cpu_to_le16(phyctl1);
7111
7112 if (use_rts || use_cts) {
7113 phyctl1 = brcms_c_phytxctl1_calc(wlc, rts_rspec[0]);
7114 txh->PhyTxControlWord_1_Rts = cpu_to_le16(phyctl1);
7115 phyctl1 = brcms_c_phytxctl1_calc(wlc, rts_rspec[1]);
7116 txh->PhyTxControlWord_1_FbrRts = cpu_to_le16(phyctl1);
7117 }
7118
7119 /*
7120 * For mcs frames, if mixedmode(overloaded with long preamble)
7121 * is going to be set, fill in non-zero MModeLen and/or
7122 * MModeFbrLen it will be unnecessary if they are separated
7123 */
7124 if (is_mcs_rate(rspec[0]) &&
7125 (preamble_type[0] == BRCMS_MM_PREAMBLE)) {
7126 u16 mmodelen =
7127 brcms_c_calc_lsig_len(wlc, rspec[0], phylen);
7128 txh->MModeLen = cpu_to_le16(mmodelen);
7129 }
7130
7131 if (is_mcs_rate(rspec[1]) &&
7132 (preamble_type[1] == BRCMS_MM_PREAMBLE)) {
7133 u16 mmodefbrlen =
7134 brcms_c_calc_lsig_len(wlc, rspec[1], phylen);
7135 txh->MModeFbrLen = cpu_to_le16(mmodefbrlen);
7136 }
7137 }
7138
7139 ac = skb_get_queue_mapping(p);
7140 if ((scb->flags & SCB_WMECAP) && qos && wlc->edcf_txop[ac]) {
7141 uint frag_dur, dur, dur_fallback;
7142
7143 /* WME: Update TXOP threshold */
7144 if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU) && frag == 0) {
7145 frag_dur =
7146 brcms_c_calc_frame_time(wlc, rspec[0],
7147 preamble_type[0], phylen);
7148
7149 if (rts) {
7150 /* 1 RTS or CTS-to-self frame */
7151 dur =
7152 brcms_c_calc_cts_time(wlc, rts_rspec[0],
7153 rts_preamble_type[0]);
7154 dur_fallback =
7155 brcms_c_calc_cts_time(wlc, rts_rspec[1],
7156 rts_preamble_type[1]);
7157 /* (SIFS + CTS) + SIFS + frame + SIFS + ACK */
7158 dur += le16_to_cpu(rts->duration);
7159 dur_fallback +=
7160 le16_to_cpu(txh->RTSDurFallback);
7161 } else if (use_rifs) {
7162 dur = frag_dur;
7163 dur_fallback = 0;
7164 } else {
7165 /* frame + SIFS + ACK */
7166 dur = frag_dur;
7167 dur +=
7168 brcms_c_compute_frame_dur(wlc, rspec[0],
7169 preamble_type[0], 0);
7170
7171 dur_fallback =
7172 brcms_c_calc_frame_time(wlc, rspec[1],
7173 preamble_type[1],
7174 phylen);
7175 dur_fallback +=
7176 brcms_c_compute_frame_dur(wlc, rspec[1],
7177 preamble_type[1], 0);
7178 }
7179 /* NEED to set TxFesTimeNormal (hard) */
7180 txh->TxFesTimeNormal = cpu_to_le16((u16) dur);
7181 /*
7182 * NEED to set fallback rate version of
7183 * TxFesTimeNormal (hard)
7184 */
7185 txh->TxFesTimeFallback =
7186 cpu_to_le16((u16) dur_fallback);
7187
7188 /*
7189 * update txop byte threshold (txop minus intraframe
7190 * overhead)
7191 */
7192 if (wlc->edcf_txop[ac] >= (dur - frag_dur)) {
7193 uint newfragthresh;
7194
7195 newfragthresh =
7196 brcms_c_calc_frame_len(wlc,
7197 rspec[0], preamble_type[0],
7198 (wlc->edcf_txop[ac] -
7199 (dur - frag_dur)));
7200 /* range bound the fragthreshold */
7201 if (newfragthresh < DOT11_MIN_FRAG_LEN)
7202 newfragthresh =
7203 DOT11_MIN_FRAG_LEN;
7204 else if (newfragthresh >
7205 wlc->usr_fragthresh)
7206 newfragthresh =
7207 wlc->usr_fragthresh;
7208 /* update the fragthresh and do txc update */
7209 if (wlc->fragthresh[queue] !=
7210 (u16) newfragthresh)
7211 wlc->fragthresh[queue] =
7212 (u16) newfragthresh;
7213 } else {
7214 wiphy_err(wlc->wiphy, "wl%d: %s txop invalid "
7215 "for rate %d\n",
7216 wlc->pub->unit, fifo_names[queue],
7217 rspec2rate(rspec[0]));
7218 }
7219
7220 if (dur > wlc->edcf_txop[ac])
7221 wiphy_err(wlc->wiphy, "wl%d: %s: %s txop "
7222 "exceeded phylen %d/%d dur %d/%d\n",
7223 wlc->pub->unit, __func__,
7224 fifo_names[queue],
7225 phylen, wlc->fragthresh[queue],
7226 dur, wlc->edcf_txop[ac]);
7227 }
7228 }
7229
7230 return 0;
7231 }
7232
7233 void brcms_c_sendpkt_mac80211(struct brcms_c_info *wlc, struct sk_buff *sdu,
7234 struct ieee80211_hw *hw)
7235 {
7236 uint fifo;
7237 struct scb *scb = &wlc->pri_scb;
7238
7239 fifo = brcms_ac_to_fifo(skb_get_queue_mapping(sdu));
7240 if (brcms_c_d11hdrs_mac80211(wlc, hw, sdu, scb, 0, 1, fifo, 0))
7241 return;
7242 brcms_c_txq_enq(wlc, scb, sdu);
7243 brcms_c_send_q(wlc);
7244 }
7245
7246 void brcms_c_send_q(struct brcms_c_info *wlc)
7247 {
7248 struct sk_buff *pkt[DOT11_MAXNUMFRAGS];
7249 int prec;
7250 u16 prec_map;
7251 int err = 0, i, count;
7252 uint fifo;
7253 struct brcms_txq_info *qi = wlc->pkt_queue;
7254 struct pktq *q = &qi->q;
7255 struct ieee80211_tx_info *tx_info;
7256
7257 prec_map = wlc->tx_prec_map;
7258
7259 /* Send all the enq'd pkts that we can.
7260 * Dequeue packets with precedence with empty HW fifo only
7261 */
7262 while (prec_map && (pkt[0] = brcmu_pktq_mdeq(q, prec_map, &prec))) {
7263 tx_info = IEEE80211_SKB_CB(pkt[0]);
7264 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
7265 err = brcms_c_sendampdu(wlc->ampdu, qi, pkt, prec);
7266 } else {
7267 count = 1;
7268 err = brcms_c_prep_pdu(wlc, pkt[0], &fifo);
7269 if (!err) {
7270 for (i = 0; i < count; i++)
7271 brcms_c_txfifo(wlc, fifo, pkt[i], true);
7272 }
7273 }
7274
7275 if (err == -EBUSY) {
7276 brcmu_pktq_penq_head(q, prec, pkt[0]);
7277 /*
7278 * If send failed due to any other reason than a
7279 * change in HW FIFO condition, quit. Otherwise,
7280 * read the new prec_map!
7281 */
7282 if (prec_map == wlc->tx_prec_map)
7283 break;
7284 prec_map = wlc->tx_prec_map;
7285 }
7286 }
7287 }
7288
7289 void
7290 brcms_c_txfifo(struct brcms_c_info *wlc, uint fifo, struct sk_buff *p,
7291 bool commit)
7292 {
7293 u16 frameid = INVALIDFID;
7294 struct d11txh *txh;
7295
7296 txh = (struct d11txh *) (p->data);
7297
7298 /* When a BC/MC frame is being committed to the BCMC fifo
7299 * via DMA (NOT PIO), update ucode or BSS info as appropriate.
7300 */
7301 if (fifo == TX_BCMC_FIFO)
7302 frameid = le16_to_cpu(txh->TxFrameID);
7303
7304 /*
7305 * Bump up pending count for if not using rpc. If rpc is
7306 * used, this will be handled in brcms_b_txfifo()
7307 */
7308 if (commit) {
7309 wlc->core->txpktpend[fifo] += 1;
7310 BCMMSG(wlc->wiphy, "pktpend inc 1 to %d\n",
7311 wlc->core->txpktpend[fifo]);
7312 }
7313
7314 /* Commit BCMC sequence number in the SHM frame ID location */
7315 if (frameid != INVALIDFID) {
7316 /*
7317 * To inform the ucode of the last mcast frame posted
7318 * so that it can clear moredata bit
7319 */
7320 brcms_b_write_shm(wlc->hw, M_BCMC_FID, frameid);
7321 }
7322
7323 if (dma_txfast(wlc->hw->di[fifo], p, commit) < 0)
7324 wiphy_err(wlc->wiphy, "txfifo: fatal, toss frames !!!\n");
7325 }
7326
7327 u32
7328 brcms_c_rspec_to_rts_rspec(struct brcms_c_info *wlc, u32 rspec,
7329 bool use_rspec, u16 mimo_ctlchbw)
7330 {
7331 u32 rts_rspec = 0;
7332
7333 if (use_rspec)
7334 /* use frame rate as rts rate */
7335 rts_rspec = rspec;
7336 else if (wlc->band->gmode && wlc->protection->_g && !is_cck_rate(rspec))
7337 /* Use 11Mbps as the g protection RTS target rate and fallback.
7338 * Use the brcms_basic_rate() lookup to find the best basic rate
7339 * under the target in case 11 Mbps is not Basic.
7340 * 6 and 9 Mbps are not usually selected by rate selection, but
7341 * even if the OFDM rate we are protecting is 6 or 9 Mbps, 11
7342 * is more robust.
7343 */
7344 rts_rspec = brcms_basic_rate(wlc, BRCM_RATE_11M);
7345 else
7346 /* calculate RTS rate and fallback rate based on the frame rate
7347 * RTS must be sent at a basic rate since it is a
7348 * control frame, sec 9.6 of 802.11 spec
7349 */
7350 rts_rspec = brcms_basic_rate(wlc, rspec);
7351
7352 if (BRCMS_PHY_11N_CAP(wlc->band)) {
7353 /* set rts txbw to correct side band */
7354 rts_rspec &= ~RSPEC_BW_MASK;
7355
7356 /*
7357 * if rspec/rspec_fallback is 40MHz, then send RTS on both
7358 * 20MHz channel (DUP), otherwise send RTS on control channel
7359 */
7360 if (rspec_is40mhz(rspec) && !is_cck_rate(rts_rspec))
7361 rts_rspec |= (PHY_TXC1_BW_40MHZ_DUP << RSPEC_BW_SHIFT);
7362 else
7363 rts_rspec |= (mimo_ctlchbw << RSPEC_BW_SHIFT);
7364
7365 /* pick siso/cdd as default for ofdm */
7366 if (is_ofdm_rate(rts_rspec)) {
7367 rts_rspec &= ~RSPEC_STF_MASK;
7368 rts_rspec |= (wlc->stf->ss_opmode << RSPEC_STF_SHIFT);
7369 }
7370 }
7371 return rts_rspec;
7372 }
7373
7374 void
7375 brcms_c_txfifo_complete(struct brcms_c_info *wlc, uint fifo)
7376 {
7377 wlc->core->txpktpend[fifo] -= 1;
7378 BCMMSG(wlc->wiphy, "pktpend dec 1 to %d\n",
7379 wlc->core->txpktpend[fifo]);
7380
7381 /* There is more room; mark precedences related to this FIFO sendable */
7382 wlc->tx_prec_map |= 1 << fifo;
7383
7384 /* figure out which bsscfg is being worked on... */
7385 }
7386
7387 /* Update beacon listen interval in shared memory */
7388 static void brcms_c_bcn_li_upd(struct brcms_c_info *wlc)
7389 {
7390 /* wake up every DTIM is the default */
7391 if (wlc->bcn_li_dtim == 1)
7392 brcms_b_write_shm(wlc->hw, M_BCN_LI, 0);
7393 else
7394 brcms_b_write_shm(wlc->hw, M_BCN_LI,
7395 (wlc->bcn_li_dtim << 8) | wlc->bcn_li_bcn);
7396 }
7397
7398 static void
7399 brcms_b_read_tsf(struct brcms_hardware *wlc_hw, u32 *tsf_l_ptr,
7400 u32 *tsf_h_ptr)
7401 {
7402 struct bcma_device *core = wlc_hw->d11core;
7403
7404 /* read the tsf timer low, then high to get an atomic read */
7405 *tsf_l_ptr = bcma_read32(core, D11REGOFFS(tsf_timerlow));
7406 *tsf_h_ptr = bcma_read32(core, D11REGOFFS(tsf_timerhigh));
7407 }
7408
7409 /*
7410 * recover 64bit TSF value from the 16bit TSF value in the rx header
7411 * given the assumption that the TSF passed in header is within 65ms
7412 * of the current tsf.
7413 *
7414 * 6 5 4 4 3 2 1
7415 * 3.......6.......8.......0.......2.......4.......6.......8......0
7416 * |<---------- tsf_h ----------->||<--- tsf_l -->||<-RxTSFTime ->|
7417 *
7418 * The RxTSFTime are the lowest 16 bits and provided by the ucode. The
7419 * tsf_l is filled in by brcms_b_recv, which is done earlier in the
7420 * receive call sequence after rx interrupt. Only the higher 16 bits
7421 * are used. Finally, the tsf_h is read from the tsf register.
7422 */
7423 static u64 brcms_c_recover_tsf64(struct brcms_c_info *wlc,
7424 struct d11rxhdr *rxh)
7425 {
7426 u32 tsf_h, tsf_l;
7427 u16 rx_tsf_0_15, rx_tsf_16_31;
7428
7429 brcms_b_read_tsf(wlc->hw, &tsf_l, &tsf_h);
7430
7431 rx_tsf_16_31 = (u16)(tsf_l >> 16);
7432 rx_tsf_0_15 = rxh->RxTSFTime;
7433
7434 /*
7435 * a greater tsf time indicates the low 16 bits of
7436 * tsf_l wrapped, so decrement the high 16 bits.
7437 */
7438 if ((u16)tsf_l < rx_tsf_0_15) {
7439 rx_tsf_16_31 -= 1;
7440 if (rx_tsf_16_31 == 0xffff)
7441 tsf_h -= 1;
7442 }
7443
7444 return ((u64)tsf_h << 32) | (((u32)rx_tsf_16_31 << 16) + rx_tsf_0_15);
7445 }
7446
7447 static void
7448 prep_mac80211_status(struct brcms_c_info *wlc, struct d11rxhdr *rxh,
7449 struct sk_buff *p,
7450 struct ieee80211_rx_status *rx_status)
7451 {
7452 int preamble;
7453 int channel;
7454 u32 rspec;
7455 unsigned char *plcp;
7456
7457 /* fill in TSF and flag its presence */
7458 rx_status->mactime = brcms_c_recover_tsf64(wlc, rxh);
7459 rx_status->flag |= RX_FLAG_MACTIME_MPDU;
7460
7461 channel = BRCMS_CHAN_CHANNEL(rxh->RxChan);
7462
7463 rx_status->band =
7464 channel > 14 ? IEEE80211_BAND_5GHZ : IEEE80211_BAND_2GHZ;
7465 rx_status->freq =
7466 ieee80211_channel_to_frequency(channel, rx_status->band);
7467
7468 rx_status->signal = wlc_phy_rssi_compute(wlc->hw->band->pi, rxh);
7469
7470 /* noise */
7471 /* qual */
7472 rx_status->antenna =
7473 (rxh->PhyRxStatus_0 & PRXS0_RXANT_UPSUBBAND) ? 1 : 0;
7474
7475 plcp = p->data;
7476
7477 rspec = brcms_c_compute_rspec(rxh, plcp);
7478 if (is_mcs_rate(rspec)) {
7479 rx_status->rate_idx = rspec & RSPEC_RATE_MASK;
7480 rx_status->flag |= RX_FLAG_HT;
7481 if (rspec_is40mhz(rspec))
7482 rx_status->flag |= RX_FLAG_40MHZ;
7483 } else {
7484 switch (rspec2rate(rspec)) {
7485 case BRCM_RATE_1M:
7486 rx_status->rate_idx = 0;
7487 break;
7488 case BRCM_RATE_2M:
7489 rx_status->rate_idx = 1;
7490 break;
7491 case BRCM_RATE_5M5:
7492 rx_status->rate_idx = 2;
7493 break;
7494 case BRCM_RATE_11M:
7495 rx_status->rate_idx = 3;
7496 break;
7497 case BRCM_RATE_6M:
7498 rx_status->rate_idx = 4;
7499 break;
7500 case BRCM_RATE_9M:
7501 rx_status->rate_idx = 5;
7502 break;
7503 case BRCM_RATE_12M:
7504 rx_status->rate_idx = 6;
7505 break;
7506 case BRCM_RATE_18M:
7507 rx_status->rate_idx = 7;
7508 break;
7509 case BRCM_RATE_24M:
7510 rx_status->rate_idx = 8;
7511 break;
7512 case BRCM_RATE_36M:
7513 rx_status->rate_idx = 9;
7514 break;
7515 case BRCM_RATE_48M:
7516 rx_status->rate_idx = 10;
7517 break;
7518 case BRCM_RATE_54M:
7519 rx_status->rate_idx = 11;
7520 break;
7521 default:
7522 wiphy_err(wlc->wiphy, "%s: Unknown rate\n", __func__);
7523 }
7524
7525 /*
7526 * For 5GHz, we should decrease the index as it is
7527 * a subset of the 2.4G rates. See bitrates field
7528 * of brcms_band_5GHz_nphy (in mac80211_if.c).
7529 */
7530 if (rx_status->band == IEEE80211_BAND_5GHZ)
7531 rx_status->rate_idx -= BRCMS_LEGACY_5G_RATE_OFFSET;
7532
7533 /* Determine short preamble and rate_idx */
7534 preamble = 0;
7535 if (is_cck_rate(rspec)) {
7536 if (rxh->PhyRxStatus_0 & PRXS0_SHORTH)
7537 rx_status->flag |= RX_FLAG_SHORTPRE;
7538 } else if (is_ofdm_rate(rspec)) {
7539 rx_status->flag |= RX_FLAG_SHORTPRE;
7540 } else {
7541 wiphy_err(wlc->wiphy, "%s: Unknown modulation\n",
7542 __func__);
7543 }
7544 }
7545
7546 if (plcp3_issgi(plcp[3]))
7547 rx_status->flag |= RX_FLAG_SHORT_GI;
7548
7549 if (rxh->RxStatus1 & RXS_DECERR) {
7550 rx_status->flag |= RX_FLAG_FAILED_PLCP_CRC;
7551 wiphy_err(wlc->wiphy, "%s: RX_FLAG_FAILED_PLCP_CRC\n",
7552 __func__);
7553 }
7554 if (rxh->RxStatus1 & RXS_FCSERR) {
7555 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
7556 wiphy_err(wlc->wiphy, "%s: RX_FLAG_FAILED_FCS_CRC\n",
7557 __func__);
7558 }
7559 }
7560
7561 static void
7562 brcms_c_recvctl(struct brcms_c_info *wlc, struct d11rxhdr *rxh,
7563 struct sk_buff *p)
7564 {
7565 int len_mpdu;
7566 struct ieee80211_rx_status rx_status;
7567 struct ieee80211_hdr *hdr;
7568
7569 memset(&rx_status, 0, sizeof(rx_status));
7570 prep_mac80211_status(wlc, rxh, p, &rx_status);
7571
7572 /* mac header+body length, exclude CRC and plcp header */
7573 len_mpdu = p->len - D11_PHY_HDR_LEN - FCS_LEN;
7574 skb_pull(p, D11_PHY_HDR_LEN);
7575 __skb_trim(p, len_mpdu);
7576
7577 /* unmute transmit */
7578 if (wlc->hw->suspended_fifos) {
7579 hdr = (struct ieee80211_hdr *)p->data;
7580 if (ieee80211_is_beacon(hdr->frame_control))
7581 brcms_b_mute(wlc->hw, false);
7582 }
7583
7584 memcpy(IEEE80211_SKB_RXCB(p), &rx_status, sizeof(rx_status));
7585 ieee80211_rx_irqsafe(wlc->pub->ieee_hw, p);
7586 }
7587
7588 /* calculate frame duration for Mixed-mode L-SIG spoofing, return
7589 * number of bytes goes in the length field
7590 *
7591 * Formula given by HT PHY Spec v 1.13
7592 * len = 3(nsyms + nstream + 3) - 3
7593 */
7594 u16
7595 brcms_c_calc_lsig_len(struct brcms_c_info *wlc, u32 ratespec,
7596 uint mac_len)
7597 {
7598 uint nsyms, len = 0, kNdps;
7599
7600 BCMMSG(wlc->wiphy, "wl%d: rate %d, len%d\n",
7601 wlc->pub->unit, rspec2rate(ratespec), mac_len);
7602
7603 if (is_mcs_rate(ratespec)) {
7604 uint mcs = ratespec & RSPEC_RATE_MASK;
7605 int tot_streams = (mcs_2_txstreams(mcs) + 1) +
7606 rspec_stc(ratespec);
7607
7608 /*
7609 * the payload duration calculation matches that
7610 * of regular ofdm
7611 */
7612 /* 1000Ndbps = kbps * 4 */
7613 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
7614 rspec_issgi(ratespec)) * 4;
7615
7616 if (rspec_stc(ratespec) == 0)
7617 nsyms =
7618 CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
7619 APHY_TAIL_NBITS) * 1000, kNdps);
7620 else
7621 /* STBC needs to have even number of symbols */
7622 nsyms =
7623 2 *
7624 CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
7625 APHY_TAIL_NBITS) * 1000, 2 * kNdps);
7626
7627 /* (+3) account for HT-SIG(2) and HT-STF(1) */
7628 nsyms += (tot_streams + 3);
7629 /*
7630 * 3 bytes/symbol @ legacy 6Mbps rate
7631 * (-3) excluding service bits and tail bits
7632 */
7633 len = (3 * nsyms) - 3;
7634 }
7635
7636 return (u16) len;
7637 }
7638
7639 static void
7640 brcms_c_mod_prb_rsp_rate_table(struct brcms_c_info *wlc, uint frame_len)
7641 {
7642 const struct brcms_c_rateset *rs_dflt;
7643 struct brcms_c_rateset rs;
7644 u8 rate;
7645 u16 entry_ptr;
7646 u8 plcp[D11_PHY_HDR_LEN];
7647 u16 dur, sifs;
7648 uint i;
7649
7650 sifs = get_sifs(wlc->band);
7651
7652 rs_dflt = brcms_c_rateset_get_hwrs(wlc);
7653
7654 brcms_c_rateset_copy(rs_dflt, &rs);
7655 brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams);
7656
7657 /*
7658 * walk the phy rate table and update MAC core SHM
7659 * basic rate table entries
7660 */
7661 for (i = 0; i < rs.count; i++) {
7662 rate = rs.rates[i] & BRCMS_RATE_MASK;
7663
7664 entry_ptr = brcms_b_rate_shm_offset(wlc->hw, rate);
7665
7666 /* Calculate the Probe Response PLCP for the given rate */
7667 brcms_c_compute_plcp(wlc, rate, frame_len, plcp);
7668
7669 /*
7670 * Calculate the duration of the Probe Response
7671 * frame plus SIFS for the MAC
7672 */
7673 dur = (u16) brcms_c_calc_frame_time(wlc, rate,
7674 BRCMS_LONG_PREAMBLE, frame_len);
7675 dur += sifs;
7676
7677 /* Update the SHM Rate Table entry Probe Response values */
7678 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_PLCP_POS,
7679 (u16) (plcp[0] + (plcp[1] << 8)));
7680 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_PLCP_POS + 2,
7681 (u16) (plcp[2] + (plcp[3] << 8)));
7682 brcms_b_write_shm(wlc->hw, entry_ptr + M_RT_PRS_DUR_POS, dur);
7683 }
7684 }
7685
7686 /* Max buffering needed for beacon template/prb resp template is 142 bytes.
7687 *
7688 * PLCP header is 6 bytes.
7689 * 802.11 A3 header is 24 bytes.
7690 * Max beacon frame body template length is 112 bytes.
7691 * Max probe resp frame body template length is 110 bytes.
7692 *
7693 * *len on input contains the max length of the packet available.
7694 *
7695 * The *len value is set to the number of bytes in buf used, and starts
7696 * with the PLCP and included up to, but not including, the 4 byte FCS.
7697 */
7698 static void
7699 brcms_c_bcn_prb_template(struct brcms_c_info *wlc, u16 type,
7700 u32 bcn_rspec,
7701 struct brcms_bss_cfg *cfg, u16 *buf, int *len)
7702 {
7703 static const u8 ether_bcast[ETH_ALEN] = {255, 255, 255, 255, 255, 255};
7704 struct cck_phy_hdr *plcp;
7705 struct ieee80211_mgmt *h;
7706 int hdr_len, body_len;
7707
7708 hdr_len = D11_PHY_HDR_LEN + DOT11_MAC_HDR_LEN;
7709
7710 /* calc buffer size provided for frame body */
7711 body_len = *len - hdr_len;
7712 /* return actual size */
7713 *len = hdr_len + body_len;
7714
7715 /* format PHY and MAC headers */
7716 memset((char *)buf, 0, hdr_len);
7717
7718 plcp = (struct cck_phy_hdr *) buf;
7719
7720 /*
7721 * PLCP for Probe Response frames are filled in from
7722 * core's rate table
7723 */
7724 if (type == IEEE80211_STYPE_BEACON)
7725 /* fill in PLCP */
7726 brcms_c_compute_plcp(wlc, bcn_rspec,
7727 (DOT11_MAC_HDR_LEN + body_len + FCS_LEN),
7728 (u8 *) plcp);
7729
7730 /* "Regular" and 16 MBSS but not for 4 MBSS */
7731 /* Update the phytxctl for the beacon based on the rspec */
7732 brcms_c_beacon_phytxctl_txant_upd(wlc, bcn_rspec);
7733
7734 h = (struct ieee80211_mgmt *)&plcp[1];
7735
7736 /* fill in 802.11 header */
7737 h->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT | type);
7738
7739 /* DUR is 0 for multicast bcn, or filled in by MAC for prb resp */
7740 /* A1 filled in by MAC for prb resp, broadcast for bcn */
7741 if (type == IEEE80211_STYPE_BEACON)
7742 memcpy(&h->da, &ether_bcast, ETH_ALEN);
7743 memcpy(&h->sa, &cfg->cur_etheraddr, ETH_ALEN);
7744 memcpy(&h->bssid, &cfg->BSSID, ETH_ALEN);
7745
7746 /* SEQ filled in by MAC */
7747 }
7748
7749 int brcms_c_get_header_len(void)
7750 {
7751 return TXOFF;
7752 }
7753
7754 /*
7755 * Update all beacons for the system.
7756 */
7757 void brcms_c_update_beacon(struct brcms_c_info *wlc)
7758 {
7759 struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
7760
7761 if (bsscfg->up && !bsscfg->BSS)
7762 /* Clear the soft intmask */
7763 wlc->defmacintmask &= ~MI_BCNTPL;
7764 }
7765
7766 /* Write ssid into shared memory */
7767 static void
7768 brcms_c_shm_ssid_upd(struct brcms_c_info *wlc, struct brcms_bss_cfg *cfg)
7769 {
7770 u8 *ssidptr = cfg->SSID;
7771 u16 base = M_SSID;
7772 u8 ssidbuf[IEEE80211_MAX_SSID_LEN];
7773
7774 /* padding the ssid with zero and copy it into shm */
7775 memset(ssidbuf, 0, IEEE80211_MAX_SSID_LEN);
7776 memcpy(ssidbuf, ssidptr, cfg->SSID_len);
7777
7778 brcms_c_copyto_shm(wlc, base, ssidbuf, IEEE80211_MAX_SSID_LEN);
7779 brcms_b_write_shm(wlc->hw, M_SSIDLEN, (u16) cfg->SSID_len);
7780 }
7781
7782 static void
7783 brcms_c_bss_update_probe_resp(struct brcms_c_info *wlc,
7784 struct brcms_bss_cfg *cfg,
7785 bool suspend)
7786 {
7787 u16 prb_resp[BCN_TMPL_LEN / 2];
7788 int len = BCN_TMPL_LEN;
7789
7790 /*
7791 * write the probe response to hardware, or save in
7792 * the config structure
7793 */
7794
7795 /* create the probe response template */
7796 brcms_c_bcn_prb_template(wlc, IEEE80211_STYPE_PROBE_RESP, 0,
7797 cfg, prb_resp, &len);
7798
7799 if (suspend)
7800 brcms_c_suspend_mac_and_wait(wlc);
7801
7802 /* write the probe response into the template region */
7803 brcms_b_write_template_ram(wlc->hw, T_PRS_TPL_BASE,
7804 (len + 3) & ~3, prb_resp);
7805
7806 /* write the length of the probe response frame (+PLCP/-FCS) */
7807 brcms_b_write_shm(wlc->hw, M_PRB_RESP_FRM_LEN, (u16) len);
7808
7809 /* write the SSID and SSID length */
7810 brcms_c_shm_ssid_upd(wlc, cfg);
7811
7812 /*
7813 * Write PLCP headers and durations for probe response frames
7814 * at all rates. Use the actual frame length covered by the
7815 * PLCP header for the call to brcms_c_mod_prb_rsp_rate_table()
7816 * by subtracting the PLCP len and adding the FCS.
7817 */
7818 len += (-D11_PHY_HDR_LEN + FCS_LEN);
7819 brcms_c_mod_prb_rsp_rate_table(wlc, (u16) len);
7820
7821 if (suspend)
7822 brcms_c_enable_mac(wlc);
7823 }
7824
7825 void brcms_c_update_probe_resp(struct brcms_c_info *wlc, bool suspend)
7826 {
7827 struct brcms_bss_cfg *bsscfg = wlc->bsscfg;
7828
7829 /* update AP or IBSS probe responses */
7830 if (bsscfg->up && !bsscfg->BSS)
7831 brcms_c_bss_update_probe_resp(wlc, bsscfg, suspend);
7832 }
7833
7834 /* prepares pdu for transmission. returns BCM error codes */
7835 int brcms_c_prep_pdu(struct brcms_c_info *wlc, struct sk_buff *pdu, uint *fifop)
7836 {
7837 uint fifo;
7838 struct d11txh *txh;
7839 struct ieee80211_hdr *h;
7840 struct scb *scb;
7841
7842 txh = (struct d11txh *) (pdu->data);
7843 h = (struct ieee80211_hdr *)((u8 *) (txh + 1) + D11_PHY_HDR_LEN);
7844
7845 /* get the pkt queue info. This was put at brcms_c_sendctl or
7846 * brcms_c_send for PDU */
7847 fifo = le16_to_cpu(txh->TxFrameID) & TXFID_QUEUE_MASK;
7848
7849 scb = NULL;
7850
7851 *fifop = fifo;
7852
7853 /* return if insufficient dma resources */
7854 if (*wlc->core->txavail[fifo] < MAX_DMA_SEGS) {
7855 /* Mark precedences related to this FIFO, unsendable */
7856 /* A fifo is full. Clear precedences related to that FIFO */
7857 wlc->tx_prec_map &= ~(1 << fifo);
7858 return -EBUSY;
7859 }
7860 return 0;
7861 }
7862
7863 int brcms_b_xmtfifo_sz_get(struct brcms_hardware *wlc_hw, uint fifo,
7864 uint *blocks)
7865 {
7866 if (fifo >= NFIFO)
7867 return -EINVAL;
7868
7869 *blocks = wlc_hw->xmtfifo_sz[fifo];
7870
7871 return 0;
7872 }
7873
7874 void
7875 brcms_c_set_addrmatch(struct brcms_c_info *wlc, int match_reg_offset,
7876 const u8 *addr)
7877 {
7878 brcms_b_set_addrmatch(wlc->hw, match_reg_offset, addr);
7879 if (match_reg_offset == RCM_BSSID_OFFSET)
7880 memcpy(wlc->bsscfg->BSSID, addr, ETH_ALEN);
7881 }
7882
7883 /*
7884 * Flag 'scan in progress' to withhold dynamic phy calibration
7885 */
7886 void brcms_c_scan_start(struct brcms_c_info *wlc)
7887 {
7888 wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, true);
7889 }
7890
7891 void brcms_c_scan_stop(struct brcms_c_info *wlc)
7892 {
7893 wlc_phy_hold_upd(wlc->band->pi, PHY_HOLD_FOR_SCAN, false);
7894 }
7895
7896 void brcms_c_associate_upd(struct brcms_c_info *wlc, bool state)
7897 {
7898 wlc->pub->associated = state;
7899 wlc->bsscfg->associated = state;
7900 }
7901
7902 /*
7903 * When a remote STA/AP is removed by Mac80211, or when it can no longer accept
7904 * AMPDU traffic, packets pending in hardware have to be invalidated so that
7905 * when later on hardware releases them, they can be handled appropriately.
7906 */
7907 void brcms_c_inval_dma_pkts(struct brcms_hardware *hw,
7908 struct ieee80211_sta *sta,
7909 void (*dma_callback_fn))
7910 {
7911 struct dma_pub *dmah;
7912 int i;
7913 for (i = 0; i < NFIFO; i++) {
7914 dmah = hw->di[i];
7915 if (dmah != NULL)
7916 dma_walk_packets(dmah, dma_callback_fn, sta);
7917 }
7918 }
7919
7920 int brcms_c_get_curband(struct brcms_c_info *wlc)
7921 {
7922 return wlc->band->bandunit;
7923 }
7924
7925 void brcms_c_wait_for_tx_completion(struct brcms_c_info *wlc, bool drop)
7926 {
7927 int timeout = 20;
7928
7929 /* flush packet queue when requested */
7930 if (drop)
7931 brcmu_pktq_flush(&wlc->pkt_queue->q, false, NULL, NULL);
7932
7933 /* wait for queue and DMA fifos to run dry */
7934 while (!pktq_empty(&wlc->pkt_queue->q) || brcms_txpktpendtot(wlc) > 0) {
7935 brcms_msleep(wlc->wl, 1);
7936
7937 if (--timeout == 0)
7938 break;
7939 }
7940
7941 WARN_ON_ONCE(timeout == 0);
7942 }
7943
7944 void brcms_c_set_beacon_listen_interval(struct brcms_c_info *wlc, u8 interval)
7945 {
7946 wlc->bcn_li_bcn = interval;
7947 if (wlc->pub->up)
7948 brcms_c_bcn_li_upd(wlc);
7949 }
7950
7951 int brcms_c_set_tx_power(struct brcms_c_info *wlc, int txpwr)
7952 {
7953 uint qdbm;
7954
7955 /* Remove override bit and clip to max qdbm value */
7956 qdbm = min_t(uint, txpwr * BRCMS_TXPWR_DB_FACTOR, 0xff);
7957 return wlc_phy_txpower_set(wlc->band->pi, qdbm, false);
7958 }
7959
7960 int brcms_c_get_tx_power(struct brcms_c_info *wlc)
7961 {
7962 uint qdbm;
7963 bool override;
7964
7965 wlc_phy_txpower_get(wlc->band->pi, &qdbm, &override);
7966
7967 /* Return qdbm units */
7968 return (int)(qdbm / BRCMS_TXPWR_DB_FACTOR);
7969 }
7970
7971 /* Process received frames */
7972 /*
7973 * Return true if more frames need to be processed. false otherwise.
7974 * Param 'bound' indicates max. # frames to process before break out.
7975 */
7976 static void brcms_c_recv(struct brcms_c_info *wlc, struct sk_buff *p)
7977 {
7978 struct d11rxhdr *rxh;
7979 struct ieee80211_hdr *h;
7980 uint len;
7981 bool is_amsdu;
7982
7983 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
7984
7985 /* frame starts with rxhdr */
7986 rxh = (struct d11rxhdr *) (p->data);
7987
7988 /* strip off rxhdr */
7989 skb_pull(p, BRCMS_HWRXOFF);
7990
7991 /* MAC inserts 2 pad bytes for a4 headers or QoS or A-MSDU subframes */
7992 if (rxh->RxStatus1 & RXS_PBPRES) {
7993 if (p->len < 2) {
7994 wiphy_err(wlc->wiphy, "wl%d: recv: rcvd runt of "
7995 "len %d\n", wlc->pub->unit, p->len);
7996 goto toss;
7997 }
7998 skb_pull(p, 2);
7999 }
8000
8001 h = (struct ieee80211_hdr *)(p->data + D11_PHY_HDR_LEN);
8002 len = p->len;
8003
8004 if (rxh->RxStatus1 & RXS_FCSERR) {
8005 if (!(wlc->filter_flags & FIF_FCSFAIL))
8006 goto toss;
8007 }
8008
8009 /* check received pkt has at least frame control field */
8010 if (len < D11_PHY_HDR_LEN + sizeof(h->frame_control))
8011 goto toss;
8012
8013 /* not supporting A-MSDU */
8014 is_amsdu = rxh->RxStatus2 & RXS_AMSDU_MASK;
8015 if (is_amsdu)
8016 goto toss;
8017
8018 brcms_c_recvctl(wlc, rxh, p);
8019 return;
8020
8021 toss:
8022 brcmu_pkt_buf_free_skb(p);
8023 }
8024
8025 /* Process received frames */
8026 /*
8027 * Return true if more frames need to be processed. false otherwise.
8028 * Param 'bound' indicates max. # frames to process before break out.
8029 */
8030 static bool
8031 brcms_b_recv(struct brcms_hardware *wlc_hw, uint fifo, bool bound)
8032 {
8033 struct sk_buff *p;
8034 struct sk_buff *next = NULL;
8035 struct sk_buff_head recv_frames;
8036
8037 uint n = 0;
8038 uint bound_limit = bound ? RXBND : -1;
8039
8040 BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
8041 skb_queue_head_init(&recv_frames);
8042
8043 /* gather received frames */
8044 while (dma_rx(wlc_hw->di[fifo], &recv_frames)) {
8045
8046 /* !give others some time to run! */
8047 if (++n >= bound_limit)
8048 break;
8049 }
8050
8051 /* post more rbufs */
8052 dma_rxfill(wlc_hw->di[fifo]);
8053
8054 /* process each frame */
8055 skb_queue_walk_safe(&recv_frames, p, next) {
8056 struct d11rxhdr_le *rxh_le;
8057 struct d11rxhdr *rxh;
8058
8059 skb_unlink(p, &recv_frames);
8060 rxh_le = (struct d11rxhdr_le *)p->data;
8061 rxh = (struct d11rxhdr *)p->data;
8062
8063 /* fixup rx header endianness */
8064 rxh->RxFrameSize = le16_to_cpu(rxh_le->RxFrameSize);
8065 rxh->PhyRxStatus_0 = le16_to_cpu(rxh_le->PhyRxStatus_0);
8066 rxh->PhyRxStatus_1 = le16_to_cpu(rxh_le->PhyRxStatus_1);
8067 rxh->PhyRxStatus_2 = le16_to_cpu(rxh_le->PhyRxStatus_2);
8068 rxh->PhyRxStatus_3 = le16_to_cpu(rxh_le->PhyRxStatus_3);
8069 rxh->PhyRxStatus_4 = le16_to_cpu(rxh_le->PhyRxStatus_4);
8070 rxh->PhyRxStatus_5 = le16_to_cpu(rxh_le->PhyRxStatus_5);
8071 rxh->RxStatus1 = le16_to_cpu(rxh_le->RxStatus1);
8072 rxh->RxStatus2 = le16_to_cpu(rxh_le->RxStatus2);
8073 rxh->RxTSFTime = le16_to_cpu(rxh_le->RxTSFTime);
8074 rxh->RxChan = le16_to_cpu(rxh_le->RxChan);
8075
8076 brcms_c_recv(wlc_hw->wlc, p);
8077 }
8078
8079 return n >= bound_limit;
8080 }
8081
8082 /* second-level interrupt processing
8083 * Return true if another dpc needs to be re-scheduled. false otherwise.
8084 * Param 'bounded' indicates if applicable loops should be bounded.
8085 */
8086 bool brcms_c_dpc(struct brcms_c_info *wlc, bool bounded)
8087 {
8088 u32 macintstatus;
8089 struct brcms_hardware *wlc_hw = wlc->hw;
8090 struct bcma_device *core = wlc_hw->d11core;
8091 struct wiphy *wiphy = wlc->wiphy;
8092
8093 if (brcms_deviceremoved(wlc)) {
8094 wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
8095 __func__);
8096 brcms_down(wlc->wl);
8097 return false;
8098 }
8099
8100 /* grab and clear the saved software intstatus bits */
8101 macintstatus = wlc->macintstatus;
8102 wlc->macintstatus = 0;
8103
8104 BCMMSG(wlc->wiphy, "wl%d: macintstatus 0x%x\n",
8105 wlc_hw->unit, macintstatus);
8106
8107 WARN_ON(macintstatus & MI_PRQ); /* PRQ Interrupt in non-MBSS */
8108
8109 /* tx status */
8110 if (macintstatus & MI_TFS) {
8111 bool fatal;
8112 if (brcms_b_txstatus(wlc->hw, bounded, &fatal))
8113 wlc->macintstatus |= MI_TFS;
8114 if (fatal) {
8115 wiphy_err(wiphy, "MI_TFS: fatal\n");
8116 goto fatal;
8117 }
8118 }
8119
8120 if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
8121 brcms_c_tbtt(wlc);
8122
8123 /* ATIM window end */
8124 if (macintstatus & MI_ATIMWINEND) {
8125 BCMMSG(wlc->wiphy, "end of ATIM window\n");
8126 bcma_set32(core, D11REGOFFS(maccommand), wlc->qvalid);
8127 wlc->qvalid = 0;
8128 }
8129
8130 /*
8131 * received data or control frame, MI_DMAINT is
8132 * indication of RX_FIFO interrupt
8133 */
8134 if (macintstatus & MI_DMAINT)
8135 if (brcms_b_recv(wlc_hw, RX_FIFO, bounded))
8136 wlc->macintstatus |= MI_DMAINT;
8137
8138 /* noise sample collected */
8139 if (macintstatus & MI_BG_NOISE)
8140 wlc_phy_noise_sample_intr(wlc_hw->band->pi);
8141
8142 if (macintstatus & MI_GP0) {
8143 wiphy_err(wiphy, "wl%d: PSM microcode watchdog fired at %d "
8144 "(seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now);
8145
8146 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
8147 __func__, ai_get_chip_id(wlc_hw->sih),
8148 ai_get_chiprev(wlc_hw->sih));
8149 brcms_fatal_error(wlc_hw->wlc->wl);
8150 }
8151
8152 /* gptimer timeout */
8153 if (macintstatus & MI_TO)
8154 bcma_write32(core, D11REGOFFS(gptimer), 0);
8155
8156 if (macintstatus & MI_RFDISABLE) {
8157 BCMMSG(wlc->wiphy, "wl%d: BMAC Detected a change on the"
8158 " RF Disable Input\n", wlc_hw->unit);
8159 brcms_rfkill_set_hw_state(wlc->wl);
8160 }
8161
8162 /* send any enq'd tx packets. Just makes sure to jump start tx */
8163 if (!pktq_empty(&wlc->pkt_queue->q))
8164 brcms_c_send_q(wlc);
8165
8166 /* it isn't done and needs to be resched if macintstatus is non-zero */
8167 return wlc->macintstatus != 0;
8168
8169 fatal:
8170 brcms_fatal_error(wlc_hw->wlc->wl);
8171 return wlc->macintstatus != 0;
8172 }
8173
8174 void brcms_c_init(struct brcms_c_info *wlc, bool mute_tx)
8175 {
8176 struct bcma_device *core = wlc->hw->d11core;
8177 struct ieee80211_channel *ch = wlc->pub->ieee_hw->conf.channel;
8178 u16 chanspec;
8179
8180 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
8181
8182 chanspec = ch20mhz_chspec(ch->hw_value);
8183
8184 brcms_b_init(wlc->hw, chanspec);
8185
8186 /* update beacon listen interval */
8187 brcms_c_bcn_li_upd(wlc);
8188
8189 /* write ethernet address to core */
8190 brcms_c_set_mac(wlc->bsscfg);
8191 brcms_c_set_bssid(wlc->bsscfg);
8192
8193 /* Update tsf_cfprep if associated and up */
8194 if (wlc->pub->associated && wlc->bsscfg->up) {
8195 u32 bi;
8196
8197 /* get beacon period and convert to uS */
8198 bi = wlc->bsscfg->current_bss->beacon_period << 10;
8199 /*
8200 * update since init path would reset
8201 * to default value
8202 */
8203 bcma_write32(core, D11REGOFFS(tsf_cfprep),
8204 bi << CFPREP_CBI_SHIFT);
8205
8206 /* Update maccontrol PM related bits */
8207 brcms_c_set_ps_ctrl(wlc);
8208 }
8209
8210 brcms_c_bandinit_ordered(wlc, chanspec);
8211
8212 /* init probe response timeout */
8213 brcms_b_write_shm(wlc->hw, M_PRS_MAXTIME, wlc->prb_resp_timeout);
8214
8215 /* init max burst txop (framebursting) */
8216 brcms_b_write_shm(wlc->hw, M_MBURST_TXOP,
8217 (wlc->
8218 _rifs ? (EDCF_AC_VO_TXOP_AP << 5) : MAXFRAMEBURST_TXOP));
8219
8220 /* initialize maximum allowed duty cycle */
8221 brcms_c_duty_cycle_set(wlc, wlc->tx_duty_cycle_ofdm, true, true);
8222 brcms_c_duty_cycle_set(wlc, wlc->tx_duty_cycle_cck, false, true);
8223
8224 /*
8225 * Update some shared memory locations related to
8226 * max AMPDU size allowed to received
8227 */
8228 brcms_c_ampdu_shm_upd(wlc->ampdu);
8229
8230 /* band-specific inits */
8231 brcms_c_bsinit(wlc);
8232
8233 /* Enable EDCF mode (while the MAC is suspended) */
8234 bcma_set16(core, D11REGOFFS(ifs_ctl), IFS_USEEDCF);
8235 brcms_c_edcf_setparams(wlc, false);
8236
8237 /* Init precedence maps for empty FIFOs */
8238 brcms_c_tx_prec_map_init(wlc);
8239
8240 /* read the ucode version if we have not yet done so */
8241 if (wlc->ucode_rev == 0) {
8242 wlc->ucode_rev =
8243 brcms_b_read_shm(wlc->hw, M_BOM_REV_MAJOR) << NBITS(u16);
8244 wlc->ucode_rev |= brcms_b_read_shm(wlc->hw, M_BOM_REV_MINOR);
8245 }
8246
8247 /* ..now really unleash hell (allow the MAC out of suspend) */
8248 brcms_c_enable_mac(wlc);
8249
8250 /* suspend the tx fifos and mute the phy for preism cac time */
8251 if (mute_tx)
8252 brcms_b_mute(wlc->hw, true);
8253
8254 /* enable the RF Disable Delay timer */
8255 bcma_write32(core, D11REGOFFS(rfdisabledly), RFDISABLE_DEFAULT);
8256
8257 /*
8258 * Initialize WME parameters; if they haven't been set by some other
8259 * mechanism (IOVar, etc) then read them from the hardware.
8260 */
8261 if (GFIELD(wlc->wme_retries[0], EDCF_SHORT) == 0) {
8262 /* Uninitialized; read from HW */
8263 int ac;
8264
8265 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
8266 wlc->wme_retries[ac] =
8267 brcms_b_read_shm(wlc->hw, M_AC_TXLMT_ADDR(ac));
8268 }
8269 }
8270
8271 /*
8272 * The common driver entry routine. Error codes should be unique
8273 */
8274 struct brcms_c_info *
8275 brcms_c_attach(struct brcms_info *wl, struct bcma_device *core, uint unit,
8276 bool piomode, uint *perr)
8277 {
8278 struct brcms_c_info *wlc;
8279 uint err = 0;
8280 uint i, j;
8281 struct brcms_pub *pub;
8282
8283 /* allocate struct brcms_c_info state and its substructures */
8284 wlc = brcms_c_attach_malloc(unit, &err, 0);
8285 if (wlc == NULL)
8286 goto fail;
8287 wlc->wiphy = wl->wiphy;
8288 pub = wlc->pub;
8289
8290 #if defined(DEBUG)
8291 wlc_info_dbg = wlc;
8292 #endif
8293
8294 wlc->band = wlc->bandstate[0];
8295 wlc->core = wlc->corestate;
8296 wlc->wl = wl;
8297 pub->unit = unit;
8298 pub->_piomode = piomode;
8299 wlc->bandinit_pending = false;
8300
8301 /* populate struct brcms_c_info with default values */
8302 brcms_c_info_init(wlc, unit);
8303
8304 /* update sta/ap related parameters */
8305 brcms_c_ap_upd(wlc);
8306
8307 /*
8308 * low level attach steps(all hw accesses go
8309 * inside, no more in rest of the attach)
8310 */
8311 err = brcms_b_attach(wlc, core, unit, piomode);
8312 if (err)
8313 goto fail;
8314
8315 brcms_c_protection_upd(wlc, BRCMS_PROT_N_PAM_OVR, OFF);
8316
8317 pub->phy_11ncapable = BRCMS_PHY_11N_CAP(wlc->band);
8318
8319 /* disable allowed duty cycle */
8320 wlc->tx_duty_cycle_ofdm = 0;
8321 wlc->tx_duty_cycle_cck = 0;
8322
8323 brcms_c_stf_phy_chain_calc(wlc);
8324
8325 /* txchain 1: txant 0, txchain 2: txant 1 */
8326 if (BRCMS_ISNPHY(wlc->band) && (wlc->stf->txstreams == 1))
8327 wlc->stf->txant = wlc->stf->hw_txchain - 1;
8328
8329 /* push to BMAC driver */
8330 wlc_phy_stf_chain_init(wlc->band->pi, wlc->stf->hw_txchain,
8331 wlc->stf->hw_rxchain);
8332
8333 /* pull up some info resulting from the low attach */
8334 for (i = 0; i < NFIFO; i++)
8335 wlc->core->txavail[i] = wlc->hw->txavail[i];
8336
8337 memcpy(&wlc->perm_etheraddr, &wlc->hw->etheraddr, ETH_ALEN);
8338 memcpy(&pub->cur_etheraddr, &wlc->hw->etheraddr, ETH_ALEN);
8339
8340 for (j = 0; j < wlc->pub->_nbands; j++) {
8341 wlc->band = wlc->bandstate[j];
8342
8343 if (!brcms_c_attach_stf_ant_init(wlc)) {
8344 err = 24;
8345 goto fail;
8346 }
8347
8348 /* default contention windows size limits */
8349 wlc->band->CWmin = APHY_CWMIN;
8350 wlc->band->CWmax = PHY_CWMAX;
8351
8352 /* init gmode value */
8353 if (wlc->band->bandtype == BRCM_BAND_2G) {
8354 wlc->band->gmode = GMODE_AUTO;
8355 brcms_c_protection_upd(wlc, BRCMS_PROT_G_USER,
8356 wlc->band->gmode);
8357 }
8358
8359 /* init _n_enab supported mode */
8360 if (BRCMS_PHY_11N_CAP(wlc->band)) {
8361 pub->_n_enab = SUPPORT_11N;
8362 brcms_c_protection_upd(wlc, BRCMS_PROT_N_USER,
8363 ((pub->_n_enab ==
8364 SUPPORT_11N) ? WL_11N_2x2 :
8365 WL_11N_3x3));
8366 }
8367
8368 /* init per-band default rateset, depend on band->gmode */
8369 brcms_default_rateset(wlc, &wlc->band->defrateset);
8370
8371 /* fill in hw_rateset */
8372 brcms_c_rateset_filter(&wlc->band->defrateset,
8373 &wlc->band->hw_rateset, false,
8374 BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK,
8375 (bool) (wlc->pub->_n_enab & SUPPORT_11N));
8376 }
8377
8378 /*
8379 * update antenna config due to
8380 * wlc->stf->txant/txchain/ant_rx_ovr change
8381 */
8382 brcms_c_stf_phy_txant_upd(wlc);
8383
8384 /* attach each modules */
8385 err = brcms_c_attach_module(wlc);
8386 if (err != 0)
8387 goto fail;
8388
8389 if (!brcms_c_timers_init(wlc, unit)) {
8390 wiphy_err(wl->wiphy, "wl%d: %s: init_timer failed\n", unit,
8391 __func__);
8392 err = 32;
8393 goto fail;
8394 }
8395
8396 /* depend on rateset, gmode */
8397 wlc->cmi = brcms_c_channel_mgr_attach(wlc);
8398 if (!wlc->cmi) {
8399 wiphy_err(wl->wiphy, "wl%d: %s: channel_mgr_attach failed"
8400 "\n", unit, __func__);
8401 err = 33;
8402 goto fail;
8403 }
8404
8405 /* init default when all parameters are ready, i.e. ->rateset */
8406 brcms_c_bss_default_init(wlc);
8407
8408 /*
8409 * Complete the wlc default state initializations..
8410 */
8411
8412 /* allocate our initial queue */
8413 wlc->pkt_queue = brcms_c_txq_alloc(wlc);
8414 if (wlc->pkt_queue == NULL) {
8415 wiphy_err(wl->wiphy, "wl%d: %s: failed to malloc tx queue\n",
8416 unit, __func__);
8417 err = 100;
8418 goto fail;
8419 }
8420
8421 wlc->bsscfg->wlc = wlc;
8422
8423 wlc->mimoft = FT_HT;
8424 wlc->mimo_40txbw = AUTO;
8425 wlc->ofdm_40txbw = AUTO;
8426 wlc->cck_40txbw = AUTO;
8427 brcms_c_update_mimo_band_bwcap(wlc, BRCMS_N_BW_20IN2G_40IN5G);
8428
8429 /* Set default values of SGI */
8430 if (BRCMS_SGI_CAP_PHY(wlc)) {
8431 brcms_c_ht_update_sgi_rx(wlc, (BRCMS_N_SGI_20 |
8432 BRCMS_N_SGI_40));
8433 } else if (BRCMS_ISSSLPNPHY(wlc->band)) {
8434 brcms_c_ht_update_sgi_rx(wlc, (BRCMS_N_SGI_20 |
8435 BRCMS_N_SGI_40));
8436 } else {
8437 brcms_c_ht_update_sgi_rx(wlc, 0);
8438 }
8439
8440 brcms_b_antsel_set(wlc->hw, wlc->asi->antsel_avail);
8441
8442 if (perr)
8443 *perr = 0;
8444
8445 return wlc;
8446
8447 fail:
8448 wiphy_err(wl->wiphy, "wl%d: %s: failed with err %d\n",
8449 unit, __func__, err);
8450 if (wlc)
8451 brcms_c_detach(wlc);
8452
8453 if (perr)
8454 *perr = err;
8455 return NULL;
8456 }