drivers/net/wireless/iwlwifi/iwl-helpers.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
   4  *
   5  * Portions of this file are derived from the ipw3945 project, as well
   6  * as portions of the ieee80211 subsystem header files.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of version 2 of the GNU General Public License as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20  *
  21  * The full GNU General Public License is included in this distribution in the
  22  * file called LICENSE.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29
  30 #ifndef __iwl_helpers_h__
  31 #define __iwl_helpers_h__
  32
  33 #include <linux/ctype.h>
  34 #include <net/mac80211.h>
  35
  36 #include "iwl-io.h"
  37
  38 #define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo))))
  39
  40
  41 static inline struct ieee80211_conf *ieee80211_get_hw_conf(
  42         struct ieee80211_hw *hw)
  43 {
  44         return &hw->conf;
  45 }
  46
  47 /**
  48  * iwl_queue_inc_wrap - increment queue index, wrap back to beginning
  49  * @index -- current index
  50  * @n_bd -- total number of entries in queue (must be power of 2)
  51  */
  52 static inline int iwl_queue_inc_wrap(int index, int n_bd)
  53 {
  54         return ++index & (n_bd - 1);
  55 }
  56
  57 /**
  58  * iwl_queue_dec_wrap - decrement queue index, wrap back to end
  59  * @index -- current index
  60  * @n_bd -- total number of entries in queue (must be power of 2)
  61  */
  62 static inline int iwl_queue_dec_wrap(int index, int n_bd)
  63 {
  64         return --index & (n_bd - 1);
  65 }
  66
  67 /* TODO: Move fw_desc functions to iwl-pci.ko */
  68 static inline void iwl_free_fw_desc(struct pci_dev *pci_dev,
  69                                     struct fw_desc *desc)
  70 {
  71         if (desc->v_addr)
  72                 dma_free_coherent(&pci_dev->dev, desc->len,
  73                                   desc->v_addr, desc->p_addr);
  74         desc->v_addr = NULL;
  75         desc->len = 0;
  76 }
  77
  78 static inline int iwl_alloc_fw_desc(struct pci_dev *pci_dev,
  79                                     struct fw_desc *desc)
  80 {
  81         if (!desc->len) {
  82                 desc->v_addr = NULL;
  83                 return -EINVAL;
  84         }
  85
  86         desc->v_addr = dma_alloc_coherent(&pci_dev->dev, desc->len,
  87                                           &desc->p_addr, GFP_KERNEL);
  88         return (desc->v_addr != NULL) ? 0 : -ENOMEM;
  89 }
  90
  91 /*
  92  * we have 8 bits used like this:
  93  *
  94  * 7 6 5 4 3 2 1 0
  95  * | | | | | | | |
  96  * | | | | | | +-+-------- AC queue (0-3)
  97  * | | | | | |
  98  * | +-+-+-+-+------------ HW queue ID
  99  * |
 100  * +---------------------- unused
 101  */
 102 static inline void iwl_set_swq_id(struct iwl_tx_queue *txq, u8 ac, u8 hwq)
 103 {
 104         BUG_ON(ac > 3);   /* only have 2 bits */
 105         BUG_ON(hwq > 31); /* only use 5 bits */
 106
 107         txq->swq_id = (hwq << 2) | ac;
 108 }
 109
 110 static inline void iwl_wake_queue(struct iwl_priv *priv,
 111                                   struct iwl_tx_queue *txq)
 112 {
 113         u8 queue = txq->swq_id;
 114         u8 ac = queue & 3;
 115         u8 hwq = (queue >> 2) & 0x1f;
 116
 117         if (test_and_clear_bit(hwq, priv->queue_stopped))
 118                 if (atomic_dec_return(&priv->queue_stop_count[ac]) <= 0)
 119                         ieee80211_wake_queue(priv->hw, ac);
 120 }
 121
 122 static inline void iwl_stop_queue(struct iwl_priv *priv,
 123                                   struct iwl_tx_queue *txq)
 124 {
 125         u8 queue = txq->swq_id;
 126         u8 ac = queue & 3;
 127         u8 hwq = (queue >> 2) & 0x1f;
 128
 129         if (!test_and_set_bit(hwq, priv->queue_stopped))
 130                 if (atomic_inc_return(&priv->queue_stop_count[ac]) > 0)
 131                         ieee80211_stop_queue(priv->hw, ac);
 132 }
 133
 134 #define ieee80211_stop_queue DO_NOT_USE_ieee80211_stop_queue
 135 #define ieee80211_wake_queue DO_NOT_USE_ieee80211_wake_queue
 136
 137 static inline void iwl_disable_interrupts(struct iwl_priv *priv)
 138 {
 139         clear_bit(STATUS_INT_ENABLED, &priv->status);
 140
 141         /* disable interrupts from uCode/NIC to host */
 142         iwl_write32(priv, CSR_INT_MASK, 0x00000000);
 143
 144         /* acknowledge/clear/reset any interrupts still pending
 145          * from uCode or flow handler (Rx/Tx DMA) */
 146         iwl_write32(priv, CSR_INT, 0xffffffff);
 147         iwl_write32(priv, CSR_FH_INT_STATUS, 0xffffffff);
 148         IWL_DEBUG_ISR(priv, "Disabled interrupts\n");
 149 }
 150
 151 static inline void iwl_enable_rfkill_int(struct iwl_priv *priv)
 152 {
 153         IWL_DEBUG_ISR(priv, "Enabling rfkill interrupt\n");
 154         iwl_write32(priv, CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
 155 }
 156
 157 static inline void iwl_enable_interrupts(struct iwl_priv *priv)
 158 {
 159         IWL_DEBUG_ISR(priv, "Enabling interrupts\n");
 160         set_bit(STATUS_INT_ENABLED, &priv->status);
 161         iwl_write32(priv, CSR_INT_MASK, priv->inta_mask);
 162 }
 163
 164 /**
 165  * iwl_beacon_time_mask_low - mask of lower 32 bit of beacon time
 166  * @priv -- pointer to iwl_priv data structure
 167  * @tsf_bits -- number of bits need to shift for masking)
 168  */
 169 static inline u32 iwl_beacon_time_mask_low(struct iwl_priv *priv,
 170                                            u16 tsf_bits)
 171 {
 172         return (1 << tsf_bits) - 1;
 173 }
 174
 175 /**
 176  * iwl_beacon_time_mask_high - mask of higher 32 bit of beacon time
 177  * @priv -- pointer to iwl_priv data structure
 178  * @tsf_bits -- number of bits need to shift for masking)
 179  */
 180 static inline u32 iwl_beacon_time_mask_high(struct iwl_priv *priv,
 181                                             u16 tsf_bits)
 182 {
 183         return ((1 << (32 - tsf_bits)) - 1) << tsf_bits;
 184 }
 185
 186 #endif                          /* __iwl_helpers_h__ */