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rtlwifi: Modify core.c for new drivers
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / rtlwifi / wifi.h
1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30 #ifndef __RTL_WIFI_H__
31 #define __RTL_WIFI_H__
32
33 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
34
35 #include <linux/sched.h>
36 #include <linux/firmware.h>
37 #include <linux/etherdevice.h>
38 #include <linux/vmalloc.h>
39 #include <linux/usb.h>
40 #include <net/mac80211.h>
41 #include <linux/completion.h>
42 #include "debug.h"
43
44 #define MASKBYTE0 0xff
45 #define MASKBYTE1 0xff00
46 #define MASKBYTE2 0xff0000
47 #define MASKBYTE3 0xff000000
48 #define MASKHWORD 0xffff0000
49 #define MASKLWORD 0x0000ffff
50 #define MASKDWORD 0xffffffff
51 #define MASK12BITS 0xfff
52 #define MASKH4BITS 0xf0000000
53 #define MASKOFDM_D 0xffc00000
54 #define MASKCCK 0x3f3f3f3f
55
56 #define MASK4BITS 0x0f
57 #define MASK20BITS 0xfffff
58 #define RFREG_OFFSET_MASK 0xfffff
59
60 #define MASKBYTE0 0xff
61 #define MASKBYTE1 0xff00
62 #define MASKBYTE2 0xff0000
63 #define MASKBYTE3 0xff000000
64 #define MASKHWORD 0xffff0000
65 #define MASKLWORD 0x0000ffff
66 #define MASKDWORD 0xffffffff
67 #define MASK12BITS 0xfff
68 #define MASKH4BITS 0xf0000000
69 #define MASKOFDM_D 0xffc00000
70 #define MASKCCK 0x3f3f3f3f
71
72 #define MASK4BITS 0x0f
73 #define MASK20BITS 0xfffff
74 #define RFREG_OFFSET_MASK 0xfffff
75
76 #define RF_CHANGE_BY_INIT 0
77 #define RF_CHANGE_BY_IPS BIT(28)
78 #define RF_CHANGE_BY_PS BIT(29)
79 #define RF_CHANGE_BY_HW BIT(30)
80 #define RF_CHANGE_BY_SW BIT(31)
81
82 #define IQK_ADDA_REG_NUM 16
83 #define IQK_MAC_REG_NUM 4
84 #define IQK_THRESHOLD 8
85
86 #define MAX_KEY_LEN 61
87 #define KEY_BUF_SIZE 5
88
89 /* QoS related. */
90 /*aci: 0x00 Best Effort*/
91 /*aci: 0x01 Background*/
92 /*aci: 0x10 Video*/
93 /*aci: 0x11 Voice*/
94 /*Max: define total number.*/
95 #define AC0_BE 0
96 #define AC1_BK 1
97 #define AC2_VI 2
98 #define AC3_VO 3
99 #define AC_MAX 4
100 #define QOS_QUEUE_NUM 4
101 #define RTL_MAC80211_NUM_QUEUE 5
102 #define REALTEK_USB_VENQT_MAX_BUF_SIZE 254
103 #define RTL_USB_MAX_RX_COUNT 100
104 #define QBSS_LOAD_SIZE 5
105 #define MAX_WMMELE_LENGTH 64
106
107 #define TOTAL_CAM_ENTRY 32
108
109 /*slot time for 11g. */
110 #define RTL_SLOT_TIME_9 9
111 #define RTL_SLOT_TIME_20 20
112
113 /*related to tcp/ip. */
114 #define SNAP_SIZE 6
115 #define PROTOC_TYPE_SIZE 2
116
117 /*related with 802.11 frame*/
118 #define MAC80211_3ADDR_LEN 24
119 #define MAC80211_4ADDR_LEN 30
120
121 #define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */
122 #define CHANNEL_MAX_NUMBER_2G 14
123 #define CHANNEL_MAX_NUMBER_5G 54 /* Please refer to
124 *"phy_GetChnlGroup8812A" and
125 * "Hal_ReadTxPowerInfo8812A"
126 */
127 #define CHANNEL_MAX_NUMBER_5G_80M 7
128 #define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */
129 #define CHANNEL_MAX_NUMBER_5G 54 /* Please refer to
130 *"phy_GetChnlGroup8812A" and
131 * "Hal_ReadTxPowerInfo8812A"
132 */
133 #define CHANNEL_MAX_NUMBER_5G_80M 7
134 #define MAX_PG_GROUP 13
135 #define CHANNEL_GROUP_MAX_2G 3
136 #define CHANNEL_GROUP_IDX_5GL 3
137 #define CHANNEL_GROUP_IDX_5GM 6
138 #define CHANNEL_GROUP_IDX_5GH 9
139 #define CHANNEL_GROUP_MAX_5G 9
140 #define CHANNEL_MAX_NUMBER_2G 14
141 #define AVG_THERMAL_NUM 8
142 #define AVG_THERMAL_NUM_88E 4
143 #define AVG_THERMAL_NUM_8723BE 4
144 #define MAX_TID_COUNT 9
145
146 /* for early mode */
147 #define FCS_LEN 4
148 #define EM_HDR_LEN 8
149
150 #define MAX_TX_COUNT 4
151 #define MAX_RF_PATH 4
152 #define MAX_CHNL_GROUP_24G 6
153 #define MAX_CHNL_GROUP_5G 14
154
155 #define TX_PWR_BY_RATE_NUM_BAND 2
156 #define TX_PWR_BY_RATE_NUM_RF 4
157 #define TX_PWR_BY_RATE_NUM_SECTION 12
158 #define MAX_BASE_NUM_IN_PHY_REG_PG_24G 6
159 #define MAX_BASE_NUM_IN_PHY_REG_PG_5G 5
160
161 #define RTL8192EE_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */
162
163 #define DEL_SW_IDX_SZ 30
164 #define BAND_NUM 3
165
166 /* For now, it's just for 8192ee
167 * but not OK yet, keep it 0
168 */
169 #define DMA_IS_64BIT 0
170 #define RTL8192EE_SEG_NUM 1 /* 0:2 seg, 1: 4 seg, 2: 8 seg */
171
172 enum rf_tx_num {
173 RF_1TX = 0,
174 RF_2TX,
175 RF_MAX_TX_NUM,
176 RF_TX_NUM_NONIMPLEMENT,
177 };
178
179 #define PACKET_NORMAL 0
180 #define PACKET_DHCP 1
181 #define PACKET_ARP 2
182 #define PACKET_EAPOL 3
183
184 #define MAX_SUPPORT_WOL_PATTERN_NUM 16
185 #define RSVD_WOL_PATTERN_NUM 1
186 #define WKFMCAM_ADDR_NUM 6
187 #define WKFMCAM_SIZE 24
188
189 #define MAX_WOL_BIT_MASK_SIZE 16
190 /* MIN LEN keeps 13 here */
191 #define MIN_WOL_PATTERN_SIZE 13
192 #define MAX_WOL_PATTERN_SIZE 128
193
194 #define WAKE_ON_MAGIC_PACKET BIT(0)
195 #define WAKE_ON_PATTERN_MATCH BIT(1)
196
197 #define WOL_REASON_PTK_UPDATE BIT(0)
198 #define WOL_REASON_GTK_UPDATE BIT(1)
199 #define WOL_REASON_DISASSOC BIT(2)
200 #define WOL_REASON_DEAUTH BIT(3)
201 #define WOL_REASON_AP_LOST BIT(4)
202 #define WOL_REASON_MAGIC_PKT BIT(5)
203 #define WOL_REASON_UNICAST_PKT BIT(6)
204 #define WOL_REASON_PATTERN_PKT BIT(7)
205 #define WOL_REASON_RTD3_SSID_MATCH BIT(8)
206 #define WOL_REASON_REALWOW_V2_WAKEUPPKT BIT(9)
207 #define WOL_REASON_REALWOW_V2_ACKLOST BIT(10)
208
209 struct txpower_info_2g {
210 u8 index_cck_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
211 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
212 /*If only one tx, only BW20 and OFDM are used.*/
213 u8 cck_diff[MAX_RF_PATH][MAX_TX_COUNT];
214 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
215 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
216 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
217 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
218 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
219 };
220
221 struct txpower_info_5g {
222 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_5G];
223 /*If only one tx, only BW20, OFDM, BW80 and BW160 are used.*/
224 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
225 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
226 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
227 u8 bw80_diff[MAX_RF_PATH][MAX_TX_COUNT];
228 u8 bw160_diff[MAX_RF_PATH][MAX_TX_COUNT];
229 };
230
231 enum rate_section {
232 CCK = 0,
233 OFDM,
234 HT_MCS0_MCS7,
235 HT_MCS8_MCS15,
236 VHT_1SSMCS0_1SSMCS9,
237 VHT_2SSMCS0_2SSMCS9,
238 };
239
240 enum intf_type {
241 INTF_PCI = 0,
242 INTF_USB = 1,
243 };
244
245 enum radio_path {
246 RF90_PATH_A = 0,
247 RF90_PATH_B = 1,
248 RF90_PATH_C = 2,
249 RF90_PATH_D = 3,
250 };
251
252 enum rt_eeprom_type {
253 EEPROM_93C46,
254 EEPROM_93C56,
255 EEPROM_BOOT_EFUSE,
256 };
257
258 enum ttl_status {
259 RTL_STATUS_INTERFACE_START = 0,
260 };
261
262 enum hardware_type {
263 HARDWARE_TYPE_RTL8192E,
264 HARDWARE_TYPE_RTL8192U,
265 HARDWARE_TYPE_RTL8192SE,
266 HARDWARE_TYPE_RTL8192SU,
267 HARDWARE_TYPE_RTL8192CE,
268 HARDWARE_TYPE_RTL8192CU,
269 HARDWARE_TYPE_RTL8192DE,
270 HARDWARE_TYPE_RTL8192DU,
271 HARDWARE_TYPE_RTL8723AE,
272 HARDWARE_TYPE_RTL8723U,
273 HARDWARE_TYPE_RTL8188EE,
274 HARDWARE_TYPE_RTL8723BE,
275 HARDWARE_TYPE_RTL8192EE,
276 HARDWARE_TYPE_RTL8821AE,
277 HARDWARE_TYPE_RTL8812AE,
278
279 /* keep it last */
280 HARDWARE_TYPE_NUM
281 };
282
283 #define IS_HARDWARE_TYPE_8192SU(rtlhal) \
284 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SU)
285 #define IS_HARDWARE_TYPE_8192SE(rtlhal) \
286 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
287 #define IS_HARDWARE_TYPE_8192CE(rtlhal) \
288 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE)
289 #define IS_HARDWARE_TYPE_8192CU(rtlhal) \
290 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CU)
291 #define IS_HARDWARE_TYPE_8192DE(rtlhal) \
292 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE)
293 #define IS_HARDWARE_TYPE_8192DU(rtlhal) \
294 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DU)
295 #define IS_HARDWARE_TYPE_8723E(rtlhal) \
296 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723E)
297 #define IS_HARDWARE_TYPE_8723U(rtlhal) \
298 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
299 #define IS_HARDWARE_TYPE_8192S(rtlhal) \
300 (IS_HARDWARE_TYPE_8192SE(rtlhal) || IS_HARDWARE_TYPE_8192SU(rtlhal))
301 #define IS_HARDWARE_TYPE_8192C(rtlhal) \
302 (IS_HARDWARE_TYPE_8192CE(rtlhal) || IS_HARDWARE_TYPE_8192CU(rtlhal))
303 #define IS_HARDWARE_TYPE_8192D(rtlhal) \
304 (IS_HARDWARE_TYPE_8192DE(rtlhal) || IS_HARDWARE_TYPE_8192DU(rtlhal))
305 #define IS_HARDWARE_TYPE_8723(rtlhal) \
306 (IS_HARDWARE_TYPE_8723E(rtlhal) || IS_HARDWARE_TYPE_8723U(rtlhal))
307
308 #define RX_HAL_IS_CCK_RATE(_pdesc)\
309 (_pdesc->rxmcs == DESC92_RATE1M || \
310 _pdesc->rxmcs == DESC92_RATE2M || \
311 _pdesc->rxmcs == DESC92_RATE5_5M || \
312 _pdesc->rxmcs == DESC92_RATE11M)
313
314 #define RTL8723E_RX_HAL_IS_CCK_RATE(rxmcs) \
315 ((rxmcs) == DESC92_RATE1M || \
316 (rxmcs) == DESC92_RATE2M || \
317 (rxmcs) == DESC92_RATE5_5M || \
318 (rxmcs) == DESC92_RATE11M)
319
320 enum scan_operation_backup_opt {
321 SCAN_OPT_BACKUP = 0,
322 SCAN_OPT_BACKUP_BAND0 = 0,
323 SCAN_OPT_BACKUP_BAND1,
324 SCAN_OPT_RESTORE,
325 SCAN_OPT_MAX
326 };
327
328 /*RF state.*/
329 enum rf_pwrstate {
330 ERFON,
331 ERFSLEEP,
332 ERFOFF
333 };
334
335 struct bb_reg_def {
336 u32 rfintfs;
337 u32 rfintfi;
338 u32 rfintfo;
339 u32 rfintfe;
340 u32 rf3wire_offset;
341 u32 rflssi_select;
342 u32 rftxgain_stage;
343 u32 rfhssi_para1;
344 u32 rfhssi_para2;
345 u32 rfsw_ctrl;
346 u32 rfagc_control1;
347 u32 rfagc_control2;
348 u32 rfrxiq_imbal;
349 u32 rfrx_afe;
350 u32 rftxiq_imbal;
351 u32 rftx_afe;
352 u32 rf_rb; /* rflssi_readback */
353 u32 rf_rbpi; /* rflssi_readbackpi */
354 };
355
356 enum io_type {
357 IO_CMD_PAUSE_DM_BY_SCAN = 0,
358 IO_CMD_PAUSE_BAND0_DM_BY_SCAN = 0,
359 IO_CMD_PAUSE_BAND1_DM_BY_SCAN = 1,
360 IO_CMD_RESUME_DM_BY_SCAN = 2,
361 };
362
363 enum hw_variables {
364 HW_VAR_ETHER_ADDR,
365 HW_VAR_MULTICAST_REG,
366 HW_VAR_BASIC_RATE,
367 HW_VAR_BSSID,
368 HW_VAR_MEDIA_STATUS,
369 HW_VAR_SECURITY_CONF,
370 HW_VAR_BEACON_INTERVAL,
371 HW_VAR_ATIM_WINDOW,
372 HW_VAR_LISTEN_INTERVAL,
373 HW_VAR_CS_COUNTER,
374 HW_VAR_DEFAULTKEY0,
375 HW_VAR_DEFAULTKEY1,
376 HW_VAR_DEFAULTKEY2,
377 HW_VAR_DEFAULTKEY3,
378 HW_VAR_SIFS,
379 HW_VAR_DIFS,
380 HW_VAR_EIFS,
381 HW_VAR_SLOT_TIME,
382 HW_VAR_ACK_PREAMBLE,
383 HW_VAR_CW_CONFIG,
384 HW_VAR_CW_VALUES,
385 HW_VAR_RATE_FALLBACK_CONTROL,
386 HW_VAR_CONTENTION_WINDOW,
387 HW_VAR_RETRY_COUNT,
388 HW_VAR_TR_SWITCH,
389 HW_VAR_COMMAND,
390 HW_VAR_WPA_CONFIG,
391 HW_VAR_AMPDU_MIN_SPACE,
392 HW_VAR_SHORTGI_DENSITY,
393 HW_VAR_AMPDU_FACTOR,
394 HW_VAR_MCS_RATE_AVAILABLE,
395 HW_VAR_AC_PARAM,
396 HW_VAR_ACM_CTRL,
397 HW_VAR_DIS_Req_Qsize,
398 HW_VAR_CCX_CHNL_LOAD,
399 HW_VAR_CCX_NOISE_HISTOGRAM,
400 HW_VAR_CCX_CLM_NHM,
401 HW_VAR_TxOPLimit,
402 HW_VAR_TURBO_MODE,
403 HW_VAR_RF_STATE,
404 HW_VAR_RF_OFF_BY_HW,
405 HW_VAR_BUS_SPEED,
406 HW_VAR_SET_DEV_POWER,
407
408 HW_VAR_RCR,
409 HW_VAR_RATR_0,
410 HW_VAR_RRSR,
411 HW_VAR_CPU_RST,
412 HW_VAR_CHECK_BSSID,
413 HW_VAR_LBK_MODE,
414 HW_VAR_AES_11N_FIX,
415 HW_VAR_USB_RX_AGGR,
416 HW_VAR_USER_CONTROL_TURBO_MODE,
417 HW_VAR_RETRY_LIMIT,
418 HW_VAR_INIT_TX_RATE,
419 HW_VAR_TX_RATE_REG,
420 HW_VAR_EFUSE_USAGE,
421 HW_VAR_EFUSE_BYTES,
422 HW_VAR_AUTOLOAD_STATUS,
423 HW_VAR_RF_2R_DISABLE,
424 HW_VAR_SET_RPWM,
425 HW_VAR_H2C_FW_PWRMODE,
426 HW_VAR_H2C_FW_JOINBSSRPT,
427 HW_VAR_H2C_FW_MEDIASTATUSRPT,
428 HW_VAR_H2C_FW_P2P_PS_OFFLOAD,
429 HW_VAR_FW_PSMODE_STATUS,
430 HW_VAR_RESUME_CLK_ON,
431 HW_VAR_FW_LPS_ACTION,
432 HW_VAR_1X1_RECV_COMBINE,
433 HW_VAR_STOP_SEND_BEACON,
434 HW_VAR_TSF_TIMER,
435 HW_VAR_IO_CMD,
436
437 HW_VAR_RF_RECOVERY,
438 HW_VAR_H2C_FW_UPDATE_GTK,
439 HW_VAR_WF_MASK,
440 HW_VAR_WF_CRC,
441 HW_VAR_WF_IS_MAC_ADDR,
442 HW_VAR_H2C_FW_OFFLOAD,
443 HW_VAR_RESET_WFCRC,
444
445 HW_VAR_HANDLE_FW_C2H,
446 HW_VAR_DL_FW_RSVD_PAGE,
447 HW_VAR_AID,
448 HW_VAR_HW_SEQ_ENABLE,
449 HW_VAR_CORRECT_TSF,
450 HW_VAR_BCN_VALID,
451 HW_VAR_FWLPS_RF_ON,
452 HW_VAR_DUAL_TSF_RST,
453 HW_VAR_SWITCH_EPHY_WoWLAN,
454 HW_VAR_INT_MIGRATION,
455 HW_VAR_INT_AC,
456 HW_VAR_RF_TIMING,
457
458 HAL_DEF_WOWLAN,
459 HW_VAR_MRC,
460 HW_VAR_KEEP_ALIVE,
461 HW_VAR_NAV_UPPER,
462
463 HW_VAR_MGT_FILTER,
464 HW_VAR_CTRL_FILTER,
465 HW_VAR_DATA_FILTER,
466 };
467
468 enum rt_media_status {
469 RT_MEDIA_DISCONNECT = 0,
470 RT_MEDIA_CONNECT = 1
471 };
472
473 enum rt_oem_id {
474 RT_CID_DEFAULT = 0,
475 RT_CID_8187_ALPHA0 = 1,
476 RT_CID_8187_SERCOMM_PS = 2,
477 RT_CID_8187_HW_LED = 3,
478 RT_CID_8187_NETGEAR = 4,
479 RT_CID_WHQL = 5,
480 RT_CID_819X_CAMEO = 6,
481 RT_CID_819X_RUNTOP = 7,
482 RT_CID_819X_SENAO = 8,
483 RT_CID_TOSHIBA = 9,
484 RT_CID_819X_NETCORE = 10,
485 RT_CID_NETTRONIX = 11,
486 RT_CID_DLINK = 12,
487 RT_CID_PRONET = 13,
488 RT_CID_COREGA = 14,
489 RT_CID_819X_ALPHA = 15,
490 RT_CID_819X_SITECOM = 16,
491 RT_CID_CCX = 17,
492 RT_CID_819X_LENOVO = 18,
493 RT_CID_819X_QMI = 19,
494 RT_CID_819X_EDIMAX_BELKIN = 20,
495 RT_CID_819X_SERCOMM_BELKIN = 21,
496 RT_CID_819X_CAMEO1 = 22,
497 RT_CID_819X_MSI = 23,
498 RT_CID_819X_ACER = 24,
499 RT_CID_819X_HP = 27,
500 RT_CID_819X_CLEVO = 28,
501 RT_CID_819X_ARCADYAN_BELKIN = 29,
502 RT_CID_819X_SAMSUNG = 30,
503 RT_CID_819X_WNC_COREGA = 31,
504 RT_CID_819X_FOXCOON = 32,
505 RT_CID_819X_DELL = 33,
506 RT_CID_819X_PRONETS = 34,
507 RT_CID_819X_EDIMAX_ASUS = 35,
508 RT_CID_NETGEAR = 36,
509 RT_CID_PLANEX = 37,
510 RT_CID_CC_C = 38,
511 };
512
513 enum hw_descs {
514 HW_DESC_OWN,
515 HW_DESC_RXOWN,
516 HW_DESC_TX_NEXTDESC_ADDR,
517 HW_DESC_TXBUFF_ADDR,
518 HW_DESC_RXBUFF_ADDR,
519 HW_DESC_RXPKT_LEN,
520 HW_DESC_RXERO,
521 HW_DESC_RX_PREPARE,
522 };
523
524 enum prime_sc {
525 PRIME_CHNL_OFFSET_DONT_CARE = 0,
526 PRIME_CHNL_OFFSET_LOWER = 1,
527 PRIME_CHNL_OFFSET_UPPER = 2,
528 };
529
530 enum rf_type {
531 RF_1T1R = 0,
532 RF_1T2R = 1,
533 RF_2T2R = 2,
534 RF_2T2R_GREEN = 3,
535 };
536
537 enum ht_channel_width {
538 HT_CHANNEL_WIDTH_20 = 0,
539 HT_CHANNEL_WIDTH_20_40 = 1,
540 HT_CHANNEL_WIDTH_80 = 2,
541 };
542
543 /* Ref: 802.11i sepc D10.0 7.3.2.25.1
544 Cipher Suites Encryption Algorithms */
545 enum rt_enc_alg {
546 NO_ENCRYPTION = 0,
547 WEP40_ENCRYPTION = 1,
548 TKIP_ENCRYPTION = 2,
549 RSERVED_ENCRYPTION = 3,
550 AESCCMP_ENCRYPTION = 4,
551 WEP104_ENCRYPTION = 5,
552 AESCMAC_ENCRYPTION = 6, /*IEEE802.11w */
553 };
554
555 enum rtl_hal_state {
556 _HAL_STATE_STOP = 0,
557 _HAL_STATE_START = 1,
558 };
559
560 enum rtl_desc92_rate {
561 DESC92_RATE1M = 0x00,
562 DESC92_RATE2M = 0x01,
563 DESC92_RATE5_5M = 0x02,
564 DESC92_RATE11M = 0x03,
565
566 DESC92_RATE6M = 0x04,
567 DESC92_RATE9M = 0x05,
568 DESC92_RATE12M = 0x06,
569 DESC92_RATE18M = 0x07,
570 DESC92_RATE24M = 0x08,
571 DESC92_RATE36M = 0x09,
572 DESC92_RATE48M = 0x0a,
573 DESC92_RATE54M = 0x0b,
574
575 DESC92_RATEMCS0 = 0x0c,
576 DESC92_RATEMCS1 = 0x0d,
577 DESC92_RATEMCS2 = 0x0e,
578 DESC92_RATEMCS3 = 0x0f,
579 DESC92_RATEMCS4 = 0x10,
580 DESC92_RATEMCS5 = 0x11,
581 DESC92_RATEMCS6 = 0x12,
582 DESC92_RATEMCS7 = 0x13,
583 DESC92_RATEMCS8 = 0x14,
584 DESC92_RATEMCS9 = 0x15,
585 DESC92_RATEMCS10 = 0x16,
586 DESC92_RATEMCS11 = 0x17,
587 DESC92_RATEMCS12 = 0x18,
588 DESC92_RATEMCS13 = 0x19,
589 DESC92_RATEMCS14 = 0x1a,
590 DESC92_RATEMCS15 = 0x1b,
591 DESC92_RATEMCS15_SG = 0x1c,
592 DESC92_RATEMCS32 = 0x20,
593 };
594
595 enum rtl_var_map {
596 /*reg map */
597 SYS_ISO_CTRL = 0,
598 SYS_FUNC_EN,
599 SYS_CLK,
600 MAC_RCR_AM,
601 MAC_RCR_AB,
602 MAC_RCR_ACRC32,
603 MAC_RCR_ACF,
604 MAC_RCR_AAP,
605 MAC_HIMR,
606 MAC_HIMRE,
607 MAC_HSISR,
608
609 /*efuse map */
610 EFUSE_TEST,
611 EFUSE_CTRL,
612 EFUSE_CLK,
613 EFUSE_CLK_CTRL,
614 EFUSE_PWC_EV12V,
615 EFUSE_FEN_ELDR,
616 EFUSE_LOADER_CLK_EN,
617 EFUSE_ANA8M,
618 EFUSE_HWSET_MAX_SIZE,
619 EFUSE_MAX_SECTION_MAP,
620 EFUSE_REAL_CONTENT_SIZE,
621 EFUSE_OOB_PROTECT_BYTES_LEN,
622 EFUSE_ACCESS,
623
624 /*CAM map */
625 RWCAM,
626 WCAMI,
627 RCAMO,
628 CAMDBG,
629 SECR,
630 SEC_CAM_NONE,
631 SEC_CAM_WEP40,
632 SEC_CAM_TKIP,
633 SEC_CAM_AES,
634 SEC_CAM_WEP104,
635
636 /*IMR map */
637 RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */
638 RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */
639 RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */
640 RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */
641 RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */
642 RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */
643 RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */
644 RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */
645 RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */
646 RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */
647 RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */
648 RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */
649 RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */
650 RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */
651 RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */
652 RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */
653 RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */
654 RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */
655 RTL_IMR_BCNINT, /*Beacon DMA Interrupt 0 */
656 RTL_IMR_RXFOVW, /*Receive FIFO Overflow */
657 RTL_IMR_RDU, /*Receive Descriptor Unavailable */
658 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */
659 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */
660 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */
661 RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/
662 RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */
663 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */
664 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */
665 RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */
666 RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */
667 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */
668 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */
669 RTL_IMR_ROK, /*Receive DMA OK Interrupt */
670 RTL_IMR_HSISR_IND, /*HSISR Interrupt*/
671 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BCNINT | RTL_IMR_TBDOK |
672 * RTL_IMR_TBDER) */
673 RTL_IMR_C2HCMD, /*fw interrupt*/
674
675 /*CCK Rates, TxHT = 0 */
676 RTL_RC_CCK_RATE1M,
677 RTL_RC_CCK_RATE2M,
678 RTL_RC_CCK_RATE5_5M,
679 RTL_RC_CCK_RATE11M,
680
681 /*OFDM Rates, TxHT = 0 */
682 RTL_RC_OFDM_RATE6M,
683 RTL_RC_OFDM_RATE9M,
684 RTL_RC_OFDM_RATE12M,
685 RTL_RC_OFDM_RATE18M,
686 RTL_RC_OFDM_RATE24M,
687 RTL_RC_OFDM_RATE36M,
688 RTL_RC_OFDM_RATE48M,
689 RTL_RC_OFDM_RATE54M,
690
691 RTL_RC_HT_RATEMCS7,
692 RTL_RC_HT_RATEMCS15,
693
694 /*keep it last */
695 RTL_VAR_MAP_MAX,
696 };
697
698 /*Firmware PS mode for control LPS.*/
699 enum _fw_ps_mode {
700 FW_PS_ACTIVE_MODE = 0,
701 FW_PS_MIN_MODE = 1,
702 FW_PS_MAX_MODE = 2,
703 FW_PS_DTIM_MODE = 3,
704 FW_PS_VOIP_MODE = 4,
705 FW_PS_UAPSD_WMM_MODE = 5,
706 FW_PS_UAPSD_MODE = 6,
707 FW_PS_IBSS_MODE = 7,
708 FW_PS_WWLAN_MODE = 8,
709 FW_PS_PM_Radio_Off = 9,
710 FW_PS_PM_Card_Disable = 10,
711 };
712
713 enum rt_psmode {
714 EACTIVE, /*Active/Continuous access. */
715 EMAXPS, /*Max power save mode. */
716 EFASTPS, /*Fast power save mode. */
717 EAUTOPS, /*Auto power save mode. */
718 };
719
720 /*LED related.*/
721 enum led_ctl_mode {
722 LED_CTL_POWER_ON = 1,
723 LED_CTL_LINK = 2,
724 LED_CTL_NO_LINK = 3,
725 LED_CTL_TX = 4,
726 LED_CTL_RX = 5,
727 LED_CTL_SITE_SURVEY = 6,
728 LED_CTL_POWER_OFF = 7,
729 LED_CTL_START_TO_LINK = 8,
730 LED_CTL_START_WPS = 9,
731 LED_CTL_STOP_WPS = 10,
732 };
733
734 enum rtl_led_pin {
735 LED_PIN_GPIO0,
736 LED_PIN_LED0,
737 LED_PIN_LED1,
738 LED_PIN_LED2
739 };
740
741 /*QoS related.*/
742 /*acm implementation method.*/
743 enum acm_method {
744 eAcmWay0_SwAndHw = 0,
745 eAcmWay1_HW = 1,
746 EACMWAY2_SW = 2,
747 };
748
749 enum macphy_mode {
750 SINGLEMAC_SINGLEPHY = 0,
751 DUALMAC_DUALPHY,
752 DUALMAC_SINGLEPHY,
753 };
754
755 enum band_type {
756 BAND_ON_2_4G = 0,
757 BAND_ON_5G,
758 BAND_ON_BOTH,
759 BANDMAX
760 };
761
762 /*aci/aifsn Field.
763 Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/
764 union aci_aifsn {
765 u8 char_data;
766
767 struct {
768 u8 aifsn:4;
769 u8 acm:1;
770 u8 aci:2;
771 u8 reserved:1;
772 } f; /* Field */
773 };
774
775 /*mlme related.*/
776 enum wireless_mode {
777 WIRELESS_MODE_UNKNOWN = 0x00,
778 WIRELESS_MODE_A = 0x01,
779 WIRELESS_MODE_B = 0x02,
780 WIRELESS_MODE_G = 0x04,
781 WIRELESS_MODE_AUTO = 0x08,
782 WIRELESS_MODE_N_24G = 0x10,
783 WIRELESS_MODE_N_5G = 0x20,
784 WIRELESS_MODE_AC_5G = 0x40,
785 WIRELESS_MODE_AC_24G = 0x80
786 };
787
788 #define IS_WIRELESS_MODE_A(wirelessmode) \
789 (wirelessmode == WIRELESS_MODE_A)
790 #define IS_WIRELESS_MODE_B(wirelessmode) \
791 (wirelessmode == WIRELESS_MODE_B)
792 #define IS_WIRELESS_MODE_G(wirelessmode) \
793 (wirelessmode == WIRELESS_MODE_G)
794 #define IS_WIRELESS_MODE_N_24G(wirelessmode) \
795 (wirelessmode == WIRELESS_MODE_N_24G)
796 #define IS_WIRELESS_MODE_N_5G(wirelessmode) \
797 (wirelessmode == WIRELESS_MODE_N_5G)
798
799 enum ratr_table_mode {
800 RATR_INX_WIRELESS_NGB = 0,
801 RATR_INX_WIRELESS_NG = 1,
802 RATR_INX_WIRELESS_NB = 2,
803 RATR_INX_WIRELESS_N = 3,
804 RATR_INX_WIRELESS_GB = 4,
805 RATR_INX_WIRELESS_G = 5,
806 RATR_INX_WIRELESS_B = 6,
807 RATR_INX_WIRELESS_MC = 7,
808 RATR_INX_WIRELESS_A = 8,
809 RATR_INX_WIRELESS_AC_5N = 8,
810 RATR_INX_WIRELESS_AC_24N = 9,
811 };
812
813 enum rtl_link_state {
814 MAC80211_NOLINK = 0,
815 MAC80211_LINKING = 1,
816 MAC80211_LINKED = 2,
817 MAC80211_LINKED_SCANNING = 3,
818 };
819
820 enum act_category {
821 ACT_CAT_QOS = 1,
822 ACT_CAT_DLS = 2,
823 ACT_CAT_BA = 3,
824 ACT_CAT_HT = 7,
825 ACT_CAT_WMM = 17,
826 };
827
828 enum ba_action {
829 ACT_ADDBAREQ = 0,
830 ACT_ADDBARSP = 1,
831 ACT_DELBA = 2,
832 };
833
834 enum rt_polarity_ctl {
835 RT_POLARITY_LOW_ACT = 0,
836 RT_POLARITY_HIGH_ACT = 1,
837 };
838
839 enum wolpattern_type {
840 UNICAST_PATTERN = 0,
841 MULTICAST_PATTERN = 1,
842 BROADCAST_PATTERN = 2,
843 DONT_CARE_DA = 3,
844 UNKNOWN_TYPE = 4,
845 };
846
847 struct octet_string {
848 u8 *octet;
849 u16 length;
850 };
851
852 struct rtl_hdr_3addr {
853 __le16 frame_ctl;
854 __le16 duration_id;
855 u8 addr1[ETH_ALEN];
856 u8 addr2[ETH_ALEN];
857 u8 addr3[ETH_ALEN];
858 __le16 seq_ctl;
859 u8 payload[0];
860 } __packed;
861
862 struct rtl_info_element {
863 u8 id;
864 u8 len;
865 u8 data[0];
866 } __packed;
867
868 struct rtl_probe_rsp {
869 struct rtl_hdr_3addr header;
870 u32 time_stamp[2];
871 __le16 beacon_interval;
872 __le16 capability;
873 /*SSID, supported rates, FH params, DS params,
874 CF params, IBSS params, TIM (if beacon), RSN */
875 struct rtl_info_element info_element[0];
876 } __packed;
877
878 /*LED related.*/
879 /*ledpin Identify how to implement this SW led.*/
880 struct rtl_led {
881 void *hw;
882 enum rtl_led_pin ledpin;
883 bool ledon;
884 };
885
886 struct rtl_led_ctl {
887 bool led_opendrain;
888 struct rtl_led sw_led0;
889 struct rtl_led sw_led1;
890 };
891
892 struct rtl_qos_parameters {
893 __le16 cw_min;
894 __le16 cw_max;
895 u8 aifs;
896 u8 flag;
897 __le16 tx_op;
898 } __packed;
899
900 struct rt_smooth_data {
901 u32 elements[100]; /*array to store values */
902 u32 index; /*index to current array to store */
903 u32 total_num; /*num of valid elements */
904 u32 total_val; /*sum of valid elements */
905 };
906
907 struct false_alarm_statistics {
908 u32 cnt_parity_fail;
909 u32 cnt_rate_illegal;
910 u32 cnt_crc8_fail;
911 u32 cnt_mcs_fail;
912 u32 cnt_fast_fsync_fail;
913 u32 cnt_sb_search_fail;
914 u32 cnt_ofdm_fail;
915 u32 cnt_cck_fail;
916 u32 cnt_all;
917 u32 cnt_ofdm_cca;
918 u32 cnt_cck_cca;
919 u32 cnt_cca_all;
920 u32 cnt_bw_usc;
921 u32 cnt_bw_lsc;
922 };
923
924 struct init_gain {
925 u8 xaagccore1;
926 u8 xbagccore1;
927 u8 xcagccore1;
928 u8 xdagccore1;
929 u8 cca;
930
931 };
932
933 struct wireless_stats {
934 unsigned long txbytesunicast;
935 unsigned long txbytesmulticast;
936 unsigned long txbytesbroadcast;
937 unsigned long rxbytesunicast;
938
939 long rx_snr_db[4];
940 /*Correct smoothed ss in Dbm, only used
941 in driver to report real power now. */
942 long recv_signal_power;
943 long signal_quality;
944 long last_sigstrength_inpercent;
945
946 u32 rssi_calculate_cnt;
947
948 /*Transformed, in dbm. Beautified signal
949 strength for UI, not correct. */
950 long signal_strength;
951
952 u8 rx_rssi_percentage[4];
953 u8 rx_evm_dbm[4];
954 u8 rx_evm_percentage[2];
955
956 u16 rx_cfo_short[4];
957 u16 rx_cfo_tail[4];
958
959 struct rt_smooth_data ui_rssi;
960 struct rt_smooth_data ui_link_quality;
961 };
962
963 struct rate_adaptive {
964 u8 rate_adaptive_disabled;
965 u8 ratr_state;
966 u16 reserve;
967
968 u32 high_rssi_thresh_for_ra;
969 u32 high2low_rssi_thresh_for_ra;
970 u8 low2high_rssi_thresh_for_ra40m;
971 u32 low_rssi_thresh_for_ra40m;
972 u8 low2high_rssi_thresh_for_ra20m;
973 u32 low_rssi_thresh_for_ra20m;
974 u32 upper_rssi_threshold_ratr;
975 u32 middleupper_rssi_threshold_ratr;
976 u32 middle_rssi_threshold_ratr;
977 u32 middlelow_rssi_threshold_ratr;
978 u32 low_rssi_threshold_ratr;
979 u32 ultralow_rssi_threshold_ratr;
980 u32 low_rssi_threshold_ratr_40m;
981 u32 low_rssi_threshold_ratr_20m;
982 u8 ping_rssi_enable;
983 u32 ping_rssi_ratr;
984 u32 ping_rssi_thresh_for_ra;
985 u32 last_ratr;
986 u8 pre_ratr_state;
987 u8 ldpc_thres;
988 bool use_ldpc;
989 bool lower_rts_rate;
990 bool is_special_data;
991 };
992
993 struct regd_pair_mapping {
994 u16 reg_dmnenum;
995 u16 reg_5ghz_ctl;
996 u16 reg_2ghz_ctl;
997 };
998
999 struct dynamic_primary_cca {
1000 u8 pricca_flag;
1001 u8 intf_flag;
1002 u8 intf_type;
1003 u8 dup_rts_flag;
1004 u8 monitor_flag;
1005 u8 ch_offset;
1006 u8 mf_state;
1007 };
1008
1009 struct rtl_regulatory {
1010 char alpha2[2];
1011 u16 country_code;
1012 u16 max_power_level;
1013 u32 tp_scale;
1014 u16 current_rd;
1015 u16 current_rd_ext;
1016 int16_t power_limit;
1017 struct regd_pair_mapping *regpair;
1018 };
1019
1020 struct rtl_rfkill {
1021 bool rfkill_state; /*0 is off, 1 is on */
1022 };
1023
1024 /*for P2P PS**/
1025 #define P2P_MAX_NOA_NUM 2
1026
1027 enum p2p_role {
1028 P2P_ROLE_DISABLE = 0,
1029 P2P_ROLE_DEVICE = 1,
1030 P2P_ROLE_CLIENT = 2,
1031 P2P_ROLE_GO = 3
1032 };
1033
1034 enum p2p_ps_state {
1035 P2P_PS_DISABLE = 0,
1036 P2P_PS_ENABLE = 1,
1037 P2P_PS_SCAN = 2,
1038 P2P_PS_SCAN_DONE = 3,
1039 P2P_PS_ALLSTASLEEP = 4, /* for P2P GO */
1040 };
1041
1042 enum p2p_ps_mode {
1043 P2P_PS_NONE = 0,
1044 P2P_PS_CTWINDOW = 1,
1045 P2P_PS_NOA = 2,
1046 P2P_PS_MIX = 3, /* CTWindow and NoA */
1047 };
1048
1049 struct rtl_p2p_ps_info {
1050 enum p2p_ps_mode p2p_ps_mode; /* indicate p2p ps mode */
1051 enum p2p_ps_state p2p_ps_state; /* indicate p2p ps state */
1052 u8 noa_index; /* Identifies instance of Notice of Absence timing. */
1053 /* Client traffic window. A period of time in TU after TBTT. */
1054 u8 ctwindow;
1055 u8 opp_ps; /* opportunistic power save. */
1056 u8 noa_num; /* number of NoA descriptor in P2P IE. */
1057 /* Count for owner, Type of client. */
1058 u8 noa_count_type[P2P_MAX_NOA_NUM];
1059 /* Max duration for owner, preferred or min acceptable duration
1060 * for client.
1061 */
1062 u32 noa_duration[P2P_MAX_NOA_NUM];
1063 /* Length of interval for owner, preferred or max acceptable intervali
1064 * of client.
1065 */
1066 u32 noa_interval[P2P_MAX_NOA_NUM];
1067 /* schedule in terms of the lower 4 bytes of the TSF timer. */
1068 u32 noa_start_time[P2P_MAX_NOA_NUM];
1069 };
1070
1071 struct p2p_ps_offload_t {
1072 u8 offload_en:1;
1073 u8 role:1; /* 1: Owner, 0: Client */
1074 u8 ctwindow_en:1;
1075 u8 noa0_en:1;
1076 u8 noa1_en:1;
1077 u8 allstasleep:1;
1078 u8 discovery:1;
1079 u8 reserved:1;
1080 };
1081
1082 #define IQK_MATRIX_REG_NUM 8
1083 #define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21)
1084
1085 struct iqk_matrix_regs {
1086 bool iqk_done;
1087 long value[1][IQK_MATRIX_REG_NUM];
1088 };
1089
1090 struct phy_parameters {
1091 u16 length;
1092 u32 *pdata;
1093 };
1094
1095 enum hw_param_tab_index {
1096 PHY_REG_2T,
1097 PHY_REG_1T,
1098 PHY_REG_PG,
1099 RADIOA_2T,
1100 RADIOB_2T,
1101 RADIOA_1T,
1102 RADIOB_1T,
1103 MAC_REG,
1104 AGCTAB_2T,
1105 AGCTAB_1T,
1106 MAX_TAB
1107 };
1108
1109 struct rtl_phy {
1110 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */
1111 struct init_gain initgain_backup;
1112 enum io_type current_io_type;
1113
1114 u8 rf_mode;
1115 u8 rf_type;
1116 u8 current_chan_bw;
1117 u8 set_bwmode_inprogress;
1118 u8 sw_chnl_inprogress;
1119 u8 sw_chnl_stage;
1120 u8 sw_chnl_step;
1121 u8 current_channel;
1122 u8 h2c_box_num;
1123 u8 set_io_inprogress;
1124 u8 lck_inprogress;
1125
1126 /* record for power tracking */
1127 s32 reg_e94;
1128 s32 reg_e9c;
1129 s32 reg_ea4;
1130 s32 reg_eac;
1131 s32 reg_eb4;
1132 s32 reg_ebc;
1133 s32 reg_ec4;
1134 s32 reg_ecc;
1135 u8 rfpienable;
1136 u8 reserve_0;
1137 u16 reserve_1;
1138 u32 reg_c04, reg_c08, reg_874;
1139 u32 adda_backup[16];
1140 u32 iqk_mac_backup[IQK_MAC_REG_NUM];
1141 u32 iqk_bb_backup[10];
1142 bool iqk_initialized;
1143
1144 bool rfpath_rx_enable[MAX_RF_PATH];
1145 u8 reg_837;
1146 /* Dual mac */
1147 bool need_iqk;
1148 struct iqk_matrix_regs iqk_matrix[IQK_MATRIX_SETTINGS_NUM];
1149
1150 bool rfpi_enable;
1151 bool iqk_in_progress;
1152
1153 u8 pwrgroup_cnt;
1154 u8 cck_high_power;
1155 /* MAX_PG_GROUP groups of pwr diff by rates */
1156 u32 mcs_offset[MAX_PG_GROUP][16];
1157 u32 tx_power_by_rate_offset[TX_PWR_BY_RATE_NUM_BAND]
1158 [TX_PWR_BY_RATE_NUM_RF]
1159 [TX_PWR_BY_RATE_NUM_RF]
1160 [TX_PWR_BY_RATE_NUM_SECTION];
1161 u8 txpwr_by_rate_base_24g[TX_PWR_BY_RATE_NUM_RF]
1162 [TX_PWR_BY_RATE_NUM_RF]
1163 [MAX_BASE_NUM_IN_PHY_REG_PG_24G];
1164 u8 txpwr_by_rate_base_5g[TX_PWR_BY_RATE_NUM_RF]
1165 [TX_PWR_BY_RATE_NUM_RF]
1166 [MAX_BASE_NUM_IN_PHY_REG_PG_5G];
1167 u8 default_initialgain[4];
1168
1169 /* the current Tx power level */
1170 u8 cur_cck_txpwridx;
1171 u8 cur_ofdm24g_txpwridx;
1172 u8 cur_bw20_txpwridx;
1173 u8 cur_bw40_txpwridx;
1174
1175 u32 rfreg_chnlval[2];
1176 bool apk_done;
1177 u32 reg_rf3c[2]; /* pathA / pathB */
1178
1179 u32 backup_rf_0x1a;/*92ee*/
1180 /* bfsync */
1181 u8 framesync;
1182 u32 framesync_c34;
1183
1184 u8 num_total_rfpath;
1185 struct phy_parameters hwparam_tables[MAX_TAB];
1186 u16 rf_pathmap;
1187
1188 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
1189 enum rt_polarity_ctl polarity_ctl;
1190 };
1191
1192 #define MAX_TID_COUNT 9
1193 #define RTL_AGG_STOP 0
1194 #define RTL_AGG_PROGRESS 1
1195 #define RTL_AGG_START 2
1196 #define RTL_AGG_OPERATIONAL 3
1197 #define RTL_AGG_OFF 0
1198 #define RTL_AGG_ON 1
1199 #define RTL_RX_AGG_START 1
1200 #define RTL_RX_AGG_STOP 0
1201 #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2
1202 #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3
1203
1204 struct rtl_ht_agg {
1205 u16 txq_id;
1206 u16 wait_for_ba;
1207 u16 start_idx;
1208 u64 bitmap;
1209 u32 rate_n_flags;
1210 u8 agg_state;
1211 u8 rx_agg_state;
1212 };
1213
1214 struct rssi_sta {
1215 long undec_sm_pwdb;
1216 long undec_sm_cck;
1217 };
1218
1219 struct rtl_tid_data {
1220 u16 seq_number;
1221 struct rtl_ht_agg agg;
1222 };
1223
1224 struct rtl_sta_info {
1225 struct list_head list;
1226 u8 ratr_index;
1227 u8 wireless_mode;
1228 u8 mimo_ps;
1229 u8 mac_addr[ETH_ALEN];
1230 struct rtl_tid_data tids[MAX_TID_COUNT];
1231
1232 /* just used for ap adhoc or mesh*/
1233 struct rssi_sta rssi_stat;
1234 } __packed;
1235
1236 struct rtl_priv;
1237 struct rtl_io {
1238 struct device *dev;
1239 struct mutex bb_mutex;
1240
1241 /*PCI MEM map */
1242 unsigned long pci_mem_end; /*shared mem end */
1243 unsigned long pci_mem_start; /*shared mem start */
1244
1245 /*PCI IO map */
1246 unsigned long pci_base_addr; /*device I/O address */
1247
1248 void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val);
1249 void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val);
1250 void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val);
1251 void (*writeN_sync) (struct rtl_priv *rtlpriv, u32 addr, void *buf,
1252 u16 len);
1253
1254 u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr);
1255 u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr);
1256 u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr);
1257
1258 };
1259
1260 struct rtl_mac {
1261 u8 mac_addr[ETH_ALEN];
1262 u8 mac80211_registered;
1263 u8 beacon_enabled;
1264
1265 u32 tx_ss_num;
1266 u32 rx_ss_num;
1267
1268 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
1269 struct ieee80211_hw *hw;
1270 struct ieee80211_vif *vif;
1271 enum nl80211_iftype opmode;
1272
1273 /*Probe Beacon management */
1274 struct rtl_tid_data tids[MAX_TID_COUNT];
1275 enum rtl_link_state link_state;
1276
1277 int n_channels;
1278 int n_bitrates;
1279
1280 bool offchan_delay;
1281 u8 p2p; /*using p2p role*/
1282 bool p2p_in_use;
1283
1284 /*filters */
1285 u32 rx_conf;
1286 u16 rx_mgt_filter;
1287 u16 rx_ctrl_filter;
1288 u16 rx_data_filter;
1289
1290 bool act_scanning;
1291 u8 cnt_after_linked;
1292 bool skip_scan;
1293
1294 /* early mode */
1295 /* skb wait queue */
1296 struct sk_buff_head skb_waitq[MAX_TID_COUNT];
1297
1298 u8 ht_stbc_cap;
1299 u8 ht_cur_stbc;
1300
1301 /*vht support*/
1302 u8 vht_enable;
1303 u8 bw_80;
1304 u8 vht_cur_ldpc;
1305 u8 vht_cur_stbc;
1306 u8 vht_stbc_cap;
1307 u8 vht_ldpc_cap;
1308
1309 /*RDG*/
1310 bool rdg_en;
1311
1312 /*AP*/
1313 u8 bssid[6];
1314 u32 vendor;
1315 u8 mcs[16]; /* 16 bytes mcs for HT rates. */
1316 u32 basic_rates; /* b/g rates */
1317 u8 ht_enable;
1318 u8 sgi_40;
1319 u8 sgi_20;
1320 u8 bw_40;
1321 u16 mode; /* wireless mode */
1322 u8 slot_time;
1323 u8 short_preamble;
1324 u8 use_cts_protect;
1325 u8 cur_40_prime_sc;
1326 u8 cur_40_prime_sc_bk;
1327 u8 cur_80_prime_sc;
1328 u64 tsf;
1329 u8 retry_short;
1330 u8 retry_long;
1331 u16 assoc_id;
1332 bool hiddenssid;
1333
1334 /*IBSS*/
1335 int beacon_interval;
1336
1337 /*AMPDU*/
1338 u8 min_space_cfg; /*For Min spacing configurations */
1339 u8 max_mss_density;
1340 u8 current_ampdu_factor;
1341 u8 current_ampdu_density;
1342
1343 /*QOS & EDCA */
1344 struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
1345 struct rtl_qos_parameters ac[AC_MAX];
1346
1347 /* counters */
1348 u64 last_txok_cnt;
1349 u64 last_rxok_cnt;
1350 u32 last_bt_edca_ul;
1351 u32 last_bt_edca_dl;
1352 };
1353
1354 struct btdm_8723 {
1355 bool all_off;
1356 bool agc_table_en;
1357 bool adc_back_off_on;
1358 bool b2_ant_hid_en;
1359 bool low_penalty_rate_adaptive;
1360 bool rf_rx_lpf_shrink;
1361 bool reject_aggre_pkt;
1362 bool tra_tdma_on;
1363 u8 tra_tdma_nav;
1364 u8 tra_tdma_ant;
1365 bool tdma_on;
1366 u8 tdma_ant;
1367 u8 tdma_nav;
1368 u8 tdma_dac_swing;
1369 u8 fw_dac_swing_lvl;
1370 bool ps_tdma_on;
1371 u8 ps_tdma_byte[5];
1372 bool pta_on;
1373 u32 val_0x6c0;
1374 u32 val_0x6c8;
1375 u32 val_0x6cc;
1376 bool sw_dac_swing_on;
1377 u32 sw_dac_swing_lvl;
1378 u32 wlan_act_hi;
1379 u32 wlan_act_lo;
1380 u32 bt_retry_index;
1381 bool dec_bt_pwr;
1382 bool ignore_wlan_act;
1383 };
1384
1385 struct bt_coexist_8723 {
1386 u32 high_priority_tx;
1387 u32 high_priority_rx;
1388 u32 low_priority_tx;
1389 u32 low_priority_rx;
1390 u8 c2h_bt_info;
1391 bool c2h_bt_info_req_sent;
1392 bool c2h_bt_inquiry_page;
1393 u32 bt_inq_page_start_time;
1394 u8 bt_retry_cnt;
1395 u8 c2h_bt_info_original;
1396 u8 bt_inquiry_page_cnt;
1397 struct btdm_8723 btdm;
1398 };
1399
1400 struct rtl_hal {
1401 struct ieee80211_hw *hw;
1402 bool driver_is_goingto_unload;
1403 bool up_first_time;
1404 bool first_init;
1405 bool being_init_adapter;
1406 bool bbrf_ready;
1407 bool mac_func_enable;
1408 bool pre_edcca_enable;
1409 struct bt_coexist_8723 hal_coex_8723;
1410
1411 enum intf_type interface;
1412 u16 hw_type; /*92c or 92d or 92s and so on */
1413 u8 ic_class;
1414 u8 oem_id;
1415 u32 version; /*version of chip */
1416 u8 state; /*stop 0, start 1 */
1417 u8 board_type;
1418
1419 /*firmware */
1420 u32 fwsize;
1421 u8 *pfirmware;
1422 u16 fw_version;
1423 u16 fw_subversion;
1424 bool h2c_setinprogress;
1425 u8 last_hmeboxnum;
1426 bool fw_ready;
1427 /*Reserve page start offset except beacon in TxQ. */
1428 u8 fw_rsvdpage_startoffset;
1429 u8 h2c_txcmd_seq;
1430 u8 current_ra_rate;
1431
1432 /* FW Cmd IO related */
1433 u16 fwcmd_iomap;
1434 u32 fwcmd_ioparam;
1435 bool set_fwcmd_inprogress;
1436 u8 current_fwcmd_io;
1437
1438 struct p2p_ps_offload_t p2p_ps_offload;
1439 bool fw_clk_change_in_progress;
1440 bool allow_sw_to_change_hwclc;
1441 u8 fw_ps_state;
1442 /**/
1443 bool driver_going2unload;
1444
1445 /*AMPDU init min space*/
1446 u8 minspace_cfg; /*For Min spacing configurations */
1447
1448 /* Dual mac */
1449 enum macphy_mode macphymode;
1450 enum band_type current_bandtype; /* 0:2.4G, 1:5G */
1451 enum band_type current_bandtypebackup;
1452 enum band_type bandset;
1453 /* dual MAC 0--Mac0 1--Mac1 */
1454 u32 interfaceindex;
1455 /* just for DualMac S3S4 */
1456 u8 macphyctl_reg;
1457 bool earlymode_enable;
1458 u8 max_earlymode_num;
1459 /* Dual mac*/
1460 bool during_mac0init_radiob;
1461 bool during_mac1init_radioa;
1462 bool reloadtxpowerindex;
1463 /* True if IMR or IQK have done
1464 for 2.4G in scan progress */
1465 bool load_imrandiqk_setting_for2g;
1466
1467 bool disable_amsdu_8k;
1468 bool master_of_dmsp;
1469 bool slave_of_dmsp;
1470
1471 u16 rx_tag;/*for 92ee*/
1472 u8 rts_en;
1473
1474 /*for wowlan*/
1475 bool wow_enable;
1476 bool enter_pnp_sleep;
1477 bool wake_from_pnp_sleep;
1478 bool wow_enabled;
1479 __kernel_time_t last_suspend_sec;
1480 u32 wowlan_fwsize;
1481 u8 *wowlan_firmware;
1482
1483 u8 hw_rof_enable; /*Enable GPIO[9] as WL RF HW PDn source*/
1484
1485 bool real_wow_v2_enable;
1486 bool re_init_llt_table;
1487 };
1488
1489 struct rtl_security {
1490 /*default 0 */
1491 bool use_sw_sec;
1492
1493 bool being_setkey;
1494 bool use_defaultkey;
1495 /*Encryption Algorithm for Unicast Packet */
1496 enum rt_enc_alg pairwise_enc_algorithm;
1497 /*Encryption Algorithm for Brocast/Multicast */
1498 enum rt_enc_alg group_enc_algorithm;
1499 /*Cam Entry Bitmap */
1500 u32 hwsec_cam_bitmap;
1501 u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN];
1502 /*local Key buffer, indx 0 is for
1503 pairwise key 1-4 is for agoup key. */
1504 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
1505 u8 key_len[KEY_BUF_SIZE];
1506
1507 /*The pointer of Pairwise Key,
1508 it always points to KeyBuf[4] */
1509 u8 *pairwise_key;
1510 };
1511
1512 #define ASSOCIATE_ENTRY_NUM 33
1513
1514 struct fast_ant_training {
1515 u8 bssid[6];
1516 u8 antsel_rx_keep_0;
1517 u8 antsel_rx_keep_1;
1518 u8 antsel_rx_keep_2;
1519 u32 ant_sum[7];
1520 u32 ant_cnt[7];
1521 u32 ant_ave[7];
1522 u8 fat_state;
1523 u32 train_idx;
1524 u8 antsel_a[ASSOCIATE_ENTRY_NUM];
1525 u8 antsel_b[ASSOCIATE_ENTRY_NUM];
1526 u8 antsel_c[ASSOCIATE_ENTRY_NUM];
1527 u32 main_ant_sum[ASSOCIATE_ENTRY_NUM];
1528 u32 aux_ant_sum[ASSOCIATE_ENTRY_NUM];
1529 u32 main_ant_cnt[ASSOCIATE_ENTRY_NUM];
1530 u32 aux_ant_cnt[ASSOCIATE_ENTRY_NUM];
1531 u8 rx_idle_ant;
1532 bool becomelinked;
1533 };
1534
1535 struct dm_phy_dbg_info {
1536 char rx_snrdb[4];
1537 u64 num_qry_phy_status;
1538 u64 num_qry_phy_status_cck;
1539 u64 num_qry_phy_status_ofdm;
1540 u16 num_qry_beacon_pkt;
1541 u16 num_non_be_pkt;
1542 s32 rx_evm[4];
1543 };
1544
1545 struct rtl_dm {
1546 /*PHY status for Dynamic Management */
1547 long entry_min_undec_sm_pwdb;
1548 long undec_sm_cck;
1549 long undec_sm_pwdb; /*out dm */
1550 long entry_max_undec_sm_pwdb;
1551 s32 ofdm_pkt_cnt;
1552 bool dm_initialgain_enable;
1553 bool dynamic_txpower_enable;
1554 bool current_turbo_edca;
1555 bool is_any_nonbepkts; /*out dm */
1556 bool is_cur_rdlstate;
1557 bool txpower_trackinginit;
1558 bool disable_framebursting;
1559 bool cck_inch14;
1560 bool txpower_tracking;
1561 bool useramask;
1562 bool rfpath_rxenable[4];
1563 bool inform_fw_driverctrldm;
1564 bool current_mrc_switch;
1565 u8 txpowercount;
1566 u8 powerindex_backup[6];
1567
1568 u8 thermalvalue_rxgain;
1569 u8 thermalvalue_iqk;
1570 u8 thermalvalue_lck;
1571 u8 thermalvalue;
1572 u8 last_dtp_lvl;
1573 u8 thermalvalue_avg[AVG_THERMAL_NUM];
1574 u8 thermalvalue_avg_index;
1575 bool done_txpower;
1576 u8 dynamic_txhighpower_lvl; /*Tx high power level */
1577 u8 dm_flag; /*Indicate each dynamic mechanism's status. */
1578 u8 dm_flag_tmp;
1579 u8 dm_type;
1580 u8 dm_rssi_sel;
1581 u8 txpower_track_control;
1582 bool interrupt_migration;
1583 bool disable_tx_int;
1584 char ofdm_index[MAX_RF_PATH];
1585 u8 default_ofdm_index;
1586 u8 default_cck_index;
1587 char cck_index;
1588 char delta_power_index[MAX_RF_PATH];
1589 char delta_power_index_last[MAX_RF_PATH];
1590 char power_index_offset[MAX_RF_PATH];
1591 char absolute_ofdm_swing_idx[MAX_RF_PATH];
1592 char remnant_ofdm_swing_idx[MAX_RF_PATH];
1593 char remnant_cck_idx;
1594 bool modify_txagc_flag_path_a;
1595 bool modify_txagc_flag_path_b;
1596
1597 bool one_entry_only;
1598 struct dm_phy_dbg_info dbginfo;
1599
1600 /* Dynamic ATC switch */
1601 bool atc_status;
1602 bool large_cfo_hit;
1603 bool is_freeze;
1604 int cfo_tail[2];
1605 int cfo_ave_pre;
1606 int crystal_cap;
1607 u8 cfo_threshold;
1608 u32 packet_count;
1609 u32 packet_count_pre;
1610 u8 tx_rate;
1611
1612 /*88e tx power tracking*/
1613 u8 swing_idx_ofdm[MAX_RF_PATH];
1614 u8 swing_idx_ofdm_cur;
1615 u8 swing_idx_ofdm_base[MAX_RF_PATH];
1616 bool swing_flag_ofdm;
1617 u8 swing_idx_cck;
1618 u8 swing_idx_cck_cur;
1619 u8 swing_idx_cck_base;
1620 bool swing_flag_cck;
1621
1622 char swing_diff_2g;
1623 char swing_diff_5g;
1624
1625 u8 delta_swing_table_idx_24gccka_p[DEL_SW_IDX_SZ];
1626 u8 delta_swing_table_idx_24gccka_n[DEL_SW_IDX_SZ];
1627 u8 delta_swing_table_idx_24gcckb_p[DEL_SW_IDX_SZ];
1628 u8 delta_swing_table_idx_24gcckb_n[DEL_SW_IDX_SZ];
1629 u8 delta_swing_table_idx_24ga_p[DEL_SW_IDX_SZ];
1630 u8 delta_swing_table_idx_24ga_n[DEL_SW_IDX_SZ];
1631 u8 delta_swing_table_idx_24gb_p[DEL_SW_IDX_SZ];
1632 u8 delta_swing_table_idx_24gb_n[DEL_SW_IDX_SZ];
1633 u8 delta_swing_table_idx_5ga_p[BAND_NUM][DEL_SW_IDX_SZ];
1634 u8 delta_swing_table_idx_5ga_n[BAND_NUM][DEL_SW_IDX_SZ];
1635 u8 delta_swing_table_idx_5gb_p[BAND_NUM][DEL_SW_IDX_SZ];
1636 u8 delta_swing_table_idx_5gb_n[BAND_NUM][DEL_SW_IDX_SZ];
1637 u8 delta_swing_table_idx_24ga_p_8188e[DEL_SW_IDX_SZ];
1638 u8 delta_swing_table_idx_24ga_n_8188e[DEL_SW_IDX_SZ];
1639
1640 /* DMSP */
1641 bool supp_phymode_switch;
1642
1643 /* DulMac */
1644 struct fast_ant_training fat_table;
1645
1646 u8 resp_tx_path;
1647 u8 path_sel;
1648 u32 patha_sum;
1649 u32 pathb_sum;
1650 u32 patha_cnt;
1651 u32 pathb_cnt;
1652
1653 u8 pre_channel;
1654 u8 *p_channel;
1655 u8 linked_interval;
1656
1657 u64 last_tx_ok_cnt;
1658 u64 last_rx_ok_cnt;
1659 };
1660
1661 #define EFUSE_MAX_LOGICAL_SIZE 512
1662
1663 struct rtl_efuse {
1664 bool autoLoad_ok;
1665 bool bootfromefuse;
1666 u16 max_physical_size;
1667
1668 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
1669 u16 efuse_usedbytes;
1670 u8 efuse_usedpercentage;
1671 #ifdef EFUSE_REPG_WORKAROUND
1672 bool efuse_re_pg_sec1flag;
1673 u8 efuse_re_pg_data[8];
1674 #endif
1675
1676 u8 autoload_failflag;
1677 u8 autoload_status;
1678
1679 short epromtype;
1680 u16 eeprom_vid;
1681 u16 eeprom_did;
1682 u16 eeprom_svid;
1683 u16 eeprom_smid;
1684 u8 eeprom_oemid;
1685 u16 eeprom_channelplan;
1686 u8 eeprom_version;
1687 u8 board_type;
1688 u8 external_pa;
1689
1690 u8 dev_addr[6];
1691 u8 wowlan_enable;
1692 u8 antenna_div_cfg;
1693 u8 antenna_div_type;
1694
1695 bool txpwr_fromeprom;
1696 u8 eeprom_crystalcap;
1697 u8 eeprom_tssi[2];
1698 u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
1699 u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
1700 u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
1701 u8 eeprom_chnlarea_txpwr_cck[MAX_RF_PATH][CHANNEL_GROUP_MAX_2G];
1702 u8 eeprom_chnlarea_txpwr_ht40_1s[MAX_RF_PATH][CHANNEL_GROUP_MAX];
1703 u8 eprom_chnl_txpwr_ht40_2sdf[MAX_RF_PATH][CHANNEL_GROUP_MAX];
1704
1705 u8 internal_pa_5g[2]; /* pathA / pathB */
1706 u8 eeprom_c9;
1707 u8 eeprom_cc;
1708
1709 /*For power group */
1710 u8 eeprom_pwrgroup[2][3];
1711 u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
1712 u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
1713
1714 u8 txpwrlevel_cck[MAX_RF_PATH][CHANNEL_MAX_NUMBER_2G];
1715 /*For HT 40MHZ pwr */
1716 u8 txpwrlevel_ht40_1s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1717 /*For HT 40MHZ pwr */
1718 u8 txpwrlevel_ht40_2s[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1719
1720 /*--------------------------------------------------------*
1721 * 8192CE\8192SE\8192DE\8723AE use the following 4 arrays,
1722 * other ICs (8188EE\8723BE\8192EE\8812AE...)
1723 * define new arrays in Windows code.
1724 * BUT, in linux code, we use the same array for all ICs.
1725 *
1726 * The Correspondance relation between two arrays is:
1727 * txpwr_cckdiff[][] == CCK_24G_Diff[][]
1728 * txpwr_ht20diff[][] == BW20_24G_Diff[][]
1729 * txpwr_ht40diff[][] == BW40_24G_Diff[][]
1730 * txpwr_legacyhtdiff[][] == OFDM_24G_Diff[][]
1731 *
1732 * Sizes of these arrays are decided by the larger ones.
1733 */
1734 char txpwr_cckdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1735 char txpwr_ht20diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1736 char txpwr_ht40diff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1737 char txpwr_legacyhtdiff[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1738
1739 u8 txpwr_5g_bw40base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
1740 u8 txpwr_5g_bw80base[MAX_RF_PATH][CHANNEL_MAX_NUMBER_5G_80M];
1741 char txpwr_5g_ofdmdiff[MAX_RF_PATH][MAX_TX_COUNT];
1742 char txpwr_5g_bw20diff[MAX_RF_PATH][MAX_TX_COUNT];
1743 char txpwr_5g_bw40diff[MAX_RF_PATH][MAX_TX_COUNT];
1744 char txpwr_5g_bw80diff[MAX_RF_PATH][MAX_TX_COUNT];
1745
1746 u8 txpwr_safetyflag; /* Band edge enable flag */
1747 u16 eeprom_txpowerdiff;
1748 u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */
1749 u8 antenna_txpwdiff[3];
1750
1751 u8 eeprom_regulatory;
1752 u8 eeprom_thermalmeter;
1753 u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
1754 u16 tssi_13dbm;
1755 u8 crystalcap; /* CrystalCap. */
1756 u8 delta_iqk;
1757 u8 delta_lck;
1758
1759 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */
1760 bool apk_thermalmeterignore;
1761
1762 bool b1x1_recvcombine;
1763 bool b1ss_support;
1764
1765 /*channel plan */
1766 u8 channel_plan;
1767 };
1768
1769 struct rtl_ps_ctl {
1770 bool pwrdomain_protect;
1771 bool in_powersavemode;
1772 bool rfchange_inprogress;
1773 bool swrf_processing;
1774 bool hwradiooff;
1775 /*
1776 * just for PCIE ASPM
1777 * If it supports ASPM, Offset[560h] = 0x40,
1778 * otherwise Offset[560h] = 0x00.
1779 * */
1780 bool support_aspm;
1781 bool support_backdoor;
1782
1783 /*for LPS */
1784 enum rt_psmode dot11_psmode; /*Power save mode configured. */
1785 bool swctrl_lps;
1786 bool leisure_ps;
1787 bool fwctrl_lps;
1788 u8 fwctrl_psmode;
1789 /*For Fw control LPS mode */
1790 u8 reg_fwctrl_lps;
1791 /*Record Fw PS mode status. */
1792 bool fw_current_inpsmode;
1793 u8 reg_max_lps_awakeintvl;
1794 bool report_linked;
1795 bool low_power_enable;/*for 32k*/
1796
1797 /*for IPS */
1798 bool inactiveps;
1799
1800 u32 rfoff_reason;
1801
1802 /*RF OFF Level */
1803 u32 cur_ps_level;
1804 u32 reg_rfps_level;
1805
1806 /*just for PCIE ASPM */
1807 u8 const_amdpci_aspm;
1808 bool pwrdown_mode;
1809
1810 enum rf_pwrstate inactive_pwrstate;
1811 enum rf_pwrstate rfpwr_state; /*cur power state */
1812
1813 /* for SW LPS*/
1814 bool sw_ps_enabled;
1815 bool state;
1816 bool state_inap;
1817 bool multi_buffered;
1818 u16 nullfunc_seq;
1819 unsigned int dtim_counter;
1820 unsigned int sleep_ms;
1821 unsigned long last_sleep_jiffies;
1822 unsigned long last_awake_jiffies;
1823 unsigned long last_delaylps_stamp_jiffies;
1824 unsigned long last_dtim;
1825 unsigned long last_beacon;
1826 unsigned long last_action;
1827 unsigned long last_slept;
1828
1829 /*For P2P PS */
1830 struct rtl_p2p_ps_info p2p_ps_info;
1831 u8 pwr_mode;
1832 u8 smart_ps;
1833
1834 /* wake up on line */
1835 u8 wo_wlan_mode;
1836 u8 arp_offload_enable;
1837 u8 gtk_offload_enable;
1838 /* Used for WOL, indicates the reason for waking event.*/
1839 u32 wakeup_reason;
1840 /* Record the last waking time for comparison with setting key. */
1841 u64 last_wakeup_time;
1842 };
1843
1844 struct rtl_stats {
1845 u8 psaddr[ETH_ALEN];
1846 u32 mac_time[2];
1847 s8 rssi;
1848 u8 signal;
1849 u8 noise;
1850 u8 rate; /* hw desc rate */
1851 u8 received_channel;
1852 u8 control;
1853 u8 mask;
1854 u8 freq;
1855 u16 len;
1856 u64 tsf;
1857 u32 beacon_time;
1858 u8 nic_type;
1859 u16 length;
1860 u8 signalquality; /*in 0-100 index. */
1861 /*
1862 * Real power in dBm for this packet,
1863 * no beautification and aggregation.
1864 * */
1865 s32 recvsignalpower;
1866 s8 rxpower; /*in dBm Translate from PWdB */
1867 u8 signalstrength; /*in 0-100 index. */
1868 u16 hwerror:1;
1869 u16 crc:1;
1870 u16 icv:1;
1871 u16 shortpreamble:1;
1872 u16 antenna:1;
1873 u16 decrypted:1;
1874 u16 wakeup:1;
1875 u32 timestamp_low;
1876 u32 timestamp_high;
1877
1878 u8 rx_drvinfo_size;
1879 u8 rx_bufshift;
1880 bool isampdu;
1881 bool isfirst_ampdu;
1882 bool rx_is40Mhzpacket;
1883 u32 rx_pwdb_all;
1884 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */
1885 s8 rx_mimo_sig_qual[4];
1886 u8 rx_pwr[4]; /* per-path's pwdb */
1887 u8 rx_snr[4]; /* per-path's SNR */
1888 bool packet_matchbssid;
1889 bool is_cck;
1890 bool is_ht;
1891 bool packet_toself;
1892 bool packet_beacon; /*for rssi */
1893 char cck_adc_pwdb[4]; /*for rx path selection */
1894
1895 u8 packet_report_type;
1896
1897 u32 macid;
1898 u8 wake_match;
1899 u32 bt_rx_rssi_percentage;
1900 u32 macid_valid_entry[2];
1901 };
1902
1903
1904 struct rt_link_detect {
1905 /* count for roaming */
1906 u32 bcn_rx_inperiod;
1907 u32 roam_times;
1908
1909 u32 num_tx_in4period[4];
1910 u32 num_rx_in4period[4];
1911
1912 u32 num_tx_inperiod;
1913 u32 num_rx_inperiod;
1914
1915 bool busytraffic;
1916 bool tx_busy_traffic;
1917 bool rx_busy_traffic;
1918 bool higher_busytraffic;
1919 bool higher_busyrxtraffic;
1920
1921 u32 tidtx_in4period[MAX_TID_COUNT][4];
1922 u32 tidtx_inperiod[MAX_TID_COUNT];
1923 bool higher_busytxtraffic[MAX_TID_COUNT];
1924 };
1925
1926 struct rtl_tcb_desc {
1927 u8 packet_bw:1;
1928 u8 multicast:1;
1929 u8 broadcast:1;
1930
1931 u8 rts_stbc:1;
1932 u8 rts_enable:1;
1933 u8 cts_enable:1;
1934 u8 rts_use_shortpreamble:1;
1935 u8 rts_use_shortgi:1;
1936 u8 rts_sc:1;
1937 u8 rts_bw:1;
1938 u8 rts_rate;
1939
1940 u8 use_shortgi:1;
1941 u8 use_shortpreamble:1;
1942 u8 use_driver_rate:1;
1943 u8 disable_ratefallback:1;
1944
1945 u8 ratr_index;
1946 u8 mac_id;
1947 u8 hw_rate;
1948
1949 u8 last_inipkt:1;
1950 u8 cmd_or_init:1;
1951 u8 queue_index;
1952
1953 /* early mode */
1954 u8 empkt_num;
1955 /* The max value by HW */
1956 u32 empkt_len[10];
1957 bool btx_enable_sw_calc_duration;
1958 };
1959
1960 struct rtl92c_firmware_header;
1961
1962 struct rtl_wow_pattern {
1963 u8 type;
1964 u16 crc;
1965 u32 mask[4];
1966 };
1967
1968 struct rtl_hal_ops {
1969 int (*init_sw_vars) (struct ieee80211_hw *hw);
1970 void (*deinit_sw_vars) (struct ieee80211_hw *hw);
1971 void (*read_chip_version)(struct ieee80211_hw *hw);
1972 void (*read_eeprom_info) (struct ieee80211_hw *hw);
1973 void (*interrupt_recognized) (struct ieee80211_hw *hw,
1974 u32 *p_inta, u32 *p_intb);
1975 int (*hw_init) (struct ieee80211_hw *hw);
1976 void (*hw_disable) (struct ieee80211_hw *hw);
1977 void (*hw_suspend) (struct ieee80211_hw *hw);
1978 void (*hw_resume) (struct ieee80211_hw *hw);
1979 void (*enable_interrupt) (struct ieee80211_hw *hw);
1980 void (*disable_interrupt) (struct ieee80211_hw *hw);
1981 int (*set_network_type) (struct ieee80211_hw *hw,
1982 enum nl80211_iftype type);
1983 void (*set_chk_bssid)(struct ieee80211_hw *hw,
1984 bool check_bssid);
1985 void (*set_bw_mode) (struct ieee80211_hw *hw,
1986 enum nl80211_channel_type ch_type);
1987 u8(*switch_channel) (struct ieee80211_hw *hw);
1988 void (*set_qos) (struct ieee80211_hw *hw, int aci);
1989 void (*set_bcn_reg) (struct ieee80211_hw *hw);
1990 void (*set_bcn_intv) (struct ieee80211_hw *hw);
1991 void (*update_interrupt_mask) (struct ieee80211_hw *hw,
1992 u32 add_msr, u32 rm_msr);
1993 void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1994 void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1995 void (*update_rate_tbl) (struct ieee80211_hw *hw,
1996 struct ieee80211_sta *sta, u8 rssi_level);
1997 void (*pre_fill_tx_bd_desc)(struct ieee80211_hw *hw, u8 *tx_bd_desc,
1998 u8 *desc, u8 queue_index,
1999 struct sk_buff *skb, dma_addr_t addr);
2000 void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level);
2001 u16 (*rx_desc_buff_remained_cnt)(struct ieee80211_hw *hw,
2002 u8 queue_index);
2003 void (*rx_check_dma_ok)(struct ieee80211_hw *hw, u8 *header_desc,
2004 u8 queue_index);
2005 void (*fill_tx_desc) (struct ieee80211_hw *hw,
2006 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
2007 u8 *pbd_desc_tx,
2008 struct ieee80211_tx_info *info,
2009 struct ieee80211_sta *sta,
2010 struct sk_buff *skb, u8 hw_queue,
2011 struct rtl_tcb_desc *ptcb_desc);
2012 void (*fill_fake_txdesc) (struct ieee80211_hw *hw, u8 *pDesc,
2013 u32 buffer_len, bool bIsPsPoll);
2014 void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc,
2015 bool firstseg, bool lastseg,
2016 struct sk_buff *skb);
2017 bool (*cmd_send_packet)(struct ieee80211_hw *hw, struct sk_buff *skb);
2018 bool (*query_rx_desc) (struct ieee80211_hw *hw,
2019 struct rtl_stats *stats,
2020 struct ieee80211_rx_status *rx_status,
2021 u8 *pdesc, struct sk_buff *skb);
2022 void (*set_channel_access) (struct ieee80211_hw *hw);
2023 bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid);
2024 void (*dm_watchdog) (struct ieee80211_hw *hw);
2025 void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation);
2026 bool (*set_rf_power_state) (struct ieee80211_hw *hw,
2027 enum rf_pwrstate rfpwr_state);
2028 void (*led_control) (struct ieee80211_hw *hw,
2029 enum led_ctl_mode ledaction);
2030 void (*set_desc)(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
2031 u8 desc_name, u8 *val);
2032 u32 (*get_desc) (u8 *pdesc, bool istx, u8 desc_name);
2033 bool (*is_tx_desc_closed) (struct ieee80211_hw *hw,
2034 u8 hw_queue, u16 index);
2035 void (*tx_polling) (struct ieee80211_hw *hw, u8 hw_queue);
2036 void (*enable_hw_sec) (struct ieee80211_hw *hw);
2037 void (*set_key) (struct ieee80211_hw *hw, u32 key_index,
2038 u8 *macaddr, bool is_group, u8 enc_algo,
2039 bool is_wepkey, bool clear_all);
2040 void (*init_sw_leds) (struct ieee80211_hw *hw);
2041 void (*deinit_sw_leds) (struct ieee80211_hw *hw);
2042 u32 (*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
2043 void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
2044 u32 data);
2045 u32 (*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
2046 u32 regaddr, u32 bitmask);
2047 void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
2048 u32 regaddr, u32 bitmask, u32 data);
2049 void (*linked_set_reg) (struct ieee80211_hw *hw);
2050 void (*chk_switch_dmdp) (struct ieee80211_hw *hw);
2051 void (*dualmac_easy_concurrent) (struct ieee80211_hw *hw);
2052 void (*dualmac_switch_to_dmdp) (struct ieee80211_hw *hw);
2053 bool (*phy_rf6052_config) (struct ieee80211_hw *hw);
2054 void (*phy_rf6052_set_cck_txpower) (struct ieee80211_hw *hw,
2055 u8 *powerlevel);
2056 void (*phy_rf6052_set_ofdm_txpower) (struct ieee80211_hw *hw,
2057 u8 *ppowerlevel, u8 channel);
2058 bool (*config_bb_with_headerfile) (struct ieee80211_hw *hw,
2059 u8 configtype);
2060 bool (*config_bb_with_pgheaderfile) (struct ieee80211_hw *hw,
2061 u8 configtype);
2062 void (*phy_lc_calibrate) (struct ieee80211_hw *hw, bool is2t);
2063 void (*phy_set_bw_mode_callback) (struct ieee80211_hw *hw);
2064 void (*dm_dynamic_txpower) (struct ieee80211_hw *hw);
2065 void (*c2h_command_handle) (struct ieee80211_hw *hw);
2066 void (*bt_wifi_media_status_notify) (struct ieee80211_hw *hw,
2067 bool mstate);
2068 void (*bt_coex_off_before_lps) (struct ieee80211_hw *hw);
2069 void (*fill_h2c_cmd) (struct ieee80211_hw *hw, u8 element_id,
2070 u32 cmd_len, u8 *p_cmdbuffer);
2071 bool (*get_btc_status) (void);
2072 bool (*is_fw_header) (struct rtl92c_firmware_header *hdr);
2073 u32 (*rx_command_packet)(struct ieee80211_hw *hw,
2074 struct rtl_stats status, struct sk_buff *skb);
2075 void (*add_wowlan_pattern)(struct ieee80211_hw *hw,
2076 struct rtl_wow_pattern *rtl_pattern,
2077 u8 index);
2078 };
2079
2080 struct rtl_intf_ops {
2081 /*com */
2082 void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
2083 int (*adapter_start) (struct ieee80211_hw *hw);
2084 void (*adapter_stop) (struct ieee80211_hw *hw);
2085 bool (*check_buddy_priv)(struct ieee80211_hw *hw,
2086 struct rtl_priv **buddy_priv);
2087
2088 int (*adapter_tx) (struct ieee80211_hw *hw,
2089 struct ieee80211_sta *sta,
2090 struct sk_buff *skb,
2091 struct rtl_tcb_desc *ptcb_desc);
2092 void (*flush)(struct ieee80211_hw *hw, u32 queues, bool drop);
2093 int (*reset_trx_ring) (struct ieee80211_hw *hw);
2094 bool (*waitq_insert) (struct ieee80211_hw *hw,
2095 struct ieee80211_sta *sta,
2096 struct sk_buff *skb);
2097
2098 /*pci */
2099 void (*disable_aspm) (struct ieee80211_hw *hw);
2100 void (*enable_aspm) (struct ieee80211_hw *hw);
2101
2102 /*usb */
2103 };
2104
2105 struct rtl_mod_params {
2106 /* default: 0 = using hardware encryption */
2107 bool sw_crypto;
2108
2109 /* default: 0 = DBG_EMERG (0)*/
2110 int debug;
2111
2112 /* default: 1 = using no linked power save */
2113 bool inactiveps;
2114
2115 /* default: 1 = using linked sw power save */
2116 bool swctrl_lps;
2117
2118 /* default: 1 = using linked fw power save */
2119 bool fwctrl_lps;
2120
2121 /* default: 0 = not using MSI interrupts mode */
2122 /* submodules should set their own defalut value */
2123 bool msi_support;
2124 };
2125
2126 struct rtl_hal_usbint_cfg {
2127 /* data - rx */
2128 u32 in_ep_num;
2129 u32 rx_urb_num;
2130 u32 rx_max_size;
2131
2132 /* op - rx */
2133 void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *);
2134 void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *,
2135 struct sk_buff_head *);
2136
2137 /* tx */
2138 void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *);
2139 int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *,
2140 struct sk_buff *);
2141 struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *,
2142 struct sk_buff_head *);
2143
2144 /* endpoint mapping */
2145 int (*usb_endpoint_mapping)(struct ieee80211_hw *hw);
2146 u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index);
2147 };
2148
2149 struct rtl_hal_cfg {
2150 u8 bar_id;
2151 bool write_readback;
2152 char *name;
2153 char *fw_name;
2154 char *alt_fw_name;
2155 struct rtl_hal_ops *ops;
2156 struct rtl_mod_params *mod_params;
2157 struct rtl_hal_usbint_cfg *usb_interface_cfg;
2158
2159 /*this map used for some registers or vars
2160 defined int HAL but used in MAIN */
2161 u32 maps[RTL_VAR_MAP_MAX];
2162
2163 };
2164
2165 struct rtl_locks {
2166 /* mutex */
2167 struct mutex conf_mutex;
2168 struct mutex ps_mutex;
2169
2170 /*spin lock */
2171 spinlock_t ips_lock;
2172 spinlock_t irq_th_lock;
2173 spinlock_t irq_pci_lock;
2174 spinlock_t tx_lock;
2175 spinlock_t h2c_lock;
2176 spinlock_t rf_ps_lock;
2177 spinlock_t rf_lock;
2178 spinlock_t lps_lock;
2179 spinlock_t waitq_lock;
2180 spinlock_t entry_list_lock;
2181 spinlock_t usb_lock;
2182
2183 /*FW clock change */
2184 spinlock_t fw_ps_lock;
2185
2186 /*Dual mac*/
2187 spinlock_t cck_and_rw_pagea_lock;
2188
2189 /*Easy concurrent*/
2190 spinlock_t check_sendpkt_lock;
2191
2192 spinlock_t iqk_lock;
2193 };
2194
2195 struct rtl_works {
2196 struct ieee80211_hw *hw;
2197
2198 /*timer */
2199 struct timer_list watchdog_timer;
2200 struct timer_list dualmac_easyconcurrent_retrytimer;
2201 struct timer_list fw_clockoff_timer;
2202 struct timer_list fast_antenna_training_timer;
2203 /*task */
2204 struct tasklet_struct irq_tasklet;
2205 struct tasklet_struct irq_prepare_bcn_tasklet;
2206
2207 /*work queue */
2208 struct workqueue_struct *rtl_wq;
2209 struct delayed_work watchdog_wq;
2210 struct delayed_work ips_nic_off_wq;
2211
2212 /* For SW LPS */
2213 struct delayed_work ps_work;
2214 struct delayed_work ps_rfon_wq;
2215 struct delayed_work fwevt_wq;
2216
2217 struct work_struct lps_change_work;
2218 struct work_struct fill_h2c_cmd;
2219 };
2220
2221 struct rtl_debug {
2222 u32 dbgp_type[DBGP_TYPE_MAX];
2223 int global_debuglevel;
2224 u64 global_debugcomponents;
2225
2226 /* add for proc debug */
2227 struct proc_dir_entry *proc_dir;
2228 char proc_name[20];
2229 };
2230
2231 #define MIMO_PS_STATIC 0
2232 #define MIMO_PS_DYNAMIC 1
2233 #define MIMO_PS_NOLIMIT 3
2234
2235 struct rtl_dualmac_easy_concurrent_ctl {
2236 enum band_type currentbandtype_backfordmdp;
2237 bool close_bbandrf_for_dmsp;
2238 bool change_to_dmdp;
2239 bool change_to_dmsp;
2240 bool switch_in_process;
2241 };
2242
2243 struct rtl_dmsp_ctl {
2244 bool activescan_for_slaveofdmsp;
2245 bool scan_for_anothermac_fordmsp;
2246 bool scan_for_itself_fordmsp;
2247 bool writedig_for_anothermacofdmsp;
2248 u32 curdigvalue_for_anothermacofdmsp;
2249 bool changecckpdstate_for_anothermacofdmsp;
2250 u8 curcckpdstate_for_anothermacofdmsp;
2251 bool changetxhighpowerlvl_for_anothermacofdmsp;
2252 u8 curtxhighlvl_for_anothermacofdmsp;
2253 long rssivalmin_for_anothermacofdmsp;
2254 };
2255
2256 struct ps_t {
2257 u8 pre_ccastate;
2258 u8 cur_ccasate;
2259 u8 pre_rfstate;
2260 u8 cur_rfstate;
2261 u8 initialize;
2262 long rssi_val_min;
2263 };
2264
2265 struct dig_t {
2266 u32 rssi_lowthresh;
2267 u32 rssi_highthresh;
2268 u32 fa_lowthresh;
2269 u32 fa_highthresh;
2270 long last_min_undec_pwdb_for_dm;
2271 long rssi_highpower_lowthresh;
2272 long rssi_highpower_highthresh;
2273 u32 recover_cnt;
2274 u32 pre_igvalue;
2275 u32 cur_igvalue;
2276 long rssi_val;
2277 u8 dig_enable_flag;
2278 u8 dig_ext_port_stage;
2279 u8 dig_algorithm;
2280 u8 dig_twoport_algorithm;
2281 u8 dig_dbgmode;
2282 u8 dig_slgorithm_switch;
2283 u8 cursta_cstate;
2284 u8 presta_cstate;
2285 u8 curmultista_cstate;
2286 u8 stop_dig;
2287 char back_val;
2288 char back_range_max;
2289 char back_range_min;
2290 u8 rx_gain_max;
2291 u8 rx_gain_min;
2292 u8 min_undec_pwdb_for_dm;
2293 u8 rssi_val_min;
2294 u8 pre_cck_cca_thres;
2295 u8 cur_cck_cca_thres;
2296 u8 pre_cck_pd_state;
2297 u8 cur_cck_pd_state;
2298 u8 pre_cck_fa_state;
2299 u8 cur_cck_fa_state;
2300 u8 pre_ccastate;
2301 u8 cur_ccasate;
2302 u8 large_fa_hit;
2303 u8 dig_dynamic_min;
2304 u8 dig_dynamic_min_1;
2305 u8 forbidden_igi;
2306 u8 dig_state;
2307 u8 dig_highpwrstate;
2308 u8 cur_sta_cstate;
2309 u8 pre_sta_cstate;
2310 u8 cur_ap_cstate;
2311 u8 pre_ap_cstate;
2312 u8 cur_pd_thstate;
2313 u8 pre_pd_thstate;
2314 u8 cur_cs_ratiostate;
2315 u8 pre_cs_ratiostate;
2316 u8 backoff_enable_flag;
2317 char backoffval_range_max;
2318 char backoffval_range_min;
2319 u8 dig_min_0;
2320 u8 dig_min_1;
2321 u8 bt30_cur_igi;
2322 bool media_connect_0;
2323 bool media_connect_1;
2324
2325 u32 antdiv_rssi_max;
2326 u32 rssi_max;
2327 };
2328
2329 struct rtl_global_var {
2330 /* from this list we can get
2331 * other adapter's rtl_priv */
2332 struct list_head glb_priv_list;
2333 spinlock_t glb_list_lock;
2334 };
2335
2336 struct rtl_btc_info {
2337 u8 bt_type;
2338 u8 btcoexist;
2339 u8 ant_num;
2340 };
2341
2342 struct bt_coexist_info {
2343 struct rtl_btc_ops *btc_ops;
2344 struct rtl_btc_info btc_info;
2345 /* EEPROM BT info. */
2346 u8 eeprom_bt_coexist;
2347 u8 eeprom_bt_type;
2348 u8 eeprom_bt_ant_num;
2349 u8 eeprom_bt_ant_isol;
2350 u8 eeprom_bt_radio_shared;
2351
2352 u8 bt_coexistence;
2353 u8 bt_ant_num;
2354 u8 bt_coexist_type;
2355 u8 bt_state;
2356 u8 bt_cur_state; /* 0:on, 1:off */
2357 u8 bt_ant_isolation; /* 0:good, 1:bad */
2358 u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */
2359 u8 bt_service;
2360 u8 bt_radio_shared_type;
2361 u8 bt_rfreg_origin_1e;
2362 u8 bt_rfreg_origin_1f;
2363 u8 bt_rssi_state;
2364 u32 ratio_tx;
2365 u32 ratio_pri;
2366 u32 bt_edca_ul;
2367 u32 bt_edca_dl;
2368
2369 bool init_set;
2370 bool bt_busy_traffic;
2371 bool bt_traffic_mode_set;
2372 bool bt_non_traffic_mode_set;
2373
2374 bool fw_coexist_all_off;
2375 bool sw_coexist_all_off;
2376 bool hw_coexist_all_off;
2377 u32 cstate;
2378 u32 previous_state;
2379 u32 cstate_h;
2380 u32 previous_state_h;
2381
2382 u8 bt_pre_rssi_state;
2383 u8 bt_pre_rssi_state1;
2384
2385 u8 reg_bt_iso;
2386 u8 reg_bt_sco;
2387 bool balance_on;
2388 u8 bt_active_zero_cnt;
2389 bool cur_bt_disabled;
2390 bool pre_bt_disabled;
2391
2392 u8 bt_profile_case;
2393 u8 bt_profile_action;
2394 bool bt_busy;
2395 bool hold_for_bt_operation;
2396 u8 lps_counter;
2397 };
2398
2399 struct rtl_btc_ops {
2400 void (*btc_init_variables) (struct rtl_priv *rtlpriv);
2401 void (*btc_init_hal_vars) (struct rtl_priv *rtlpriv);
2402 void (*btc_init_hw_config) (struct rtl_priv *rtlpriv);
2403 void (*btc_ips_notify) (struct rtl_priv *rtlpriv, u8 type);
2404 void (*btc_lps_notify)(struct rtl_priv *rtlpriv, u8 type);
2405 void (*btc_scan_notify) (struct rtl_priv *rtlpriv, u8 scantype);
2406 void (*btc_connect_notify) (struct rtl_priv *rtlpriv, u8 action);
2407 void (*btc_mediastatus_notify) (struct rtl_priv *rtlpriv,
2408 enum rt_media_status mstatus);
2409 void (*btc_periodical) (struct rtl_priv *rtlpriv);
2410 void (*btc_halt_notify) (void);
2411 void (*btc_btinfo_notify) (struct rtl_priv *rtlpriv,
2412 u8 *tmp_buf, u8 length);
2413 bool (*btc_is_limited_dig) (struct rtl_priv *rtlpriv);
2414 bool (*btc_is_disable_edca_turbo) (struct rtl_priv *rtlpriv);
2415 bool (*btc_is_bt_disabled) (struct rtl_priv *rtlpriv);
2416 void (*btc_special_packet_notify)(struct rtl_priv *rtlpriv,
2417 u8 pkt_type);
2418 };
2419
2420 struct proxim {
2421 bool proxim_on;
2422
2423 void *proximity_priv;
2424 int (*proxim_rx)(struct ieee80211_hw *hw, struct rtl_stats *status,
2425 struct sk_buff *skb);
2426 u8 (*proxim_get_var)(struct ieee80211_hw *hw, u8 type);
2427 };
2428
2429 struct rtl_priv {
2430 struct ieee80211_hw *hw;
2431 struct completion firmware_loading_complete;
2432 struct list_head list;
2433 struct rtl_priv *buddy_priv;
2434 struct rtl_global_var *glb_var;
2435 struct rtl_dualmac_easy_concurrent_ctl easy_concurrent_ctl;
2436 struct rtl_dmsp_ctl dmsp_ctl;
2437 struct rtl_locks locks;
2438 struct rtl_works works;
2439 struct rtl_mac mac80211;
2440 struct rtl_hal rtlhal;
2441 struct rtl_regulatory regd;
2442 struct rtl_rfkill rfkill;
2443 struct rtl_io io;
2444 struct rtl_phy phy;
2445 struct rtl_dm dm;
2446 struct rtl_security sec;
2447 struct rtl_efuse efuse;
2448
2449 struct rtl_ps_ctl psc;
2450 struct rate_adaptive ra;
2451 struct dynamic_primary_cca primarycca;
2452 struct wireless_stats stats;
2453 struct rt_link_detect link_info;
2454 struct false_alarm_statistics falsealm_cnt;
2455
2456 struct rtl_rate_priv *rate_priv;
2457
2458 /* sta entry list for ap adhoc or mesh */
2459 struct list_head entry_list;
2460
2461 struct rtl_debug dbg;
2462 int max_fw_size;
2463
2464 /*
2465 *hal_cfg : for diff cards
2466 *intf_ops : for diff interrface usb/pcie
2467 */
2468 struct rtl_hal_cfg *cfg;
2469 struct rtl_intf_ops *intf_ops;
2470
2471 /*this var will be set by set_bit,
2472 and was used to indicate status of
2473 interface or hardware */
2474 unsigned long status;
2475
2476 /* tables for dm */
2477 struct dig_t dm_digtable;
2478 struct ps_t dm_pstable;
2479
2480 u32 reg_874;
2481 u32 reg_c70;
2482 u32 reg_85c;
2483 u32 reg_a74;
2484 bool reg_init; /* true if regs saved */
2485 bool bt_operation_on;
2486 __le32 *usb_data;
2487 int usb_data_index;
2488 bool initialized;
2489 bool enter_ps; /* true when entering PS */
2490 u8 rate_mask[5];
2491
2492 /* intel Proximity, should be alloc mem
2493 * in intel Proximity module and can only
2494 * be used in intel Proximity mode
2495 */
2496 struct proxim proximity;
2497
2498 /*for bt coexist use*/
2499 struct bt_coexist_info btcoexist;
2500
2501 /* separate 92ee from other ICs,
2502 * 92ee use new trx flow.
2503 */
2504 bool use_new_trx_flow;
2505
2506 /*This must be the last item so
2507 that it points to the data allocated
2508 beyond this structure like:
2509 rtl_pci_priv or rtl_usb_priv */
2510 u8 priv[0] __aligned(sizeof(void *));
2511 };
2512
2513 #define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv))
2514 #define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211))
2515 #define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal))
2516 #define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse))
2517 #define rtl_psc(rtlpriv) (&((rtlpriv)->psc))
2518
2519
2520 /***************************************
2521 Bluetooth Co-existence Related
2522 ****************************************/
2523
2524 enum bt_ant_num {
2525 ANT_X2 = 0,
2526 ANT_X1 = 1,
2527 };
2528
2529 enum bt_co_type {
2530 BT_2WIRE = 0,
2531 BT_ISSC_3WIRE = 1,
2532 BT_ACCEL = 2,
2533 BT_CSR_BC4 = 3,
2534 BT_CSR_BC8 = 4,
2535 BT_RTL8756 = 5,
2536 BT_RTL8723A = 6,
2537 BT_RTL8821A = 7,
2538 BT_RTL8723B = 8,
2539 BT_RTL8192E = 9,
2540 BT_RTL8812A = 11,
2541 };
2542
2543 enum bt_total_ant_num {
2544 ANT_TOTAL_X2 = 0,
2545 ANT_TOTAL_X1 = 1
2546 };
2547
2548 enum bt_cur_state {
2549 BT_OFF = 0,
2550 BT_ON = 1,
2551 };
2552
2553 enum bt_service_type {
2554 BT_SCO = 0,
2555 BT_A2DP = 1,
2556 BT_HID = 2,
2557 BT_HID_IDLE = 3,
2558 BT_SCAN = 4,
2559 BT_IDLE = 5,
2560 BT_OTHER_ACTION = 6,
2561 BT_BUSY = 7,
2562 BT_OTHERBUSY = 8,
2563 BT_PAN = 9,
2564 };
2565
2566 enum bt_radio_shared {
2567 BT_RADIO_SHARED = 0,
2568 BT_RADIO_INDIVIDUAL = 1,
2569 };
2570
2571
2572 /****************************************
2573 mem access macro define start
2574 Call endian free function when
2575 1. Read/write packet content.
2576 2. Before write integer to IO.
2577 3. After read integer from IO.
2578 ****************************************/
2579 /* Convert little data endian to host ordering */
2580 #define EF1BYTE(_val) \
2581 ((u8)(_val))
2582 #define EF2BYTE(_val) \
2583 (le16_to_cpu(_val))
2584 #define EF4BYTE(_val) \
2585 (le32_to_cpu(_val))
2586
2587 /* Read data from memory */
2588 #define READEF1BYTE(_ptr) \
2589 EF1BYTE(*((u8 *)(_ptr)))
2590 /* Read le16 data from memory and convert to host ordering */
2591 #define READEF2BYTE(_ptr) \
2592 EF2BYTE(*(_ptr))
2593 #define READEF4BYTE(_ptr) \
2594 EF4BYTE(*(_ptr))
2595
2596 /* Write data to memory */
2597 #define WRITEEF1BYTE(_ptr, _val) \
2598 (*((u8 *)(_ptr))) = EF1BYTE(_val)
2599 /* Write le16 data to memory in host ordering */
2600 #define WRITEEF2BYTE(_ptr, _val) \
2601 (*((u16 *)(_ptr))) = EF2BYTE(_val)
2602 #define WRITEEF4BYTE(_ptr, _val) \
2603 (*((u32 *)(_ptr))) = EF2BYTE(_val)
2604
2605 /* Create a bit mask
2606 * Examples:
2607 * BIT_LEN_MASK_32(0) => 0x00000000
2608 * BIT_LEN_MASK_32(1) => 0x00000001
2609 * BIT_LEN_MASK_32(2) => 0x00000003
2610 * BIT_LEN_MASK_32(32) => 0xFFFFFFFF
2611 */
2612 #define BIT_LEN_MASK_32(__bitlen) \
2613 (0xFFFFFFFF >> (32 - (__bitlen)))
2614 #define BIT_LEN_MASK_16(__bitlen) \
2615 (0xFFFF >> (16 - (__bitlen)))
2616 #define BIT_LEN_MASK_8(__bitlen) \
2617 (0xFF >> (8 - (__bitlen)))
2618
2619 /* Create an offset bit mask
2620 * Examples:
2621 * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
2622 * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
2623 */
2624 #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
2625 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
2626 #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
2627 (BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
2628 #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
2629 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
2630
2631 /*Description:
2632 * Return 4-byte value in host byte ordering from
2633 * 4-byte pointer in little-endian system.
2634 */
2635 #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
2636 (EF4BYTE(*((__le32 *)(__pstart))))
2637 #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
2638 (EF2BYTE(*((__le16 *)(__pstart))))
2639 #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
2640 (EF1BYTE(*((u8 *)(__pstart))))
2641
2642 /*Description:
2643 Translate subfield (continuous bits in little-endian) of 4-byte
2644 value to host byte ordering.*/
2645 #define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
2646 ( \
2647 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \
2648 BIT_LEN_MASK_32(__bitlen) \
2649 )
2650 #define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
2651 ( \
2652 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \
2653 BIT_LEN_MASK_16(__bitlen) \
2654 )
2655 #define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
2656 ( \
2657 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \
2658 BIT_LEN_MASK_8(__bitlen) \
2659 )
2660
2661 /* Description:
2662 * Mask subfield (continuous bits in little-endian) of 4-byte value
2663 * and return the result in 4-byte value in host byte ordering.
2664 */
2665 #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
2666 ( \
2667 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \
2668 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \
2669 )
2670 #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
2671 ( \
2672 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
2673 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \
2674 )
2675 #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
2676 ( \
2677 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
2678 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \
2679 )
2680
2681 /* Description:
2682 * Set subfield of little-endian 4-byte value to specified value.
2683 */
2684 #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
2685 *((u32 *)(__pstart)) = \
2686 ( \
2687 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
2688 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \
2689 );
2690 #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
2691 *((u16 *)(__pstart)) = \
2692 ( \
2693 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
2694 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \
2695 );
2696 #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
2697 *((u8 *)(__pstart)) = EF1BYTE \
2698 ( \
2699 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
2700 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
2701 );
2702
2703 #define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \
2704 (__value) : (((__value + __aligment - 1) / __aligment) * __aligment))
2705
2706 /****************************************
2707 mem access macro define end
2708 ****************************************/
2709
2710 #define byte(x, n) ((x >> (8 * n)) & 0xff)
2711
2712 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
2713 #define RTL_WATCH_DOG_TIME 2000
2714 #define MSECS(t) msecs_to_jiffies(t)
2715 #define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS)
2716 #define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE)
2717 #define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE)
2718 #define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA)
2719 #define rtl_dm(rtlpriv) (&((rtlpriv)->dm))
2720
2721 #define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */
2722 #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */
2723 #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */
2724 /*NIC halt, re-initialize hw parameters*/
2725 #define RT_RF_OFF_LEVL_HALT_NIC BIT(3)
2726 #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */
2727 #define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */
2728 /*Always enable ASPM and Clock Req in initialization.*/
2729 #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6)
2730 /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
2731 #define RT_PS_LEVEL_ASPM BIT(7)
2732 /*When LPS is on, disable 2R if no packet is received or transmittd.*/
2733 #define RT_RF_LPS_DISALBE_2R BIT(30)
2734 #define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */
2735 #define RT_IN_PS_LEVEL(ppsc, _ps_flg) \
2736 ((ppsc->cur_ps_level & _ps_flg) ? true : false)
2737 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \
2738 (ppsc->cur_ps_level &= (~(_ps_flg)))
2739 #define RT_SET_PS_LEVEL(ppsc, _ps_flg) \
2740 (ppsc->cur_ps_level |= _ps_flg)
2741
2742 #define container_of_dwork_rtl(x, y, z) \
2743 container_of(container_of(x, struct delayed_work, work), y, z)
2744
2745 #define FILL_OCTET_STRING(_os, _octet, _len) \
2746 (_os).octet = (u8 *)(_octet); \
2747 (_os).length = (_len);
2748
2749 #define CP_MACADDR(des, src) \
2750 ((des)[0] = (src)[0], (des)[1] = (src)[1],\
2751 (des)[2] = (src)[2], (des)[3] = (src)[3],\
2752 (des)[4] = (src)[4], (des)[5] = (src)[5])
2753
2754 static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
2755 {
2756 return rtlpriv->io.read8_sync(rtlpriv, addr);
2757 }
2758
2759 static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
2760 {
2761 return rtlpriv->io.read16_sync(rtlpriv, addr);
2762 }
2763
2764 static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
2765 {
2766 return rtlpriv->io.read32_sync(rtlpriv, addr);
2767 }
2768
2769 static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
2770 {
2771 rtlpriv->io.write8_async(rtlpriv, addr, val8);
2772
2773 if (rtlpriv->cfg->write_readback)
2774 rtlpriv->io.read8_sync(rtlpriv, addr);
2775 }
2776
2777 static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
2778 {
2779 rtlpriv->io.write16_async(rtlpriv, addr, val16);
2780
2781 if (rtlpriv->cfg->write_readback)
2782 rtlpriv->io.read16_sync(rtlpriv, addr);
2783 }
2784
2785 static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
2786 u32 addr, u32 val32)
2787 {
2788 rtlpriv->io.write32_async(rtlpriv, addr, val32);
2789
2790 if (rtlpriv->cfg->write_readback)
2791 rtlpriv->io.read32_sync(rtlpriv, addr);
2792 }
2793
2794 static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
2795 u32 regaddr, u32 bitmask)
2796 {
2797 struct rtl_priv *rtlpriv = hw->priv;
2798
2799 return rtlpriv->cfg->ops->get_bbreg(hw, regaddr, bitmask);
2800 }
2801
2802 static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
2803 u32 bitmask, u32 data)
2804 {
2805 struct rtl_priv *rtlpriv = hw->priv;
2806
2807 rtlpriv->cfg->ops->set_bbreg(hw, regaddr, bitmask, data);
2808 }
2809
2810 static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
2811 enum radio_path rfpath, u32 regaddr,
2812 u32 bitmask)
2813 {
2814 struct rtl_priv *rtlpriv = hw->priv;
2815
2816 return rtlpriv->cfg->ops->get_rfreg(hw, rfpath, regaddr, bitmask);
2817 }
2818
2819 static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
2820 enum radio_path rfpath, u32 regaddr,
2821 u32 bitmask, u32 data)
2822 {
2823 struct rtl_priv *rtlpriv = hw->priv;
2824
2825 rtlpriv->cfg->ops->set_rfreg(hw, rfpath, regaddr, bitmask, data);
2826 }
2827
2828 static inline bool is_hal_stop(struct rtl_hal *rtlhal)
2829 {
2830 return (_HAL_STATE_STOP == rtlhal->state);
2831 }
2832
2833 static inline void set_hal_start(struct rtl_hal *rtlhal)
2834 {
2835 rtlhal->state = _HAL_STATE_START;
2836 }
2837
2838 static inline void set_hal_stop(struct rtl_hal *rtlhal)
2839 {
2840 rtlhal->state = _HAL_STATE_STOP;
2841 }
2842
2843 static inline u8 get_rf_type(struct rtl_phy *rtlphy)
2844 {
2845 return rtlphy->rf_type;
2846 }
2847
2848 static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb)
2849 {
2850 return (struct ieee80211_hdr *)(skb->data);
2851 }
2852
2853 static inline __le16 rtl_get_fc(struct sk_buff *skb)
2854 {
2855 return rtl_get_hdr(skb)->frame_control;
2856 }
2857
2858 static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr)
2859 {
2860 return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK;
2861 }
2862
2863 static inline u16 rtl_get_tid(struct sk_buff *skb)
2864 {
2865 return rtl_get_tid_h(rtl_get_hdr(skb));
2866 }
2867
2868 static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw,
2869 struct ieee80211_vif *vif,
2870 const u8 *bssid)
2871 {
2872 return ieee80211_find_sta(vif, bssid);
2873 }
2874
2875 static inline struct ieee80211_sta *rtl_find_sta(struct ieee80211_hw *hw,
2876 u8 *mac_addr)
2877 {
2878 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2879 return ieee80211_find_sta(mac->vif, mac_addr);
2880 }
2881
2882 #endif
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