2 * This file is part of wl1271
4 * Copyright (C) 2008-2010 Nokia Corporation
6 * Contact: Luciano Coelho <luciano.coelho@nokia.com>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
24 #include <linux/slab.h>
25 #include <linux/wl12xx.h>
35 static struct wl1271_partition_set part_table
[PART_TABLE_LEN
] = {
42 .start
= REGISTERS_BASE
,
61 .start
= REGISTERS_BASE
,
94 static void wl1271_boot_set_ecpu_ctrl(struct wl1271
*wl
, u32 flag
)
98 /* 10.5.0 run the firmware (I) */
99 cpu_ctrl
= wl1271_read32(wl
, ACX_REG_ECPU_CONTROL
);
101 /* 10.5.1 run the firmware (II) */
103 wl1271_write32(wl
, ACX_REG_ECPU_CONTROL
, cpu_ctrl
);
106 static unsigned int wl12xx_get_fw_ver_quirks(struct wl1271
*wl
)
108 unsigned int quirks
= 0;
109 unsigned int *fw_ver
= wl
->chip
.fw_ver
;
111 /* Only new station firmwares support routing fw logs to the host */
112 if ((fw_ver
[FW_VER_IF_TYPE
] == FW_VER_IF_TYPE_STA
) &&
113 (fw_ver
[FW_VER_MINOR
] < FW_VER_MINOR_FWLOG_STA_MIN
))
114 quirks
|= WL12XX_QUIRK_FWLOG_NOT_IMPLEMENTED
;
116 /* This feature is not yet supported for AP mode */
117 if (fw_ver
[FW_VER_IF_TYPE
] == FW_VER_IF_TYPE_AP
)
118 quirks
|= WL12XX_QUIRK_FWLOG_NOT_IMPLEMENTED
;
123 static void wl1271_parse_fw_ver(struct wl1271
*wl
)
127 ret
= sscanf(wl
->chip
.fw_ver_str
+ 4, "%u.%u.%u.%u.%u",
128 &wl
->chip
.fw_ver
[0], &wl
->chip
.fw_ver
[1],
129 &wl
->chip
.fw_ver
[2], &wl
->chip
.fw_ver
[3],
130 &wl
->chip
.fw_ver
[4]);
133 wl1271_warning("fw version incorrect value");
134 memset(wl
->chip
.fw_ver
, 0, sizeof(wl
->chip
.fw_ver
));
138 /* Check if any quirks are needed with older fw versions */
139 wl
->quirks
|= wl12xx_get_fw_ver_quirks(wl
);
142 static void wl1271_boot_fw_version(struct wl1271
*wl
)
144 struct wl1271_static_data static_data
;
146 wl1271_read(wl
, wl
->cmd_box_addr
, &static_data
, sizeof(static_data
),
149 strncpy(wl
->chip
.fw_ver_str
, static_data
.fw_version
,
150 sizeof(wl
->chip
.fw_ver_str
));
152 /* make sure the string is NULL-terminated */
153 wl
->chip
.fw_ver_str
[sizeof(wl
->chip
.fw_ver_str
) - 1] = '\0';
155 wl1271_parse_fw_ver(wl
);
158 static int wl1271_boot_upload_firmware_chunk(struct wl1271
*wl
, void *buf
,
159 size_t fw_data_len
, u32 dest
)
161 struct wl1271_partition_set partition
;
162 int addr
, chunk_num
, partition_limit
;
165 /* whal_FwCtrl_LoadFwImageSm() */
167 wl1271_debug(DEBUG_BOOT
, "starting firmware upload");
169 wl1271_debug(DEBUG_BOOT
, "fw_data_len %zd chunk_size %d",
170 fw_data_len
, CHUNK_SIZE
);
172 if ((fw_data_len
% 4) != 0) {
173 wl1271_error("firmware length not multiple of four");
177 chunk
= kmalloc(CHUNK_SIZE
, GFP_KERNEL
);
179 wl1271_error("allocation for firmware upload chunk failed");
183 memcpy(&partition
, &part_table
[PART_DOWN
], sizeof(partition
));
184 partition
.mem
.start
= dest
;
185 wl1271_set_partition(wl
, &partition
);
187 /* 10.1 set partition limit and chunk num */
189 partition_limit
= part_table
[PART_DOWN
].mem
.size
;
191 while (chunk_num
< fw_data_len
/ CHUNK_SIZE
) {
192 /* 10.2 update partition, if needed */
193 addr
= dest
+ (chunk_num
+ 2) * CHUNK_SIZE
;
194 if (addr
> partition_limit
) {
195 addr
= dest
+ chunk_num
* CHUNK_SIZE
;
196 partition_limit
= chunk_num
* CHUNK_SIZE
+
197 part_table
[PART_DOWN
].mem
.size
;
198 partition
.mem
.start
= addr
;
199 wl1271_set_partition(wl
, &partition
);
202 /* 10.3 upload the chunk */
203 addr
= dest
+ chunk_num
* CHUNK_SIZE
;
204 p
= buf
+ chunk_num
* CHUNK_SIZE
;
205 memcpy(chunk
, p
, CHUNK_SIZE
);
206 wl1271_debug(DEBUG_BOOT
, "uploading fw chunk 0x%p to 0x%x",
208 wl1271_write(wl
, addr
, chunk
, CHUNK_SIZE
, false);
213 /* 10.4 upload the last chunk */
214 addr
= dest
+ chunk_num
* CHUNK_SIZE
;
215 p
= buf
+ chunk_num
* CHUNK_SIZE
;
216 memcpy(chunk
, p
, fw_data_len
% CHUNK_SIZE
);
217 wl1271_debug(DEBUG_BOOT
, "uploading fw last chunk (%zd B) 0x%p to 0x%x",
218 fw_data_len
% CHUNK_SIZE
, p
, addr
);
219 wl1271_write(wl
, addr
, chunk
, fw_data_len
% CHUNK_SIZE
, false);
225 static int wl1271_boot_upload_firmware(struct wl1271
*wl
)
227 u32 chunks
, addr
, len
;
232 chunks
= be32_to_cpup((__be32
*) fw
);
235 wl1271_debug(DEBUG_BOOT
, "firmware chunks to be uploaded: %u", chunks
);
238 addr
= be32_to_cpup((__be32
*) fw
);
240 len
= be32_to_cpup((__be32
*) fw
);
244 wl1271_info("firmware chunk too long: %u", len
);
247 wl1271_debug(DEBUG_BOOT
, "chunk %d addr 0x%x len %u",
249 ret
= wl1271_boot_upload_firmware_chunk(wl
, fw
, len
, addr
);
258 static int wl1271_boot_upload_nvs(struct wl1271
*wl
)
260 size_t nvs_len
, burst_len
;
263 u8
*nvs_ptr
, *nvs_aligned
;
268 if (wl
->chip
.id
== CHIP_ID_1283_PG20
) {
269 struct wl128x_nvs_file
*nvs
= (struct wl128x_nvs_file
*)wl
->nvs
;
271 if (wl
->nvs_len
== sizeof(struct wl128x_nvs_file
)) {
272 if (nvs
->general_params
.dual_mode_select
)
273 wl
->enable_11a
= true;
275 wl1271_error("nvs size is not as expected: %zu != %zu",
277 sizeof(struct wl128x_nvs_file
));
284 /* only the first part of the NVS needs to be uploaded */
285 nvs_len
= sizeof(nvs
->nvs
);
286 nvs_ptr
= (u8
*)nvs
->nvs
;
289 struct wl1271_nvs_file
*nvs
=
290 (struct wl1271_nvs_file
*)wl
->nvs
;
292 * FIXME: the LEGACY NVS image support (NVS's missing the 5GHz
293 * band configurations) can be removed when those NVS files stop
296 if (wl
->nvs_len
== sizeof(struct wl1271_nvs_file
) ||
297 wl
->nvs_len
== WL1271_INI_LEGACY_NVS_FILE_SIZE
) {
298 if (nvs
->general_params
.dual_mode_select
)
299 wl
->enable_11a
= true;
302 if (wl
->nvs_len
!= sizeof(struct wl1271_nvs_file
) &&
303 (wl
->nvs_len
!= WL1271_INI_LEGACY_NVS_FILE_SIZE
||
305 wl1271_error("nvs size is not as expected: %zu != %zu",
306 wl
->nvs_len
, sizeof(struct wl1271_nvs_file
));
313 /* only the first part of the NVS needs to be uploaded */
314 nvs_len
= sizeof(nvs
->nvs
);
315 nvs_ptr
= (u8
*) nvs
->nvs
;
318 /* update current MAC address to NVS */
319 nvs_ptr
[11] = wl
->mac_addr
[0];
320 nvs_ptr
[10] = wl
->mac_addr
[1];
321 nvs_ptr
[6] = wl
->mac_addr
[2];
322 nvs_ptr
[5] = wl
->mac_addr
[3];
323 nvs_ptr
[4] = wl
->mac_addr
[4];
324 nvs_ptr
[3] = wl
->mac_addr
[5];
327 * Layout before the actual NVS tables:
328 * 1 byte : burst length.
329 * 2 bytes: destination address.
330 * n bytes: data to burst copy.
332 * This is ended by a 0 length, then the NVS tables.
335 /* FIXME: Do we need to check here whether the LSB is 1? */
337 burst_len
= nvs_ptr
[0];
338 dest_addr
= (nvs_ptr
[1] & 0xfe) | ((u32
)(nvs_ptr
[2] << 8));
341 * Due to our new wl1271_translate_reg_addr function,
342 * we need to add the REGISTER_BASE to the destination
344 dest_addr
+= REGISTERS_BASE
;
346 /* We move our pointer to the data */
349 for (i
= 0; i
< burst_len
; i
++) {
350 val
= (nvs_ptr
[0] | (nvs_ptr
[1] << 8)
351 | (nvs_ptr
[2] << 16) | (nvs_ptr
[3] << 24));
353 wl1271_debug(DEBUG_BOOT
,
354 "nvs burst write 0x%x: 0x%x",
356 wl1271_write32(wl
, dest_addr
, val
);
364 * We've reached the first zero length, the first NVS table
365 * is located at an aligned offset which is at least 7 bytes further.
366 * NOTE: The wl->nvs->nvs element must be first, in order to
367 * simplify the casting, we assume it is at the beginning of
368 * the wl->nvs structure.
370 nvs_ptr
= (u8
*)wl
->nvs
+
371 ALIGN(nvs_ptr
- (u8
*)wl
->nvs
+ 7, 4);
372 nvs_len
-= nvs_ptr
- (u8
*)wl
->nvs
;
374 /* Now we must set the partition correctly */
375 wl1271_set_partition(wl
, &part_table
[PART_WORK
]);
377 /* Copy the NVS tables to a new block to ensure alignment */
378 nvs_aligned
= kmemdup(nvs_ptr
, nvs_len
, GFP_KERNEL
);
382 /* And finally we upload the NVS tables */
383 wl1271_write(wl
, CMD_MBOX_ADDRESS
, nvs_aligned
, nvs_len
, false);
389 static void wl1271_boot_enable_interrupts(struct wl1271
*wl
)
391 wl1271_enable_interrupts(wl
);
392 wl1271_write32(wl
, ACX_REG_INTERRUPT_MASK
,
393 WL1271_ACX_INTR_ALL
& ~(WL1271_INTR_MASK
));
394 wl1271_write32(wl
, HI_CFG
, HI_CFG_DEF_VAL
);
397 static int wl1271_boot_soft_reset(struct wl1271
*wl
)
399 unsigned long timeout
;
402 /* perform soft reset */
403 wl1271_write32(wl
, ACX_REG_SLV_SOFT_RESET
, ACX_SLV_SOFT_RESET_BIT
);
405 /* SOFT_RESET is self clearing */
406 timeout
= jiffies
+ usecs_to_jiffies(SOFT_RESET_MAX_TIME
);
408 boot_data
= wl1271_read32(wl
, ACX_REG_SLV_SOFT_RESET
);
409 wl1271_debug(DEBUG_BOOT
, "soft reset bootdata 0x%x", boot_data
);
410 if ((boot_data
& ACX_SLV_SOFT_RESET_BIT
) == 0)
413 if (time_after(jiffies
, timeout
)) {
414 /* 1.2 check pWhalBus->uSelfClearTime if the
415 * timeout was reached */
416 wl1271_error("soft reset timeout");
420 udelay(SOFT_RESET_STALL_TIME
);
424 wl1271_write32(wl
, ENABLE
, 0x0);
426 /* disable auto calibration on start*/
427 wl1271_write32(wl
, SPARE_A2
, 0xffff);
432 static int wl1271_boot_run_firmware(struct wl1271
*wl
)
437 wl1271_boot_set_ecpu_ctrl(wl
, ECPU_CONTROL_HALT
);
439 chip_id
= wl1271_read32(wl
, CHIP_ID_B
);
441 wl1271_debug(DEBUG_BOOT
, "chip id after firmware boot: 0x%x", chip_id
);
443 if (chip_id
!= wl
->chip
.id
) {
444 wl1271_error("chip id doesn't match after firmware boot");
448 /* wait for init to complete */
450 while (loop
++ < INIT_LOOP
) {
451 udelay(INIT_LOOP_DELAY
);
452 intr
= wl1271_read32(wl
, ACX_REG_INTERRUPT_NO_CLEAR
);
454 if (intr
== 0xffffffff) {
455 wl1271_error("error reading hardware complete "
459 /* check that ACX_INTR_INIT_COMPLETE is enabled */
460 else if (intr
& WL1271_ACX_INTR_INIT_COMPLETE
) {
461 wl1271_write32(wl
, ACX_REG_INTERRUPT_ACK
,
462 WL1271_ACX_INTR_INIT_COMPLETE
);
467 if (loop
> INIT_LOOP
) {
468 wl1271_error("timeout waiting for the hardware to "
469 "complete initialization");
473 /* get hardware config command mail box */
474 wl
->cmd_box_addr
= wl1271_read32(wl
, REG_COMMAND_MAILBOX_PTR
);
476 /* get hardware config event mail box */
477 wl
->event_box_addr
= wl1271_read32(wl
, REG_EVENT_MAILBOX_PTR
);
479 /* set the working partition to its "running" mode offset */
480 wl1271_set_partition(wl
, &part_table
[PART_WORK
]);
482 wl1271_debug(DEBUG_MAILBOX
, "cmd_box_addr 0x%x event_box_addr 0x%x",
483 wl
->cmd_box_addr
, wl
->event_box_addr
);
485 wl1271_boot_fw_version(wl
);
488 * in case of full asynchronous mode the firmware event must be
489 * ready to receive event from the command mailbox
492 /* unmask required mbox events */
493 wl
->event_mask
= BSS_LOSE_EVENT_ID
|
494 SCAN_COMPLETE_EVENT_ID
|
496 DISCONNECT_EVENT_COMPLETE_ID
|
497 RSSI_SNR_TRIGGER_0_EVENT_ID
|
498 PSPOLL_DELIVERY_FAILURE_EVENT_ID
|
499 SOFT_GEMINI_SENSE_EVENT_ID
|
500 PERIODIC_SCAN_REPORT_EVENT_ID
|
501 PERIODIC_SCAN_COMPLETE_EVENT_ID
|
502 DUMMY_PACKET_EVENT_ID
|
503 PEER_REMOVE_COMPLETE_EVENT_ID
|
504 BA_SESSION_RX_CONSTRAINT_EVENT_ID
|
505 REMAIN_ON_CHANNEL_COMPLETE_EVENT_ID
|
506 INACTIVE_STA_EVENT_ID
|
507 MAX_TX_RETRY_EVENT_ID
|
508 CHANNEL_SWITCH_COMPLETE_EVENT_ID
;
510 ret
= wl1271_event_unmask(wl
);
512 wl1271_error("EVENT mask setting failed");
516 wl1271_event_mbox_config(wl
);
518 /* firmware startup completed */
522 static int wl1271_boot_write_irq_polarity(struct wl1271
*wl
)
526 polarity
= wl1271_top_reg_read(wl
, OCP_REG_POLARITY
);
528 /* We use HIGH polarity, so unset the LOW bit */
529 polarity
&= ~POLARITY_LOW
;
530 wl1271_top_reg_write(wl
, OCP_REG_POLARITY
, polarity
);
535 static void wl1271_boot_hw_version(struct wl1271
*wl
)
539 if (wl
->chip
.id
== CHIP_ID_1283_PG20
)
540 fuse
= wl1271_top_reg_read(wl
, WL128X_REG_FUSE_DATA_2_1
);
542 fuse
= wl1271_top_reg_read(wl
, WL127X_REG_FUSE_DATA_2_1
);
543 fuse
= (fuse
& PG_VER_MASK
) >> PG_VER_OFFSET
;
545 wl
->hw_pg_ver
= (s8
)fuse
;
548 static int wl128x_switch_tcxo_to_fref(struct wl1271
*wl
)
552 /* Mask bits [2] & [8:4] in the sys_clk_cfg register */
553 spare_reg
= wl1271_top_reg_read(wl
, WL_SPARE_REG
);
554 if (spare_reg
== 0xFFFF)
556 spare_reg
|= (BIT(3) | BIT(5) | BIT(6));
557 wl1271_top_reg_write(wl
, WL_SPARE_REG
, spare_reg
);
559 /* Enable FREF_CLK_REQ & mux MCS and coex PLLs to FREF */
560 wl1271_top_reg_write(wl
, SYS_CLK_CFG_REG
,
561 WL_CLK_REQ_TYPE_PG2
| MCS_PLL_CLK_SEL_FREF
);
563 /* Delay execution for 15msec, to let the HW settle */
569 static bool wl128x_is_tcxo_valid(struct wl1271
*wl
)
573 tcxo_detection
= wl1271_top_reg_read(wl
, TCXO_CLK_DETECT_REG
);
574 if (tcxo_detection
& TCXO_DET_FAILED
)
580 static bool wl128x_is_fref_valid(struct wl1271
*wl
)
584 fref_detection
= wl1271_top_reg_read(wl
, FREF_CLK_DETECT_REG
);
585 if (fref_detection
& FREF_CLK_DETECT_FAIL
)
591 static int wl128x_manually_configure_mcs_pll(struct wl1271
*wl
)
593 wl1271_top_reg_write(wl
, MCS_PLL_M_REG
, MCS_PLL_M_REG_VAL
);
594 wl1271_top_reg_write(wl
, MCS_PLL_N_REG
, MCS_PLL_N_REG_VAL
);
595 wl1271_top_reg_write(wl
, MCS_PLL_CONFIG_REG
, MCS_PLL_CONFIG_REG_VAL
);
600 static int wl128x_configure_mcs_pll(struct wl1271
*wl
, int clk
)
606 /* Mask bits [3:1] in the sys_clk_cfg register */
607 spare_reg
= wl1271_top_reg_read(wl
, WL_SPARE_REG
);
608 if (spare_reg
== 0xFFFF)
611 wl1271_top_reg_write(wl
, WL_SPARE_REG
, spare_reg
);
613 /* Handle special cases of the TCXO clock */
614 if (wl
->tcxo_clock
== WL12XX_TCXOCLOCK_16_8
||
615 wl
->tcxo_clock
== WL12XX_TCXOCLOCK_33_6
)
616 return wl128x_manually_configure_mcs_pll(wl
);
618 /* Set the input frequency according to the selected clock source */
619 input_freq
= (clk
& 1) + 1;
621 pll_config
= wl1271_top_reg_read(wl
, MCS_PLL_CONFIG_REG
);
622 if (pll_config
== 0xFFFF)
624 pll_config
|= (input_freq
<< MCS_SEL_IN_FREQ_SHIFT
);
625 pll_config
|= MCS_PLL_ENABLE_HP
;
626 wl1271_top_reg_write(wl
, MCS_PLL_CONFIG_REG
, pll_config
);
632 * WL128x has two clocks input - TCXO and FREF.
633 * TCXO is the main clock of the device, while FREF is used to sync
634 * between the GPS and the cellular modem.
635 * In cases where TCXO is 32.736MHz or 16.368MHz, the FREF will be used
636 * as the WLAN/BT main clock.
638 static int wl128x_boot_clk(struct wl1271
*wl
, int *selected_clock
)
642 /* For XTAL-only modes, FREF will be used after switching from TCXO */
643 if (wl
->ref_clock
== WL12XX_REFCLOCK_26_XTAL
||
644 wl
->ref_clock
== WL12XX_REFCLOCK_38_XTAL
) {
645 if (!wl128x_switch_tcxo_to_fref(wl
))
650 /* Query the HW, to determine which clock source we should use */
651 sys_clk_cfg
= wl1271_top_reg_read(wl
, SYS_CLK_CFG_REG
);
652 if (sys_clk_cfg
== 0xFFFF)
654 if (sys_clk_cfg
& PRCM_CM_EN_MUX_WLAN_FREF
)
657 /* If TCXO is either 32.736MHz or 16.368MHz, switch to FREF */
658 if (wl
->tcxo_clock
== WL12XX_TCXOCLOCK_16_368
||
659 wl
->tcxo_clock
== WL12XX_TCXOCLOCK_32_736
) {
660 if (!wl128x_switch_tcxo_to_fref(wl
))
665 /* TCXO clock is selected */
666 if (!wl128x_is_tcxo_valid(wl
))
668 *selected_clock
= wl
->tcxo_clock
;
672 /* FREF clock is selected */
673 if (!wl128x_is_fref_valid(wl
))
675 *selected_clock
= wl
->ref_clock
;
678 return wl128x_configure_mcs_pll(wl
, *selected_clock
);
681 static int wl127x_boot_clk(struct wl1271
*wl
)
686 if (((wl
->hw_pg_ver
& PG_MAJOR_VER_MASK
) >> PG_MAJOR_VER_OFFSET
) < 3)
687 wl
->quirks
|= WL12XX_QUIRK_END_OF_TRANSACTION
;
689 if (wl
->ref_clock
== CONF_REF_CLK_19_2_E
||
690 wl
->ref_clock
== CONF_REF_CLK_38_4_E
||
691 wl
->ref_clock
== CONF_REF_CLK_38_4_M_XTAL
)
692 /* ref clk: 19.2/38.4/38.4-XTAL */
694 else if (wl
->ref_clock
== CONF_REF_CLK_26_E
||
695 wl
->ref_clock
== CONF_REF_CLK_52_E
)
701 if (wl
->ref_clock
!= CONF_REF_CLK_19_2_E
) {
703 /* Set clock type (open drain) */
704 val
= wl1271_top_reg_read(wl
, OCP_REG_CLK_TYPE
);
705 val
&= FREF_CLK_TYPE_BITS
;
706 wl1271_top_reg_write(wl
, OCP_REG_CLK_TYPE
, val
);
708 /* Set clock pull mode (no pull) */
709 val
= wl1271_top_reg_read(wl
, OCP_REG_CLK_PULL
);
711 wl1271_top_reg_write(wl
, OCP_REG_CLK_PULL
, val
);
714 /* Set clock polarity */
715 val
= wl1271_top_reg_read(wl
, OCP_REG_CLK_POLARITY
);
716 val
&= FREF_CLK_POLARITY_BITS
;
717 val
|= CLK_REQ_OUTN_SEL
;
718 wl1271_top_reg_write(wl
, OCP_REG_CLK_POLARITY
, val
);
721 wl1271_write32(wl
, PLL_PARAMETERS
, clk
);
723 pause
= wl1271_read32(wl
, PLL_PARAMETERS
);
725 wl1271_debug(DEBUG_BOOT
, "pause1 0x%x", pause
);
727 pause
&= ~(WU_COUNTER_PAUSE_VAL
);
728 pause
|= WU_COUNTER_PAUSE_VAL
;
729 wl1271_write32(wl
, WU_COUNTER_PAUSE
, pause
);
734 /* uploads NVS and firmware */
735 int wl1271_load_firmware(struct wl1271
*wl
)
739 int selected_clock
= -1;
741 wl1271_boot_hw_version(wl
);
743 if (wl
->chip
.id
== CHIP_ID_1283_PG20
) {
744 ret
= wl128x_boot_clk(wl
, &selected_clock
);
748 ret
= wl127x_boot_clk(wl
);
753 /* Continue the ELP wake up sequence */
754 wl1271_write32(wl
, WELP_ARM_COMMAND
, WELP_ARM_COMMAND_VAL
);
757 wl1271_set_partition(wl
, &part_table
[PART_DRPW
]);
759 /* Read-modify-write DRPW_SCRATCH_START register (see next state)
760 to be used by DRPw FW. The RTRIM value will be added by the FW
761 before taking DRPw out of reset */
763 wl1271_debug(DEBUG_BOOT
, "DRPW_SCRATCH_START %08x", DRPW_SCRATCH_START
);
764 clk
= wl1271_read32(wl
, DRPW_SCRATCH_START
);
766 wl1271_debug(DEBUG_BOOT
, "clk2 0x%x", clk
);
768 if (wl
->chip
.id
== CHIP_ID_1283_PG20
) {
769 clk
|= ((selected_clock
& 0x3) << 1) << 4;
771 clk
|= (wl
->ref_clock
<< 1) << 4;
774 wl1271_write32(wl
, DRPW_SCRATCH_START
, clk
);
776 wl1271_set_partition(wl
, &part_table
[PART_WORK
]);
778 /* Disable interrupts */
779 wl1271_write32(wl
, ACX_REG_INTERRUPT_MASK
, WL1271_ACX_INTR_ALL
);
781 ret
= wl1271_boot_soft_reset(wl
);
785 /* 2. start processing NVS file */
786 ret
= wl1271_boot_upload_nvs(wl
);
790 /* write firmware's last address (ie. it's length) to
791 * ACX_EEPROMLESS_IND_REG */
792 wl1271_debug(DEBUG_BOOT
, "ACX_EEPROMLESS_IND_REG");
794 wl1271_write32(wl
, ACX_EEPROMLESS_IND_REG
, ACX_EEPROMLESS_IND_REG
);
796 tmp
= wl1271_read32(wl
, CHIP_ID_B
);
798 wl1271_debug(DEBUG_BOOT
, "chip id 0x%x", tmp
);
800 /* 6. read the EEPROM parameters */
801 tmp
= wl1271_read32(wl
, SCR_PAD2
);
803 /* WL1271: The reference driver skips steps 7 to 10 (jumps directly
806 if (wl
->chip
.id
== CHIP_ID_1283_PG20
)
807 wl1271_top_reg_write(wl
, SDIO_IO_DS
, wl
->conf
.hci_io_ds
);
809 ret
= wl1271_boot_upload_firmware(wl
);
816 EXPORT_SYMBOL_GPL(wl1271_load_firmware
);
818 int wl1271_boot(struct wl1271
*wl
)
822 /* upload NVS and firmware */
823 ret
= wl1271_load_firmware(wl
);
827 /* 10.5 start firmware */
828 ret
= wl1271_boot_run_firmware(wl
);
832 ret
= wl1271_boot_write_irq_polarity(wl
);
836 wl1271_write32(wl
, ACX_REG_INTERRUPT_MASK
,
837 WL1271_ACX_ALL_EVENTS_VECTOR
);
839 /* Enable firmware interrupts now */
840 wl1271_boot_enable_interrupts(wl
);
842 wl1271_event_mbox_config(wl
);