2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/aer.h>
16 #include <linux/bitops.h>
17 #include <linux/blkdev.h>
18 #include <linux/blk-mq.h>
19 #include <linux/blk-mq-pci.h>
20 #include <linux/dmi.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
25 #include <linux/module.h>
26 #include <linux/mutex.h>
27 #include <linux/pci.h>
28 #include <linux/poison.h>
29 #include <linux/t10-pi.h>
30 #include <linux/timer.h>
31 #include <linux/types.h>
32 #include <linux/io-64-nonatomic-lo-hi.h>
33 #include <asm/unaligned.h>
34 #include <linux/sed-opal.h>
38 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
39 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
42 * We handle AEN commands ourselves and don't even let the
43 * block layer know about them.
45 #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AERS)
47 static int use_threaded_interrupts
;
48 module_param(use_threaded_interrupts
, int, 0);
50 static bool use_cmb_sqes
= true;
51 module_param(use_cmb_sqes
, bool, 0644);
52 MODULE_PARM_DESC(use_cmb_sqes
, "use controller's memory buffer for I/O SQes");
54 static unsigned int max_host_mem_size_mb
= 128;
55 module_param(max_host_mem_size_mb
, uint
, 0444);
56 MODULE_PARM_DESC(max_host_mem_size_mb
,
57 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
59 static int io_queue_depth_set(const char *val
, const struct kernel_param
*kp
);
60 static const struct kernel_param_ops io_queue_depth_ops
= {
61 .set
= io_queue_depth_set
,
65 static int io_queue_depth
= 1024;
66 module_param_cb(io_queue_depth
, &io_queue_depth_ops
, &io_queue_depth
, 0644);
67 MODULE_PARM_DESC(io_queue_depth
, "set io queue depth, should >= 2");
72 static void nvme_process_cq(struct nvme_queue
*nvmeq
);
73 static void nvme_dev_disable(struct nvme_dev
*dev
, bool shutdown
);
76 * Represents an NVM Express device. Each nvme_dev is a PCI function.
79 struct nvme_queue
**queues
;
80 struct blk_mq_tag_set tagset
;
81 struct blk_mq_tag_set admin_tagset
;
84 struct dma_pool
*prp_page_pool
;
85 struct dma_pool
*prp_small_pool
;
86 unsigned online_queues
;
91 unsigned long bar_mapped_size
;
92 struct work_struct remove_work
;
93 struct mutex shutdown_lock
;
96 dma_addr_t cmb_dma_addr
;
100 struct nvme_ctrl ctrl
;
101 struct completion ioq_wait
;
103 /* shadow doorbell buffer support: */
105 dma_addr_t dbbuf_dbs_dma_addr
;
107 dma_addr_t dbbuf_eis_dma_addr
;
109 /* host memory buffer support: */
111 u32 nr_host_mem_descs
;
112 dma_addr_t host_mem_descs_dma
;
113 struct nvme_host_mem_buf_desc
*host_mem_descs
;
114 void **host_mem_desc_bufs
;
117 static int io_queue_depth_set(const char *val
, const struct kernel_param
*kp
)
121 ret
= kstrtoint(val
, 10, &n
);
122 if (ret
!= 0 || n
< 2)
125 return param_set_int(val
, kp
);
128 static inline unsigned int sq_idx(unsigned int qid
, u32 stride
)
130 return qid
* 2 * stride
;
133 static inline unsigned int cq_idx(unsigned int qid
, u32 stride
)
135 return (qid
* 2 + 1) * stride
;
138 static inline struct nvme_dev
*to_nvme_dev(struct nvme_ctrl
*ctrl
)
140 return container_of(ctrl
, struct nvme_dev
, ctrl
);
144 * An NVM Express queue. Each device has at least two (one for admin
145 * commands and one for I/O commands).
148 struct device
*q_dmadev
;
149 struct nvme_dev
*dev
;
151 struct nvme_command
*sq_cmds
;
152 struct nvme_command __iomem
*sq_cmds_io
;
153 volatile struct nvme_completion
*cqes
;
154 struct blk_mq_tags
**tags
;
155 dma_addr_t sq_dma_addr
;
156 dma_addr_t cq_dma_addr
;
172 * The nvme_iod describes the data in an I/O, including the list of PRP
173 * entries. You can't see it in this data structure because C doesn't let
174 * me express that. Use nvme_init_iod to ensure there's enough space
175 * allocated to store the PRP list.
178 struct nvme_request req
;
179 struct nvme_queue
*nvmeq
;
181 int npages
; /* In the PRP list. 0 means small pool in use */
182 int nents
; /* Used in scatterlist */
183 int length
; /* Of data, in bytes */
184 dma_addr_t first_dma
;
185 struct scatterlist meta_sg
; /* metadata requires single contiguous buffer */
186 struct scatterlist
*sg
;
187 struct scatterlist inline_sg
[0];
191 * Check we didin't inadvertently grow the command struct
193 static inline void _nvme_check_size(void)
195 BUILD_BUG_ON(sizeof(struct nvme_rw_command
) != 64);
196 BUILD_BUG_ON(sizeof(struct nvme_create_cq
) != 64);
197 BUILD_BUG_ON(sizeof(struct nvme_create_sq
) != 64);
198 BUILD_BUG_ON(sizeof(struct nvme_delete_queue
) != 64);
199 BUILD_BUG_ON(sizeof(struct nvme_features
) != 64);
200 BUILD_BUG_ON(sizeof(struct nvme_format_cmd
) != 64);
201 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd
) != 64);
202 BUILD_BUG_ON(sizeof(struct nvme_command
) != 64);
203 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl
) != NVME_IDENTIFY_DATA_SIZE
);
204 BUILD_BUG_ON(sizeof(struct nvme_id_ns
) != NVME_IDENTIFY_DATA_SIZE
);
205 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type
) != 64);
206 BUILD_BUG_ON(sizeof(struct nvme_smart_log
) != 512);
207 BUILD_BUG_ON(sizeof(struct nvme_dbbuf
) != 64);
210 static inline unsigned int nvme_dbbuf_size(u32 stride
)
212 return ((num_possible_cpus() + 1) * 8 * stride
);
215 static int nvme_dbbuf_dma_alloc(struct nvme_dev
*dev
)
217 unsigned int mem_size
= nvme_dbbuf_size(dev
->db_stride
);
222 dev
->dbbuf_dbs
= dma_alloc_coherent(dev
->dev
, mem_size
,
223 &dev
->dbbuf_dbs_dma_addr
,
227 dev
->dbbuf_eis
= dma_alloc_coherent(dev
->dev
, mem_size
,
228 &dev
->dbbuf_eis_dma_addr
,
230 if (!dev
->dbbuf_eis
) {
231 dma_free_coherent(dev
->dev
, mem_size
,
232 dev
->dbbuf_dbs
, dev
->dbbuf_dbs_dma_addr
);
233 dev
->dbbuf_dbs
= NULL
;
240 static void nvme_dbbuf_dma_free(struct nvme_dev
*dev
)
242 unsigned int mem_size
= nvme_dbbuf_size(dev
->db_stride
);
244 if (dev
->dbbuf_dbs
) {
245 dma_free_coherent(dev
->dev
, mem_size
,
246 dev
->dbbuf_dbs
, dev
->dbbuf_dbs_dma_addr
);
247 dev
->dbbuf_dbs
= NULL
;
249 if (dev
->dbbuf_eis
) {
250 dma_free_coherent(dev
->dev
, mem_size
,
251 dev
->dbbuf_eis
, dev
->dbbuf_eis_dma_addr
);
252 dev
->dbbuf_eis
= NULL
;
256 static void nvme_dbbuf_init(struct nvme_dev
*dev
,
257 struct nvme_queue
*nvmeq
, int qid
)
259 if (!dev
->dbbuf_dbs
|| !qid
)
262 nvmeq
->dbbuf_sq_db
= &dev
->dbbuf_dbs
[sq_idx(qid
, dev
->db_stride
)];
263 nvmeq
->dbbuf_cq_db
= &dev
->dbbuf_dbs
[cq_idx(qid
, dev
->db_stride
)];
264 nvmeq
->dbbuf_sq_ei
= &dev
->dbbuf_eis
[sq_idx(qid
, dev
->db_stride
)];
265 nvmeq
->dbbuf_cq_ei
= &dev
->dbbuf_eis
[cq_idx(qid
, dev
->db_stride
)];
268 static void nvme_dbbuf_set(struct nvme_dev
*dev
)
270 struct nvme_command c
;
275 memset(&c
, 0, sizeof(c
));
276 c
.dbbuf
.opcode
= nvme_admin_dbbuf
;
277 c
.dbbuf
.prp1
= cpu_to_le64(dev
->dbbuf_dbs_dma_addr
);
278 c
.dbbuf
.prp2
= cpu_to_le64(dev
->dbbuf_eis_dma_addr
);
280 if (nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0)) {
281 dev_warn(dev
->ctrl
.device
, "unable to set dbbuf\n");
282 /* Free memory and continue on */
283 nvme_dbbuf_dma_free(dev
);
287 static inline int nvme_dbbuf_need_event(u16 event_idx
, u16 new_idx
, u16 old
)
289 return (u16
)(new_idx
- event_idx
- 1) < (u16
)(new_idx
- old
);
292 /* Update dbbuf and return true if an MMIO is required */
293 static bool nvme_dbbuf_update_and_check_event(u16 value
, u32
*dbbuf_db
,
294 volatile u32
*dbbuf_ei
)
300 * Ensure that the queue is written before updating
301 * the doorbell in memory
305 old_value
= *dbbuf_db
;
308 if (!nvme_dbbuf_need_event(*dbbuf_ei
, value
, old_value
))
316 * Max size of iod being embedded in the request payload
318 #define NVME_INT_PAGES 2
319 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
322 * Will slightly overestimate the number of pages needed. This is OK
323 * as it only leads to a small amount of wasted memory for the lifetime of
326 static int nvme_npages(unsigned size
, struct nvme_dev
*dev
)
328 unsigned nprps
= DIV_ROUND_UP(size
+ dev
->ctrl
.page_size
,
329 dev
->ctrl
.page_size
);
330 return DIV_ROUND_UP(8 * nprps
, PAGE_SIZE
- 8);
333 static unsigned int nvme_iod_alloc_size(struct nvme_dev
*dev
,
334 unsigned int size
, unsigned int nseg
)
336 return sizeof(__le64
*) * nvme_npages(size
, dev
) +
337 sizeof(struct scatterlist
) * nseg
;
340 static unsigned int nvme_cmd_size(struct nvme_dev
*dev
)
342 return sizeof(struct nvme_iod
) +
343 nvme_iod_alloc_size(dev
, NVME_INT_BYTES(dev
), NVME_INT_PAGES
);
346 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
347 unsigned int hctx_idx
)
349 struct nvme_dev
*dev
= data
;
350 struct nvme_queue
*nvmeq
= dev
->queues
[0];
352 WARN_ON(hctx_idx
!= 0);
353 WARN_ON(dev
->admin_tagset
.tags
[0] != hctx
->tags
);
354 WARN_ON(nvmeq
->tags
);
356 hctx
->driver_data
= nvmeq
;
357 nvmeq
->tags
= &dev
->admin_tagset
.tags
[0];
361 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx
*hctx
, unsigned int hctx_idx
)
363 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
368 static int nvme_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
369 unsigned int hctx_idx
)
371 struct nvme_dev
*dev
= data
;
372 struct nvme_queue
*nvmeq
= dev
->queues
[hctx_idx
+ 1];
375 nvmeq
->tags
= &dev
->tagset
.tags
[hctx_idx
];
377 WARN_ON(dev
->tagset
.tags
[hctx_idx
] != hctx
->tags
);
378 hctx
->driver_data
= nvmeq
;
382 static int nvme_init_request(struct blk_mq_tag_set
*set
, struct request
*req
,
383 unsigned int hctx_idx
, unsigned int numa_node
)
385 struct nvme_dev
*dev
= set
->driver_data
;
386 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
387 int queue_idx
= (set
== &dev
->tagset
) ? hctx_idx
+ 1 : 0;
388 struct nvme_queue
*nvmeq
= dev
->queues
[queue_idx
];
395 static int nvme_pci_map_queues(struct blk_mq_tag_set
*set
)
397 struct nvme_dev
*dev
= set
->driver_data
;
399 return blk_mq_pci_map_queues(set
, to_pci_dev(dev
->dev
));
403 * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
404 * @nvmeq: The queue to use
405 * @cmd: The command to send
407 * Safe to use from interrupt context
409 static void __nvme_submit_cmd(struct nvme_queue
*nvmeq
,
410 struct nvme_command
*cmd
)
412 u16 tail
= nvmeq
->sq_tail
;
414 if (nvmeq
->sq_cmds_io
)
415 memcpy_toio(&nvmeq
->sq_cmds_io
[tail
], cmd
, sizeof(*cmd
));
417 memcpy(&nvmeq
->sq_cmds
[tail
], cmd
, sizeof(*cmd
));
419 if (++tail
== nvmeq
->q_depth
)
421 if (nvme_dbbuf_update_and_check_event(tail
, nvmeq
->dbbuf_sq_db
,
423 writel(tail
, nvmeq
->q_db
);
424 nvmeq
->sq_tail
= tail
;
427 static __le64
**iod_list(struct request
*req
)
429 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
430 return (__le64
**)(iod
->sg
+ blk_rq_nr_phys_segments(req
));
433 static blk_status_t
nvme_init_iod(struct request
*rq
, struct nvme_dev
*dev
)
435 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(rq
);
436 int nseg
= blk_rq_nr_phys_segments(rq
);
437 unsigned int size
= blk_rq_payload_bytes(rq
);
439 if (nseg
> NVME_INT_PAGES
|| size
> NVME_INT_BYTES(dev
)) {
440 iod
->sg
= kmalloc(nvme_iod_alloc_size(dev
, size
, nseg
), GFP_ATOMIC
);
442 return BLK_STS_RESOURCE
;
444 iod
->sg
= iod
->inline_sg
;
455 static void nvme_free_iod(struct nvme_dev
*dev
, struct request
*req
)
457 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
458 const int last_prp
= dev
->ctrl
.page_size
/ 8 - 1;
460 __le64
**list
= iod_list(req
);
461 dma_addr_t prp_dma
= iod
->first_dma
;
463 if (iod
->npages
== 0)
464 dma_pool_free(dev
->prp_small_pool
, list
[0], prp_dma
);
465 for (i
= 0; i
< iod
->npages
; i
++) {
466 __le64
*prp_list
= list
[i
];
467 dma_addr_t next_prp_dma
= le64_to_cpu(prp_list
[last_prp
]);
468 dma_pool_free(dev
->prp_page_pool
, prp_list
, prp_dma
);
469 prp_dma
= next_prp_dma
;
472 if (iod
->sg
!= iod
->inline_sg
)
476 #ifdef CONFIG_BLK_DEV_INTEGRITY
477 static void nvme_dif_prep(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
479 if (be32_to_cpu(pi
->ref_tag
) == v
)
480 pi
->ref_tag
= cpu_to_be32(p
);
483 static void nvme_dif_complete(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
485 if (be32_to_cpu(pi
->ref_tag
) == p
)
486 pi
->ref_tag
= cpu_to_be32(v
);
490 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
492 * The virtual start sector is the one that was originally submitted by the
493 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
494 * start sector may be different. Remap protection information to match the
495 * physical LBA on writes, and back to the original seed on reads.
497 * Type 0 and 3 do not have a ref tag, so no remapping required.
499 static void nvme_dif_remap(struct request
*req
,
500 void (*dif_swap
)(u32 p
, u32 v
, struct t10_pi_tuple
*pi
))
502 struct nvme_ns
*ns
= req
->rq_disk
->private_data
;
503 struct bio_integrity_payload
*bip
;
504 struct t10_pi_tuple
*pi
;
506 u32 i
, nlb
, ts
, phys
, virt
;
508 if (!ns
->pi_type
|| ns
->pi_type
== NVME_NS_DPS_PI_TYPE3
)
511 bip
= bio_integrity(req
->bio
);
515 pmap
= kmap_atomic(bip
->bip_vec
->bv_page
) + bip
->bip_vec
->bv_offset
;
518 virt
= bip_get_seed(bip
);
519 phys
= nvme_block_nr(ns
, blk_rq_pos(req
));
520 nlb
= (blk_rq_bytes(req
) >> ns
->lba_shift
);
521 ts
= ns
->disk
->queue
->integrity
.tuple_size
;
523 for (i
= 0; i
< nlb
; i
++, virt
++, phys
++) {
524 pi
= (struct t10_pi_tuple
*)p
;
525 dif_swap(phys
, virt
, pi
);
530 #else /* CONFIG_BLK_DEV_INTEGRITY */
531 static void nvme_dif_remap(struct request
*req
,
532 void (*dif_swap
)(u32 p
, u32 v
, struct t10_pi_tuple
*pi
))
535 static void nvme_dif_prep(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
538 static void nvme_dif_complete(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
543 static blk_status_t
nvme_setup_prps(struct nvme_dev
*dev
, struct request
*req
)
545 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
546 struct dma_pool
*pool
;
547 int length
= blk_rq_payload_bytes(req
);
548 struct scatterlist
*sg
= iod
->sg
;
549 int dma_len
= sg_dma_len(sg
);
550 u64 dma_addr
= sg_dma_address(sg
);
551 u32 page_size
= dev
->ctrl
.page_size
;
552 int offset
= dma_addr
& (page_size
- 1);
554 __le64
**list
= iod_list(req
);
558 length
-= (page_size
- offset
);
564 dma_len
-= (page_size
- offset
);
566 dma_addr
+= (page_size
- offset
);
569 dma_addr
= sg_dma_address(sg
);
570 dma_len
= sg_dma_len(sg
);
573 if (length
<= page_size
) {
574 iod
->first_dma
= dma_addr
;
578 nprps
= DIV_ROUND_UP(length
, page_size
);
579 if (nprps
<= (256 / 8)) {
580 pool
= dev
->prp_small_pool
;
583 pool
= dev
->prp_page_pool
;
587 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
589 iod
->first_dma
= dma_addr
;
591 return BLK_STS_RESOURCE
;
594 iod
->first_dma
= prp_dma
;
597 if (i
== page_size
>> 3) {
598 __le64
*old_prp_list
= prp_list
;
599 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
601 return BLK_STS_RESOURCE
;
602 list
[iod
->npages
++] = prp_list
;
603 prp_list
[0] = old_prp_list
[i
- 1];
604 old_prp_list
[i
- 1] = cpu_to_le64(prp_dma
);
607 prp_list
[i
++] = cpu_to_le64(dma_addr
);
608 dma_len
-= page_size
;
609 dma_addr
+= page_size
;
615 if (unlikely(dma_len
< 0))
618 dma_addr
= sg_dma_address(sg
);
619 dma_len
= sg_dma_len(sg
);
625 if (WARN_ONCE(1, "Invalid SGL for payload:%d nents:%d\n",
626 blk_rq_payload_bytes(req
), iod
->nents
)) {
627 for_each_sg(iod
->sg
, sg
, iod
->nents
, i
) {
628 dma_addr_t phys
= sg_phys(sg
);
629 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
630 "dma_address:%pad dma_length:%d\n", i
, &phys
,
631 sg
->offset
, sg
->length
,
636 return BLK_STS_IOERR
;
640 static blk_status_t
nvme_map_data(struct nvme_dev
*dev
, struct request
*req
,
641 struct nvme_command
*cmnd
)
643 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
644 struct request_queue
*q
= req
->q
;
645 enum dma_data_direction dma_dir
= rq_data_dir(req
) ?
646 DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
647 blk_status_t ret
= BLK_STS_IOERR
;
649 sg_init_table(iod
->sg
, blk_rq_nr_phys_segments(req
));
650 iod
->nents
= blk_rq_map_sg(q
, req
, iod
->sg
);
654 ret
= BLK_STS_RESOURCE
;
655 if (!dma_map_sg_attrs(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
,
659 ret
= nvme_setup_prps(dev
, req
);
660 if (ret
!= BLK_STS_OK
)
664 if (blk_integrity_rq(req
)) {
665 if (blk_rq_count_integrity_sg(q
, req
->bio
) != 1)
668 sg_init_table(&iod
->meta_sg
, 1);
669 if (blk_rq_map_integrity_sg(q
, req
->bio
, &iod
->meta_sg
) != 1)
672 if (req_op(req
) == REQ_OP_WRITE
)
673 nvme_dif_remap(req
, nvme_dif_prep
);
675 if (!dma_map_sg(dev
->dev
, &iod
->meta_sg
, 1, dma_dir
))
679 cmnd
->rw
.dptr
.prp1
= cpu_to_le64(sg_dma_address(iod
->sg
));
680 cmnd
->rw
.dptr
.prp2
= cpu_to_le64(iod
->first_dma
);
681 if (blk_integrity_rq(req
))
682 cmnd
->rw
.metadata
= cpu_to_le64(sg_dma_address(&iod
->meta_sg
));
686 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
);
691 static void nvme_unmap_data(struct nvme_dev
*dev
, struct request
*req
)
693 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
694 enum dma_data_direction dma_dir
= rq_data_dir(req
) ?
695 DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
698 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
);
699 if (blk_integrity_rq(req
)) {
700 if (req_op(req
) == REQ_OP_READ
)
701 nvme_dif_remap(req
, nvme_dif_complete
);
702 dma_unmap_sg(dev
->dev
, &iod
->meta_sg
, 1, dma_dir
);
706 nvme_cleanup_cmd(req
);
707 nvme_free_iod(dev
, req
);
711 * NOTE: ns is NULL when called on the admin queue.
713 static blk_status_t
nvme_queue_rq(struct blk_mq_hw_ctx
*hctx
,
714 const struct blk_mq_queue_data
*bd
)
716 struct nvme_ns
*ns
= hctx
->queue
->queuedata
;
717 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
718 struct nvme_dev
*dev
= nvmeq
->dev
;
719 struct request
*req
= bd
->rq
;
720 struct nvme_command cmnd
;
723 ret
= nvme_setup_cmd(ns
, req
, &cmnd
);
727 ret
= nvme_init_iod(req
, dev
);
731 if (blk_rq_nr_phys_segments(req
)) {
732 ret
= nvme_map_data(dev
, req
, &cmnd
);
734 goto out_cleanup_iod
;
737 blk_mq_start_request(req
);
739 spin_lock_irq(&nvmeq
->q_lock
);
740 if (unlikely(nvmeq
->cq_vector
< 0)) {
742 spin_unlock_irq(&nvmeq
->q_lock
);
743 goto out_cleanup_iod
;
745 __nvme_submit_cmd(nvmeq
, &cmnd
);
746 nvme_process_cq(nvmeq
);
747 spin_unlock_irq(&nvmeq
->q_lock
);
750 nvme_free_iod(dev
, req
);
752 nvme_cleanup_cmd(req
);
756 static void nvme_pci_complete_rq(struct request
*req
)
758 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
760 nvme_unmap_data(iod
->nvmeq
->dev
, req
);
761 nvme_complete_rq(req
);
764 /* We read the CQE phase first to check if the rest of the entry is valid */
765 static inline bool nvme_cqe_valid(struct nvme_queue
*nvmeq
, u16 head
,
768 return (le16_to_cpu(nvmeq
->cqes
[head
].status
) & 1) == phase
;
771 static inline void nvme_ring_cq_doorbell(struct nvme_queue
*nvmeq
)
773 u16 head
= nvmeq
->cq_head
;
775 if (likely(nvmeq
->cq_vector
>= 0)) {
776 if (nvme_dbbuf_update_and_check_event(head
, nvmeq
->dbbuf_cq_db
,
778 writel(head
, nvmeq
->q_db
+ nvmeq
->dev
->db_stride
);
782 static inline void nvme_handle_cqe(struct nvme_queue
*nvmeq
,
783 struct nvme_completion
*cqe
)
787 if (unlikely(cqe
->command_id
>= nvmeq
->q_depth
)) {
788 dev_warn(nvmeq
->dev
->ctrl
.device
,
789 "invalid id %d completed on queue %d\n",
790 cqe
->command_id
, le16_to_cpu(cqe
->sq_id
));
795 * AEN requests are special as they don't time out and can
796 * survive any kind of queue freeze and often don't respond to
797 * aborts. We don't even bother to allocate a struct request
798 * for them but rather special case them here.
800 if (unlikely(nvmeq
->qid
== 0 &&
801 cqe
->command_id
>= NVME_AQ_BLKMQ_DEPTH
)) {
802 nvme_complete_async_event(&nvmeq
->dev
->ctrl
,
803 cqe
->status
, &cqe
->result
);
808 req
= blk_mq_tag_to_rq(*nvmeq
->tags
, cqe
->command_id
);
809 nvme_end_request(req
, cqe
->status
, cqe
->result
);
812 static inline bool nvme_read_cqe(struct nvme_queue
*nvmeq
,
813 struct nvme_completion
*cqe
)
815 if (nvme_cqe_valid(nvmeq
, nvmeq
->cq_head
, nvmeq
->cq_phase
)) {
816 *cqe
= nvmeq
->cqes
[nvmeq
->cq_head
];
818 if (++nvmeq
->cq_head
== nvmeq
->q_depth
) {
820 nvmeq
->cq_phase
= !nvmeq
->cq_phase
;
827 static void nvme_process_cq(struct nvme_queue
*nvmeq
)
829 struct nvme_completion cqe
;
832 while (nvme_read_cqe(nvmeq
, &cqe
)) {
833 nvme_handle_cqe(nvmeq
, &cqe
);
838 nvme_ring_cq_doorbell(nvmeq
);
841 static irqreturn_t
nvme_irq(int irq
, void *data
)
844 struct nvme_queue
*nvmeq
= data
;
845 spin_lock(&nvmeq
->q_lock
);
846 nvme_process_cq(nvmeq
);
847 result
= nvmeq
->cqe_seen
? IRQ_HANDLED
: IRQ_NONE
;
849 spin_unlock(&nvmeq
->q_lock
);
853 static irqreturn_t
nvme_irq_check(int irq
, void *data
)
855 struct nvme_queue
*nvmeq
= data
;
856 if (nvme_cqe_valid(nvmeq
, nvmeq
->cq_head
, nvmeq
->cq_phase
))
857 return IRQ_WAKE_THREAD
;
861 static int __nvme_poll(struct nvme_queue
*nvmeq
, unsigned int tag
)
863 struct nvme_completion cqe
;
864 int found
= 0, consumed
= 0;
866 if (!nvme_cqe_valid(nvmeq
, nvmeq
->cq_head
, nvmeq
->cq_phase
))
869 spin_lock_irq(&nvmeq
->q_lock
);
870 while (nvme_read_cqe(nvmeq
, &cqe
)) {
871 nvme_handle_cqe(nvmeq
, &cqe
);
874 if (tag
== cqe
.command_id
) {
881 nvme_ring_cq_doorbell(nvmeq
);
882 spin_unlock_irq(&nvmeq
->q_lock
);
887 static int nvme_poll(struct blk_mq_hw_ctx
*hctx
, unsigned int tag
)
889 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
891 return __nvme_poll(nvmeq
, tag
);
894 static void nvme_pci_submit_async_event(struct nvme_ctrl
*ctrl
, int aer_idx
)
896 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
897 struct nvme_queue
*nvmeq
= dev
->queues
[0];
898 struct nvme_command c
;
900 memset(&c
, 0, sizeof(c
));
901 c
.common
.opcode
= nvme_admin_async_event
;
902 c
.common
.command_id
= NVME_AQ_BLKMQ_DEPTH
+ aer_idx
;
904 spin_lock_irq(&nvmeq
->q_lock
);
905 __nvme_submit_cmd(nvmeq
, &c
);
906 spin_unlock_irq(&nvmeq
->q_lock
);
909 static int adapter_delete_queue(struct nvme_dev
*dev
, u8 opcode
, u16 id
)
911 struct nvme_command c
;
913 memset(&c
, 0, sizeof(c
));
914 c
.delete_queue
.opcode
= opcode
;
915 c
.delete_queue
.qid
= cpu_to_le16(id
);
917 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
920 static int adapter_alloc_cq(struct nvme_dev
*dev
, u16 qid
,
921 struct nvme_queue
*nvmeq
)
923 struct nvme_command c
;
924 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_CQ_IRQ_ENABLED
;
927 * Note: we (ab)use the fact the the prp fields survive if no data
928 * is attached to the request.
930 memset(&c
, 0, sizeof(c
));
931 c
.create_cq
.opcode
= nvme_admin_create_cq
;
932 c
.create_cq
.prp1
= cpu_to_le64(nvmeq
->cq_dma_addr
);
933 c
.create_cq
.cqid
= cpu_to_le16(qid
);
934 c
.create_cq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
935 c
.create_cq
.cq_flags
= cpu_to_le16(flags
);
936 c
.create_cq
.irq_vector
= cpu_to_le16(nvmeq
->cq_vector
);
938 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
941 static int adapter_alloc_sq(struct nvme_dev
*dev
, u16 qid
,
942 struct nvme_queue
*nvmeq
)
944 struct nvme_command c
;
945 int flags
= NVME_QUEUE_PHYS_CONTIG
;
948 * Note: we (ab)use the fact the the prp fields survive if no data
949 * is attached to the request.
951 memset(&c
, 0, sizeof(c
));
952 c
.create_sq
.opcode
= nvme_admin_create_sq
;
953 c
.create_sq
.prp1
= cpu_to_le64(nvmeq
->sq_dma_addr
);
954 c
.create_sq
.sqid
= cpu_to_le16(qid
);
955 c
.create_sq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
956 c
.create_sq
.sq_flags
= cpu_to_le16(flags
);
957 c
.create_sq
.cqid
= cpu_to_le16(qid
);
959 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
962 static int adapter_delete_cq(struct nvme_dev
*dev
, u16 cqid
)
964 return adapter_delete_queue(dev
, nvme_admin_delete_cq
, cqid
);
967 static int adapter_delete_sq(struct nvme_dev
*dev
, u16 sqid
)
969 return adapter_delete_queue(dev
, nvme_admin_delete_sq
, sqid
);
972 static void abort_endio(struct request
*req
, blk_status_t error
)
974 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
975 struct nvme_queue
*nvmeq
= iod
->nvmeq
;
977 dev_warn(nvmeq
->dev
->ctrl
.device
,
978 "Abort status: 0x%x", nvme_req(req
)->status
);
979 atomic_inc(&nvmeq
->dev
->ctrl
.abort_limit
);
980 blk_mq_free_request(req
);
983 static bool nvme_should_reset(struct nvme_dev
*dev
, u32 csts
)
986 /* If true, indicates loss of adapter communication, possibly by a
987 * NVMe Subsystem reset.
989 bool nssro
= dev
->subsystem
&& (csts
& NVME_CSTS_NSSRO
);
991 /* If there is a reset ongoing, we shouldn't reset again. */
992 if (dev
->ctrl
.state
== NVME_CTRL_RESETTING
)
995 /* We shouldn't reset unless the controller is on fatal error state
996 * _or_ if we lost the communication with it.
998 if (!(csts
& NVME_CSTS_CFS
) && !nssro
)
1001 /* If PCI error recovery process is happening, we cannot reset or
1002 * the recovery mechanism will surely fail.
1004 if (pci_channel_offline(to_pci_dev(dev
->dev
)))
1010 static void nvme_warn_reset(struct nvme_dev
*dev
, u32 csts
)
1012 /* Read a config register to help see what died. */
1016 result
= pci_read_config_word(to_pci_dev(dev
->dev
), PCI_STATUS
,
1018 if (result
== PCIBIOS_SUCCESSFUL
)
1019 dev_warn(dev
->ctrl
.device
,
1020 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1023 dev_warn(dev
->ctrl
.device
,
1024 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1028 static enum blk_eh_timer_return
nvme_timeout(struct request
*req
, bool reserved
)
1030 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
1031 struct nvme_queue
*nvmeq
= iod
->nvmeq
;
1032 struct nvme_dev
*dev
= nvmeq
->dev
;
1033 struct request
*abort_req
;
1034 struct nvme_command cmd
;
1035 u32 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
1038 * Reset immediately if the controller is failed
1040 if (nvme_should_reset(dev
, csts
)) {
1041 nvme_warn_reset(dev
, csts
);
1042 nvme_dev_disable(dev
, false);
1043 nvme_reset_ctrl(&dev
->ctrl
);
1044 return BLK_EH_HANDLED
;
1048 * Did we miss an interrupt?
1050 if (__nvme_poll(nvmeq
, req
->tag
)) {
1051 dev_warn(dev
->ctrl
.device
,
1052 "I/O %d QID %d timeout, completion polled\n",
1053 req
->tag
, nvmeq
->qid
);
1054 return BLK_EH_HANDLED
;
1058 * Shutdown immediately if controller times out while starting. The
1059 * reset work will see the pci device disabled when it gets the forced
1060 * cancellation error. All outstanding requests are completed on
1061 * shutdown, so we return BLK_EH_HANDLED.
1063 if (dev
->ctrl
.state
== NVME_CTRL_RESETTING
) {
1064 dev_warn(dev
->ctrl
.device
,
1065 "I/O %d QID %d timeout, disable controller\n",
1066 req
->tag
, nvmeq
->qid
);
1067 nvme_dev_disable(dev
, false);
1068 nvme_req(req
)->flags
|= NVME_REQ_CANCELLED
;
1069 return BLK_EH_HANDLED
;
1073 * Shutdown the controller immediately and schedule a reset if the
1074 * command was already aborted once before and still hasn't been
1075 * returned to the driver, or if this is the admin queue.
1077 if (!nvmeq
->qid
|| iod
->aborted
) {
1078 dev_warn(dev
->ctrl
.device
,
1079 "I/O %d QID %d timeout, reset controller\n",
1080 req
->tag
, nvmeq
->qid
);
1081 nvme_dev_disable(dev
, false);
1082 nvme_reset_ctrl(&dev
->ctrl
);
1085 * Mark the request as handled, since the inline shutdown
1086 * forces all outstanding requests to complete.
1088 nvme_req(req
)->flags
|= NVME_REQ_CANCELLED
;
1089 return BLK_EH_HANDLED
;
1092 if (atomic_dec_return(&dev
->ctrl
.abort_limit
) < 0) {
1093 atomic_inc(&dev
->ctrl
.abort_limit
);
1094 return BLK_EH_RESET_TIMER
;
1098 memset(&cmd
, 0, sizeof(cmd
));
1099 cmd
.abort
.opcode
= nvme_admin_abort_cmd
;
1100 cmd
.abort
.cid
= req
->tag
;
1101 cmd
.abort
.sqid
= cpu_to_le16(nvmeq
->qid
);
1103 dev_warn(nvmeq
->dev
->ctrl
.device
,
1104 "I/O %d QID %d timeout, aborting\n",
1105 req
->tag
, nvmeq
->qid
);
1107 abort_req
= nvme_alloc_request(dev
->ctrl
.admin_q
, &cmd
,
1108 BLK_MQ_REQ_NOWAIT
, NVME_QID_ANY
);
1109 if (IS_ERR(abort_req
)) {
1110 atomic_inc(&dev
->ctrl
.abort_limit
);
1111 return BLK_EH_RESET_TIMER
;
1114 abort_req
->timeout
= ADMIN_TIMEOUT
;
1115 abort_req
->end_io_data
= NULL
;
1116 blk_execute_rq_nowait(abort_req
->q
, NULL
, abort_req
, 0, abort_endio
);
1119 * The aborted req will be completed on receiving the abort req.
1120 * We enable the timer again. If hit twice, it'll cause a device reset,
1121 * as the device then is in a faulty state.
1123 return BLK_EH_RESET_TIMER
;
1126 static void nvme_free_queue(struct nvme_queue
*nvmeq
)
1128 dma_free_coherent(nvmeq
->q_dmadev
, CQ_SIZE(nvmeq
->q_depth
),
1129 (void *)nvmeq
->cqes
, nvmeq
->cq_dma_addr
);
1131 dma_free_coherent(nvmeq
->q_dmadev
, SQ_SIZE(nvmeq
->q_depth
),
1132 nvmeq
->sq_cmds
, nvmeq
->sq_dma_addr
);
1136 static void nvme_free_queues(struct nvme_dev
*dev
, int lowest
)
1140 for (i
= dev
->ctrl
.queue_count
- 1; i
>= lowest
; i
--) {
1141 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
1142 dev
->ctrl
.queue_count
--;
1143 dev
->queues
[i
] = NULL
;
1144 nvme_free_queue(nvmeq
);
1149 * nvme_suspend_queue - put queue into suspended state
1150 * @nvmeq - queue to suspend
1152 static int nvme_suspend_queue(struct nvme_queue
*nvmeq
)
1156 spin_lock_irq(&nvmeq
->q_lock
);
1157 if (nvmeq
->cq_vector
== -1) {
1158 spin_unlock_irq(&nvmeq
->q_lock
);
1161 vector
= nvmeq
->cq_vector
;
1162 nvmeq
->dev
->online_queues
--;
1163 nvmeq
->cq_vector
= -1;
1164 spin_unlock_irq(&nvmeq
->q_lock
);
1166 if (!nvmeq
->qid
&& nvmeq
->dev
->ctrl
.admin_q
)
1167 blk_mq_quiesce_queue(nvmeq
->dev
->ctrl
.admin_q
);
1169 pci_free_irq(to_pci_dev(nvmeq
->dev
->dev
), vector
, nvmeq
);
1174 static void nvme_disable_admin_queue(struct nvme_dev
*dev
, bool shutdown
)
1176 struct nvme_queue
*nvmeq
= dev
->queues
[0];
1180 if (nvme_suspend_queue(nvmeq
))
1184 nvme_shutdown_ctrl(&dev
->ctrl
);
1186 nvme_disable_ctrl(&dev
->ctrl
, dev
->ctrl
.cap
);
1188 spin_lock_irq(&nvmeq
->q_lock
);
1189 nvme_process_cq(nvmeq
);
1190 spin_unlock_irq(&nvmeq
->q_lock
);
1193 static int nvme_cmb_qdepth(struct nvme_dev
*dev
, int nr_io_queues
,
1196 int q_depth
= dev
->q_depth
;
1197 unsigned q_size_aligned
= roundup(q_depth
* entry_size
,
1198 dev
->ctrl
.page_size
);
1200 if (q_size_aligned
* nr_io_queues
> dev
->cmb_size
) {
1201 u64 mem_per_q
= div_u64(dev
->cmb_size
, nr_io_queues
);
1202 mem_per_q
= round_down(mem_per_q
, dev
->ctrl
.page_size
);
1203 q_depth
= div_u64(mem_per_q
, entry_size
);
1206 * Ensure the reduced q_depth is above some threshold where it
1207 * would be better to map queues in system memory with the
1217 static int nvme_alloc_sq_cmds(struct nvme_dev
*dev
, struct nvme_queue
*nvmeq
,
1220 if (qid
&& dev
->cmb
&& use_cmb_sqes
&& NVME_CMB_SQS(dev
->cmbsz
)) {
1221 unsigned offset
= (qid
- 1) * roundup(SQ_SIZE(depth
),
1222 dev
->ctrl
.page_size
);
1223 nvmeq
->sq_dma_addr
= dev
->cmb_dma_addr
+ offset
;
1224 nvmeq
->sq_cmds_io
= dev
->cmb
+ offset
;
1226 nvmeq
->sq_cmds
= dma_alloc_coherent(dev
->dev
, SQ_SIZE(depth
),
1227 &nvmeq
->sq_dma_addr
, GFP_KERNEL
);
1228 if (!nvmeq
->sq_cmds
)
1235 static struct nvme_queue
*nvme_alloc_queue(struct nvme_dev
*dev
, int qid
,
1236 int depth
, int node
)
1238 struct nvme_queue
*nvmeq
= kzalloc_node(sizeof(*nvmeq
), GFP_KERNEL
,
1243 nvmeq
->cqes
= dma_zalloc_coherent(dev
->dev
, CQ_SIZE(depth
),
1244 &nvmeq
->cq_dma_addr
, GFP_KERNEL
);
1248 if (nvme_alloc_sq_cmds(dev
, nvmeq
, qid
, depth
))
1251 nvmeq
->q_dmadev
= dev
->dev
;
1253 spin_lock_init(&nvmeq
->q_lock
);
1255 nvmeq
->cq_phase
= 1;
1256 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1257 nvmeq
->q_depth
= depth
;
1259 nvmeq
->cq_vector
= -1;
1260 dev
->queues
[qid
] = nvmeq
;
1261 dev
->ctrl
.queue_count
++;
1266 dma_free_coherent(dev
->dev
, CQ_SIZE(depth
), (void *)nvmeq
->cqes
,
1267 nvmeq
->cq_dma_addr
);
1273 static int queue_request_irq(struct nvme_queue
*nvmeq
)
1275 struct pci_dev
*pdev
= to_pci_dev(nvmeq
->dev
->dev
);
1276 int nr
= nvmeq
->dev
->ctrl
.instance
;
1278 if (use_threaded_interrupts
) {
1279 return pci_request_irq(pdev
, nvmeq
->cq_vector
, nvme_irq_check
,
1280 nvme_irq
, nvmeq
, "nvme%dq%d", nr
, nvmeq
->qid
);
1282 return pci_request_irq(pdev
, nvmeq
->cq_vector
, nvme_irq
,
1283 NULL
, nvmeq
, "nvme%dq%d", nr
, nvmeq
->qid
);
1287 static void nvme_init_queue(struct nvme_queue
*nvmeq
, u16 qid
)
1289 struct nvme_dev
*dev
= nvmeq
->dev
;
1291 spin_lock_irq(&nvmeq
->q_lock
);
1294 nvmeq
->cq_phase
= 1;
1295 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1296 memset((void *)nvmeq
->cqes
, 0, CQ_SIZE(nvmeq
->q_depth
));
1297 nvme_dbbuf_init(dev
, nvmeq
, qid
);
1298 dev
->online_queues
++;
1299 spin_unlock_irq(&nvmeq
->q_lock
);
1302 static int nvme_create_queue(struct nvme_queue
*nvmeq
, int qid
)
1304 struct nvme_dev
*dev
= nvmeq
->dev
;
1307 nvmeq
->cq_vector
= qid
- 1;
1308 result
= adapter_alloc_cq(dev
, qid
, nvmeq
);
1312 result
= adapter_alloc_sq(dev
, qid
, nvmeq
);
1316 result
= queue_request_irq(nvmeq
);
1320 nvme_init_queue(nvmeq
, qid
);
1324 adapter_delete_sq(dev
, qid
);
1326 adapter_delete_cq(dev
, qid
);
1330 static const struct blk_mq_ops nvme_mq_admin_ops
= {
1331 .queue_rq
= nvme_queue_rq
,
1332 .complete
= nvme_pci_complete_rq
,
1333 .init_hctx
= nvme_admin_init_hctx
,
1334 .exit_hctx
= nvme_admin_exit_hctx
,
1335 .init_request
= nvme_init_request
,
1336 .timeout
= nvme_timeout
,
1339 static const struct blk_mq_ops nvme_mq_ops
= {
1340 .queue_rq
= nvme_queue_rq
,
1341 .complete
= nvme_pci_complete_rq
,
1342 .init_hctx
= nvme_init_hctx
,
1343 .init_request
= nvme_init_request
,
1344 .map_queues
= nvme_pci_map_queues
,
1345 .timeout
= nvme_timeout
,
1349 static void nvme_dev_remove_admin(struct nvme_dev
*dev
)
1351 if (dev
->ctrl
.admin_q
&& !blk_queue_dying(dev
->ctrl
.admin_q
)) {
1353 * If the controller was reset during removal, it's possible
1354 * user requests may be waiting on a stopped queue. Start the
1355 * queue to flush these to completion.
1357 blk_mq_unquiesce_queue(dev
->ctrl
.admin_q
);
1358 blk_cleanup_queue(dev
->ctrl
.admin_q
);
1359 blk_mq_free_tag_set(&dev
->admin_tagset
);
1363 static int nvme_alloc_admin_tags(struct nvme_dev
*dev
)
1365 if (!dev
->ctrl
.admin_q
) {
1366 dev
->admin_tagset
.ops
= &nvme_mq_admin_ops
;
1367 dev
->admin_tagset
.nr_hw_queues
= 1;
1370 * Subtract one to leave an empty queue entry for 'Full Queue'
1371 * condition. See NVM-Express 1.2 specification, section 4.1.2.
1373 dev
->admin_tagset
.queue_depth
= NVME_AQ_BLKMQ_DEPTH
- 1;
1374 dev
->admin_tagset
.timeout
= ADMIN_TIMEOUT
;
1375 dev
->admin_tagset
.numa_node
= dev_to_node(dev
->dev
);
1376 dev
->admin_tagset
.cmd_size
= nvme_cmd_size(dev
);
1377 dev
->admin_tagset
.flags
= BLK_MQ_F_NO_SCHED
;
1378 dev
->admin_tagset
.driver_data
= dev
;
1380 if (blk_mq_alloc_tag_set(&dev
->admin_tagset
))
1382 dev
->ctrl
.admin_tagset
= &dev
->admin_tagset
;
1384 dev
->ctrl
.admin_q
= blk_mq_init_queue(&dev
->admin_tagset
);
1385 if (IS_ERR(dev
->ctrl
.admin_q
)) {
1386 blk_mq_free_tag_set(&dev
->admin_tagset
);
1389 if (!blk_get_queue(dev
->ctrl
.admin_q
)) {
1390 nvme_dev_remove_admin(dev
);
1391 dev
->ctrl
.admin_q
= NULL
;
1395 blk_mq_unquiesce_queue(dev
->ctrl
.admin_q
);
1400 static unsigned long db_bar_size(struct nvme_dev
*dev
, unsigned nr_io_queues
)
1402 return NVME_REG_DBS
+ ((nr_io_queues
+ 1) * 8 * dev
->db_stride
);
1405 static int nvme_remap_bar(struct nvme_dev
*dev
, unsigned long size
)
1407 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1409 if (size
<= dev
->bar_mapped_size
)
1411 if (size
> pci_resource_len(pdev
, 0))
1415 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), size
);
1417 dev
->bar_mapped_size
= 0;
1420 dev
->bar_mapped_size
= size
;
1421 dev
->dbs
= dev
->bar
+ NVME_REG_DBS
;
1426 static int nvme_pci_configure_admin_queue(struct nvme_dev
*dev
)
1430 struct nvme_queue
*nvmeq
;
1432 result
= nvme_remap_bar(dev
, db_bar_size(dev
, 0));
1436 dev
->subsystem
= readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 1, 0) ?
1437 NVME_CAP_NSSRC(dev
->ctrl
.cap
) : 0;
1439 if (dev
->subsystem
&&
1440 (readl(dev
->bar
+ NVME_REG_CSTS
) & NVME_CSTS_NSSRO
))
1441 writel(NVME_CSTS_NSSRO
, dev
->bar
+ NVME_REG_CSTS
);
1443 result
= nvme_disable_ctrl(&dev
->ctrl
, dev
->ctrl
.cap
);
1447 nvmeq
= dev
->queues
[0];
1449 nvmeq
= nvme_alloc_queue(dev
, 0, NVME_AQ_DEPTH
,
1450 dev_to_node(dev
->dev
));
1455 aqa
= nvmeq
->q_depth
- 1;
1458 writel(aqa
, dev
->bar
+ NVME_REG_AQA
);
1459 lo_hi_writeq(nvmeq
->sq_dma_addr
, dev
->bar
+ NVME_REG_ASQ
);
1460 lo_hi_writeq(nvmeq
->cq_dma_addr
, dev
->bar
+ NVME_REG_ACQ
);
1462 result
= nvme_enable_ctrl(&dev
->ctrl
, dev
->ctrl
.cap
);
1466 nvmeq
->cq_vector
= 0;
1467 result
= queue_request_irq(nvmeq
);
1469 nvmeq
->cq_vector
= -1;
1476 static int nvme_create_io_queues(struct nvme_dev
*dev
)
1481 for (i
= dev
->ctrl
.queue_count
; i
<= dev
->max_qid
; i
++) {
1482 /* vector == qid - 1, match nvme_create_queue */
1483 if (!nvme_alloc_queue(dev
, i
, dev
->q_depth
,
1484 pci_irq_get_node(to_pci_dev(dev
->dev
), i
- 1))) {
1490 max
= min(dev
->max_qid
, dev
->ctrl
.queue_count
- 1);
1491 for (i
= dev
->online_queues
; i
<= max
; i
++) {
1492 ret
= nvme_create_queue(dev
->queues
[i
], i
);
1498 * Ignore failing Create SQ/CQ commands, we can continue with less
1499 * than the desired aount of queues, and even a controller without
1500 * I/O queues an still be used to issue admin commands. This might
1501 * be useful to upgrade a buggy firmware for example.
1503 return ret
>= 0 ? 0 : ret
;
1506 static ssize_t
nvme_cmb_show(struct device
*dev
,
1507 struct device_attribute
*attr
,
1510 struct nvme_dev
*ndev
= to_nvme_dev(dev_get_drvdata(dev
));
1512 return scnprintf(buf
, PAGE_SIZE
, "cmbloc : x%08x\ncmbsz : x%08x\n",
1513 ndev
->cmbloc
, ndev
->cmbsz
);
1515 static DEVICE_ATTR(cmb
, S_IRUGO
, nvme_cmb_show
, NULL
);
1517 static void __iomem
*nvme_map_cmb(struct nvme_dev
*dev
)
1519 u64 szu
, size
, offset
;
1520 resource_size_t bar_size
;
1521 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1523 dma_addr_t dma_addr
;
1525 dev
->cmbsz
= readl(dev
->bar
+ NVME_REG_CMBSZ
);
1526 if (!(NVME_CMB_SZ(dev
->cmbsz
)))
1528 dev
->cmbloc
= readl(dev
->bar
+ NVME_REG_CMBLOC
);
1533 szu
= (u64
)1 << (12 + 4 * NVME_CMB_SZU(dev
->cmbsz
));
1534 size
= szu
* NVME_CMB_SZ(dev
->cmbsz
);
1535 offset
= szu
* NVME_CMB_OFST(dev
->cmbloc
);
1536 bar_size
= pci_resource_len(pdev
, NVME_CMB_BIR(dev
->cmbloc
));
1538 if (offset
> bar_size
)
1542 * Controllers may support a CMB size larger than their BAR,
1543 * for example, due to being behind a bridge. Reduce the CMB to
1544 * the reported size of the BAR
1546 if (size
> bar_size
- offset
)
1547 size
= bar_size
- offset
;
1549 dma_addr
= pci_resource_start(pdev
, NVME_CMB_BIR(dev
->cmbloc
)) + offset
;
1550 cmb
= ioremap_wc(dma_addr
, size
);
1554 dev
->cmb_dma_addr
= dma_addr
;
1555 dev
->cmb_size
= size
;
1559 static inline void nvme_release_cmb(struct nvme_dev
*dev
)
1564 sysfs_remove_file_from_group(&dev
->ctrl
.device
->kobj
,
1565 &dev_attr_cmb
.attr
, NULL
);
1570 static int nvme_set_host_mem(struct nvme_dev
*dev
, u32 bits
)
1572 u64 dma_addr
= dev
->host_mem_descs_dma
;
1573 struct nvme_command c
;
1576 memset(&c
, 0, sizeof(c
));
1577 c
.features
.opcode
= nvme_admin_set_features
;
1578 c
.features
.fid
= cpu_to_le32(NVME_FEAT_HOST_MEM_BUF
);
1579 c
.features
.dword11
= cpu_to_le32(bits
);
1580 c
.features
.dword12
= cpu_to_le32(dev
->host_mem_size
>>
1581 ilog2(dev
->ctrl
.page_size
));
1582 c
.features
.dword13
= cpu_to_le32(lower_32_bits(dma_addr
));
1583 c
.features
.dword14
= cpu_to_le32(upper_32_bits(dma_addr
));
1584 c
.features
.dword15
= cpu_to_le32(dev
->nr_host_mem_descs
);
1586 ret
= nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
1588 dev_warn(dev
->ctrl
.device
,
1589 "failed to set host mem (err %d, flags %#x).\n",
1595 static void nvme_free_host_mem(struct nvme_dev
*dev
)
1599 for (i
= 0; i
< dev
->nr_host_mem_descs
; i
++) {
1600 struct nvme_host_mem_buf_desc
*desc
= &dev
->host_mem_descs
[i
];
1601 size_t size
= le32_to_cpu(desc
->size
) * dev
->ctrl
.page_size
;
1603 dma_free_coherent(dev
->dev
, size
, dev
->host_mem_desc_bufs
[i
],
1604 le64_to_cpu(desc
->addr
));
1607 kfree(dev
->host_mem_desc_bufs
);
1608 dev
->host_mem_desc_bufs
= NULL
;
1609 dma_free_coherent(dev
->dev
,
1610 dev
->nr_host_mem_descs
* sizeof(*dev
->host_mem_descs
),
1611 dev
->host_mem_descs
, dev
->host_mem_descs_dma
);
1612 dev
->host_mem_descs
= NULL
;
1615 static int nvme_alloc_host_mem(struct nvme_dev
*dev
, u64 min
, u64 preferred
)
1617 struct nvme_host_mem_buf_desc
*descs
;
1618 u32 chunk_size
, max_entries
, len
;
1619 dma_addr_t descs_dma
;
1624 /* start big and work our way down */
1625 chunk_size
= min(preferred
, (u64
)PAGE_SIZE
<< MAX_ORDER
);
1627 tmp
= (preferred
+ chunk_size
- 1);
1628 do_div(tmp
, chunk_size
);
1630 descs
= dma_zalloc_coherent(dev
->dev
, max_entries
* sizeof(*descs
),
1631 &descs_dma
, GFP_KERNEL
);
1635 bufs
= kcalloc(max_entries
, sizeof(*bufs
), GFP_KERNEL
);
1637 goto out_free_descs
;
1639 for (size
= 0; size
< preferred
; size
+= len
) {
1640 dma_addr_t dma_addr
;
1642 len
= min_t(u64
, chunk_size
, preferred
- size
);
1643 bufs
[i
] = dma_alloc_attrs(dev
->dev
, len
, &dma_addr
, GFP_KERNEL
,
1644 DMA_ATTR_NO_KERNEL_MAPPING
| DMA_ATTR_NO_WARN
);
1648 descs
[i
].addr
= cpu_to_le64(dma_addr
);
1649 descs
[i
].size
= cpu_to_le32(len
/ dev
->ctrl
.page_size
);
1653 if (!size
|| (min
&& size
< min
)) {
1654 dev_warn(dev
->ctrl
.device
,
1655 "failed to allocate host memory buffer.\n");
1659 dev_info(dev
->ctrl
.device
,
1660 "allocated %lld MiB host memory buffer.\n",
1661 size
>> ilog2(SZ_1M
));
1662 dev
->nr_host_mem_descs
= i
;
1663 dev
->host_mem_size
= size
;
1664 dev
->host_mem_descs
= descs
;
1665 dev
->host_mem_descs_dma
= descs_dma
;
1666 dev
->host_mem_desc_bufs
= bufs
;
1671 size_t size
= le32_to_cpu(descs
[i
].size
) * dev
->ctrl
.page_size
;
1673 dma_free_coherent(dev
->dev
, size
, bufs
[i
],
1674 le64_to_cpu(descs
[i
].addr
));
1679 dma_free_coherent(dev
->dev
, max_entries
* sizeof(*descs
), descs
,
1682 /* try a smaller chunk size if we failed early */
1683 if (chunk_size
>= PAGE_SIZE
* 2 && (i
== 0 || size
< min
)) {
1687 dev
->host_mem_descs
= NULL
;
1691 static void nvme_setup_host_mem(struct nvme_dev
*dev
)
1693 u64 max
= (u64
)max_host_mem_size_mb
* SZ_1M
;
1694 u64 preferred
= (u64
)dev
->ctrl
.hmpre
* 4096;
1695 u64 min
= (u64
)dev
->ctrl
.hmmin
* 4096;
1696 u32 enable_bits
= NVME_HOST_MEM_ENABLE
;
1698 preferred
= min(preferred
, max
);
1700 dev_warn(dev
->ctrl
.device
,
1701 "min host memory (%lld MiB) above limit (%d MiB).\n",
1702 min
>> ilog2(SZ_1M
), max_host_mem_size_mb
);
1703 nvme_free_host_mem(dev
);
1708 * If we already have a buffer allocated check if we can reuse it.
1710 if (dev
->host_mem_descs
) {
1711 if (dev
->host_mem_size
>= min
)
1712 enable_bits
|= NVME_HOST_MEM_RETURN
;
1714 nvme_free_host_mem(dev
);
1717 if (!dev
->host_mem_descs
) {
1718 if (nvme_alloc_host_mem(dev
, min
, preferred
))
1722 if (nvme_set_host_mem(dev
, enable_bits
))
1723 nvme_free_host_mem(dev
);
1726 static int nvme_setup_io_queues(struct nvme_dev
*dev
)
1728 struct nvme_queue
*adminq
= dev
->queues
[0];
1729 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1730 int result
, nr_io_queues
;
1733 nr_io_queues
= num_present_cpus();
1734 result
= nvme_set_queue_count(&dev
->ctrl
, &nr_io_queues
);
1738 if (nr_io_queues
== 0)
1741 if (dev
->cmb
&& NVME_CMB_SQS(dev
->cmbsz
)) {
1742 result
= nvme_cmb_qdepth(dev
, nr_io_queues
,
1743 sizeof(struct nvme_command
));
1745 dev
->q_depth
= result
;
1747 nvme_release_cmb(dev
);
1751 size
= db_bar_size(dev
, nr_io_queues
);
1752 result
= nvme_remap_bar(dev
, size
);
1755 if (!--nr_io_queues
)
1758 adminq
->q_db
= dev
->dbs
;
1760 /* Deregister the admin queue's interrupt */
1761 pci_free_irq(pdev
, 0, adminq
);
1764 * If we enable msix early due to not intx, disable it again before
1765 * setting up the full range we need.
1767 pci_free_irq_vectors(pdev
);
1768 nr_io_queues
= pci_alloc_irq_vectors(pdev
, 1, nr_io_queues
,
1769 PCI_IRQ_ALL_TYPES
| PCI_IRQ_AFFINITY
);
1770 if (nr_io_queues
<= 0)
1772 dev
->max_qid
= nr_io_queues
;
1775 * Should investigate if there's a performance win from allocating
1776 * more queues than interrupt vectors; it might allow the submission
1777 * path to scale better, even if the receive path is limited by the
1778 * number of interrupts.
1781 result
= queue_request_irq(adminq
);
1783 adminq
->cq_vector
= -1;
1786 return nvme_create_io_queues(dev
);
1789 static void nvme_del_queue_end(struct request
*req
, blk_status_t error
)
1791 struct nvme_queue
*nvmeq
= req
->end_io_data
;
1793 blk_mq_free_request(req
);
1794 complete(&nvmeq
->dev
->ioq_wait
);
1797 static void nvme_del_cq_end(struct request
*req
, blk_status_t error
)
1799 struct nvme_queue
*nvmeq
= req
->end_io_data
;
1802 unsigned long flags
;
1805 * We might be called with the AQ q_lock held
1806 * and the I/O queue q_lock should always
1807 * nest inside the AQ one.
1809 spin_lock_irqsave_nested(&nvmeq
->q_lock
, flags
,
1810 SINGLE_DEPTH_NESTING
);
1811 nvme_process_cq(nvmeq
);
1812 spin_unlock_irqrestore(&nvmeq
->q_lock
, flags
);
1815 nvme_del_queue_end(req
, error
);
1818 static int nvme_delete_queue(struct nvme_queue
*nvmeq
, u8 opcode
)
1820 struct request_queue
*q
= nvmeq
->dev
->ctrl
.admin_q
;
1821 struct request
*req
;
1822 struct nvme_command cmd
;
1824 memset(&cmd
, 0, sizeof(cmd
));
1825 cmd
.delete_queue
.opcode
= opcode
;
1826 cmd
.delete_queue
.qid
= cpu_to_le16(nvmeq
->qid
);
1828 req
= nvme_alloc_request(q
, &cmd
, BLK_MQ_REQ_NOWAIT
, NVME_QID_ANY
);
1830 return PTR_ERR(req
);
1832 req
->timeout
= ADMIN_TIMEOUT
;
1833 req
->end_io_data
= nvmeq
;
1835 blk_execute_rq_nowait(q
, NULL
, req
, false,
1836 opcode
== nvme_admin_delete_cq
?
1837 nvme_del_cq_end
: nvme_del_queue_end
);
1841 static void nvme_disable_io_queues(struct nvme_dev
*dev
, int queues
)
1844 unsigned long timeout
;
1845 u8 opcode
= nvme_admin_delete_sq
;
1847 for (pass
= 0; pass
< 2; pass
++) {
1848 int sent
= 0, i
= queues
;
1850 reinit_completion(&dev
->ioq_wait
);
1852 timeout
= ADMIN_TIMEOUT
;
1853 for (; i
> 0; i
--, sent
++)
1854 if (nvme_delete_queue(dev
->queues
[i
], opcode
))
1858 timeout
= wait_for_completion_io_timeout(&dev
->ioq_wait
, timeout
);
1864 opcode
= nvme_admin_delete_cq
;
1869 * Return: error value if an error occurred setting up the queues or calling
1870 * Identify Device. 0 if these succeeded, even if adding some of the
1871 * namespaces failed. At the moment, these failures are silent. TBD which
1872 * failures should be reported.
1874 static int nvme_dev_add(struct nvme_dev
*dev
)
1876 if (!dev
->ctrl
.tagset
) {
1877 dev
->tagset
.ops
= &nvme_mq_ops
;
1878 dev
->tagset
.nr_hw_queues
= dev
->online_queues
- 1;
1879 dev
->tagset
.timeout
= NVME_IO_TIMEOUT
;
1880 dev
->tagset
.numa_node
= dev_to_node(dev
->dev
);
1881 dev
->tagset
.queue_depth
=
1882 min_t(int, dev
->q_depth
, BLK_MQ_MAX_DEPTH
) - 1;
1883 dev
->tagset
.cmd_size
= nvme_cmd_size(dev
);
1884 dev
->tagset
.flags
= BLK_MQ_F_SHOULD_MERGE
;
1885 dev
->tagset
.driver_data
= dev
;
1887 if (blk_mq_alloc_tag_set(&dev
->tagset
))
1889 dev
->ctrl
.tagset
= &dev
->tagset
;
1891 nvme_dbbuf_set(dev
);
1893 blk_mq_update_nr_hw_queues(&dev
->tagset
, dev
->online_queues
- 1);
1895 /* Free previously allocated queues that are no longer usable */
1896 nvme_free_queues(dev
, dev
->online_queues
);
1902 static int nvme_pci_enable(struct nvme_dev
*dev
)
1904 int result
= -ENOMEM
;
1905 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1907 if (pci_enable_device_mem(pdev
))
1910 pci_set_master(pdev
);
1912 if (dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(64)) &&
1913 dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(32)))
1916 if (readl(dev
->bar
+ NVME_REG_CSTS
) == -1) {
1922 * Some devices and/or platforms don't advertise or work with INTx
1923 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
1924 * adjust this later.
1926 result
= pci_alloc_irq_vectors(pdev
, 1, 1, PCI_IRQ_ALL_TYPES
);
1930 dev
->ctrl
.cap
= lo_hi_readq(dev
->bar
+ NVME_REG_CAP
);
1932 dev
->q_depth
= min_t(int, NVME_CAP_MQES(dev
->ctrl
.cap
) + 1,
1934 dev
->db_stride
= 1 << NVME_CAP_STRIDE(dev
->ctrl
.cap
);
1935 dev
->dbs
= dev
->bar
+ 4096;
1938 * Temporary fix for the Apple controller found in the MacBook8,1 and
1939 * some MacBook7,1 to avoid controller resets and data loss.
1941 if (pdev
->vendor
== PCI_VENDOR_ID_APPLE
&& pdev
->device
== 0x2001) {
1943 dev_warn(dev
->ctrl
.device
, "detected Apple NVMe controller, "
1944 "set queue depth=%u to work around controller resets\n",
1946 } else if (pdev
->vendor
== PCI_VENDOR_ID_SAMSUNG
&&
1947 (pdev
->device
== 0xa821 || pdev
->device
== 0xa822) &&
1948 NVME_CAP_MQES(dev
->ctrl
.cap
) == 0) {
1950 dev_err(dev
->ctrl
.device
, "detected PM1725 NVMe controller, "
1951 "set queue depth=%u\n", dev
->q_depth
);
1955 * CMBs can currently only exist on >=1.2 PCIe devices. We only
1956 * populate sysfs if a CMB is implemented. Since nvme_dev_attrs_group
1957 * has no name we can pass NULL as final argument to
1958 * sysfs_add_file_to_group.
1961 if (readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 2, 0)) {
1962 dev
->cmb
= nvme_map_cmb(dev
);
1964 if (sysfs_add_file_to_group(&dev
->ctrl
.device
->kobj
,
1965 &dev_attr_cmb
.attr
, NULL
))
1966 dev_warn(dev
->ctrl
.device
,
1967 "failed to add sysfs attribute for CMB\n");
1971 pci_enable_pcie_error_reporting(pdev
);
1972 pci_save_state(pdev
);
1976 pci_disable_device(pdev
);
1980 static void nvme_dev_unmap(struct nvme_dev
*dev
)
1984 pci_release_mem_regions(to_pci_dev(dev
->dev
));
1987 static void nvme_pci_disable(struct nvme_dev
*dev
)
1989 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1991 nvme_release_cmb(dev
);
1992 pci_free_irq_vectors(pdev
);
1994 if (pci_is_enabled(pdev
)) {
1995 pci_disable_pcie_error_reporting(pdev
);
1996 pci_disable_device(pdev
);
2000 static void nvme_dev_disable(struct nvme_dev
*dev
, bool shutdown
)
2004 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2006 mutex_lock(&dev
->shutdown_lock
);
2007 if (pci_is_enabled(pdev
)) {
2008 u32 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
2010 if (dev
->ctrl
.state
== NVME_CTRL_LIVE
||
2011 dev
->ctrl
.state
== NVME_CTRL_RESETTING
)
2012 nvme_start_freeze(&dev
->ctrl
);
2013 dead
= !!((csts
& NVME_CSTS_CFS
) || !(csts
& NVME_CSTS_RDY
) ||
2014 pdev
->error_state
!= pci_channel_io_normal
);
2018 * Give the controller a chance to complete all entered requests if
2019 * doing a safe shutdown.
2023 nvme_wait_freeze_timeout(&dev
->ctrl
, NVME_IO_TIMEOUT
);
2026 * If the controller is still alive tell it to stop using the
2027 * host memory buffer. In theory the shutdown / reset should
2028 * make sure that it doesn't access the host memoery anymore,
2029 * but I'd rather be safe than sorry..
2031 if (dev
->host_mem_descs
)
2032 nvme_set_host_mem(dev
, 0);
2035 nvme_stop_queues(&dev
->ctrl
);
2037 queues
= dev
->online_queues
- 1;
2038 for (i
= dev
->ctrl
.queue_count
- 1; i
> 0; i
--)
2039 nvme_suspend_queue(dev
->queues
[i
]);
2042 /* A device might become IO incapable very soon during
2043 * probe, before the admin queue is configured. Thus,
2044 * queue_count can be 0 here.
2046 if (dev
->ctrl
.queue_count
)
2047 nvme_suspend_queue(dev
->queues
[0]);
2049 nvme_disable_io_queues(dev
, queues
);
2050 nvme_disable_admin_queue(dev
, shutdown
);
2052 nvme_pci_disable(dev
);
2054 blk_mq_tagset_busy_iter(&dev
->tagset
, nvme_cancel_request
, &dev
->ctrl
);
2055 blk_mq_tagset_busy_iter(&dev
->admin_tagset
, nvme_cancel_request
, &dev
->ctrl
);
2058 * The driver will not be starting up queues again if shutting down so
2059 * must flush all entered requests to their failed completion to avoid
2060 * deadlocking blk-mq hot-cpu notifier.
2063 nvme_start_queues(&dev
->ctrl
);
2064 mutex_unlock(&dev
->shutdown_lock
);
2067 static int nvme_setup_prp_pools(struct nvme_dev
*dev
)
2069 dev
->prp_page_pool
= dma_pool_create("prp list page", dev
->dev
,
2070 PAGE_SIZE
, PAGE_SIZE
, 0);
2071 if (!dev
->prp_page_pool
)
2074 /* Optimisation for I/Os between 4k and 128k */
2075 dev
->prp_small_pool
= dma_pool_create("prp list 256", dev
->dev
,
2077 if (!dev
->prp_small_pool
) {
2078 dma_pool_destroy(dev
->prp_page_pool
);
2084 static void nvme_release_prp_pools(struct nvme_dev
*dev
)
2086 dma_pool_destroy(dev
->prp_page_pool
);
2087 dma_pool_destroy(dev
->prp_small_pool
);
2090 static void nvme_pci_free_ctrl(struct nvme_ctrl
*ctrl
)
2092 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
2094 nvme_dbbuf_dma_free(dev
);
2095 put_device(dev
->dev
);
2096 if (dev
->tagset
.tags
)
2097 blk_mq_free_tag_set(&dev
->tagset
);
2098 if (dev
->ctrl
.admin_q
)
2099 blk_put_queue(dev
->ctrl
.admin_q
);
2101 free_opal_dev(dev
->ctrl
.opal_dev
);
2105 static void nvme_remove_dead_ctrl(struct nvme_dev
*dev
, int status
)
2107 dev_warn(dev
->ctrl
.device
, "Removing after probe failure status: %d\n", status
);
2109 kref_get(&dev
->ctrl
.kref
);
2110 nvme_dev_disable(dev
, false);
2111 if (!schedule_work(&dev
->remove_work
))
2112 nvme_put_ctrl(&dev
->ctrl
);
2115 static void nvme_reset_work(struct work_struct
*work
)
2117 struct nvme_dev
*dev
=
2118 container_of(work
, struct nvme_dev
, ctrl
.reset_work
);
2119 bool was_suspend
= !!(dev
->ctrl
.ctrl_config
& NVME_CC_SHN_NORMAL
);
2120 int result
= -ENODEV
;
2122 if (WARN_ON(dev
->ctrl
.state
!= NVME_CTRL_RESETTING
))
2126 * If we're called to reset a live controller first shut it down before
2129 if (dev
->ctrl
.ctrl_config
& NVME_CC_ENABLE
)
2130 nvme_dev_disable(dev
, false);
2132 result
= nvme_pci_enable(dev
);
2136 result
= nvme_pci_configure_admin_queue(dev
);
2140 nvme_init_queue(dev
->queues
[0], 0);
2141 result
= nvme_alloc_admin_tags(dev
);
2145 result
= nvme_init_identify(&dev
->ctrl
);
2149 if (dev
->ctrl
.oacs
& NVME_CTRL_OACS_SEC_SUPP
) {
2150 if (!dev
->ctrl
.opal_dev
)
2151 dev
->ctrl
.opal_dev
=
2152 init_opal_dev(&dev
->ctrl
, &nvme_sec_submit
);
2153 else if (was_suspend
)
2154 opal_unlock_from_suspend(dev
->ctrl
.opal_dev
);
2156 free_opal_dev(dev
->ctrl
.opal_dev
);
2157 dev
->ctrl
.opal_dev
= NULL
;
2160 if (dev
->ctrl
.oacs
& NVME_CTRL_OACS_DBBUF_SUPP
) {
2161 result
= nvme_dbbuf_dma_alloc(dev
);
2164 "unable to allocate dma for dbbuf\n");
2167 if (dev
->ctrl
.hmpre
)
2168 nvme_setup_host_mem(dev
);
2170 result
= nvme_setup_io_queues(dev
);
2175 * Keep the controller around but remove all namespaces if we don't have
2176 * any working I/O queue.
2178 if (dev
->online_queues
< 2) {
2179 dev_warn(dev
->ctrl
.device
, "IO queues not created\n");
2180 nvme_kill_queues(&dev
->ctrl
);
2181 nvme_remove_namespaces(&dev
->ctrl
);
2183 nvme_start_queues(&dev
->ctrl
);
2184 nvme_wait_freeze(&dev
->ctrl
);
2186 nvme_unfreeze(&dev
->ctrl
);
2189 if (!nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_LIVE
)) {
2190 dev_warn(dev
->ctrl
.device
, "failed to mark controller live\n");
2194 nvme_start_ctrl(&dev
->ctrl
);
2198 nvme_remove_dead_ctrl(dev
, result
);
2201 static void nvme_remove_dead_ctrl_work(struct work_struct
*work
)
2203 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, remove_work
);
2204 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2206 nvme_kill_queues(&dev
->ctrl
);
2207 if (pci_get_drvdata(pdev
))
2208 device_release_driver(&pdev
->dev
);
2209 nvme_put_ctrl(&dev
->ctrl
);
2212 static int nvme_pci_reg_read32(struct nvme_ctrl
*ctrl
, u32 off
, u32
*val
)
2214 *val
= readl(to_nvme_dev(ctrl
)->bar
+ off
);
2218 static int nvme_pci_reg_write32(struct nvme_ctrl
*ctrl
, u32 off
, u32 val
)
2220 writel(val
, to_nvme_dev(ctrl
)->bar
+ off
);
2224 static int nvme_pci_reg_read64(struct nvme_ctrl
*ctrl
, u32 off
, u64
*val
)
2226 *val
= readq(to_nvme_dev(ctrl
)->bar
+ off
);
2230 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops
= {
2232 .module
= THIS_MODULE
,
2233 .flags
= NVME_F_METADATA_SUPPORTED
,
2234 .reg_read32
= nvme_pci_reg_read32
,
2235 .reg_write32
= nvme_pci_reg_write32
,
2236 .reg_read64
= nvme_pci_reg_read64
,
2237 .free_ctrl
= nvme_pci_free_ctrl
,
2238 .submit_async_event
= nvme_pci_submit_async_event
,
2241 static int nvme_dev_map(struct nvme_dev
*dev
)
2243 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2245 if (pci_request_mem_regions(pdev
, "nvme"))
2248 if (nvme_remap_bar(dev
, NVME_REG_DBS
+ 4096))
2253 pci_release_mem_regions(pdev
);
2257 static unsigned long check_dell_samsung_bug(struct pci_dev
*pdev
)
2259 if (pdev
->vendor
== 0x144d && pdev
->device
== 0xa802) {
2261 * Several Samsung devices seem to drop off the PCIe bus
2262 * randomly when APST is on and uses the deepest sleep state.
2263 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2264 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2265 * 950 PRO 256GB", but it seems to be restricted to two Dell
2268 if (dmi_match(DMI_SYS_VENDOR
, "Dell Inc.") &&
2269 (dmi_match(DMI_PRODUCT_NAME
, "XPS 15 9550") ||
2270 dmi_match(DMI_PRODUCT_NAME
, "Precision 5510")))
2271 return NVME_QUIRK_NO_DEEPEST_PS
;
2277 static int nvme_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
2279 int node
, result
= -ENOMEM
;
2280 struct nvme_dev
*dev
;
2281 unsigned long quirks
= id
->driver_data
;
2283 node
= dev_to_node(&pdev
->dev
);
2284 if (node
== NUMA_NO_NODE
)
2285 set_dev_node(&pdev
->dev
, first_memory_node
);
2287 dev
= kzalloc_node(sizeof(*dev
), GFP_KERNEL
, node
);
2290 dev
->queues
= kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2295 dev
->dev
= get_device(&pdev
->dev
);
2296 pci_set_drvdata(pdev
, dev
);
2298 result
= nvme_dev_map(dev
);
2302 INIT_WORK(&dev
->ctrl
.reset_work
, nvme_reset_work
);
2303 INIT_WORK(&dev
->remove_work
, nvme_remove_dead_ctrl_work
);
2304 mutex_init(&dev
->shutdown_lock
);
2305 init_completion(&dev
->ioq_wait
);
2307 result
= nvme_setup_prp_pools(dev
);
2311 quirks
|= check_dell_samsung_bug(pdev
);
2313 result
= nvme_init_ctrl(&dev
->ctrl
, &pdev
->dev
, &nvme_pci_ctrl_ops
,
2318 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_RESETTING
);
2319 dev_info(dev
->ctrl
.device
, "pci function %s\n", dev_name(&pdev
->dev
));
2321 queue_work(nvme_wq
, &dev
->ctrl
.reset_work
);
2325 nvme_release_prp_pools(dev
);
2327 nvme_dev_unmap(dev
);
2329 put_device(dev
->dev
);
2336 static void nvme_reset_prepare(struct pci_dev
*pdev
)
2338 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2339 nvme_dev_disable(dev
, false);
2342 static void nvme_reset_done(struct pci_dev
*pdev
)
2344 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2345 nvme_reset_ctrl(&dev
->ctrl
);
2348 static void nvme_shutdown(struct pci_dev
*pdev
)
2350 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2351 nvme_dev_disable(dev
, true);
2355 * The driver's remove may be called on a device in a partially initialized
2356 * state. This function must not have any dependencies on the device state in
2359 static void nvme_remove(struct pci_dev
*pdev
)
2361 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2363 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_DELETING
);
2365 cancel_work_sync(&dev
->ctrl
.reset_work
);
2366 pci_set_drvdata(pdev
, NULL
);
2368 if (!pci_device_is_present(pdev
)) {
2369 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_DEAD
);
2370 nvme_dev_disable(dev
, false);
2373 flush_work(&dev
->ctrl
.reset_work
);
2374 nvme_stop_ctrl(&dev
->ctrl
);
2375 nvme_remove_namespaces(&dev
->ctrl
);
2376 nvme_dev_disable(dev
, true);
2377 nvme_free_host_mem(dev
);
2378 nvme_dev_remove_admin(dev
);
2379 nvme_free_queues(dev
, 0);
2380 nvme_uninit_ctrl(&dev
->ctrl
);
2381 nvme_release_prp_pools(dev
);
2382 nvme_dev_unmap(dev
);
2383 nvme_put_ctrl(&dev
->ctrl
);
2386 static int nvme_pci_sriov_configure(struct pci_dev
*pdev
, int numvfs
)
2391 if (pci_vfs_assigned(pdev
)) {
2392 dev_warn(&pdev
->dev
,
2393 "Cannot disable SR-IOV VFs while assigned\n");
2396 pci_disable_sriov(pdev
);
2400 ret
= pci_enable_sriov(pdev
, numvfs
);
2401 return ret
? ret
: numvfs
;
2404 #ifdef CONFIG_PM_SLEEP
2405 static int nvme_suspend(struct device
*dev
)
2407 struct pci_dev
*pdev
= to_pci_dev(dev
);
2408 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2410 nvme_dev_disable(ndev
, true);
2414 static int nvme_resume(struct device
*dev
)
2416 struct pci_dev
*pdev
= to_pci_dev(dev
);
2417 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2419 nvme_reset_ctrl(&ndev
->ctrl
);
2424 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops
, nvme_suspend
, nvme_resume
);
2426 static pci_ers_result_t
nvme_error_detected(struct pci_dev
*pdev
,
2427 pci_channel_state_t state
)
2429 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2432 * A frozen channel requires a reset. When detected, this method will
2433 * shutdown the controller to quiesce. The controller will be restarted
2434 * after the slot reset through driver's slot_reset callback.
2437 case pci_channel_io_normal
:
2438 return PCI_ERS_RESULT_CAN_RECOVER
;
2439 case pci_channel_io_frozen
:
2440 dev_warn(dev
->ctrl
.device
,
2441 "frozen state error detected, reset controller\n");
2442 nvme_dev_disable(dev
, false);
2443 return PCI_ERS_RESULT_NEED_RESET
;
2444 case pci_channel_io_perm_failure
:
2445 dev_warn(dev
->ctrl
.device
,
2446 "failure state error detected, request disconnect\n");
2447 return PCI_ERS_RESULT_DISCONNECT
;
2449 return PCI_ERS_RESULT_NEED_RESET
;
2452 static pci_ers_result_t
nvme_slot_reset(struct pci_dev
*pdev
)
2454 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2456 dev_info(dev
->ctrl
.device
, "restart after slot reset\n");
2457 pci_restore_state(pdev
);
2458 nvme_reset_ctrl(&dev
->ctrl
);
2459 return PCI_ERS_RESULT_RECOVERED
;
2462 static void nvme_error_resume(struct pci_dev
*pdev
)
2464 pci_cleanup_aer_uncorrect_error_status(pdev
);
2467 static const struct pci_error_handlers nvme_err_handler
= {
2468 .error_detected
= nvme_error_detected
,
2469 .slot_reset
= nvme_slot_reset
,
2470 .resume
= nvme_error_resume
,
2471 .reset_prepare
= nvme_reset_prepare
,
2472 .reset_done
= nvme_reset_done
,
2475 static const struct pci_device_id nvme_id_table
[] = {
2476 { PCI_VDEVICE(INTEL
, 0x0953),
2477 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2478 NVME_QUIRK_DEALLOCATE_ZEROES
, },
2479 { PCI_VDEVICE(INTEL
, 0x0a53),
2480 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2481 NVME_QUIRK_DEALLOCATE_ZEROES
, },
2482 { PCI_VDEVICE(INTEL
, 0x0a54),
2483 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2484 NVME_QUIRK_DEALLOCATE_ZEROES
, },
2485 { PCI_VDEVICE(INTEL
, 0x0a55),
2486 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2487 NVME_QUIRK_DEALLOCATE_ZEROES
, },
2488 { PCI_VDEVICE(INTEL
, 0xf1a5), /* Intel 600P/P3100 */
2489 .driver_data
= NVME_QUIRK_NO_DEEPEST_PS
},
2490 { PCI_VDEVICE(INTEL
, 0x5845), /* Qemu emulated controller */
2491 .driver_data
= NVME_QUIRK_IDENTIFY_CNS
, },
2492 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2493 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
2494 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2495 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
2496 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
2497 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
2498 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
2499 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
2500 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS
, 0xffffff) },
2501 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, 0x2001) },
2502 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, 0x2003) },
2505 MODULE_DEVICE_TABLE(pci
, nvme_id_table
);
2507 static struct pci_driver nvme_driver
= {
2509 .id_table
= nvme_id_table
,
2510 .probe
= nvme_probe
,
2511 .remove
= nvme_remove
,
2512 .shutdown
= nvme_shutdown
,
2514 .pm
= &nvme_dev_pm_ops
,
2516 .sriov_configure
= nvme_pci_sriov_configure
,
2517 .err_handler
= &nvme_err_handler
,
2520 static int __init
nvme_init(void)
2522 return pci_register_driver(&nvme_driver
);
2525 static void __exit
nvme_exit(void)
2527 pci_unregister_driver(&nvme_driver
);
2531 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2532 MODULE_LICENSE("GPL");
2533 MODULE_VERSION("1.0");
2534 module_init(nvme_init
);
2535 module_exit(nvme_exit
);