2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/aer.h>
16 #include <linux/bitops.h>
17 #include <linux/blkdev.h>
18 #include <linux/blk-mq.h>
19 #include <linux/blk-mq-pci.h>
20 #include <linux/dmi.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
25 #include <linux/module.h>
26 #include <linux/mutex.h>
27 #include <linux/once.h>
28 #include <linux/pci.h>
29 #include <linux/poison.h>
30 #include <linux/t10-pi.h>
31 #include <linux/timer.h>
32 #include <linux/types.h>
33 #include <linux/io-64-nonatomic-lo-hi.h>
34 #include <asm/unaligned.h>
35 #include <linux/sed-opal.h>
39 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
40 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
43 * We handle AEN commands ourselves and don't even let the
44 * block layer know about them.
46 #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AERS)
48 static int use_threaded_interrupts
;
49 module_param(use_threaded_interrupts
, int, 0);
51 static bool use_cmb_sqes
= true;
52 module_param(use_cmb_sqes
, bool, 0644);
53 MODULE_PARM_DESC(use_cmb_sqes
, "use controller's memory buffer for I/O SQes");
55 static unsigned int max_host_mem_size_mb
= 128;
56 module_param(max_host_mem_size_mb
, uint
, 0444);
57 MODULE_PARM_DESC(max_host_mem_size_mb
,
58 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
60 static int io_queue_depth_set(const char *val
, const struct kernel_param
*kp
);
61 static const struct kernel_param_ops io_queue_depth_ops
= {
62 .set
= io_queue_depth_set
,
66 static int io_queue_depth
= 1024;
67 module_param_cb(io_queue_depth
, &io_queue_depth_ops
, &io_queue_depth
, 0644);
68 MODULE_PARM_DESC(io_queue_depth
, "set io queue depth, should >= 2");
73 static void nvme_process_cq(struct nvme_queue
*nvmeq
);
74 static void nvme_dev_disable(struct nvme_dev
*dev
, bool shutdown
);
77 * Represents an NVM Express device. Each nvme_dev is a PCI function.
80 struct nvme_queue
**queues
;
81 struct blk_mq_tag_set tagset
;
82 struct blk_mq_tag_set admin_tagset
;
85 struct dma_pool
*prp_page_pool
;
86 struct dma_pool
*prp_small_pool
;
87 unsigned online_queues
;
92 unsigned long bar_mapped_size
;
93 struct work_struct remove_work
;
94 struct mutex shutdown_lock
;
97 dma_addr_t cmb_dma_addr
;
101 struct nvme_ctrl ctrl
;
102 struct completion ioq_wait
;
104 /* shadow doorbell buffer support: */
106 dma_addr_t dbbuf_dbs_dma_addr
;
108 dma_addr_t dbbuf_eis_dma_addr
;
110 /* host memory buffer support: */
112 u32 nr_host_mem_descs
;
113 dma_addr_t host_mem_descs_dma
;
114 struct nvme_host_mem_buf_desc
*host_mem_descs
;
115 void **host_mem_desc_bufs
;
118 static int io_queue_depth_set(const char *val
, const struct kernel_param
*kp
)
122 ret
= kstrtoint(val
, 10, &n
);
123 if (ret
!= 0 || n
< 2)
126 return param_set_int(val
, kp
);
129 static inline unsigned int sq_idx(unsigned int qid
, u32 stride
)
131 return qid
* 2 * stride
;
134 static inline unsigned int cq_idx(unsigned int qid
, u32 stride
)
136 return (qid
* 2 + 1) * stride
;
139 static inline struct nvme_dev
*to_nvme_dev(struct nvme_ctrl
*ctrl
)
141 return container_of(ctrl
, struct nvme_dev
, ctrl
);
145 * An NVM Express queue. Each device has at least two (one for admin
146 * commands and one for I/O commands).
149 struct device
*q_dmadev
;
150 struct nvme_dev
*dev
;
152 struct nvme_command
*sq_cmds
;
153 struct nvme_command __iomem
*sq_cmds_io
;
154 volatile struct nvme_completion
*cqes
;
155 struct blk_mq_tags
**tags
;
156 dma_addr_t sq_dma_addr
;
157 dma_addr_t cq_dma_addr
;
173 * The nvme_iod describes the data in an I/O, including the list of PRP
174 * entries. You can't see it in this data structure because C doesn't let
175 * me express that. Use nvme_init_iod to ensure there's enough space
176 * allocated to store the PRP list.
179 struct nvme_request req
;
180 struct nvme_queue
*nvmeq
;
182 int npages
; /* In the PRP list. 0 means small pool in use */
183 int nents
; /* Used in scatterlist */
184 int length
; /* Of data, in bytes */
185 dma_addr_t first_dma
;
186 struct scatterlist meta_sg
; /* metadata requires single contiguous buffer */
187 struct scatterlist
*sg
;
188 struct scatterlist inline_sg
[0];
192 * Check we didin't inadvertently grow the command struct
194 static inline void _nvme_check_size(void)
196 BUILD_BUG_ON(sizeof(struct nvme_rw_command
) != 64);
197 BUILD_BUG_ON(sizeof(struct nvme_create_cq
) != 64);
198 BUILD_BUG_ON(sizeof(struct nvme_create_sq
) != 64);
199 BUILD_BUG_ON(sizeof(struct nvme_delete_queue
) != 64);
200 BUILD_BUG_ON(sizeof(struct nvme_features
) != 64);
201 BUILD_BUG_ON(sizeof(struct nvme_format_cmd
) != 64);
202 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd
) != 64);
203 BUILD_BUG_ON(sizeof(struct nvme_command
) != 64);
204 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl
) != NVME_IDENTIFY_DATA_SIZE
);
205 BUILD_BUG_ON(sizeof(struct nvme_id_ns
) != NVME_IDENTIFY_DATA_SIZE
);
206 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type
) != 64);
207 BUILD_BUG_ON(sizeof(struct nvme_smart_log
) != 512);
208 BUILD_BUG_ON(sizeof(struct nvme_dbbuf
) != 64);
211 static inline unsigned int nvme_dbbuf_size(u32 stride
)
213 return ((num_possible_cpus() + 1) * 8 * stride
);
216 static int nvme_dbbuf_dma_alloc(struct nvme_dev
*dev
)
218 unsigned int mem_size
= nvme_dbbuf_size(dev
->db_stride
);
223 dev
->dbbuf_dbs
= dma_alloc_coherent(dev
->dev
, mem_size
,
224 &dev
->dbbuf_dbs_dma_addr
,
228 dev
->dbbuf_eis
= dma_alloc_coherent(dev
->dev
, mem_size
,
229 &dev
->dbbuf_eis_dma_addr
,
231 if (!dev
->dbbuf_eis
) {
232 dma_free_coherent(dev
->dev
, mem_size
,
233 dev
->dbbuf_dbs
, dev
->dbbuf_dbs_dma_addr
);
234 dev
->dbbuf_dbs
= NULL
;
241 static void nvme_dbbuf_dma_free(struct nvme_dev
*dev
)
243 unsigned int mem_size
= nvme_dbbuf_size(dev
->db_stride
);
245 if (dev
->dbbuf_dbs
) {
246 dma_free_coherent(dev
->dev
, mem_size
,
247 dev
->dbbuf_dbs
, dev
->dbbuf_dbs_dma_addr
);
248 dev
->dbbuf_dbs
= NULL
;
250 if (dev
->dbbuf_eis
) {
251 dma_free_coherent(dev
->dev
, mem_size
,
252 dev
->dbbuf_eis
, dev
->dbbuf_eis_dma_addr
);
253 dev
->dbbuf_eis
= NULL
;
257 static void nvme_dbbuf_init(struct nvme_dev
*dev
,
258 struct nvme_queue
*nvmeq
, int qid
)
260 if (!dev
->dbbuf_dbs
|| !qid
)
263 nvmeq
->dbbuf_sq_db
= &dev
->dbbuf_dbs
[sq_idx(qid
, dev
->db_stride
)];
264 nvmeq
->dbbuf_cq_db
= &dev
->dbbuf_dbs
[cq_idx(qid
, dev
->db_stride
)];
265 nvmeq
->dbbuf_sq_ei
= &dev
->dbbuf_eis
[sq_idx(qid
, dev
->db_stride
)];
266 nvmeq
->dbbuf_cq_ei
= &dev
->dbbuf_eis
[cq_idx(qid
, dev
->db_stride
)];
269 static void nvme_dbbuf_set(struct nvme_dev
*dev
)
271 struct nvme_command c
;
276 memset(&c
, 0, sizeof(c
));
277 c
.dbbuf
.opcode
= nvme_admin_dbbuf
;
278 c
.dbbuf
.prp1
= cpu_to_le64(dev
->dbbuf_dbs_dma_addr
);
279 c
.dbbuf
.prp2
= cpu_to_le64(dev
->dbbuf_eis_dma_addr
);
281 if (nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0)) {
282 dev_warn(dev
->ctrl
.device
, "unable to set dbbuf\n");
283 /* Free memory and continue on */
284 nvme_dbbuf_dma_free(dev
);
288 static inline int nvme_dbbuf_need_event(u16 event_idx
, u16 new_idx
, u16 old
)
290 return (u16
)(new_idx
- event_idx
- 1) < (u16
)(new_idx
- old
);
293 /* Update dbbuf and return true if an MMIO is required */
294 static bool nvme_dbbuf_update_and_check_event(u16 value
, u32
*dbbuf_db
,
295 volatile u32
*dbbuf_ei
)
301 * Ensure that the queue is written before updating
302 * the doorbell in memory
306 old_value
= *dbbuf_db
;
309 if (!nvme_dbbuf_need_event(*dbbuf_ei
, value
, old_value
))
317 * Max size of iod being embedded in the request payload
319 #define NVME_INT_PAGES 2
320 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
323 * Will slightly overestimate the number of pages needed. This is OK
324 * as it only leads to a small amount of wasted memory for the lifetime of
327 static int nvme_npages(unsigned size
, struct nvme_dev
*dev
)
329 unsigned nprps
= DIV_ROUND_UP(size
+ dev
->ctrl
.page_size
,
330 dev
->ctrl
.page_size
);
331 return DIV_ROUND_UP(8 * nprps
, PAGE_SIZE
- 8);
334 static unsigned int nvme_iod_alloc_size(struct nvme_dev
*dev
,
335 unsigned int size
, unsigned int nseg
)
337 return sizeof(__le64
*) * nvme_npages(size
, dev
) +
338 sizeof(struct scatterlist
) * nseg
;
341 static unsigned int nvme_cmd_size(struct nvme_dev
*dev
)
343 return sizeof(struct nvme_iod
) +
344 nvme_iod_alloc_size(dev
, NVME_INT_BYTES(dev
), NVME_INT_PAGES
);
347 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
348 unsigned int hctx_idx
)
350 struct nvme_dev
*dev
= data
;
351 struct nvme_queue
*nvmeq
= dev
->queues
[0];
353 WARN_ON(hctx_idx
!= 0);
354 WARN_ON(dev
->admin_tagset
.tags
[0] != hctx
->tags
);
355 WARN_ON(nvmeq
->tags
);
357 hctx
->driver_data
= nvmeq
;
358 nvmeq
->tags
= &dev
->admin_tagset
.tags
[0];
362 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx
*hctx
, unsigned int hctx_idx
)
364 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
369 static int nvme_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
370 unsigned int hctx_idx
)
372 struct nvme_dev
*dev
= data
;
373 struct nvme_queue
*nvmeq
= dev
->queues
[hctx_idx
+ 1];
376 nvmeq
->tags
= &dev
->tagset
.tags
[hctx_idx
];
378 WARN_ON(dev
->tagset
.tags
[hctx_idx
] != hctx
->tags
);
379 hctx
->driver_data
= nvmeq
;
383 static int nvme_init_request(struct blk_mq_tag_set
*set
, struct request
*req
,
384 unsigned int hctx_idx
, unsigned int numa_node
)
386 struct nvme_dev
*dev
= set
->driver_data
;
387 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
388 int queue_idx
= (set
== &dev
->tagset
) ? hctx_idx
+ 1 : 0;
389 struct nvme_queue
*nvmeq
= dev
->queues
[queue_idx
];
396 static int nvme_pci_map_queues(struct blk_mq_tag_set
*set
)
398 struct nvme_dev
*dev
= set
->driver_data
;
400 return blk_mq_pci_map_queues(set
, to_pci_dev(dev
->dev
));
404 * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
405 * @nvmeq: The queue to use
406 * @cmd: The command to send
408 * Safe to use from interrupt context
410 static void __nvme_submit_cmd(struct nvme_queue
*nvmeq
,
411 struct nvme_command
*cmd
)
413 u16 tail
= nvmeq
->sq_tail
;
415 if (nvmeq
->sq_cmds_io
)
416 memcpy_toio(&nvmeq
->sq_cmds_io
[tail
], cmd
, sizeof(*cmd
));
418 memcpy(&nvmeq
->sq_cmds
[tail
], cmd
, sizeof(*cmd
));
420 if (++tail
== nvmeq
->q_depth
)
422 if (nvme_dbbuf_update_and_check_event(tail
, nvmeq
->dbbuf_sq_db
,
424 writel(tail
, nvmeq
->q_db
);
425 nvmeq
->sq_tail
= tail
;
428 static __le64
**iod_list(struct request
*req
)
430 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
431 return (__le64
**)(iod
->sg
+ blk_rq_nr_phys_segments(req
));
434 static blk_status_t
nvme_init_iod(struct request
*rq
, struct nvme_dev
*dev
)
436 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(rq
);
437 int nseg
= blk_rq_nr_phys_segments(rq
);
438 unsigned int size
= blk_rq_payload_bytes(rq
);
440 if (nseg
> NVME_INT_PAGES
|| size
> NVME_INT_BYTES(dev
)) {
441 iod
->sg
= kmalloc(nvme_iod_alloc_size(dev
, size
, nseg
), GFP_ATOMIC
);
443 return BLK_STS_RESOURCE
;
445 iod
->sg
= iod
->inline_sg
;
456 static void nvme_free_iod(struct nvme_dev
*dev
, struct request
*req
)
458 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
459 const int last_prp
= dev
->ctrl
.page_size
/ 8 - 1;
461 __le64
**list
= iod_list(req
);
462 dma_addr_t prp_dma
= iod
->first_dma
;
464 if (iod
->npages
== 0)
465 dma_pool_free(dev
->prp_small_pool
, list
[0], prp_dma
);
466 for (i
= 0; i
< iod
->npages
; i
++) {
467 __le64
*prp_list
= list
[i
];
468 dma_addr_t next_prp_dma
= le64_to_cpu(prp_list
[last_prp
]);
469 dma_pool_free(dev
->prp_page_pool
, prp_list
, prp_dma
);
470 prp_dma
= next_prp_dma
;
473 if (iod
->sg
!= iod
->inline_sg
)
477 #ifdef CONFIG_BLK_DEV_INTEGRITY
478 static void nvme_dif_prep(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
480 if (be32_to_cpu(pi
->ref_tag
) == v
)
481 pi
->ref_tag
= cpu_to_be32(p
);
484 static void nvme_dif_complete(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
486 if (be32_to_cpu(pi
->ref_tag
) == p
)
487 pi
->ref_tag
= cpu_to_be32(v
);
491 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
493 * The virtual start sector is the one that was originally submitted by the
494 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
495 * start sector may be different. Remap protection information to match the
496 * physical LBA on writes, and back to the original seed on reads.
498 * Type 0 and 3 do not have a ref tag, so no remapping required.
500 static void nvme_dif_remap(struct request
*req
,
501 void (*dif_swap
)(u32 p
, u32 v
, struct t10_pi_tuple
*pi
))
503 struct nvme_ns
*ns
= req
->rq_disk
->private_data
;
504 struct bio_integrity_payload
*bip
;
505 struct t10_pi_tuple
*pi
;
507 u32 i
, nlb
, ts
, phys
, virt
;
509 if (!ns
->pi_type
|| ns
->pi_type
== NVME_NS_DPS_PI_TYPE3
)
512 bip
= bio_integrity(req
->bio
);
516 pmap
= kmap_atomic(bip
->bip_vec
->bv_page
) + bip
->bip_vec
->bv_offset
;
519 virt
= bip_get_seed(bip
);
520 phys
= nvme_block_nr(ns
, blk_rq_pos(req
));
521 nlb
= (blk_rq_bytes(req
) >> ns
->lba_shift
);
522 ts
= ns
->disk
->queue
->integrity
.tuple_size
;
524 for (i
= 0; i
< nlb
; i
++, virt
++, phys
++) {
525 pi
= (struct t10_pi_tuple
*)p
;
526 dif_swap(phys
, virt
, pi
);
531 #else /* CONFIG_BLK_DEV_INTEGRITY */
532 static void nvme_dif_remap(struct request
*req
,
533 void (*dif_swap
)(u32 p
, u32 v
, struct t10_pi_tuple
*pi
))
536 static void nvme_dif_prep(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
539 static void nvme_dif_complete(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
544 static void nvme_print_sgl(struct scatterlist
*sgl
, int nents
)
547 struct scatterlist
*sg
;
549 for_each_sg(sgl
, sg
, nents
, i
) {
550 dma_addr_t phys
= sg_phys(sg
);
551 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
552 "dma_address:%pad dma_length:%d\n",
553 i
, &phys
, sg
->offset
, sg
->length
, &sg_dma_address(sg
),
558 static blk_status_t
nvme_setup_prps(struct nvme_dev
*dev
, struct request
*req
)
560 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
561 struct dma_pool
*pool
;
562 int length
= blk_rq_payload_bytes(req
);
563 struct scatterlist
*sg
= iod
->sg
;
564 int dma_len
= sg_dma_len(sg
);
565 u64 dma_addr
= sg_dma_address(sg
);
566 u32 page_size
= dev
->ctrl
.page_size
;
567 int offset
= dma_addr
& (page_size
- 1);
569 __le64
**list
= iod_list(req
);
573 length
-= (page_size
- offset
);
579 dma_len
-= (page_size
- offset
);
581 dma_addr
+= (page_size
- offset
);
584 dma_addr
= sg_dma_address(sg
);
585 dma_len
= sg_dma_len(sg
);
588 if (length
<= page_size
) {
589 iod
->first_dma
= dma_addr
;
593 nprps
= DIV_ROUND_UP(length
, page_size
);
594 if (nprps
<= (256 / 8)) {
595 pool
= dev
->prp_small_pool
;
598 pool
= dev
->prp_page_pool
;
602 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
604 iod
->first_dma
= dma_addr
;
606 return BLK_STS_RESOURCE
;
609 iod
->first_dma
= prp_dma
;
612 if (i
== page_size
>> 3) {
613 __le64
*old_prp_list
= prp_list
;
614 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
616 return BLK_STS_RESOURCE
;
617 list
[iod
->npages
++] = prp_list
;
618 prp_list
[0] = old_prp_list
[i
- 1];
619 old_prp_list
[i
- 1] = cpu_to_le64(prp_dma
);
622 prp_list
[i
++] = cpu_to_le64(dma_addr
);
623 dma_len
-= page_size
;
624 dma_addr
+= page_size
;
630 if (unlikely(dma_len
< 0))
633 dma_addr
= sg_dma_address(sg
);
634 dma_len
= sg_dma_len(sg
);
640 WARN(DO_ONCE(nvme_print_sgl
, iod
->sg
, iod
->nents
),
641 "Invalid SGL for payload:%d nents:%d\n",
642 blk_rq_payload_bytes(req
), iod
->nents
);
643 return BLK_STS_IOERR
;
646 static blk_status_t
nvme_map_data(struct nvme_dev
*dev
, struct request
*req
,
647 struct nvme_command
*cmnd
)
649 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
650 struct request_queue
*q
= req
->q
;
651 enum dma_data_direction dma_dir
= rq_data_dir(req
) ?
652 DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
653 blk_status_t ret
= BLK_STS_IOERR
;
655 sg_init_table(iod
->sg
, blk_rq_nr_phys_segments(req
));
656 iod
->nents
= blk_rq_map_sg(q
, req
, iod
->sg
);
660 ret
= BLK_STS_RESOURCE
;
661 if (!dma_map_sg_attrs(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
,
665 ret
= nvme_setup_prps(dev
, req
);
666 if (ret
!= BLK_STS_OK
)
670 if (blk_integrity_rq(req
)) {
671 if (blk_rq_count_integrity_sg(q
, req
->bio
) != 1)
674 sg_init_table(&iod
->meta_sg
, 1);
675 if (blk_rq_map_integrity_sg(q
, req
->bio
, &iod
->meta_sg
) != 1)
678 if (req_op(req
) == REQ_OP_WRITE
)
679 nvme_dif_remap(req
, nvme_dif_prep
);
681 if (!dma_map_sg(dev
->dev
, &iod
->meta_sg
, 1, dma_dir
))
685 cmnd
->rw
.dptr
.prp1
= cpu_to_le64(sg_dma_address(iod
->sg
));
686 cmnd
->rw
.dptr
.prp2
= cpu_to_le64(iod
->first_dma
);
687 if (blk_integrity_rq(req
))
688 cmnd
->rw
.metadata
= cpu_to_le64(sg_dma_address(&iod
->meta_sg
));
692 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
);
697 static void nvme_unmap_data(struct nvme_dev
*dev
, struct request
*req
)
699 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
700 enum dma_data_direction dma_dir
= rq_data_dir(req
) ?
701 DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
704 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
);
705 if (blk_integrity_rq(req
)) {
706 if (req_op(req
) == REQ_OP_READ
)
707 nvme_dif_remap(req
, nvme_dif_complete
);
708 dma_unmap_sg(dev
->dev
, &iod
->meta_sg
, 1, dma_dir
);
712 nvme_cleanup_cmd(req
);
713 nvme_free_iod(dev
, req
);
717 * NOTE: ns is NULL when called on the admin queue.
719 static blk_status_t
nvme_queue_rq(struct blk_mq_hw_ctx
*hctx
,
720 const struct blk_mq_queue_data
*bd
)
722 struct nvme_ns
*ns
= hctx
->queue
->queuedata
;
723 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
724 struct nvme_dev
*dev
= nvmeq
->dev
;
725 struct request
*req
= bd
->rq
;
726 struct nvme_command cmnd
;
729 ret
= nvme_setup_cmd(ns
, req
, &cmnd
);
733 ret
= nvme_init_iod(req
, dev
);
737 if (blk_rq_nr_phys_segments(req
)) {
738 ret
= nvme_map_data(dev
, req
, &cmnd
);
740 goto out_cleanup_iod
;
743 blk_mq_start_request(req
);
745 spin_lock_irq(&nvmeq
->q_lock
);
746 if (unlikely(nvmeq
->cq_vector
< 0)) {
748 spin_unlock_irq(&nvmeq
->q_lock
);
749 goto out_cleanup_iod
;
751 __nvme_submit_cmd(nvmeq
, &cmnd
);
752 nvme_process_cq(nvmeq
);
753 spin_unlock_irq(&nvmeq
->q_lock
);
756 nvme_free_iod(dev
, req
);
758 nvme_cleanup_cmd(req
);
762 static void nvme_pci_complete_rq(struct request
*req
)
764 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
766 nvme_unmap_data(iod
->nvmeq
->dev
, req
);
767 nvme_complete_rq(req
);
770 /* We read the CQE phase first to check if the rest of the entry is valid */
771 static inline bool nvme_cqe_valid(struct nvme_queue
*nvmeq
, u16 head
,
774 return (le16_to_cpu(nvmeq
->cqes
[head
].status
) & 1) == phase
;
777 static inline void nvme_ring_cq_doorbell(struct nvme_queue
*nvmeq
)
779 u16 head
= nvmeq
->cq_head
;
781 if (likely(nvmeq
->cq_vector
>= 0)) {
782 if (nvme_dbbuf_update_and_check_event(head
, nvmeq
->dbbuf_cq_db
,
784 writel(head
, nvmeq
->q_db
+ nvmeq
->dev
->db_stride
);
788 static inline void nvme_handle_cqe(struct nvme_queue
*nvmeq
,
789 struct nvme_completion
*cqe
)
793 if (unlikely(cqe
->command_id
>= nvmeq
->q_depth
)) {
794 dev_warn(nvmeq
->dev
->ctrl
.device
,
795 "invalid id %d completed on queue %d\n",
796 cqe
->command_id
, le16_to_cpu(cqe
->sq_id
));
801 * AEN requests are special as they don't time out and can
802 * survive any kind of queue freeze and often don't respond to
803 * aborts. We don't even bother to allocate a struct request
804 * for them but rather special case them here.
806 if (unlikely(nvmeq
->qid
== 0 &&
807 cqe
->command_id
>= NVME_AQ_BLKMQ_DEPTH
)) {
808 nvme_complete_async_event(&nvmeq
->dev
->ctrl
,
809 cqe
->status
, &cqe
->result
);
814 req
= blk_mq_tag_to_rq(*nvmeq
->tags
, cqe
->command_id
);
815 nvme_end_request(req
, cqe
->status
, cqe
->result
);
818 static inline bool nvme_read_cqe(struct nvme_queue
*nvmeq
,
819 struct nvme_completion
*cqe
)
821 if (nvme_cqe_valid(nvmeq
, nvmeq
->cq_head
, nvmeq
->cq_phase
)) {
822 *cqe
= nvmeq
->cqes
[nvmeq
->cq_head
];
824 if (++nvmeq
->cq_head
== nvmeq
->q_depth
) {
826 nvmeq
->cq_phase
= !nvmeq
->cq_phase
;
833 static void nvme_process_cq(struct nvme_queue
*nvmeq
)
835 struct nvme_completion cqe
;
838 while (nvme_read_cqe(nvmeq
, &cqe
)) {
839 nvme_handle_cqe(nvmeq
, &cqe
);
844 nvme_ring_cq_doorbell(nvmeq
);
847 static irqreturn_t
nvme_irq(int irq
, void *data
)
850 struct nvme_queue
*nvmeq
= data
;
851 spin_lock(&nvmeq
->q_lock
);
852 nvme_process_cq(nvmeq
);
853 result
= nvmeq
->cqe_seen
? IRQ_HANDLED
: IRQ_NONE
;
855 spin_unlock(&nvmeq
->q_lock
);
859 static irqreturn_t
nvme_irq_check(int irq
, void *data
)
861 struct nvme_queue
*nvmeq
= data
;
862 if (nvme_cqe_valid(nvmeq
, nvmeq
->cq_head
, nvmeq
->cq_phase
))
863 return IRQ_WAKE_THREAD
;
867 static int __nvme_poll(struct nvme_queue
*nvmeq
, unsigned int tag
)
869 struct nvme_completion cqe
;
870 int found
= 0, consumed
= 0;
872 if (!nvme_cqe_valid(nvmeq
, nvmeq
->cq_head
, nvmeq
->cq_phase
))
875 spin_lock_irq(&nvmeq
->q_lock
);
876 while (nvme_read_cqe(nvmeq
, &cqe
)) {
877 nvme_handle_cqe(nvmeq
, &cqe
);
880 if (tag
== cqe
.command_id
) {
887 nvme_ring_cq_doorbell(nvmeq
);
888 spin_unlock_irq(&nvmeq
->q_lock
);
893 static int nvme_poll(struct blk_mq_hw_ctx
*hctx
, unsigned int tag
)
895 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
897 return __nvme_poll(nvmeq
, tag
);
900 static void nvme_pci_submit_async_event(struct nvme_ctrl
*ctrl
, int aer_idx
)
902 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
903 struct nvme_queue
*nvmeq
= dev
->queues
[0];
904 struct nvme_command c
;
906 memset(&c
, 0, sizeof(c
));
907 c
.common
.opcode
= nvme_admin_async_event
;
908 c
.common
.command_id
= NVME_AQ_BLKMQ_DEPTH
+ aer_idx
;
910 spin_lock_irq(&nvmeq
->q_lock
);
911 __nvme_submit_cmd(nvmeq
, &c
);
912 spin_unlock_irq(&nvmeq
->q_lock
);
915 static int adapter_delete_queue(struct nvme_dev
*dev
, u8 opcode
, u16 id
)
917 struct nvme_command c
;
919 memset(&c
, 0, sizeof(c
));
920 c
.delete_queue
.opcode
= opcode
;
921 c
.delete_queue
.qid
= cpu_to_le16(id
);
923 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
926 static int adapter_alloc_cq(struct nvme_dev
*dev
, u16 qid
,
927 struct nvme_queue
*nvmeq
)
929 struct nvme_command c
;
930 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_CQ_IRQ_ENABLED
;
933 * Note: we (ab)use the fact the the prp fields survive if no data
934 * is attached to the request.
936 memset(&c
, 0, sizeof(c
));
937 c
.create_cq
.opcode
= nvme_admin_create_cq
;
938 c
.create_cq
.prp1
= cpu_to_le64(nvmeq
->cq_dma_addr
);
939 c
.create_cq
.cqid
= cpu_to_le16(qid
);
940 c
.create_cq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
941 c
.create_cq
.cq_flags
= cpu_to_le16(flags
);
942 c
.create_cq
.irq_vector
= cpu_to_le16(nvmeq
->cq_vector
);
944 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
947 static int adapter_alloc_sq(struct nvme_dev
*dev
, u16 qid
,
948 struct nvme_queue
*nvmeq
)
950 struct nvme_command c
;
951 int flags
= NVME_QUEUE_PHYS_CONTIG
;
954 * Note: we (ab)use the fact the the prp fields survive if no data
955 * is attached to the request.
957 memset(&c
, 0, sizeof(c
));
958 c
.create_sq
.opcode
= nvme_admin_create_sq
;
959 c
.create_sq
.prp1
= cpu_to_le64(nvmeq
->sq_dma_addr
);
960 c
.create_sq
.sqid
= cpu_to_le16(qid
);
961 c
.create_sq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
962 c
.create_sq
.sq_flags
= cpu_to_le16(flags
);
963 c
.create_sq
.cqid
= cpu_to_le16(qid
);
965 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
968 static int adapter_delete_cq(struct nvme_dev
*dev
, u16 cqid
)
970 return adapter_delete_queue(dev
, nvme_admin_delete_cq
, cqid
);
973 static int adapter_delete_sq(struct nvme_dev
*dev
, u16 sqid
)
975 return adapter_delete_queue(dev
, nvme_admin_delete_sq
, sqid
);
978 static void abort_endio(struct request
*req
, blk_status_t error
)
980 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
981 struct nvme_queue
*nvmeq
= iod
->nvmeq
;
983 dev_warn(nvmeq
->dev
->ctrl
.device
,
984 "Abort status: 0x%x", nvme_req(req
)->status
);
985 atomic_inc(&nvmeq
->dev
->ctrl
.abort_limit
);
986 blk_mq_free_request(req
);
989 static bool nvme_should_reset(struct nvme_dev
*dev
, u32 csts
)
992 /* If true, indicates loss of adapter communication, possibly by a
993 * NVMe Subsystem reset.
995 bool nssro
= dev
->subsystem
&& (csts
& NVME_CSTS_NSSRO
);
997 /* If there is a reset ongoing, we shouldn't reset again. */
998 if (dev
->ctrl
.state
== NVME_CTRL_RESETTING
)
1001 /* We shouldn't reset unless the controller is on fatal error state
1002 * _or_ if we lost the communication with it.
1004 if (!(csts
& NVME_CSTS_CFS
) && !nssro
)
1007 /* If PCI error recovery process is happening, we cannot reset or
1008 * the recovery mechanism will surely fail.
1010 if (pci_channel_offline(to_pci_dev(dev
->dev
)))
1016 static void nvme_warn_reset(struct nvme_dev
*dev
, u32 csts
)
1018 /* Read a config register to help see what died. */
1022 result
= pci_read_config_word(to_pci_dev(dev
->dev
), PCI_STATUS
,
1024 if (result
== PCIBIOS_SUCCESSFUL
)
1025 dev_warn(dev
->ctrl
.device
,
1026 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1029 dev_warn(dev
->ctrl
.device
,
1030 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1034 static enum blk_eh_timer_return
nvme_timeout(struct request
*req
, bool reserved
)
1036 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
1037 struct nvme_queue
*nvmeq
= iod
->nvmeq
;
1038 struct nvme_dev
*dev
= nvmeq
->dev
;
1039 struct request
*abort_req
;
1040 struct nvme_command cmd
;
1041 u32 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
1044 * Reset immediately if the controller is failed
1046 if (nvme_should_reset(dev
, csts
)) {
1047 nvme_warn_reset(dev
, csts
);
1048 nvme_dev_disable(dev
, false);
1049 nvme_reset_ctrl(&dev
->ctrl
);
1050 return BLK_EH_HANDLED
;
1054 * Did we miss an interrupt?
1056 if (__nvme_poll(nvmeq
, req
->tag
)) {
1057 dev_warn(dev
->ctrl
.device
,
1058 "I/O %d QID %d timeout, completion polled\n",
1059 req
->tag
, nvmeq
->qid
);
1060 return BLK_EH_HANDLED
;
1064 * Shutdown immediately if controller times out while starting. The
1065 * reset work will see the pci device disabled when it gets the forced
1066 * cancellation error. All outstanding requests are completed on
1067 * shutdown, so we return BLK_EH_HANDLED.
1069 if (dev
->ctrl
.state
== NVME_CTRL_RESETTING
) {
1070 dev_warn(dev
->ctrl
.device
,
1071 "I/O %d QID %d timeout, disable controller\n",
1072 req
->tag
, nvmeq
->qid
);
1073 nvme_dev_disable(dev
, false);
1074 nvme_req(req
)->flags
|= NVME_REQ_CANCELLED
;
1075 return BLK_EH_HANDLED
;
1079 * Shutdown the controller immediately and schedule a reset if the
1080 * command was already aborted once before and still hasn't been
1081 * returned to the driver, or if this is the admin queue.
1083 if (!nvmeq
->qid
|| iod
->aborted
) {
1084 dev_warn(dev
->ctrl
.device
,
1085 "I/O %d QID %d timeout, reset controller\n",
1086 req
->tag
, nvmeq
->qid
);
1087 nvme_dev_disable(dev
, false);
1088 nvme_reset_ctrl(&dev
->ctrl
);
1091 * Mark the request as handled, since the inline shutdown
1092 * forces all outstanding requests to complete.
1094 nvme_req(req
)->flags
|= NVME_REQ_CANCELLED
;
1095 return BLK_EH_HANDLED
;
1098 if (atomic_dec_return(&dev
->ctrl
.abort_limit
) < 0) {
1099 atomic_inc(&dev
->ctrl
.abort_limit
);
1100 return BLK_EH_RESET_TIMER
;
1104 memset(&cmd
, 0, sizeof(cmd
));
1105 cmd
.abort
.opcode
= nvme_admin_abort_cmd
;
1106 cmd
.abort
.cid
= req
->tag
;
1107 cmd
.abort
.sqid
= cpu_to_le16(nvmeq
->qid
);
1109 dev_warn(nvmeq
->dev
->ctrl
.device
,
1110 "I/O %d QID %d timeout, aborting\n",
1111 req
->tag
, nvmeq
->qid
);
1113 abort_req
= nvme_alloc_request(dev
->ctrl
.admin_q
, &cmd
,
1114 BLK_MQ_REQ_NOWAIT
, NVME_QID_ANY
);
1115 if (IS_ERR(abort_req
)) {
1116 atomic_inc(&dev
->ctrl
.abort_limit
);
1117 return BLK_EH_RESET_TIMER
;
1120 abort_req
->timeout
= ADMIN_TIMEOUT
;
1121 abort_req
->end_io_data
= NULL
;
1122 blk_execute_rq_nowait(abort_req
->q
, NULL
, abort_req
, 0, abort_endio
);
1125 * The aborted req will be completed on receiving the abort req.
1126 * We enable the timer again. If hit twice, it'll cause a device reset,
1127 * as the device then is in a faulty state.
1129 return BLK_EH_RESET_TIMER
;
1132 static void nvme_free_queue(struct nvme_queue
*nvmeq
)
1134 dma_free_coherent(nvmeq
->q_dmadev
, CQ_SIZE(nvmeq
->q_depth
),
1135 (void *)nvmeq
->cqes
, nvmeq
->cq_dma_addr
);
1137 dma_free_coherent(nvmeq
->q_dmadev
, SQ_SIZE(nvmeq
->q_depth
),
1138 nvmeq
->sq_cmds
, nvmeq
->sq_dma_addr
);
1142 static void nvme_free_queues(struct nvme_dev
*dev
, int lowest
)
1146 for (i
= dev
->ctrl
.queue_count
- 1; i
>= lowest
; i
--) {
1147 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
1148 dev
->ctrl
.queue_count
--;
1149 dev
->queues
[i
] = NULL
;
1150 nvme_free_queue(nvmeq
);
1155 * nvme_suspend_queue - put queue into suspended state
1156 * @nvmeq - queue to suspend
1158 static int nvme_suspend_queue(struct nvme_queue
*nvmeq
)
1162 spin_lock_irq(&nvmeq
->q_lock
);
1163 if (nvmeq
->cq_vector
== -1) {
1164 spin_unlock_irq(&nvmeq
->q_lock
);
1167 vector
= nvmeq
->cq_vector
;
1168 nvmeq
->dev
->online_queues
--;
1169 nvmeq
->cq_vector
= -1;
1170 spin_unlock_irq(&nvmeq
->q_lock
);
1172 if (!nvmeq
->qid
&& nvmeq
->dev
->ctrl
.admin_q
)
1173 blk_mq_quiesce_queue(nvmeq
->dev
->ctrl
.admin_q
);
1175 pci_free_irq(to_pci_dev(nvmeq
->dev
->dev
), vector
, nvmeq
);
1180 static void nvme_disable_admin_queue(struct nvme_dev
*dev
, bool shutdown
)
1182 struct nvme_queue
*nvmeq
= dev
->queues
[0];
1186 if (nvme_suspend_queue(nvmeq
))
1190 nvme_shutdown_ctrl(&dev
->ctrl
);
1192 nvme_disable_ctrl(&dev
->ctrl
, dev
->ctrl
.cap
);
1194 spin_lock_irq(&nvmeq
->q_lock
);
1195 nvme_process_cq(nvmeq
);
1196 spin_unlock_irq(&nvmeq
->q_lock
);
1199 static int nvme_cmb_qdepth(struct nvme_dev
*dev
, int nr_io_queues
,
1202 int q_depth
= dev
->q_depth
;
1203 unsigned q_size_aligned
= roundup(q_depth
* entry_size
,
1204 dev
->ctrl
.page_size
);
1206 if (q_size_aligned
* nr_io_queues
> dev
->cmb_size
) {
1207 u64 mem_per_q
= div_u64(dev
->cmb_size
, nr_io_queues
);
1208 mem_per_q
= round_down(mem_per_q
, dev
->ctrl
.page_size
);
1209 q_depth
= div_u64(mem_per_q
, entry_size
);
1212 * Ensure the reduced q_depth is above some threshold where it
1213 * would be better to map queues in system memory with the
1223 static int nvme_alloc_sq_cmds(struct nvme_dev
*dev
, struct nvme_queue
*nvmeq
,
1226 if (qid
&& dev
->cmb
&& use_cmb_sqes
&& NVME_CMB_SQS(dev
->cmbsz
)) {
1227 unsigned offset
= (qid
- 1) * roundup(SQ_SIZE(depth
),
1228 dev
->ctrl
.page_size
);
1229 nvmeq
->sq_dma_addr
= dev
->cmb_dma_addr
+ offset
;
1230 nvmeq
->sq_cmds_io
= dev
->cmb
+ offset
;
1232 nvmeq
->sq_cmds
= dma_alloc_coherent(dev
->dev
, SQ_SIZE(depth
),
1233 &nvmeq
->sq_dma_addr
, GFP_KERNEL
);
1234 if (!nvmeq
->sq_cmds
)
1241 static struct nvme_queue
*nvme_alloc_queue(struct nvme_dev
*dev
, int qid
,
1242 int depth
, int node
)
1244 struct nvme_queue
*nvmeq
= kzalloc_node(sizeof(*nvmeq
), GFP_KERNEL
,
1249 nvmeq
->cqes
= dma_zalloc_coherent(dev
->dev
, CQ_SIZE(depth
),
1250 &nvmeq
->cq_dma_addr
, GFP_KERNEL
);
1254 if (nvme_alloc_sq_cmds(dev
, nvmeq
, qid
, depth
))
1257 nvmeq
->q_dmadev
= dev
->dev
;
1259 spin_lock_init(&nvmeq
->q_lock
);
1261 nvmeq
->cq_phase
= 1;
1262 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1263 nvmeq
->q_depth
= depth
;
1265 nvmeq
->cq_vector
= -1;
1266 dev
->queues
[qid
] = nvmeq
;
1267 dev
->ctrl
.queue_count
++;
1272 dma_free_coherent(dev
->dev
, CQ_SIZE(depth
), (void *)nvmeq
->cqes
,
1273 nvmeq
->cq_dma_addr
);
1279 static int queue_request_irq(struct nvme_queue
*nvmeq
)
1281 struct pci_dev
*pdev
= to_pci_dev(nvmeq
->dev
->dev
);
1282 int nr
= nvmeq
->dev
->ctrl
.instance
;
1284 if (use_threaded_interrupts
) {
1285 return pci_request_irq(pdev
, nvmeq
->cq_vector
, nvme_irq_check
,
1286 nvme_irq
, nvmeq
, "nvme%dq%d", nr
, nvmeq
->qid
);
1288 return pci_request_irq(pdev
, nvmeq
->cq_vector
, nvme_irq
,
1289 NULL
, nvmeq
, "nvme%dq%d", nr
, nvmeq
->qid
);
1293 static void nvme_init_queue(struct nvme_queue
*nvmeq
, u16 qid
)
1295 struct nvme_dev
*dev
= nvmeq
->dev
;
1297 spin_lock_irq(&nvmeq
->q_lock
);
1300 nvmeq
->cq_phase
= 1;
1301 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1302 memset((void *)nvmeq
->cqes
, 0, CQ_SIZE(nvmeq
->q_depth
));
1303 nvme_dbbuf_init(dev
, nvmeq
, qid
);
1304 dev
->online_queues
++;
1305 spin_unlock_irq(&nvmeq
->q_lock
);
1308 static int nvme_create_queue(struct nvme_queue
*nvmeq
, int qid
)
1310 struct nvme_dev
*dev
= nvmeq
->dev
;
1313 nvmeq
->cq_vector
= qid
- 1;
1314 result
= adapter_alloc_cq(dev
, qid
, nvmeq
);
1318 result
= adapter_alloc_sq(dev
, qid
, nvmeq
);
1322 nvme_init_queue(nvmeq
, qid
);
1323 result
= queue_request_irq(nvmeq
);
1330 adapter_delete_sq(dev
, qid
);
1332 adapter_delete_cq(dev
, qid
);
1336 static const struct blk_mq_ops nvme_mq_admin_ops
= {
1337 .queue_rq
= nvme_queue_rq
,
1338 .complete
= nvme_pci_complete_rq
,
1339 .init_hctx
= nvme_admin_init_hctx
,
1340 .exit_hctx
= nvme_admin_exit_hctx
,
1341 .init_request
= nvme_init_request
,
1342 .timeout
= nvme_timeout
,
1345 static const struct blk_mq_ops nvme_mq_ops
= {
1346 .queue_rq
= nvme_queue_rq
,
1347 .complete
= nvme_pci_complete_rq
,
1348 .init_hctx
= nvme_init_hctx
,
1349 .init_request
= nvme_init_request
,
1350 .map_queues
= nvme_pci_map_queues
,
1351 .timeout
= nvme_timeout
,
1355 static void nvme_dev_remove_admin(struct nvme_dev
*dev
)
1357 if (dev
->ctrl
.admin_q
&& !blk_queue_dying(dev
->ctrl
.admin_q
)) {
1359 * If the controller was reset during removal, it's possible
1360 * user requests may be waiting on a stopped queue. Start the
1361 * queue to flush these to completion.
1363 blk_mq_unquiesce_queue(dev
->ctrl
.admin_q
);
1364 blk_cleanup_queue(dev
->ctrl
.admin_q
);
1365 blk_mq_free_tag_set(&dev
->admin_tagset
);
1369 static int nvme_alloc_admin_tags(struct nvme_dev
*dev
)
1371 if (!dev
->ctrl
.admin_q
) {
1372 dev
->admin_tagset
.ops
= &nvme_mq_admin_ops
;
1373 dev
->admin_tagset
.nr_hw_queues
= 1;
1376 * Subtract one to leave an empty queue entry for 'Full Queue'
1377 * condition. See NVM-Express 1.2 specification, section 4.1.2.
1379 dev
->admin_tagset
.queue_depth
= NVME_AQ_BLKMQ_DEPTH
- 1;
1380 dev
->admin_tagset
.timeout
= ADMIN_TIMEOUT
;
1381 dev
->admin_tagset
.numa_node
= dev_to_node(dev
->dev
);
1382 dev
->admin_tagset
.cmd_size
= nvme_cmd_size(dev
);
1383 dev
->admin_tagset
.flags
= BLK_MQ_F_NO_SCHED
;
1384 dev
->admin_tagset
.driver_data
= dev
;
1386 if (blk_mq_alloc_tag_set(&dev
->admin_tagset
))
1388 dev
->ctrl
.admin_tagset
= &dev
->admin_tagset
;
1390 dev
->ctrl
.admin_q
= blk_mq_init_queue(&dev
->admin_tagset
);
1391 if (IS_ERR(dev
->ctrl
.admin_q
)) {
1392 blk_mq_free_tag_set(&dev
->admin_tagset
);
1395 if (!blk_get_queue(dev
->ctrl
.admin_q
)) {
1396 nvme_dev_remove_admin(dev
);
1397 dev
->ctrl
.admin_q
= NULL
;
1401 blk_mq_unquiesce_queue(dev
->ctrl
.admin_q
);
1406 static unsigned long db_bar_size(struct nvme_dev
*dev
, unsigned nr_io_queues
)
1408 return NVME_REG_DBS
+ ((nr_io_queues
+ 1) * 8 * dev
->db_stride
);
1411 static int nvme_remap_bar(struct nvme_dev
*dev
, unsigned long size
)
1413 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1415 if (size
<= dev
->bar_mapped_size
)
1417 if (size
> pci_resource_len(pdev
, 0))
1421 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), size
);
1423 dev
->bar_mapped_size
= 0;
1426 dev
->bar_mapped_size
= size
;
1427 dev
->dbs
= dev
->bar
+ NVME_REG_DBS
;
1432 static int nvme_pci_configure_admin_queue(struct nvme_dev
*dev
)
1436 struct nvme_queue
*nvmeq
;
1438 result
= nvme_remap_bar(dev
, db_bar_size(dev
, 0));
1442 dev
->subsystem
= readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 1, 0) ?
1443 NVME_CAP_NSSRC(dev
->ctrl
.cap
) : 0;
1445 if (dev
->subsystem
&&
1446 (readl(dev
->bar
+ NVME_REG_CSTS
) & NVME_CSTS_NSSRO
))
1447 writel(NVME_CSTS_NSSRO
, dev
->bar
+ NVME_REG_CSTS
);
1449 result
= nvme_disable_ctrl(&dev
->ctrl
, dev
->ctrl
.cap
);
1453 nvmeq
= dev
->queues
[0];
1455 nvmeq
= nvme_alloc_queue(dev
, 0, NVME_AQ_DEPTH
,
1456 dev_to_node(dev
->dev
));
1461 aqa
= nvmeq
->q_depth
- 1;
1464 writel(aqa
, dev
->bar
+ NVME_REG_AQA
);
1465 lo_hi_writeq(nvmeq
->sq_dma_addr
, dev
->bar
+ NVME_REG_ASQ
);
1466 lo_hi_writeq(nvmeq
->cq_dma_addr
, dev
->bar
+ NVME_REG_ACQ
);
1468 result
= nvme_enable_ctrl(&dev
->ctrl
, dev
->ctrl
.cap
);
1472 nvmeq
->cq_vector
= 0;
1473 nvme_init_queue(nvmeq
, 0);
1474 result
= queue_request_irq(nvmeq
);
1476 nvmeq
->cq_vector
= -1;
1483 static int nvme_create_io_queues(struct nvme_dev
*dev
)
1488 for (i
= dev
->ctrl
.queue_count
; i
<= dev
->max_qid
; i
++) {
1489 /* vector == qid - 1, match nvme_create_queue */
1490 if (!nvme_alloc_queue(dev
, i
, dev
->q_depth
,
1491 pci_irq_get_node(to_pci_dev(dev
->dev
), i
- 1))) {
1497 max
= min(dev
->max_qid
, dev
->ctrl
.queue_count
- 1);
1498 for (i
= dev
->online_queues
; i
<= max
; i
++) {
1499 ret
= nvme_create_queue(dev
->queues
[i
], i
);
1505 * Ignore failing Create SQ/CQ commands, we can continue with less
1506 * than the desired aount of queues, and even a controller without
1507 * I/O queues an still be used to issue admin commands. This might
1508 * be useful to upgrade a buggy firmware for example.
1510 return ret
>= 0 ? 0 : ret
;
1513 static ssize_t
nvme_cmb_show(struct device
*dev
,
1514 struct device_attribute
*attr
,
1517 struct nvme_dev
*ndev
= to_nvme_dev(dev_get_drvdata(dev
));
1519 return scnprintf(buf
, PAGE_SIZE
, "cmbloc : x%08x\ncmbsz : x%08x\n",
1520 ndev
->cmbloc
, ndev
->cmbsz
);
1522 static DEVICE_ATTR(cmb
, S_IRUGO
, nvme_cmb_show
, NULL
);
1524 static void __iomem
*nvme_map_cmb(struct nvme_dev
*dev
)
1526 u64 szu
, size
, offset
;
1527 resource_size_t bar_size
;
1528 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1530 dma_addr_t dma_addr
;
1532 dev
->cmbsz
= readl(dev
->bar
+ NVME_REG_CMBSZ
);
1533 if (!(NVME_CMB_SZ(dev
->cmbsz
)))
1535 dev
->cmbloc
= readl(dev
->bar
+ NVME_REG_CMBLOC
);
1540 szu
= (u64
)1 << (12 + 4 * NVME_CMB_SZU(dev
->cmbsz
));
1541 size
= szu
* NVME_CMB_SZ(dev
->cmbsz
);
1542 offset
= szu
* NVME_CMB_OFST(dev
->cmbloc
);
1543 bar_size
= pci_resource_len(pdev
, NVME_CMB_BIR(dev
->cmbloc
));
1545 if (offset
> bar_size
)
1549 * Controllers may support a CMB size larger than their BAR,
1550 * for example, due to being behind a bridge. Reduce the CMB to
1551 * the reported size of the BAR
1553 if (size
> bar_size
- offset
)
1554 size
= bar_size
- offset
;
1556 dma_addr
= pci_resource_start(pdev
, NVME_CMB_BIR(dev
->cmbloc
)) + offset
;
1557 cmb
= ioremap_wc(dma_addr
, size
);
1561 dev
->cmb_dma_addr
= dma_addr
;
1562 dev
->cmb_size
= size
;
1566 static inline void nvme_release_cmb(struct nvme_dev
*dev
)
1571 sysfs_remove_file_from_group(&dev
->ctrl
.device
->kobj
,
1572 &dev_attr_cmb
.attr
, NULL
);
1577 static int nvme_set_host_mem(struct nvme_dev
*dev
, u32 bits
)
1579 u64 dma_addr
= dev
->host_mem_descs_dma
;
1580 struct nvme_command c
;
1583 memset(&c
, 0, sizeof(c
));
1584 c
.features
.opcode
= nvme_admin_set_features
;
1585 c
.features
.fid
= cpu_to_le32(NVME_FEAT_HOST_MEM_BUF
);
1586 c
.features
.dword11
= cpu_to_le32(bits
);
1587 c
.features
.dword12
= cpu_to_le32(dev
->host_mem_size
>>
1588 ilog2(dev
->ctrl
.page_size
));
1589 c
.features
.dword13
= cpu_to_le32(lower_32_bits(dma_addr
));
1590 c
.features
.dword14
= cpu_to_le32(upper_32_bits(dma_addr
));
1591 c
.features
.dword15
= cpu_to_le32(dev
->nr_host_mem_descs
);
1593 ret
= nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
1595 dev_warn(dev
->ctrl
.device
,
1596 "failed to set host mem (err %d, flags %#x).\n",
1602 static void nvme_free_host_mem(struct nvme_dev
*dev
)
1606 for (i
= 0; i
< dev
->nr_host_mem_descs
; i
++) {
1607 struct nvme_host_mem_buf_desc
*desc
= &dev
->host_mem_descs
[i
];
1608 size_t size
= le32_to_cpu(desc
->size
) * dev
->ctrl
.page_size
;
1610 dma_free_coherent(dev
->dev
, size
, dev
->host_mem_desc_bufs
[i
],
1611 le64_to_cpu(desc
->addr
));
1614 kfree(dev
->host_mem_desc_bufs
);
1615 dev
->host_mem_desc_bufs
= NULL
;
1616 dma_free_coherent(dev
->dev
,
1617 dev
->nr_host_mem_descs
* sizeof(*dev
->host_mem_descs
),
1618 dev
->host_mem_descs
, dev
->host_mem_descs_dma
);
1619 dev
->host_mem_descs
= NULL
;
1622 static int __nvme_alloc_host_mem(struct nvme_dev
*dev
, u64 preferred
,
1625 struct nvme_host_mem_buf_desc
*descs
;
1626 u32 max_entries
, len
;
1627 dma_addr_t descs_dma
;
1632 tmp
= (preferred
+ chunk_size
- 1);
1633 do_div(tmp
, chunk_size
);
1636 if (dev
->ctrl
.hmmaxd
&& dev
->ctrl
.hmmaxd
< max_entries
)
1637 max_entries
= dev
->ctrl
.hmmaxd
;
1639 descs
= dma_zalloc_coherent(dev
->dev
, max_entries
* sizeof(*descs
),
1640 &descs_dma
, GFP_KERNEL
);
1644 bufs
= kcalloc(max_entries
, sizeof(*bufs
), GFP_KERNEL
);
1646 goto out_free_descs
;
1648 for (size
= 0; size
< preferred
; size
+= len
) {
1649 dma_addr_t dma_addr
;
1651 len
= min_t(u64
, chunk_size
, preferred
- size
);
1652 bufs
[i
] = dma_alloc_attrs(dev
->dev
, len
, &dma_addr
, GFP_KERNEL
,
1653 DMA_ATTR_NO_KERNEL_MAPPING
| DMA_ATTR_NO_WARN
);
1657 descs
[i
].addr
= cpu_to_le64(dma_addr
);
1658 descs
[i
].size
= cpu_to_le32(len
/ dev
->ctrl
.page_size
);
1665 dev
->nr_host_mem_descs
= i
;
1666 dev
->host_mem_size
= size
;
1667 dev
->host_mem_descs
= descs
;
1668 dev
->host_mem_descs_dma
= descs_dma
;
1669 dev
->host_mem_desc_bufs
= bufs
;
1674 size_t size
= le32_to_cpu(descs
[i
].size
) * dev
->ctrl
.page_size
;
1676 dma_free_coherent(dev
->dev
, size
, bufs
[i
],
1677 le64_to_cpu(descs
[i
].addr
));
1682 dma_free_coherent(dev
->dev
, max_entries
* sizeof(*descs
), descs
,
1685 dev
->host_mem_descs
= NULL
;
1689 static int nvme_alloc_host_mem(struct nvme_dev
*dev
, u64 min
, u64 preferred
)
1693 /* start big and work our way down */
1694 for (chunk_size
= min_t(u64
, preferred
, PAGE_SIZE
* MAX_ORDER_NR_PAGES
);
1695 chunk_size
>= max_t(u32
, dev
->ctrl
.hmminds
* 4096, PAGE_SIZE
* 2);
1697 if (!__nvme_alloc_host_mem(dev
, preferred
, chunk_size
)) {
1698 if (!min
|| dev
->host_mem_size
>= min
)
1700 nvme_free_host_mem(dev
);
1707 static int nvme_setup_host_mem(struct nvme_dev
*dev
)
1709 u64 max
= (u64
)max_host_mem_size_mb
* SZ_1M
;
1710 u64 preferred
= (u64
)dev
->ctrl
.hmpre
* 4096;
1711 u64 min
= (u64
)dev
->ctrl
.hmmin
* 4096;
1712 u32 enable_bits
= NVME_HOST_MEM_ENABLE
;
1715 preferred
= min(preferred
, max
);
1717 dev_warn(dev
->ctrl
.device
,
1718 "min host memory (%lld MiB) above limit (%d MiB).\n",
1719 min
>> ilog2(SZ_1M
), max_host_mem_size_mb
);
1720 nvme_free_host_mem(dev
);
1725 * If we already have a buffer allocated check if we can reuse it.
1727 if (dev
->host_mem_descs
) {
1728 if (dev
->host_mem_size
>= min
)
1729 enable_bits
|= NVME_HOST_MEM_RETURN
;
1731 nvme_free_host_mem(dev
);
1734 if (!dev
->host_mem_descs
) {
1735 if (nvme_alloc_host_mem(dev
, min
, preferred
)) {
1736 dev_warn(dev
->ctrl
.device
,
1737 "failed to allocate host memory buffer.\n");
1738 return 0; /* controller must work without HMB */
1741 dev_info(dev
->ctrl
.device
,
1742 "allocated %lld MiB host memory buffer.\n",
1743 dev
->host_mem_size
>> ilog2(SZ_1M
));
1746 ret
= nvme_set_host_mem(dev
, enable_bits
);
1748 nvme_free_host_mem(dev
);
1752 static int nvme_setup_io_queues(struct nvme_dev
*dev
)
1754 struct nvme_queue
*adminq
= dev
->queues
[0];
1755 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1756 int result
, nr_io_queues
;
1759 nr_io_queues
= num_present_cpus();
1760 result
= nvme_set_queue_count(&dev
->ctrl
, &nr_io_queues
);
1764 if (nr_io_queues
== 0)
1767 if (dev
->cmb
&& NVME_CMB_SQS(dev
->cmbsz
)) {
1768 result
= nvme_cmb_qdepth(dev
, nr_io_queues
,
1769 sizeof(struct nvme_command
));
1771 dev
->q_depth
= result
;
1773 nvme_release_cmb(dev
);
1777 size
= db_bar_size(dev
, nr_io_queues
);
1778 result
= nvme_remap_bar(dev
, size
);
1781 if (!--nr_io_queues
)
1784 adminq
->q_db
= dev
->dbs
;
1786 /* Deregister the admin queue's interrupt */
1787 pci_free_irq(pdev
, 0, adminq
);
1790 * If we enable msix early due to not intx, disable it again before
1791 * setting up the full range we need.
1793 pci_free_irq_vectors(pdev
);
1794 nr_io_queues
= pci_alloc_irq_vectors(pdev
, 1, nr_io_queues
,
1795 PCI_IRQ_ALL_TYPES
| PCI_IRQ_AFFINITY
);
1796 if (nr_io_queues
<= 0)
1798 dev
->max_qid
= nr_io_queues
;
1801 * Should investigate if there's a performance win from allocating
1802 * more queues than interrupt vectors; it might allow the submission
1803 * path to scale better, even if the receive path is limited by the
1804 * number of interrupts.
1807 result
= queue_request_irq(adminq
);
1809 adminq
->cq_vector
= -1;
1812 return nvme_create_io_queues(dev
);
1815 static void nvme_del_queue_end(struct request
*req
, blk_status_t error
)
1817 struct nvme_queue
*nvmeq
= req
->end_io_data
;
1819 blk_mq_free_request(req
);
1820 complete(&nvmeq
->dev
->ioq_wait
);
1823 static void nvme_del_cq_end(struct request
*req
, blk_status_t error
)
1825 struct nvme_queue
*nvmeq
= req
->end_io_data
;
1828 unsigned long flags
;
1831 * We might be called with the AQ q_lock held
1832 * and the I/O queue q_lock should always
1833 * nest inside the AQ one.
1835 spin_lock_irqsave_nested(&nvmeq
->q_lock
, flags
,
1836 SINGLE_DEPTH_NESTING
);
1837 nvme_process_cq(nvmeq
);
1838 spin_unlock_irqrestore(&nvmeq
->q_lock
, flags
);
1841 nvme_del_queue_end(req
, error
);
1844 static int nvme_delete_queue(struct nvme_queue
*nvmeq
, u8 opcode
)
1846 struct request_queue
*q
= nvmeq
->dev
->ctrl
.admin_q
;
1847 struct request
*req
;
1848 struct nvme_command cmd
;
1850 memset(&cmd
, 0, sizeof(cmd
));
1851 cmd
.delete_queue
.opcode
= opcode
;
1852 cmd
.delete_queue
.qid
= cpu_to_le16(nvmeq
->qid
);
1854 req
= nvme_alloc_request(q
, &cmd
, BLK_MQ_REQ_NOWAIT
, NVME_QID_ANY
);
1856 return PTR_ERR(req
);
1858 req
->timeout
= ADMIN_TIMEOUT
;
1859 req
->end_io_data
= nvmeq
;
1861 blk_execute_rq_nowait(q
, NULL
, req
, false,
1862 opcode
== nvme_admin_delete_cq
?
1863 nvme_del_cq_end
: nvme_del_queue_end
);
1867 static void nvme_disable_io_queues(struct nvme_dev
*dev
, int queues
)
1870 unsigned long timeout
;
1871 u8 opcode
= nvme_admin_delete_sq
;
1873 for (pass
= 0; pass
< 2; pass
++) {
1874 int sent
= 0, i
= queues
;
1876 reinit_completion(&dev
->ioq_wait
);
1878 timeout
= ADMIN_TIMEOUT
;
1879 for (; i
> 0; i
--, sent
++)
1880 if (nvme_delete_queue(dev
->queues
[i
], opcode
))
1884 timeout
= wait_for_completion_io_timeout(&dev
->ioq_wait
, timeout
);
1890 opcode
= nvme_admin_delete_cq
;
1895 * Return: error value if an error occurred setting up the queues or calling
1896 * Identify Device. 0 if these succeeded, even if adding some of the
1897 * namespaces failed. At the moment, these failures are silent. TBD which
1898 * failures should be reported.
1900 static int nvme_dev_add(struct nvme_dev
*dev
)
1902 if (!dev
->ctrl
.tagset
) {
1903 dev
->tagset
.ops
= &nvme_mq_ops
;
1904 dev
->tagset
.nr_hw_queues
= dev
->online_queues
- 1;
1905 dev
->tagset
.timeout
= NVME_IO_TIMEOUT
;
1906 dev
->tagset
.numa_node
= dev_to_node(dev
->dev
);
1907 dev
->tagset
.queue_depth
=
1908 min_t(int, dev
->q_depth
, BLK_MQ_MAX_DEPTH
) - 1;
1909 dev
->tagset
.cmd_size
= nvme_cmd_size(dev
);
1910 dev
->tagset
.flags
= BLK_MQ_F_SHOULD_MERGE
;
1911 dev
->tagset
.driver_data
= dev
;
1913 if (blk_mq_alloc_tag_set(&dev
->tagset
))
1915 dev
->ctrl
.tagset
= &dev
->tagset
;
1917 nvme_dbbuf_set(dev
);
1919 blk_mq_update_nr_hw_queues(&dev
->tagset
, dev
->online_queues
- 1);
1921 /* Free previously allocated queues that are no longer usable */
1922 nvme_free_queues(dev
, dev
->online_queues
);
1928 static int nvme_pci_enable(struct nvme_dev
*dev
)
1930 int result
= -ENOMEM
;
1931 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1933 if (pci_enable_device_mem(pdev
))
1936 pci_set_master(pdev
);
1938 if (dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(64)) &&
1939 dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(32)))
1942 if (readl(dev
->bar
+ NVME_REG_CSTS
) == -1) {
1948 * Some devices and/or platforms don't advertise or work with INTx
1949 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
1950 * adjust this later.
1952 result
= pci_alloc_irq_vectors(pdev
, 1, 1, PCI_IRQ_ALL_TYPES
);
1956 dev
->ctrl
.cap
= lo_hi_readq(dev
->bar
+ NVME_REG_CAP
);
1958 dev
->q_depth
= min_t(int, NVME_CAP_MQES(dev
->ctrl
.cap
) + 1,
1960 dev
->db_stride
= 1 << NVME_CAP_STRIDE(dev
->ctrl
.cap
);
1961 dev
->dbs
= dev
->bar
+ 4096;
1964 * Temporary fix for the Apple controller found in the MacBook8,1 and
1965 * some MacBook7,1 to avoid controller resets and data loss.
1967 if (pdev
->vendor
== PCI_VENDOR_ID_APPLE
&& pdev
->device
== 0x2001) {
1969 dev_warn(dev
->ctrl
.device
, "detected Apple NVMe controller, "
1970 "set queue depth=%u to work around controller resets\n",
1972 } else if (pdev
->vendor
== PCI_VENDOR_ID_SAMSUNG
&&
1973 (pdev
->device
== 0xa821 || pdev
->device
== 0xa822) &&
1974 NVME_CAP_MQES(dev
->ctrl
.cap
) == 0) {
1976 dev_err(dev
->ctrl
.device
, "detected PM1725 NVMe controller, "
1977 "set queue depth=%u\n", dev
->q_depth
);
1981 * CMBs can currently only exist on >=1.2 PCIe devices. We only
1982 * populate sysfs if a CMB is implemented. Since nvme_dev_attrs_group
1983 * has no name we can pass NULL as final argument to
1984 * sysfs_add_file_to_group.
1987 if (readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 2, 0)) {
1988 dev
->cmb
= nvme_map_cmb(dev
);
1990 if (sysfs_add_file_to_group(&dev
->ctrl
.device
->kobj
,
1991 &dev_attr_cmb
.attr
, NULL
))
1992 dev_warn(dev
->ctrl
.device
,
1993 "failed to add sysfs attribute for CMB\n");
1997 pci_enable_pcie_error_reporting(pdev
);
1998 pci_save_state(pdev
);
2002 pci_disable_device(pdev
);
2006 static void nvme_dev_unmap(struct nvme_dev
*dev
)
2010 pci_release_mem_regions(to_pci_dev(dev
->dev
));
2013 static void nvme_pci_disable(struct nvme_dev
*dev
)
2015 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2017 nvme_release_cmb(dev
);
2018 pci_free_irq_vectors(pdev
);
2020 if (pci_is_enabled(pdev
)) {
2021 pci_disable_pcie_error_reporting(pdev
);
2022 pci_disable_device(pdev
);
2026 static void nvme_dev_disable(struct nvme_dev
*dev
, bool shutdown
)
2030 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2032 mutex_lock(&dev
->shutdown_lock
);
2033 if (pci_is_enabled(pdev
)) {
2034 u32 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
2036 if (dev
->ctrl
.state
== NVME_CTRL_LIVE
||
2037 dev
->ctrl
.state
== NVME_CTRL_RESETTING
)
2038 nvme_start_freeze(&dev
->ctrl
);
2039 dead
= !!((csts
& NVME_CSTS_CFS
) || !(csts
& NVME_CSTS_RDY
) ||
2040 pdev
->error_state
!= pci_channel_io_normal
);
2044 * Give the controller a chance to complete all entered requests if
2045 * doing a safe shutdown.
2049 nvme_wait_freeze_timeout(&dev
->ctrl
, NVME_IO_TIMEOUT
);
2052 * If the controller is still alive tell it to stop using the
2053 * host memory buffer. In theory the shutdown / reset should
2054 * make sure that it doesn't access the host memoery anymore,
2055 * but I'd rather be safe than sorry..
2057 if (dev
->host_mem_descs
)
2058 nvme_set_host_mem(dev
, 0);
2061 nvme_stop_queues(&dev
->ctrl
);
2063 queues
= dev
->online_queues
- 1;
2064 for (i
= dev
->ctrl
.queue_count
- 1; i
> 0; i
--)
2065 nvme_suspend_queue(dev
->queues
[i
]);
2068 /* A device might become IO incapable very soon during
2069 * probe, before the admin queue is configured. Thus,
2070 * queue_count can be 0 here.
2072 if (dev
->ctrl
.queue_count
)
2073 nvme_suspend_queue(dev
->queues
[0]);
2075 nvme_disable_io_queues(dev
, queues
);
2076 nvme_disable_admin_queue(dev
, shutdown
);
2078 nvme_pci_disable(dev
);
2080 blk_mq_tagset_busy_iter(&dev
->tagset
, nvme_cancel_request
, &dev
->ctrl
);
2081 blk_mq_tagset_busy_iter(&dev
->admin_tagset
, nvme_cancel_request
, &dev
->ctrl
);
2084 * The driver will not be starting up queues again if shutting down so
2085 * must flush all entered requests to their failed completion to avoid
2086 * deadlocking blk-mq hot-cpu notifier.
2089 nvme_start_queues(&dev
->ctrl
);
2090 mutex_unlock(&dev
->shutdown_lock
);
2093 static int nvme_setup_prp_pools(struct nvme_dev
*dev
)
2095 dev
->prp_page_pool
= dma_pool_create("prp list page", dev
->dev
,
2096 PAGE_SIZE
, PAGE_SIZE
, 0);
2097 if (!dev
->prp_page_pool
)
2100 /* Optimisation for I/Os between 4k and 128k */
2101 dev
->prp_small_pool
= dma_pool_create("prp list 256", dev
->dev
,
2103 if (!dev
->prp_small_pool
) {
2104 dma_pool_destroy(dev
->prp_page_pool
);
2110 static void nvme_release_prp_pools(struct nvme_dev
*dev
)
2112 dma_pool_destroy(dev
->prp_page_pool
);
2113 dma_pool_destroy(dev
->prp_small_pool
);
2116 static void nvme_pci_free_ctrl(struct nvme_ctrl
*ctrl
)
2118 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
2120 nvme_dbbuf_dma_free(dev
);
2121 put_device(dev
->dev
);
2122 if (dev
->tagset
.tags
)
2123 blk_mq_free_tag_set(&dev
->tagset
);
2124 if (dev
->ctrl
.admin_q
)
2125 blk_put_queue(dev
->ctrl
.admin_q
);
2127 free_opal_dev(dev
->ctrl
.opal_dev
);
2131 static void nvme_remove_dead_ctrl(struct nvme_dev
*dev
, int status
)
2133 dev_warn(dev
->ctrl
.device
, "Removing after probe failure status: %d\n", status
);
2135 kref_get(&dev
->ctrl
.kref
);
2136 nvme_dev_disable(dev
, false);
2137 if (!schedule_work(&dev
->remove_work
))
2138 nvme_put_ctrl(&dev
->ctrl
);
2141 static void nvme_reset_work(struct work_struct
*work
)
2143 struct nvme_dev
*dev
=
2144 container_of(work
, struct nvme_dev
, ctrl
.reset_work
);
2145 bool was_suspend
= !!(dev
->ctrl
.ctrl_config
& NVME_CC_SHN_NORMAL
);
2146 int result
= -ENODEV
;
2148 if (WARN_ON(dev
->ctrl
.state
!= NVME_CTRL_RESETTING
))
2152 * If we're called to reset a live controller first shut it down before
2155 if (dev
->ctrl
.ctrl_config
& NVME_CC_ENABLE
)
2156 nvme_dev_disable(dev
, false);
2158 result
= nvme_pci_enable(dev
);
2162 result
= nvme_pci_configure_admin_queue(dev
);
2166 result
= nvme_alloc_admin_tags(dev
);
2170 result
= nvme_init_identify(&dev
->ctrl
);
2174 if (dev
->ctrl
.oacs
& NVME_CTRL_OACS_SEC_SUPP
) {
2175 if (!dev
->ctrl
.opal_dev
)
2176 dev
->ctrl
.opal_dev
=
2177 init_opal_dev(&dev
->ctrl
, &nvme_sec_submit
);
2178 else if (was_suspend
)
2179 opal_unlock_from_suspend(dev
->ctrl
.opal_dev
);
2181 free_opal_dev(dev
->ctrl
.opal_dev
);
2182 dev
->ctrl
.opal_dev
= NULL
;
2185 if (dev
->ctrl
.oacs
& NVME_CTRL_OACS_DBBUF_SUPP
) {
2186 result
= nvme_dbbuf_dma_alloc(dev
);
2189 "unable to allocate dma for dbbuf\n");
2192 if (dev
->ctrl
.hmpre
) {
2193 result
= nvme_setup_host_mem(dev
);
2198 result
= nvme_setup_io_queues(dev
);
2203 * Keep the controller around but remove all namespaces if we don't have
2204 * any working I/O queue.
2206 if (dev
->online_queues
< 2) {
2207 dev_warn(dev
->ctrl
.device
, "IO queues not created\n");
2208 nvme_kill_queues(&dev
->ctrl
);
2209 nvme_remove_namespaces(&dev
->ctrl
);
2211 nvme_start_queues(&dev
->ctrl
);
2212 nvme_wait_freeze(&dev
->ctrl
);
2214 nvme_unfreeze(&dev
->ctrl
);
2217 if (!nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_LIVE
)) {
2218 dev_warn(dev
->ctrl
.device
, "failed to mark controller live\n");
2222 nvme_start_ctrl(&dev
->ctrl
);
2226 nvme_remove_dead_ctrl(dev
, result
);
2229 static void nvme_remove_dead_ctrl_work(struct work_struct
*work
)
2231 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, remove_work
);
2232 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2234 nvme_kill_queues(&dev
->ctrl
);
2235 if (pci_get_drvdata(pdev
))
2236 device_release_driver(&pdev
->dev
);
2237 nvme_put_ctrl(&dev
->ctrl
);
2240 static int nvme_pci_reg_read32(struct nvme_ctrl
*ctrl
, u32 off
, u32
*val
)
2242 *val
= readl(to_nvme_dev(ctrl
)->bar
+ off
);
2246 static int nvme_pci_reg_write32(struct nvme_ctrl
*ctrl
, u32 off
, u32 val
)
2248 writel(val
, to_nvme_dev(ctrl
)->bar
+ off
);
2252 static int nvme_pci_reg_read64(struct nvme_ctrl
*ctrl
, u32 off
, u64
*val
)
2254 *val
= readq(to_nvme_dev(ctrl
)->bar
+ off
);
2258 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops
= {
2260 .module
= THIS_MODULE
,
2261 .flags
= NVME_F_METADATA_SUPPORTED
,
2262 .reg_read32
= nvme_pci_reg_read32
,
2263 .reg_write32
= nvme_pci_reg_write32
,
2264 .reg_read64
= nvme_pci_reg_read64
,
2265 .free_ctrl
= nvme_pci_free_ctrl
,
2266 .submit_async_event
= nvme_pci_submit_async_event
,
2269 static int nvme_dev_map(struct nvme_dev
*dev
)
2271 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2273 if (pci_request_mem_regions(pdev
, "nvme"))
2276 if (nvme_remap_bar(dev
, NVME_REG_DBS
+ 4096))
2281 pci_release_mem_regions(pdev
);
2285 static unsigned long check_dell_samsung_bug(struct pci_dev
*pdev
)
2287 if (pdev
->vendor
== 0x144d && pdev
->device
== 0xa802) {
2289 * Several Samsung devices seem to drop off the PCIe bus
2290 * randomly when APST is on and uses the deepest sleep state.
2291 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2292 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2293 * 950 PRO 256GB", but it seems to be restricted to two Dell
2296 if (dmi_match(DMI_SYS_VENDOR
, "Dell Inc.") &&
2297 (dmi_match(DMI_PRODUCT_NAME
, "XPS 15 9550") ||
2298 dmi_match(DMI_PRODUCT_NAME
, "Precision 5510")))
2299 return NVME_QUIRK_NO_DEEPEST_PS
;
2305 static int nvme_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
2307 int node
, result
= -ENOMEM
;
2308 struct nvme_dev
*dev
;
2309 unsigned long quirks
= id
->driver_data
;
2311 node
= dev_to_node(&pdev
->dev
);
2312 if (node
== NUMA_NO_NODE
)
2313 set_dev_node(&pdev
->dev
, first_memory_node
);
2315 dev
= kzalloc_node(sizeof(*dev
), GFP_KERNEL
, node
);
2318 dev
->queues
= kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2323 dev
->dev
= get_device(&pdev
->dev
);
2324 pci_set_drvdata(pdev
, dev
);
2326 result
= nvme_dev_map(dev
);
2330 INIT_WORK(&dev
->ctrl
.reset_work
, nvme_reset_work
);
2331 INIT_WORK(&dev
->remove_work
, nvme_remove_dead_ctrl_work
);
2332 mutex_init(&dev
->shutdown_lock
);
2333 init_completion(&dev
->ioq_wait
);
2335 result
= nvme_setup_prp_pools(dev
);
2339 quirks
|= check_dell_samsung_bug(pdev
);
2341 result
= nvme_init_ctrl(&dev
->ctrl
, &pdev
->dev
, &nvme_pci_ctrl_ops
,
2346 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_RESETTING
);
2347 dev_info(dev
->ctrl
.device
, "pci function %s\n", dev_name(&pdev
->dev
));
2349 queue_work(nvme_wq
, &dev
->ctrl
.reset_work
);
2353 nvme_release_prp_pools(dev
);
2355 nvme_dev_unmap(dev
);
2357 put_device(dev
->dev
);
2364 static void nvme_reset_prepare(struct pci_dev
*pdev
)
2366 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2367 nvme_dev_disable(dev
, false);
2370 static void nvme_reset_done(struct pci_dev
*pdev
)
2372 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2373 nvme_reset_ctrl(&dev
->ctrl
);
2376 static void nvme_shutdown(struct pci_dev
*pdev
)
2378 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2379 nvme_dev_disable(dev
, true);
2383 * The driver's remove may be called on a device in a partially initialized
2384 * state. This function must not have any dependencies on the device state in
2387 static void nvme_remove(struct pci_dev
*pdev
)
2389 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2391 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_DELETING
);
2393 cancel_work_sync(&dev
->ctrl
.reset_work
);
2394 pci_set_drvdata(pdev
, NULL
);
2396 if (!pci_device_is_present(pdev
)) {
2397 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_DEAD
);
2398 nvme_dev_disable(dev
, false);
2401 flush_work(&dev
->ctrl
.reset_work
);
2402 nvme_stop_ctrl(&dev
->ctrl
);
2403 nvme_remove_namespaces(&dev
->ctrl
);
2404 nvme_dev_disable(dev
, true);
2405 nvme_free_host_mem(dev
);
2406 nvme_dev_remove_admin(dev
);
2407 nvme_free_queues(dev
, 0);
2408 nvme_uninit_ctrl(&dev
->ctrl
);
2409 nvme_release_prp_pools(dev
);
2410 nvme_dev_unmap(dev
);
2411 nvme_put_ctrl(&dev
->ctrl
);
2414 static int nvme_pci_sriov_configure(struct pci_dev
*pdev
, int numvfs
)
2419 if (pci_vfs_assigned(pdev
)) {
2420 dev_warn(&pdev
->dev
,
2421 "Cannot disable SR-IOV VFs while assigned\n");
2424 pci_disable_sriov(pdev
);
2428 ret
= pci_enable_sriov(pdev
, numvfs
);
2429 return ret
? ret
: numvfs
;
2432 #ifdef CONFIG_PM_SLEEP
2433 static int nvme_suspend(struct device
*dev
)
2435 struct pci_dev
*pdev
= to_pci_dev(dev
);
2436 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2438 nvme_dev_disable(ndev
, true);
2442 static int nvme_resume(struct device
*dev
)
2444 struct pci_dev
*pdev
= to_pci_dev(dev
);
2445 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2447 nvme_reset_ctrl(&ndev
->ctrl
);
2452 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops
, nvme_suspend
, nvme_resume
);
2454 static pci_ers_result_t
nvme_error_detected(struct pci_dev
*pdev
,
2455 pci_channel_state_t state
)
2457 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2460 * A frozen channel requires a reset. When detected, this method will
2461 * shutdown the controller to quiesce. The controller will be restarted
2462 * after the slot reset through driver's slot_reset callback.
2465 case pci_channel_io_normal
:
2466 return PCI_ERS_RESULT_CAN_RECOVER
;
2467 case pci_channel_io_frozen
:
2468 dev_warn(dev
->ctrl
.device
,
2469 "frozen state error detected, reset controller\n");
2470 nvme_dev_disable(dev
, false);
2471 return PCI_ERS_RESULT_NEED_RESET
;
2472 case pci_channel_io_perm_failure
:
2473 dev_warn(dev
->ctrl
.device
,
2474 "failure state error detected, request disconnect\n");
2475 return PCI_ERS_RESULT_DISCONNECT
;
2477 return PCI_ERS_RESULT_NEED_RESET
;
2480 static pci_ers_result_t
nvme_slot_reset(struct pci_dev
*pdev
)
2482 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2484 dev_info(dev
->ctrl
.device
, "restart after slot reset\n");
2485 pci_restore_state(pdev
);
2486 nvme_reset_ctrl(&dev
->ctrl
);
2487 return PCI_ERS_RESULT_RECOVERED
;
2490 static void nvme_error_resume(struct pci_dev
*pdev
)
2492 pci_cleanup_aer_uncorrect_error_status(pdev
);
2495 static const struct pci_error_handlers nvme_err_handler
= {
2496 .error_detected
= nvme_error_detected
,
2497 .slot_reset
= nvme_slot_reset
,
2498 .resume
= nvme_error_resume
,
2499 .reset_prepare
= nvme_reset_prepare
,
2500 .reset_done
= nvme_reset_done
,
2503 static const struct pci_device_id nvme_id_table
[] = {
2504 { PCI_VDEVICE(INTEL
, 0x0953),
2505 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2506 NVME_QUIRK_DEALLOCATE_ZEROES
, },
2507 { PCI_VDEVICE(INTEL
, 0x0a53),
2508 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2509 NVME_QUIRK_DEALLOCATE_ZEROES
, },
2510 { PCI_VDEVICE(INTEL
, 0x0a54),
2511 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2512 NVME_QUIRK_DEALLOCATE_ZEROES
, },
2513 { PCI_VDEVICE(INTEL
, 0x0a55),
2514 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2515 NVME_QUIRK_DEALLOCATE_ZEROES
, },
2516 { PCI_VDEVICE(INTEL
, 0xf1a5), /* Intel 600P/P3100 */
2517 .driver_data
= NVME_QUIRK_NO_DEEPEST_PS
},
2518 { PCI_VDEVICE(INTEL
, 0x5845), /* Qemu emulated controller */
2519 .driver_data
= NVME_QUIRK_IDENTIFY_CNS
, },
2520 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2521 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
2522 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2523 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
2524 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
2525 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
2526 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
2527 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
2528 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */
2529 .driver_data
= NVME_QUIRK_LIGHTNVM
, },
2530 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */
2531 .driver_data
= NVME_QUIRK_LIGHTNVM
, },
2532 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS
, 0xffffff) },
2533 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, 0x2001) },
2534 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, 0x2003) },
2537 MODULE_DEVICE_TABLE(pci
, nvme_id_table
);
2539 static struct pci_driver nvme_driver
= {
2541 .id_table
= nvme_id_table
,
2542 .probe
= nvme_probe
,
2543 .remove
= nvme_remove
,
2544 .shutdown
= nvme_shutdown
,
2546 .pm
= &nvme_dev_pm_ops
,
2548 .sriov_configure
= nvme_pci_sriov_configure
,
2549 .err_handler
= &nvme_err_handler
,
2552 static int __init
nvme_init(void)
2554 return pci_register_driver(&nvme_driver
);
2557 static void __exit
nvme_exit(void)
2559 pci_unregister_driver(&nvme_driver
);
2563 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2564 MODULE_LICENSE("GPL");
2565 MODULE_VERSION("1.0");
2566 module_init(nvme_init
);
2567 module_exit(nvme_exit
);