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1 /*
2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 */
14
15 #include <linux/bitops.h>
16 #include <linux/blkdev.h>
17 #include <linux/blk-mq.h>
18 #include <linux/cpu.h>
19 #include <linux/delay.h>
20 #include <linux/errno.h>
21 #include <linux/fs.h>
22 #include <linux/genhd.h>
23 #include <linux/hdreg.h>
24 #include <linux/idr.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/io.h>
28 #include <linux/kdev_t.h>
29 #include <linux/kthread.h>
30 #include <linux/kernel.h>
31 #include <linux/list_sort.h>
32 #include <linux/mm.h>
33 #include <linux/module.h>
34 #include <linux/moduleparam.h>
35 #include <linux/pci.h>
36 #include <linux/poison.h>
37 #include <linux/ptrace.h>
38 #include <linux/sched.h>
39 #include <linux/slab.h>
40 #include <linux/t10-pi.h>
41 #include <linux/types.h>
42 #include <linux/pr.h>
43 #include <scsi/sg.h>
44 #include <linux/io-64-nonatomic-lo-hi.h>
45 #include <asm/unaligned.h>
46
47 #include <uapi/linux/nvme_ioctl.h>
48 #include "nvme.h"
49
50 #define NVME_MINORS (1U << MINORBITS)
51 #define NVME_Q_DEPTH 1024
52 #define NVME_AQ_DEPTH 256
53 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
54 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
55 #define ADMIN_TIMEOUT (admin_timeout * HZ)
56 #define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ)
57
58 static unsigned char admin_timeout = 60;
59 module_param(admin_timeout, byte, 0644);
60 MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
61
62 unsigned char nvme_io_timeout = 30;
63 module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
64 MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
65
66 static unsigned char shutdown_timeout = 5;
67 module_param(shutdown_timeout, byte, 0644);
68 MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
69
70 static int nvme_major;
71 module_param(nvme_major, int, 0);
72
73 static int nvme_char_major;
74 module_param(nvme_char_major, int, 0);
75
76 static int use_threaded_interrupts;
77 module_param(use_threaded_interrupts, int, 0);
78
79 static bool use_cmb_sqes = true;
80 module_param(use_cmb_sqes, bool, 0644);
81 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
82
83 static DEFINE_SPINLOCK(dev_list_lock);
84 static LIST_HEAD(dev_list);
85 static struct task_struct *nvme_thread;
86 static struct workqueue_struct *nvme_workq;
87 static wait_queue_head_t nvme_kthread_wait;
88
89 static struct class *nvme_class;
90
91 static int __nvme_reset(struct nvme_dev *dev);
92 static int nvme_reset(struct nvme_dev *dev);
93 static int nvme_process_cq(struct nvme_queue *nvmeq);
94 static void nvme_dead_ctrl(struct nvme_dev *dev);
95
96 struct async_cmd_info {
97 struct kthread_work work;
98 struct kthread_worker *worker;
99 struct request *req;
100 u32 result;
101 int status;
102 void *ctx;
103 };
104
105 /*
106 * An NVM Express queue. Each device has at least two (one for admin
107 * commands and one for I/O commands).
108 */
109 struct nvme_queue {
110 struct device *q_dmadev;
111 struct nvme_dev *dev;
112 char irqname[24]; /* nvme4294967295-65535\0 */
113 spinlock_t q_lock;
114 struct nvme_command *sq_cmds;
115 struct nvme_command __iomem *sq_cmds_io;
116 volatile struct nvme_completion *cqes;
117 struct blk_mq_tags **tags;
118 dma_addr_t sq_dma_addr;
119 dma_addr_t cq_dma_addr;
120 u32 __iomem *q_db;
121 u16 q_depth;
122 s16 cq_vector;
123 u16 sq_head;
124 u16 sq_tail;
125 u16 cq_head;
126 u16 qid;
127 u8 cq_phase;
128 u8 cqe_seen;
129 struct async_cmd_info cmdinfo;
130 };
131
132 /*
133 * Check we didin't inadvertently grow the command struct
134 */
135 static inline void _nvme_check_size(void)
136 {
137 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
138 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
139 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
140 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
141 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
142 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
143 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
144 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
145 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
146 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
147 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
148 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
149 }
150
151 typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
152 struct nvme_completion *);
153
154 struct nvme_cmd_info {
155 nvme_completion_fn fn;
156 void *ctx;
157 int aborted;
158 struct nvme_queue *nvmeq;
159 struct nvme_iod iod[0];
160 };
161
162 /*
163 * Max size of iod being embedded in the request payload
164 */
165 #define NVME_INT_PAGES 2
166 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->page_size)
167 #define NVME_INT_MASK 0x01
168
169 /*
170 * Will slightly overestimate the number of pages needed. This is OK
171 * as it only leads to a small amount of wasted memory for the lifetime of
172 * the I/O.
173 */
174 static int nvme_npages(unsigned size, struct nvme_dev *dev)
175 {
176 unsigned nprps = DIV_ROUND_UP(size + dev->page_size, dev->page_size);
177 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
178 }
179
180 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
181 {
182 unsigned int ret = sizeof(struct nvme_cmd_info);
183
184 ret += sizeof(struct nvme_iod);
185 ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev);
186 ret += sizeof(struct scatterlist) * NVME_INT_PAGES;
187
188 return ret;
189 }
190
191 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
192 unsigned int hctx_idx)
193 {
194 struct nvme_dev *dev = data;
195 struct nvme_queue *nvmeq = dev->queues[0];
196
197 WARN_ON(hctx_idx != 0);
198 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
199 WARN_ON(nvmeq->tags);
200
201 hctx->driver_data = nvmeq;
202 nvmeq->tags = &dev->admin_tagset.tags[0];
203 return 0;
204 }
205
206 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
207 {
208 struct nvme_queue *nvmeq = hctx->driver_data;
209
210 nvmeq->tags = NULL;
211 }
212
213 static int nvme_admin_init_request(void *data, struct request *req,
214 unsigned int hctx_idx, unsigned int rq_idx,
215 unsigned int numa_node)
216 {
217 struct nvme_dev *dev = data;
218 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
219 struct nvme_queue *nvmeq = dev->queues[0];
220
221 BUG_ON(!nvmeq);
222 cmd->nvmeq = nvmeq;
223 return 0;
224 }
225
226 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
227 unsigned int hctx_idx)
228 {
229 struct nvme_dev *dev = data;
230 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
231
232 if (!nvmeq->tags)
233 nvmeq->tags = &dev->tagset.tags[hctx_idx];
234
235 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
236 hctx->driver_data = nvmeq;
237 return 0;
238 }
239
240 static int nvme_init_request(void *data, struct request *req,
241 unsigned int hctx_idx, unsigned int rq_idx,
242 unsigned int numa_node)
243 {
244 struct nvme_dev *dev = data;
245 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
246 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
247
248 BUG_ON(!nvmeq);
249 cmd->nvmeq = nvmeq;
250 return 0;
251 }
252
253 static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx,
254 nvme_completion_fn handler)
255 {
256 cmd->fn = handler;
257 cmd->ctx = ctx;
258 cmd->aborted = 0;
259 blk_mq_start_request(blk_mq_rq_from_pdu(cmd));
260 }
261
262 static void *iod_get_private(struct nvme_iod *iod)
263 {
264 return (void *) (iod->private & ~0x1UL);
265 }
266
267 /*
268 * If bit 0 is set, the iod is embedded in the request payload.
269 */
270 static bool iod_should_kfree(struct nvme_iod *iod)
271 {
272 return (iod->private & NVME_INT_MASK) == 0;
273 }
274
275 /* Special values must be less than 0x1000 */
276 #define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
277 #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
278 #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
279 #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
280
281 static void special_completion(struct nvme_queue *nvmeq, void *ctx,
282 struct nvme_completion *cqe)
283 {
284 if (ctx == CMD_CTX_CANCELLED)
285 return;
286 if (ctx == CMD_CTX_COMPLETED) {
287 dev_warn(nvmeq->q_dmadev,
288 "completed id %d twice on queue %d\n",
289 cqe->command_id, le16_to_cpup(&cqe->sq_id));
290 return;
291 }
292 if (ctx == CMD_CTX_INVALID) {
293 dev_warn(nvmeq->q_dmadev,
294 "invalid id %d completed on queue %d\n",
295 cqe->command_id, le16_to_cpup(&cqe->sq_id));
296 return;
297 }
298 dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
299 }
300
301 static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn)
302 {
303 void *ctx;
304
305 if (fn)
306 *fn = cmd->fn;
307 ctx = cmd->ctx;
308 cmd->fn = special_completion;
309 cmd->ctx = CMD_CTX_CANCELLED;
310 return ctx;
311 }
312
313 static void async_req_completion(struct nvme_queue *nvmeq, void *ctx,
314 struct nvme_completion *cqe)
315 {
316 u32 result = le32_to_cpup(&cqe->result);
317 u16 status = le16_to_cpup(&cqe->status) >> 1;
318
319 if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
320 ++nvmeq->dev->event_limit;
321 if (status != NVME_SC_SUCCESS)
322 return;
323
324 switch (result & 0xff07) {
325 case NVME_AER_NOTICE_NS_CHANGED:
326 dev_info(nvmeq->q_dmadev, "rescanning\n");
327 schedule_work(&nvmeq->dev->scan_work);
328 default:
329 dev_warn(nvmeq->q_dmadev, "async event result %08x\n", result);
330 }
331 }
332
333 static void abort_completion(struct nvme_queue *nvmeq, void *ctx,
334 struct nvme_completion *cqe)
335 {
336 struct request *req = ctx;
337
338 u16 status = le16_to_cpup(&cqe->status) >> 1;
339 u32 result = le32_to_cpup(&cqe->result);
340
341 blk_mq_free_request(req);
342
343 dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result);
344 ++nvmeq->dev->abort_limit;
345 }
346
347 static void async_completion(struct nvme_queue *nvmeq, void *ctx,
348 struct nvme_completion *cqe)
349 {
350 struct async_cmd_info *cmdinfo = ctx;
351 cmdinfo->result = le32_to_cpup(&cqe->result);
352 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
353 queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
354 blk_mq_free_request(cmdinfo->req);
355 }
356
357 static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq,
358 unsigned int tag)
359 {
360 struct request *req = blk_mq_tag_to_rq(*nvmeq->tags, tag);
361
362 return blk_mq_rq_to_pdu(req);
363 }
364
365 /*
366 * Called with local interrupts disabled and the q_lock held. May not sleep.
367 */
368 static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag,
369 nvme_completion_fn *fn)
370 {
371 struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag);
372 void *ctx;
373 if (tag >= nvmeq->q_depth) {
374 *fn = special_completion;
375 return CMD_CTX_INVALID;
376 }
377 if (fn)
378 *fn = cmd->fn;
379 ctx = cmd->ctx;
380 cmd->fn = special_completion;
381 cmd->ctx = CMD_CTX_COMPLETED;
382 return ctx;
383 }
384
385 /**
386 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
387 * @nvmeq: The queue to use
388 * @cmd: The command to send
389 *
390 * Safe to use from interrupt context
391 */
392 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
393 struct nvme_command *cmd)
394 {
395 u16 tail = nvmeq->sq_tail;
396
397 if (nvmeq->sq_cmds_io)
398 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
399 else
400 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
401
402 if (++tail == nvmeq->q_depth)
403 tail = 0;
404 writel(tail, nvmeq->q_db);
405 nvmeq->sq_tail = tail;
406 }
407
408 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
409 {
410 unsigned long flags;
411 spin_lock_irqsave(&nvmeq->q_lock, flags);
412 __nvme_submit_cmd(nvmeq, cmd);
413 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
414 }
415
416 static __le64 **iod_list(struct nvme_iod *iod)
417 {
418 return ((void *)iod) + iod->offset;
419 }
420
421 static inline void iod_init(struct nvme_iod *iod, unsigned nbytes,
422 unsigned nseg, unsigned long private)
423 {
424 iod->private = private;
425 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
426 iod->npages = -1;
427 iod->length = nbytes;
428 iod->nents = 0;
429 }
430
431 static struct nvme_iod *
432 __nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev,
433 unsigned long priv, gfp_t gfp)
434 {
435 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
436 sizeof(__le64 *) * nvme_npages(bytes, dev) +
437 sizeof(struct scatterlist) * nseg, gfp);
438
439 if (iod)
440 iod_init(iod, bytes, nseg, priv);
441
442 return iod;
443 }
444
445 static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev,
446 gfp_t gfp)
447 {
448 unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) :
449 sizeof(struct nvme_dsm_range);
450 struct nvme_iod *iod;
451
452 if (rq->nr_phys_segments <= NVME_INT_PAGES &&
453 size <= NVME_INT_BYTES(dev)) {
454 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq);
455
456 iod = cmd->iod;
457 iod_init(iod, size, rq->nr_phys_segments,
458 (unsigned long) rq | NVME_INT_MASK);
459 return iod;
460 }
461
462 return __nvme_alloc_iod(rq->nr_phys_segments, size, dev,
463 (unsigned long) rq, gfp);
464 }
465
466 static void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
467 {
468 const int last_prp = dev->page_size / 8 - 1;
469 int i;
470 __le64 **list = iod_list(iod);
471 dma_addr_t prp_dma = iod->first_dma;
472
473 if (iod->npages == 0)
474 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
475 for (i = 0; i < iod->npages; i++) {
476 __le64 *prp_list = list[i];
477 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
478 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
479 prp_dma = next_prp_dma;
480 }
481
482 if (iod_should_kfree(iod))
483 kfree(iod);
484 }
485
486 static int nvme_error_status(u16 status)
487 {
488 switch (status & 0x7ff) {
489 case NVME_SC_SUCCESS:
490 return 0;
491 case NVME_SC_CAP_EXCEEDED:
492 return -ENOSPC;
493 default:
494 return -EIO;
495 }
496 }
497
498 #ifdef CONFIG_BLK_DEV_INTEGRITY
499 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
500 {
501 if (be32_to_cpu(pi->ref_tag) == v)
502 pi->ref_tag = cpu_to_be32(p);
503 }
504
505 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
506 {
507 if (be32_to_cpu(pi->ref_tag) == p)
508 pi->ref_tag = cpu_to_be32(v);
509 }
510
511 /**
512 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
513 *
514 * The virtual start sector is the one that was originally submitted by the
515 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
516 * start sector may be different. Remap protection information to match the
517 * physical LBA on writes, and back to the original seed on reads.
518 *
519 * Type 0 and 3 do not have a ref tag, so no remapping required.
520 */
521 static void nvme_dif_remap(struct request *req,
522 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
523 {
524 struct nvme_ns *ns = req->rq_disk->private_data;
525 struct bio_integrity_payload *bip;
526 struct t10_pi_tuple *pi;
527 void *p, *pmap;
528 u32 i, nlb, ts, phys, virt;
529
530 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
531 return;
532
533 bip = bio_integrity(req->bio);
534 if (!bip)
535 return;
536
537 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
538
539 p = pmap;
540 virt = bip_get_seed(bip);
541 phys = nvme_block_nr(ns, blk_rq_pos(req));
542 nlb = (blk_rq_bytes(req) >> ns->lba_shift);
543 ts = ns->disk->queue->integrity.tuple_size;
544
545 for (i = 0; i < nlb; i++, virt++, phys++) {
546 pi = (struct t10_pi_tuple *)p;
547 dif_swap(phys, virt, pi);
548 p += ts;
549 }
550 kunmap_atomic(pmap);
551 }
552
553 static void nvme_init_integrity(struct nvme_ns *ns)
554 {
555 struct blk_integrity integrity;
556
557 switch (ns->pi_type) {
558 case NVME_NS_DPS_PI_TYPE3:
559 integrity.profile = &t10_pi_type3_crc;
560 break;
561 case NVME_NS_DPS_PI_TYPE1:
562 case NVME_NS_DPS_PI_TYPE2:
563 integrity.profile = &t10_pi_type1_crc;
564 break;
565 default:
566 integrity.profile = NULL;
567 break;
568 }
569 integrity.tuple_size = ns->ms;
570 blk_integrity_register(ns->disk, &integrity);
571 blk_queue_max_integrity_segments(ns->queue, 1);
572 }
573 #else /* CONFIG_BLK_DEV_INTEGRITY */
574 static void nvme_dif_remap(struct request *req,
575 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
576 {
577 }
578 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
579 {
580 }
581 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
582 {
583 }
584 static void nvme_init_integrity(struct nvme_ns *ns)
585 {
586 }
587 #endif
588
589 static void req_completion(struct nvme_queue *nvmeq, void *ctx,
590 struct nvme_completion *cqe)
591 {
592 struct nvme_iod *iod = ctx;
593 struct request *req = iod_get_private(iod);
594 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
595 u16 status = le16_to_cpup(&cqe->status) >> 1;
596 bool requeue = false;
597 int error = 0;
598
599 if (unlikely(status)) {
600 if (!(status & NVME_SC_DNR || blk_noretry_request(req))
601 && (jiffies - req->start_time) < req->timeout) {
602 unsigned long flags;
603
604 requeue = true;
605 blk_mq_requeue_request(req);
606 spin_lock_irqsave(req->q->queue_lock, flags);
607 if (!blk_queue_stopped(req->q))
608 blk_mq_kick_requeue_list(req->q);
609 spin_unlock_irqrestore(req->q->queue_lock, flags);
610 goto release_iod;
611 }
612
613 if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
614 if (cmd_rq->ctx == CMD_CTX_CANCELLED)
615 error = -EINTR;
616 else
617 error = status;
618 } else {
619 error = nvme_error_status(status);
620 }
621 }
622
623 if (req->cmd_type == REQ_TYPE_DRV_PRIV) {
624 u32 result = le32_to_cpup(&cqe->result);
625 req->special = (void *)(uintptr_t)result;
626 }
627
628 if (cmd_rq->aborted)
629 dev_warn(nvmeq->dev->dev,
630 "completing aborted command with status:%04x\n",
631 error);
632
633 release_iod:
634 if (iod->nents) {
635 dma_unmap_sg(nvmeq->dev->dev, iod->sg, iod->nents,
636 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
637 if (blk_integrity_rq(req)) {
638 if (!rq_data_dir(req))
639 nvme_dif_remap(req, nvme_dif_complete);
640 dma_unmap_sg(nvmeq->dev->dev, iod->meta_sg, 1,
641 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
642 }
643 }
644 nvme_free_iod(nvmeq->dev, iod);
645
646 if (likely(!requeue))
647 blk_mq_complete_request(req, error);
648 }
649
650 /* length is in bytes. gfp flags indicates whether we may sleep. */
651 static int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod,
652 int total_len, gfp_t gfp)
653 {
654 struct dma_pool *pool;
655 int length = total_len;
656 struct scatterlist *sg = iod->sg;
657 int dma_len = sg_dma_len(sg);
658 u64 dma_addr = sg_dma_address(sg);
659 u32 page_size = dev->page_size;
660 int offset = dma_addr & (page_size - 1);
661 __le64 *prp_list;
662 __le64 **list = iod_list(iod);
663 dma_addr_t prp_dma;
664 int nprps, i;
665
666 length -= (page_size - offset);
667 if (length <= 0)
668 return total_len;
669
670 dma_len -= (page_size - offset);
671 if (dma_len) {
672 dma_addr += (page_size - offset);
673 } else {
674 sg = sg_next(sg);
675 dma_addr = sg_dma_address(sg);
676 dma_len = sg_dma_len(sg);
677 }
678
679 if (length <= page_size) {
680 iod->first_dma = dma_addr;
681 return total_len;
682 }
683
684 nprps = DIV_ROUND_UP(length, page_size);
685 if (nprps <= (256 / 8)) {
686 pool = dev->prp_small_pool;
687 iod->npages = 0;
688 } else {
689 pool = dev->prp_page_pool;
690 iod->npages = 1;
691 }
692
693 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
694 if (!prp_list) {
695 iod->first_dma = dma_addr;
696 iod->npages = -1;
697 return (total_len - length) + page_size;
698 }
699 list[0] = prp_list;
700 iod->first_dma = prp_dma;
701 i = 0;
702 for (;;) {
703 if (i == page_size >> 3) {
704 __le64 *old_prp_list = prp_list;
705 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
706 if (!prp_list)
707 return total_len - length;
708 list[iod->npages++] = prp_list;
709 prp_list[0] = old_prp_list[i - 1];
710 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
711 i = 1;
712 }
713 prp_list[i++] = cpu_to_le64(dma_addr);
714 dma_len -= page_size;
715 dma_addr += page_size;
716 length -= page_size;
717 if (length <= 0)
718 break;
719 if (dma_len > 0)
720 continue;
721 BUG_ON(dma_len < 0);
722 sg = sg_next(sg);
723 dma_addr = sg_dma_address(sg);
724 dma_len = sg_dma_len(sg);
725 }
726
727 return total_len;
728 }
729
730 static void nvme_submit_priv(struct nvme_queue *nvmeq, struct request *req,
731 struct nvme_iod *iod)
732 {
733 struct nvme_command cmnd;
734
735 memcpy(&cmnd, req->cmd, sizeof(cmnd));
736 cmnd.rw.command_id = req->tag;
737 if (req->nr_phys_segments) {
738 cmnd.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
739 cmnd.rw.prp2 = cpu_to_le64(iod->first_dma);
740 }
741
742 __nvme_submit_cmd(nvmeq, &cmnd);
743 }
744
745 /*
746 * We reuse the small pool to allocate the 16-byte range here as it is not
747 * worth having a special pool for these or additional cases to handle freeing
748 * the iod.
749 */
750 static void nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
751 struct request *req, struct nvme_iod *iod)
752 {
753 struct nvme_dsm_range *range =
754 (struct nvme_dsm_range *)iod_list(iod)[0];
755 struct nvme_command cmnd;
756
757 range->cattr = cpu_to_le32(0);
758 range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
759 range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
760
761 memset(&cmnd, 0, sizeof(cmnd));
762 cmnd.dsm.opcode = nvme_cmd_dsm;
763 cmnd.dsm.command_id = req->tag;
764 cmnd.dsm.nsid = cpu_to_le32(ns->ns_id);
765 cmnd.dsm.prp1 = cpu_to_le64(iod->first_dma);
766 cmnd.dsm.nr = 0;
767 cmnd.dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
768
769 __nvme_submit_cmd(nvmeq, &cmnd);
770 }
771
772 static void nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
773 int cmdid)
774 {
775 struct nvme_command cmnd;
776
777 memset(&cmnd, 0, sizeof(cmnd));
778 cmnd.common.opcode = nvme_cmd_flush;
779 cmnd.common.command_id = cmdid;
780 cmnd.common.nsid = cpu_to_le32(ns->ns_id);
781
782 __nvme_submit_cmd(nvmeq, &cmnd);
783 }
784
785 static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod,
786 struct nvme_ns *ns)
787 {
788 struct request *req = iod_get_private(iod);
789 struct nvme_command cmnd;
790 u16 control = 0;
791 u32 dsmgmt = 0;
792
793 if (req->cmd_flags & REQ_FUA)
794 control |= NVME_RW_FUA;
795 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
796 control |= NVME_RW_LR;
797
798 if (req->cmd_flags & REQ_RAHEAD)
799 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
800
801 memset(&cmnd, 0, sizeof(cmnd));
802 cmnd.rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
803 cmnd.rw.command_id = req->tag;
804 cmnd.rw.nsid = cpu_to_le32(ns->ns_id);
805 cmnd.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
806 cmnd.rw.prp2 = cpu_to_le64(iod->first_dma);
807 cmnd.rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
808 cmnd.rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
809
810 if (ns->ms) {
811 switch (ns->pi_type) {
812 case NVME_NS_DPS_PI_TYPE3:
813 control |= NVME_RW_PRINFO_PRCHK_GUARD;
814 break;
815 case NVME_NS_DPS_PI_TYPE1:
816 case NVME_NS_DPS_PI_TYPE2:
817 control |= NVME_RW_PRINFO_PRCHK_GUARD |
818 NVME_RW_PRINFO_PRCHK_REF;
819 cmnd.rw.reftag = cpu_to_le32(
820 nvme_block_nr(ns, blk_rq_pos(req)));
821 break;
822 }
823 if (blk_integrity_rq(req))
824 cmnd.rw.metadata =
825 cpu_to_le64(sg_dma_address(iod->meta_sg));
826 else
827 control |= NVME_RW_PRINFO_PRACT;
828 }
829
830 cmnd.rw.control = cpu_to_le16(control);
831 cmnd.rw.dsmgmt = cpu_to_le32(dsmgmt);
832
833 __nvme_submit_cmd(nvmeq, &cmnd);
834
835 return 0;
836 }
837
838 /*
839 * NOTE: ns is NULL when called on the admin queue.
840 */
841 static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
842 const struct blk_mq_queue_data *bd)
843 {
844 struct nvme_ns *ns = hctx->queue->queuedata;
845 struct nvme_queue *nvmeq = hctx->driver_data;
846 struct nvme_dev *dev = nvmeq->dev;
847 struct request *req = bd->rq;
848 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
849 struct nvme_iod *iod;
850 enum dma_data_direction dma_dir;
851
852 /*
853 * If formated with metadata, require the block layer provide a buffer
854 * unless this namespace is formated such that the metadata can be
855 * stripped/generated by the controller with PRACT=1.
856 */
857 if (ns && ns->ms && !blk_integrity_rq(req)) {
858 if (!(ns->pi_type && ns->ms == 8) &&
859 req->cmd_type != REQ_TYPE_DRV_PRIV) {
860 blk_mq_complete_request(req, -EFAULT);
861 return BLK_MQ_RQ_QUEUE_OK;
862 }
863 }
864
865 iod = nvme_alloc_iod(req, dev, GFP_ATOMIC);
866 if (!iod)
867 return BLK_MQ_RQ_QUEUE_BUSY;
868
869 if (req->cmd_flags & REQ_DISCARD) {
870 void *range;
871 /*
872 * We reuse the small pool to allocate the 16-byte range here
873 * as it is not worth having a special pool for these or
874 * additional cases to handle freeing the iod.
875 */
876 range = dma_pool_alloc(dev->prp_small_pool, GFP_ATOMIC,
877 &iod->first_dma);
878 if (!range)
879 goto retry_cmd;
880 iod_list(iod)[0] = (__le64 *)range;
881 iod->npages = 0;
882 } else if (req->nr_phys_segments) {
883 dma_dir = rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
884
885 sg_init_table(iod->sg, req->nr_phys_segments);
886 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
887 if (!iod->nents)
888 goto error_cmd;
889
890 if (!dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir))
891 goto retry_cmd;
892
893 if (blk_rq_bytes(req) !=
894 nvme_setup_prps(dev, iod, blk_rq_bytes(req), GFP_ATOMIC)) {
895 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
896 goto retry_cmd;
897 }
898 if (blk_integrity_rq(req)) {
899 if (blk_rq_count_integrity_sg(req->q, req->bio) != 1)
900 goto error_cmd;
901
902 sg_init_table(iod->meta_sg, 1);
903 if (blk_rq_map_integrity_sg(
904 req->q, req->bio, iod->meta_sg) != 1)
905 goto error_cmd;
906
907 if (rq_data_dir(req))
908 nvme_dif_remap(req, nvme_dif_prep);
909
910 if (!dma_map_sg(nvmeq->q_dmadev, iod->meta_sg, 1, dma_dir))
911 goto error_cmd;
912 }
913 }
914
915 nvme_set_info(cmd, iod, req_completion);
916 spin_lock_irq(&nvmeq->q_lock);
917 if (req->cmd_type == REQ_TYPE_DRV_PRIV)
918 nvme_submit_priv(nvmeq, req, iod);
919 else if (req->cmd_flags & REQ_DISCARD)
920 nvme_submit_discard(nvmeq, ns, req, iod);
921 else if (req->cmd_flags & REQ_FLUSH)
922 nvme_submit_flush(nvmeq, ns, req->tag);
923 else
924 nvme_submit_iod(nvmeq, iod, ns);
925
926 nvme_process_cq(nvmeq);
927 spin_unlock_irq(&nvmeq->q_lock);
928 return BLK_MQ_RQ_QUEUE_OK;
929
930 error_cmd:
931 nvme_free_iod(dev, iod);
932 return BLK_MQ_RQ_QUEUE_ERROR;
933 retry_cmd:
934 nvme_free_iod(dev, iod);
935 return BLK_MQ_RQ_QUEUE_BUSY;
936 }
937
938 static int nvme_process_cq(struct nvme_queue *nvmeq)
939 {
940 u16 head, phase;
941
942 head = nvmeq->cq_head;
943 phase = nvmeq->cq_phase;
944
945 for (;;) {
946 void *ctx;
947 nvme_completion_fn fn;
948 struct nvme_completion cqe = nvmeq->cqes[head];
949 if ((le16_to_cpu(cqe.status) & 1) != phase)
950 break;
951 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
952 if (++head == nvmeq->q_depth) {
953 head = 0;
954 phase = !phase;
955 }
956 ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn);
957 fn(nvmeq, ctx, &cqe);
958 }
959
960 /* If the controller ignores the cq head doorbell and continuously
961 * writes to the queue, it is theoretically possible to wrap around
962 * the queue twice and mistakenly return IRQ_NONE. Linux only
963 * requires that 0.1% of your interrupts are handled, so this isn't
964 * a big problem.
965 */
966 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
967 return 0;
968
969 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
970 nvmeq->cq_head = head;
971 nvmeq->cq_phase = phase;
972
973 nvmeq->cqe_seen = 1;
974 return 1;
975 }
976
977 static irqreturn_t nvme_irq(int irq, void *data)
978 {
979 irqreturn_t result;
980 struct nvme_queue *nvmeq = data;
981 spin_lock(&nvmeq->q_lock);
982 nvme_process_cq(nvmeq);
983 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
984 nvmeq->cqe_seen = 0;
985 spin_unlock(&nvmeq->q_lock);
986 return result;
987 }
988
989 static irqreturn_t nvme_irq_check(int irq, void *data)
990 {
991 struct nvme_queue *nvmeq = data;
992 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
993 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
994 return IRQ_NONE;
995 return IRQ_WAKE_THREAD;
996 }
997
998 /*
999 * Returns 0 on success. If the result is negative, it's a Linux error code;
1000 * if the result is positive, it's an NVM Express status code
1001 */
1002 int __nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
1003 void *buffer, void __user *ubuffer, unsigned bufflen,
1004 u32 *result, unsigned timeout)
1005 {
1006 bool write = cmd->common.opcode & 1;
1007 struct bio *bio = NULL;
1008 struct request *req;
1009 int ret;
1010
1011 req = blk_mq_alloc_request(q, write, GFP_KERNEL, false);
1012 if (IS_ERR(req))
1013 return PTR_ERR(req);
1014
1015 req->cmd_type = REQ_TYPE_DRV_PRIV;
1016 req->cmd_flags |= REQ_FAILFAST_DRIVER;
1017 req->__data_len = 0;
1018 req->__sector = (sector_t) -1;
1019 req->bio = req->biotail = NULL;
1020
1021 req->timeout = timeout ? timeout : ADMIN_TIMEOUT;
1022
1023 req->cmd = (unsigned char *)cmd;
1024 req->cmd_len = sizeof(struct nvme_command);
1025 req->special = (void *)0;
1026
1027 if (buffer && bufflen) {
1028 ret = blk_rq_map_kern(q, req, buffer, bufflen,
1029 __GFP_DIRECT_RECLAIM);
1030 if (ret)
1031 goto out;
1032 } else if (ubuffer && bufflen) {
1033 ret = blk_rq_map_user(q, req, NULL, ubuffer, bufflen,
1034 __GFP_DIRECT_RECLAIM);
1035 if (ret)
1036 goto out;
1037 bio = req->bio;
1038 }
1039
1040 blk_execute_rq(req->q, NULL, req, 0);
1041 if (bio)
1042 blk_rq_unmap_user(bio);
1043 if (result)
1044 *result = (u32)(uintptr_t)req->special;
1045 ret = req->errors;
1046 out:
1047 blk_mq_free_request(req);
1048 return ret;
1049 }
1050
1051 int nvme_submit_sync_cmd(struct request_queue *q, struct nvme_command *cmd,
1052 void *buffer, unsigned bufflen)
1053 {
1054 return __nvme_submit_sync_cmd(q, cmd, buffer, NULL, bufflen, NULL, 0);
1055 }
1056
1057 static int nvme_submit_async_admin_req(struct nvme_dev *dev)
1058 {
1059 struct nvme_queue *nvmeq = dev->queues[0];
1060 struct nvme_command c;
1061 struct nvme_cmd_info *cmd_info;
1062 struct request *req;
1063
1064 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC, true);
1065 if (IS_ERR(req))
1066 return PTR_ERR(req);
1067
1068 req->cmd_flags |= REQ_NO_TIMEOUT;
1069 cmd_info = blk_mq_rq_to_pdu(req);
1070 nvme_set_info(cmd_info, NULL, async_req_completion);
1071
1072 memset(&c, 0, sizeof(c));
1073 c.common.opcode = nvme_admin_async_event;
1074 c.common.command_id = req->tag;
1075
1076 blk_mq_free_request(req);
1077 __nvme_submit_cmd(nvmeq, &c);
1078 return 0;
1079 }
1080
1081 static int nvme_submit_admin_async_cmd(struct nvme_dev *dev,
1082 struct nvme_command *cmd,
1083 struct async_cmd_info *cmdinfo, unsigned timeout)
1084 {
1085 struct nvme_queue *nvmeq = dev->queues[0];
1086 struct request *req;
1087 struct nvme_cmd_info *cmd_rq;
1088
1089 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
1090 if (IS_ERR(req))
1091 return PTR_ERR(req);
1092
1093 req->timeout = timeout;
1094 cmd_rq = blk_mq_rq_to_pdu(req);
1095 cmdinfo->req = req;
1096 nvme_set_info(cmd_rq, cmdinfo, async_completion);
1097 cmdinfo->status = -EINTR;
1098
1099 cmd->common.command_id = req->tag;
1100
1101 nvme_submit_cmd(nvmeq, cmd);
1102 return 0;
1103 }
1104
1105 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1106 {
1107 struct nvme_command c;
1108
1109 memset(&c, 0, sizeof(c));
1110 c.delete_queue.opcode = opcode;
1111 c.delete_queue.qid = cpu_to_le16(id);
1112
1113 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
1114 }
1115
1116 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1117 struct nvme_queue *nvmeq)
1118 {
1119 struct nvme_command c;
1120 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1121
1122 /*
1123 * Note: we (ab)use the fact the the prp fields survive if no data
1124 * is attached to the request.
1125 */
1126 memset(&c, 0, sizeof(c));
1127 c.create_cq.opcode = nvme_admin_create_cq;
1128 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1129 c.create_cq.cqid = cpu_to_le16(qid);
1130 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1131 c.create_cq.cq_flags = cpu_to_le16(flags);
1132 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
1133
1134 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
1135 }
1136
1137 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1138 struct nvme_queue *nvmeq)
1139 {
1140 struct nvme_command c;
1141 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
1142
1143 /*
1144 * Note: we (ab)use the fact the the prp fields survive if no data
1145 * is attached to the request.
1146 */
1147 memset(&c, 0, sizeof(c));
1148 c.create_sq.opcode = nvme_admin_create_sq;
1149 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1150 c.create_sq.sqid = cpu_to_le16(qid);
1151 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1152 c.create_sq.sq_flags = cpu_to_le16(flags);
1153 c.create_sq.cqid = cpu_to_le16(qid);
1154
1155 return nvme_submit_sync_cmd(dev->admin_q, &c, NULL, 0);
1156 }
1157
1158 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1159 {
1160 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1161 }
1162
1163 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1164 {
1165 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1166 }
1167
1168 int nvme_identify_ctrl(struct nvme_dev *dev, struct nvme_id_ctrl **id)
1169 {
1170 struct nvme_command c = { };
1171 int error;
1172
1173 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
1174 c.identify.opcode = nvme_admin_identify;
1175 c.identify.cns = cpu_to_le32(1);
1176
1177 *id = kmalloc(sizeof(struct nvme_id_ctrl), GFP_KERNEL);
1178 if (!*id)
1179 return -ENOMEM;
1180
1181 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
1182 sizeof(struct nvme_id_ctrl));
1183 if (error)
1184 kfree(*id);
1185 return error;
1186 }
1187
1188 int nvme_identify_ns(struct nvme_dev *dev, unsigned nsid,
1189 struct nvme_id_ns **id)
1190 {
1191 struct nvme_command c = { };
1192 int error;
1193
1194 /* gcc-4.4.4 (at least) has issues with initializers and anon unions */
1195 c.identify.opcode = nvme_admin_identify,
1196 c.identify.nsid = cpu_to_le32(nsid),
1197
1198 *id = kmalloc(sizeof(struct nvme_id_ns), GFP_KERNEL);
1199 if (!*id)
1200 return -ENOMEM;
1201
1202 error = nvme_submit_sync_cmd(dev->admin_q, &c, *id,
1203 sizeof(struct nvme_id_ns));
1204 if (error)
1205 kfree(*id);
1206 return error;
1207 }
1208
1209 int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
1210 dma_addr_t dma_addr, u32 *result)
1211 {
1212 struct nvme_command c;
1213
1214 memset(&c, 0, sizeof(c));
1215 c.features.opcode = nvme_admin_get_features;
1216 c.features.nsid = cpu_to_le32(nsid);
1217 c.features.prp1 = cpu_to_le64(dma_addr);
1218 c.features.fid = cpu_to_le32(fid);
1219
1220 return __nvme_submit_sync_cmd(dev->admin_q, &c, NULL, NULL, 0,
1221 result, 0);
1222 }
1223
1224 int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
1225 dma_addr_t dma_addr, u32 *result)
1226 {
1227 struct nvme_command c;
1228
1229 memset(&c, 0, sizeof(c));
1230 c.features.opcode = nvme_admin_set_features;
1231 c.features.prp1 = cpu_to_le64(dma_addr);
1232 c.features.fid = cpu_to_le32(fid);
1233 c.features.dword11 = cpu_to_le32(dword11);
1234
1235 return __nvme_submit_sync_cmd(dev->admin_q, &c, NULL, NULL, 0,
1236 result, 0);
1237 }
1238
1239 int nvme_get_log_page(struct nvme_dev *dev, struct nvme_smart_log **log)
1240 {
1241 struct nvme_command c = { };
1242 int error;
1243
1244 c.common.opcode = nvme_admin_get_log_page,
1245 c.common.nsid = cpu_to_le32(0xFFFFFFFF),
1246 c.common.cdw10[0] = cpu_to_le32(
1247 (((sizeof(struct nvme_smart_log) / 4) - 1) << 16) |
1248 NVME_LOG_SMART),
1249
1250 *log = kmalloc(sizeof(struct nvme_smart_log), GFP_KERNEL);
1251 if (!*log)
1252 return -ENOMEM;
1253
1254 error = nvme_submit_sync_cmd(dev->admin_q, &c, *log,
1255 sizeof(struct nvme_smart_log));
1256 if (error)
1257 kfree(*log);
1258 return error;
1259 }
1260
1261 /**
1262 * nvme_abort_req - Attempt aborting a request
1263 *
1264 * Schedule controller reset if the command was already aborted once before and
1265 * still hasn't been returned to the driver, or if this is the admin queue.
1266 */
1267 static void nvme_abort_req(struct request *req)
1268 {
1269 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
1270 struct nvme_queue *nvmeq = cmd_rq->nvmeq;
1271 struct nvme_dev *dev = nvmeq->dev;
1272 struct request *abort_req;
1273 struct nvme_cmd_info *abort_cmd;
1274 struct nvme_command cmd;
1275
1276 if (!nvmeq->qid || cmd_rq->aborted) {
1277 spin_lock(&dev_list_lock);
1278 if (!__nvme_reset(dev)) {
1279 dev_warn(dev->dev,
1280 "I/O %d QID %d timeout, reset controller\n",
1281 req->tag, nvmeq->qid);
1282 }
1283 spin_unlock(&dev_list_lock);
1284 return;
1285 }
1286
1287 if (!dev->abort_limit)
1288 return;
1289
1290 abort_req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC,
1291 false);
1292 if (IS_ERR(abort_req))
1293 return;
1294
1295 abort_cmd = blk_mq_rq_to_pdu(abort_req);
1296 nvme_set_info(abort_cmd, abort_req, abort_completion);
1297
1298 memset(&cmd, 0, sizeof(cmd));
1299 cmd.abort.opcode = nvme_admin_abort_cmd;
1300 cmd.abort.cid = req->tag;
1301 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1302 cmd.abort.command_id = abort_req->tag;
1303
1304 --dev->abort_limit;
1305 cmd_rq->aborted = 1;
1306
1307 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag,
1308 nvmeq->qid);
1309 nvme_submit_cmd(dev->queues[0], &cmd);
1310 }
1311
1312 static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved)
1313 {
1314 struct nvme_queue *nvmeq = data;
1315 void *ctx;
1316 nvme_completion_fn fn;
1317 struct nvme_cmd_info *cmd;
1318 struct nvme_completion cqe;
1319
1320 if (!blk_mq_request_started(req))
1321 return;
1322
1323 cmd = blk_mq_rq_to_pdu(req);
1324
1325 if (cmd->ctx == CMD_CTX_CANCELLED)
1326 return;
1327
1328 if (blk_queue_dying(req->q))
1329 cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1);
1330 else
1331 cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1);
1332
1333
1334 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n",
1335 req->tag, nvmeq->qid);
1336 ctx = cancel_cmd_info(cmd, &fn);
1337 fn(nvmeq, ctx, &cqe);
1338 }
1339
1340 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1341 {
1342 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
1343 struct nvme_queue *nvmeq = cmd->nvmeq;
1344
1345 dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag,
1346 nvmeq->qid);
1347 spin_lock_irq(&nvmeq->q_lock);
1348 nvme_abort_req(req);
1349 spin_unlock_irq(&nvmeq->q_lock);
1350
1351 /*
1352 * The aborted req will be completed on receiving the abort req.
1353 * We enable the timer again. If hit twice, it'll cause a device reset,
1354 * as the device then is in a faulty state.
1355 */
1356 return BLK_EH_RESET_TIMER;
1357 }
1358
1359 static void nvme_free_queue(struct nvme_queue *nvmeq)
1360 {
1361 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1362 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1363 if (nvmeq->sq_cmds)
1364 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1365 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1366 kfree(nvmeq);
1367 }
1368
1369 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1370 {
1371 int i;
1372
1373 for (i = dev->queue_count - 1; i >= lowest; i--) {
1374 struct nvme_queue *nvmeq = dev->queues[i];
1375 dev->queue_count--;
1376 dev->queues[i] = NULL;
1377 nvme_free_queue(nvmeq);
1378 }
1379 }
1380
1381 /**
1382 * nvme_suspend_queue - put queue into suspended state
1383 * @nvmeq - queue to suspend
1384 */
1385 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1386 {
1387 int vector;
1388
1389 spin_lock_irq(&nvmeq->q_lock);
1390 if (nvmeq->cq_vector == -1) {
1391 spin_unlock_irq(&nvmeq->q_lock);
1392 return 1;
1393 }
1394 vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
1395 nvmeq->dev->online_queues--;
1396 nvmeq->cq_vector = -1;
1397 spin_unlock_irq(&nvmeq->q_lock);
1398
1399 if (!nvmeq->qid && nvmeq->dev->admin_q)
1400 blk_mq_freeze_queue_start(nvmeq->dev->admin_q);
1401
1402 irq_set_affinity_hint(vector, NULL);
1403 free_irq(vector, nvmeq);
1404
1405 return 0;
1406 }
1407
1408 static void nvme_clear_queue(struct nvme_queue *nvmeq)
1409 {
1410 spin_lock_irq(&nvmeq->q_lock);
1411 if (nvmeq->tags && *nvmeq->tags)
1412 blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq);
1413 spin_unlock_irq(&nvmeq->q_lock);
1414 }
1415
1416 static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1417 {
1418 struct nvme_queue *nvmeq = dev->queues[qid];
1419
1420 if (!nvmeq)
1421 return;
1422 if (nvme_suspend_queue(nvmeq))
1423 return;
1424
1425 /* Don't tell the adapter to delete the admin queue.
1426 * Don't tell a removed adapter to delete IO queues. */
1427 if (qid && readl(&dev->bar->csts) != -1) {
1428 adapter_delete_sq(dev, qid);
1429 adapter_delete_cq(dev, qid);
1430 }
1431
1432 spin_lock_irq(&nvmeq->q_lock);
1433 nvme_process_cq(nvmeq);
1434 spin_unlock_irq(&nvmeq->q_lock);
1435 }
1436
1437 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1438 int entry_size)
1439 {
1440 int q_depth = dev->q_depth;
1441 unsigned q_size_aligned = roundup(q_depth * entry_size, dev->page_size);
1442
1443 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1444 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1445 mem_per_q = round_down(mem_per_q, dev->page_size);
1446 q_depth = div_u64(mem_per_q, entry_size);
1447
1448 /*
1449 * Ensure the reduced q_depth is above some threshold where it
1450 * would be better to map queues in system memory with the
1451 * original depth
1452 */
1453 if (q_depth < 64)
1454 return -ENOMEM;
1455 }
1456
1457 return q_depth;
1458 }
1459
1460 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1461 int qid, int depth)
1462 {
1463 if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1464 unsigned offset = (qid - 1) *
1465 roundup(SQ_SIZE(depth), dev->page_size);
1466 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1467 nvmeq->sq_cmds_io = dev->cmb + offset;
1468 } else {
1469 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1470 &nvmeq->sq_dma_addr, GFP_KERNEL);
1471 if (!nvmeq->sq_cmds)
1472 return -ENOMEM;
1473 }
1474
1475 return 0;
1476 }
1477
1478 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1479 int depth)
1480 {
1481 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
1482 if (!nvmeq)
1483 return NULL;
1484
1485 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1486 &nvmeq->cq_dma_addr, GFP_KERNEL);
1487 if (!nvmeq->cqes)
1488 goto free_nvmeq;
1489
1490 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1491 goto free_cqdma;
1492
1493 nvmeq->q_dmadev = dev->dev;
1494 nvmeq->dev = dev;
1495 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1496 dev->instance, qid);
1497 spin_lock_init(&nvmeq->q_lock);
1498 nvmeq->cq_head = 0;
1499 nvmeq->cq_phase = 1;
1500 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1501 nvmeq->q_depth = depth;
1502 nvmeq->qid = qid;
1503 nvmeq->cq_vector = -1;
1504 dev->queues[qid] = nvmeq;
1505
1506 /* make sure queue descriptor is set before queue count, for kthread */
1507 mb();
1508 dev->queue_count++;
1509
1510 return nvmeq;
1511
1512 free_cqdma:
1513 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1514 nvmeq->cq_dma_addr);
1515 free_nvmeq:
1516 kfree(nvmeq);
1517 return NULL;
1518 }
1519
1520 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1521 const char *name)
1522 {
1523 if (use_threaded_interrupts)
1524 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
1525 nvme_irq_check, nvme_irq, IRQF_SHARED,
1526 name, nvmeq);
1527 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
1528 IRQF_SHARED, name, nvmeq);
1529 }
1530
1531 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1532 {
1533 struct nvme_dev *dev = nvmeq->dev;
1534
1535 spin_lock_irq(&nvmeq->q_lock);
1536 nvmeq->sq_tail = 0;
1537 nvmeq->cq_head = 0;
1538 nvmeq->cq_phase = 1;
1539 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1540 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1541 dev->online_queues++;
1542 spin_unlock_irq(&nvmeq->q_lock);
1543 }
1544
1545 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1546 {
1547 struct nvme_dev *dev = nvmeq->dev;
1548 int result;
1549
1550 nvmeq->cq_vector = qid - 1;
1551 result = adapter_alloc_cq(dev, qid, nvmeq);
1552 if (result < 0)
1553 return result;
1554
1555 result = adapter_alloc_sq(dev, qid, nvmeq);
1556 if (result < 0)
1557 goto release_cq;
1558
1559 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1560 if (result < 0)
1561 goto release_sq;
1562
1563 nvme_init_queue(nvmeq, qid);
1564 return result;
1565
1566 release_sq:
1567 adapter_delete_sq(dev, qid);
1568 release_cq:
1569 adapter_delete_cq(dev, qid);
1570 return result;
1571 }
1572
1573 static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1574 {
1575 unsigned long timeout;
1576 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1577
1578 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1579
1580 while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1581 msleep(100);
1582 if (fatal_signal_pending(current))
1583 return -EINTR;
1584 if (time_after(jiffies, timeout)) {
1585 dev_err(dev->dev,
1586 "Device not ready; aborting %s\n", enabled ?
1587 "initialisation" : "reset");
1588 return -ENODEV;
1589 }
1590 }
1591
1592 return 0;
1593 }
1594
1595 /*
1596 * If the device has been passed off to us in an enabled state, just clear
1597 * the enabled bit. The spec says we should set the 'shutdown notification
1598 * bits', but doing so may cause the device to complete commands to the
1599 * admin queue ... and we don't know what memory that might be pointing at!
1600 */
1601 static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1602 {
1603 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1604 dev->ctrl_config &= ~NVME_CC_ENABLE;
1605 writel(dev->ctrl_config, &dev->bar->cc);
1606
1607 return nvme_wait_ready(dev, cap, false);
1608 }
1609
1610 static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1611 {
1612 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1613 dev->ctrl_config |= NVME_CC_ENABLE;
1614 writel(dev->ctrl_config, &dev->bar->cc);
1615
1616 return nvme_wait_ready(dev, cap, true);
1617 }
1618
1619 static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1620 {
1621 unsigned long timeout;
1622
1623 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1624 dev->ctrl_config |= NVME_CC_SHN_NORMAL;
1625
1626 writel(dev->ctrl_config, &dev->bar->cc);
1627
1628 timeout = SHUTDOWN_TIMEOUT + jiffies;
1629 while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1630 NVME_CSTS_SHST_CMPLT) {
1631 msleep(100);
1632 if (fatal_signal_pending(current))
1633 return -EINTR;
1634 if (time_after(jiffies, timeout)) {
1635 dev_err(dev->dev,
1636 "Device shutdown incomplete; abort shutdown\n");
1637 return -ENODEV;
1638 }
1639 }
1640
1641 return 0;
1642 }
1643
1644 static struct blk_mq_ops nvme_mq_admin_ops = {
1645 .queue_rq = nvme_queue_rq,
1646 .map_queue = blk_mq_map_queue,
1647 .init_hctx = nvme_admin_init_hctx,
1648 .exit_hctx = nvme_admin_exit_hctx,
1649 .init_request = nvme_admin_init_request,
1650 .timeout = nvme_timeout,
1651 };
1652
1653 static struct blk_mq_ops nvme_mq_ops = {
1654 .queue_rq = nvme_queue_rq,
1655 .map_queue = blk_mq_map_queue,
1656 .init_hctx = nvme_init_hctx,
1657 .init_request = nvme_init_request,
1658 .timeout = nvme_timeout,
1659 };
1660
1661 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1662 {
1663 if (dev->admin_q && !blk_queue_dying(dev->admin_q)) {
1664 blk_cleanup_queue(dev->admin_q);
1665 blk_mq_free_tag_set(&dev->admin_tagset);
1666 }
1667 }
1668
1669 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1670 {
1671 if (!dev->admin_q) {
1672 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1673 dev->admin_tagset.nr_hw_queues = 1;
1674 dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1;
1675 dev->admin_tagset.reserved_tags = 1;
1676 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1677 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1678 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1679 dev->admin_tagset.driver_data = dev;
1680
1681 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1682 return -ENOMEM;
1683
1684 dev->admin_q = blk_mq_init_queue(&dev->admin_tagset);
1685 if (IS_ERR(dev->admin_q)) {
1686 blk_mq_free_tag_set(&dev->admin_tagset);
1687 return -ENOMEM;
1688 }
1689 if (!blk_get_queue(dev->admin_q)) {
1690 nvme_dev_remove_admin(dev);
1691 dev->admin_q = NULL;
1692 return -ENODEV;
1693 }
1694 } else
1695 blk_mq_unfreeze_queue(dev->admin_q);
1696
1697 return 0;
1698 }
1699
1700 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1701 {
1702 int result;
1703 u32 aqa;
1704 u64 cap = readq(&dev->bar->cap);
1705 struct nvme_queue *nvmeq;
1706 unsigned page_shift = PAGE_SHIFT;
1707 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12;
1708 unsigned dev_page_max = NVME_CAP_MPSMAX(cap) + 12;
1709
1710 if (page_shift < dev_page_min) {
1711 dev_err(dev->dev,
1712 "Minimum device page size (%u) too large for "
1713 "host (%u)\n", 1 << dev_page_min,
1714 1 << page_shift);
1715 return -ENODEV;
1716 }
1717 if (page_shift > dev_page_max) {
1718 dev_info(dev->dev,
1719 "Device maximum page size (%u) smaller than "
1720 "host (%u); enabling work-around\n",
1721 1 << dev_page_max, 1 << page_shift);
1722 page_shift = dev_page_max;
1723 }
1724
1725 dev->subsystem = readl(&dev->bar->vs) >= NVME_VS(1, 1) ?
1726 NVME_CAP_NSSRC(cap) : 0;
1727
1728 if (dev->subsystem && (readl(&dev->bar->csts) & NVME_CSTS_NSSRO))
1729 writel(NVME_CSTS_NSSRO, &dev->bar->csts);
1730
1731 result = nvme_disable_ctrl(dev, cap);
1732 if (result < 0)
1733 return result;
1734
1735 nvmeq = dev->queues[0];
1736 if (!nvmeq) {
1737 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1738 if (!nvmeq)
1739 return -ENOMEM;
1740 }
1741
1742 aqa = nvmeq->q_depth - 1;
1743 aqa |= aqa << 16;
1744
1745 dev->page_size = 1 << page_shift;
1746
1747 dev->ctrl_config = NVME_CC_CSS_NVM;
1748 dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
1749 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
1750 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
1751
1752 writel(aqa, &dev->bar->aqa);
1753 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1754 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
1755
1756 result = nvme_enable_ctrl(dev, cap);
1757 if (result)
1758 goto free_nvmeq;
1759
1760 nvmeq->cq_vector = 0;
1761 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
1762 if (result) {
1763 nvmeq->cq_vector = -1;
1764 goto free_nvmeq;
1765 }
1766
1767 return result;
1768
1769 free_nvmeq:
1770 nvme_free_queues(dev, 0);
1771 return result;
1772 }
1773
1774 static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1775 {
1776 struct nvme_dev *dev = ns->dev;
1777 struct nvme_user_io io;
1778 struct nvme_command c;
1779 unsigned length, meta_len;
1780 int status, write;
1781 dma_addr_t meta_dma = 0;
1782 void *meta = NULL;
1783 void __user *metadata;
1784
1785 if (copy_from_user(&io, uio, sizeof(io)))
1786 return -EFAULT;
1787
1788 switch (io.opcode) {
1789 case nvme_cmd_write:
1790 case nvme_cmd_read:
1791 case nvme_cmd_compare:
1792 break;
1793 default:
1794 return -EINVAL;
1795 }
1796
1797 length = (io.nblocks + 1) << ns->lba_shift;
1798 meta_len = (io.nblocks + 1) * ns->ms;
1799 metadata = (void __user *)(uintptr_t)io.metadata;
1800 write = io.opcode & 1;
1801
1802 if (ns->ext) {
1803 length += meta_len;
1804 meta_len = 0;
1805 }
1806 if (meta_len) {
1807 if (((io.metadata & 3) || !io.metadata) && !ns->ext)
1808 return -EINVAL;
1809
1810 meta = dma_alloc_coherent(dev->dev, meta_len,
1811 &meta_dma, GFP_KERNEL);
1812
1813 if (!meta) {
1814 status = -ENOMEM;
1815 goto unmap;
1816 }
1817 if (write) {
1818 if (copy_from_user(meta, metadata, meta_len)) {
1819 status = -EFAULT;
1820 goto unmap;
1821 }
1822 }
1823 }
1824
1825 memset(&c, 0, sizeof(c));
1826 c.rw.opcode = io.opcode;
1827 c.rw.flags = io.flags;
1828 c.rw.nsid = cpu_to_le32(ns->ns_id);
1829 c.rw.slba = cpu_to_le64(io.slba);
1830 c.rw.length = cpu_to_le16(io.nblocks);
1831 c.rw.control = cpu_to_le16(io.control);
1832 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1833 c.rw.reftag = cpu_to_le32(io.reftag);
1834 c.rw.apptag = cpu_to_le16(io.apptag);
1835 c.rw.appmask = cpu_to_le16(io.appmask);
1836 c.rw.metadata = cpu_to_le64(meta_dma);
1837
1838 status = __nvme_submit_sync_cmd(ns->queue, &c, NULL,
1839 (void __user *)(uintptr_t)io.addr, length, NULL, 0);
1840 unmap:
1841 if (meta) {
1842 if (status == NVME_SC_SUCCESS && !write) {
1843 if (copy_to_user(metadata, meta, meta_len))
1844 status = -EFAULT;
1845 }
1846 dma_free_coherent(dev->dev, meta_len, meta, meta_dma);
1847 }
1848 return status;
1849 }
1850
1851 static int nvme_user_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
1852 struct nvme_passthru_cmd __user *ucmd)
1853 {
1854 struct nvme_passthru_cmd cmd;
1855 struct nvme_command c;
1856 unsigned timeout = 0;
1857 int status;
1858
1859 if (!capable(CAP_SYS_ADMIN))
1860 return -EACCES;
1861 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
1862 return -EFAULT;
1863
1864 memset(&c, 0, sizeof(c));
1865 c.common.opcode = cmd.opcode;
1866 c.common.flags = cmd.flags;
1867 c.common.nsid = cpu_to_le32(cmd.nsid);
1868 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1869 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1870 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1871 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1872 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1873 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1874 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1875 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1876
1877 if (cmd.timeout_ms)
1878 timeout = msecs_to_jiffies(cmd.timeout_ms);
1879
1880 status = __nvme_submit_sync_cmd(ns ? ns->queue : dev->admin_q, &c,
1881 NULL, (void __user *)(uintptr_t)cmd.addr, cmd.data_len,
1882 &cmd.result, timeout);
1883 if (status >= 0) {
1884 if (put_user(cmd.result, &ucmd->result))
1885 return -EFAULT;
1886 }
1887
1888 return status;
1889 }
1890
1891 static int nvme_subsys_reset(struct nvme_dev *dev)
1892 {
1893 if (!dev->subsystem)
1894 return -ENOTTY;
1895
1896 writel(0x4E564D65, &dev->bar->nssr); /* "NVMe" */
1897 return 0;
1898 }
1899
1900 static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1901 unsigned long arg)
1902 {
1903 struct nvme_ns *ns = bdev->bd_disk->private_data;
1904
1905 switch (cmd) {
1906 case NVME_IOCTL_ID:
1907 force_successful_syscall_return();
1908 return ns->ns_id;
1909 case NVME_IOCTL_ADMIN_CMD:
1910 return nvme_user_cmd(ns->dev, NULL, (void __user *)arg);
1911 case NVME_IOCTL_IO_CMD:
1912 return nvme_user_cmd(ns->dev, ns, (void __user *)arg);
1913 case NVME_IOCTL_SUBMIT_IO:
1914 return nvme_submit_io(ns, (void __user *)arg);
1915 case SG_GET_VERSION_NUM:
1916 return nvme_sg_get_version_num((void __user *)arg);
1917 case SG_IO:
1918 return nvme_sg_io(ns, (void __user *)arg);
1919 default:
1920 return -ENOTTY;
1921 }
1922 }
1923
1924 #ifdef CONFIG_COMPAT
1925 static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1926 unsigned int cmd, unsigned long arg)
1927 {
1928 switch (cmd) {
1929 case SG_IO:
1930 return -ENOIOCTLCMD;
1931 }
1932 return nvme_ioctl(bdev, mode, cmd, arg);
1933 }
1934 #else
1935 #define nvme_compat_ioctl NULL
1936 #endif
1937
1938 static void nvme_free_dev(struct kref *kref);
1939 static void nvme_free_ns(struct kref *kref)
1940 {
1941 struct nvme_ns *ns = container_of(kref, struct nvme_ns, kref);
1942
1943 if (ns->type == NVME_NS_LIGHTNVM)
1944 nvme_nvm_unregister(ns->queue, ns->disk->disk_name);
1945
1946 spin_lock(&dev_list_lock);
1947 ns->disk->private_data = NULL;
1948 spin_unlock(&dev_list_lock);
1949
1950 kref_put(&ns->dev->kref, nvme_free_dev);
1951 put_disk(ns->disk);
1952 kfree(ns);
1953 }
1954
1955 static int nvme_open(struct block_device *bdev, fmode_t mode)
1956 {
1957 int ret = 0;
1958 struct nvme_ns *ns;
1959
1960 spin_lock(&dev_list_lock);
1961 ns = bdev->bd_disk->private_data;
1962 if (!ns)
1963 ret = -ENXIO;
1964 else if (!kref_get_unless_zero(&ns->kref))
1965 ret = -ENXIO;
1966 spin_unlock(&dev_list_lock);
1967
1968 return ret;
1969 }
1970
1971 static void nvme_release(struct gendisk *disk, fmode_t mode)
1972 {
1973 struct nvme_ns *ns = disk->private_data;
1974 kref_put(&ns->kref, nvme_free_ns);
1975 }
1976
1977 static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo)
1978 {
1979 /* some standard values */
1980 geo->heads = 1 << 6;
1981 geo->sectors = 1 << 5;
1982 geo->cylinders = get_capacity(bd->bd_disk) >> 11;
1983 return 0;
1984 }
1985
1986 static void nvme_config_discard(struct nvme_ns *ns)
1987 {
1988 u32 logical_block_size = queue_logical_block_size(ns->queue);
1989 ns->queue->limits.discard_zeroes_data = 0;
1990 ns->queue->limits.discard_alignment = logical_block_size;
1991 ns->queue->limits.discard_granularity = logical_block_size;
1992 blk_queue_max_discard_sectors(ns->queue, 0xffffffff);
1993 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
1994 }
1995
1996 static int nvme_revalidate_disk(struct gendisk *disk)
1997 {
1998 struct nvme_ns *ns = disk->private_data;
1999 struct nvme_dev *dev = ns->dev;
2000 struct nvme_id_ns *id;
2001 u8 lbaf, pi_type;
2002 u16 old_ms;
2003 unsigned short bs;
2004
2005 if (nvme_identify_ns(dev, ns->ns_id, &id)) {
2006 dev_warn(dev->dev, "%s: Identify failure nvme%dn%d\n", __func__,
2007 dev->instance, ns->ns_id);
2008 return -ENODEV;
2009 }
2010 if (id->ncap == 0) {
2011 kfree(id);
2012 return -ENODEV;
2013 }
2014
2015 if (nvme_nvm_ns_supported(ns, id) && ns->type != NVME_NS_LIGHTNVM) {
2016 if (nvme_nvm_register(ns->queue, disk->disk_name)) {
2017 dev_warn(dev->dev,
2018 "%s: LightNVM init failure\n", __func__);
2019 kfree(id);
2020 return -ENODEV;
2021 }
2022 ns->type = NVME_NS_LIGHTNVM;
2023 }
2024
2025 old_ms = ns->ms;
2026 lbaf = id->flbas & NVME_NS_FLBAS_LBA_MASK;
2027 ns->lba_shift = id->lbaf[lbaf].ds;
2028 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
2029 ns->ext = ns->ms && (id->flbas & NVME_NS_FLBAS_META_EXT);
2030
2031 /*
2032 * If identify namespace failed, use default 512 byte block size so
2033 * block layer can use before failing read/write for 0 capacity.
2034 */
2035 if (ns->lba_shift == 0)
2036 ns->lba_shift = 9;
2037 bs = 1 << ns->lba_shift;
2038
2039 /* XXX: PI implementation requires metadata equal t10 pi tuple size */
2040 pi_type = ns->ms == sizeof(struct t10_pi_tuple) ?
2041 id->dps & NVME_NS_DPS_PI_MASK : 0;
2042
2043 blk_mq_freeze_queue(disk->queue);
2044 if (blk_get_integrity(disk) && (ns->pi_type != pi_type ||
2045 ns->ms != old_ms ||
2046 bs != queue_logical_block_size(disk->queue) ||
2047 (ns->ms && ns->ext)))
2048 blk_integrity_unregister(disk);
2049
2050 ns->pi_type = pi_type;
2051 blk_queue_logical_block_size(ns->queue, bs);
2052
2053 if (ns->ms && !ns->ext)
2054 nvme_init_integrity(ns);
2055
2056 if ((ns->ms && !(ns->ms == 8 && ns->pi_type) &&
2057 !blk_get_integrity(disk)) ||
2058 ns->type == NVME_NS_LIGHTNVM)
2059 set_capacity(disk, 0);
2060 else
2061 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
2062
2063 if (dev->oncs & NVME_CTRL_ONCS_DSM)
2064 nvme_config_discard(ns);
2065 blk_mq_unfreeze_queue(disk->queue);
2066
2067 kfree(id);
2068 return 0;
2069 }
2070
2071 static char nvme_pr_type(enum pr_type type)
2072 {
2073 switch (type) {
2074 case PR_WRITE_EXCLUSIVE:
2075 return 1;
2076 case PR_EXCLUSIVE_ACCESS:
2077 return 2;
2078 case PR_WRITE_EXCLUSIVE_REG_ONLY:
2079 return 3;
2080 case PR_EXCLUSIVE_ACCESS_REG_ONLY:
2081 return 4;
2082 case PR_WRITE_EXCLUSIVE_ALL_REGS:
2083 return 5;
2084 case PR_EXCLUSIVE_ACCESS_ALL_REGS:
2085 return 6;
2086 default:
2087 return 0;
2088 }
2089 };
2090
2091 static int nvme_pr_command(struct block_device *bdev, u32 cdw10,
2092 u64 key, u64 sa_key, u8 op)
2093 {
2094 struct nvme_ns *ns = bdev->bd_disk->private_data;
2095 struct nvme_command c;
2096 u8 data[16] = { 0, };
2097
2098 put_unaligned_le64(key, &data[0]);
2099 put_unaligned_le64(sa_key, &data[8]);
2100
2101 memset(&c, 0, sizeof(c));
2102 c.common.opcode = op;
2103 c.common.nsid = cpu_to_le32(ns->ns_id);
2104 c.common.cdw10[0] = cpu_to_le32(cdw10);
2105
2106 return nvme_submit_sync_cmd(ns->queue, &c, data, 16);
2107 }
2108
2109 static int nvme_pr_register(struct block_device *bdev, u64 old,
2110 u64 new, unsigned flags)
2111 {
2112 u32 cdw10;
2113
2114 if (flags & ~PR_FL_IGNORE_KEY)
2115 return -EOPNOTSUPP;
2116
2117 cdw10 = old ? 2 : 0;
2118 cdw10 |= (flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0;
2119 cdw10 |= (1 << 30) | (1 << 31); /* PTPL=1 */
2120 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_register);
2121 }
2122
2123 static int nvme_pr_reserve(struct block_device *bdev, u64 key,
2124 enum pr_type type, unsigned flags)
2125 {
2126 u32 cdw10;
2127
2128 if (flags & ~PR_FL_IGNORE_KEY)
2129 return -EOPNOTSUPP;
2130
2131 cdw10 = nvme_pr_type(type) << 8;
2132 cdw10 |= ((flags & PR_FL_IGNORE_KEY) ? 1 << 3 : 0);
2133 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_acquire);
2134 }
2135
2136 static int nvme_pr_preempt(struct block_device *bdev, u64 old, u64 new,
2137 enum pr_type type, bool abort)
2138 {
2139 u32 cdw10 = nvme_pr_type(type) << 8 | abort ? 2 : 1;
2140 return nvme_pr_command(bdev, cdw10, old, new, nvme_cmd_resv_acquire);
2141 }
2142
2143 static int nvme_pr_clear(struct block_device *bdev, u64 key)
2144 {
2145 u32 cdw10 = 1 | (key ? 1 << 3 : 0);
2146 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_register);
2147 }
2148
2149 static int nvme_pr_release(struct block_device *bdev, u64 key, enum pr_type type)
2150 {
2151 u32 cdw10 = nvme_pr_type(type) << 8 | key ? 1 << 3 : 0;
2152 return nvme_pr_command(bdev, cdw10, key, 0, nvme_cmd_resv_release);
2153 }
2154
2155 static const struct pr_ops nvme_pr_ops = {
2156 .pr_register = nvme_pr_register,
2157 .pr_reserve = nvme_pr_reserve,
2158 .pr_release = nvme_pr_release,
2159 .pr_preempt = nvme_pr_preempt,
2160 .pr_clear = nvme_pr_clear,
2161 };
2162
2163 static const struct block_device_operations nvme_fops = {
2164 .owner = THIS_MODULE,
2165 .ioctl = nvme_ioctl,
2166 .compat_ioctl = nvme_compat_ioctl,
2167 .open = nvme_open,
2168 .release = nvme_release,
2169 .getgeo = nvme_getgeo,
2170 .revalidate_disk= nvme_revalidate_disk,
2171 .pr_ops = &nvme_pr_ops,
2172 };
2173
2174 static int nvme_kthread(void *data)
2175 {
2176 struct nvme_dev *dev, *next;
2177
2178 while (!kthread_should_stop()) {
2179 set_current_state(TASK_INTERRUPTIBLE);
2180 spin_lock(&dev_list_lock);
2181 list_for_each_entry_safe(dev, next, &dev_list, node) {
2182 int i;
2183 u32 csts = readl(&dev->bar->csts);
2184
2185 if ((dev->subsystem && (csts & NVME_CSTS_NSSRO)) ||
2186 csts & NVME_CSTS_CFS) {
2187 if (!__nvme_reset(dev)) {
2188 dev_warn(dev->dev,
2189 "Failed status: %x, reset controller\n",
2190 readl(&dev->bar->csts));
2191 }
2192 continue;
2193 }
2194 for (i = 0; i < dev->queue_count; i++) {
2195 struct nvme_queue *nvmeq = dev->queues[i];
2196 if (!nvmeq)
2197 continue;
2198 spin_lock_irq(&nvmeq->q_lock);
2199 nvme_process_cq(nvmeq);
2200
2201 while ((i == 0) && (dev->event_limit > 0)) {
2202 if (nvme_submit_async_admin_req(dev))
2203 break;
2204 dev->event_limit--;
2205 }
2206 spin_unlock_irq(&nvmeq->q_lock);
2207 }
2208 }
2209 spin_unlock(&dev_list_lock);
2210 schedule_timeout(round_jiffies_relative(HZ));
2211 }
2212 return 0;
2213 }
2214
2215 static void nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid)
2216 {
2217 struct nvme_ns *ns;
2218 struct gendisk *disk;
2219 int node = dev_to_node(dev->dev);
2220
2221 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
2222 if (!ns)
2223 return;
2224
2225 ns->queue = blk_mq_init_queue(&dev->tagset);
2226 if (IS_ERR(ns->queue))
2227 goto out_free_ns;
2228 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
2229 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
2230 ns->dev = dev;
2231 ns->queue->queuedata = ns;
2232
2233 disk = alloc_disk_node(0, node);
2234 if (!disk)
2235 goto out_free_queue;
2236
2237 kref_init(&ns->kref);
2238 ns->ns_id = nsid;
2239 ns->disk = disk;
2240 ns->lba_shift = 9; /* set to a default value for 512 until disk is validated */
2241 list_add_tail(&ns->list, &dev->namespaces);
2242
2243 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
2244 if (dev->max_hw_sectors) {
2245 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
2246 blk_queue_max_segments(ns->queue,
2247 ((dev->max_hw_sectors << 9) / dev->page_size) + 1);
2248 }
2249 if (dev->stripe_size)
2250 blk_queue_chunk_sectors(ns->queue, dev->stripe_size >> 9);
2251 if (dev->vwc & NVME_CTRL_VWC_PRESENT)
2252 blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA);
2253 blk_queue_virt_boundary(ns->queue, dev->page_size - 1);
2254
2255 disk->major = nvme_major;
2256 disk->first_minor = 0;
2257 disk->fops = &nvme_fops;
2258 disk->private_data = ns;
2259 disk->queue = ns->queue;
2260 disk->driverfs_dev = dev->device;
2261 disk->flags = GENHD_FL_EXT_DEVT;
2262 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
2263
2264 /*
2265 * Initialize capacity to 0 until we establish the namespace format and
2266 * setup integrity extentions if necessary. The revalidate_disk after
2267 * add_disk allows the driver to register with integrity if the format
2268 * requires it.
2269 */
2270 set_capacity(disk, 0);
2271 if (nvme_revalidate_disk(ns->disk))
2272 goto out_free_disk;
2273
2274 kref_get(&dev->kref);
2275 if (ns->type != NVME_NS_LIGHTNVM) {
2276 add_disk(ns->disk);
2277 if (ns->ms) {
2278 struct block_device *bd = bdget_disk(ns->disk, 0);
2279 if (!bd)
2280 return;
2281 if (blkdev_get(bd, FMODE_READ, NULL)) {
2282 bdput(bd);
2283 return;
2284 }
2285 blkdev_reread_part(bd);
2286 blkdev_put(bd, FMODE_READ);
2287 }
2288 }
2289 return;
2290 out_free_disk:
2291 kfree(disk);
2292 list_del(&ns->list);
2293 out_free_queue:
2294 blk_cleanup_queue(ns->queue);
2295 out_free_ns:
2296 kfree(ns);
2297 }
2298
2299 /*
2300 * Create I/O queues. Failing to create an I/O queue is not an issue,
2301 * we can continue with less than the desired amount of queues, and
2302 * even a controller without I/O queues an still be used to issue
2303 * admin commands. This might be useful to upgrade a buggy firmware
2304 * for example.
2305 */
2306 static void nvme_create_io_queues(struct nvme_dev *dev)
2307 {
2308 unsigned i;
2309
2310 for (i = dev->queue_count; i <= dev->max_qid; i++)
2311 if (!nvme_alloc_queue(dev, i, dev->q_depth))
2312 break;
2313
2314 for (i = dev->online_queues; i <= dev->queue_count - 1; i++)
2315 if (nvme_create_queue(dev->queues[i], i)) {
2316 nvme_free_queues(dev, i);
2317 break;
2318 }
2319 }
2320
2321 static int set_queue_count(struct nvme_dev *dev, int count)
2322 {
2323 int status;
2324 u32 result;
2325 u32 q_count = (count - 1) | ((count - 1) << 16);
2326
2327 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
2328 &result);
2329 if (status < 0)
2330 return status;
2331 if (status > 0) {
2332 dev_err(dev->dev, "Could not set queue count (%d)\n", status);
2333 return 0;
2334 }
2335 return min(result & 0xffff, result >> 16) + 1;
2336 }
2337
2338 static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
2339 {
2340 u64 szu, size, offset;
2341 u32 cmbloc;
2342 resource_size_t bar_size;
2343 struct pci_dev *pdev = to_pci_dev(dev->dev);
2344 void __iomem *cmb;
2345 dma_addr_t dma_addr;
2346
2347 if (!use_cmb_sqes)
2348 return NULL;
2349
2350 dev->cmbsz = readl(&dev->bar->cmbsz);
2351 if (!(NVME_CMB_SZ(dev->cmbsz)))
2352 return NULL;
2353
2354 cmbloc = readl(&dev->bar->cmbloc);
2355
2356 szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
2357 size = szu * NVME_CMB_SZ(dev->cmbsz);
2358 offset = szu * NVME_CMB_OFST(cmbloc);
2359 bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc));
2360
2361 if (offset > bar_size)
2362 return NULL;
2363
2364 /*
2365 * Controllers may support a CMB size larger than their BAR,
2366 * for example, due to being behind a bridge. Reduce the CMB to
2367 * the reported size of the BAR
2368 */
2369 if (size > bar_size - offset)
2370 size = bar_size - offset;
2371
2372 dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset;
2373 cmb = ioremap_wc(dma_addr, size);
2374 if (!cmb)
2375 return NULL;
2376
2377 dev->cmb_dma_addr = dma_addr;
2378 dev->cmb_size = size;
2379 return cmb;
2380 }
2381
2382 static inline void nvme_release_cmb(struct nvme_dev *dev)
2383 {
2384 if (dev->cmb) {
2385 iounmap(dev->cmb);
2386 dev->cmb = NULL;
2387 }
2388 }
2389
2390 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
2391 {
2392 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
2393 }
2394
2395 static int nvme_setup_io_queues(struct nvme_dev *dev)
2396 {
2397 struct nvme_queue *adminq = dev->queues[0];
2398 struct pci_dev *pdev = to_pci_dev(dev->dev);
2399 int result, i, vecs, nr_io_queues, size;
2400
2401 nr_io_queues = num_possible_cpus();
2402 result = set_queue_count(dev, nr_io_queues);
2403 if (result <= 0)
2404 return result;
2405 if (result < nr_io_queues)
2406 nr_io_queues = result;
2407
2408 if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
2409 result = nvme_cmb_qdepth(dev, nr_io_queues,
2410 sizeof(struct nvme_command));
2411 if (result > 0)
2412 dev->q_depth = result;
2413 else
2414 nvme_release_cmb(dev);
2415 }
2416
2417 size = db_bar_size(dev, nr_io_queues);
2418 if (size > 8192) {
2419 iounmap(dev->bar);
2420 do {
2421 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
2422 if (dev->bar)
2423 break;
2424 if (!--nr_io_queues)
2425 return -ENOMEM;
2426 size = db_bar_size(dev, nr_io_queues);
2427 } while (1);
2428 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2429 adminq->q_db = dev->dbs;
2430 }
2431
2432 /* Deregister the admin queue's interrupt */
2433 free_irq(dev->entry[0].vector, adminq);
2434
2435 /*
2436 * If we enable msix early due to not intx, disable it again before
2437 * setting up the full range we need.
2438 */
2439 if (!pdev->irq)
2440 pci_disable_msix(pdev);
2441
2442 for (i = 0; i < nr_io_queues; i++)
2443 dev->entry[i].entry = i;
2444 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
2445 if (vecs < 0) {
2446 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
2447 if (vecs < 0) {
2448 vecs = 1;
2449 } else {
2450 for (i = 0; i < vecs; i++)
2451 dev->entry[i].vector = i + pdev->irq;
2452 }
2453 }
2454
2455 /*
2456 * Should investigate if there's a performance win from allocating
2457 * more queues than interrupt vectors; it might allow the submission
2458 * path to scale better, even if the receive path is limited by the
2459 * number of interrupts.
2460 */
2461 nr_io_queues = vecs;
2462 dev->max_qid = nr_io_queues;
2463
2464 result = queue_request_irq(dev, adminq, adminq->irqname);
2465 if (result) {
2466 adminq->cq_vector = -1;
2467 goto free_queues;
2468 }
2469
2470 /* Free previously allocated queues that are no longer usable */
2471 nvme_free_queues(dev, nr_io_queues + 1);
2472 nvme_create_io_queues(dev);
2473
2474 return 0;
2475
2476 free_queues:
2477 nvme_free_queues(dev, 1);
2478 return result;
2479 }
2480
2481 static int ns_cmp(void *priv, struct list_head *a, struct list_head *b)
2482 {
2483 struct nvme_ns *nsa = container_of(a, struct nvme_ns, list);
2484 struct nvme_ns *nsb = container_of(b, struct nvme_ns, list);
2485
2486 return nsa->ns_id - nsb->ns_id;
2487 }
2488
2489 static struct nvme_ns *nvme_find_ns(struct nvme_dev *dev, unsigned nsid)
2490 {
2491 struct nvme_ns *ns;
2492
2493 list_for_each_entry(ns, &dev->namespaces, list) {
2494 if (ns->ns_id == nsid)
2495 return ns;
2496 if (ns->ns_id > nsid)
2497 break;
2498 }
2499 return NULL;
2500 }
2501
2502 static inline bool nvme_io_incapable(struct nvme_dev *dev)
2503 {
2504 return (!dev->bar || readl(&dev->bar->csts) & NVME_CSTS_CFS ||
2505 dev->online_queues < 2);
2506 }
2507
2508 static void nvme_ns_remove(struct nvme_ns *ns)
2509 {
2510 bool kill = nvme_io_incapable(ns->dev) && !blk_queue_dying(ns->queue);
2511
2512 if (kill)
2513 blk_set_queue_dying(ns->queue);
2514 if (ns->disk->flags & GENHD_FL_UP)
2515 del_gendisk(ns->disk);
2516 if (kill || !blk_queue_dying(ns->queue)) {
2517 blk_mq_abort_requeue_list(ns->queue);
2518 blk_cleanup_queue(ns->queue);
2519 }
2520 list_del_init(&ns->list);
2521 kref_put(&ns->kref, nvme_free_ns);
2522 }
2523
2524 static void nvme_scan_namespaces(struct nvme_dev *dev, unsigned nn)
2525 {
2526 struct nvme_ns *ns, *next;
2527 unsigned i;
2528
2529 for (i = 1; i <= nn; i++) {
2530 ns = nvme_find_ns(dev, i);
2531 if (ns) {
2532 if (revalidate_disk(ns->disk))
2533 nvme_ns_remove(ns);
2534 } else
2535 nvme_alloc_ns(dev, i);
2536 }
2537 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
2538 if (ns->ns_id > nn)
2539 nvme_ns_remove(ns);
2540 }
2541 list_sort(NULL, &dev->namespaces, ns_cmp);
2542 }
2543
2544 static void nvme_set_irq_hints(struct nvme_dev *dev)
2545 {
2546 struct nvme_queue *nvmeq;
2547 int i;
2548
2549 for (i = 0; i < dev->online_queues; i++) {
2550 nvmeq = dev->queues[i];
2551
2552 if (!nvmeq->tags || !(*nvmeq->tags))
2553 continue;
2554
2555 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
2556 blk_mq_tags_cpumask(*nvmeq->tags));
2557 }
2558 }
2559
2560 static void nvme_dev_scan(struct work_struct *work)
2561 {
2562 struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work);
2563 struct nvme_id_ctrl *ctrl;
2564
2565 if (!dev->tagset.tags)
2566 return;
2567 if (nvme_identify_ctrl(dev, &ctrl))
2568 return;
2569 nvme_scan_namespaces(dev, le32_to_cpup(&ctrl->nn));
2570 kfree(ctrl);
2571 nvme_set_irq_hints(dev);
2572 }
2573
2574 /*
2575 * Return: error value if an error occurred setting up the queues or calling
2576 * Identify Device. 0 if these succeeded, even if adding some of the
2577 * namespaces failed. At the moment, these failures are silent. TBD which
2578 * failures should be reported.
2579 */
2580 static int nvme_dev_add(struct nvme_dev *dev)
2581 {
2582 struct pci_dev *pdev = to_pci_dev(dev->dev);
2583 int res;
2584 struct nvme_id_ctrl *ctrl;
2585 int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
2586
2587 res = nvme_identify_ctrl(dev, &ctrl);
2588 if (res) {
2589 dev_err(dev->dev, "Identify Controller failed (%d)\n", res);
2590 return -EIO;
2591 }
2592
2593 dev->oncs = le16_to_cpup(&ctrl->oncs);
2594 dev->abort_limit = ctrl->acl + 1;
2595 dev->vwc = ctrl->vwc;
2596 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
2597 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
2598 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
2599 if (ctrl->mdts)
2600 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
2601 if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
2602 (pdev->device == 0x0953) && ctrl->vs[3]) {
2603 unsigned int max_hw_sectors;
2604
2605 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
2606 max_hw_sectors = dev->stripe_size >> (shift - 9);
2607 if (dev->max_hw_sectors) {
2608 dev->max_hw_sectors = min(max_hw_sectors,
2609 dev->max_hw_sectors);
2610 } else
2611 dev->max_hw_sectors = max_hw_sectors;
2612 }
2613 kfree(ctrl);
2614
2615 if (!dev->tagset.tags) {
2616 dev->tagset.ops = &nvme_mq_ops;
2617 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2618 dev->tagset.timeout = NVME_IO_TIMEOUT;
2619 dev->tagset.numa_node = dev_to_node(dev->dev);
2620 dev->tagset.queue_depth =
2621 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2622 dev->tagset.cmd_size = nvme_cmd_size(dev);
2623 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2624 dev->tagset.driver_data = dev;
2625
2626 if (blk_mq_alloc_tag_set(&dev->tagset))
2627 return 0;
2628 }
2629 schedule_work(&dev->scan_work);
2630 return 0;
2631 }
2632
2633 static int nvme_dev_map(struct nvme_dev *dev)
2634 {
2635 u64 cap;
2636 int bars, result = -ENOMEM;
2637 struct pci_dev *pdev = to_pci_dev(dev->dev);
2638
2639 if (pci_enable_device_mem(pdev))
2640 return result;
2641
2642 dev->entry[0].vector = pdev->irq;
2643 pci_set_master(pdev);
2644 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2645 if (!bars)
2646 goto disable_pci;
2647
2648 if (pci_request_selected_regions(pdev, bars, "nvme"))
2649 goto disable_pci;
2650
2651 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
2652 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
2653 goto disable;
2654
2655 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2656 if (!dev->bar)
2657 goto disable;
2658
2659 if (readl(&dev->bar->csts) == -1) {
2660 result = -ENODEV;
2661 goto unmap;
2662 }
2663
2664 /*
2665 * Some devices don't advertse INTx interrupts, pre-enable a single
2666 * MSIX vec for setup. We'll adjust this later.
2667 */
2668 if (!pdev->irq) {
2669 result = pci_enable_msix(pdev, dev->entry, 1);
2670 if (result < 0)
2671 goto unmap;
2672 }
2673
2674 cap = readq(&dev->bar->cap);
2675 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
2676 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
2677 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2678 if (readl(&dev->bar->vs) >= NVME_VS(1, 2))
2679 dev->cmb = nvme_map_cmb(dev);
2680
2681 return 0;
2682
2683 unmap:
2684 iounmap(dev->bar);
2685 dev->bar = NULL;
2686 disable:
2687 pci_release_regions(pdev);
2688 disable_pci:
2689 pci_disable_device(pdev);
2690 return result;
2691 }
2692
2693 static void nvme_dev_unmap(struct nvme_dev *dev)
2694 {
2695 struct pci_dev *pdev = to_pci_dev(dev->dev);
2696
2697 if (pdev->msi_enabled)
2698 pci_disable_msi(pdev);
2699 else if (pdev->msix_enabled)
2700 pci_disable_msix(pdev);
2701
2702 if (dev->bar) {
2703 iounmap(dev->bar);
2704 dev->bar = NULL;
2705 pci_release_regions(pdev);
2706 }
2707
2708 if (pci_is_enabled(pdev))
2709 pci_disable_device(pdev);
2710 }
2711
2712 struct nvme_delq_ctx {
2713 struct task_struct *waiter;
2714 struct kthread_worker *worker;
2715 atomic_t refcount;
2716 };
2717
2718 static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2719 {
2720 dq->waiter = current;
2721 mb();
2722
2723 for (;;) {
2724 set_current_state(TASK_KILLABLE);
2725 if (!atomic_read(&dq->refcount))
2726 break;
2727 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2728 fatal_signal_pending(current)) {
2729 /*
2730 * Disable the controller first since we can't trust it
2731 * at this point, but leave the admin queue enabled
2732 * until all queue deletion requests are flushed.
2733 * FIXME: This may take a while if there are more h/w
2734 * queues than admin tags.
2735 */
2736 set_current_state(TASK_RUNNING);
2737 nvme_disable_ctrl(dev, readq(&dev->bar->cap));
2738 nvme_clear_queue(dev->queues[0]);
2739 flush_kthread_worker(dq->worker);
2740 nvme_disable_queue(dev, 0);
2741 return;
2742 }
2743 }
2744 set_current_state(TASK_RUNNING);
2745 }
2746
2747 static void nvme_put_dq(struct nvme_delq_ctx *dq)
2748 {
2749 atomic_dec(&dq->refcount);
2750 if (dq->waiter)
2751 wake_up_process(dq->waiter);
2752 }
2753
2754 static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2755 {
2756 atomic_inc(&dq->refcount);
2757 return dq;
2758 }
2759
2760 static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2761 {
2762 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
2763 nvme_put_dq(dq);
2764 }
2765
2766 static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2767 kthread_work_func_t fn)
2768 {
2769 struct nvme_command c;
2770
2771 memset(&c, 0, sizeof(c));
2772 c.delete_queue.opcode = opcode;
2773 c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2774
2775 init_kthread_work(&nvmeq->cmdinfo.work, fn);
2776 return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo,
2777 ADMIN_TIMEOUT);
2778 }
2779
2780 static void nvme_del_cq_work_handler(struct kthread_work *work)
2781 {
2782 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2783 cmdinfo.work);
2784 nvme_del_queue_end(nvmeq);
2785 }
2786
2787 static int nvme_delete_cq(struct nvme_queue *nvmeq)
2788 {
2789 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2790 nvme_del_cq_work_handler);
2791 }
2792
2793 static void nvme_del_sq_work_handler(struct kthread_work *work)
2794 {
2795 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2796 cmdinfo.work);
2797 int status = nvmeq->cmdinfo.status;
2798
2799 if (!status)
2800 status = nvme_delete_cq(nvmeq);
2801 if (status)
2802 nvme_del_queue_end(nvmeq);
2803 }
2804
2805 static int nvme_delete_sq(struct nvme_queue *nvmeq)
2806 {
2807 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2808 nvme_del_sq_work_handler);
2809 }
2810
2811 static void nvme_del_queue_start(struct kthread_work *work)
2812 {
2813 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2814 cmdinfo.work);
2815 if (nvme_delete_sq(nvmeq))
2816 nvme_del_queue_end(nvmeq);
2817 }
2818
2819 static void nvme_disable_io_queues(struct nvme_dev *dev)
2820 {
2821 int i;
2822 DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2823 struct nvme_delq_ctx dq;
2824 struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2825 &worker, "nvme%d", dev->instance);
2826
2827 if (IS_ERR(kworker_task)) {
2828 dev_err(dev->dev,
2829 "Failed to create queue del task\n");
2830 for (i = dev->queue_count - 1; i > 0; i--)
2831 nvme_disable_queue(dev, i);
2832 return;
2833 }
2834
2835 dq.waiter = NULL;
2836 atomic_set(&dq.refcount, 0);
2837 dq.worker = &worker;
2838 for (i = dev->queue_count - 1; i > 0; i--) {
2839 struct nvme_queue *nvmeq = dev->queues[i];
2840
2841 if (nvme_suspend_queue(nvmeq))
2842 continue;
2843 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2844 nvmeq->cmdinfo.worker = dq.worker;
2845 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2846 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2847 }
2848 nvme_wait_dq(&dq, dev);
2849 kthread_stop(kworker_task);
2850 }
2851
2852 /*
2853 * Remove the node from the device list and check
2854 * for whether or not we need to stop the nvme_thread.
2855 */
2856 static void nvme_dev_list_remove(struct nvme_dev *dev)
2857 {
2858 struct task_struct *tmp = NULL;
2859
2860 spin_lock(&dev_list_lock);
2861 list_del_init(&dev->node);
2862 if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2863 tmp = nvme_thread;
2864 nvme_thread = NULL;
2865 }
2866 spin_unlock(&dev_list_lock);
2867
2868 if (tmp)
2869 kthread_stop(tmp);
2870 }
2871
2872 static void nvme_freeze_queues(struct nvme_dev *dev)
2873 {
2874 struct nvme_ns *ns;
2875
2876 list_for_each_entry(ns, &dev->namespaces, list) {
2877 blk_mq_freeze_queue_start(ns->queue);
2878
2879 spin_lock_irq(ns->queue->queue_lock);
2880 queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue);
2881 spin_unlock_irq(ns->queue->queue_lock);
2882
2883 blk_mq_cancel_requeue_work(ns->queue);
2884 blk_mq_stop_hw_queues(ns->queue);
2885 }
2886 }
2887
2888 static void nvme_unfreeze_queues(struct nvme_dev *dev)
2889 {
2890 struct nvme_ns *ns;
2891
2892 list_for_each_entry(ns, &dev->namespaces, list) {
2893 queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue);
2894 blk_mq_unfreeze_queue(ns->queue);
2895 blk_mq_start_stopped_hw_queues(ns->queue, true);
2896 blk_mq_kick_requeue_list(ns->queue);
2897 }
2898 }
2899
2900 static void nvme_dev_shutdown(struct nvme_dev *dev)
2901 {
2902 int i;
2903 u32 csts = -1;
2904
2905 nvme_dev_list_remove(dev);
2906
2907 if (dev->bar) {
2908 nvme_freeze_queues(dev);
2909 csts = readl(&dev->bar->csts);
2910 }
2911 if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
2912 for (i = dev->queue_count - 1; i >= 0; i--) {
2913 struct nvme_queue *nvmeq = dev->queues[i];
2914 nvme_suspend_queue(nvmeq);
2915 }
2916 } else {
2917 nvme_disable_io_queues(dev);
2918 nvme_shutdown_ctrl(dev);
2919 nvme_disable_queue(dev, 0);
2920 }
2921 nvme_dev_unmap(dev);
2922
2923 for (i = dev->queue_count - 1; i >= 0; i--)
2924 nvme_clear_queue(dev->queues[i]);
2925 }
2926
2927 static void nvme_dev_remove(struct nvme_dev *dev)
2928 {
2929 struct nvme_ns *ns, *next;
2930
2931 list_for_each_entry_safe(ns, next, &dev->namespaces, list)
2932 nvme_ns_remove(ns);
2933 }
2934
2935 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2936 {
2937 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2938 PAGE_SIZE, PAGE_SIZE, 0);
2939 if (!dev->prp_page_pool)
2940 return -ENOMEM;
2941
2942 /* Optimisation for I/Os between 4k and 128k */
2943 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2944 256, 256, 0);
2945 if (!dev->prp_small_pool) {
2946 dma_pool_destroy(dev->prp_page_pool);
2947 return -ENOMEM;
2948 }
2949 return 0;
2950 }
2951
2952 static void nvme_release_prp_pools(struct nvme_dev *dev)
2953 {
2954 dma_pool_destroy(dev->prp_page_pool);
2955 dma_pool_destroy(dev->prp_small_pool);
2956 }
2957
2958 static DEFINE_IDA(nvme_instance_ida);
2959
2960 static int nvme_set_instance(struct nvme_dev *dev)
2961 {
2962 int instance, error;
2963
2964 do {
2965 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2966 return -ENODEV;
2967
2968 spin_lock(&dev_list_lock);
2969 error = ida_get_new(&nvme_instance_ida, &instance);
2970 spin_unlock(&dev_list_lock);
2971 } while (error == -EAGAIN);
2972
2973 if (error)
2974 return -ENODEV;
2975
2976 dev->instance = instance;
2977 return 0;
2978 }
2979
2980 static void nvme_release_instance(struct nvme_dev *dev)
2981 {
2982 spin_lock(&dev_list_lock);
2983 ida_remove(&nvme_instance_ida, dev->instance);
2984 spin_unlock(&dev_list_lock);
2985 }
2986
2987 static void nvme_free_dev(struct kref *kref)
2988 {
2989 struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
2990
2991 put_device(dev->dev);
2992 put_device(dev->device);
2993 nvme_release_instance(dev);
2994 if (dev->tagset.tags)
2995 blk_mq_free_tag_set(&dev->tagset);
2996 if (dev->admin_q)
2997 blk_put_queue(dev->admin_q);
2998 kfree(dev->queues);
2999 kfree(dev->entry);
3000 kfree(dev);
3001 }
3002
3003 static int nvme_dev_open(struct inode *inode, struct file *f)
3004 {
3005 struct nvme_dev *dev;
3006 int instance = iminor(inode);
3007 int ret = -ENODEV;
3008
3009 spin_lock(&dev_list_lock);
3010 list_for_each_entry(dev, &dev_list, node) {
3011 if (dev->instance == instance) {
3012 if (!dev->admin_q) {
3013 ret = -EWOULDBLOCK;
3014 break;
3015 }
3016 if (!kref_get_unless_zero(&dev->kref))
3017 break;
3018 f->private_data = dev;
3019 ret = 0;
3020 break;
3021 }
3022 }
3023 spin_unlock(&dev_list_lock);
3024
3025 return ret;
3026 }
3027
3028 static int nvme_dev_release(struct inode *inode, struct file *f)
3029 {
3030 struct nvme_dev *dev = f->private_data;
3031 kref_put(&dev->kref, nvme_free_dev);
3032 return 0;
3033 }
3034
3035 static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
3036 {
3037 struct nvme_dev *dev = f->private_data;
3038 struct nvme_ns *ns;
3039
3040 switch (cmd) {
3041 case NVME_IOCTL_ADMIN_CMD:
3042 return nvme_user_cmd(dev, NULL, (void __user *)arg);
3043 case NVME_IOCTL_IO_CMD:
3044 if (list_empty(&dev->namespaces))
3045 return -ENOTTY;
3046 ns = list_first_entry(&dev->namespaces, struct nvme_ns, list);
3047 return nvme_user_cmd(dev, ns, (void __user *)arg);
3048 case NVME_IOCTL_RESET:
3049 dev_warn(dev->dev, "resetting controller\n");
3050 return nvme_reset(dev);
3051 case NVME_IOCTL_SUBSYS_RESET:
3052 return nvme_subsys_reset(dev);
3053 default:
3054 return -ENOTTY;
3055 }
3056 }
3057
3058 static const struct file_operations nvme_dev_fops = {
3059 .owner = THIS_MODULE,
3060 .open = nvme_dev_open,
3061 .release = nvme_dev_release,
3062 .unlocked_ioctl = nvme_dev_ioctl,
3063 .compat_ioctl = nvme_dev_ioctl,
3064 };
3065
3066 static void nvme_probe_work(struct work_struct *work)
3067 {
3068 struct nvme_dev *dev = container_of(work, struct nvme_dev, probe_work);
3069 bool start_thread = false;
3070 int result;
3071
3072 result = nvme_dev_map(dev);
3073 if (result)
3074 goto out;
3075
3076 result = nvme_configure_admin_queue(dev);
3077 if (result)
3078 goto unmap;
3079
3080 spin_lock(&dev_list_lock);
3081 if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
3082 start_thread = true;
3083 nvme_thread = NULL;
3084 }
3085 list_add(&dev->node, &dev_list);
3086 spin_unlock(&dev_list_lock);
3087
3088 if (start_thread) {
3089 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
3090 wake_up_all(&nvme_kthread_wait);
3091 } else
3092 wait_event_killable(nvme_kthread_wait, nvme_thread);
3093
3094 if (IS_ERR_OR_NULL(nvme_thread)) {
3095 result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
3096 goto disable;
3097 }
3098
3099 nvme_init_queue(dev->queues[0], 0);
3100 result = nvme_alloc_admin_tags(dev);
3101 if (result)
3102 goto disable;
3103
3104 result = nvme_setup_io_queues(dev);
3105 if (result)
3106 goto free_tags;
3107
3108 dev->event_limit = 1;
3109
3110 /*
3111 * Keep the controller around but remove all namespaces if we don't have
3112 * any working I/O queue.
3113 */
3114 if (dev->online_queues < 2) {
3115 dev_warn(dev->dev, "IO queues not created\n");
3116 nvme_dev_remove(dev);
3117 } else {
3118 nvme_unfreeze_queues(dev);
3119 nvme_dev_add(dev);
3120 }
3121
3122 return;
3123
3124 free_tags:
3125 nvme_dev_remove_admin(dev);
3126 blk_put_queue(dev->admin_q);
3127 dev->admin_q = NULL;
3128 dev->queues[0]->tags = NULL;
3129 disable:
3130 nvme_disable_queue(dev, 0);
3131 nvme_dev_list_remove(dev);
3132 unmap:
3133 nvme_dev_unmap(dev);
3134 out:
3135 if (!work_busy(&dev->reset_work))
3136 nvme_dead_ctrl(dev);
3137 }
3138
3139 static int nvme_remove_dead_ctrl(void *arg)
3140 {
3141 struct nvme_dev *dev = (struct nvme_dev *)arg;
3142 struct pci_dev *pdev = to_pci_dev(dev->dev);
3143
3144 if (pci_get_drvdata(pdev))
3145 pci_stop_and_remove_bus_device_locked(pdev);
3146 kref_put(&dev->kref, nvme_free_dev);
3147 return 0;
3148 }
3149
3150 static void nvme_dead_ctrl(struct nvme_dev *dev)
3151 {
3152 dev_warn(dev->dev, "Device failed to resume\n");
3153 kref_get(&dev->kref);
3154 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
3155 dev->instance))) {
3156 dev_err(dev->dev,
3157 "Failed to start controller remove task\n");
3158 kref_put(&dev->kref, nvme_free_dev);
3159 }
3160 }
3161
3162 static void nvme_reset_work(struct work_struct *ws)
3163 {
3164 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
3165 bool in_probe = work_busy(&dev->probe_work);
3166
3167 nvme_dev_shutdown(dev);
3168
3169 /* Synchronize with device probe so that work will see failure status
3170 * and exit gracefully without trying to schedule another reset */
3171 flush_work(&dev->probe_work);
3172
3173 /* Fail this device if reset occured during probe to avoid
3174 * infinite initialization loops. */
3175 if (in_probe) {
3176 nvme_dead_ctrl(dev);
3177 return;
3178 }
3179 /* Schedule device resume asynchronously so the reset work is available
3180 * to cleanup errors that may occur during reinitialization */
3181 schedule_work(&dev->probe_work);
3182 }
3183
3184 static int __nvme_reset(struct nvme_dev *dev)
3185 {
3186 if (work_pending(&dev->reset_work))
3187 return -EBUSY;
3188 list_del_init(&dev->node);
3189 queue_work(nvme_workq, &dev->reset_work);
3190 return 0;
3191 }
3192
3193 static int nvme_reset(struct nvme_dev *dev)
3194 {
3195 int ret;
3196
3197 if (!dev->admin_q || blk_queue_dying(dev->admin_q))
3198 return -ENODEV;
3199
3200 spin_lock(&dev_list_lock);
3201 ret = __nvme_reset(dev);
3202 spin_unlock(&dev_list_lock);
3203
3204 if (!ret) {
3205 flush_work(&dev->reset_work);
3206 flush_work(&dev->probe_work);
3207 return 0;
3208 }
3209
3210 return ret;
3211 }
3212
3213 static ssize_t nvme_sysfs_reset(struct device *dev,
3214 struct device_attribute *attr, const char *buf,
3215 size_t count)
3216 {
3217 struct nvme_dev *ndev = dev_get_drvdata(dev);
3218 int ret;
3219
3220 ret = nvme_reset(ndev);
3221 if (ret < 0)
3222 return ret;
3223
3224 return count;
3225 }
3226 static DEVICE_ATTR(reset_controller, S_IWUSR, NULL, nvme_sysfs_reset);
3227
3228 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3229 {
3230 int node, result = -ENOMEM;
3231 struct nvme_dev *dev;
3232
3233 node = dev_to_node(&pdev->dev);
3234 if (node == NUMA_NO_NODE)
3235 set_dev_node(&pdev->dev, 0);
3236
3237 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
3238 if (!dev)
3239 return -ENOMEM;
3240 dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
3241 GFP_KERNEL, node);
3242 if (!dev->entry)
3243 goto free;
3244 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
3245 GFP_KERNEL, node);
3246 if (!dev->queues)
3247 goto free;
3248
3249 INIT_LIST_HEAD(&dev->namespaces);
3250 INIT_WORK(&dev->reset_work, nvme_reset_work);
3251 dev->dev = get_device(&pdev->dev);
3252 pci_set_drvdata(pdev, dev);
3253 result = nvme_set_instance(dev);
3254 if (result)
3255 goto put_pci;
3256
3257 result = nvme_setup_prp_pools(dev);
3258 if (result)
3259 goto release;
3260
3261 kref_init(&dev->kref);
3262 dev->device = device_create(nvme_class, &pdev->dev,
3263 MKDEV(nvme_char_major, dev->instance),
3264 dev, "nvme%d", dev->instance);
3265 if (IS_ERR(dev->device)) {
3266 result = PTR_ERR(dev->device);
3267 goto release_pools;
3268 }
3269 get_device(dev->device);
3270 dev_set_drvdata(dev->device, dev);
3271
3272 result = device_create_file(dev->device, &dev_attr_reset_controller);
3273 if (result)
3274 goto put_dev;
3275
3276 INIT_LIST_HEAD(&dev->node);
3277 INIT_WORK(&dev->scan_work, nvme_dev_scan);
3278 INIT_WORK(&dev->probe_work, nvme_probe_work);
3279 schedule_work(&dev->probe_work);
3280 return 0;
3281
3282 put_dev:
3283 device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance));
3284 put_device(dev->device);
3285 release_pools:
3286 nvme_release_prp_pools(dev);
3287 release:
3288 nvme_release_instance(dev);
3289 put_pci:
3290 put_device(dev->dev);
3291 free:
3292 kfree(dev->queues);
3293 kfree(dev->entry);
3294 kfree(dev);
3295 return result;
3296 }
3297
3298 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
3299 {
3300 struct nvme_dev *dev = pci_get_drvdata(pdev);
3301
3302 if (prepare)
3303 nvme_dev_shutdown(dev);
3304 else
3305 schedule_work(&dev->probe_work);
3306 }
3307
3308 static void nvme_shutdown(struct pci_dev *pdev)
3309 {
3310 struct nvme_dev *dev = pci_get_drvdata(pdev);
3311 nvme_dev_shutdown(dev);
3312 }
3313
3314 static void nvme_remove(struct pci_dev *pdev)
3315 {
3316 struct nvme_dev *dev = pci_get_drvdata(pdev);
3317
3318 spin_lock(&dev_list_lock);
3319 list_del_init(&dev->node);
3320 spin_unlock(&dev_list_lock);
3321
3322 pci_set_drvdata(pdev, NULL);
3323 flush_work(&dev->probe_work);
3324 flush_work(&dev->reset_work);
3325 flush_work(&dev->scan_work);
3326 device_remove_file(dev->device, &dev_attr_reset_controller);
3327 nvme_dev_remove(dev);
3328 nvme_dev_shutdown(dev);
3329 nvme_dev_remove_admin(dev);
3330 device_destroy(nvme_class, MKDEV(nvme_char_major, dev->instance));
3331 nvme_free_queues(dev, 0);
3332 nvme_release_cmb(dev);
3333 nvme_release_prp_pools(dev);
3334 kref_put(&dev->kref, nvme_free_dev);
3335 }
3336
3337 /* These functions are yet to be implemented */
3338 #define nvme_error_detected NULL
3339 #define nvme_dump_registers NULL
3340 #define nvme_link_reset NULL
3341 #define nvme_slot_reset NULL
3342 #define nvme_error_resume NULL
3343
3344 #ifdef CONFIG_PM_SLEEP
3345 static int nvme_suspend(struct device *dev)
3346 {
3347 struct pci_dev *pdev = to_pci_dev(dev);
3348 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3349
3350 nvme_dev_shutdown(ndev);
3351 return 0;
3352 }
3353
3354 static int nvme_resume(struct device *dev)
3355 {
3356 struct pci_dev *pdev = to_pci_dev(dev);
3357 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3358
3359 schedule_work(&ndev->probe_work);
3360 return 0;
3361 }
3362 #endif
3363
3364 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
3365
3366 static const struct pci_error_handlers nvme_err_handler = {
3367 .error_detected = nvme_error_detected,
3368 .mmio_enabled = nvme_dump_registers,
3369 .link_reset = nvme_link_reset,
3370 .slot_reset = nvme_slot_reset,
3371 .resume = nvme_error_resume,
3372 .reset_notify = nvme_reset_notify,
3373 };
3374
3375 /* Move to pci_ids.h later */
3376 #define PCI_CLASS_STORAGE_EXPRESS 0x010802
3377
3378 static const struct pci_device_id nvme_id_table[] = {
3379 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3380 { 0, }
3381 };
3382 MODULE_DEVICE_TABLE(pci, nvme_id_table);
3383
3384 static struct pci_driver nvme_driver = {
3385 .name = "nvme",
3386 .id_table = nvme_id_table,
3387 .probe = nvme_probe,
3388 .remove = nvme_remove,
3389 .shutdown = nvme_shutdown,
3390 .driver = {
3391 .pm = &nvme_dev_pm_ops,
3392 },
3393 .err_handler = &nvme_err_handler,
3394 };
3395
3396 static int __init nvme_init(void)
3397 {
3398 int result;
3399
3400 init_waitqueue_head(&nvme_kthread_wait);
3401
3402 nvme_workq = create_singlethread_workqueue("nvme");
3403 if (!nvme_workq)
3404 return -ENOMEM;
3405
3406 result = register_blkdev(nvme_major, "nvme");
3407 if (result < 0)
3408 goto kill_workq;
3409 else if (result > 0)
3410 nvme_major = result;
3411
3412 result = __register_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme",
3413 &nvme_dev_fops);
3414 if (result < 0)
3415 goto unregister_blkdev;
3416 else if (result > 0)
3417 nvme_char_major = result;
3418
3419 nvme_class = class_create(THIS_MODULE, "nvme");
3420 if (IS_ERR(nvme_class)) {
3421 result = PTR_ERR(nvme_class);
3422 goto unregister_chrdev;
3423 }
3424
3425 result = pci_register_driver(&nvme_driver);
3426 if (result)
3427 goto destroy_class;
3428 return 0;
3429
3430 destroy_class:
3431 class_destroy(nvme_class);
3432 unregister_chrdev:
3433 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
3434 unregister_blkdev:
3435 unregister_blkdev(nvme_major, "nvme");
3436 kill_workq:
3437 destroy_workqueue(nvme_workq);
3438 return result;
3439 }
3440
3441 static void __exit nvme_exit(void)
3442 {
3443 pci_unregister_driver(&nvme_driver);
3444 unregister_blkdev(nvme_major, "nvme");
3445 destroy_workqueue(nvme_workq);
3446 class_destroy(nvme_class);
3447 __unregister_chrdev(nvme_char_major, 0, NVME_MINORS, "nvme");
3448 BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
3449 _nvme_check_size();
3450 }
3451
3452 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3453 MODULE_LICENSE("GPL");
3454 MODULE_VERSION("1.0");
3455 module_init(nvme_init);
3456 module_exit(nvme_exit);