2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/aer.h>
16 #include <linux/bitops.h>
17 #include <linux/blkdev.h>
18 #include <linux/blk-mq.h>
19 #include <linux/blk-mq-pci.h>
20 #include <linux/cpu.h>
21 #include <linux/delay.h>
22 #include <linux/dmi.h>
23 #include <linux/errno.h>
25 #include <linux/genhd.h>
26 #include <linux/hdreg.h>
27 #include <linux/idr.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
31 #include <linux/kdev_t.h>
32 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/moduleparam.h>
36 #include <linux/mutex.h>
37 #include <linux/pci.h>
38 #include <linux/poison.h>
39 #include <linux/ptrace.h>
40 #include <linux/sched.h>
41 #include <linux/slab.h>
42 #include <linux/t10-pi.h>
43 #include <linux/timer.h>
44 #include <linux/types.h>
45 #include <linux/io-64-nonatomic-lo-hi.h>
46 #include <asm/unaligned.h>
47 #include <linux/sed-opal.h>
51 #define NVME_Q_DEPTH 1024
52 #define NVME_AQ_DEPTH 256
53 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
54 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
57 * We handle AEN commands ourselves and don't even let the
58 * block layer know about them.
60 #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AERS)
62 static int use_threaded_interrupts
;
63 module_param(use_threaded_interrupts
, int, 0);
65 static bool use_cmb_sqes
= true;
66 module_param(use_cmb_sqes
, bool, 0644);
67 MODULE_PARM_DESC(use_cmb_sqes
, "use controller's memory buffer for I/O SQes");
69 static unsigned int max_host_mem_size_mb
= 128;
70 module_param(max_host_mem_size_mb
, uint
, 0444);
71 MODULE_PARM_DESC(max_host_mem_size_mb
,
72 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
74 static struct workqueue_struct
*nvme_workq
;
79 static int nvme_reset(struct nvme_dev
*dev
);
80 static void nvme_process_cq(struct nvme_queue
*nvmeq
);
81 static void nvme_dev_disable(struct nvme_dev
*dev
, bool shutdown
);
84 * Represents an NVM Express device. Each nvme_dev is a PCI function.
87 struct nvme_queue
**queues
;
88 struct blk_mq_tag_set tagset
;
89 struct blk_mq_tag_set admin_tagset
;
92 struct dma_pool
*prp_page_pool
;
93 struct dma_pool
*prp_small_pool
;
95 unsigned online_queues
;
100 struct work_struct reset_work
;
101 struct work_struct remove_work
;
102 struct timer_list watchdog_timer
;
103 struct mutex shutdown_lock
;
106 dma_addr_t cmb_dma_addr
;
110 struct nvme_ctrl ctrl
;
111 struct completion ioq_wait
;
113 /* shadow doorbell buffer support: */
115 dma_addr_t dbbuf_dbs_dma_addr
;
117 dma_addr_t dbbuf_eis_dma_addr
;
119 /* host memory buffer support: */
121 u32 nr_host_mem_descs
;
122 struct nvme_host_mem_buf_desc
*host_mem_descs
;
123 void **host_mem_desc_bufs
;
126 static inline unsigned int sq_idx(unsigned int qid
, u32 stride
)
128 return qid
* 2 * stride
;
131 static inline unsigned int cq_idx(unsigned int qid
, u32 stride
)
133 return (qid
* 2 + 1) * stride
;
136 static inline struct nvme_dev
*to_nvme_dev(struct nvme_ctrl
*ctrl
)
138 return container_of(ctrl
, struct nvme_dev
, ctrl
);
142 * An NVM Express queue. Each device has at least two (one for admin
143 * commands and one for I/O commands).
146 struct device
*q_dmadev
;
147 struct nvme_dev
*dev
;
149 struct nvme_command
*sq_cmds
;
150 struct nvme_command __iomem
*sq_cmds_io
;
151 volatile struct nvme_completion
*cqes
;
152 struct blk_mq_tags
**tags
;
153 dma_addr_t sq_dma_addr
;
154 dma_addr_t cq_dma_addr
;
170 * The nvme_iod describes the data in an I/O, including the list of PRP
171 * entries. You can't see it in this data structure because C doesn't let
172 * me express that. Use nvme_init_iod to ensure there's enough space
173 * allocated to store the PRP list.
176 struct nvme_request req
;
177 struct nvme_queue
*nvmeq
;
179 int npages
; /* In the PRP list. 0 means small pool in use */
180 int nents
; /* Used in scatterlist */
181 int length
; /* Of data, in bytes */
182 dma_addr_t first_dma
;
183 struct scatterlist meta_sg
; /* metadata requires single contiguous buffer */
184 struct scatterlist
*sg
;
185 struct scatterlist inline_sg
[0];
189 * Check we didin't inadvertently grow the command struct
191 static inline void _nvme_check_size(void)
193 BUILD_BUG_ON(sizeof(struct nvme_rw_command
) != 64);
194 BUILD_BUG_ON(sizeof(struct nvme_create_cq
) != 64);
195 BUILD_BUG_ON(sizeof(struct nvme_create_sq
) != 64);
196 BUILD_BUG_ON(sizeof(struct nvme_delete_queue
) != 64);
197 BUILD_BUG_ON(sizeof(struct nvme_features
) != 64);
198 BUILD_BUG_ON(sizeof(struct nvme_format_cmd
) != 64);
199 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd
) != 64);
200 BUILD_BUG_ON(sizeof(struct nvme_command
) != 64);
201 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl
) != 4096);
202 BUILD_BUG_ON(sizeof(struct nvme_id_ns
) != 4096);
203 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type
) != 64);
204 BUILD_BUG_ON(sizeof(struct nvme_smart_log
) != 512);
205 BUILD_BUG_ON(sizeof(struct nvme_dbbuf
) != 64);
208 static inline unsigned int nvme_dbbuf_size(u32 stride
)
210 return ((num_possible_cpus() + 1) * 8 * stride
);
213 static int nvme_dbbuf_dma_alloc(struct nvme_dev
*dev
)
215 unsigned int mem_size
= nvme_dbbuf_size(dev
->db_stride
);
220 dev
->dbbuf_dbs
= dma_alloc_coherent(dev
->dev
, mem_size
,
221 &dev
->dbbuf_dbs_dma_addr
,
225 dev
->dbbuf_eis
= dma_alloc_coherent(dev
->dev
, mem_size
,
226 &dev
->dbbuf_eis_dma_addr
,
228 if (!dev
->dbbuf_eis
) {
229 dma_free_coherent(dev
->dev
, mem_size
,
230 dev
->dbbuf_dbs
, dev
->dbbuf_dbs_dma_addr
);
231 dev
->dbbuf_dbs
= NULL
;
238 static void nvme_dbbuf_dma_free(struct nvme_dev
*dev
)
240 unsigned int mem_size
= nvme_dbbuf_size(dev
->db_stride
);
242 if (dev
->dbbuf_dbs
) {
243 dma_free_coherent(dev
->dev
, mem_size
,
244 dev
->dbbuf_dbs
, dev
->dbbuf_dbs_dma_addr
);
245 dev
->dbbuf_dbs
= NULL
;
247 if (dev
->dbbuf_eis
) {
248 dma_free_coherent(dev
->dev
, mem_size
,
249 dev
->dbbuf_eis
, dev
->dbbuf_eis_dma_addr
);
250 dev
->dbbuf_eis
= NULL
;
254 static void nvme_dbbuf_init(struct nvme_dev
*dev
,
255 struct nvme_queue
*nvmeq
, int qid
)
257 if (!dev
->dbbuf_dbs
|| !qid
)
260 nvmeq
->dbbuf_sq_db
= &dev
->dbbuf_dbs
[sq_idx(qid
, dev
->db_stride
)];
261 nvmeq
->dbbuf_cq_db
= &dev
->dbbuf_dbs
[cq_idx(qid
, dev
->db_stride
)];
262 nvmeq
->dbbuf_sq_ei
= &dev
->dbbuf_eis
[sq_idx(qid
, dev
->db_stride
)];
263 nvmeq
->dbbuf_cq_ei
= &dev
->dbbuf_eis
[cq_idx(qid
, dev
->db_stride
)];
266 static void nvme_dbbuf_set(struct nvme_dev
*dev
)
268 struct nvme_command c
;
273 memset(&c
, 0, sizeof(c
));
274 c
.dbbuf
.opcode
= nvme_admin_dbbuf
;
275 c
.dbbuf
.prp1
= cpu_to_le64(dev
->dbbuf_dbs_dma_addr
);
276 c
.dbbuf
.prp2
= cpu_to_le64(dev
->dbbuf_eis_dma_addr
);
278 if (nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0)) {
279 dev_warn(dev
->ctrl
.device
, "unable to set dbbuf\n");
280 /* Free memory and continue on */
281 nvme_dbbuf_dma_free(dev
);
285 static inline int nvme_dbbuf_need_event(u16 event_idx
, u16 new_idx
, u16 old
)
287 return (u16
)(new_idx
- event_idx
- 1) < (u16
)(new_idx
- old
);
290 /* Update dbbuf and return true if an MMIO is required */
291 static bool nvme_dbbuf_update_and_check_event(u16 value
, u32
*dbbuf_db
,
292 volatile u32
*dbbuf_ei
)
298 * Ensure that the queue is written before updating
299 * the doorbell in memory
303 old_value
= *dbbuf_db
;
306 if (!nvme_dbbuf_need_event(*dbbuf_ei
, value
, old_value
))
314 * Max size of iod being embedded in the request payload
316 #define NVME_INT_PAGES 2
317 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
320 * Will slightly overestimate the number of pages needed. This is OK
321 * as it only leads to a small amount of wasted memory for the lifetime of
324 static int nvme_npages(unsigned size
, struct nvme_dev
*dev
)
326 unsigned nprps
= DIV_ROUND_UP(size
+ dev
->ctrl
.page_size
,
327 dev
->ctrl
.page_size
);
328 return DIV_ROUND_UP(8 * nprps
, PAGE_SIZE
- 8);
331 static unsigned int nvme_iod_alloc_size(struct nvme_dev
*dev
,
332 unsigned int size
, unsigned int nseg
)
334 return sizeof(__le64
*) * nvme_npages(size
, dev
) +
335 sizeof(struct scatterlist
) * nseg
;
338 static unsigned int nvme_cmd_size(struct nvme_dev
*dev
)
340 return sizeof(struct nvme_iod
) +
341 nvme_iod_alloc_size(dev
, NVME_INT_BYTES(dev
), NVME_INT_PAGES
);
344 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
345 unsigned int hctx_idx
)
347 struct nvme_dev
*dev
= data
;
348 struct nvme_queue
*nvmeq
= dev
->queues
[0];
350 WARN_ON(hctx_idx
!= 0);
351 WARN_ON(dev
->admin_tagset
.tags
[0] != hctx
->tags
);
352 WARN_ON(nvmeq
->tags
);
354 hctx
->driver_data
= nvmeq
;
355 nvmeq
->tags
= &dev
->admin_tagset
.tags
[0];
359 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx
*hctx
, unsigned int hctx_idx
)
361 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
366 static int nvme_admin_init_request(struct blk_mq_tag_set
*set
,
367 struct request
*req
, unsigned int hctx_idx
,
368 unsigned int numa_node
)
370 struct nvme_dev
*dev
= set
->driver_data
;
371 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
372 struct nvme_queue
*nvmeq
= dev
->queues
[0];
379 static int nvme_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
380 unsigned int hctx_idx
)
382 struct nvme_dev
*dev
= data
;
383 struct nvme_queue
*nvmeq
= dev
->queues
[hctx_idx
+ 1];
386 nvmeq
->tags
= &dev
->tagset
.tags
[hctx_idx
];
388 WARN_ON(dev
->tagset
.tags
[hctx_idx
] != hctx
->tags
);
389 hctx
->driver_data
= nvmeq
;
393 static int nvme_init_request(struct blk_mq_tag_set
*set
, struct request
*req
,
394 unsigned int hctx_idx
, unsigned int numa_node
)
396 struct nvme_dev
*dev
= set
->driver_data
;
397 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
398 struct nvme_queue
*nvmeq
= dev
->queues
[hctx_idx
+ 1];
405 static int nvme_pci_map_queues(struct blk_mq_tag_set
*set
)
407 struct nvme_dev
*dev
= set
->driver_data
;
409 return blk_mq_pci_map_queues(set
, to_pci_dev(dev
->dev
));
413 * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
414 * @nvmeq: The queue to use
415 * @cmd: The command to send
417 * Safe to use from interrupt context
419 static void __nvme_submit_cmd(struct nvme_queue
*nvmeq
,
420 struct nvme_command
*cmd
)
422 u16 tail
= nvmeq
->sq_tail
;
424 if (nvmeq
->sq_cmds_io
)
425 memcpy_toio(&nvmeq
->sq_cmds_io
[tail
], cmd
, sizeof(*cmd
));
427 memcpy(&nvmeq
->sq_cmds
[tail
], cmd
, sizeof(*cmd
));
429 if (++tail
== nvmeq
->q_depth
)
431 if (nvme_dbbuf_update_and_check_event(tail
, nvmeq
->dbbuf_sq_db
,
433 writel(tail
, nvmeq
->q_db
);
434 nvmeq
->sq_tail
= tail
;
437 static __le64
**iod_list(struct request
*req
)
439 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
440 return (__le64
**)(iod
->sg
+ blk_rq_nr_phys_segments(req
));
443 static blk_status_t
nvme_init_iod(struct request
*rq
, struct nvme_dev
*dev
)
445 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(rq
);
446 int nseg
= blk_rq_nr_phys_segments(rq
);
447 unsigned int size
= blk_rq_payload_bytes(rq
);
449 if (nseg
> NVME_INT_PAGES
|| size
> NVME_INT_BYTES(dev
)) {
450 iod
->sg
= kmalloc(nvme_iod_alloc_size(dev
, size
, nseg
), GFP_ATOMIC
);
452 return BLK_STS_RESOURCE
;
454 iod
->sg
= iod
->inline_sg
;
465 static void nvme_free_iod(struct nvme_dev
*dev
, struct request
*req
)
467 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
468 const int last_prp
= dev
->ctrl
.page_size
/ 8 - 1;
470 __le64
**list
= iod_list(req
);
471 dma_addr_t prp_dma
= iod
->first_dma
;
473 if (iod
->npages
== 0)
474 dma_pool_free(dev
->prp_small_pool
, list
[0], prp_dma
);
475 for (i
= 0; i
< iod
->npages
; i
++) {
476 __le64
*prp_list
= list
[i
];
477 dma_addr_t next_prp_dma
= le64_to_cpu(prp_list
[last_prp
]);
478 dma_pool_free(dev
->prp_page_pool
, prp_list
, prp_dma
);
479 prp_dma
= next_prp_dma
;
482 if (iod
->sg
!= iod
->inline_sg
)
486 #ifdef CONFIG_BLK_DEV_INTEGRITY
487 static void nvme_dif_prep(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
489 if (be32_to_cpu(pi
->ref_tag
) == v
)
490 pi
->ref_tag
= cpu_to_be32(p
);
493 static void nvme_dif_complete(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
495 if (be32_to_cpu(pi
->ref_tag
) == p
)
496 pi
->ref_tag
= cpu_to_be32(v
);
500 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
502 * The virtual start sector is the one that was originally submitted by the
503 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
504 * start sector may be different. Remap protection information to match the
505 * physical LBA on writes, and back to the original seed on reads.
507 * Type 0 and 3 do not have a ref tag, so no remapping required.
509 static void nvme_dif_remap(struct request
*req
,
510 void (*dif_swap
)(u32 p
, u32 v
, struct t10_pi_tuple
*pi
))
512 struct nvme_ns
*ns
= req
->rq_disk
->private_data
;
513 struct bio_integrity_payload
*bip
;
514 struct t10_pi_tuple
*pi
;
516 u32 i
, nlb
, ts
, phys
, virt
;
518 if (!ns
->pi_type
|| ns
->pi_type
== NVME_NS_DPS_PI_TYPE3
)
521 bip
= bio_integrity(req
->bio
);
525 pmap
= kmap_atomic(bip
->bip_vec
->bv_page
) + bip
->bip_vec
->bv_offset
;
528 virt
= bip_get_seed(bip
);
529 phys
= nvme_block_nr(ns
, blk_rq_pos(req
));
530 nlb
= (blk_rq_bytes(req
) >> ns
->lba_shift
);
531 ts
= ns
->disk
->queue
->integrity
.tuple_size
;
533 for (i
= 0; i
< nlb
; i
++, virt
++, phys
++) {
534 pi
= (struct t10_pi_tuple
*)p
;
535 dif_swap(phys
, virt
, pi
);
540 #else /* CONFIG_BLK_DEV_INTEGRITY */
541 static void nvme_dif_remap(struct request
*req
,
542 void (*dif_swap
)(u32 p
, u32 v
, struct t10_pi_tuple
*pi
))
545 static void nvme_dif_prep(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
548 static void nvme_dif_complete(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
553 static bool nvme_setup_prps(struct nvme_dev
*dev
, struct request
*req
)
555 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
556 struct dma_pool
*pool
;
557 int length
= blk_rq_payload_bytes(req
);
558 struct scatterlist
*sg
= iod
->sg
;
559 int dma_len
= sg_dma_len(sg
);
560 u64 dma_addr
= sg_dma_address(sg
);
561 u32 page_size
= dev
->ctrl
.page_size
;
562 int offset
= dma_addr
& (page_size
- 1);
564 __le64
**list
= iod_list(req
);
568 length
-= (page_size
- offset
);
572 dma_len
-= (page_size
- offset
);
574 dma_addr
+= (page_size
- offset
);
577 dma_addr
= sg_dma_address(sg
);
578 dma_len
= sg_dma_len(sg
);
581 if (length
<= page_size
) {
582 iod
->first_dma
= dma_addr
;
586 nprps
= DIV_ROUND_UP(length
, page_size
);
587 if (nprps
<= (256 / 8)) {
588 pool
= dev
->prp_small_pool
;
591 pool
= dev
->prp_page_pool
;
595 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
597 iod
->first_dma
= dma_addr
;
602 iod
->first_dma
= prp_dma
;
605 if (i
== page_size
>> 3) {
606 __le64
*old_prp_list
= prp_list
;
607 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
610 list
[iod
->npages
++] = prp_list
;
611 prp_list
[0] = old_prp_list
[i
- 1];
612 old_prp_list
[i
- 1] = cpu_to_le64(prp_dma
);
615 prp_list
[i
++] = cpu_to_le64(dma_addr
);
616 dma_len
-= page_size
;
617 dma_addr
+= page_size
;
625 dma_addr
= sg_dma_address(sg
);
626 dma_len
= sg_dma_len(sg
);
632 static blk_status_t
nvme_map_data(struct nvme_dev
*dev
, struct request
*req
,
633 struct nvme_command
*cmnd
)
635 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
636 struct request_queue
*q
= req
->q
;
637 enum dma_data_direction dma_dir
= rq_data_dir(req
) ?
638 DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
639 blk_status_t ret
= BLK_STS_IOERR
;
641 sg_init_table(iod
->sg
, blk_rq_nr_phys_segments(req
));
642 iod
->nents
= blk_rq_map_sg(q
, req
, iod
->sg
);
646 ret
= BLK_STS_RESOURCE
;
647 if (!dma_map_sg_attrs(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
,
651 if (!nvme_setup_prps(dev
, req
))
655 if (blk_integrity_rq(req
)) {
656 if (blk_rq_count_integrity_sg(q
, req
->bio
) != 1)
659 sg_init_table(&iod
->meta_sg
, 1);
660 if (blk_rq_map_integrity_sg(q
, req
->bio
, &iod
->meta_sg
) != 1)
663 if (rq_data_dir(req
))
664 nvme_dif_remap(req
, nvme_dif_prep
);
666 if (!dma_map_sg(dev
->dev
, &iod
->meta_sg
, 1, dma_dir
))
670 cmnd
->rw
.dptr
.prp1
= cpu_to_le64(sg_dma_address(iod
->sg
));
671 cmnd
->rw
.dptr
.prp2
= cpu_to_le64(iod
->first_dma
);
672 if (blk_integrity_rq(req
))
673 cmnd
->rw
.metadata
= cpu_to_le64(sg_dma_address(&iod
->meta_sg
));
677 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
);
682 static void nvme_unmap_data(struct nvme_dev
*dev
, struct request
*req
)
684 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
685 enum dma_data_direction dma_dir
= rq_data_dir(req
) ?
686 DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
689 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
);
690 if (blk_integrity_rq(req
)) {
691 if (!rq_data_dir(req
))
692 nvme_dif_remap(req
, nvme_dif_complete
);
693 dma_unmap_sg(dev
->dev
, &iod
->meta_sg
, 1, dma_dir
);
697 nvme_cleanup_cmd(req
);
698 nvme_free_iod(dev
, req
);
702 * NOTE: ns is NULL when called on the admin queue.
704 static blk_status_t
nvme_queue_rq(struct blk_mq_hw_ctx
*hctx
,
705 const struct blk_mq_queue_data
*bd
)
707 struct nvme_ns
*ns
= hctx
->queue
->queuedata
;
708 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
709 struct nvme_dev
*dev
= nvmeq
->dev
;
710 struct request
*req
= bd
->rq
;
711 struct nvme_command cmnd
;
712 blk_status_t ret
= BLK_STS_OK
;
715 * If formated with metadata, require the block layer provide a buffer
716 * unless this namespace is formated such that the metadata can be
717 * stripped/generated by the controller with PRACT=1.
719 if (ns
&& ns
->ms
&& !blk_integrity_rq(req
)) {
720 if (!(ns
->pi_type
&& ns
->ms
== 8) &&
721 !blk_rq_is_passthrough(req
))
722 return BLK_STS_NOTSUPP
;
725 ret
= nvme_setup_cmd(ns
, req
, &cmnd
);
729 ret
= nvme_init_iod(req
, dev
);
733 if (blk_rq_nr_phys_segments(req
)) {
734 ret
= nvme_map_data(dev
, req
, &cmnd
);
736 goto out_cleanup_iod
;
739 blk_mq_start_request(req
);
741 spin_lock_irq(&nvmeq
->q_lock
);
742 if (unlikely(nvmeq
->cq_vector
< 0)) {
744 spin_unlock_irq(&nvmeq
->q_lock
);
745 goto out_cleanup_iod
;
747 __nvme_submit_cmd(nvmeq
, &cmnd
);
748 nvme_process_cq(nvmeq
);
749 spin_unlock_irq(&nvmeq
->q_lock
);
752 nvme_free_iod(dev
, req
);
754 nvme_cleanup_cmd(req
);
758 static void nvme_pci_complete_rq(struct request
*req
)
760 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
762 nvme_unmap_data(iod
->nvmeq
->dev
, req
);
763 nvme_complete_rq(req
);
766 /* We read the CQE phase first to check if the rest of the entry is valid */
767 static inline bool nvme_cqe_valid(struct nvme_queue
*nvmeq
, u16 head
,
770 return (le16_to_cpu(nvmeq
->cqes
[head
].status
) & 1) == phase
;
773 static void __nvme_process_cq(struct nvme_queue
*nvmeq
, unsigned int *tag
)
777 head
= nvmeq
->cq_head
;
778 phase
= nvmeq
->cq_phase
;
780 while (nvme_cqe_valid(nvmeq
, head
, phase
)) {
781 struct nvme_completion cqe
= nvmeq
->cqes
[head
];
784 if (++head
== nvmeq
->q_depth
) {
789 if (tag
&& *tag
== cqe
.command_id
)
792 if (unlikely(cqe
.command_id
>= nvmeq
->q_depth
)) {
793 dev_warn(nvmeq
->dev
->ctrl
.device
,
794 "invalid id %d completed on queue %d\n",
795 cqe
.command_id
, le16_to_cpu(cqe
.sq_id
));
800 * AEN requests are special as they don't time out and can
801 * survive any kind of queue freeze and often don't respond to
802 * aborts. We don't even bother to allocate a struct request
803 * for them but rather special case them here.
805 if (unlikely(nvmeq
->qid
== 0 &&
806 cqe
.command_id
>= NVME_AQ_BLKMQ_DEPTH
)) {
807 nvme_complete_async_event(&nvmeq
->dev
->ctrl
,
808 cqe
.status
, &cqe
.result
);
812 req
= blk_mq_tag_to_rq(*nvmeq
->tags
, cqe
.command_id
);
813 nvme_end_request(req
, cqe
.status
, cqe
.result
);
816 if (head
== nvmeq
->cq_head
&& phase
== nvmeq
->cq_phase
)
819 if (likely(nvmeq
->cq_vector
>= 0))
820 if (nvme_dbbuf_update_and_check_event(head
, nvmeq
->dbbuf_cq_db
,
822 writel(head
, nvmeq
->q_db
+ nvmeq
->dev
->db_stride
);
823 nvmeq
->cq_head
= head
;
824 nvmeq
->cq_phase
= phase
;
829 static void nvme_process_cq(struct nvme_queue
*nvmeq
)
831 __nvme_process_cq(nvmeq
, NULL
);
834 static irqreturn_t
nvme_irq(int irq
, void *data
)
837 struct nvme_queue
*nvmeq
= data
;
838 spin_lock(&nvmeq
->q_lock
);
839 nvme_process_cq(nvmeq
);
840 result
= nvmeq
->cqe_seen
? IRQ_HANDLED
: IRQ_NONE
;
842 spin_unlock(&nvmeq
->q_lock
);
846 static irqreturn_t
nvme_irq_check(int irq
, void *data
)
848 struct nvme_queue
*nvmeq
= data
;
849 if (nvme_cqe_valid(nvmeq
, nvmeq
->cq_head
, nvmeq
->cq_phase
))
850 return IRQ_WAKE_THREAD
;
854 static int __nvme_poll(struct nvme_queue
*nvmeq
, unsigned int tag
)
856 if (nvme_cqe_valid(nvmeq
, nvmeq
->cq_head
, nvmeq
->cq_phase
)) {
857 spin_lock_irq(&nvmeq
->q_lock
);
858 __nvme_process_cq(nvmeq
, &tag
);
859 spin_unlock_irq(&nvmeq
->q_lock
);
868 static int nvme_poll(struct blk_mq_hw_ctx
*hctx
, unsigned int tag
)
870 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
872 return __nvme_poll(nvmeq
, tag
);
875 static void nvme_pci_submit_async_event(struct nvme_ctrl
*ctrl
, int aer_idx
)
877 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
878 struct nvme_queue
*nvmeq
= dev
->queues
[0];
879 struct nvme_command c
;
881 memset(&c
, 0, sizeof(c
));
882 c
.common
.opcode
= nvme_admin_async_event
;
883 c
.common
.command_id
= NVME_AQ_BLKMQ_DEPTH
+ aer_idx
;
885 spin_lock_irq(&nvmeq
->q_lock
);
886 __nvme_submit_cmd(nvmeq
, &c
);
887 spin_unlock_irq(&nvmeq
->q_lock
);
890 static int adapter_delete_queue(struct nvme_dev
*dev
, u8 opcode
, u16 id
)
892 struct nvme_command c
;
894 memset(&c
, 0, sizeof(c
));
895 c
.delete_queue
.opcode
= opcode
;
896 c
.delete_queue
.qid
= cpu_to_le16(id
);
898 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
901 static int adapter_alloc_cq(struct nvme_dev
*dev
, u16 qid
,
902 struct nvme_queue
*nvmeq
)
904 struct nvme_command c
;
905 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_CQ_IRQ_ENABLED
;
908 * Note: we (ab)use the fact the the prp fields survive if no data
909 * is attached to the request.
911 memset(&c
, 0, sizeof(c
));
912 c
.create_cq
.opcode
= nvme_admin_create_cq
;
913 c
.create_cq
.prp1
= cpu_to_le64(nvmeq
->cq_dma_addr
);
914 c
.create_cq
.cqid
= cpu_to_le16(qid
);
915 c
.create_cq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
916 c
.create_cq
.cq_flags
= cpu_to_le16(flags
);
917 c
.create_cq
.irq_vector
= cpu_to_le16(nvmeq
->cq_vector
);
919 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
922 static int adapter_alloc_sq(struct nvme_dev
*dev
, u16 qid
,
923 struct nvme_queue
*nvmeq
)
925 struct nvme_command c
;
926 int flags
= NVME_QUEUE_PHYS_CONTIG
;
929 * Note: we (ab)use the fact the the prp fields survive if no data
930 * is attached to the request.
932 memset(&c
, 0, sizeof(c
));
933 c
.create_sq
.opcode
= nvme_admin_create_sq
;
934 c
.create_sq
.prp1
= cpu_to_le64(nvmeq
->sq_dma_addr
);
935 c
.create_sq
.sqid
= cpu_to_le16(qid
);
936 c
.create_sq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
937 c
.create_sq
.sq_flags
= cpu_to_le16(flags
);
938 c
.create_sq
.cqid
= cpu_to_le16(qid
);
940 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
943 static int adapter_delete_cq(struct nvme_dev
*dev
, u16 cqid
)
945 return adapter_delete_queue(dev
, nvme_admin_delete_cq
, cqid
);
948 static int adapter_delete_sq(struct nvme_dev
*dev
, u16 sqid
)
950 return adapter_delete_queue(dev
, nvme_admin_delete_sq
, sqid
);
953 static void abort_endio(struct request
*req
, blk_status_t error
)
955 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
956 struct nvme_queue
*nvmeq
= iod
->nvmeq
;
958 dev_warn(nvmeq
->dev
->ctrl
.device
,
959 "Abort status: 0x%x", nvme_req(req
)->status
);
960 atomic_inc(&nvmeq
->dev
->ctrl
.abort_limit
);
961 blk_mq_free_request(req
);
964 static enum blk_eh_timer_return
nvme_timeout(struct request
*req
, bool reserved
)
966 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
967 struct nvme_queue
*nvmeq
= iod
->nvmeq
;
968 struct nvme_dev
*dev
= nvmeq
->dev
;
969 struct request
*abort_req
;
970 struct nvme_command cmd
;
973 * Did we miss an interrupt?
975 if (__nvme_poll(nvmeq
, req
->tag
)) {
976 dev_warn(dev
->ctrl
.device
,
977 "I/O %d QID %d timeout, completion polled\n",
978 req
->tag
, nvmeq
->qid
);
979 return BLK_EH_HANDLED
;
983 * Shutdown immediately if controller times out while starting. The
984 * reset work will see the pci device disabled when it gets the forced
985 * cancellation error. All outstanding requests are completed on
986 * shutdown, so we return BLK_EH_HANDLED.
988 if (dev
->ctrl
.state
== NVME_CTRL_RESETTING
) {
989 dev_warn(dev
->ctrl
.device
,
990 "I/O %d QID %d timeout, disable controller\n",
991 req
->tag
, nvmeq
->qid
);
992 nvme_dev_disable(dev
, false);
993 nvme_req(req
)->flags
|= NVME_REQ_CANCELLED
;
994 return BLK_EH_HANDLED
;
998 * Shutdown the controller immediately and schedule a reset if the
999 * command was already aborted once before and still hasn't been
1000 * returned to the driver, or if this is the admin queue.
1002 if (!nvmeq
->qid
|| iod
->aborted
) {
1003 dev_warn(dev
->ctrl
.device
,
1004 "I/O %d QID %d timeout, reset controller\n",
1005 req
->tag
, nvmeq
->qid
);
1006 nvme_dev_disable(dev
, false);
1010 * Mark the request as handled, since the inline shutdown
1011 * forces all outstanding requests to complete.
1013 nvme_req(req
)->flags
|= NVME_REQ_CANCELLED
;
1014 return BLK_EH_HANDLED
;
1017 if (atomic_dec_return(&dev
->ctrl
.abort_limit
) < 0) {
1018 atomic_inc(&dev
->ctrl
.abort_limit
);
1019 return BLK_EH_RESET_TIMER
;
1023 memset(&cmd
, 0, sizeof(cmd
));
1024 cmd
.abort
.opcode
= nvme_admin_abort_cmd
;
1025 cmd
.abort
.cid
= req
->tag
;
1026 cmd
.abort
.sqid
= cpu_to_le16(nvmeq
->qid
);
1028 dev_warn(nvmeq
->dev
->ctrl
.device
,
1029 "I/O %d QID %d timeout, aborting\n",
1030 req
->tag
, nvmeq
->qid
);
1032 abort_req
= nvme_alloc_request(dev
->ctrl
.admin_q
, &cmd
,
1033 BLK_MQ_REQ_NOWAIT
, NVME_QID_ANY
);
1034 if (IS_ERR(abort_req
)) {
1035 atomic_inc(&dev
->ctrl
.abort_limit
);
1036 return BLK_EH_RESET_TIMER
;
1039 abort_req
->timeout
= ADMIN_TIMEOUT
;
1040 abort_req
->end_io_data
= NULL
;
1041 blk_execute_rq_nowait(abort_req
->q
, NULL
, abort_req
, 0, abort_endio
);
1044 * The aborted req will be completed on receiving the abort req.
1045 * We enable the timer again. If hit twice, it'll cause a device reset,
1046 * as the device then is in a faulty state.
1048 return BLK_EH_RESET_TIMER
;
1051 static void nvme_free_queue(struct nvme_queue
*nvmeq
)
1053 dma_free_coherent(nvmeq
->q_dmadev
, CQ_SIZE(nvmeq
->q_depth
),
1054 (void *)nvmeq
->cqes
, nvmeq
->cq_dma_addr
);
1056 dma_free_coherent(nvmeq
->q_dmadev
, SQ_SIZE(nvmeq
->q_depth
),
1057 nvmeq
->sq_cmds
, nvmeq
->sq_dma_addr
);
1061 static void nvme_free_queues(struct nvme_dev
*dev
, int lowest
)
1065 for (i
= dev
->queue_count
- 1; i
>= lowest
; i
--) {
1066 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
1068 dev
->queues
[i
] = NULL
;
1069 nvme_free_queue(nvmeq
);
1074 * nvme_suspend_queue - put queue into suspended state
1075 * @nvmeq - queue to suspend
1077 static int nvme_suspend_queue(struct nvme_queue
*nvmeq
)
1081 spin_lock_irq(&nvmeq
->q_lock
);
1082 if (nvmeq
->cq_vector
== -1) {
1083 spin_unlock_irq(&nvmeq
->q_lock
);
1086 vector
= nvmeq
->cq_vector
;
1087 nvmeq
->dev
->online_queues
--;
1088 nvmeq
->cq_vector
= -1;
1089 spin_unlock_irq(&nvmeq
->q_lock
);
1091 if (!nvmeq
->qid
&& nvmeq
->dev
->ctrl
.admin_q
)
1092 blk_mq_stop_hw_queues(nvmeq
->dev
->ctrl
.admin_q
);
1094 pci_free_irq(to_pci_dev(nvmeq
->dev
->dev
), vector
, nvmeq
);
1099 static void nvme_disable_admin_queue(struct nvme_dev
*dev
, bool shutdown
)
1101 struct nvme_queue
*nvmeq
= dev
->queues
[0];
1105 if (nvme_suspend_queue(nvmeq
))
1109 nvme_shutdown_ctrl(&dev
->ctrl
);
1111 nvme_disable_ctrl(&dev
->ctrl
, lo_hi_readq(
1112 dev
->bar
+ NVME_REG_CAP
));
1114 spin_lock_irq(&nvmeq
->q_lock
);
1115 nvme_process_cq(nvmeq
);
1116 spin_unlock_irq(&nvmeq
->q_lock
);
1119 static int nvme_cmb_qdepth(struct nvme_dev
*dev
, int nr_io_queues
,
1122 int q_depth
= dev
->q_depth
;
1123 unsigned q_size_aligned
= roundup(q_depth
* entry_size
,
1124 dev
->ctrl
.page_size
);
1126 if (q_size_aligned
* nr_io_queues
> dev
->cmb_size
) {
1127 u64 mem_per_q
= div_u64(dev
->cmb_size
, nr_io_queues
);
1128 mem_per_q
= round_down(mem_per_q
, dev
->ctrl
.page_size
);
1129 q_depth
= div_u64(mem_per_q
, entry_size
);
1132 * Ensure the reduced q_depth is above some threshold where it
1133 * would be better to map queues in system memory with the
1143 static int nvme_alloc_sq_cmds(struct nvme_dev
*dev
, struct nvme_queue
*nvmeq
,
1146 if (qid
&& dev
->cmb
&& use_cmb_sqes
&& NVME_CMB_SQS(dev
->cmbsz
)) {
1147 unsigned offset
= (qid
- 1) * roundup(SQ_SIZE(depth
),
1148 dev
->ctrl
.page_size
);
1149 nvmeq
->sq_dma_addr
= dev
->cmb_dma_addr
+ offset
;
1150 nvmeq
->sq_cmds_io
= dev
->cmb
+ offset
;
1152 nvmeq
->sq_cmds
= dma_alloc_coherent(dev
->dev
, SQ_SIZE(depth
),
1153 &nvmeq
->sq_dma_addr
, GFP_KERNEL
);
1154 if (!nvmeq
->sq_cmds
)
1161 static struct nvme_queue
*nvme_alloc_queue(struct nvme_dev
*dev
, int qid
,
1162 int depth
, int node
)
1164 struct nvme_queue
*nvmeq
= kzalloc_node(sizeof(*nvmeq
), GFP_KERNEL
,
1169 nvmeq
->cqes
= dma_zalloc_coherent(dev
->dev
, CQ_SIZE(depth
),
1170 &nvmeq
->cq_dma_addr
, GFP_KERNEL
);
1174 if (nvme_alloc_sq_cmds(dev
, nvmeq
, qid
, depth
))
1177 nvmeq
->q_dmadev
= dev
->dev
;
1179 spin_lock_init(&nvmeq
->q_lock
);
1181 nvmeq
->cq_phase
= 1;
1182 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1183 nvmeq
->q_depth
= depth
;
1185 nvmeq
->cq_vector
= -1;
1186 dev
->queues
[qid
] = nvmeq
;
1192 dma_free_coherent(dev
->dev
, CQ_SIZE(depth
), (void *)nvmeq
->cqes
,
1193 nvmeq
->cq_dma_addr
);
1199 static int queue_request_irq(struct nvme_queue
*nvmeq
)
1201 struct pci_dev
*pdev
= to_pci_dev(nvmeq
->dev
->dev
);
1202 int nr
= nvmeq
->dev
->ctrl
.instance
;
1204 if (use_threaded_interrupts
) {
1205 return pci_request_irq(pdev
, nvmeq
->cq_vector
, nvme_irq_check
,
1206 nvme_irq
, nvmeq
, "nvme%dq%d", nr
, nvmeq
->qid
);
1208 return pci_request_irq(pdev
, nvmeq
->cq_vector
, nvme_irq
,
1209 NULL
, nvmeq
, "nvme%dq%d", nr
, nvmeq
->qid
);
1213 static void nvme_init_queue(struct nvme_queue
*nvmeq
, u16 qid
)
1215 struct nvme_dev
*dev
= nvmeq
->dev
;
1217 spin_lock_irq(&nvmeq
->q_lock
);
1220 nvmeq
->cq_phase
= 1;
1221 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1222 memset((void *)nvmeq
->cqes
, 0, CQ_SIZE(nvmeq
->q_depth
));
1223 nvme_dbbuf_init(dev
, nvmeq
, qid
);
1224 dev
->online_queues
++;
1225 spin_unlock_irq(&nvmeq
->q_lock
);
1228 static int nvme_create_queue(struct nvme_queue
*nvmeq
, int qid
)
1230 struct nvme_dev
*dev
= nvmeq
->dev
;
1233 nvmeq
->cq_vector
= qid
- 1;
1234 result
= adapter_alloc_cq(dev
, qid
, nvmeq
);
1238 result
= adapter_alloc_sq(dev
, qid
, nvmeq
);
1242 result
= queue_request_irq(nvmeq
);
1246 nvme_init_queue(nvmeq
, qid
);
1250 adapter_delete_sq(dev
, qid
);
1252 adapter_delete_cq(dev
, qid
);
1256 static const struct blk_mq_ops nvme_mq_admin_ops
= {
1257 .queue_rq
= nvme_queue_rq
,
1258 .complete
= nvme_pci_complete_rq
,
1259 .init_hctx
= nvme_admin_init_hctx
,
1260 .exit_hctx
= nvme_admin_exit_hctx
,
1261 .init_request
= nvme_admin_init_request
,
1262 .timeout
= nvme_timeout
,
1265 static const struct blk_mq_ops nvme_mq_ops
= {
1266 .queue_rq
= nvme_queue_rq
,
1267 .complete
= nvme_pci_complete_rq
,
1268 .init_hctx
= nvme_init_hctx
,
1269 .init_request
= nvme_init_request
,
1270 .map_queues
= nvme_pci_map_queues
,
1271 .timeout
= nvme_timeout
,
1275 static void nvme_dev_remove_admin(struct nvme_dev
*dev
)
1277 if (dev
->ctrl
.admin_q
&& !blk_queue_dying(dev
->ctrl
.admin_q
)) {
1279 * If the controller was reset during removal, it's possible
1280 * user requests may be waiting on a stopped queue. Start the
1281 * queue to flush these to completion.
1283 blk_mq_start_stopped_hw_queues(dev
->ctrl
.admin_q
, true);
1284 blk_cleanup_queue(dev
->ctrl
.admin_q
);
1285 blk_mq_free_tag_set(&dev
->admin_tagset
);
1289 static int nvme_alloc_admin_tags(struct nvme_dev
*dev
)
1291 if (!dev
->ctrl
.admin_q
) {
1292 dev
->admin_tagset
.ops
= &nvme_mq_admin_ops
;
1293 dev
->admin_tagset
.nr_hw_queues
= 1;
1296 * Subtract one to leave an empty queue entry for 'Full Queue'
1297 * condition. See NVM-Express 1.2 specification, section 4.1.2.
1299 dev
->admin_tagset
.queue_depth
= NVME_AQ_BLKMQ_DEPTH
- 1;
1300 dev
->admin_tagset
.timeout
= ADMIN_TIMEOUT
;
1301 dev
->admin_tagset
.numa_node
= dev_to_node(dev
->dev
);
1302 dev
->admin_tagset
.cmd_size
= nvme_cmd_size(dev
);
1303 dev
->admin_tagset
.flags
= BLK_MQ_F_NO_SCHED
;
1304 dev
->admin_tagset
.driver_data
= dev
;
1306 if (blk_mq_alloc_tag_set(&dev
->admin_tagset
))
1309 dev
->ctrl
.admin_q
= blk_mq_init_queue(&dev
->admin_tagset
);
1310 if (IS_ERR(dev
->ctrl
.admin_q
)) {
1311 blk_mq_free_tag_set(&dev
->admin_tagset
);
1314 if (!blk_get_queue(dev
->ctrl
.admin_q
)) {
1315 nvme_dev_remove_admin(dev
);
1316 dev
->ctrl
.admin_q
= NULL
;
1320 blk_mq_start_stopped_hw_queues(dev
->ctrl
.admin_q
, true);
1325 static int nvme_configure_admin_queue(struct nvme_dev
*dev
)
1329 u64 cap
= lo_hi_readq(dev
->bar
+ NVME_REG_CAP
);
1330 struct nvme_queue
*nvmeq
;
1332 dev
->subsystem
= readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 1, 0) ?
1333 NVME_CAP_NSSRC(cap
) : 0;
1335 if (dev
->subsystem
&&
1336 (readl(dev
->bar
+ NVME_REG_CSTS
) & NVME_CSTS_NSSRO
))
1337 writel(NVME_CSTS_NSSRO
, dev
->bar
+ NVME_REG_CSTS
);
1339 result
= nvme_disable_ctrl(&dev
->ctrl
, cap
);
1343 nvmeq
= dev
->queues
[0];
1345 nvmeq
= nvme_alloc_queue(dev
, 0, NVME_AQ_DEPTH
,
1346 dev_to_node(dev
->dev
));
1351 aqa
= nvmeq
->q_depth
- 1;
1354 writel(aqa
, dev
->bar
+ NVME_REG_AQA
);
1355 lo_hi_writeq(nvmeq
->sq_dma_addr
, dev
->bar
+ NVME_REG_ASQ
);
1356 lo_hi_writeq(nvmeq
->cq_dma_addr
, dev
->bar
+ NVME_REG_ACQ
);
1358 result
= nvme_enable_ctrl(&dev
->ctrl
, cap
);
1362 nvmeq
->cq_vector
= 0;
1363 result
= queue_request_irq(nvmeq
);
1365 nvmeq
->cq_vector
= -1;
1372 static bool nvme_should_reset(struct nvme_dev
*dev
, u32 csts
)
1375 /* If true, indicates loss of adapter communication, possibly by a
1376 * NVMe Subsystem reset.
1378 bool nssro
= dev
->subsystem
&& (csts
& NVME_CSTS_NSSRO
);
1380 /* If there is a reset ongoing, we shouldn't reset again. */
1381 if (dev
->ctrl
.state
== NVME_CTRL_RESETTING
)
1384 /* We shouldn't reset unless the controller is on fatal error state
1385 * _or_ if we lost the communication with it.
1387 if (!(csts
& NVME_CSTS_CFS
) && !nssro
)
1390 /* If PCI error recovery process is happening, we cannot reset or
1391 * the recovery mechanism will surely fail.
1393 if (pci_channel_offline(to_pci_dev(dev
->dev
)))
1399 static void nvme_warn_reset(struct nvme_dev
*dev
, u32 csts
)
1401 /* Read a config register to help see what died. */
1405 result
= pci_read_config_word(to_pci_dev(dev
->dev
), PCI_STATUS
,
1407 if (result
== PCIBIOS_SUCCESSFUL
)
1408 dev_warn(dev
->ctrl
.device
,
1409 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1412 dev_warn(dev
->ctrl
.device
,
1413 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1417 static void nvme_watchdog_timer(unsigned long data
)
1419 struct nvme_dev
*dev
= (struct nvme_dev
*)data
;
1420 u32 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
1422 /* Skip controllers under certain specific conditions. */
1423 if (nvme_should_reset(dev
, csts
)) {
1424 if (!nvme_reset(dev
))
1425 nvme_warn_reset(dev
, csts
);
1429 mod_timer(&dev
->watchdog_timer
, round_jiffies(jiffies
+ HZ
));
1432 static int nvme_create_io_queues(struct nvme_dev
*dev
)
1437 for (i
= dev
->queue_count
; i
<= dev
->max_qid
; i
++) {
1438 /* vector == qid - 1, match nvme_create_queue */
1439 if (!nvme_alloc_queue(dev
, i
, dev
->q_depth
,
1440 pci_irq_get_node(to_pci_dev(dev
->dev
), i
- 1))) {
1446 max
= min(dev
->max_qid
, dev
->queue_count
- 1);
1447 for (i
= dev
->online_queues
; i
<= max
; i
++) {
1448 ret
= nvme_create_queue(dev
->queues
[i
], i
);
1454 * Ignore failing Create SQ/CQ commands, we can continue with less
1455 * than the desired aount of queues, and even a controller without
1456 * I/O queues an still be used to issue admin commands. This might
1457 * be useful to upgrade a buggy firmware for example.
1459 return ret
>= 0 ? 0 : ret
;
1462 static ssize_t
nvme_cmb_show(struct device
*dev
,
1463 struct device_attribute
*attr
,
1466 struct nvme_dev
*ndev
= to_nvme_dev(dev_get_drvdata(dev
));
1468 return scnprintf(buf
, PAGE_SIZE
, "cmbloc : x%08x\ncmbsz : x%08x\n",
1469 ndev
->cmbloc
, ndev
->cmbsz
);
1471 static DEVICE_ATTR(cmb
, S_IRUGO
, nvme_cmb_show
, NULL
);
1473 static void __iomem
*nvme_map_cmb(struct nvme_dev
*dev
)
1475 u64 szu
, size
, offset
;
1476 resource_size_t bar_size
;
1477 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1479 dma_addr_t dma_addr
;
1481 dev
->cmbsz
= readl(dev
->bar
+ NVME_REG_CMBSZ
);
1482 if (!(NVME_CMB_SZ(dev
->cmbsz
)))
1484 dev
->cmbloc
= readl(dev
->bar
+ NVME_REG_CMBLOC
);
1489 szu
= (u64
)1 << (12 + 4 * NVME_CMB_SZU(dev
->cmbsz
));
1490 size
= szu
* NVME_CMB_SZ(dev
->cmbsz
);
1491 offset
= szu
* NVME_CMB_OFST(dev
->cmbloc
);
1492 bar_size
= pci_resource_len(pdev
, NVME_CMB_BIR(dev
->cmbloc
));
1494 if (offset
> bar_size
)
1498 * Controllers may support a CMB size larger than their BAR,
1499 * for example, due to being behind a bridge. Reduce the CMB to
1500 * the reported size of the BAR
1502 if (size
> bar_size
- offset
)
1503 size
= bar_size
- offset
;
1505 dma_addr
= pci_resource_start(pdev
, NVME_CMB_BIR(dev
->cmbloc
)) + offset
;
1506 cmb
= ioremap_wc(dma_addr
, size
);
1510 dev
->cmb_dma_addr
= dma_addr
;
1511 dev
->cmb_size
= size
;
1515 static inline void nvme_release_cmb(struct nvme_dev
*dev
)
1521 sysfs_remove_file_from_group(&dev
->ctrl
.device
->kobj
,
1522 &dev_attr_cmb
.attr
, NULL
);
1528 static int nvme_set_host_mem(struct nvme_dev
*dev
, u32 bits
)
1530 size_t len
= dev
->nr_host_mem_descs
* sizeof(*dev
->host_mem_descs
);
1531 struct nvme_command c
;
1535 dma_addr
= dma_map_single(dev
->dev
, dev
->host_mem_descs
, len
,
1537 if (dma_mapping_error(dev
->dev
, dma_addr
))
1540 memset(&c
, 0, sizeof(c
));
1541 c
.features
.opcode
= nvme_admin_set_features
;
1542 c
.features
.fid
= cpu_to_le32(NVME_FEAT_HOST_MEM_BUF
);
1543 c
.features
.dword11
= cpu_to_le32(bits
);
1544 c
.features
.dword12
= cpu_to_le32(dev
->host_mem_size
>>
1545 ilog2(dev
->ctrl
.page_size
));
1546 c
.features
.dword13
= cpu_to_le32(lower_32_bits(dma_addr
));
1547 c
.features
.dword14
= cpu_to_le32(upper_32_bits(dma_addr
));
1548 c
.features
.dword15
= cpu_to_le32(dev
->nr_host_mem_descs
);
1550 ret
= nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
1552 dev_warn(dev
->ctrl
.device
,
1553 "failed to set host mem (err %d, flags %#x).\n",
1556 dma_unmap_single(dev
->dev
, dma_addr
, len
, DMA_TO_DEVICE
);
1560 static void nvme_free_host_mem(struct nvme_dev
*dev
)
1564 for (i
= 0; i
< dev
->nr_host_mem_descs
; i
++) {
1565 struct nvme_host_mem_buf_desc
*desc
= &dev
->host_mem_descs
[i
];
1566 size_t size
= le32_to_cpu(desc
->size
) * dev
->ctrl
.page_size
;
1568 dma_free_coherent(dev
->dev
, size
, dev
->host_mem_desc_bufs
[i
],
1569 le64_to_cpu(desc
->addr
));
1572 kfree(dev
->host_mem_desc_bufs
);
1573 dev
->host_mem_desc_bufs
= NULL
;
1574 kfree(dev
->host_mem_descs
);
1575 dev
->host_mem_descs
= NULL
;
1578 static int nvme_alloc_host_mem(struct nvme_dev
*dev
, u64 min
, u64 preferred
)
1580 struct nvme_host_mem_buf_desc
*descs
;
1581 u32 chunk_size
, max_entries
, i
= 0;
1585 /* start big and work our way down */
1586 chunk_size
= min(preferred
, (u64
)PAGE_SIZE
<< MAX_ORDER
);
1588 tmp
= (preferred
+ chunk_size
- 1);
1589 do_div(tmp
, chunk_size
);
1591 descs
= kcalloc(max_entries
, sizeof(*descs
), GFP_KERNEL
);
1595 bufs
= kcalloc(max_entries
, sizeof(*bufs
), GFP_KERNEL
);
1597 goto out_free_descs
;
1599 for (size
= 0; size
< preferred
; size
+= chunk_size
) {
1600 u32 len
= min_t(u64
, chunk_size
, preferred
- size
);
1601 dma_addr_t dma_addr
;
1603 bufs
[i
] = dma_alloc_attrs(dev
->dev
, len
, &dma_addr
, GFP_KERNEL
,
1604 DMA_ATTR_NO_KERNEL_MAPPING
| DMA_ATTR_NO_WARN
);
1608 descs
[i
].addr
= cpu_to_le64(dma_addr
);
1609 descs
[i
].size
= cpu_to_le32(len
/ dev
->ctrl
.page_size
);
1613 if (!size
|| (min
&& size
< min
)) {
1614 dev_warn(dev
->ctrl
.device
,
1615 "failed to allocate host memory buffer.\n");
1619 dev_info(dev
->ctrl
.device
,
1620 "allocated %lld MiB host memory buffer.\n",
1621 size
>> ilog2(SZ_1M
));
1622 dev
->nr_host_mem_descs
= i
;
1623 dev
->host_mem_size
= size
;
1624 dev
->host_mem_descs
= descs
;
1625 dev
->host_mem_desc_bufs
= bufs
;
1630 size_t size
= le32_to_cpu(descs
[i
].size
) * dev
->ctrl
.page_size
;
1632 dma_free_coherent(dev
->dev
, size
, bufs
[i
],
1633 le64_to_cpu(descs
[i
].addr
));
1640 /* try a smaller chunk size if we failed early */
1641 if (chunk_size
>= PAGE_SIZE
* 2 && (i
== 0 || size
< min
)) {
1645 dev
->host_mem_descs
= NULL
;
1649 static void nvme_setup_host_mem(struct nvme_dev
*dev
)
1651 u64 max
= (u64
)max_host_mem_size_mb
* SZ_1M
;
1652 u64 preferred
= (u64
)dev
->ctrl
.hmpre
* 4096;
1653 u64 min
= (u64
)dev
->ctrl
.hmmin
* 4096;
1654 u32 enable_bits
= NVME_HOST_MEM_ENABLE
;
1656 preferred
= min(preferred
, max
);
1658 dev_warn(dev
->ctrl
.device
,
1659 "min host memory (%lld MiB) above limit (%d MiB).\n",
1660 min
>> ilog2(SZ_1M
), max_host_mem_size_mb
);
1661 nvme_free_host_mem(dev
);
1666 * If we already have a buffer allocated check if we can reuse it.
1668 if (dev
->host_mem_descs
) {
1669 if (dev
->host_mem_size
>= min
)
1670 enable_bits
|= NVME_HOST_MEM_RETURN
;
1672 nvme_free_host_mem(dev
);
1675 if (!dev
->host_mem_descs
) {
1676 if (nvme_alloc_host_mem(dev
, min
, preferred
))
1680 if (nvme_set_host_mem(dev
, enable_bits
))
1681 nvme_free_host_mem(dev
);
1684 static size_t db_bar_size(struct nvme_dev
*dev
, unsigned nr_io_queues
)
1686 return 4096 + ((nr_io_queues
+ 1) * 8 * dev
->db_stride
);
1689 static int nvme_setup_io_queues(struct nvme_dev
*dev
)
1691 struct nvme_queue
*adminq
= dev
->queues
[0];
1692 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1693 int result
, nr_io_queues
, size
;
1695 nr_io_queues
= num_online_cpus();
1696 result
= nvme_set_queue_count(&dev
->ctrl
, &nr_io_queues
);
1700 if (nr_io_queues
== 0)
1703 if (dev
->cmb
&& NVME_CMB_SQS(dev
->cmbsz
)) {
1704 result
= nvme_cmb_qdepth(dev
, nr_io_queues
,
1705 sizeof(struct nvme_command
));
1707 dev
->q_depth
= result
;
1709 nvme_release_cmb(dev
);
1712 size
= db_bar_size(dev
, nr_io_queues
);
1716 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), size
);
1719 if (!--nr_io_queues
)
1721 size
= db_bar_size(dev
, nr_io_queues
);
1723 dev
->dbs
= dev
->bar
+ 4096;
1724 adminq
->q_db
= dev
->dbs
;
1727 /* Deregister the admin queue's interrupt */
1728 pci_free_irq(pdev
, 0, adminq
);
1731 * If we enable msix early due to not intx, disable it again before
1732 * setting up the full range we need.
1734 pci_free_irq_vectors(pdev
);
1735 nr_io_queues
= pci_alloc_irq_vectors(pdev
, 1, nr_io_queues
,
1736 PCI_IRQ_ALL_TYPES
| PCI_IRQ_AFFINITY
);
1737 if (nr_io_queues
<= 0)
1739 dev
->max_qid
= nr_io_queues
;
1742 * Should investigate if there's a performance win from allocating
1743 * more queues than interrupt vectors; it might allow the submission
1744 * path to scale better, even if the receive path is limited by the
1745 * number of interrupts.
1748 result
= queue_request_irq(adminq
);
1750 adminq
->cq_vector
= -1;
1753 return nvme_create_io_queues(dev
);
1756 static void nvme_del_queue_end(struct request
*req
, blk_status_t error
)
1758 struct nvme_queue
*nvmeq
= req
->end_io_data
;
1760 blk_mq_free_request(req
);
1761 complete(&nvmeq
->dev
->ioq_wait
);
1764 static void nvme_del_cq_end(struct request
*req
, blk_status_t error
)
1766 struct nvme_queue
*nvmeq
= req
->end_io_data
;
1769 unsigned long flags
;
1772 * We might be called with the AQ q_lock held
1773 * and the I/O queue q_lock should always
1774 * nest inside the AQ one.
1776 spin_lock_irqsave_nested(&nvmeq
->q_lock
, flags
,
1777 SINGLE_DEPTH_NESTING
);
1778 nvme_process_cq(nvmeq
);
1779 spin_unlock_irqrestore(&nvmeq
->q_lock
, flags
);
1782 nvme_del_queue_end(req
, error
);
1785 static int nvme_delete_queue(struct nvme_queue
*nvmeq
, u8 opcode
)
1787 struct request_queue
*q
= nvmeq
->dev
->ctrl
.admin_q
;
1788 struct request
*req
;
1789 struct nvme_command cmd
;
1791 memset(&cmd
, 0, sizeof(cmd
));
1792 cmd
.delete_queue
.opcode
= opcode
;
1793 cmd
.delete_queue
.qid
= cpu_to_le16(nvmeq
->qid
);
1795 req
= nvme_alloc_request(q
, &cmd
, BLK_MQ_REQ_NOWAIT
, NVME_QID_ANY
);
1797 return PTR_ERR(req
);
1799 req
->timeout
= ADMIN_TIMEOUT
;
1800 req
->end_io_data
= nvmeq
;
1802 blk_execute_rq_nowait(q
, NULL
, req
, false,
1803 opcode
== nvme_admin_delete_cq
?
1804 nvme_del_cq_end
: nvme_del_queue_end
);
1808 static void nvme_disable_io_queues(struct nvme_dev
*dev
, int queues
)
1811 unsigned long timeout
;
1812 u8 opcode
= nvme_admin_delete_sq
;
1814 for (pass
= 0; pass
< 2; pass
++) {
1815 int sent
= 0, i
= queues
;
1817 reinit_completion(&dev
->ioq_wait
);
1819 timeout
= ADMIN_TIMEOUT
;
1820 for (; i
> 0; i
--, sent
++)
1821 if (nvme_delete_queue(dev
->queues
[i
], opcode
))
1825 timeout
= wait_for_completion_io_timeout(&dev
->ioq_wait
, timeout
);
1831 opcode
= nvme_admin_delete_cq
;
1836 * Return: error value if an error occurred setting up the queues or calling
1837 * Identify Device. 0 if these succeeded, even if adding some of the
1838 * namespaces failed. At the moment, these failures are silent. TBD which
1839 * failures should be reported.
1841 static int nvme_dev_add(struct nvme_dev
*dev
)
1843 if (!dev
->ctrl
.tagset
) {
1844 dev
->tagset
.ops
= &nvme_mq_ops
;
1845 dev
->tagset
.nr_hw_queues
= dev
->online_queues
- 1;
1846 dev
->tagset
.timeout
= NVME_IO_TIMEOUT
;
1847 dev
->tagset
.numa_node
= dev_to_node(dev
->dev
);
1848 dev
->tagset
.queue_depth
=
1849 min_t(int, dev
->q_depth
, BLK_MQ_MAX_DEPTH
) - 1;
1850 dev
->tagset
.cmd_size
= nvme_cmd_size(dev
);
1851 dev
->tagset
.flags
= BLK_MQ_F_SHOULD_MERGE
;
1852 dev
->tagset
.driver_data
= dev
;
1854 if (blk_mq_alloc_tag_set(&dev
->tagset
))
1856 dev
->ctrl
.tagset
= &dev
->tagset
;
1858 nvme_dbbuf_set(dev
);
1860 blk_mq_update_nr_hw_queues(&dev
->tagset
, dev
->online_queues
- 1);
1862 /* Free previously allocated queues that are no longer usable */
1863 nvme_free_queues(dev
, dev
->online_queues
);
1869 static int nvme_pci_enable(struct nvme_dev
*dev
)
1872 int result
= -ENOMEM
;
1873 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1875 if (pci_enable_device_mem(pdev
))
1878 pci_set_master(pdev
);
1880 if (dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(64)) &&
1881 dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(32)))
1884 if (readl(dev
->bar
+ NVME_REG_CSTS
) == -1) {
1890 * Some devices and/or platforms don't advertise or work with INTx
1891 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
1892 * adjust this later.
1894 result
= pci_alloc_irq_vectors(pdev
, 1, 1, PCI_IRQ_ALL_TYPES
);
1898 cap
= lo_hi_readq(dev
->bar
+ NVME_REG_CAP
);
1900 dev
->q_depth
= min_t(int, NVME_CAP_MQES(cap
) + 1, NVME_Q_DEPTH
);
1901 dev
->db_stride
= 1 << NVME_CAP_STRIDE(cap
);
1902 dev
->dbs
= dev
->bar
+ 4096;
1905 * Temporary fix for the Apple controller found in the MacBook8,1 and
1906 * some MacBook7,1 to avoid controller resets and data loss.
1908 if (pdev
->vendor
== PCI_VENDOR_ID_APPLE
&& pdev
->device
== 0x2001) {
1910 dev_warn(dev
->ctrl
.device
, "detected Apple NVMe controller, "
1911 "set queue depth=%u to work around controller resets\n",
1916 * CMBs can currently only exist on >=1.2 PCIe devices. We only
1917 * populate sysfs if a CMB is implemented. Note that we add the
1918 * CMB attribute to the nvme_ctrl kobj which removes the need to remove
1919 * it on exit. Since nvme_dev_attrs_group has no name we can pass
1920 * NULL as final argument to sysfs_add_file_to_group.
1923 if (readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 2, 0)) {
1924 dev
->cmb
= nvme_map_cmb(dev
);
1927 if (sysfs_add_file_to_group(&dev
->ctrl
.device
->kobj
,
1928 &dev_attr_cmb
.attr
, NULL
))
1929 dev_warn(dev
->ctrl
.device
,
1930 "failed to add sysfs attribute for CMB\n");
1934 pci_enable_pcie_error_reporting(pdev
);
1935 pci_save_state(pdev
);
1939 pci_disable_device(pdev
);
1943 static void nvme_dev_unmap(struct nvme_dev
*dev
)
1947 pci_release_mem_regions(to_pci_dev(dev
->dev
));
1950 static void nvme_pci_disable(struct nvme_dev
*dev
)
1952 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1954 nvme_release_cmb(dev
);
1955 pci_free_irq_vectors(pdev
);
1957 if (pci_is_enabled(pdev
)) {
1958 pci_disable_pcie_error_reporting(pdev
);
1959 pci_disable_device(pdev
);
1963 static void nvme_dev_disable(struct nvme_dev
*dev
, bool shutdown
)
1967 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1969 del_timer_sync(&dev
->watchdog_timer
);
1971 mutex_lock(&dev
->shutdown_lock
);
1972 if (pci_is_enabled(pdev
)) {
1973 u32 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
1975 if (dev
->ctrl
.state
== NVME_CTRL_LIVE
)
1976 nvme_start_freeze(&dev
->ctrl
);
1977 dead
= !!((csts
& NVME_CSTS_CFS
) || !(csts
& NVME_CSTS_RDY
) ||
1978 pdev
->error_state
!= pci_channel_io_normal
);
1982 * Give the controller a chance to complete all entered requests if
1983 * doing a safe shutdown.
1987 nvme_wait_freeze_timeout(&dev
->ctrl
, NVME_IO_TIMEOUT
);
1990 * If the controller is still alive tell it to stop using the
1991 * host memory buffer. In theory the shutdown / reset should
1992 * make sure that it doesn't access the host memoery anymore,
1993 * but I'd rather be safe than sorry..
1995 if (dev
->host_mem_descs
)
1996 nvme_set_host_mem(dev
, 0);
1999 nvme_stop_queues(&dev
->ctrl
);
2001 queues
= dev
->online_queues
- 1;
2002 for (i
= dev
->queue_count
- 1; i
> 0; i
--)
2003 nvme_suspend_queue(dev
->queues
[i
]);
2006 /* A device might become IO incapable very soon during
2007 * probe, before the admin queue is configured. Thus,
2008 * queue_count can be 0 here.
2010 if (dev
->queue_count
)
2011 nvme_suspend_queue(dev
->queues
[0]);
2013 nvme_disable_io_queues(dev
, queues
);
2014 nvme_disable_admin_queue(dev
, shutdown
);
2016 nvme_pci_disable(dev
);
2018 blk_mq_tagset_busy_iter(&dev
->tagset
, nvme_cancel_request
, &dev
->ctrl
);
2019 blk_mq_tagset_busy_iter(&dev
->admin_tagset
, nvme_cancel_request
, &dev
->ctrl
);
2022 * The driver will not be starting up queues again if shutting down so
2023 * must flush all entered requests to their failed completion to avoid
2024 * deadlocking blk-mq hot-cpu notifier.
2027 nvme_start_queues(&dev
->ctrl
);
2028 mutex_unlock(&dev
->shutdown_lock
);
2031 static int nvme_setup_prp_pools(struct nvme_dev
*dev
)
2033 dev
->prp_page_pool
= dma_pool_create("prp list page", dev
->dev
,
2034 PAGE_SIZE
, PAGE_SIZE
, 0);
2035 if (!dev
->prp_page_pool
)
2038 /* Optimisation for I/Os between 4k and 128k */
2039 dev
->prp_small_pool
= dma_pool_create("prp list 256", dev
->dev
,
2041 if (!dev
->prp_small_pool
) {
2042 dma_pool_destroy(dev
->prp_page_pool
);
2048 static void nvme_release_prp_pools(struct nvme_dev
*dev
)
2050 dma_pool_destroy(dev
->prp_page_pool
);
2051 dma_pool_destroy(dev
->prp_small_pool
);
2054 static void nvme_pci_free_ctrl(struct nvme_ctrl
*ctrl
)
2056 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
2058 nvme_dbbuf_dma_free(dev
);
2059 put_device(dev
->dev
);
2060 if (dev
->tagset
.tags
)
2061 blk_mq_free_tag_set(&dev
->tagset
);
2062 if (dev
->ctrl
.admin_q
)
2063 blk_put_queue(dev
->ctrl
.admin_q
);
2065 free_opal_dev(dev
->ctrl
.opal_dev
);
2069 static void nvme_remove_dead_ctrl(struct nvme_dev
*dev
, int status
)
2071 dev_warn(dev
->ctrl
.device
, "Removing after probe failure status: %d\n", status
);
2073 kref_get(&dev
->ctrl
.kref
);
2074 nvme_dev_disable(dev
, false);
2075 if (!schedule_work(&dev
->remove_work
))
2076 nvme_put_ctrl(&dev
->ctrl
);
2079 static void nvme_reset_work(struct work_struct
*work
)
2081 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, reset_work
);
2082 bool was_suspend
= !!(dev
->ctrl
.ctrl_config
& NVME_CC_SHN_NORMAL
);
2083 int result
= -ENODEV
;
2085 if (WARN_ON(dev
->ctrl
.state
!= NVME_CTRL_RESETTING
))
2089 * If we're called to reset a live controller first shut it down before
2092 if (dev
->ctrl
.ctrl_config
& NVME_CC_ENABLE
)
2093 nvme_dev_disable(dev
, false);
2095 result
= nvme_pci_enable(dev
);
2099 result
= nvme_configure_admin_queue(dev
);
2103 nvme_init_queue(dev
->queues
[0], 0);
2104 result
= nvme_alloc_admin_tags(dev
);
2108 result
= nvme_init_identify(&dev
->ctrl
);
2112 if (dev
->ctrl
.oacs
& NVME_CTRL_OACS_SEC_SUPP
) {
2113 if (!dev
->ctrl
.opal_dev
)
2114 dev
->ctrl
.opal_dev
=
2115 init_opal_dev(&dev
->ctrl
, &nvme_sec_submit
);
2116 else if (was_suspend
)
2117 opal_unlock_from_suspend(dev
->ctrl
.opal_dev
);
2119 free_opal_dev(dev
->ctrl
.opal_dev
);
2120 dev
->ctrl
.opal_dev
= NULL
;
2123 if (dev
->ctrl
.oacs
& NVME_CTRL_OACS_DBBUF_SUPP
) {
2124 result
= nvme_dbbuf_dma_alloc(dev
);
2127 "unable to allocate dma for dbbuf\n");
2130 if (dev
->ctrl
.hmpre
)
2131 nvme_setup_host_mem(dev
);
2133 result
= nvme_setup_io_queues(dev
);
2138 * A controller that can not execute IO typically requires user
2139 * intervention to correct. For such degraded controllers, the driver
2140 * should not submit commands the user did not request, so skip
2141 * registering for asynchronous event notification on this condition.
2143 if (dev
->online_queues
> 1)
2144 nvme_queue_async_events(&dev
->ctrl
);
2146 mod_timer(&dev
->watchdog_timer
, round_jiffies(jiffies
+ HZ
));
2149 * Keep the controller around but remove all namespaces if we don't have
2150 * any working I/O queue.
2152 if (dev
->online_queues
< 2) {
2153 dev_warn(dev
->ctrl
.device
, "IO queues not created\n");
2154 nvme_kill_queues(&dev
->ctrl
);
2155 nvme_remove_namespaces(&dev
->ctrl
);
2157 nvme_start_queues(&dev
->ctrl
);
2158 nvme_wait_freeze(&dev
->ctrl
);
2160 nvme_unfreeze(&dev
->ctrl
);
2163 if (!nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_LIVE
)) {
2164 dev_warn(dev
->ctrl
.device
, "failed to mark controller live\n");
2168 if (dev
->online_queues
> 1)
2169 nvme_queue_scan(&dev
->ctrl
);
2173 nvme_remove_dead_ctrl(dev
, result
);
2176 static void nvme_remove_dead_ctrl_work(struct work_struct
*work
)
2178 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, remove_work
);
2179 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2181 nvme_kill_queues(&dev
->ctrl
);
2182 if (pci_get_drvdata(pdev
))
2183 device_release_driver(&pdev
->dev
);
2184 nvme_put_ctrl(&dev
->ctrl
);
2187 static int nvme_reset(struct nvme_dev
*dev
)
2189 if (!dev
->ctrl
.admin_q
|| blk_queue_dying(dev
->ctrl
.admin_q
))
2191 if (!nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_RESETTING
))
2193 if (!queue_work(nvme_workq
, &dev
->reset_work
))
2198 static int nvme_pci_reg_read32(struct nvme_ctrl
*ctrl
, u32 off
, u32
*val
)
2200 *val
= readl(to_nvme_dev(ctrl
)->bar
+ off
);
2204 static int nvme_pci_reg_write32(struct nvme_ctrl
*ctrl
, u32 off
, u32 val
)
2206 writel(val
, to_nvme_dev(ctrl
)->bar
+ off
);
2210 static int nvme_pci_reg_read64(struct nvme_ctrl
*ctrl
, u32 off
, u64
*val
)
2212 *val
= readq(to_nvme_dev(ctrl
)->bar
+ off
);
2216 static int nvme_pci_reset_ctrl(struct nvme_ctrl
*ctrl
)
2218 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
2219 int ret
= nvme_reset(dev
);
2222 flush_work(&dev
->reset_work
);
2226 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops
= {
2228 .module
= THIS_MODULE
,
2229 .flags
= NVME_F_METADATA_SUPPORTED
,
2230 .reg_read32
= nvme_pci_reg_read32
,
2231 .reg_write32
= nvme_pci_reg_write32
,
2232 .reg_read64
= nvme_pci_reg_read64
,
2233 .reset_ctrl
= nvme_pci_reset_ctrl
,
2234 .free_ctrl
= nvme_pci_free_ctrl
,
2235 .submit_async_event
= nvme_pci_submit_async_event
,
2238 static int nvme_dev_map(struct nvme_dev
*dev
)
2240 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2242 if (pci_request_mem_regions(pdev
, "nvme"))
2245 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), 8192);
2251 pci_release_mem_regions(pdev
);
2255 static unsigned long check_dell_samsung_bug(struct pci_dev
*pdev
)
2257 if (pdev
->vendor
== 0x144d && pdev
->device
== 0xa802) {
2259 * Several Samsung devices seem to drop off the PCIe bus
2260 * randomly when APST is on and uses the deepest sleep state.
2261 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2262 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2263 * 950 PRO 256GB", but it seems to be restricted to two Dell
2266 if (dmi_match(DMI_SYS_VENDOR
, "Dell Inc.") &&
2267 (dmi_match(DMI_PRODUCT_NAME
, "XPS 15 9550") ||
2268 dmi_match(DMI_PRODUCT_NAME
, "Precision 5510")))
2269 return NVME_QUIRK_NO_DEEPEST_PS
;
2275 static int nvme_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
2277 int node
, result
= -ENOMEM
;
2278 struct nvme_dev
*dev
;
2279 unsigned long quirks
= id
->driver_data
;
2281 node
= dev_to_node(&pdev
->dev
);
2282 if (node
== NUMA_NO_NODE
)
2283 set_dev_node(&pdev
->dev
, first_memory_node
);
2285 dev
= kzalloc_node(sizeof(*dev
), GFP_KERNEL
, node
);
2288 dev
->queues
= kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2293 dev
->dev
= get_device(&pdev
->dev
);
2294 pci_set_drvdata(pdev
, dev
);
2296 result
= nvme_dev_map(dev
);
2300 INIT_WORK(&dev
->reset_work
, nvme_reset_work
);
2301 INIT_WORK(&dev
->remove_work
, nvme_remove_dead_ctrl_work
);
2302 setup_timer(&dev
->watchdog_timer
, nvme_watchdog_timer
,
2303 (unsigned long)dev
);
2304 mutex_init(&dev
->shutdown_lock
);
2305 init_completion(&dev
->ioq_wait
);
2307 result
= nvme_setup_prp_pools(dev
);
2311 quirks
|= check_dell_samsung_bug(pdev
);
2313 result
= nvme_init_ctrl(&dev
->ctrl
, &pdev
->dev
, &nvme_pci_ctrl_ops
,
2318 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_RESETTING
);
2319 dev_info(dev
->ctrl
.device
, "pci function %s\n", dev_name(&pdev
->dev
));
2321 queue_work(nvme_workq
, &dev
->reset_work
);
2325 nvme_release_prp_pools(dev
);
2327 put_device(dev
->dev
);
2328 nvme_dev_unmap(dev
);
2335 static void nvme_reset_notify(struct pci_dev
*pdev
, bool prepare
)
2337 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2340 nvme_dev_disable(dev
, false);
2345 static void nvme_shutdown(struct pci_dev
*pdev
)
2347 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2348 nvme_dev_disable(dev
, true);
2352 * The driver's remove may be called on a device in a partially initialized
2353 * state. This function must not have any dependencies on the device state in
2356 static void nvme_remove(struct pci_dev
*pdev
)
2358 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2360 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_DELETING
);
2362 cancel_work_sync(&dev
->reset_work
);
2363 pci_set_drvdata(pdev
, NULL
);
2365 if (!pci_device_is_present(pdev
)) {
2366 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_DEAD
);
2367 nvme_dev_disable(dev
, false);
2370 flush_work(&dev
->reset_work
);
2371 nvme_uninit_ctrl(&dev
->ctrl
);
2372 nvme_dev_disable(dev
, true);
2373 nvme_free_host_mem(dev
);
2374 nvme_dev_remove_admin(dev
);
2375 nvme_free_queues(dev
, 0);
2376 nvme_release_prp_pools(dev
);
2377 nvme_dev_unmap(dev
);
2378 nvme_put_ctrl(&dev
->ctrl
);
2381 static int nvme_pci_sriov_configure(struct pci_dev
*pdev
, int numvfs
)
2386 if (pci_vfs_assigned(pdev
)) {
2387 dev_warn(&pdev
->dev
,
2388 "Cannot disable SR-IOV VFs while assigned\n");
2391 pci_disable_sriov(pdev
);
2395 ret
= pci_enable_sriov(pdev
, numvfs
);
2396 return ret
? ret
: numvfs
;
2399 #ifdef CONFIG_PM_SLEEP
2400 static int nvme_suspend(struct device
*dev
)
2402 struct pci_dev
*pdev
= to_pci_dev(dev
);
2403 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2405 nvme_dev_disable(ndev
, true);
2409 static int nvme_resume(struct device
*dev
)
2411 struct pci_dev
*pdev
= to_pci_dev(dev
);
2412 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2419 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops
, nvme_suspend
, nvme_resume
);
2421 static pci_ers_result_t
nvme_error_detected(struct pci_dev
*pdev
,
2422 pci_channel_state_t state
)
2424 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2427 * A frozen channel requires a reset. When detected, this method will
2428 * shutdown the controller to quiesce. The controller will be restarted
2429 * after the slot reset through driver's slot_reset callback.
2432 case pci_channel_io_normal
:
2433 return PCI_ERS_RESULT_CAN_RECOVER
;
2434 case pci_channel_io_frozen
:
2435 dev_warn(dev
->ctrl
.device
,
2436 "frozen state error detected, reset controller\n");
2437 nvme_dev_disable(dev
, false);
2438 return PCI_ERS_RESULT_NEED_RESET
;
2439 case pci_channel_io_perm_failure
:
2440 dev_warn(dev
->ctrl
.device
,
2441 "failure state error detected, request disconnect\n");
2442 return PCI_ERS_RESULT_DISCONNECT
;
2444 return PCI_ERS_RESULT_NEED_RESET
;
2447 static pci_ers_result_t
nvme_slot_reset(struct pci_dev
*pdev
)
2449 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2451 dev_info(dev
->ctrl
.device
, "restart after slot reset\n");
2452 pci_restore_state(pdev
);
2454 return PCI_ERS_RESULT_RECOVERED
;
2457 static void nvme_error_resume(struct pci_dev
*pdev
)
2459 pci_cleanup_aer_uncorrect_error_status(pdev
);
2462 static const struct pci_error_handlers nvme_err_handler
= {
2463 .error_detected
= nvme_error_detected
,
2464 .slot_reset
= nvme_slot_reset
,
2465 .resume
= nvme_error_resume
,
2466 .reset_notify
= nvme_reset_notify
,
2469 static const struct pci_device_id nvme_id_table
[] = {
2470 { PCI_VDEVICE(INTEL
, 0x0953),
2471 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2472 NVME_QUIRK_DEALLOCATE_ZEROES
, },
2473 { PCI_VDEVICE(INTEL
, 0x0a53),
2474 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2475 NVME_QUIRK_DEALLOCATE_ZEROES
, },
2476 { PCI_VDEVICE(INTEL
, 0x0a54),
2477 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2478 NVME_QUIRK_DEALLOCATE_ZEROES
, },
2479 { PCI_VDEVICE(INTEL
, 0xf1a5), /* Intel 600P/P3100 */
2480 .driver_data
= NVME_QUIRK_NO_DEEPEST_PS
},
2481 { PCI_VDEVICE(INTEL
, 0x5845), /* Qemu emulated controller */
2482 .driver_data
= NVME_QUIRK_IDENTIFY_CNS
, },
2483 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2484 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
2485 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2486 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
2487 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS
, 0xffffff) },
2488 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, 0x2001) },
2489 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, 0x2003) },
2492 MODULE_DEVICE_TABLE(pci
, nvme_id_table
);
2494 static struct pci_driver nvme_driver
= {
2496 .id_table
= nvme_id_table
,
2497 .probe
= nvme_probe
,
2498 .remove
= nvme_remove
,
2499 .shutdown
= nvme_shutdown
,
2501 .pm
= &nvme_dev_pm_ops
,
2503 .sriov_configure
= nvme_pci_sriov_configure
,
2504 .err_handler
= &nvme_err_handler
,
2507 static int __init
nvme_init(void)
2511 nvme_workq
= alloc_workqueue("nvme", WQ_UNBOUND
| WQ_MEM_RECLAIM
, 0);
2515 result
= pci_register_driver(&nvme_driver
);
2517 destroy_workqueue(nvme_workq
);
2521 static void __exit
nvme_exit(void)
2523 pci_unregister_driver(&nvme_driver
);
2524 destroy_workqueue(nvme_workq
);
2528 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2529 MODULE_LICENSE("GPL");
2530 MODULE_VERSION("1.0");
2531 module_init(nvme_init
);
2532 module_exit(nvme_exit
);