drivers/pci/host/pci-layerscape.c

   1 /*
   2  * PCIe host controller driver for Freescale Layerscape SoCs
   3  *
   4  * Copyright (C) 2014 Freescale Semiconductor.
   5  *
   6  * Author: Minghuan Lian <Minghuan.Lian@freescale.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/init.h>
  16 #include <linux/of_pci.h>
  17 #include <linux/of_platform.h>
  18 #include <linux/of_irq.h>
  19 #include <linux/of_address.h>
  20 #include <linux/pci.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/resource.h>
  23 #include <linux/mfd/syscon.h>
  24 #include <linux/regmap.h>
  25
  26 #include "pcie-designware.h"
  27
  28 /* PEX1/2 Misc Ports Status Register */
  29 #define SCFG_PEXMSCPORTSR(pex_idx)      (0x94 + (pex_idx) * 4)
  30 #define LTSSM_STATE_SHIFT       20
  31 #define LTSSM_STATE_MASK        0x3f
  32 #define LTSSM_PCIE_L0           0x11 /* L0 state */
  33
  34 /* PEX Internal Configuration Registers */
  35 #define PCIE_STRFMR1            0x71c /* Symbol Timer & Filter Mask Register1 */
  36 #define PCIE_DBI_RO_WR_EN       0x8bc /* DBI Read-Only Write Enable Register */
  37
  38 struct ls_pcie_drvdata {
  39         u32 lut_offset;
  40         u32 ltssm_shift;
  41         u32 lut_dbg;
  42         struct pcie_host_ops *ops;
  43 };
  44
  45 struct ls_pcie {
  46         struct pcie_port pp;            /* pp.dbi_base is DT regs */
  47         void __iomem *lut;
  48         struct regmap *scfg;
  49         const struct ls_pcie_drvdata *drvdata;
  50         int index;
  51 };
  52
  53 #define to_ls_pcie(x)   container_of(x, struct ls_pcie, pp)
  54
  55 static bool ls_pcie_is_bridge(struct ls_pcie *pcie)
  56 {
  57         u32 header_type;
  58
  59         header_type = ioread8(pcie->pp.dbi_base + PCI_HEADER_TYPE);
  60         header_type &= 0x7f;
  61
  62         return header_type == PCI_HEADER_TYPE_BRIDGE;
  63 }
  64
  65 /* Clear multi-function bit */
  66 static void ls_pcie_clear_multifunction(struct ls_pcie *pcie)
  67 {
  68         iowrite8(PCI_HEADER_TYPE_BRIDGE, pcie->pp.dbi_base + PCI_HEADER_TYPE);
  69 }
  70
  71 /* Fix class value */
  72 static void ls_pcie_fix_class(struct ls_pcie *pcie)
  73 {
  74         iowrite16(PCI_CLASS_BRIDGE_PCI, pcie->pp.dbi_base + PCI_CLASS_DEVICE);
  75 }
  76
  77 /* Drop MSG TLP except for Vendor MSG */
  78 static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
  79 {
  80         u32 val;
  81
  82         val = ioread32(pcie->pp.dbi_base + PCIE_STRFMR1);
  83         val &= 0xDFFFFFFF;
  84         iowrite32(val, pcie->pp.dbi_base + PCIE_STRFMR1);
  85 }
  86
  87 static int ls1021_pcie_link_up(struct pcie_port *pp)
  88 {
  89         u32 state;
  90         struct ls_pcie *pcie = to_ls_pcie(pp);
  91
  92         if (!pcie->scfg)
  93                 return 0;
  94
  95         regmap_read(pcie->scfg, SCFG_PEXMSCPORTSR(pcie->index), &state);
  96         state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
  97
  98         if (state < LTSSM_PCIE_L0)
  99                 return 0;
 100
 101         return 1;
 102 }
 103
 104 static void ls1021_pcie_host_init(struct pcie_port *pp)
 105 {
 106         struct device *dev = pp->dev;
 107         struct ls_pcie *pcie = to_ls_pcie(pp);
 108         u32 index[2];
 109
 110         pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node,
 111                                                      "fsl,pcie-scfg");
 112         if (IS_ERR(pcie->scfg)) {
 113                 dev_err(dev, "No syscfg phandle specified\n");
 114                 pcie->scfg = NULL;
 115                 return;
 116         }
 117
 118         if (of_property_read_u32_array(dev->of_node,
 119                                        "fsl,pcie-scfg", index, 2)) {
 120                 pcie->scfg = NULL;
 121                 return;
 122         }
 123         pcie->index = index[1];
 124
 125         dw_pcie_setup_rc(pp);
 126
 127         ls_pcie_drop_msg_tlp(pcie);
 128 }
 129
 130 static int ls_pcie_link_up(struct pcie_port *pp)
 131 {
 132         struct ls_pcie *pcie = to_ls_pcie(pp);
 133         u32 state;
 134
 135         state = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >>
 136                  pcie->drvdata->ltssm_shift) &
 137                  LTSSM_STATE_MASK;
 138
 139         if (state < LTSSM_PCIE_L0)
 140                 return 0;
 141
 142         return 1;
 143 }
 144
 145 static void ls_pcie_host_init(struct pcie_port *pp)
 146 {
 147         struct ls_pcie *pcie = to_ls_pcie(pp);
 148
 149         iowrite32(1, pcie->pp.dbi_base + PCIE_DBI_RO_WR_EN);
 150         ls_pcie_fix_class(pcie);
 151         ls_pcie_clear_multifunction(pcie);
 152         ls_pcie_drop_msg_tlp(pcie);
 153         iowrite32(0, pcie->pp.dbi_base + PCIE_DBI_RO_WR_EN);
 154 }
 155
 156 static int ls_pcie_msi_host_init(struct pcie_port *pp,
 157                                  struct msi_controller *chip)
 158 {
 159         struct device *dev = pp->dev;
 160         struct device_node *np = dev->of_node;
 161         struct device_node *msi_node;
 162
 163         /*
 164          * The MSI domain is set by the generic of_msi_configure().  This
 165          * .msi_host_init() function keeps us from doing the default MSI
 166          * domain setup in dw_pcie_host_init() and also enforces the
 167          * requirement that "msi-parent" exists.
 168          */
 169         msi_node = of_parse_phandle(np, "msi-parent", 0);
 170         if (!msi_node) {
 171                 dev_err(dev, "failed to find msi-parent\n");
 172                 return -EINVAL;
 173         }
 174
 175         return 0;
 176 }
 177
 178 static struct pcie_host_ops ls1021_pcie_host_ops = {
 179         .link_up = ls1021_pcie_link_up,
 180         .host_init = ls1021_pcie_host_init,
 181         .msi_host_init = ls_pcie_msi_host_init,
 182 };
 183
 184 static struct pcie_host_ops ls_pcie_host_ops = {
 185         .link_up = ls_pcie_link_up,
 186         .host_init = ls_pcie_host_init,
 187         .msi_host_init = ls_pcie_msi_host_init,
 188 };
 189
 190 static struct ls_pcie_drvdata ls1021_drvdata = {
 191         .ops = &ls1021_pcie_host_ops,
 192 };
 193
 194 static struct ls_pcie_drvdata ls1043_drvdata = {
 195         .lut_offset = 0x10000,
 196         .ltssm_shift = 24,
 197         .lut_dbg = 0x7fc,
 198         .ops = &ls_pcie_host_ops,
 199 };
 200
 201 static struct ls_pcie_drvdata ls1046_drvdata = {
 202         .lut_offset = 0x80000,
 203         .ltssm_shift = 24,
 204         .lut_dbg = 0x407fc,
 205         .ops = &ls_pcie_host_ops,
 206 };
 207
 208 static struct ls_pcie_drvdata ls2080_drvdata = {
 209         .lut_offset = 0x80000,
 210         .ltssm_shift = 0,
 211         .lut_dbg = 0x7fc,
 212         .ops = &ls_pcie_host_ops,
 213 };
 214
 215 static const struct of_device_id ls_pcie_of_match[] = {
 216         { .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata },
 217         { .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata },
 218         { .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata },
 219         { .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata },
 220         { .compatible = "fsl,ls2085a-pcie", .data = &ls2080_drvdata },
 221         { },
 222 };
 223
 224 static int __init ls_add_pcie_port(struct ls_pcie *pcie)
 225 {
 226         struct pcie_port *pp = &pcie->pp;
 227         struct device *dev = pp->dev;
 228         int ret;
 229
 230         ret = dw_pcie_host_init(pp);
 231         if (ret) {
 232                 dev_err(dev, "failed to initialize host\n");
 233                 return ret;
 234         }
 235
 236         return 0;
 237 }
 238
 239 static int __init ls_pcie_probe(struct platform_device *pdev)
 240 {
 241         struct device *dev = &pdev->dev;
 242         const struct of_device_id *match;
 243         struct ls_pcie *pcie;
 244         struct pcie_port *pp;
 245         struct resource *dbi_base;
 246         int ret;
 247
 248         match = of_match_device(ls_pcie_of_match, dev);
 249         if (!match)
 250                 return -ENODEV;
 251
 252         pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
 253         if (!pcie)
 254                 return -ENOMEM;
 255
 256         pp = &pcie->pp;
 257         pp->dev = dev;
 258         pcie->drvdata = match->data;
 259         pp->ops = pcie->drvdata->ops;
 260
 261         dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
 262         pcie->pp.dbi_base = devm_ioremap_resource(dev, dbi_base);
 263         if (IS_ERR(pcie->pp.dbi_base))
 264                 return PTR_ERR(pcie->pp.dbi_base);
 265
 266         pcie->lut = pcie->pp.dbi_base + pcie->drvdata->lut_offset;
 267
 268         if (!ls_pcie_is_bridge(pcie))
 269                 return -ENODEV;
 270
 271         ret = ls_add_pcie_port(pcie);
 272         if (ret < 0)
 273                 return ret;
 274
 275         return 0;
 276 }
 277
 278 static struct platform_driver ls_pcie_driver = {
 279         .driver = {
 280                 .name = "layerscape-pcie",
 281                 .of_match_table = ls_pcie_of_match,
 282         },
 283 };
 284 builtin_platform_driver_probe(ls_pcie_driver, ls_pcie_probe);