2 * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $
4 * PCI Bus Services, see include/linux/pci.h for further explanation.
6 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
9 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/init.h>
15 #include <linux/pci.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <asm/dma.h> /* isa_dma_bridge_buggy */
23 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
24 * @bus: pointer to PCI bus structure to search
26 * Given a PCI bus, returns the highest PCI bus number present in the set
27 * including the given PCI bus and its list of child PCI buses.
29 unsigned char __devinit
30 pci_bus_max_busnr(struct pci_bus
* bus
)
32 struct list_head
*tmp
;
36 list_for_each(tmp
, &bus
->children
) {
37 n
= pci_bus_max_busnr(pci_bus_b(tmp
));
45 * pci_max_busnr - returns maximum PCI bus number
47 * Returns the highest PCI bus number present in the system global list of
50 unsigned char __devinit
53 struct pci_bus
*bus
= NULL
;
57 while ((bus
= pci_find_next_bus(bus
)) != NULL
) {
58 n
= pci_bus_max_busnr(bus
);
65 static int __pci_bus_find_cap(struct pci_bus
*bus
, unsigned int devfn
, u8 hdr_type
, int cap
)
71 pci_bus_read_config_word(bus
, devfn
, PCI_STATUS
, &status
);
72 if (!(status
& PCI_STATUS_CAP_LIST
))
76 case PCI_HEADER_TYPE_NORMAL
:
77 case PCI_HEADER_TYPE_BRIDGE
:
78 pci_bus_read_config_byte(bus
, devfn
, PCI_CAPABILITY_LIST
, &pos
);
80 case PCI_HEADER_TYPE_CARDBUS
:
81 pci_bus_read_config_byte(bus
, devfn
, PCI_CB_CAPABILITY_LIST
, &pos
);
86 while (ttl
-- && pos
>= 0x40) {
88 pci_bus_read_config_byte(bus
, devfn
, pos
+ PCI_CAP_LIST_ID
, &id
);
93 pci_bus_read_config_byte(bus
, devfn
, pos
+ PCI_CAP_LIST_NEXT
, &pos
);
99 * pci_find_capability - query for devices' capabilities
100 * @dev: PCI device to query
101 * @cap: capability code
103 * Tell if a device supports a given PCI capability.
104 * Returns the address of the requested capability structure within the
105 * device's PCI configuration space or 0 in case the device does not
106 * support it. Possible values for @cap:
108 * %PCI_CAP_ID_PM Power Management
109 * %PCI_CAP_ID_AGP Accelerated Graphics Port
110 * %PCI_CAP_ID_VPD Vital Product Data
111 * %PCI_CAP_ID_SLOTID Slot Identification
112 * %PCI_CAP_ID_MSI Message Signalled Interrupts
113 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
114 * %PCI_CAP_ID_PCIX PCI-X
115 * %PCI_CAP_ID_EXP PCI Express
117 int pci_find_capability(struct pci_dev
*dev
, int cap
)
119 return __pci_bus_find_cap(dev
->bus
, dev
->devfn
, dev
->hdr_type
, cap
);
123 * pci_bus_find_capability - query for devices' capabilities
124 * @bus: the PCI bus to query
125 * @devfn: PCI device to query
126 * @cap: capability code
128 * Like pci_find_capability() but works for pci devices that do not have a
129 * pci_dev structure set up yet.
131 * Returns the address of the requested capability structure within the
132 * device's PCI configuration space or 0 in case the device does not
135 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
)
139 pci_bus_read_config_byte(bus
, devfn
, PCI_HEADER_TYPE
, &hdr_type
);
141 return __pci_bus_find_cap(bus
, devfn
, hdr_type
& 0x7f, cap
);
145 * pci_find_ext_capability - Find an extended capability
146 * @dev: PCI device to query
147 * @cap: capability code
149 * Returns the address of the requested extended capability structure
150 * within the device's PCI configuration space or 0 if the device does
151 * not support it. Possible values for @cap:
153 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
154 * %PCI_EXT_CAP_ID_VC Virtual Channel
155 * %PCI_EXT_CAP_ID_DSN Device Serial Number
156 * %PCI_EXT_CAP_ID_PWR Power Budgeting
158 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
161 int ttl
= 480; /* 3840 bytes, minimum 8 bytes per capability */
164 if (dev
->cfg_size
<= 256)
167 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
171 * If we have no capabilities, this is indicated by cap ID,
172 * cap version and next pointer all being 0.
178 if (PCI_EXT_CAP_ID(header
) == cap
)
181 pos
= PCI_EXT_CAP_NEXT(header
);
185 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
193 * pci_find_parent_resource - return resource region of parent bus of given region
194 * @dev: PCI device structure contains resources to be searched
195 * @res: child resource record for which parent is sought
197 * For given resource region of given device, return the resource
198 * region of parent bus the given region is contained in or where
199 * it should be allocated from.
202 pci_find_parent_resource(const struct pci_dev
*dev
, struct resource
*res
)
204 const struct pci_bus
*bus
= dev
->bus
;
206 struct resource
*best
= NULL
;
208 for(i
= 0; i
< PCI_BUS_NUM_RESOURCES
; i
++) {
209 struct resource
*r
= bus
->resource
[i
];
212 if (res
->start
&& !(res
->start
>= r
->start
&& res
->end
<= r
->end
))
213 continue; /* Not contained */
214 if ((res
->flags
^ r
->flags
) & (IORESOURCE_IO
| IORESOURCE_MEM
))
215 continue; /* Wrong type */
216 if (!((res
->flags
^ r
->flags
) & IORESOURCE_PREFETCH
))
217 return r
; /* Exact match */
218 if ((res
->flags
& IORESOURCE_PREFETCH
) && !(r
->flags
& IORESOURCE_PREFETCH
))
219 best
= r
; /* Approximating prefetchable by non-prefetchable */
225 * pci_set_power_state - Set the power state of a PCI device
226 * @dev: PCI device to be suspended
227 * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering
229 * Transition a device to a new power state, using the Power Management
230 * Capabilities in the device's config space.
233 * -EINVAL if trying to enter a lower state than we're already in.
234 * 0 if we're already in the requested state.
235 * -EIO if device does not support PCI PM.
236 * 0 if we can successfully change the power state.
238 int (*platform_pci_set_power_state
)(struct pci_dev
*dev
, pci_power_t t
);
240 pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
245 /* bound the state we're entering */
246 if (state
> PCI_D3hot
)
249 /* Validate current state:
250 * Can enter D0 from any state, but if we can only go deeper
251 * to sleep if we're already in a low power state
253 if (state
!= PCI_D0
&& dev
->current_state
> state
)
255 else if (dev
->current_state
== state
)
256 return 0; /* we're already there */
258 /* find PCI PM capability in list */
259 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
261 /* abort if the device doesn't support PM capabilities */
265 pci_read_config_word(dev
,pm
+ PCI_PM_PMC
,&pmc
);
266 if ((pmc
& PCI_PM_CAP_VER_MASK
) > 2) {
268 "PCI: %s has unsupported PM cap regs version (%u)\n",
269 pci_name(dev
), pmc
& PCI_PM_CAP_VER_MASK
);
273 /* check if this device supports the desired state */
274 if (state
== PCI_D1
|| state
== PCI_D2
) {
275 if (state
== PCI_D1
&& !(pmc
& PCI_PM_CAP_D1
))
277 else if (state
== PCI_D2
&& !(pmc
& PCI_PM_CAP_D2
))
281 /* If we're in D3, force entire word to 0.
282 * This doesn't affect PME_Status, disables PME_En, and
283 * sets PowerState to 0.
285 if (dev
->current_state
>= PCI_D3hot
)
288 pci_read_config_word(dev
, pm
+ PCI_PM_CTRL
, &pmcsr
);
289 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
293 /* enter specified state */
294 pci_write_config_word(dev
, pm
+ PCI_PM_CTRL
, pmcsr
);
296 /* Mandatory power management transition delays */
297 /* see PCI PM 1.1 5.6.1 table 18 */
298 if (state
== PCI_D3hot
|| dev
->current_state
== PCI_D3hot
)
300 else if (state
== PCI_D2
|| dev
->current_state
== PCI_D2
)
304 * Give firmware a chance to be called, such as ACPI _PRx, _PSx
305 * Firmware method after natice method ?
307 if (platform_pci_set_power_state
)
308 platform_pci_set_power_state(dev
, state
);
310 dev
->current_state
= state
;
314 int (*platform_pci_choose_state
)(struct pci_dev
*dev
, pm_message_t state
);
317 * pci_choose_state - Choose the power state of a PCI device
318 * @dev: PCI device to be suspended
319 * @state: target sleep state for the whole system. This is the value
320 * that is passed to suspend() function.
322 * Returns PCI power state suitable for given device and given system
326 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
)
330 if (!pci_find_capability(dev
, PCI_CAP_ID_PM
))
333 if (platform_pci_choose_state
) {
334 ret
= platform_pci_choose_state(dev
, state
);
339 case 0: return PCI_D0
;
340 case 3: return PCI_D3hot
;
342 printk("They asked me for state %d\n", state
);
348 EXPORT_SYMBOL(pci_choose_state
);
351 * pci_save_state - save the PCI configuration space of a device before suspending
352 * @dev: - PCI device that we're dealing with
355 pci_save_state(struct pci_dev
*dev
)
358 /* XXX: 100% dword access ok here? */
359 for (i
= 0; i
< 16; i
++)
360 pci_read_config_dword(dev
, i
* 4,&dev
->saved_config_space
[i
]);
365 * pci_restore_state - Restore the saved state of a PCI device
366 * @dev: - PCI device that we're dealing with
369 pci_restore_state(struct pci_dev
*dev
)
373 for (i
= 0; i
< 16; i
++)
374 pci_write_config_dword(dev
,i
* 4, dev
->saved_config_space
[i
]);
379 * pci_enable_device_bars - Initialize some of a device for use
380 * @dev: PCI device to be initialized
381 * @bars: bitmask of BAR's that must be configured
383 * Initialize device before it's used by a driver. Ask low-level code
384 * to enable selected I/O and memory resources. Wake up the device if it
385 * was suspended. Beware, this function can fail.
389 pci_enable_device_bars(struct pci_dev
*dev
, int bars
)
393 pci_set_power_state(dev
, PCI_D0
);
394 if ((err
= pcibios_enable_device(dev
, bars
)) < 0)
400 * pci_enable_device - Initialize device before it's used by a driver.
401 * @dev: PCI device to be initialized
403 * Initialize device before it's used by a driver. Ask low-level code
404 * to enable I/O and memory. Wake up the device if it was suspended.
405 * Beware, this function can fail.
408 pci_enable_device(struct pci_dev
*dev
)
412 if ((err
= pci_enable_device_bars(dev
, (1 << PCI_NUM_RESOURCES
) - 1)))
414 pci_fixup_device(pci_fixup_enable
, dev
);
420 * pcibios_disable_device - disable arch specific PCI resources for device dev
421 * @dev: the PCI device to disable
423 * Disables architecture specific PCI resources for the device. This
424 * is the default implementation. Architecture implementations can
427 void __attribute__ ((weak
)) pcibios_disable_device (struct pci_dev
*dev
) {}
430 * pci_disable_device - Disable PCI device after use
431 * @dev: PCI device to be disabled
433 * Signal to the system that the PCI device is not in use by the system
434 * anymore. This only involves disabling PCI bus-mastering, if active.
437 pci_disable_device(struct pci_dev
*dev
)
441 pci_read_config_word(dev
, PCI_COMMAND
, &pci_command
);
442 if (pci_command
& PCI_COMMAND_MASTER
) {
443 pci_command
&= ~PCI_COMMAND_MASTER
;
444 pci_write_config_word(dev
, PCI_COMMAND
, pci_command
);
446 dev
->is_busmaster
= 0;
448 pcibios_disable_device(dev
);
453 * pci_enable_wake - enable device to generate PME# when suspended
454 * @dev: - PCI device to operate on
455 * @state: - Current state of device.
456 * @enable: - Flag to enable or disable generation
458 * Set the bits in the device's PM Capabilities to generate PME# when
459 * the system is suspended.
461 * -EIO is returned if device doesn't have PM Capabilities.
462 * -EINVAL is returned if device supports it, but can't generate wake events.
463 * 0 if operation is successful.
466 int pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
, int enable
)
471 /* find PCI PM capability in list */
472 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
474 /* If device doesn't support PM Capabilities, but request is to disable
475 * wake events, it's a nop; otherwise fail */
477 return enable
? -EIO
: 0;
479 /* Check device's ability to generate PME# */
480 pci_read_config_word(dev
,pm
+PCI_PM_PMC
,&value
);
482 value
&= PCI_PM_CAP_PME_MASK
;
483 value
>>= ffs(PCI_PM_CAP_PME_MASK
) - 1; /* First bit of mask */
485 /* Check if it can generate PME# from requested state. */
486 if (!value
|| !(value
& (1 << state
)))
487 return enable
? -EINVAL
: 0;
489 pci_read_config_word(dev
, pm
+ PCI_PM_CTRL
, &value
);
491 /* Clear PME_Status by writing 1 to it and enable PME# */
492 value
|= PCI_PM_CTRL_PME_STATUS
| PCI_PM_CTRL_PME_ENABLE
;
495 value
&= ~PCI_PM_CTRL_PME_ENABLE
;
497 pci_write_config_word(dev
, pm
+ PCI_PM_CTRL
, value
);
503 pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
)
507 pci_read_config_byte(dev
, PCI_INTERRUPT_PIN
, &pin
);
511 while (dev
->bus
->self
) {
512 pin
= (pin
+ PCI_SLOT(dev
->devfn
)) % 4;
513 dev
= dev
->bus
->self
;
520 * pci_release_region - Release a PCI bar
521 * @pdev: PCI device whose resources were previously reserved by pci_request_region
522 * @bar: BAR to release
524 * Releases the PCI I/O and memory resources previously reserved by a
525 * successful call to pci_request_region. Call this function only
526 * after all use of the PCI regions has ceased.
528 void pci_release_region(struct pci_dev
*pdev
, int bar
)
530 if (pci_resource_len(pdev
, bar
) == 0)
532 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
)
533 release_region(pci_resource_start(pdev
, bar
),
534 pci_resource_len(pdev
, bar
));
535 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)
536 release_mem_region(pci_resource_start(pdev
, bar
),
537 pci_resource_len(pdev
, bar
));
541 * pci_request_region - Reserved PCI I/O and memory resource
542 * @pdev: PCI device whose resources are to be reserved
543 * @bar: BAR to be reserved
544 * @res_name: Name to be associated with resource.
546 * Mark the PCI region associated with PCI device @pdev BR @bar as
547 * being reserved by owner @res_name. Do not access any
548 * address inside the PCI regions unless this call returns
551 * Returns 0 on success, or %EBUSY on error. A warning
552 * message is also printed on failure.
554 int pci_request_region(struct pci_dev
*pdev
, int bar
, char *res_name
)
556 if (pci_resource_len(pdev
, bar
) == 0)
559 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
) {
560 if (!request_region(pci_resource_start(pdev
, bar
),
561 pci_resource_len(pdev
, bar
), res_name
))
564 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
) {
565 if (!request_mem_region(pci_resource_start(pdev
, bar
),
566 pci_resource_len(pdev
, bar
), res_name
))
573 printk (KERN_WARNING
"PCI: Unable to reserve %s region #%d:%lx@%lx for device %s\n",
574 pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
? "I/O" : "mem",
575 bar
+ 1, /* PCI BAR # */
576 pci_resource_len(pdev
, bar
), pci_resource_start(pdev
, bar
),
583 * pci_release_regions - Release reserved PCI I/O and memory resources
584 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
586 * Releases all PCI I/O and memory resources previously reserved by a
587 * successful call to pci_request_regions. Call this function only
588 * after all use of the PCI regions has ceased.
591 void pci_release_regions(struct pci_dev
*pdev
)
595 for (i
= 0; i
< 6; i
++)
596 pci_release_region(pdev
, i
);
600 * pci_request_regions - Reserved PCI I/O and memory resources
601 * @pdev: PCI device whose resources are to be reserved
602 * @res_name: Name to be associated with resource.
604 * Mark all PCI regions associated with PCI device @pdev as
605 * being reserved by owner @res_name. Do not access any
606 * address inside the PCI regions unless this call returns
609 * Returns 0 on success, or %EBUSY on error. A warning
610 * message is also printed on failure.
612 int pci_request_regions(struct pci_dev
*pdev
, char *res_name
)
616 for (i
= 0; i
< 6; i
++)
617 if(pci_request_region(pdev
, i
, res_name
))
623 pci_release_region(pdev
, i
);
629 * pci_set_master - enables bus-mastering for device dev
630 * @dev: the PCI device to enable
632 * Enables bus-mastering on the device and calls pcibios_set_master()
633 * to do the needed arch specific settings.
636 pci_set_master(struct pci_dev
*dev
)
640 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
641 if (! (cmd
& PCI_COMMAND_MASTER
)) {
642 pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev
));
643 cmd
|= PCI_COMMAND_MASTER
;
644 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
646 dev
->is_busmaster
= 1;
647 pcibios_set_master(dev
);
650 #ifndef HAVE_ARCH_PCI_MWI
651 /* This can be overridden by arch code. */
652 u8 pci_cache_line_size
= L1_CACHE_BYTES
>> 2;
655 * pci_generic_prep_mwi - helper function for pci_set_mwi
656 * @dev: the PCI device for which MWI is enabled
658 * Helper function for generic implementation of pcibios_prep_mwi
659 * function. Originally copied from drivers/net/acenic.c.
660 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
662 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
665 pci_generic_prep_mwi(struct pci_dev
*dev
)
669 if (!pci_cache_line_size
)
670 return -EINVAL
; /* The system doesn't support MWI. */
672 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
673 equal to or multiple of the right value. */
674 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
675 if (cacheline_size
>= pci_cache_line_size
&&
676 (cacheline_size
% pci_cache_line_size
) == 0)
679 /* Write the correct value. */
680 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, pci_cache_line_size
);
682 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
683 if (cacheline_size
== pci_cache_line_size
)
686 printk(KERN_DEBUG
"PCI: cache line size of %d is not supported "
687 "by device %s\n", pci_cache_line_size
<< 2, pci_name(dev
));
691 #endif /* !HAVE_ARCH_PCI_MWI */
694 * pci_set_mwi - enables memory-write-invalidate PCI transaction
695 * @dev: the PCI device for which MWI is enabled
697 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND,
698 * and then calls @pcibios_set_mwi to do the needed arch specific
699 * operations or a generic mwi-prep function.
701 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
704 pci_set_mwi(struct pci_dev
*dev
)
709 #ifdef HAVE_ARCH_PCI_MWI
710 rc
= pcibios_prep_mwi(dev
);
712 rc
= pci_generic_prep_mwi(dev
);
718 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
719 if (! (cmd
& PCI_COMMAND_INVALIDATE
)) {
720 pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n", pci_name(dev
));
721 cmd
|= PCI_COMMAND_INVALIDATE
;
722 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
729 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
730 * @dev: the PCI device to disable
732 * Disables PCI Memory-Write-Invalidate transaction on the device
735 pci_clear_mwi(struct pci_dev
*dev
)
739 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
740 if (cmd
& PCI_COMMAND_INVALIDATE
) {
741 cmd
&= ~PCI_COMMAND_INVALIDATE
;
742 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
746 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
748 * These can be overridden by arch-specific implementations
751 pci_set_dma_mask(struct pci_dev
*dev
, u64 mask
)
753 if (!pci_dma_supported(dev
, mask
))
756 dev
->dma_mask
= mask
;
762 pci_set_consistent_dma_mask(struct pci_dev
*dev
, u64 mask
)
764 if (!pci_dma_supported(dev
, mask
))
767 dev
->dev
.coherent_dma_mask
= mask
;
773 static int __devinit
pci_init(void)
775 struct pci_dev
*dev
= NULL
;
777 while ((dev
= pci_get_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
)) != NULL
) {
778 pci_fixup_device(pci_fixup_final
, dev
);
783 static int __devinit
pci_setup(char *str
)
786 char *k
= strchr(str
, ',');
789 if (*str
&& (str
= pcibios_setup(str
)) && *str
) {
790 /* PCI layer options should be handled here */
791 printk(KERN_ERR
"PCI: Unknown option `%s'\n", str
);
798 device_initcall(pci_init
);
800 __setup("pci=", pci_setup
);
802 #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
803 /* FIXME: Some boxes have multiple ISA bridges! */
804 struct pci_dev
*isa_bridge
;
805 EXPORT_SYMBOL(isa_bridge
);
808 EXPORT_SYMBOL(pci_enable_device_bars
);
809 EXPORT_SYMBOL(pci_enable_device
);
810 EXPORT_SYMBOL(pci_disable_device
);
811 EXPORT_SYMBOL(pci_max_busnr
);
812 EXPORT_SYMBOL(pci_bus_max_busnr
);
813 EXPORT_SYMBOL(pci_find_capability
);
814 EXPORT_SYMBOL(pci_bus_find_capability
);
815 EXPORT_SYMBOL(pci_release_regions
);
816 EXPORT_SYMBOL(pci_request_regions
);
817 EXPORT_SYMBOL(pci_release_region
);
818 EXPORT_SYMBOL(pci_request_region
);
819 EXPORT_SYMBOL(pci_set_master
);
820 EXPORT_SYMBOL(pci_set_mwi
);
821 EXPORT_SYMBOL(pci_clear_mwi
);
822 EXPORT_SYMBOL(pci_set_dma_mask
);
823 EXPORT_SYMBOL(pci_set_consistent_dma_mask
);
824 EXPORT_SYMBOL(pci_assign_resource
);
825 EXPORT_SYMBOL(pci_find_parent_resource
);
827 EXPORT_SYMBOL(pci_set_power_state
);
828 EXPORT_SYMBOL(pci_save_state
);
829 EXPORT_SYMBOL(pci_restore_state
);
830 EXPORT_SYMBOL(pci_enable_wake
);
834 EXPORT_SYMBOL(isa_dma_bridge_buggy
);
835 EXPORT_SYMBOL(pci_pci_problems
);