drivers/pci/pci.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef DRIVERS_PCI_H
   3 #define DRIVERS_PCI_H
   4
   5 #include <linux/pci.h>
   6
   7 /* Number of possible devfns: 0.0 to 1f.7 inclusive */
   8 #define MAX_NR_DEVFNS 256
   9
  10 #define PCI_FIND_CAP_TTL        48
  11
  12 #define PCI_VSEC_ID_INTEL_TBT   0x1234  /* Thunderbolt */
  13
  14 extern const unsigned char pcie_link_speed[];
  15 extern bool pci_early_dump;
  16
  17 bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
  18 bool pcie_cap_has_rtctl(const struct pci_dev *dev);
  19
  20 /* Functions internal to the PCI core code */
  21
  22 int pci_create_sysfs_dev_files(struct pci_dev *pdev);
  23 void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
  24 void pci_cleanup_rom(struct pci_dev *dev);
  25 #ifdef CONFIG_DMI
  26 extern const struct attribute_group pci_dev_smbios_attr_group;
  27 #endif
  28
  29 enum pci_mmap_api {
  30         PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
  31         PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
  32 };
  33 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
  34                   enum pci_mmap_api mmap_api);
  35
  36 bool pci_reset_supported(struct pci_dev *dev);
  37 void pci_init_reset_methods(struct pci_dev *dev);
  38 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
  39 int pci_bus_error_reset(struct pci_dev *dev);
  40
  41 struct pci_cap_saved_data {
  42         u16             cap_nr;
  43         bool            cap_extended;
  44         unsigned int    size;
  45         u32             data[];
  46 };
  47
  48 struct pci_cap_saved_state {
  49         struct hlist_node               next;
  50         struct pci_cap_saved_data       cap;
  51 };
  52
  53 void pci_allocate_cap_save_buffers(struct pci_dev *dev);
  54 void pci_free_cap_save_buffers(struct pci_dev *dev);
  55 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
  56 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
  57                                 u16 cap, unsigned int size);
  58 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
  59 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
  60                                                    u16 cap);
  61
  62 #define PCI_PM_D2_DELAY         200     /* usec; see PCIe r4.0, sec 5.9.1 */
  63 #define PCI_PM_D3HOT_WAIT       10      /* msec */
  64 #define PCI_PM_D3COLD_WAIT      100     /* msec */
  65
  66 /**
  67  * struct pci_platform_pm_ops - Firmware PM callbacks
  68  *
  69  * @bridge_d3: Does the bridge allow entering into D3
  70  *
  71  * @is_manageable: returns 'true' if given device is power manageable by the
  72  *                 platform firmware
  73  *
  74  * @set_state: invokes the platform firmware to set the device's power state
  75  *
  76  * @get_state: queries the platform firmware for a device's current power state
  77  *
  78  * @refresh_state: asks the platform to refresh the device's power state data
  79  *
  80  * @choose_state: returns PCI power state of given device preferred by the
  81  *                platform; to be used during system-wide transitions from a
  82  *                sleeping state to the working state and vice versa
  83  *
  84  * @set_wakeup: enables/disables wakeup capability for the device
  85  *
  86  * @need_resume: returns 'true' if the given device (which is currently
  87  *               suspended) needs to be resumed to be configured for system
  88  *               wakeup.
  89  *
  90  * If given platform is generally capable of power managing PCI devices, all of
  91  * these callbacks are mandatory.
  92  */
  93 struct pci_platform_pm_ops {
  94         bool (*bridge_d3)(struct pci_dev *dev);
  95         bool (*is_manageable)(struct pci_dev *dev);
  96         int (*set_state)(struct pci_dev *dev, pci_power_t state);
  97         pci_power_t (*get_state)(struct pci_dev *dev);
  98         void (*refresh_state)(struct pci_dev *dev);
  99         pci_power_t (*choose_state)(struct pci_dev *dev);
 100         int (*set_wakeup)(struct pci_dev *dev, bool enable);
 101         bool (*need_resume)(struct pci_dev *dev);
 102 };
 103
 104 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops);
 105 void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
 106 void pci_refresh_power_state(struct pci_dev *dev);
 107 int pci_power_up(struct pci_dev *dev);
 108 void pci_disable_enabled_device(struct pci_dev *dev);
 109 int pci_finish_runtime_suspend(struct pci_dev *dev);
 110 void pcie_clear_device_status(struct pci_dev *dev);
 111 void pcie_clear_root_pme_status(struct pci_dev *dev);
 112 bool pci_check_pme_status(struct pci_dev *dev);
 113 void pci_pme_wakeup_bus(struct pci_bus *bus);
 114 int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
 115 void pci_pme_restore(struct pci_dev *dev);
 116 bool pci_dev_need_resume(struct pci_dev *dev);
 117 void pci_dev_adjust_pme(struct pci_dev *dev);
 118 void pci_dev_complete_resume(struct pci_dev *pci_dev);
 119 void pci_config_pm_runtime_get(struct pci_dev *dev);
 120 void pci_config_pm_runtime_put(struct pci_dev *dev);
 121 void pci_pm_init(struct pci_dev *dev);
 122 void pci_ea_init(struct pci_dev *dev);
 123 void pci_msi_init(struct pci_dev *dev);
 124 void pci_msix_init(struct pci_dev *dev);
 125 bool pci_bridge_d3_possible(struct pci_dev *dev);
 126 void pci_bridge_d3_update(struct pci_dev *dev);
 127 void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev);
 128 void pci_bridge_reconfigure_ltr(struct pci_dev *dev);
 129
 130 static inline void pci_wakeup_event(struct pci_dev *dev)
 131 {
 132         /* Wait 100 ms before the system can be put into a sleep state. */
 133         pm_wakeup_event(&dev->dev, 100);
 134 }
 135
 136 static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
 137 {
 138         return !!(pci_dev->subordinate);
 139 }
 140
 141 static inline bool pci_power_manageable(struct pci_dev *pci_dev)
 142 {
 143         /*
 144          * Currently we allow normal PCI devices and PCI bridges transition
 145          * into D3 if their bridge_d3 is set.
 146          */
 147         return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
 148 }
 149
 150 static inline bool pcie_downstream_port(const struct pci_dev *dev)
 151 {
 152         int type = pci_pcie_type(dev);
 153
 154         return type == PCI_EXP_TYPE_ROOT_PORT ||
 155                type == PCI_EXP_TYPE_DOWNSTREAM ||
 156                type == PCI_EXP_TYPE_PCIE_BRIDGE;
 157 }
 158
 159 void pci_vpd_init(struct pci_dev *dev);
 160 void pci_vpd_release(struct pci_dev *dev);
 161 extern const struct attribute_group pci_dev_vpd_attr_group;
 162
 163 /* PCI Virtual Channel */
 164 int pci_save_vc_state(struct pci_dev *dev);
 165 void pci_restore_vc_state(struct pci_dev *dev);
 166 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
 167
 168 /* PCI /proc functions */
 169 #ifdef CONFIG_PROC_FS
 170 int pci_proc_attach_device(struct pci_dev *dev);
 171 int pci_proc_detach_device(struct pci_dev *dev);
 172 int pci_proc_detach_bus(struct pci_bus *bus);
 173 #else
 174 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
 175 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
 176 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
 177 #endif
 178
 179 /* Functions for PCI Hotplug drivers to use */
 180 int pci_hp_add_bridge(struct pci_dev *dev);
 181
 182 #ifdef HAVE_PCI_LEGACY
 183 void pci_create_legacy_files(struct pci_bus *bus);
 184 void pci_remove_legacy_files(struct pci_bus *bus);
 185 #else
 186 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
 187 static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
 188 #endif
 189
 190 /* Lock for read/write access to pci device and bus lists */
 191 extern struct rw_semaphore pci_bus_sem;
 192 extern struct mutex pci_slot_mutex;
 193
 194 extern raw_spinlock_t pci_lock;
 195
 196 extern unsigned int pci_pm_d3hot_delay;
 197
 198 #ifdef CONFIG_PCI_MSI
 199 void pci_no_msi(void);
 200 #else
 201 static inline void pci_no_msi(void) { }
 202 #endif
 203
 204 void pci_realloc_get_opt(char *);
 205
 206 static inline int pci_no_d1d2(struct pci_dev *dev)
 207 {
 208         unsigned int parent_dstates = 0;
 209
 210         if (dev->bus->self)
 211                 parent_dstates = dev->bus->self->no_d1d2;
 212         return (dev->no_d1d2 || parent_dstates);
 213
 214 }
 215 extern const struct attribute_group *pci_dev_groups[];
 216 extern const struct attribute_group *pcibus_groups[];
 217 extern const struct device_type pci_dev_type;
 218 extern const struct attribute_group *pci_bus_groups[];
 219
 220 extern unsigned long pci_hotplug_io_size;
 221 extern unsigned long pci_hotplug_mmio_size;
 222 extern unsigned long pci_hotplug_mmio_pref_size;
 223 extern unsigned long pci_hotplug_bus_size;
 224
 225 /**
 226  * pci_match_one_device - Tell if a PCI device structure has a matching
 227  *                        PCI device id structure
 228  * @id: single PCI device id structure to match
 229  * @dev: the PCI device structure to match against
 230  *
 231  * Returns the matching pci_device_id structure or %NULL if there is no match.
 232  */
 233 static inline const struct pci_device_id *
 234 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
 235 {
 236         if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
 237             (id->device == PCI_ANY_ID || id->device == dev->device) &&
 238             (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
 239             (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
 240             !((id->class ^ dev->class) & id->class_mask))
 241                 return id;
 242         return NULL;
 243 }
 244
 245 /* PCI slot sysfs helper code */
 246 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
 247
 248 extern struct kset *pci_slots_kset;
 249
 250 struct pci_slot_attribute {
 251         struct attribute attr;
 252         ssize_t (*show)(struct pci_slot *, char *);
 253         ssize_t (*store)(struct pci_slot *, const char *, size_t);
 254 };
 255 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
 256
 257 enum pci_bar_type {
 258         pci_bar_unknown,        /* Standard PCI BAR probe */
 259         pci_bar_io,             /* An I/O port BAR */
 260         pci_bar_mem32,          /* A 32-bit memory BAR */
 261         pci_bar_mem64,          /* A 64-bit memory BAR */
 262 };
 263
 264 struct device *pci_get_host_bridge_device(struct pci_dev *dev);
 265 void pci_put_host_bridge_device(struct device *dev);
 266
 267 int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
 268 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
 269                                 int crs_timeout);
 270 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
 271                                         int crs_timeout);
 272 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout);
 273
 274 int pci_setup_device(struct pci_dev *dev);
 275 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
 276                     struct resource *res, unsigned int reg);
 277 void pci_configure_ari(struct pci_dev *dev);
 278 void __pci_bus_size_bridges(struct pci_bus *bus,
 279                         struct list_head *realloc_head);
 280 void __pci_bus_assign_resources(const struct pci_bus *bus,
 281                                 struct list_head *realloc_head,
 282                                 struct list_head *fail_head);
 283 bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
 284
 285 void pci_reassigndev_resource_alignment(struct pci_dev *dev);
 286 void pci_disable_bridge_window(struct pci_dev *dev);
 287 struct pci_bus *pci_bus_get(struct pci_bus *bus);
 288 void pci_bus_put(struct pci_bus *bus);
 289
 290 /* PCIe link information from Link Capabilities 2 */
 291 #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \
 292         ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \
 293          (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
 294          (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
 295          (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
 296          (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \
 297          (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \
 298          PCI_SPEED_UNKNOWN)
 299
 300 /* PCIe speed to Mb/s reduced by encoding overhead */
 301 #define PCIE_SPEED2MBS_ENC(speed) \
 302         ((speed) == PCIE_SPEED_64_0GT ? 64000*128/130 : \
 303          (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \
 304          (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
 305          (speed) == PCIE_SPEED_8_0GT  ?  8000*128/130 : \
 306          (speed) == PCIE_SPEED_5_0GT  ?  5000*8/10 : \
 307          (speed) == PCIE_SPEED_2_5GT  ?  2500*8/10 : \
 308          0)
 309
 310 const char *pci_speed_string(enum pci_bus_speed speed);
 311 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
 312 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
 313 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
 314                            enum pcie_link_width *width);
 315 void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
 316 void pcie_report_downtraining(struct pci_dev *dev);
 317 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
 318
 319 /* Single Root I/O Virtualization */
 320 struct pci_sriov {
 321         int             pos;            /* Capability position */
 322         int             nres;           /* Number of resources */
 323         u32             cap;            /* SR-IOV Capabilities */
 324         u16             ctrl;           /* SR-IOV Control */
 325         u16             total_VFs;      /* Total VFs associated with the PF */
 326         u16             initial_VFs;    /* Initial VFs associated with the PF */
 327         u16             num_VFs;        /* Number of VFs available */
 328         u16             offset;         /* First VF Routing ID offset */
 329         u16             stride;         /* Following VF stride */
 330         u16             vf_device;      /* VF device ID */
 331         u32             pgsz;           /* Page size for BAR alignment */
 332         u8              link;           /* Function Dependency Link */
 333         u8              max_VF_buses;   /* Max buses consumed by VFs */
 334         u16             driver_max_VFs; /* Max num VFs driver supports */
 335         struct pci_dev  *dev;           /* Lowest numbered PF */
 336         struct pci_dev  *self;          /* This PF */
 337         u32             class;          /* VF device */
 338         u8              hdr_type;       /* VF header type */
 339         u16             subsystem_vendor; /* VF subsystem vendor */
 340         u16             subsystem_device; /* VF subsystem device */
 341         resource_size_t barsz[PCI_SRIOV_NUM_BARS];      /* VF BAR size */
 342         bool            drivers_autoprobe; /* Auto probing of VFs by driver */
 343 };
 344
 345 /**
 346  * pci_dev_set_io_state - Set the new error state if possible.
 347  *
 348  * @dev: PCI device to set new error_state
 349  * @new: the state we want dev to be in
 350  *
 351  * Must be called with device_lock held.
 352  *
 353  * Returns true if state has been changed to the requested state.
 354  */
 355 static inline bool pci_dev_set_io_state(struct pci_dev *dev,
 356                                         pci_channel_state_t new)
 357 {
 358         bool changed = false;
 359
 360         device_lock_assert(&dev->dev);
 361         switch (new) {
 362         case pci_channel_io_perm_failure:
 363                 switch (dev->error_state) {
 364                 case pci_channel_io_frozen:
 365                 case pci_channel_io_normal:
 366                 case pci_channel_io_perm_failure:
 367                         changed = true;
 368                         break;
 369                 }
 370                 break;
 371         case pci_channel_io_frozen:
 372                 switch (dev->error_state) {
 373                 case pci_channel_io_frozen:
 374                 case pci_channel_io_normal:
 375                         changed = true;
 376                         break;
 377                 }
 378                 break;
 379         case pci_channel_io_normal:
 380                 switch (dev->error_state) {
 381                 case pci_channel_io_frozen:
 382                 case pci_channel_io_normal:
 383                         changed = true;
 384                         break;
 385                 }
 386                 break;
 387         }
 388         if (changed)
 389                 dev->error_state = new;
 390         return changed;
 391 }
 392
 393 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)
 394 {
 395         device_lock(&dev->dev);
 396         pci_dev_set_io_state(dev, pci_channel_io_perm_failure);
 397         device_unlock(&dev->dev);
 398
 399         return 0;
 400 }
 401
 402 static inline bool pci_dev_is_disconnected(const struct pci_dev *dev)
 403 {
 404         return dev->error_state == pci_channel_io_perm_failure;
 405 }
 406
 407 /* pci_dev priv_flags */
 408 #define PCI_DEV_ADDED 0
 409 #define PCI_DPC_RECOVERED 1
 410 #define PCI_DPC_RECOVERING 2
 411
 412 static inline void pci_dev_assign_added(struct pci_dev *dev, bool added)
 413 {
 414         assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added);
 415 }
 416
 417 static inline bool pci_dev_is_added(const struct pci_dev *dev)
 418 {
 419         return test_bit(PCI_DEV_ADDED, &dev->priv_flags);
 420 }
 421
 422 #ifdef CONFIG_PCIEAER
 423 #include <linux/aer.h>
 424
 425 #define AER_MAX_MULTI_ERR_DEVICES       5       /* Not likely to have more */
 426
 427 struct aer_err_info {
 428         struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES];
 429         int error_dev_num;
 430
 431         unsigned int id:16;
 432
 433         unsigned int severity:2;        /* 0:NONFATAL | 1:FATAL | 2:COR */
 434         unsigned int __pad1:5;
 435         unsigned int multi_error_valid:1;
 436
 437         unsigned int first_error:5;
 438         unsigned int __pad2:2;
 439         unsigned int tlp_header_valid:1;
 440
 441         unsigned int status;            /* COR/UNCOR Error Status */
 442         unsigned int mask;              /* COR/UNCOR Error Mask */
 443         struct aer_header_log_regs tlp; /* TLP Header */
 444 };
 445
 446 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info);
 447 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
 448 #endif  /* CONFIG_PCIEAER */
 449
 450 #ifdef CONFIG_PCIEPORTBUS
 451 /* Cached RCEC Endpoint Association */
 452 struct rcec_ea {
 453         u8              nextbusn;
 454         u8              lastbusn;
 455         u32             bitmap;
 456 };
 457 #endif
 458
 459 #ifdef CONFIG_PCIE_DPC
 460 void pci_save_dpc_state(struct pci_dev *dev);
 461 void pci_restore_dpc_state(struct pci_dev *dev);
 462 void pci_dpc_init(struct pci_dev *pdev);
 463 void dpc_process_error(struct pci_dev *pdev);
 464 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev);
 465 bool pci_dpc_recovered(struct pci_dev *pdev);
 466 #else
 467 static inline void pci_save_dpc_state(struct pci_dev *dev) {}
 468 static inline void pci_restore_dpc_state(struct pci_dev *dev) {}
 469 static inline void pci_dpc_init(struct pci_dev *pdev) {}
 470 static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; }
 471 #endif
 472
 473 #ifdef CONFIG_PCIEPORTBUS
 474 void pci_rcec_init(struct pci_dev *dev);
 475 void pci_rcec_exit(struct pci_dev *dev);
 476 void pcie_link_rcec(struct pci_dev *rcec);
 477 void pcie_walk_rcec(struct pci_dev *rcec,
 478                     int (*cb)(struct pci_dev *, void *),
 479                     void *userdata);
 480 #else
 481 static inline void pci_rcec_init(struct pci_dev *dev) {}
 482 static inline void pci_rcec_exit(struct pci_dev *dev) {}
 483 static inline void pcie_link_rcec(struct pci_dev *rcec) {}
 484 static inline void pcie_walk_rcec(struct pci_dev *rcec,
 485                                   int (*cb)(struct pci_dev *, void *),
 486                                   void *userdata) {}
 487 #endif
 488
 489 #ifdef CONFIG_PCI_ATS
 490 /* Address Translation Service */
 491 void pci_ats_init(struct pci_dev *dev);
 492 void pci_restore_ats_state(struct pci_dev *dev);
 493 #else
 494 static inline void pci_ats_init(struct pci_dev *d) { }
 495 static inline void pci_restore_ats_state(struct pci_dev *dev) { }
 496 #endif /* CONFIG_PCI_ATS */
 497
 498 #ifdef CONFIG_PCI_PRI
 499 void pci_pri_init(struct pci_dev *dev);
 500 void pci_restore_pri_state(struct pci_dev *pdev);
 501 #else
 502 static inline void pci_pri_init(struct pci_dev *dev) { }
 503 static inline void pci_restore_pri_state(struct pci_dev *pdev) { }
 504 #endif
 505
 506 #ifdef CONFIG_PCI_PASID
 507 void pci_pasid_init(struct pci_dev *dev);
 508 void pci_restore_pasid_state(struct pci_dev *pdev);
 509 #else
 510 static inline void pci_pasid_init(struct pci_dev *dev) { }
 511 static inline void pci_restore_pasid_state(struct pci_dev *pdev) { }
 512 #endif
 513
 514 #ifdef CONFIG_PCI_IOV
 515 int pci_iov_init(struct pci_dev *dev);
 516 void pci_iov_release(struct pci_dev *dev);
 517 void pci_iov_remove(struct pci_dev *dev);
 518 void pci_iov_update_resource(struct pci_dev *dev, int resno);
 519 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
 520 void pci_restore_iov_state(struct pci_dev *dev);
 521 int pci_iov_bus_range(struct pci_bus *bus);
 522 extern const struct attribute_group sriov_pf_dev_attr_group;
 523 extern const struct attribute_group sriov_vf_dev_attr_group;
 524 #else
 525 static inline int pci_iov_init(struct pci_dev *dev)
 526 {
 527         return -ENODEV;
 528 }
 529 static inline void pci_iov_release(struct pci_dev *dev)
 530
 531 {
 532 }
 533 static inline void pci_iov_remove(struct pci_dev *dev)
 534 {
 535 }
 536 static inline void pci_restore_iov_state(struct pci_dev *dev)
 537 {
 538 }
 539 static inline int pci_iov_bus_range(struct pci_bus *bus)
 540 {
 541         return 0;
 542 }
 543
 544 #endif /* CONFIG_PCI_IOV */
 545
 546 #ifdef CONFIG_PCIE_PTM
 547 void pci_save_ptm_state(struct pci_dev *dev);
 548 void pci_restore_ptm_state(struct pci_dev *dev);
 549 void pci_disable_ptm(struct pci_dev *dev);
 550 #else
 551 static inline void pci_save_ptm_state(struct pci_dev *dev) { }
 552 static inline void pci_restore_ptm_state(struct pci_dev *dev) { }
 553 static inline void pci_disable_ptm(struct pci_dev *dev) { }
 554 #endif
 555
 556 unsigned long pci_cardbus_resource_alignment(struct resource *);
 557
 558 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
 559                                                      struct resource *res)
 560 {
 561 #ifdef CONFIG_PCI_IOV
 562         int resno = res - dev->resource;
 563
 564         if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
 565                 return pci_sriov_resource_alignment(dev, resno);
 566 #endif
 567         if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
 568                 return pci_cardbus_resource_alignment(res);
 569         return resource_alignment(res);
 570 }
 571
 572 void pci_acs_init(struct pci_dev *dev);
 573 #ifdef CONFIG_PCI_QUIRKS
 574 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
 575 int pci_dev_specific_enable_acs(struct pci_dev *dev);
 576 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev);
 577 #else
 578 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
 579                                                u16 acs_flags)
 580 {
 581         return -ENOTTY;
 582 }
 583 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
 584 {
 585         return -ENOTTY;
 586 }
 587 static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
 588 {
 589         return -ENOTTY;
 590 }
 591 #endif
 592
 593 /* PCI error reporting and recovery */
 594 pci_ers_result_t pcie_do_recovery(struct pci_dev *dev,
 595                 pci_channel_state_t state,
 596                 pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev));
 597
 598 bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
 599 #ifdef CONFIG_PCIEASPM
 600 void pcie_aspm_init_link_state(struct pci_dev *pdev);
 601 void pcie_aspm_exit_link_state(struct pci_dev *pdev);
 602 void pcie_aspm_pm_state_change(struct pci_dev *pdev);
 603 void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
 604 #else
 605 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
 606 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
 607 static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { }
 608 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
 609 #endif
 610
 611 #ifdef CONFIG_PCIE_ECRC
 612 void pcie_set_ecrc_checking(struct pci_dev *dev);
 613 void pcie_ecrc_get_policy(char *str);
 614 #else
 615 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
 616 static inline void pcie_ecrc_get_policy(char *str) { }
 617 #endif
 618
 619 #ifdef CONFIG_PCIE_PTM
 620 void pci_ptm_init(struct pci_dev *dev);
 621 #else
 622 static inline void pci_ptm_init(struct pci_dev *dev) { }
 623 #endif
 624
 625 struct pci_dev_reset_methods {
 626         u16 vendor;
 627         u16 device;
 628         int (*reset)(struct pci_dev *dev, bool probe);
 629 };
 630
 631 struct pci_reset_fn_method {
 632         int (*reset_fn)(struct pci_dev *pdev, bool probe);
 633         char *name;
 634 };
 635
 636 #ifdef CONFIG_PCI_QUIRKS
 637 int pci_dev_specific_reset(struct pci_dev *dev, bool probe);
 638 #else
 639 static inline int pci_dev_specific_reset(struct pci_dev *dev, bool probe)
 640 {
 641         return -ENOTTY;
 642 }
 643 #endif
 644
 645 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
 646 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
 647                           struct resource *res);
 648 #else
 649 static inline int acpi_get_rc_resources(struct device *dev, const char *hid,
 650                                         u16 segment, struct resource *res)
 651 {
 652         return -ENODEV;
 653 }
 654 #endif
 655
 656 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
 657 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
 658 static inline u64 pci_rebar_size_to_bytes(int size)
 659 {
 660         return 1ULL << (size + 20);
 661 }
 662
 663 struct device_node;
 664
 665 #ifdef CONFIG_OF
 666 int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
 667 int of_get_pci_domain_nr(struct device_node *node);
 668 int of_pci_get_max_link_speed(struct device_node *node);
 669 void pci_set_of_node(struct pci_dev *dev);
 670 void pci_release_of_node(struct pci_dev *dev);
 671 void pci_set_bus_of_node(struct pci_bus *bus);
 672 void pci_release_bus_of_node(struct pci_bus *bus);
 673
 674 int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge);
 675
 676 #else
 677 static inline int
 678 of_pci_parse_bus_range(struct device_node *node, struct resource *res)
 679 {
 680         return -EINVAL;
 681 }
 682
 683 static inline int
 684 of_get_pci_domain_nr(struct device_node *node)
 685 {
 686         return -1;
 687 }
 688
 689 static inline int
 690 of_pci_get_max_link_speed(struct device_node *node)
 691 {
 692         return -EINVAL;
 693 }
 694
 695 static inline void pci_set_of_node(struct pci_dev *dev) { }
 696 static inline void pci_release_of_node(struct pci_dev *dev) { }
 697 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
 698 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
 699
 700 static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge)
 701 {
 702         return 0;
 703 }
 704
 705 #endif /* CONFIG_OF */
 706
 707 #ifdef CONFIG_PCIEAER
 708 void pci_no_aer(void);
 709 void pci_aer_init(struct pci_dev *dev);
 710 void pci_aer_exit(struct pci_dev *dev);
 711 extern const struct attribute_group aer_stats_attr_group;
 712 void pci_aer_clear_fatal_status(struct pci_dev *dev);
 713 int pci_aer_clear_status(struct pci_dev *dev);
 714 int pci_aer_raw_clear_status(struct pci_dev *dev);
 715 #else
 716 static inline void pci_no_aer(void) { }
 717 static inline void pci_aer_init(struct pci_dev *d) { }
 718 static inline void pci_aer_exit(struct pci_dev *d) { }
 719 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { }
 720 static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; }
 721 static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; }
 722 #endif
 723
 724 #ifdef CONFIG_ACPI
 725 int pci_acpi_program_hp_params(struct pci_dev *dev);
 726 extern const struct attribute_group pci_dev_acpi_attr_group;
 727 void pci_set_acpi_fwnode(struct pci_dev *dev);
 728 int pci_dev_acpi_reset(struct pci_dev *dev, bool probe);
 729 #else
 730 static inline int pci_dev_acpi_reset(struct pci_dev *dev, bool probe)
 731 {
 732         return -ENOTTY;
 733 }
 734
 735 static inline void pci_set_acpi_fwnode(struct pci_dev *dev) {}
 736 static inline int pci_acpi_program_hp_params(struct pci_dev *dev)
 737 {
 738         return -ENODEV;
 739 }
 740 #endif
 741
 742 #ifdef CONFIG_PCIEASPM
 743 extern const struct attribute_group aspm_ctrl_attr_group;
 744 #endif
 745
 746 extern const struct attribute_group pci_dev_reset_method_attr_group;
 747
 748 #endif /* DRIVERS_PCI_H */