2 * probe.c - PCI detection and setup code
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
12 #include <linux/pci-aspm.h>
13 #include <acpi/acpi_hest.h>
16 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
17 #define CARDBUS_RESERVE_BUSNR 3
19 /* Ugh. Need to stop exporting this to modules. */
20 LIST_HEAD(pci_root_buses
);
21 EXPORT_SYMBOL(pci_root_buses
);
24 static int find_anything(struct device
*dev
, void *data
)
30 * Some device drivers need know if pci is initiated.
31 * Basically, we think pci is not initiated when there
32 * is no device to be found on the pci_bus_type.
34 int no_pci_devices(void)
39 dev
= bus_find_device(&pci_bus_type
, NULL
, NULL
, find_anything
);
40 no_devices
= (dev
== NULL
);
44 EXPORT_SYMBOL(no_pci_devices
);
47 * PCI Bus Class Devices
49 static ssize_t
pci_bus_show_cpuaffinity(struct device
*dev
,
51 struct device_attribute
*attr
,
55 const struct cpumask
*cpumask
;
57 cpumask
= cpumask_of_pcibus(to_pci_bus(dev
));
59 cpulist_scnprintf(buf
, PAGE_SIZE
-2, cpumask
) :
60 cpumask_scnprintf(buf
, PAGE_SIZE
-2, cpumask
);
66 static ssize_t
inline pci_bus_show_cpumaskaffinity(struct device
*dev
,
67 struct device_attribute
*attr
,
70 return pci_bus_show_cpuaffinity(dev
, 0, attr
, buf
);
73 static ssize_t
inline pci_bus_show_cpulistaffinity(struct device
*dev
,
74 struct device_attribute
*attr
,
77 return pci_bus_show_cpuaffinity(dev
, 1, attr
, buf
);
80 DEVICE_ATTR(cpuaffinity
, S_IRUGO
, pci_bus_show_cpumaskaffinity
, NULL
);
81 DEVICE_ATTR(cpulistaffinity
, S_IRUGO
, pci_bus_show_cpulistaffinity
, NULL
);
86 static void release_pcibus_dev(struct device
*dev
)
88 struct pci_bus
*pci_bus
= to_pci_bus(dev
);
91 put_device(pci_bus
->bridge
);
95 static struct class pcibus_class
= {
97 .dev_release
= &release_pcibus_dev
,
100 static int __init
pcibus_class_init(void)
102 return class_register(&pcibus_class
);
104 postcore_initcall(pcibus_class_init
);
107 * Translate the low bits of the PCI base
108 * to the resource type
110 static inline unsigned int pci_calc_resource_flags(unsigned int flags
)
112 if (flags
& PCI_BASE_ADDRESS_SPACE_IO
)
113 return IORESOURCE_IO
;
115 if (flags
& PCI_BASE_ADDRESS_MEM_PREFETCH
)
116 return IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
118 return IORESOURCE_MEM
;
121 static u64
pci_size(u64 base
, u64 maxbase
, u64 mask
)
123 u64 size
= mask
& maxbase
; /* Find the significant bits */
127 /* Get the lowest of them to find the decode size, and
128 from that the extent. */
129 size
= (size
& ~(size
-1)) - 1;
131 /* base == maxbase can be valid only if the BAR has
132 already been programmed with all 1s. */
133 if (base
== maxbase
&& ((base
| size
) & mask
) != mask
)
139 static inline enum pci_bar_type
decode_bar(struct resource
*res
, u32 bar
)
141 if ((bar
& PCI_BASE_ADDRESS_SPACE
) == PCI_BASE_ADDRESS_SPACE_IO
) {
142 res
->flags
= bar
& ~PCI_BASE_ADDRESS_IO_MASK
;
146 res
->flags
= bar
& ~PCI_BASE_ADDRESS_MEM_MASK
;
148 if (res
->flags
& PCI_BASE_ADDRESS_MEM_TYPE_64
)
149 return pci_bar_mem64
;
150 return pci_bar_mem32
;
154 * pci_read_base - read a PCI BAR
155 * @dev: the PCI device
156 * @type: type of the BAR
157 * @res: resource buffer to be filled in
158 * @pos: BAR position in the config space
160 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
162 int __pci_read_base(struct pci_dev
*dev
, enum pci_bar_type type
,
163 struct resource
*res
, unsigned int pos
)
167 mask
= type
? PCI_ROM_ADDRESS_MASK
: ~0;
169 res
->name
= pci_name(dev
);
171 pci_read_config_dword(dev
, pos
, &l
);
172 pci_write_config_dword(dev
, pos
, l
| mask
);
173 pci_read_config_dword(dev
, pos
, &sz
);
174 pci_write_config_dword(dev
, pos
, l
);
177 * All bits set in sz means the device isn't working properly.
178 * If the BAR isn't implemented, all bits must be 0. If it's a
179 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
182 if (!sz
|| sz
== 0xffffffff)
186 * I don't know how l can have all bits set. Copied from old code.
187 * Maybe it fixes a bug on some ancient platform.
192 if (type
== pci_bar_unknown
) {
193 type
= decode_bar(res
, l
);
194 res
->flags
|= pci_calc_resource_flags(l
) | IORESOURCE_SIZEALIGN
;
195 if (type
== pci_bar_io
) {
196 l
&= PCI_BASE_ADDRESS_IO_MASK
;
197 mask
= PCI_BASE_ADDRESS_IO_MASK
& IO_SPACE_LIMIT
;
199 l
&= PCI_BASE_ADDRESS_MEM_MASK
;
200 mask
= (u32
)PCI_BASE_ADDRESS_MEM_MASK
;
203 res
->flags
|= (l
& IORESOURCE_ROM_ENABLE
);
204 l
&= PCI_ROM_ADDRESS_MASK
;
205 mask
= (u32
)PCI_ROM_ADDRESS_MASK
;
208 if (type
== pci_bar_mem64
) {
211 u64 mask64
= mask
| (u64
)~0 << 32;
213 pci_read_config_dword(dev
, pos
+ 4, &l
);
214 pci_write_config_dword(dev
, pos
+ 4, ~0);
215 pci_read_config_dword(dev
, pos
+ 4, &sz
);
216 pci_write_config_dword(dev
, pos
+ 4, l
);
218 l64
|= ((u64
)l
<< 32);
219 sz64
|= ((u64
)sz
<< 32);
221 sz64
= pci_size(l64
, sz64
, mask64
);
226 if ((sizeof(resource_size_t
) < 8) && (sz64
> 0x100000000ULL
)) {
227 dev_err(&dev
->dev
, "reg %x: can't handle 64-bit BAR\n",
232 res
->flags
|= IORESOURCE_MEM_64
;
233 if ((sizeof(resource_size_t
) < 8) && l
) {
234 /* Address above 32-bit boundary; disable the BAR */
235 pci_write_config_dword(dev
, pos
, 0);
236 pci_write_config_dword(dev
, pos
+ 4, 0);
241 res
->end
= l64
+ sz64
;
242 dev_printk(KERN_DEBUG
, &dev
->dev
, "reg %x: %pR\n",
246 sz
= pci_size(l
, sz
, mask
);
254 dev_printk(KERN_DEBUG
, &dev
->dev
, "reg %x: %pR\n", pos
, res
);
258 return (type
== pci_bar_mem64
) ? 1 : 0;
264 static void pci_read_bases(struct pci_dev
*dev
, unsigned int howmany
, int rom
)
266 unsigned int pos
, reg
;
268 for (pos
= 0; pos
< howmany
; pos
++) {
269 struct resource
*res
= &dev
->resource
[pos
];
270 reg
= PCI_BASE_ADDRESS_0
+ (pos
<< 2);
271 pos
+= __pci_read_base(dev
, pci_bar_unknown
, res
, reg
);
275 struct resource
*res
= &dev
->resource
[PCI_ROM_RESOURCE
];
276 dev
->rom_base_reg
= rom
;
277 res
->flags
= IORESOURCE_MEM
| IORESOURCE_PREFETCH
|
278 IORESOURCE_READONLY
| IORESOURCE_CACHEABLE
|
279 IORESOURCE_SIZEALIGN
;
280 __pci_read_base(dev
, pci_bar_mem32
, res
, rom
);
284 void __devinit
pci_read_bridge_bases(struct pci_bus
*child
)
286 struct pci_dev
*dev
= child
->self
;
287 u8 io_base_lo
, io_limit_lo
;
288 u16 mem_base_lo
, mem_limit_lo
;
289 unsigned long base
, limit
;
290 struct resource
*res
;
293 if (pci_is_root_bus(child
)) /* It's a host bus, nothing to read */
296 dev_info(&dev
->dev
, "PCI bridge to [bus %02x-%02x]%s\n",
297 child
->secondary
, child
->subordinate
,
298 dev
->transparent
? " (subtractive decode)": "");
300 if (dev
->transparent
) {
301 for(i
= 3; i
< PCI_BUS_NUM_RESOURCES
; i
++)
302 child
->resource
[i
] = child
->parent
->resource
[i
- 3];
305 res
= child
->resource
[0];
306 pci_read_config_byte(dev
, PCI_IO_BASE
, &io_base_lo
);
307 pci_read_config_byte(dev
, PCI_IO_LIMIT
, &io_limit_lo
);
308 base
= (io_base_lo
& PCI_IO_RANGE_MASK
) << 8;
309 limit
= (io_limit_lo
& PCI_IO_RANGE_MASK
) << 8;
311 if ((io_base_lo
& PCI_IO_RANGE_TYPE_MASK
) == PCI_IO_RANGE_TYPE_32
) {
312 u16 io_base_hi
, io_limit_hi
;
313 pci_read_config_word(dev
, PCI_IO_BASE_UPPER16
, &io_base_hi
);
314 pci_read_config_word(dev
, PCI_IO_LIMIT_UPPER16
, &io_limit_hi
);
315 base
|= (io_base_hi
<< 16);
316 limit
|= (io_limit_hi
<< 16);
320 res
->flags
= (io_base_lo
& PCI_IO_RANGE_TYPE_MASK
) | IORESOURCE_IO
;
324 res
->end
= limit
+ 0xfff;
325 dev_printk(KERN_DEBUG
, &dev
->dev
, " bridge window %pR\n", res
);
328 res
= child
->resource
[1];
329 pci_read_config_word(dev
, PCI_MEMORY_BASE
, &mem_base_lo
);
330 pci_read_config_word(dev
, PCI_MEMORY_LIMIT
, &mem_limit_lo
);
331 base
= (mem_base_lo
& PCI_MEMORY_RANGE_MASK
) << 16;
332 limit
= (mem_limit_lo
& PCI_MEMORY_RANGE_MASK
) << 16;
334 res
->flags
= (mem_base_lo
& PCI_MEMORY_RANGE_TYPE_MASK
) | IORESOURCE_MEM
;
336 res
->end
= limit
+ 0xfffff;
337 dev_printk(KERN_DEBUG
, &dev
->dev
, " bridge window %pR\n", res
);
340 res
= child
->resource
[2];
341 pci_read_config_word(dev
, PCI_PREF_MEMORY_BASE
, &mem_base_lo
);
342 pci_read_config_word(dev
, PCI_PREF_MEMORY_LIMIT
, &mem_limit_lo
);
343 base
= (mem_base_lo
& PCI_PREF_RANGE_MASK
) << 16;
344 limit
= (mem_limit_lo
& PCI_PREF_RANGE_MASK
) << 16;
346 if ((mem_base_lo
& PCI_PREF_RANGE_TYPE_MASK
) == PCI_PREF_RANGE_TYPE_64
) {
347 u32 mem_base_hi
, mem_limit_hi
;
348 pci_read_config_dword(dev
, PCI_PREF_BASE_UPPER32
, &mem_base_hi
);
349 pci_read_config_dword(dev
, PCI_PREF_LIMIT_UPPER32
, &mem_limit_hi
);
352 * Some bridges set the base > limit by default, and some
353 * (broken) BIOSes do not initialize them. If we find
354 * this, just assume they are not being used.
356 if (mem_base_hi
<= mem_limit_hi
) {
357 #if BITS_PER_LONG == 64
358 base
|= ((long) mem_base_hi
) << 32;
359 limit
|= ((long) mem_limit_hi
) << 32;
361 if (mem_base_hi
|| mem_limit_hi
) {
362 dev_err(&dev
->dev
, "can't handle 64-bit "
363 "address space for bridge\n");
370 res
->flags
= (mem_base_lo
& PCI_PREF_RANGE_TYPE_MASK
) |
371 IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
372 if (res
->flags
& PCI_PREF_RANGE_TYPE_64
)
373 res
->flags
|= IORESOURCE_MEM_64
;
375 res
->end
= limit
+ 0xfffff;
376 dev_printk(KERN_DEBUG
, &dev
->dev
, " bridge window %pR\n", res
);
380 static struct pci_bus
* pci_alloc_bus(void)
384 b
= kzalloc(sizeof(*b
), GFP_KERNEL
);
386 INIT_LIST_HEAD(&b
->node
);
387 INIT_LIST_HEAD(&b
->children
);
388 INIT_LIST_HEAD(&b
->devices
);
389 INIT_LIST_HEAD(&b
->slots
);
390 b
->max_bus_speed
= PCI_SPEED_UNKNOWN
;
391 b
->cur_bus_speed
= PCI_SPEED_UNKNOWN
;
396 static unsigned char pcie_link_speed
[] = {
397 PCI_SPEED_UNKNOWN
, /* 0 */
398 PCIE_SPEED_2_5GT
, /* 1 */
399 PCIE_SPEED_5_0GT
, /* 2 */
400 PCI_SPEED_UNKNOWN
, /* 3 */
401 PCI_SPEED_UNKNOWN
, /* 4 */
402 PCI_SPEED_UNKNOWN
, /* 5 */
403 PCI_SPEED_UNKNOWN
, /* 6 */
404 PCI_SPEED_UNKNOWN
, /* 7 */
405 PCI_SPEED_UNKNOWN
, /* 8 */
406 PCI_SPEED_UNKNOWN
, /* 9 */
407 PCI_SPEED_UNKNOWN
, /* A */
408 PCI_SPEED_UNKNOWN
, /* B */
409 PCI_SPEED_UNKNOWN
, /* C */
410 PCI_SPEED_UNKNOWN
, /* D */
411 PCI_SPEED_UNKNOWN
, /* E */
412 PCI_SPEED_UNKNOWN
/* F */
415 void pcie_update_link_speed(struct pci_bus
*bus
, u16 linksta
)
417 bus
->cur_bus_speed
= pcie_link_speed
[linksta
& 0xf];
419 EXPORT_SYMBOL_GPL(pcie_update_link_speed
);
421 static struct pci_bus
*pci_alloc_child_bus(struct pci_bus
*parent
,
422 struct pci_dev
*bridge
, int busnr
)
424 struct pci_bus
*child
;
428 * Allocate a new bus, and inherit stuff from the parent..
430 child
= pci_alloc_bus();
434 child
->parent
= parent
;
435 child
->ops
= parent
->ops
;
436 child
->sysdata
= parent
->sysdata
;
437 child
->bus_flags
= parent
->bus_flags
;
439 /* initialize some portions of the bus device, but don't register it
440 * now as the parent is not properly set up yet. This device will get
441 * registered later in pci_bus_add_devices()
443 child
->dev
.class = &pcibus_class
;
444 dev_set_name(&child
->dev
, "%04x:%02x", pci_domain_nr(child
), busnr
);
447 * Set up the primary, secondary and subordinate
450 child
->number
= child
->secondary
= busnr
;
451 child
->primary
= parent
->secondary
;
452 child
->subordinate
= 0xff;
457 child
->self
= bridge
;
458 child
->bridge
= get_device(&bridge
->dev
);
460 /* Set up default resource pointers and names.. */
461 for (i
= 0; i
< PCI_BRIDGE_RESOURCE_NUM
; i
++) {
462 child
->resource
[i
] = &bridge
->resource
[PCI_BRIDGE_RESOURCES
+i
];
463 child
->resource
[i
]->name
= child
->name
;
465 bridge
->subordinate
= child
;
470 struct pci_bus
*__ref
pci_add_new_bus(struct pci_bus
*parent
, struct pci_dev
*dev
, int busnr
)
472 struct pci_bus
*child
;
474 child
= pci_alloc_child_bus(parent
, dev
, busnr
);
476 down_write(&pci_bus_sem
);
477 list_add_tail(&child
->node
, &parent
->children
);
478 up_write(&pci_bus_sem
);
483 static void pci_fixup_parent_subordinate_busnr(struct pci_bus
*child
, int max
)
485 struct pci_bus
*parent
= child
->parent
;
487 /* Attempts to fix that up are really dangerous unless
488 we're going to re-assign all bus numbers. */
489 if (!pcibios_assign_all_busses())
492 while (parent
->parent
&& parent
->subordinate
< max
) {
493 parent
->subordinate
= max
;
494 pci_write_config_byte(parent
->self
, PCI_SUBORDINATE_BUS
, max
);
495 parent
= parent
->parent
;
500 * If it's a bridge, configure it and scan the bus behind it.
501 * For CardBus bridges, we don't scan behind as the devices will
502 * be handled by the bridge driver itself.
504 * We need to process bridges in two passes -- first we scan those
505 * already configured by the BIOS and after we are done with all of
506 * them, we proceed to assigning numbers to the remaining buses in
507 * order to avoid overlaps between old and new bus numbers.
509 int __devinit
pci_scan_bridge(struct pci_bus
*bus
, struct pci_dev
*dev
, int max
, int pass
)
511 struct pci_bus
*child
;
512 int is_cardbus
= (dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
);
517 pci_read_config_dword(dev
, PCI_PRIMARY_BUS
, &buses
);
519 dev_dbg(&dev
->dev
, "scanning behind bridge, config %06x, pass %d\n",
520 buses
& 0xffffff, pass
);
522 /* Check if setup is sensible at all */
524 ((buses
& 0xff) != bus
->number
|| ((buses
>> 8) & 0xff) <= bus
->number
)) {
525 dev_dbg(&dev
->dev
, "bus configuration invalid, reconfiguring\n");
529 /* Disable MasterAbortMode during probing to avoid reporting
530 of bus errors (in some architectures) */
531 pci_read_config_word(dev
, PCI_BRIDGE_CONTROL
, &bctl
);
532 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
,
533 bctl
& ~PCI_BRIDGE_CTL_MASTER_ABORT
);
535 if ((buses
& 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus
&& !broken
) {
536 unsigned int cmax
, busnr
;
538 * Bus already configured by firmware, process it in the first
539 * pass and just note the configuration.
543 busnr
= (buses
>> 8) & 0xFF;
546 * If we already got to this bus through a different bridge,
547 * don't re-add it. This can happen with the i450NX chipset.
549 * However, we continue to descend down the hierarchy and
550 * scan remaining child buses.
552 child
= pci_find_bus(pci_domain_nr(bus
), busnr
);
554 child
= pci_add_new_bus(bus
, dev
, busnr
);
557 child
->primary
= buses
& 0xFF;
558 child
->subordinate
= (buses
>> 16) & 0xFF;
559 child
->bridge_ctl
= bctl
;
562 cmax
= pci_scan_child_bus(child
);
565 if (child
->subordinate
> max
)
566 max
= child
->subordinate
;
569 * We need to assign a number to this bus which we always
570 * do in the second pass.
573 if (pcibios_assign_all_busses() || broken
)
574 /* Temporarily disable forwarding of the
575 configuration cycles on all bridges in
576 this bus segment to avoid possible
577 conflicts in the second pass between two
578 bridges programmed with overlapping
580 pci_write_config_dword(dev
, PCI_PRIMARY_BUS
,
586 pci_write_config_word(dev
, PCI_STATUS
, 0xffff);
588 /* Prevent assigning a bus number that already exists.
589 * This can happen when a bridge is hot-plugged */
590 if (pci_find_bus(pci_domain_nr(bus
), max
+1))
592 child
= pci_add_new_bus(bus
, dev
, ++max
);
593 buses
= (buses
& 0xff000000)
594 | ((unsigned int)(child
->primary
) << 0)
595 | ((unsigned int)(child
->secondary
) << 8)
596 | ((unsigned int)(child
->subordinate
) << 16);
599 * yenta.c forces a secondary latency timer of 176.
600 * Copy that behaviour here.
603 buses
&= ~0xff000000;
604 buses
|= CARDBUS_LATENCY_TIMER
<< 24;
608 * We need to blast all three values with a single write.
610 pci_write_config_dword(dev
, PCI_PRIMARY_BUS
, buses
);
613 child
->bridge_ctl
= bctl
;
615 * Adjust subordinate busnr in parent buses.
616 * We do this before scanning for children because
617 * some devices may not be detected if the bios
620 pci_fixup_parent_subordinate_busnr(child
, max
);
621 /* Now we can scan all subordinate buses... */
622 max
= pci_scan_child_bus(child
);
624 * now fix it up again since we have found
625 * the real value of max.
627 pci_fixup_parent_subordinate_busnr(child
, max
);
630 * For CardBus bridges, we leave 4 bus numbers
631 * as cards with a PCI-to-PCI bridge can be
634 for (i
=0; i
<CARDBUS_RESERVE_BUSNR
; i
++) {
635 struct pci_bus
*parent
= bus
;
636 if (pci_find_bus(pci_domain_nr(bus
),
639 while (parent
->parent
) {
640 if ((!pcibios_assign_all_busses()) &&
641 (parent
->subordinate
> max
) &&
642 (parent
->subordinate
<= max
+i
)) {
645 parent
= parent
->parent
;
649 * Often, there are two cardbus bridges
650 * -- try to leave one valid bus number
658 pci_fixup_parent_subordinate_busnr(child
, max
);
661 * Set the subordinate bus number to its real value.
663 child
->subordinate
= max
;
664 pci_write_config_byte(dev
, PCI_SUBORDINATE_BUS
, max
);
668 (is_cardbus
? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
669 pci_domain_nr(bus
), child
->number
);
671 /* Has only triggered on CardBus, fixup is in yenta_socket */
672 while (bus
->parent
) {
673 if ((child
->subordinate
> bus
->subordinate
) ||
674 (child
->number
> bus
->subordinate
) ||
675 (child
->number
< bus
->number
) ||
676 (child
->subordinate
< bus
->number
)) {
677 dev_info(&child
->dev
, "[bus %02x-%02x] %s "
678 "hidden behind%s bridge %s [bus %02x-%02x]\n",
679 child
->number
, child
->subordinate
,
680 (bus
->number
> child
->subordinate
&&
681 bus
->subordinate
< child
->number
) ?
682 "wholly" : "partially",
683 bus
->self
->transparent
? " transparent" : "",
685 bus
->number
, bus
->subordinate
);
691 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, bctl
);
697 * Read interrupt line and base address registers.
698 * The architecture-dependent code can tweak these, of course.
700 static void pci_read_irq(struct pci_dev
*dev
)
704 pci_read_config_byte(dev
, PCI_INTERRUPT_PIN
, &irq
);
707 pci_read_config_byte(dev
, PCI_INTERRUPT_LINE
, &irq
);
711 void set_pcie_port_type(struct pci_dev
*pdev
)
716 pos
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
720 pdev
->pcie_cap
= pos
;
721 pci_read_config_word(pdev
, pos
+ PCI_EXP_FLAGS
, ®16
);
722 pdev
->pcie_type
= (reg16
& PCI_EXP_FLAGS_TYPE
) >> 4;
725 void set_pcie_hotplug_bridge(struct pci_dev
*pdev
)
731 pos
= pci_pcie_cap(pdev
);
734 pci_read_config_word(pdev
, pos
+ PCI_EXP_FLAGS
, ®16
);
735 if (!(reg16
& PCI_EXP_FLAGS_SLOT
))
737 pci_read_config_dword(pdev
, pos
+ PCI_EXP_SLTCAP
, ®32
);
738 if (reg32
& PCI_EXP_SLTCAP_HPC
)
739 pdev
->is_hotplug_bridge
= 1;
742 static void set_pci_aer_firmware_first(struct pci_dev
*pdev
)
744 if (acpi_hest_firmware_first_pci(pdev
))
745 pdev
->aer_firmware_first
= 1;
748 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
751 * pci_setup_device - fill in class and map information of a device
752 * @dev: the device structure to fill
754 * Initialize the device structure with information about the device's
755 * vendor,class,memory and IO-space addresses,IRQ lines etc.
756 * Called at initialisation of the PCI subsystem and by CardBus services.
757 * Returns 0 on success and negative if unknown type of device (not normal,
758 * bridge or CardBus).
760 int pci_setup_device(struct pci_dev
*dev
)
764 struct pci_slot
*slot
;
767 if (pci_read_config_byte(dev
, PCI_HEADER_TYPE
, &hdr_type
))
770 dev
->sysdata
= dev
->bus
->sysdata
;
771 dev
->dev
.parent
= dev
->bus
->bridge
;
772 dev
->dev
.bus
= &pci_bus_type
;
773 dev
->hdr_type
= hdr_type
& 0x7f;
774 dev
->multifunction
= !!(hdr_type
& 0x80);
775 dev
->error_state
= pci_channel_io_normal
;
776 set_pcie_port_type(dev
);
777 set_pci_aer_firmware_first(dev
);
779 list_for_each_entry(slot
, &dev
->bus
->slots
, list
)
780 if (PCI_SLOT(dev
->devfn
) == slot
->number
)
783 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
784 set this higher, assuming the system even supports it. */
785 dev
->dma_mask
= 0xffffffff;
787 dev_set_name(&dev
->dev
, "%04x:%02x:%02x.%d", pci_domain_nr(dev
->bus
),
788 dev
->bus
->number
, PCI_SLOT(dev
->devfn
),
789 PCI_FUNC(dev
->devfn
));
791 pci_read_config_dword(dev
, PCI_CLASS_REVISION
, &class);
792 dev
->revision
= class & 0xff;
793 class >>= 8; /* upper 3 bytes */
797 dev_dbg(&dev
->dev
, "found [%04x:%04x] class %06x header type %02x\n",
798 dev
->vendor
, dev
->device
, class, dev
->hdr_type
);
800 /* need to have dev->class ready */
801 dev
->cfg_size
= pci_cfg_space_size(dev
);
803 /* "Unknown power state" */
804 dev
->current_state
= PCI_UNKNOWN
;
806 /* Early fixups, before probing the BARs */
807 pci_fixup_device(pci_fixup_early
, dev
);
808 /* device class may be changed after fixup */
809 class = dev
->class >> 8;
811 switch (dev
->hdr_type
) { /* header type */
812 case PCI_HEADER_TYPE_NORMAL
: /* standard header */
813 if (class == PCI_CLASS_BRIDGE_PCI
)
816 pci_read_bases(dev
, 6, PCI_ROM_ADDRESS
);
817 pci_read_config_word(dev
, PCI_SUBSYSTEM_VENDOR_ID
, &dev
->subsystem_vendor
);
818 pci_read_config_word(dev
, PCI_SUBSYSTEM_ID
, &dev
->subsystem_device
);
821 * Do the ugly legacy mode stuff here rather than broken chip
822 * quirk code. Legacy mode ATA controllers have fixed
823 * addresses. These are not always echoed in BAR0-3, and
824 * BAR0-3 in a few cases contain junk!
826 if (class == PCI_CLASS_STORAGE_IDE
) {
828 pci_read_config_byte(dev
, PCI_CLASS_PROG
, &progif
);
829 if ((progif
& 1) == 0) {
830 dev
->resource
[0].start
= 0x1F0;
831 dev
->resource
[0].end
= 0x1F7;
832 dev
->resource
[0].flags
= LEGACY_IO_RESOURCE
;
833 dev
->resource
[1].start
= 0x3F6;
834 dev
->resource
[1].end
= 0x3F6;
835 dev
->resource
[1].flags
= LEGACY_IO_RESOURCE
;
837 if ((progif
& 4) == 0) {
838 dev
->resource
[2].start
= 0x170;
839 dev
->resource
[2].end
= 0x177;
840 dev
->resource
[2].flags
= LEGACY_IO_RESOURCE
;
841 dev
->resource
[3].start
= 0x376;
842 dev
->resource
[3].end
= 0x376;
843 dev
->resource
[3].flags
= LEGACY_IO_RESOURCE
;
848 case PCI_HEADER_TYPE_BRIDGE
: /* bridge header */
849 if (class != PCI_CLASS_BRIDGE_PCI
)
851 /* The PCI-to-PCI bridge spec requires that subtractive
852 decoding (i.e. transparent) bridge must have programming
853 interface code of 0x01. */
855 dev
->transparent
= ((dev
->class & 0xff) == 1);
856 pci_read_bases(dev
, 2, PCI_ROM_ADDRESS1
);
857 set_pcie_hotplug_bridge(dev
);
858 pos
= pci_find_capability(dev
, PCI_CAP_ID_SSVID
);
860 pci_read_config_word(dev
, pos
+ PCI_SSVID_VENDOR_ID
, &dev
->subsystem_vendor
);
861 pci_read_config_word(dev
, pos
+ PCI_SSVID_DEVICE_ID
, &dev
->subsystem_device
);
865 case PCI_HEADER_TYPE_CARDBUS
: /* CardBus bridge header */
866 if (class != PCI_CLASS_BRIDGE_CARDBUS
)
869 pci_read_bases(dev
, 1, 0);
870 pci_read_config_word(dev
, PCI_CB_SUBSYSTEM_VENDOR_ID
, &dev
->subsystem_vendor
);
871 pci_read_config_word(dev
, PCI_CB_SUBSYSTEM_ID
, &dev
->subsystem_device
);
874 default: /* unknown header */
875 dev_err(&dev
->dev
, "unknown header type %02x, "
876 "ignoring device\n", dev
->hdr_type
);
880 dev_err(&dev
->dev
, "ignoring class %02x (doesn't match header "
881 "type %02x)\n", class, dev
->hdr_type
);
882 dev
->class = PCI_CLASS_NOT_DEFINED
;
885 /* We found a fine healthy device, go go go... */
889 static void pci_release_capabilities(struct pci_dev
*dev
)
891 pci_vpd_release(dev
);
892 pci_iov_release(dev
);
896 * pci_release_dev - free a pci device structure when all users of it are finished.
897 * @dev: device that's been disconnected
899 * Will be called only by the device core when all users of this pci device are
902 static void pci_release_dev(struct device
*dev
)
904 struct pci_dev
*pci_dev
;
906 pci_dev
= to_pci_dev(dev
);
907 pci_release_capabilities(pci_dev
);
912 * pci_cfg_space_size - get the configuration space size of the PCI device.
915 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
916 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
917 * access it. Maybe we don't have a way to generate extended config space
918 * accesses, or the device is behind a reverse Express bridge. So we try
919 * reading the dword at 0x100 which must either be 0 or a valid extended
922 int pci_cfg_space_size_ext(struct pci_dev
*dev
)
925 int pos
= PCI_CFG_SPACE_SIZE
;
927 if (pci_read_config_dword(dev
, pos
, &status
) != PCIBIOS_SUCCESSFUL
)
929 if (status
== 0xffffffff)
932 return PCI_CFG_SPACE_EXP_SIZE
;
935 return PCI_CFG_SPACE_SIZE
;
938 int pci_cfg_space_size(struct pci_dev
*dev
)
944 class = dev
->class >> 8;
945 if (class == PCI_CLASS_BRIDGE_HOST
)
946 return pci_cfg_space_size_ext(dev
);
948 pos
= pci_pcie_cap(dev
);
950 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
954 pci_read_config_dword(dev
, pos
+ PCI_X_STATUS
, &status
);
955 if (!(status
& (PCI_X_STATUS_266MHZ
| PCI_X_STATUS_533MHZ
)))
959 return pci_cfg_space_size_ext(dev
);
962 return PCI_CFG_SPACE_SIZE
;
965 static void pci_release_bus_bridge_dev(struct device
*dev
)
970 struct pci_dev
*alloc_pci_dev(void)
974 dev
= kzalloc(sizeof(struct pci_dev
), GFP_KERNEL
);
978 INIT_LIST_HEAD(&dev
->bus_list
);
982 EXPORT_SYMBOL(alloc_pci_dev
);
985 * Read the config data for a PCI device, sanity-check it
986 * and fill in the dev structure...
988 static struct pci_dev
*pci_scan_device(struct pci_bus
*bus
, int devfn
)
994 if (pci_bus_read_config_dword(bus
, devfn
, PCI_VENDOR_ID
, &l
))
997 /* some broken boards return 0 or ~0 if a slot is empty: */
998 if (l
== 0xffffffff || l
== 0x00000000 ||
999 l
== 0x0000ffff || l
== 0xffff0000)
1002 /* Configuration request Retry Status */
1003 while (l
== 0xffff0001) {
1006 if (pci_bus_read_config_dword(bus
, devfn
, PCI_VENDOR_ID
, &l
))
1008 /* Card hasn't responded in 60 seconds? Must be stuck. */
1009 if (delay
> 60 * 1000) {
1010 printk(KERN_WARNING
"pci %04x:%02x:%02x.%d: not "
1011 "responding\n", pci_domain_nr(bus
),
1012 bus
->number
, PCI_SLOT(devfn
),
1018 dev
= alloc_pci_dev();
1024 dev
->vendor
= l
& 0xffff;
1025 dev
->device
= (l
>> 16) & 0xffff;
1027 if (pci_setup_device(dev
)) {
1035 static void pci_init_capabilities(struct pci_dev
*dev
)
1037 /* MSI/MSI-X list */
1038 pci_msi_init_pci_dev(dev
);
1040 /* Buffers for saving PCIe and PCI-X capabilities */
1041 pci_allocate_cap_save_buffers(dev
);
1043 /* Power Management */
1045 platform_pci_wakeup_init(dev
);
1047 /* Vital Product Data */
1048 pci_vpd_pci22_init(dev
);
1050 /* Alternative Routing-ID Forwarding */
1051 pci_enable_ari(dev
);
1053 /* Single Root I/O Virtualization */
1056 /* Enable ACS P2P upstream forwarding */
1057 pci_enable_acs(dev
);
1060 void pci_device_add(struct pci_dev
*dev
, struct pci_bus
*bus
)
1062 device_initialize(&dev
->dev
);
1063 dev
->dev
.release
= pci_release_dev
;
1066 dev
->dev
.dma_mask
= &dev
->dma_mask
;
1067 dev
->dev
.dma_parms
= &dev
->dma_parms
;
1068 dev
->dev
.coherent_dma_mask
= 0xffffffffull
;
1070 pci_set_dma_max_seg_size(dev
, 65536);
1071 pci_set_dma_seg_boundary(dev
, 0xffffffff);
1073 /* Fix up broken headers */
1074 pci_fixup_device(pci_fixup_header
, dev
);
1076 /* Clear the state_saved flag. */
1077 dev
->state_saved
= false;
1079 /* Initialize various capabilities */
1080 pci_init_capabilities(dev
);
1083 * Add the device to our list of discovered devices
1084 * and the bus list for fixup functions, etc.
1086 down_write(&pci_bus_sem
);
1087 list_add_tail(&dev
->bus_list
, &bus
->devices
);
1088 up_write(&pci_bus_sem
);
1091 struct pci_dev
*__ref
pci_scan_single_device(struct pci_bus
*bus
, int devfn
)
1093 struct pci_dev
*dev
;
1095 dev
= pci_get_slot(bus
, devfn
);
1101 dev
= pci_scan_device(bus
, devfn
);
1105 pci_device_add(dev
, bus
);
1109 EXPORT_SYMBOL(pci_scan_single_device
);
1111 static unsigned next_ari_fn(struct pci_dev
*dev
, unsigned fn
)
1114 unsigned pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ARI
);
1117 pci_read_config_word(dev
, pos
+ 4, &cap
);
1121 static unsigned next_trad_fn(struct pci_dev
*dev
, unsigned fn
)
1123 return (fn
+ 1) % 8;
1126 static unsigned no_next_fn(struct pci_dev
*dev
, unsigned fn
)
1131 static int only_one_child(struct pci_bus
*bus
)
1133 struct pci_dev
*parent
= bus
->self
;
1134 if (!parent
|| !pci_is_pcie(parent
))
1136 if (parent
->pcie_type
== PCI_EXP_TYPE_ROOT_PORT
||
1137 parent
->pcie_type
== PCI_EXP_TYPE_DOWNSTREAM
)
1143 * pci_scan_slot - scan a PCI slot on a bus for devices.
1144 * @bus: PCI bus to scan
1145 * @devfn: slot number to scan (must have zero function.)
1147 * Scan a PCI slot on the specified PCI bus for devices, adding
1148 * discovered devices to the @bus->devices list. New devices
1149 * will not have is_added set.
1151 * Returns the number of new devices found.
1153 int pci_scan_slot(struct pci_bus
*bus
, int devfn
)
1155 unsigned fn
, nr
= 0;
1156 struct pci_dev
*dev
;
1157 unsigned (*next_fn
)(struct pci_dev
*, unsigned) = no_next_fn
;
1159 if (only_one_child(bus
) && (devfn
> 0))
1160 return 0; /* Already scanned the entire slot */
1162 dev
= pci_scan_single_device(bus
, devfn
);
1163 if (dev
&& !dev
->is_added
) /* new device? */
1166 if (pci_ari_enabled(bus
))
1167 next_fn
= next_ari_fn
;
1168 else if (dev
&& dev
->multifunction
)
1169 next_fn
= next_trad_fn
;
1171 for (fn
= next_fn(dev
, 0); fn
> 0; fn
= next_fn(dev
, fn
)) {
1172 dev
= pci_scan_single_device(bus
, devfn
+ fn
);
1176 dev
->multifunction
= 1;
1180 /* only one slot has pcie device */
1181 if (bus
->self
&& nr
)
1182 pcie_aspm_init_link_state(bus
->self
);
1187 unsigned int __devinit
pci_scan_child_bus(struct pci_bus
*bus
)
1189 unsigned int devfn
, pass
, max
= bus
->secondary
;
1190 struct pci_dev
*dev
;
1192 dev_dbg(&bus
->dev
, "scanning bus\n");
1194 /* Go find them, Rover! */
1195 for (devfn
= 0; devfn
< 0x100; devfn
+= 8)
1196 pci_scan_slot(bus
, devfn
);
1198 /* Reserve buses for SR-IOV capability. */
1199 max
+= pci_iov_bus_range(bus
);
1202 * After performing arch-dependent fixup of the bus, look behind
1203 * all PCI-to-PCI bridges on this bus.
1205 if (!bus
->is_added
) {
1206 dev_dbg(&bus
->dev
, "fixups for bus\n");
1207 pcibios_fixup_bus(bus
);
1208 if (pci_is_root_bus(bus
))
1212 for (pass
=0; pass
< 2; pass
++)
1213 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1214 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
||
1215 dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
)
1216 max
= pci_scan_bridge(bus
, dev
, max
, pass
);
1220 * We've scanned the bus and so we know all about what's on
1221 * the other side of any bridges that may be on this bus plus
1224 * Return how far we've got finding sub-buses.
1226 dev_dbg(&bus
->dev
, "bus scan returning with max=%02x\n", max
);
1230 struct pci_bus
* pci_create_bus(struct device
*parent
,
1231 int bus
, struct pci_ops
*ops
, void *sysdata
)
1234 struct pci_bus
*b
, *b2
;
1237 b
= pci_alloc_bus();
1241 dev
= kzalloc(sizeof(*dev
), GFP_KERNEL
);
1247 b
->sysdata
= sysdata
;
1250 b2
= pci_find_bus(pci_domain_nr(b
), bus
);
1252 /* If we already got to this bus through a different bridge, ignore it */
1253 dev_dbg(&b2
->dev
, "bus already known\n");
1257 down_write(&pci_bus_sem
);
1258 list_add_tail(&b
->node
, &pci_root_buses
);
1259 up_write(&pci_bus_sem
);
1261 dev
->parent
= parent
;
1262 dev
->release
= pci_release_bus_bridge_dev
;
1263 dev_set_name(dev
, "pci%04x:%02x", pci_domain_nr(b
), bus
);
1264 error
= device_register(dev
);
1267 b
->bridge
= get_device(dev
);
1270 set_dev_node(b
->bridge
, pcibus_to_node(b
));
1272 b
->dev
.class = &pcibus_class
;
1273 b
->dev
.parent
= b
->bridge
;
1274 dev_set_name(&b
->dev
, "%04x:%02x", pci_domain_nr(b
), bus
);
1275 error
= device_register(&b
->dev
);
1277 goto class_dev_reg_err
;
1278 error
= device_create_file(&b
->dev
, &dev_attr_cpuaffinity
);
1280 goto dev_create_file_err
;
1282 /* Create legacy_io and legacy_mem files for this bus */
1283 pci_create_legacy_files(b
);
1285 b
->number
= b
->secondary
= bus
;
1286 b
->resource
[0] = &ioport_resource
;
1287 b
->resource
[1] = &iomem_resource
;
1291 dev_create_file_err
:
1292 device_unregister(&b
->dev
);
1294 device_unregister(dev
);
1296 down_write(&pci_bus_sem
);
1298 up_write(&pci_bus_sem
);
1305 struct pci_bus
* __devinit
pci_scan_bus_parented(struct device
*parent
,
1306 int bus
, struct pci_ops
*ops
, void *sysdata
)
1310 b
= pci_create_bus(parent
, bus
, ops
, sysdata
);
1312 b
->subordinate
= pci_scan_child_bus(b
);
1315 EXPORT_SYMBOL(pci_scan_bus_parented
);
1317 #ifdef CONFIG_HOTPLUG
1319 * pci_rescan_bus - scan a PCI bus for devices.
1320 * @bus: PCI bus to scan
1322 * Scan a PCI bus and child buses for new devices, adds them,
1325 * Returns the max number of subordinate bus discovered.
1327 unsigned int __ref
pci_rescan_bus(struct pci_bus
*bus
)
1330 struct pci_dev
*dev
;
1332 max
= pci_scan_child_bus(bus
);
1334 down_read(&pci_bus_sem
);
1335 list_for_each_entry(dev
, &bus
->devices
, bus_list
)
1336 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
||
1337 dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
)
1338 if (dev
->subordinate
)
1339 pci_bus_size_bridges(dev
->subordinate
);
1340 up_read(&pci_bus_sem
);
1342 pci_bus_assign_resources(bus
);
1343 pci_enable_bridges(bus
);
1344 pci_bus_add_devices(bus
);
1348 EXPORT_SYMBOL_GPL(pci_rescan_bus
);
1350 EXPORT_SYMBOL(pci_add_new_bus
);
1351 EXPORT_SYMBOL(pci_scan_slot
);
1352 EXPORT_SYMBOL(pci_scan_bridge
);
1353 EXPORT_SYMBOL_GPL(pci_scan_child_bus
);
1356 static int __init
pci_sort_bf_cmp(const struct device
*d_a
, const struct device
*d_b
)
1358 const struct pci_dev
*a
= to_pci_dev(d_a
);
1359 const struct pci_dev
*b
= to_pci_dev(d_b
);
1361 if (pci_domain_nr(a
->bus
) < pci_domain_nr(b
->bus
)) return -1;
1362 else if (pci_domain_nr(a
->bus
) > pci_domain_nr(b
->bus
)) return 1;
1364 if (a
->bus
->number
< b
->bus
->number
) return -1;
1365 else if (a
->bus
->number
> b
->bus
->number
) return 1;
1367 if (a
->devfn
< b
->devfn
) return -1;
1368 else if (a
->devfn
> b
->devfn
) return 1;
1373 void __init
pci_sort_breadthfirst(void)
1375 bus_sort_breadthfirst(&pci_bus_type
, &pci_sort_bf_cmp
);