1 // SPDX-License-Identifier: GPL-2.0
3 * PCI detection and setup code
6 #include <linux/kernel.h>
7 #include <linux/delay.h>
8 #include <linux/init.h>
10 #include <linux/msi.h>
11 #include <linux/of_device.h>
12 #include <linux/of_pci.h>
13 #include <linux/pci_hotplug.h>
14 #include <linux/slab.h>
15 #include <linux/module.h>
16 #include <linux/cpumask.h>
17 #include <linux/aer.h>
18 #include <linux/acpi.h>
19 #include <linux/hypervisor.h>
20 #include <linux/irqdomain.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/bitfield.h>
23 #include <linux/list_sort.h>
26 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
27 #define CARDBUS_RESERVE_BUSNR 3
29 static struct resource busn_resource
= {
33 .flags
= IORESOURCE_BUS
,
36 /* Ugh. Need to stop exporting this to modules. */
37 LIST_HEAD(pci_root_buses
);
38 EXPORT_SYMBOL(pci_root_buses
);
40 static LIST_HEAD(pci_domain_busn_res_list
);
42 struct pci_domain_busn_res
{
43 struct list_head list
;
48 static struct resource
*get_pci_domain_busn_res(int domain_nr
)
50 struct pci_domain_busn_res
*r
;
52 list_for_each_entry(r
, &pci_domain_busn_res_list
, list
)
53 if (r
->domain_nr
== domain_nr
)
56 r
= kzalloc(sizeof(*r
), GFP_KERNEL
);
60 r
->domain_nr
= domain_nr
;
63 r
->res
.flags
= IORESOURCE_BUS
| IORESOURCE_PCI_FIXED
;
65 list_add_tail(&r
->list
, &pci_domain_busn_res_list
);
71 * Some device drivers need know if PCI is initiated.
72 * Basically, we think PCI is not initiated when there
73 * is no device to be found on the pci_bus_type.
75 int no_pci_devices(void)
80 dev
= bus_find_next_device(&pci_bus_type
, NULL
);
81 no_devices
= (dev
== NULL
);
85 EXPORT_SYMBOL(no_pci_devices
);
90 static void release_pcibus_dev(struct device
*dev
)
92 struct pci_bus
*pci_bus
= to_pci_bus(dev
);
94 put_device(pci_bus
->bridge
);
95 pci_bus_remove_resources(pci_bus
);
96 pci_release_bus_of_node(pci_bus
);
100 static struct class pcibus_class
= {
102 .dev_release
= &release_pcibus_dev
,
103 .dev_groups
= pcibus_groups
,
106 static int __init
pcibus_class_init(void)
108 return class_register(&pcibus_class
);
110 postcore_initcall(pcibus_class_init
);
112 static u64
pci_size(u64 base
, u64 maxbase
, u64 mask
)
114 u64 size
= mask
& maxbase
; /* Find the significant bits */
119 * Get the lowest of them to find the decode size, and from that
122 size
= size
& ~(size
-1);
125 * base == maxbase can be valid only if the BAR has already been
126 * programmed with all 1s.
128 if (base
== maxbase
&& ((base
| (size
- 1)) & mask
) != mask
)
134 static inline unsigned long decode_bar(struct pci_dev
*dev
, u32 bar
)
139 if ((bar
& PCI_BASE_ADDRESS_SPACE
) == PCI_BASE_ADDRESS_SPACE_IO
) {
140 flags
= bar
& ~PCI_BASE_ADDRESS_IO_MASK
;
141 flags
|= IORESOURCE_IO
;
145 flags
= bar
& ~PCI_BASE_ADDRESS_MEM_MASK
;
146 flags
|= IORESOURCE_MEM
;
147 if (flags
& PCI_BASE_ADDRESS_MEM_PREFETCH
)
148 flags
|= IORESOURCE_PREFETCH
;
150 mem_type
= bar
& PCI_BASE_ADDRESS_MEM_TYPE_MASK
;
152 case PCI_BASE_ADDRESS_MEM_TYPE_32
:
154 case PCI_BASE_ADDRESS_MEM_TYPE_1M
:
155 /* 1M mem BAR treated as 32-bit BAR */
157 case PCI_BASE_ADDRESS_MEM_TYPE_64
:
158 flags
|= IORESOURCE_MEM_64
;
161 /* mem unknown type treated as 32-bit BAR */
167 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
170 * __pci_read_base - Read a PCI BAR
171 * @dev: the PCI device
172 * @type: type of the BAR
173 * @res: resource buffer to be filled in
174 * @pos: BAR position in the config space
176 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
178 int __pci_read_base(struct pci_dev
*dev
, enum pci_bar_type type
,
179 struct resource
*res
, unsigned int pos
)
181 u32 l
= 0, sz
= 0, mask
;
182 u64 l64
, sz64
, mask64
;
184 struct pci_bus_region region
, inverted_region
;
186 mask
= type
? PCI_ROM_ADDRESS_MASK
: ~0;
188 /* No printks while decoding is disabled! */
189 if (!dev
->mmio_always_on
) {
190 pci_read_config_word(dev
, PCI_COMMAND
, &orig_cmd
);
191 if (orig_cmd
& PCI_COMMAND_DECODE_ENABLE
) {
192 pci_write_config_word(dev
, PCI_COMMAND
,
193 orig_cmd
& ~PCI_COMMAND_DECODE_ENABLE
);
197 res
->name
= pci_name(dev
);
199 pci_read_config_dword(dev
, pos
, &l
);
200 pci_write_config_dword(dev
, pos
, l
| mask
);
201 pci_read_config_dword(dev
, pos
, &sz
);
202 pci_write_config_dword(dev
, pos
, l
);
205 * All bits set in sz means the device isn't working properly.
206 * If the BAR isn't implemented, all bits must be 0. If it's a
207 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
210 if (sz
== 0xffffffff)
214 * I don't know how l can have all bits set. Copied from old code.
215 * Maybe it fixes a bug on some ancient platform.
220 if (type
== pci_bar_unknown
) {
221 res
->flags
= decode_bar(dev
, l
);
222 res
->flags
|= IORESOURCE_SIZEALIGN
;
223 if (res
->flags
& IORESOURCE_IO
) {
224 l64
= l
& PCI_BASE_ADDRESS_IO_MASK
;
225 sz64
= sz
& PCI_BASE_ADDRESS_IO_MASK
;
226 mask64
= PCI_BASE_ADDRESS_IO_MASK
& (u32
)IO_SPACE_LIMIT
;
228 l64
= l
& PCI_BASE_ADDRESS_MEM_MASK
;
229 sz64
= sz
& PCI_BASE_ADDRESS_MEM_MASK
;
230 mask64
= (u32
)PCI_BASE_ADDRESS_MEM_MASK
;
233 if (l
& PCI_ROM_ADDRESS_ENABLE
)
234 res
->flags
|= IORESOURCE_ROM_ENABLE
;
235 l64
= l
& PCI_ROM_ADDRESS_MASK
;
236 sz64
= sz
& PCI_ROM_ADDRESS_MASK
;
237 mask64
= PCI_ROM_ADDRESS_MASK
;
240 if (res
->flags
& IORESOURCE_MEM_64
) {
241 pci_read_config_dword(dev
, pos
+ 4, &l
);
242 pci_write_config_dword(dev
, pos
+ 4, ~0);
243 pci_read_config_dword(dev
, pos
+ 4, &sz
);
244 pci_write_config_dword(dev
, pos
+ 4, l
);
246 l64
|= ((u64
)l
<< 32);
247 sz64
|= ((u64
)sz
<< 32);
248 mask64
|= ((u64
)~0 << 32);
251 if (!dev
->mmio_always_on
&& (orig_cmd
& PCI_COMMAND_DECODE_ENABLE
))
252 pci_write_config_word(dev
, PCI_COMMAND
, orig_cmd
);
257 sz64
= pci_size(l64
, sz64
, mask64
);
259 pci_info(dev
, FW_BUG
"reg 0x%x: invalid BAR (can't size)\n",
264 if (res
->flags
& IORESOURCE_MEM_64
) {
265 if ((sizeof(pci_bus_addr_t
) < 8 || sizeof(resource_size_t
) < 8)
266 && sz64
> 0x100000000ULL
) {
267 res
->flags
|= IORESOURCE_UNSET
| IORESOURCE_DISABLED
;
270 pci_err(dev
, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
271 pos
, (unsigned long long)sz64
);
275 if ((sizeof(pci_bus_addr_t
) < 8) && l
) {
276 /* Above 32-bit boundary; try to reallocate */
277 res
->flags
|= IORESOURCE_UNSET
;
280 pci_info(dev
, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
281 pos
, (unsigned long long)l64
);
287 region
.end
= l64
+ sz64
- 1;
289 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
290 pcibios_resource_to_bus(dev
->bus
, &inverted_region
, res
);
293 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
294 * the corresponding resource address (the physical address used by
295 * the CPU. Converting that resource address back to a bus address
296 * should yield the original BAR value:
298 * resource_to_bus(bus_to_resource(A)) == A
300 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
301 * be claimed by the device.
303 if (inverted_region
.start
!= region
.start
) {
304 res
->flags
|= IORESOURCE_UNSET
;
306 res
->end
= region
.end
- region
.start
;
307 pci_info(dev
, "reg 0x%x: initial BAR value %#010llx invalid\n",
308 pos
, (unsigned long long)region
.start
);
318 pci_info(dev
, "reg 0x%x: %pR\n", pos
, res
);
320 return (res
->flags
& IORESOURCE_MEM_64
) ? 1 : 0;
323 static void pci_read_bases(struct pci_dev
*dev
, unsigned int howmany
, int rom
)
325 unsigned int pos
, reg
;
327 if (dev
->non_compliant_bars
)
330 /* Per PCIe r4.0, sec 9.3.4.1.11, the VF BARs are all RO Zero */
334 for (pos
= 0; pos
< howmany
; pos
++) {
335 struct resource
*res
= &dev
->resource
[pos
];
336 reg
= PCI_BASE_ADDRESS_0
+ (pos
<< 2);
337 pos
+= __pci_read_base(dev
, pci_bar_unknown
, res
, reg
);
341 struct resource
*res
= &dev
->resource
[PCI_ROM_RESOURCE
];
342 dev
->rom_base_reg
= rom
;
343 res
->flags
= IORESOURCE_MEM
| IORESOURCE_PREFETCH
|
344 IORESOURCE_READONLY
| IORESOURCE_SIZEALIGN
;
345 __pci_read_base(dev
, pci_bar_mem32
, res
, rom
);
349 static void pci_read_bridge_windows(struct pci_dev
*bridge
)
354 pci_read_config_word(bridge
, PCI_IO_BASE
, &io
);
356 pci_write_config_word(bridge
, PCI_IO_BASE
, 0xe0f0);
357 pci_read_config_word(bridge
, PCI_IO_BASE
, &io
);
358 pci_write_config_word(bridge
, PCI_IO_BASE
, 0x0);
361 bridge
->io_window
= 1;
364 * DECchip 21050 pass 2 errata: the bridge may miss an address
365 * disconnect boundary by one PCI data phase. Workaround: do not
366 * use prefetching on this device.
368 if (bridge
->vendor
== PCI_VENDOR_ID_DEC
&& bridge
->device
== 0x0001)
371 pci_read_config_dword(bridge
, PCI_PREF_MEMORY_BASE
, &pmem
);
373 pci_write_config_dword(bridge
, PCI_PREF_MEMORY_BASE
,
375 pci_read_config_dword(bridge
, PCI_PREF_MEMORY_BASE
, &pmem
);
376 pci_write_config_dword(bridge
, PCI_PREF_MEMORY_BASE
, 0x0);
381 bridge
->pref_window
= 1;
383 if ((pmem
& PCI_PREF_RANGE_TYPE_MASK
) == PCI_PREF_RANGE_TYPE_64
) {
386 * Bridge claims to have a 64-bit prefetchable memory
387 * window; verify that the upper bits are actually
390 pci_read_config_dword(bridge
, PCI_PREF_BASE_UPPER32
, &pmem
);
391 pci_write_config_dword(bridge
, PCI_PREF_BASE_UPPER32
,
393 pci_read_config_dword(bridge
, PCI_PREF_BASE_UPPER32
, &tmp
);
394 pci_write_config_dword(bridge
, PCI_PREF_BASE_UPPER32
, pmem
);
396 bridge
->pref_64_window
= 1;
400 static void pci_read_bridge_io(struct pci_bus
*child
)
402 struct pci_dev
*dev
= child
->self
;
403 u8 io_base_lo
, io_limit_lo
;
404 unsigned long io_mask
, io_granularity
, base
, limit
;
405 struct pci_bus_region region
;
406 struct resource
*res
;
408 io_mask
= PCI_IO_RANGE_MASK
;
409 io_granularity
= 0x1000;
410 if (dev
->io_window_1k
) {
411 /* Support 1K I/O space granularity */
412 io_mask
= PCI_IO_1K_RANGE_MASK
;
413 io_granularity
= 0x400;
416 res
= child
->resource
[0];
417 pci_read_config_byte(dev
, PCI_IO_BASE
, &io_base_lo
);
418 pci_read_config_byte(dev
, PCI_IO_LIMIT
, &io_limit_lo
);
419 base
= (io_base_lo
& io_mask
) << 8;
420 limit
= (io_limit_lo
& io_mask
) << 8;
422 if ((io_base_lo
& PCI_IO_RANGE_TYPE_MASK
) == PCI_IO_RANGE_TYPE_32
) {
423 u16 io_base_hi
, io_limit_hi
;
425 pci_read_config_word(dev
, PCI_IO_BASE_UPPER16
, &io_base_hi
);
426 pci_read_config_word(dev
, PCI_IO_LIMIT_UPPER16
, &io_limit_hi
);
427 base
|= ((unsigned long) io_base_hi
<< 16);
428 limit
|= ((unsigned long) io_limit_hi
<< 16);
432 res
->flags
= (io_base_lo
& PCI_IO_RANGE_TYPE_MASK
) | IORESOURCE_IO
;
434 region
.end
= limit
+ io_granularity
- 1;
435 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
436 pci_info(dev
, " bridge window %pR\n", res
);
440 static void pci_read_bridge_mmio(struct pci_bus
*child
)
442 struct pci_dev
*dev
= child
->self
;
443 u16 mem_base_lo
, mem_limit_lo
;
444 unsigned long base
, limit
;
445 struct pci_bus_region region
;
446 struct resource
*res
;
448 res
= child
->resource
[1];
449 pci_read_config_word(dev
, PCI_MEMORY_BASE
, &mem_base_lo
);
450 pci_read_config_word(dev
, PCI_MEMORY_LIMIT
, &mem_limit_lo
);
451 base
= ((unsigned long) mem_base_lo
& PCI_MEMORY_RANGE_MASK
) << 16;
452 limit
= ((unsigned long) mem_limit_lo
& PCI_MEMORY_RANGE_MASK
) << 16;
454 res
->flags
= (mem_base_lo
& PCI_MEMORY_RANGE_TYPE_MASK
) | IORESOURCE_MEM
;
456 region
.end
= limit
+ 0xfffff;
457 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
458 pci_info(dev
, " bridge window %pR\n", res
);
462 static void pci_read_bridge_mmio_pref(struct pci_bus
*child
)
464 struct pci_dev
*dev
= child
->self
;
465 u16 mem_base_lo
, mem_limit_lo
;
467 pci_bus_addr_t base
, limit
;
468 struct pci_bus_region region
;
469 struct resource
*res
;
471 res
= child
->resource
[2];
472 pci_read_config_word(dev
, PCI_PREF_MEMORY_BASE
, &mem_base_lo
);
473 pci_read_config_word(dev
, PCI_PREF_MEMORY_LIMIT
, &mem_limit_lo
);
474 base64
= (mem_base_lo
& PCI_PREF_RANGE_MASK
) << 16;
475 limit64
= (mem_limit_lo
& PCI_PREF_RANGE_MASK
) << 16;
477 if ((mem_base_lo
& PCI_PREF_RANGE_TYPE_MASK
) == PCI_PREF_RANGE_TYPE_64
) {
478 u32 mem_base_hi
, mem_limit_hi
;
480 pci_read_config_dword(dev
, PCI_PREF_BASE_UPPER32
, &mem_base_hi
);
481 pci_read_config_dword(dev
, PCI_PREF_LIMIT_UPPER32
, &mem_limit_hi
);
484 * Some bridges set the base > limit by default, and some
485 * (broken) BIOSes do not initialize them. If we find
486 * this, just assume they are not being used.
488 if (mem_base_hi
<= mem_limit_hi
) {
489 base64
|= (u64
) mem_base_hi
<< 32;
490 limit64
|= (u64
) mem_limit_hi
<< 32;
494 base
= (pci_bus_addr_t
) base64
;
495 limit
= (pci_bus_addr_t
) limit64
;
497 if (base
!= base64
) {
498 pci_err(dev
, "can't handle bridge window above 4GB (bus address %#010llx)\n",
499 (unsigned long long) base64
);
504 res
->flags
= (mem_base_lo
& PCI_PREF_RANGE_TYPE_MASK
) |
505 IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
506 if (res
->flags
& PCI_PREF_RANGE_TYPE_64
)
507 res
->flags
|= IORESOURCE_MEM_64
;
509 region
.end
= limit
+ 0xfffff;
510 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
511 pci_info(dev
, " bridge window %pR\n", res
);
515 void pci_read_bridge_bases(struct pci_bus
*child
)
517 struct pci_dev
*dev
= child
->self
;
518 struct resource
*res
;
521 if (pci_is_root_bus(child
)) /* It's a host bus, nothing to read */
524 pci_info(dev
, "PCI bridge to %pR%s\n",
526 dev
->transparent
? " (subtractive decode)" : "");
528 pci_bus_remove_resources(child
);
529 for (i
= 0; i
< PCI_BRIDGE_RESOURCE_NUM
; i
++)
530 child
->resource
[i
] = &dev
->resource
[PCI_BRIDGE_RESOURCES
+i
];
532 pci_read_bridge_io(child
);
533 pci_read_bridge_mmio(child
);
534 pci_read_bridge_mmio_pref(child
);
536 if (dev
->transparent
) {
537 pci_bus_for_each_resource(child
->parent
, res
, i
) {
538 if (res
&& res
->flags
) {
539 pci_bus_add_resource(child
, res
,
540 PCI_SUBTRACTIVE_DECODE
);
541 pci_info(dev
, " bridge window %pR (subtractive decode)\n",
548 static struct pci_bus
*pci_alloc_bus(struct pci_bus
*parent
)
552 b
= kzalloc(sizeof(*b
), GFP_KERNEL
);
556 INIT_LIST_HEAD(&b
->node
);
557 INIT_LIST_HEAD(&b
->children
);
558 INIT_LIST_HEAD(&b
->devices
);
559 INIT_LIST_HEAD(&b
->slots
);
560 INIT_LIST_HEAD(&b
->resources
);
561 b
->max_bus_speed
= PCI_SPEED_UNKNOWN
;
562 b
->cur_bus_speed
= PCI_SPEED_UNKNOWN
;
563 #ifdef CONFIG_PCI_DOMAINS_GENERIC
565 b
->domain_nr
= parent
->domain_nr
;
570 static void pci_release_host_bridge_dev(struct device
*dev
)
572 struct pci_host_bridge
*bridge
= to_pci_host_bridge(dev
);
574 if (bridge
->release_fn
)
575 bridge
->release_fn(bridge
);
577 pci_free_resource_list(&bridge
->windows
);
578 pci_free_resource_list(&bridge
->dma_ranges
);
582 static void pci_init_host_bridge(struct pci_host_bridge
*bridge
)
584 INIT_LIST_HEAD(&bridge
->windows
);
585 INIT_LIST_HEAD(&bridge
->dma_ranges
);
588 * We assume we can manage these PCIe features. Some systems may
589 * reserve these for use by the platform itself, e.g., an ACPI BIOS
590 * may implement its own AER handling and use _OSC to prevent the
591 * OS from interfering.
593 bridge
->native_aer
= 1;
594 bridge
->native_pcie_hotplug
= 1;
595 bridge
->native_shpc_hotplug
= 1;
596 bridge
->native_pme
= 1;
597 bridge
->native_ltr
= 1;
598 bridge
->native_dpc
= 1;
599 bridge
->domain_nr
= PCI_DOMAIN_NR_NOT_SET
;
601 device_initialize(&bridge
->dev
);
604 struct pci_host_bridge
*pci_alloc_host_bridge(size_t priv
)
606 struct pci_host_bridge
*bridge
;
608 bridge
= kzalloc(sizeof(*bridge
) + priv
, GFP_KERNEL
);
612 pci_init_host_bridge(bridge
);
613 bridge
->dev
.release
= pci_release_host_bridge_dev
;
617 EXPORT_SYMBOL(pci_alloc_host_bridge
);
619 static void devm_pci_alloc_host_bridge_release(void *data
)
621 pci_free_host_bridge(data
);
624 struct pci_host_bridge
*devm_pci_alloc_host_bridge(struct device
*dev
,
628 struct pci_host_bridge
*bridge
;
630 bridge
= pci_alloc_host_bridge(priv
);
634 bridge
->dev
.parent
= dev
;
636 ret
= devm_add_action_or_reset(dev
, devm_pci_alloc_host_bridge_release
,
641 ret
= devm_of_pci_bridge_init(dev
, bridge
);
647 EXPORT_SYMBOL(devm_pci_alloc_host_bridge
);
649 void pci_free_host_bridge(struct pci_host_bridge
*bridge
)
651 put_device(&bridge
->dev
);
653 EXPORT_SYMBOL(pci_free_host_bridge
);
655 /* Indexed by PCI_X_SSTATUS_FREQ (secondary bus mode and frequency) */
656 static const unsigned char pcix_bus_speed
[] = {
657 PCI_SPEED_UNKNOWN
, /* 0 */
658 PCI_SPEED_66MHz_PCIX
, /* 1 */
659 PCI_SPEED_100MHz_PCIX
, /* 2 */
660 PCI_SPEED_133MHz_PCIX
, /* 3 */
661 PCI_SPEED_UNKNOWN
, /* 4 */
662 PCI_SPEED_66MHz_PCIX_ECC
, /* 5 */
663 PCI_SPEED_100MHz_PCIX_ECC
, /* 6 */
664 PCI_SPEED_133MHz_PCIX_ECC
, /* 7 */
665 PCI_SPEED_UNKNOWN
, /* 8 */
666 PCI_SPEED_66MHz_PCIX_266
, /* 9 */
667 PCI_SPEED_100MHz_PCIX_266
, /* A */
668 PCI_SPEED_133MHz_PCIX_266
, /* B */
669 PCI_SPEED_UNKNOWN
, /* C */
670 PCI_SPEED_66MHz_PCIX_533
, /* D */
671 PCI_SPEED_100MHz_PCIX_533
, /* E */
672 PCI_SPEED_133MHz_PCIX_533
/* F */
675 /* Indexed by PCI_EXP_LNKCAP_SLS, PCI_EXP_LNKSTA_CLS */
676 const unsigned char pcie_link_speed
[] = {
677 PCI_SPEED_UNKNOWN
, /* 0 */
678 PCIE_SPEED_2_5GT
, /* 1 */
679 PCIE_SPEED_5_0GT
, /* 2 */
680 PCIE_SPEED_8_0GT
, /* 3 */
681 PCIE_SPEED_16_0GT
, /* 4 */
682 PCIE_SPEED_32_0GT
, /* 5 */
683 PCIE_SPEED_64_0GT
, /* 6 */
684 PCI_SPEED_UNKNOWN
, /* 7 */
685 PCI_SPEED_UNKNOWN
, /* 8 */
686 PCI_SPEED_UNKNOWN
, /* 9 */
687 PCI_SPEED_UNKNOWN
, /* A */
688 PCI_SPEED_UNKNOWN
, /* B */
689 PCI_SPEED_UNKNOWN
, /* C */
690 PCI_SPEED_UNKNOWN
, /* D */
691 PCI_SPEED_UNKNOWN
, /* E */
692 PCI_SPEED_UNKNOWN
/* F */
694 EXPORT_SYMBOL_GPL(pcie_link_speed
);
696 const char *pci_speed_string(enum pci_bus_speed speed
)
698 /* Indexed by the pci_bus_speed enum */
699 static const char *speed_strings
[] = {
700 "33 MHz PCI", /* 0x00 */
701 "66 MHz PCI", /* 0x01 */
702 "66 MHz PCI-X", /* 0x02 */
703 "100 MHz PCI-X", /* 0x03 */
704 "133 MHz PCI-X", /* 0x04 */
709 "66 MHz PCI-X 266", /* 0x09 */
710 "100 MHz PCI-X 266", /* 0x0a */
711 "133 MHz PCI-X 266", /* 0x0b */
712 "Unknown AGP", /* 0x0c */
717 "66 MHz PCI-X 533", /* 0x11 */
718 "100 MHz PCI-X 533", /* 0x12 */
719 "133 MHz PCI-X 533", /* 0x13 */
720 "2.5 GT/s PCIe", /* 0x14 */
721 "5.0 GT/s PCIe", /* 0x15 */
722 "8.0 GT/s PCIe", /* 0x16 */
723 "16.0 GT/s PCIe", /* 0x17 */
724 "32.0 GT/s PCIe", /* 0x18 */
725 "64.0 GT/s PCIe", /* 0x19 */
728 if (speed
< ARRAY_SIZE(speed_strings
))
729 return speed_strings
[speed
];
732 EXPORT_SYMBOL_GPL(pci_speed_string
);
734 void pcie_update_link_speed(struct pci_bus
*bus
, u16 linksta
)
736 bus
->cur_bus_speed
= pcie_link_speed
[linksta
& PCI_EXP_LNKSTA_CLS
];
738 EXPORT_SYMBOL_GPL(pcie_update_link_speed
);
740 static unsigned char agp_speeds
[] = {
748 static enum pci_bus_speed
agp_speed(int agp3
, int agpstat
)
754 else if (agpstat
& 2)
756 else if (agpstat
& 1)
768 return agp_speeds
[index
];
771 static void pci_set_bus_speed(struct pci_bus
*bus
)
773 struct pci_dev
*bridge
= bus
->self
;
776 pos
= pci_find_capability(bridge
, PCI_CAP_ID_AGP
);
778 pos
= pci_find_capability(bridge
, PCI_CAP_ID_AGP3
);
782 pci_read_config_dword(bridge
, pos
+ PCI_AGP_STATUS
, &agpstat
);
783 bus
->max_bus_speed
= agp_speed(agpstat
& 8, agpstat
& 7);
785 pci_read_config_dword(bridge
, pos
+ PCI_AGP_COMMAND
, &agpcmd
);
786 bus
->cur_bus_speed
= agp_speed(agpstat
& 8, agpcmd
& 7);
789 pos
= pci_find_capability(bridge
, PCI_CAP_ID_PCIX
);
792 enum pci_bus_speed max
;
794 pci_read_config_word(bridge
, pos
+ PCI_X_BRIDGE_SSTATUS
,
797 if (status
& PCI_X_SSTATUS_533MHZ
) {
798 max
= PCI_SPEED_133MHz_PCIX_533
;
799 } else if (status
& PCI_X_SSTATUS_266MHZ
) {
800 max
= PCI_SPEED_133MHz_PCIX_266
;
801 } else if (status
& PCI_X_SSTATUS_133MHZ
) {
802 if ((status
& PCI_X_SSTATUS_VERS
) == PCI_X_SSTATUS_V2
)
803 max
= PCI_SPEED_133MHz_PCIX_ECC
;
805 max
= PCI_SPEED_133MHz_PCIX
;
807 max
= PCI_SPEED_66MHz_PCIX
;
810 bus
->max_bus_speed
= max
;
811 bus
->cur_bus_speed
= pcix_bus_speed
[
812 (status
& PCI_X_SSTATUS_FREQ
) >> 6];
817 if (pci_is_pcie(bridge
)) {
821 pcie_capability_read_dword(bridge
, PCI_EXP_LNKCAP
, &linkcap
);
822 bus
->max_bus_speed
= pcie_link_speed
[linkcap
& PCI_EXP_LNKCAP_SLS
];
823 bridge
->link_active_reporting
= !!(linkcap
& PCI_EXP_LNKCAP_DLLLARC
);
825 pcie_capability_read_word(bridge
, PCI_EXP_LNKSTA
, &linksta
);
826 pcie_update_link_speed(bus
, linksta
);
830 static struct irq_domain
*pci_host_bridge_msi_domain(struct pci_bus
*bus
)
832 struct irq_domain
*d
;
834 /* If the host bridge driver sets a MSI domain of the bridge, use it */
835 d
= dev_get_msi_domain(bus
->bridge
);
838 * Any firmware interface that can resolve the msi_domain
839 * should be called from here.
842 d
= pci_host_bridge_of_msi_domain(bus
);
844 d
= pci_host_bridge_acpi_msi_domain(bus
);
846 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
848 * If no IRQ domain was found via the OF tree, try looking it up
849 * directly through the fwnode_handle.
852 struct fwnode_handle
*fwnode
= pci_root_bus_fwnode(bus
);
855 d
= irq_find_matching_fwnode(fwnode
,
863 static void pci_set_bus_msi_domain(struct pci_bus
*bus
)
865 struct irq_domain
*d
;
869 * The bus can be a root bus, a subordinate bus, or a virtual bus
870 * created by an SR-IOV device. Walk up to the first bridge device
871 * found or derive the domain from the host bridge.
873 for (b
= bus
, d
= NULL
; !d
&& !pci_is_root_bus(b
); b
= b
->parent
) {
875 d
= dev_get_msi_domain(&b
->self
->dev
);
879 d
= pci_host_bridge_msi_domain(b
);
881 dev_set_msi_domain(&bus
->dev
, d
);
884 static int res_cmp(void *priv
, const struct list_head
*a
,
885 const struct list_head
*b
)
887 struct resource_entry
*entry1
, *entry2
;
889 entry1
= container_of(a
, struct resource_entry
, node
);
890 entry2
= container_of(b
, struct resource_entry
, node
);
892 if (entry1
->res
->flags
!= entry2
->res
->flags
)
893 return entry1
->res
->flags
> entry2
->res
->flags
;
895 if (entry1
->offset
!= entry2
->offset
)
896 return entry1
->offset
> entry2
->offset
;
898 return entry1
->res
->start
> entry2
->res
->start
;
901 static int pci_register_host_bridge(struct pci_host_bridge
*bridge
)
903 struct device
*parent
= bridge
->dev
.parent
;
904 struct resource_entry
*window
, *next
, *n
;
905 struct pci_bus
*bus
, *b
;
906 resource_size_t offset
, next_offset
;
907 LIST_HEAD(resources
);
908 struct resource
*res
, *next_res
;
913 bus
= pci_alloc_bus(NULL
);
919 /* Temporarily move resources off the list */
920 list_splice_init(&bridge
->windows
, &resources
);
921 bus
->sysdata
= bridge
->sysdata
;
922 bus
->ops
= bridge
->ops
;
923 bus
->number
= bus
->busn_res
.start
= bridge
->busnr
;
924 #ifdef CONFIG_PCI_DOMAINS_GENERIC
925 if (bridge
->domain_nr
== PCI_DOMAIN_NR_NOT_SET
)
926 bus
->domain_nr
= pci_bus_find_domain_nr(bus
, parent
);
928 bus
->domain_nr
= bridge
->domain_nr
;
931 b
= pci_find_bus(pci_domain_nr(bus
), bridge
->busnr
);
933 /* Ignore it if we already got here via a different bridge */
934 dev_dbg(&b
->dev
, "bus already known\n");
939 dev_set_name(&bridge
->dev
, "pci%04x:%02x", pci_domain_nr(bus
),
942 err
= pcibios_root_bridge_prepare(bridge
);
946 err
= device_add(&bridge
->dev
);
948 put_device(&bridge
->dev
);
951 bus
->bridge
= get_device(&bridge
->dev
);
952 device_enable_async_suspend(bus
->bridge
);
953 pci_set_bus_of_node(bus
);
954 pci_set_bus_msi_domain(bus
);
955 if (bridge
->msi_domain
&& !dev_get_msi_domain(&bus
->dev
) &&
956 !pci_host_of_has_msi_map(parent
))
957 bus
->bus_flags
|= PCI_BUS_FLAGS_NO_MSI
;
960 set_dev_node(bus
->bridge
, pcibus_to_node(bus
));
962 bus
->dev
.class = &pcibus_class
;
963 bus
->dev
.parent
= bus
->bridge
;
965 dev_set_name(&bus
->dev
, "%04x:%02x", pci_domain_nr(bus
), bus
->number
);
966 name
= dev_name(&bus
->dev
);
968 err
= device_register(&bus
->dev
);
972 pcibios_add_bus(bus
);
974 if (bus
->ops
->add_bus
) {
975 err
= bus
->ops
->add_bus(bus
);
976 if (WARN_ON(err
< 0))
977 dev_err(&bus
->dev
, "failed to add bus: %d\n", err
);
980 /* Create legacy_io and legacy_mem files for this bus */
981 pci_create_legacy_files(bus
);
984 dev_info(parent
, "PCI host bridge to bus %s\n", name
);
986 pr_info("PCI host bridge to bus %s\n", name
);
988 if (nr_node_ids
> 1 && pcibus_to_node(bus
) == NUMA_NO_NODE
)
989 dev_warn(&bus
->dev
, "Unknown NUMA node; performance will be reduced\n");
991 /* Sort and coalesce contiguous windows */
992 list_sort(NULL
, &resources
, res_cmp
);
993 resource_list_for_each_entry_safe(window
, n
, &resources
) {
994 if (list_is_last(&window
->node
, &resources
))
997 next
= list_next_entry(window
, node
);
998 offset
= window
->offset
;
1000 next_offset
= next
->offset
;
1001 next_res
= next
->res
;
1003 if (res
->flags
!= next_res
->flags
|| offset
!= next_offset
)
1006 if (res
->end
+ 1 == next_res
->start
) {
1007 next_res
->start
= res
->start
;
1008 res
->flags
= res
->start
= res
->end
= 0;
1012 /* Add initial resources to the bus */
1013 resource_list_for_each_entry_safe(window
, n
, &resources
) {
1014 offset
= window
->offset
;
1019 list_move_tail(&window
->node
, &bridge
->windows
);
1021 if (res
->flags
& IORESOURCE_BUS
)
1022 pci_bus_insert_busn_res(bus
, bus
->number
, res
->end
);
1024 pci_bus_add_resource(bus
, res
, 0);
1027 if (resource_type(res
) == IORESOURCE_IO
)
1028 fmt
= " (bus address [%#06llx-%#06llx])";
1030 fmt
= " (bus address [%#010llx-%#010llx])";
1032 snprintf(addr
, sizeof(addr
), fmt
,
1033 (unsigned long long)(res
->start
- offset
),
1034 (unsigned long long)(res
->end
- offset
));
1038 dev_info(&bus
->dev
, "root bus resource %pR%s\n", res
, addr
);
1041 down_write(&pci_bus_sem
);
1042 list_add_tail(&bus
->node
, &pci_root_buses
);
1043 up_write(&pci_bus_sem
);
1048 put_device(&bridge
->dev
);
1049 device_del(&bridge
->dev
);
1056 static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev
*bridge
)
1062 * If extended config space isn't accessible on a bridge's primary
1063 * bus, we certainly can't access it on the secondary bus.
1065 if (bridge
->bus
->bus_flags
& PCI_BUS_FLAGS_NO_EXTCFG
)
1069 * PCIe Root Ports and switch ports are PCIe on both sides, so if
1070 * extended config space is accessible on the primary, it's also
1071 * accessible on the secondary.
1073 if (pci_is_pcie(bridge
) &&
1074 (pci_pcie_type(bridge
) == PCI_EXP_TYPE_ROOT_PORT
||
1075 pci_pcie_type(bridge
) == PCI_EXP_TYPE_UPSTREAM
||
1076 pci_pcie_type(bridge
) == PCI_EXP_TYPE_DOWNSTREAM
))
1080 * For the other bridge types:
1081 * - PCI-to-PCI bridges
1082 * - PCIe-to-PCI/PCI-X forward bridges
1083 * - PCI/PCI-X-to-PCIe reverse bridges
1084 * extended config space on the secondary side is only accessible
1085 * if the bridge supports PCI-X Mode 2.
1087 pos
= pci_find_capability(bridge
, PCI_CAP_ID_PCIX
);
1091 pci_read_config_dword(bridge
, pos
+ PCI_X_STATUS
, &status
);
1092 return status
& (PCI_X_STATUS_266MHZ
| PCI_X_STATUS_533MHZ
);
1095 static struct pci_bus
*pci_alloc_child_bus(struct pci_bus
*parent
,
1096 struct pci_dev
*bridge
, int busnr
)
1098 struct pci_bus
*child
;
1099 struct pci_host_bridge
*host
;
1103 /* Allocate a new bus and inherit stuff from the parent */
1104 child
= pci_alloc_bus(parent
);
1108 child
->parent
= parent
;
1109 child
->sysdata
= parent
->sysdata
;
1110 child
->bus_flags
= parent
->bus_flags
;
1112 host
= pci_find_host_bridge(parent
);
1113 if (host
->child_ops
)
1114 child
->ops
= host
->child_ops
;
1116 child
->ops
= parent
->ops
;
1119 * Initialize some portions of the bus device, but don't register
1120 * it now as the parent is not properly set up yet.
1122 child
->dev
.class = &pcibus_class
;
1123 dev_set_name(&child
->dev
, "%04x:%02x", pci_domain_nr(child
), busnr
);
1125 /* Set up the primary, secondary and subordinate bus numbers */
1126 child
->number
= child
->busn_res
.start
= busnr
;
1127 child
->primary
= parent
->busn_res
.start
;
1128 child
->busn_res
.end
= 0xff;
1131 child
->dev
.parent
= parent
->bridge
;
1135 child
->self
= bridge
;
1136 child
->bridge
= get_device(&bridge
->dev
);
1137 child
->dev
.parent
= child
->bridge
;
1138 pci_set_bus_of_node(child
);
1139 pci_set_bus_speed(child
);
1142 * Check whether extended config space is accessible on the child
1143 * bus. Note that we currently assume it is always accessible on
1146 if (!pci_bridge_child_ext_cfg_accessible(bridge
)) {
1147 child
->bus_flags
|= PCI_BUS_FLAGS_NO_EXTCFG
;
1148 pci_info(child
, "extended config space not accessible\n");
1151 /* Set up default resource pointers and names */
1152 for (i
= 0; i
< PCI_BRIDGE_RESOURCE_NUM
; i
++) {
1153 child
->resource
[i
] = &bridge
->resource
[PCI_BRIDGE_RESOURCES
+i
];
1154 child
->resource
[i
]->name
= child
->name
;
1156 bridge
->subordinate
= child
;
1159 pci_set_bus_msi_domain(child
);
1160 ret
= device_register(&child
->dev
);
1163 pcibios_add_bus(child
);
1165 if (child
->ops
->add_bus
) {
1166 ret
= child
->ops
->add_bus(child
);
1167 if (WARN_ON(ret
< 0))
1168 dev_err(&child
->dev
, "failed to add bus: %d\n", ret
);
1171 /* Create legacy_io and legacy_mem files for this bus */
1172 pci_create_legacy_files(child
);
1177 struct pci_bus
*pci_add_new_bus(struct pci_bus
*parent
, struct pci_dev
*dev
,
1180 struct pci_bus
*child
;
1182 child
= pci_alloc_child_bus(parent
, dev
, busnr
);
1184 down_write(&pci_bus_sem
);
1185 list_add_tail(&child
->node
, &parent
->children
);
1186 up_write(&pci_bus_sem
);
1190 EXPORT_SYMBOL(pci_add_new_bus
);
1192 static void pci_enable_crs(struct pci_dev
*pdev
)
1196 /* Enable CRS Software Visibility if supported */
1197 pcie_capability_read_word(pdev
, PCI_EXP_RTCAP
, &root_cap
);
1198 if (root_cap
& PCI_EXP_RTCAP_CRSVIS
)
1199 pcie_capability_set_word(pdev
, PCI_EXP_RTCTL
,
1200 PCI_EXP_RTCTL_CRSSVE
);
1203 static unsigned int pci_scan_child_bus_extend(struct pci_bus
*bus
,
1204 unsigned int available_buses
);
1206 * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus
1207 * numbers from EA capability.
1209 * @sec: updated with secondary bus number from EA
1210 * @sub: updated with subordinate bus number from EA
1212 * If @dev is a bridge with EA capability that specifies valid secondary
1213 * and subordinate bus numbers, return true with the bus numbers in @sec
1214 * and @sub. Otherwise return false.
1216 static bool pci_ea_fixed_busnrs(struct pci_dev
*dev
, u8
*sec
, u8
*sub
)
1222 if (dev
->hdr_type
!= PCI_HEADER_TYPE_BRIDGE
)
1225 /* find PCI EA capability in list */
1226 ea
= pci_find_capability(dev
, PCI_CAP_ID_EA
);
1230 offset
= ea
+ PCI_EA_FIRST_ENT
;
1231 pci_read_config_dword(dev
, offset
, &dw
);
1232 ea_sec
= dw
& PCI_EA_SEC_BUS_MASK
;
1233 ea_sub
= (dw
& PCI_EA_SUB_BUS_MASK
) >> PCI_EA_SUB_BUS_SHIFT
;
1234 if (ea_sec
== 0 || ea_sub
< ea_sec
)
1243 * pci_scan_bridge_extend() - Scan buses behind a bridge
1244 * @bus: Parent bus the bridge is on
1245 * @dev: Bridge itself
1246 * @max: Starting subordinate number of buses behind this bridge
1247 * @available_buses: Total number of buses available for this bridge and
1248 * the devices below. After the minimal bus space has
1249 * been allocated the remaining buses will be
1250 * distributed equally between hotplug-capable bridges.
1251 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
1252 * that need to be reconfigured.
1254 * If it's a bridge, configure it and scan the bus behind it.
1255 * For CardBus bridges, we don't scan behind as the devices will
1256 * be handled by the bridge driver itself.
1258 * We need to process bridges in two passes -- first we scan those
1259 * already configured by the BIOS and after we are done with all of
1260 * them, we proceed to assigning numbers to the remaining buses in
1261 * order to avoid overlaps between old and new bus numbers.
1263 * Return: New subordinate number covering all buses behind this bridge.
1265 static int pci_scan_bridge_extend(struct pci_bus
*bus
, struct pci_dev
*dev
,
1266 int max
, unsigned int available_buses
,
1269 struct pci_bus
*child
;
1270 int is_cardbus
= (dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
);
1271 u32 buses
, i
, j
= 0;
1273 u8 primary
, secondary
, subordinate
;
1276 u8 fixed_sec
, fixed_sub
;
1280 * Make sure the bridge is powered on to be able to access config
1281 * space of devices below it.
1283 pm_runtime_get_sync(&dev
->dev
);
1285 pci_read_config_dword(dev
, PCI_PRIMARY_BUS
, &buses
);
1286 primary
= buses
& 0xFF;
1287 secondary
= (buses
>> 8) & 0xFF;
1288 subordinate
= (buses
>> 16) & 0xFF;
1290 pci_dbg(dev
, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
1291 secondary
, subordinate
, pass
);
1293 if (!primary
&& (primary
!= bus
->number
) && secondary
&& subordinate
) {
1294 pci_warn(dev
, "Primary bus is hard wired to 0\n");
1295 primary
= bus
->number
;
1298 /* Check if setup is sensible at all */
1300 (primary
!= bus
->number
|| secondary
<= bus
->number
||
1301 secondary
> subordinate
)) {
1302 pci_info(dev
, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
1303 secondary
, subordinate
);
1308 * Disable Master-Abort Mode during probing to avoid reporting of
1309 * bus errors in some architectures.
1311 pci_read_config_word(dev
, PCI_BRIDGE_CONTROL
, &bctl
);
1312 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
,
1313 bctl
& ~PCI_BRIDGE_CTL_MASTER_ABORT
);
1315 pci_enable_crs(dev
);
1317 if ((secondary
|| subordinate
) && !pcibios_assign_all_busses() &&
1318 !is_cardbus
&& !broken
) {
1322 * Bus already configured by firmware, process it in the
1323 * first pass and just note the configuration.
1329 * The bus might already exist for two reasons: Either we
1330 * are rescanning the bus or the bus is reachable through
1331 * more than one bridge. The second case can happen with
1332 * the i450NX chipset.
1334 child
= pci_find_bus(pci_domain_nr(bus
), secondary
);
1336 child
= pci_add_new_bus(bus
, dev
, secondary
);
1339 child
->primary
= primary
;
1340 pci_bus_insert_busn_res(child
, secondary
, subordinate
);
1341 child
->bridge_ctl
= bctl
;
1344 cmax
= pci_scan_child_bus(child
);
1345 if (cmax
> subordinate
)
1346 pci_warn(dev
, "bridge has subordinate %02x but max busn %02x\n",
1349 /* Subordinate should equal child->busn_res.end */
1350 if (subordinate
> max
)
1355 * We need to assign a number to this bus which we always
1356 * do in the second pass.
1359 if (pcibios_assign_all_busses() || broken
|| is_cardbus
)
1362 * Temporarily disable forwarding of the
1363 * configuration cycles on all bridges in
1364 * this bus segment to avoid possible
1365 * conflicts in the second pass between two
1366 * bridges programmed with overlapping bus
1369 pci_write_config_dword(dev
, PCI_PRIMARY_BUS
,
1375 pci_write_config_word(dev
, PCI_STATUS
, 0xffff);
1377 /* Read bus numbers from EA Capability (if present) */
1378 fixed_buses
= pci_ea_fixed_busnrs(dev
, &fixed_sec
, &fixed_sub
);
1380 next_busnr
= fixed_sec
;
1382 next_busnr
= max
+ 1;
1385 * Prevent assigning a bus number that already exists.
1386 * This can happen when a bridge is hot-plugged, so in this
1387 * case we only re-scan this bus.
1389 child
= pci_find_bus(pci_domain_nr(bus
), next_busnr
);
1391 child
= pci_add_new_bus(bus
, dev
, next_busnr
);
1394 pci_bus_insert_busn_res(child
, next_busnr
,
1398 if (available_buses
)
1401 buses
= (buses
& 0xff000000)
1402 | ((unsigned int)(child
->primary
) << 0)
1403 | ((unsigned int)(child
->busn_res
.start
) << 8)
1404 | ((unsigned int)(child
->busn_res
.end
) << 16);
1407 * yenta.c forces a secondary latency timer of 176.
1408 * Copy that behaviour here.
1411 buses
&= ~0xff000000;
1412 buses
|= CARDBUS_LATENCY_TIMER
<< 24;
1415 /* We need to blast all three values with a single write */
1416 pci_write_config_dword(dev
, PCI_PRIMARY_BUS
, buses
);
1419 child
->bridge_ctl
= bctl
;
1420 max
= pci_scan_child_bus_extend(child
, available_buses
);
1424 * For CardBus bridges, we leave 4 bus numbers as
1425 * cards with a PCI-to-PCI bridge can be inserted
1428 for (i
= 0; i
< CARDBUS_RESERVE_BUSNR
; i
++) {
1429 struct pci_bus
*parent
= bus
;
1430 if (pci_find_bus(pci_domain_nr(bus
),
1433 while (parent
->parent
) {
1434 if ((!pcibios_assign_all_busses()) &&
1435 (parent
->busn_res
.end
> max
) &&
1436 (parent
->busn_res
.end
<= max
+i
)) {
1439 parent
= parent
->parent
;
1444 * Often, there are two CardBus
1445 * bridges -- try to leave one
1446 * valid bus number for each one.
1456 * Set subordinate bus number to its real value.
1457 * If fixed subordinate bus number exists from EA
1458 * capability then use it.
1462 pci_bus_update_busn_res_end(child
, max
);
1463 pci_write_config_byte(dev
, PCI_SUBORDINATE_BUS
, max
);
1466 sprintf(child
->name
,
1467 (is_cardbus
? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
1468 pci_domain_nr(bus
), child
->number
);
1470 /* Check that all devices are accessible */
1471 while (bus
->parent
) {
1472 if ((child
->busn_res
.end
> bus
->busn_res
.end
) ||
1473 (child
->number
> bus
->busn_res
.end
) ||
1474 (child
->number
< bus
->number
) ||
1475 (child
->busn_res
.end
< bus
->number
)) {
1476 dev_info(&dev
->dev
, "devices behind bridge are unusable because %pR cannot be assigned for them\n",
1484 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, bctl
);
1486 pm_runtime_put(&dev
->dev
);
1492 * pci_scan_bridge() - Scan buses behind a bridge
1493 * @bus: Parent bus the bridge is on
1494 * @dev: Bridge itself
1495 * @max: Starting subordinate number of buses behind this bridge
1496 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
1497 * that need to be reconfigured.
1499 * If it's a bridge, configure it and scan the bus behind it.
1500 * For CardBus bridges, we don't scan behind as the devices will
1501 * be handled by the bridge driver itself.
1503 * We need to process bridges in two passes -- first we scan those
1504 * already configured by the BIOS and after we are done with all of
1505 * them, we proceed to assigning numbers to the remaining buses in
1506 * order to avoid overlaps between old and new bus numbers.
1508 * Return: New subordinate number covering all buses behind this bridge.
1510 int pci_scan_bridge(struct pci_bus
*bus
, struct pci_dev
*dev
, int max
, int pass
)
1512 return pci_scan_bridge_extend(bus
, dev
, max
, 0, pass
);
1514 EXPORT_SYMBOL(pci_scan_bridge
);
1517 * Read interrupt line and base address registers.
1518 * The architecture-dependent code can tweak these, of course.
1520 static void pci_read_irq(struct pci_dev
*dev
)
1524 /* VFs are not allowed to use INTx, so skip the config reads */
1525 if (dev
->is_virtfn
) {
1531 pci_read_config_byte(dev
, PCI_INTERRUPT_PIN
, &irq
);
1534 pci_read_config_byte(dev
, PCI_INTERRUPT_LINE
, &irq
);
1538 void set_pcie_port_type(struct pci_dev
*pdev
)
1543 struct pci_dev
*parent
;
1545 pos
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
1549 pdev
->pcie_cap
= pos
;
1550 pci_read_config_word(pdev
, pos
+ PCI_EXP_FLAGS
, ®16
);
1551 pdev
->pcie_flags_reg
= reg16
;
1552 pci_read_config_dword(pdev
, pos
+ PCI_EXP_DEVCAP
, &pdev
->devcap
);
1553 pdev
->pcie_mpss
= FIELD_GET(PCI_EXP_DEVCAP_PAYLOAD
, pdev
->devcap
);
1555 parent
= pci_upstream_bridge(pdev
);
1560 * Some systems do not identify their upstream/downstream ports
1561 * correctly so detect impossible configurations here and correct
1562 * the port type accordingly.
1564 type
= pci_pcie_type(pdev
);
1565 if (type
== PCI_EXP_TYPE_DOWNSTREAM
) {
1567 * If pdev claims to be downstream port but the parent
1568 * device is also downstream port assume pdev is actually
1571 if (pcie_downstream_port(parent
)) {
1572 pci_info(pdev
, "claims to be downstream port but is acting as upstream port, correcting type\n");
1573 pdev
->pcie_flags_reg
&= ~PCI_EXP_FLAGS_TYPE
;
1574 pdev
->pcie_flags_reg
|= PCI_EXP_TYPE_UPSTREAM
;
1576 } else if (type
== PCI_EXP_TYPE_UPSTREAM
) {
1578 * If pdev claims to be upstream port but the parent
1579 * device is also upstream port assume pdev is actually
1582 if (pci_pcie_type(parent
) == PCI_EXP_TYPE_UPSTREAM
) {
1583 pci_info(pdev
, "claims to be upstream port but is acting as downstream port, correcting type\n");
1584 pdev
->pcie_flags_reg
&= ~PCI_EXP_FLAGS_TYPE
;
1585 pdev
->pcie_flags_reg
|= PCI_EXP_TYPE_DOWNSTREAM
;
1590 void set_pcie_hotplug_bridge(struct pci_dev
*pdev
)
1594 pcie_capability_read_dword(pdev
, PCI_EXP_SLTCAP
, ®32
);
1595 if (reg32
& PCI_EXP_SLTCAP_HPC
)
1596 pdev
->is_hotplug_bridge
= 1;
1599 static void set_pcie_thunderbolt(struct pci_dev
*dev
)
1604 while ((vsec
= pci_find_next_ext_capability(dev
, vsec
,
1605 PCI_EXT_CAP_ID_VNDR
))) {
1606 pci_read_config_dword(dev
, vsec
+ PCI_VNDR_HEADER
, &header
);
1608 /* Is the device part of a Thunderbolt controller? */
1609 if (dev
->vendor
== PCI_VENDOR_ID_INTEL
&&
1610 PCI_VNDR_HEADER_ID(header
) == PCI_VSEC_ID_INTEL_TBT
) {
1611 dev
->is_thunderbolt
= 1;
1617 static void set_pcie_untrusted(struct pci_dev
*dev
)
1619 struct pci_dev
*parent
;
1622 * If the upstream bridge is untrusted we treat this device
1623 * untrusted as well.
1625 parent
= pci_upstream_bridge(dev
);
1626 if (parent
&& (parent
->untrusted
|| parent
->external_facing
))
1627 dev
->untrusted
= true;
1630 static void pci_set_removable(struct pci_dev
*dev
)
1632 struct pci_dev
*parent
= pci_upstream_bridge(dev
);
1635 * We (only) consider everything downstream from an external_facing
1636 * device to be removable by the user. We're mainly concerned with
1637 * consumer platforms with user accessible thunderbolt ports that are
1638 * vulnerable to DMA attacks, and we expect those ports to be marked by
1639 * the firmware as external_facing. Devices in traditional hotplug
1640 * slots can technically be removed, but the expectation is that unless
1641 * the port is marked with external_facing, such devices are less
1642 * accessible to user / may not be removed by end user, and thus not
1643 * exposed as "removable" to userspace.
1646 (parent
->external_facing
|| dev_is_removable(&parent
->dev
)))
1647 dev_set_removable(&dev
->dev
, DEVICE_REMOVABLE
);
1651 * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config?
1654 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1655 * when forwarding a type1 configuration request the bridge must check that
1656 * the extended register address field is zero. The bridge is not permitted
1657 * to forward the transactions and must handle it as an Unsupported Request.
1658 * Some bridges do not follow this rule and simply drop the extended register
1659 * bits, resulting in the standard config space being aliased, every 256
1660 * bytes across the entire configuration space. Test for this condition by
1661 * comparing the first dword of each potential alias to the vendor/device ID.
1663 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1664 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1666 static bool pci_ext_cfg_is_aliased(struct pci_dev
*dev
)
1668 #ifdef CONFIG_PCI_QUIRKS
1672 pci_read_config_dword(dev
, PCI_VENDOR_ID
, &header
);
1674 for (pos
= PCI_CFG_SPACE_SIZE
;
1675 pos
< PCI_CFG_SPACE_EXP_SIZE
; pos
+= PCI_CFG_SPACE_SIZE
) {
1676 if (pci_read_config_dword(dev
, pos
, &tmp
) != PCIBIOS_SUCCESSFUL
1688 * pci_cfg_space_size_ext - Get the configuration space size of the PCI device
1691 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1692 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1693 * access it. Maybe we don't have a way to generate extended config space
1694 * accesses, or the device is behind a reverse Express bridge. So we try
1695 * reading the dword at 0x100 which must either be 0 or a valid extended
1696 * capability header.
1698 static int pci_cfg_space_size_ext(struct pci_dev
*dev
)
1701 int pos
= PCI_CFG_SPACE_SIZE
;
1703 if (pci_read_config_dword(dev
, pos
, &status
) != PCIBIOS_SUCCESSFUL
)
1704 return PCI_CFG_SPACE_SIZE
;
1705 if (status
== 0xffffffff || pci_ext_cfg_is_aliased(dev
))
1706 return PCI_CFG_SPACE_SIZE
;
1708 return PCI_CFG_SPACE_EXP_SIZE
;
1711 int pci_cfg_space_size(struct pci_dev
*dev
)
1717 #ifdef CONFIG_PCI_IOV
1719 * Per the SR-IOV specification (rev 1.1, sec 3.5), VFs are required to
1720 * implement a PCIe capability and therefore must implement extended
1721 * config space. We can skip the NO_EXTCFG test below and the
1722 * reachability/aliasing test in pci_cfg_space_size_ext() by virtue of
1723 * the fact that the SR-IOV capability on the PF resides in extended
1724 * config space and must be accessible and non-aliased to have enabled
1725 * support for this VF. This is a micro performance optimization for
1726 * systems supporting many VFs.
1729 return PCI_CFG_SPACE_EXP_SIZE
;
1732 if (dev
->bus
->bus_flags
& PCI_BUS_FLAGS_NO_EXTCFG
)
1733 return PCI_CFG_SPACE_SIZE
;
1735 class = dev
->class >> 8;
1736 if (class == PCI_CLASS_BRIDGE_HOST
)
1737 return pci_cfg_space_size_ext(dev
);
1739 if (pci_is_pcie(dev
))
1740 return pci_cfg_space_size_ext(dev
);
1742 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1744 return PCI_CFG_SPACE_SIZE
;
1746 pci_read_config_dword(dev
, pos
+ PCI_X_STATUS
, &status
);
1747 if (status
& (PCI_X_STATUS_266MHZ
| PCI_X_STATUS_533MHZ
))
1748 return pci_cfg_space_size_ext(dev
);
1750 return PCI_CFG_SPACE_SIZE
;
1753 static u32
pci_class(struct pci_dev
*dev
)
1757 #ifdef CONFIG_PCI_IOV
1759 return dev
->physfn
->sriov
->class;
1761 pci_read_config_dword(dev
, PCI_CLASS_REVISION
, &class);
1765 static void pci_subsystem_ids(struct pci_dev
*dev
, u16
*vendor
, u16
*device
)
1767 #ifdef CONFIG_PCI_IOV
1768 if (dev
->is_virtfn
) {
1769 *vendor
= dev
->physfn
->sriov
->subsystem_vendor
;
1770 *device
= dev
->physfn
->sriov
->subsystem_device
;
1774 pci_read_config_word(dev
, PCI_SUBSYSTEM_VENDOR_ID
, vendor
);
1775 pci_read_config_word(dev
, PCI_SUBSYSTEM_ID
, device
);
1778 static u8
pci_hdr_type(struct pci_dev
*dev
)
1782 #ifdef CONFIG_PCI_IOV
1784 return dev
->physfn
->sriov
->hdr_type
;
1786 pci_read_config_byte(dev
, PCI_HEADER_TYPE
, &hdr_type
);
1790 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1793 * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability
1796 * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this
1797 * at enumeration-time to avoid modifying PCI_COMMAND at run-time.
1799 static int pci_intx_mask_broken(struct pci_dev
*dev
)
1801 u16 orig
, toggle
, new;
1803 pci_read_config_word(dev
, PCI_COMMAND
, &orig
);
1804 toggle
= orig
^ PCI_COMMAND_INTX_DISABLE
;
1805 pci_write_config_word(dev
, PCI_COMMAND
, toggle
);
1806 pci_read_config_word(dev
, PCI_COMMAND
, &new);
1808 pci_write_config_word(dev
, PCI_COMMAND
, orig
);
1811 * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI
1812 * r2.3, so strictly speaking, a device is not *broken* if it's not
1813 * writable. But we'll live with the misnomer for now.
1820 static void early_dump_pci_device(struct pci_dev
*pdev
)
1825 pci_info(pdev
, "config space:\n");
1827 for (i
= 0; i
< 256; i
+= 4)
1828 pci_read_config_dword(pdev
, i
, &value
[i
/ 4]);
1830 print_hex_dump(KERN_INFO
, "", DUMP_PREFIX_OFFSET
, 16, 1,
1835 * pci_setup_device - Fill in class and map information of a device
1836 * @dev: the device structure to fill
1838 * Initialize the device structure with information about the device's
1839 * vendor,class,memory and IO-space addresses, IRQ lines etc.
1840 * Called at initialisation of the PCI subsystem and by CardBus services.
1841 * Returns 0 on success and negative if unknown type of device (not normal,
1842 * bridge or CardBus).
1844 int pci_setup_device(struct pci_dev
*dev
)
1850 struct pci_bus_region region
;
1851 struct resource
*res
;
1853 hdr_type
= pci_hdr_type(dev
);
1855 dev
->sysdata
= dev
->bus
->sysdata
;
1856 dev
->dev
.parent
= dev
->bus
->bridge
;
1857 dev
->dev
.bus
= &pci_bus_type
;
1858 dev
->hdr_type
= hdr_type
& 0x7f;
1859 dev
->multifunction
= !!(hdr_type
& 0x80);
1860 dev
->error_state
= pci_channel_io_normal
;
1861 set_pcie_port_type(dev
);
1863 pci_set_of_node(dev
);
1864 pci_set_acpi_fwnode(dev
);
1866 pci_dev_assign_slot(dev
);
1869 * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1870 * set this higher, assuming the system even supports it.
1872 dev
->dma_mask
= 0xffffffff;
1874 dev_set_name(&dev
->dev
, "%04x:%02x:%02x.%d", pci_domain_nr(dev
->bus
),
1875 dev
->bus
->number
, PCI_SLOT(dev
->devfn
),
1876 PCI_FUNC(dev
->devfn
));
1878 class = pci_class(dev
);
1880 dev
->revision
= class & 0xff;
1881 dev
->class = class >> 8; /* upper 3 bytes */
1884 early_dump_pci_device(dev
);
1886 /* Need to have dev->class ready */
1887 dev
->cfg_size
= pci_cfg_space_size(dev
);
1889 /* Need to have dev->cfg_size ready */
1890 set_pcie_thunderbolt(dev
);
1892 set_pcie_untrusted(dev
);
1894 /* "Unknown power state" */
1895 dev
->current_state
= PCI_UNKNOWN
;
1897 /* Early fixups, before probing the BARs */
1898 pci_fixup_device(pci_fixup_early
, dev
);
1900 pci_set_removable(dev
);
1902 pci_info(dev
, "[%04x:%04x] type %02x class %#08x\n",
1903 dev
->vendor
, dev
->device
, dev
->hdr_type
, dev
->class);
1905 /* Device class may be changed after fixup */
1906 class = dev
->class >> 8;
1908 if (dev
->non_compliant_bars
&& !dev
->mmio_always_on
) {
1909 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1910 if (cmd
& (PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
)) {
1911 pci_info(dev
, "device has non-compliant BARs; disabling IO/MEM decoding\n");
1912 cmd
&= ~PCI_COMMAND_IO
;
1913 cmd
&= ~PCI_COMMAND_MEMORY
;
1914 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1918 dev
->broken_intx_masking
= pci_intx_mask_broken(dev
);
1920 switch (dev
->hdr_type
) { /* header type */
1921 case PCI_HEADER_TYPE_NORMAL
: /* standard header */
1922 if (class == PCI_CLASS_BRIDGE_PCI
)
1925 pci_read_bases(dev
, 6, PCI_ROM_ADDRESS
);
1927 pci_subsystem_ids(dev
, &dev
->subsystem_vendor
, &dev
->subsystem_device
);
1930 * Do the ugly legacy mode stuff here rather than broken chip
1931 * quirk code. Legacy mode ATA controllers have fixed
1932 * addresses. These are not always echoed in BAR0-3, and
1933 * BAR0-3 in a few cases contain junk!
1935 if (class == PCI_CLASS_STORAGE_IDE
) {
1937 pci_read_config_byte(dev
, PCI_CLASS_PROG
, &progif
);
1938 if ((progif
& 1) == 0) {
1939 region
.start
= 0x1F0;
1941 res
= &dev
->resource
[0];
1942 res
->flags
= LEGACY_IO_RESOURCE
;
1943 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
1944 pci_info(dev
, "legacy IDE quirk: reg 0x10: %pR\n",
1946 region
.start
= 0x3F6;
1948 res
= &dev
->resource
[1];
1949 res
->flags
= LEGACY_IO_RESOURCE
;
1950 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
1951 pci_info(dev
, "legacy IDE quirk: reg 0x14: %pR\n",
1954 if ((progif
& 4) == 0) {
1955 region
.start
= 0x170;
1957 res
= &dev
->resource
[2];
1958 res
->flags
= LEGACY_IO_RESOURCE
;
1959 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
1960 pci_info(dev
, "legacy IDE quirk: reg 0x18: %pR\n",
1962 region
.start
= 0x376;
1964 res
= &dev
->resource
[3];
1965 res
->flags
= LEGACY_IO_RESOURCE
;
1966 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
1967 pci_info(dev
, "legacy IDE quirk: reg 0x1c: %pR\n",
1973 case PCI_HEADER_TYPE_BRIDGE
: /* bridge header */
1975 * The PCI-to-PCI bridge spec requires that subtractive
1976 * decoding (i.e. transparent) bridge must have programming
1977 * interface code of 0x01.
1980 dev
->transparent
= ((dev
->class & 0xff) == 1);
1981 pci_read_bases(dev
, 2, PCI_ROM_ADDRESS1
);
1982 pci_read_bridge_windows(dev
);
1983 set_pcie_hotplug_bridge(dev
);
1984 pos
= pci_find_capability(dev
, PCI_CAP_ID_SSVID
);
1986 pci_read_config_word(dev
, pos
+ PCI_SSVID_VENDOR_ID
, &dev
->subsystem_vendor
);
1987 pci_read_config_word(dev
, pos
+ PCI_SSVID_DEVICE_ID
, &dev
->subsystem_device
);
1991 case PCI_HEADER_TYPE_CARDBUS
: /* CardBus bridge header */
1992 if (class != PCI_CLASS_BRIDGE_CARDBUS
)
1995 pci_read_bases(dev
, 1, 0);
1996 pci_read_config_word(dev
, PCI_CB_SUBSYSTEM_VENDOR_ID
, &dev
->subsystem_vendor
);
1997 pci_read_config_word(dev
, PCI_CB_SUBSYSTEM_ID
, &dev
->subsystem_device
);
2000 default: /* unknown header */
2001 pci_err(dev
, "unknown header type %02x, ignoring device\n",
2003 pci_release_of_node(dev
);
2007 pci_err(dev
, "ignoring class %#08x (doesn't match header type %02x)\n",
2008 dev
->class, dev
->hdr_type
);
2009 dev
->class = PCI_CLASS_NOT_DEFINED
<< 8;
2012 /* We found a fine healthy device, go go go... */
2016 static void pci_configure_mps(struct pci_dev
*dev
)
2018 struct pci_dev
*bridge
= pci_upstream_bridge(dev
);
2019 int mps
, mpss
, p_mps
, rc
;
2021 if (!pci_is_pcie(dev
))
2024 /* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */
2029 * For Root Complex Integrated Endpoints, program the maximum
2030 * supported value unless limited by the PCIE_BUS_PEER2PEER case.
2032 if (pci_pcie_type(dev
) == PCI_EXP_TYPE_RC_END
) {
2033 if (pcie_bus_config
== PCIE_BUS_PEER2PEER
)
2036 mps
= 128 << dev
->pcie_mpss
;
2037 rc
= pcie_set_mps(dev
, mps
);
2039 pci_warn(dev
, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
2045 if (!bridge
|| !pci_is_pcie(bridge
))
2048 mps
= pcie_get_mps(dev
);
2049 p_mps
= pcie_get_mps(bridge
);
2054 if (pcie_bus_config
== PCIE_BUS_TUNE_OFF
) {
2055 pci_warn(dev
, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
2056 mps
, pci_name(bridge
), p_mps
);
2061 * Fancier MPS configuration is done later by
2062 * pcie_bus_configure_settings()
2064 if (pcie_bus_config
!= PCIE_BUS_DEFAULT
)
2067 mpss
= 128 << dev
->pcie_mpss
;
2068 if (mpss
< p_mps
&& pci_pcie_type(bridge
) == PCI_EXP_TYPE_ROOT_PORT
) {
2069 pcie_set_mps(bridge
, mpss
);
2070 pci_info(dev
, "Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n",
2071 mpss
, p_mps
, 128 << bridge
->pcie_mpss
);
2072 p_mps
= pcie_get_mps(bridge
);
2075 rc
= pcie_set_mps(dev
, p_mps
);
2077 pci_warn(dev
, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
2082 pci_info(dev
, "Max Payload Size set to %d (was %d, max %d)\n",
2086 int pci_configure_extended_tags(struct pci_dev
*dev
, void *ign
)
2088 struct pci_host_bridge
*host
;
2093 if (!pci_is_pcie(dev
))
2096 ret
= pcie_capability_read_dword(dev
, PCI_EXP_DEVCAP
, &cap
);
2100 if (!(cap
& PCI_EXP_DEVCAP_EXT_TAG
))
2103 ret
= pcie_capability_read_word(dev
, PCI_EXP_DEVCTL
, &ctl
);
2107 host
= pci_find_host_bridge(dev
->bus
);
2112 * If some device in the hierarchy doesn't handle Extended Tags
2113 * correctly, make sure they're disabled.
2115 if (host
->no_ext_tags
) {
2116 if (ctl
& PCI_EXP_DEVCTL_EXT_TAG
) {
2117 pci_info(dev
, "disabling Extended Tags\n");
2118 pcie_capability_clear_word(dev
, PCI_EXP_DEVCTL
,
2119 PCI_EXP_DEVCTL_EXT_TAG
);
2124 if (!(ctl
& PCI_EXP_DEVCTL_EXT_TAG
)) {
2125 pci_info(dev
, "enabling Extended Tags\n");
2126 pcie_capability_set_word(dev
, PCI_EXP_DEVCTL
,
2127 PCI_EXP_DEVCTL_EXT_TAG
);
2133 * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable
2134 * @dev: PCI device to query
2136 * Returns true if the device has enabled relaxed ordering attribute.
2138 bool pcie_relaxed_ordering_enabled(struct pci_dev
*dev
)
2142 pcie_capability_read_word(dev
, PCI_EXP_DEVCTL
, &v
);
2144 return !!(v
& PCI_EXP_DEVCTL_RELAX_EN
);
2146 EXPORT_SYMBOL(pcie_relaxed_ordering_enabled
);
2148 static void pci_configure_relaxed_ordering(struct pci_dev
*dev
)
2150 struct pci_dev
*root
;
2152 /* PCI_EXP_DEVICE_RELAX_EN is RsvdP in VFs */
2156 if (!pcie_relaxed_ordering_enabled(dev
))
2160 * For now, we only deal with Relaxed Ordering issues with Root
2161 * Ports. Peer-to-Peer DMA is another can of worms.
2163 root
= pcie_find_root_port(dev
);
2167 if (root
->dev_flags
& PCI_DEV_FLAGS_NO_RELAXED_ORDERING
) {
2168 pcie_capability_clear_word(dev
, PCI_EXP_DEVCTL
,
2169 PCI_EXP_DEVCTL_RELAX_EN
);
2170 pci_info(dev
, "Relaxed Ordering disabled because the Root Port didn't support it\n");
2174 static void pci_configure_ltr(struct pci_dev
*dev
)
2176 #ifdef CONFIG_PCIEASPM
2177 struct pci_host_bridge
*host
= pci_find_host_bridge(dev
->bus
);
2178 struct pci_dev
*bridge
;
2181 if (!pci_is_pcie(dev
))
2184 /* Read L1 PM substate capabilities */
2185 dev
->l1ss
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_L1SS
);
2187 pcie_capability_read_dword(dev
, PCI_EXP_DEVCAP2
, &cap
);
2188 if (!(cap
& PCI_EXP_DEVCAP2_LTR
))
2191 pcie_capability_read_dword(dev
, PCI_EXP_DEVCTL2
, &ctl
);
2192 if (ctl
& PCI_EXP_DEVCTL2_LTR_EN
) {
2193 if (pci_pcie_type(dev
) == PCI_EXP_TYPE_ROOT_PORT
) {
2198 bridge
= pci_upstream_bridge(dev
);
2199 if (bridge
&& bridge
->ltr_path
)
2205 if (!host
->native_ltr
)
2209 * Software must not enable LTR in an Endpoint unless the Root
2210 * Complex and all intermediate Switches indicate support for LTR.
2211 * PCIe r4.0, sec 6.18.
2213 if (pci_pcie_type(dev
) == PCI_EXP_TYPE_ROOT_PORT
||
2214 ((bridge
= pci_upstream_bridge(dev
)) &&
2215 bridge
->ltr_path
)) {
2216 pcie_capability_set_word(dev
, PCI_EXP_DEVCTL2
,
2217 PCI_EXP_DEVCTL2_LTR_EN
);
2223 static void pci_configure_eetlp_prefix(struct pci_dev
*dev
)
2225 #ifdef CONFIG_PCI_PASID
2226 struct pci_dev
*bridge
;
2230 if (!pci_is_pcie(dev
))
2233 pcie_capability_read_dword(dev
, PCI_EXP_DEVCAP2
, &cap
);
2234 if (!(cap
& PCI_EXP_DEVCAP2_EE_PREFIX
))
2237 pcie_type
= pci_pcie_type(dev
);
2238 if (pcie_type
== PCI_EXP_TYPE_ROOT_PORT
||
2239 pcie_type
== PCI_EXP_TYPE_RC_END
)
2240 dev
->eetlp_prefix_path
= 1;
2242 bridge
= pci_upstream_bridge(dev
);
2243 if (bridge
&& bridge
->eetlp_prefix_path
)
2244 dev
->eetlp_prefix_path
= 1;
2249 static void pci_configure_serr(struct pci_dev
*dev
)
2253 if (dev
->hdr_type
== PCI_HEADER_TYPE_BRIDGE
) {
2256 * A bridge will not forward ERR_ messages coming from an
2257 * endpoint unless SERR# forwarding is enabled.
2259 pci_read_config_word(dev
, PCI_BRIDGE_CONTROL
, &control
);
2260 if (!(control
& PCI_BRIDGE_CTL_SERR
)) {
2261 control
|= PCI_BRIDGE_CTL_SERR
;
2262 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, control
);
2267 static void pci_configure_device(struct pci_dev
*dev
)
2269 pci_configure_mps(dev
);
2270 pci_configure_extended_tags(dev
, NULL
);
2271 pci_configure_relaxed_ordering(dev
);
2272 pci_configure_ltr(dev
);
2273 pci_configure_eetlp_prefix(dev
);
2274 pci_configure_serr(dev
);
2276 pci_acpi_program_hp_params(dev
);
2279 static void pci_release_capabilities(struct pci_dev
*dev
)
2283 pci_iov_release(dev
);
2284 pci_free_cap_save_buffers(dev
);
2288 * pci_release_dev - Free a PCI device structure when all users of it are
2290 * @dev: device that's been disconnected
2292 * Will be called only by the device core when all users of this PCI device are
2295 static void pci_release_dev(struct device
*dev
)
2297 struct pci_dev
*pci_dev
;
2299 pci_dev
= to_pci_dev(dev
);
2300 pci_release_capabilities(pci_dev
);
2301 pci_release_of_node(pci_dev
);
2302 pcibios_release_device(pci_dev
);
2303 pci_bus_put(pci_dev
->bus
);
2304 kfree(pci_dev
->driver_override
);
2305 bitmap_free(pci_dev
->dma_alias_mask
);
2306 dev_dbg(dev
, "device released\n");
2310 struct pci_dev
*pci_alloc_dev(struct pci_bus
*bus
)
2312 struct pci_dev
*dev
;
2314 dev
= kzalloc(sizeof(struct pci_dev
), GFP_KERNEL
);
2318 INIT_LIST_HEAD(&dev
->bus_list
);
2319 dev
->dev
.type
= &pci_dev_type
;
2320 dev
->bus
= pci_bus_get(bus
);
2324 EXPORT_SYMBOL(pci_alloc_dev
);
2326 static bool pci_bus_crs_vendor_id(u32 l
)
2328 return (l
& 0xffff) == 0x0001;
2331 static bool pci_bus_wait_crs(struct pci_bus
*bus
, int devfn
, u32
*l
,
2336 if (!pci_bus_crs_vendor_id(*l
))
2337 return true; /* not a CRS completion */
2340 return false; /* CRS, but caller doesn't want to wait */
2343 * We got the reserved Vendor ID that indicates a completion with
2344 * Configuration Request Retry Status (CRS). Retry until we get a
2345 * valid Vendor ID or we time out.
2347 while (pci_bus_crs_vendor_id(*l
)) {
2348 if (delay
> timeout
) {
2349 pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n",
2350 pci_domain_nr(bus
), bus
->number
,
2351 PCI_SLOT(devfn
), PCI_FUNC(devfn
), delay
- 1);
2356 pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n",
2357 pci_domain_nr(bus
), bus
->number
,
2358 PCI_SLOT(devfn
), PCI_FUNC(devfn
), delay
- 1);
2363 if (pci_bus_read_config_dword(bus
, devfn
, PCI_VENDOR_ID
, l
))
2368 pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n",
2369 pci_domain_nr(bus
), bus
->number
,
2370 PCI_SLOT(devfn
), PCI_FUNC(devfn
), delay
- 1);
2375 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus
*bus
, int devfn
, u32
*l
,
2378 if (pci_bus_read_config_dword(bus
, devfn
, PCI_VENDOR_ID
, l
))
2381 /* Some broken boards return 0 or ~0 if a slot is empty: */
2382 if (*l
== 0xffffffff || *l
== 0x00000000 ||
2383 *l
== 0x0000ffff || *l
== 0xffff0000)
2386 if (pci_bus_crs_vendor_id(*l
))
2387 return pci_bus_wait_crs(bus
, devfn
, l
, timeout
);
2392 bool pci_bus_read_dev_vendor_id(struct pci_bus
*bus
, int devfn
, u32
*l
,
2395 #ifdef CONFIG_PCI_QUIRKS
2396 struct pci_dev
*bridge
= bus
->self
;
2399 * Certain IDT switches have an issue where they improperly trigger
2400 * ACS Source Validation errors on completions for config reads.
2402 if (bridge
&& bridge
->vendor
== PCI_VENDOR_ID_IDT
&&
2403 bridge
->device
== 0x80b5)
2404 return pci_idt_bus_quirk(bus
, devfn
, l
, timeout
);
2407 return pci_bus_generic_read_dev_vendor_id(bus
, devfn
, l
, timeout
);
2409 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id
);
2412 * Read the config data for a PCI device, sanity-check it,
2413 * and fill in the dev structure.
2415 static struct pci_dev
*pci_scan_device(struct pci_bus
*bus
, int devfn
)
2417 struct pci_dev
*dev
;
2420 if (!pci_bus_read_dev_vendor_id(bus
, devfn
, &l
, 60*1000))
2423 dev
= pci_alloc_dev(bus
);
2428 dev
->vendor
= l
& 0xffff;
2429 dev
->device
= (l
>> 16) & 0xffff;
2431 if (pci_setup_device(dev
)) {
2432 pci_bus_put(dev
->bus
);
2440 void pcie_report_downtraining(struct pci_dev
*dev
)
2442 if (!pci_is_pcie(dev
))
2445 /* Look from the device up to avoid downstream ports with no devices */
2446 if ((pci_pcie_type(dev
) != PCI_EXP_TYPE_ENDPOINT
) &&
2447 (pci_pcie_type(dev
) != PCI_EXP_TYPE_LEG_END
) &&
2448 (pci_pcie_type(dev
) != PCI_EXP_TYPE_UPSTREAM
))
2451 /* Multi-function PCIe devices share the same link/status */
2452 if (PCI_FUNC(dev
->devfn
) != 0 || dev
->is_virtfn
)
2455 /* Print link status only if the device is constrained by the fabric */
2456 __pcie_print_link_status(dev
, false);
2459 static void pci_init_capabilities(struct pci_dev
*dev
)
2461 pci_ea_init(dev
); /* Enhanced Allocation */
2462 pci_msi_init(dev
); /* Disable MSI */
2463 pci_msix_init(dev
); /* Disable MSI-X */
2465 /* Buffers for saving PCIe and PCI-X capabilities */
2466 pci_allocate_cap_save_buffers(dev
);
2468 pci_pm_init(dev
); /* Power Management */
2469 pci_vpd_init(dev
); /* Vital Product Data */
2470 pci_configure_ari(dev
); /* Alternative Routing-ID Forwarding */
2471 pci_iov_init(dev
); /* Single Root I/O Virtualization */
2472 pci_ats_init(dev
); /* Address Translation Services */
2473 pci_pri_init(dev
); /* Page Request Interface */
2474 pci_pasid_init(dev
); /* Process Address Space ID */
2475 pci_acs_init(dev
); /* Access Control Services */
2476 pci_ptm_init(dev
); /* Precision Time Measurement */
2477 pci_aer_init(dev
); /* Advanced Error Reporting */
2478 pci_dpc_init(dev
); /* Downstream Port Containment */
2479 pci_rcec_init(dev
); /* Root Complex Event Collector */
2481 pcie_report_downtraining(dev
);
2482 pci_init_reset_methods(dev
);
2486 * This is the equivalent of pci_host_bridge_msi_domain() that acts on
2487 * devices. Firmware interfaces that can select the MSI domain on a
2488 * per-device basis should be called from here.
2490 static struct irq_domain
*pci_dev_msi_domain(struct pci_dev
*dev
)
2492 struct irq_domain
*d
;
2495 * If a domain has been set through the pcibios_add_device()
2496 * callback, then this is the one (platform code knows best).
2498 d
= dev_get_msi_domain(&dev
->dev
);
2503 * Let's see if we have a firmware interface able to provide
2506 d
= pci_msi_get_device_domain(dev
);
2513 static void pci_set_msi_domain(struct pci_dev
*dev
)
2515 struct irq_domain
*d
;
2518 * If the platform or firmware interfaces cannot supply a
2519 * device-specific MSI domain, then inherit the default domain
2520 * from the host bridge itself.
2522 d
= pci_dev_msi_domain(dev
);
2524 d
= dev_get_msi_domain(&dev
->bus
->dev
);
2526 dev_set_msi_domain(&dev
->dev
, d
);
2529 void pci_device_add(struct pci_dev
*dev
, struct pci_bus
*bus
)
2533 pci_configure_device(dev
);
2535 device_initialize(&dev
->dev
);
2536 dev
->dev
.release
= pci_release_dev
;
2538 set_dev_node(&dev
->dev
, pcibus_to_node(bus
));
2539 dev
->dev
.dma_mask
= &dev
->dma_mask
;
2540 dev
->dev
.dma_parms
= &dev
->dma_parms
;
2541 dev
->dev
.coherent_dma_mask
= 0xffffffffull
;
2543 dma_set_max_seg_size(&dev
->dev
, 65536);
2544 dma_set_seg_boundary(&dev
->dev
, 0xffffffff);
2546 /* Fix up broken headers */
2547 pci_fixup_device(pci_fixup_header
, dev
);
2549 pci_reassigndev_resource_alignment(dev
);
2551 dev
->state_saved
= false;
2553 pci_init_capabilities(dev
);
2556 * Add the device to our list of discovered devices
2557 * and the bus list for fixup functions, etc.
2559 down_write(&pci_bus_sem
);
2560 list_add_tail(&dev
->bus_list
, &bus
->devices
);
2561 up_write(&pci_bus_sem
);
2563 ret
= pcibios_add_device(dev
);
2566 /* Set up MSI IRQ domain */
2567 pci_set_msi_domain(dev
);
2569 /* Notifier could use PCI capabilities */
2570 dev
->match_driver
= false;
2571 ret
= device_add(&dev
->dev
);
2575 struct pci_dev
*pci_scan_single_device(struct pci_bus
*bus
, int devfn
)
2577 struct pci_dev
*dev
;
2579 dev
= pci_get_slot(bus
, devfn
);
2585 dev
= pci_scan_device(bus
, devfn
);
2589 pci_device_add(dev
, bus
);
2593 EXPORT_SYMBOL(pci_scan_single_device
);
2595 static unsigned next_fn(struct pci_bus
*bus
, struct pci_dev
*dev
, unsigned fn
)
2601 if (pci_ari_enabled(bus
)) {
2604 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ARI
);
2608 pci_read_config_word(dev
, pos
+ PCI_ARI_CAP
, &cap
);
2609 next_fn
= PCI_ARI_CAP_NFN(cap
);
2611 return 0; /* protect against malformed list */
2616 /* dev may be NULL for non-contiguous multifunction devices */
2617 if (!dev
|| dev
->multifunction
)
2618 return (fn
+ 1) % 8;
2623 static int only_one_child(struct pci_bus
*bus
)
2625 struct pci_dev
*bridge
= bus
->self
;
2628 * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so
2629 * we scan for all possible devices, not just Device 0.
2631 if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS
))
2635 * A PCIe Downstream Port normally leads to a Link with only Device
2636 * 0 on it (PCIe spec r3.1, sec 7.3.1). As an optimization, scan
2637 * only for Device 0 in that situation.
2639 if (bridge
&& pci_is_pcie(bridge
) && pcie_downstream_port(bridge
))
2646 * pci_scan_slot - Scan a PCI slot on a bus for devices
2647 * @bus: PCI bus to scan
2648 * @devfn: slot number to scan (must have zero function)
2650 * Scan a PCI slot on the specified PCI bus for devices, adding
2651 * discovered devices to the @bus->devices list. New devices
2652 * will not have is_added set.
2654 * Returns the number of new devices found.
2656 int pci_scan_slot(struct pci_bus
*bus
, int devfn
)
2658 unsigned fn
, nr
= 0;
2659 struct pci_dev
*dev
;
2661 if (only_one_child(bus
) && (devfn
> 0))
2662 return 0; /* Already scanned the entire slot */
2664 dev
= pci_scan_single_device(bus
, devfn
);
2667 if (!pci_dev_is_added(dev
))
2670 for (fn
= next_fn(bus
, dev
, 0); fn
> 0; fn
= next_fn(bus
, dev
, fn
)) {
2671 dev
= pci_scan_single_device(bus
, devfn
+ fn
);
2673 if (!pci_dev_is_added(dev
))
2675 dev
->multifunction
= 1;
2679 /* Only one slot has PCIe device */
2680 if (bus
->self
&& nr
)
2681 pcie_aspm_init_link_state(bus
->self
);
2685 EXPORT_SYMBOL(pci_scan_slot
);
2687 static int pcie_find_smpss(struct pci_dev
*dev
, void *data
)
2691 if (!pci_is_pcie(dev
))
2695 * We don't have a way to change MPS settings on devices that have
2696 * drivers attached. A hot-added device might support only the minimum
2697 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
2698 * where devices may be hot-added, we limit the fabric MPS to 128 so
2699 * hot-added devices will work correctly.
2701 * However, if we hot-add a device to a slot directly below a Root
2702 * Port, it's impossible for there to be other existing devices below
2703 * the port. We don't limit the MPS in this case because we can
2704 * reconfigure MPS on both the Root Port and the hot-added device,
2705 * and there are no other devices involved.
2707 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
2709 if (dev
->is_hotplug_bridge
&&
2710 pci_pcie_type(dev
) != PCI_EXP_TYPE_ROOT_PORT
)
2713 if (*smpss
> dev
->pcie_mpss
)
2714 *smpss
= dev
->pcie_mpss
;
2719 static void pcie_write_mps(struct pci_dev
*dev
, int mps
)
2723 if (pcie_bus_config
== PCIE_BUS_PERFORMANCE
) {
2724 mps
= 128 << dev
->pcie_mpss
;
2726 if (pci_pcie_type(dev
) != PCI_EXP_TYPE_ROOT_PORT
&&
2730 * For "Performance", the assumption is made that
2731 * downstream communication will never be larger than
2732 * the MRRS. So, the MPS only needs to be configured
2733 * for the upstream communication. This being the case,
2734 * walk from the top down and set the MPS of the child
2735 * to that of the parent bus.
2737 * Configure the device MPS with the smaller of the
2738 * device MPSS or the bridge MPS (which is assumed to be
2739 * properly configured at this point to the largest
2740 * allowable MPS based on its parent bus).
2742 mps
= min(mps
, pcie_get_mps(dev
->bus
->self
));
2745 rc
= pcie_set_mps(dev
, mps
);
2747 pci_err(dev
, "Failed attempting to set the MPS\n");
2750 static void pcie_write_mrrs(struct pci_dev
*dev
)
2755 * In the "safe" case, do not configure the MRRS. There appear to be
2756 * issues with setting MRRS to 0 on a number of devices.
2758 if (pcie_bus_config
!= PCIE_BUS_PERFORMANCE
)
2762 * For max performance, the MRRS must be set to the largest supported
2763 * value. However, it cannot be configured larger than the MPS the
2764 * device or the bus can support. This should already be properly
2765 * configured by a prior call to pcie_write_mps().
2767 mrrs
= pcie_get_mps(dev
);
2770 * MRRS is a R/W register. Invalid values can be written, but a
2771 * subsequent read will verify if the value is acceptable or not.
2772 * If the MRRS value provided is not acceptable (e.g., too large),
2773 * shrink the value until it is acceptable to the HW.
2775 while (mrrs
!= pcie_get_readrq(dev
) && mrrs
>= 128) {
2776 rc
= pcie_set_readrq(dev
, mrrs
);
2780 pci_warn(dev
, "Failed attempting to set the MRRS\n");
2785 pci_err(dev
, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
2788 static int pcie_bus_configure_set(struct pci_dev
*dev
, void *data
)
2792 if (!pci_is_pcie(dev
))
2795 if (pcie_bus_config
== PCIE_BUS_TUNE_OFF
||
2796 pcie_bus_config
== PCIE_BUS_DEFAULT
)
2799 mps
= 128 << *(u8
*)data
;
2800 orig_mps
= pcie_get_mps(dev
);
2802 pcie_write_mps(dev
, mps
);
2803 pcie_write_mrrs(dev
);
2805 pci_info(dev
, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
2806 pcie_get_mps(dev
), 128 << dev
->pcie_mpss
,
2807 orig_mps
, pcie_get_readrq(dev
));
2813 * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down,
2814 * parents then children fashion. If this changes, then this code will not
2817 void pcie_bus_configure_settings(struct pci_bus
*bus
)
2824 if (!pci_is_pcie(bus
->self
))
2828 * FIXME - Peer to peer DMA is possible, though the endpoint would need
2829 * to be aware of the MPS of the destination. To work around this,
2830 * simply force the MPS of the entire system to the smallest possible.
2832 if (pcie_bus_config
== PCIE_BUS_PEER2PEER
)
2835 if (pcie_bus_config
== PCIE_BUS_SAFE
) {
2836 smpss
= bus
->self
->pcie_mpss
;
2838 pcie_find_smpss(bus
->self
, &smpss
);
2839 pci_walk_bus(bus
, pcie_find_smpss
, &smpss
);
2842 pcie_bus_configure_set(bus
->self
, &smpss
);
2843 pci_walk_bus(bus
, pcie_bus_configure_set
, &smpss
);
2845 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings
);
2848 * Called after each bus is probed, but before its children are examined. This
2849 * is marked as __weak because multiple architectures define it.
2851 void __weak
pcibios_fixup_bus(struct pci_bus
*bus
)
2853 /* nothing to do, expected to be removed in the future */
2857 * pci_scan_child_bus_extend() - Scan devices below a bus
2858 * @bus: Bus to scan for devices
2859 * @available_buses: Total number of buses available (%0 does not try to
2860 * extend beyond the minimal)
2862 * Scans devices below @bus including subordinate buses. Returns new
2863 * subordinate number including all the found devices. Passing
2864 * @available_buses causes the remaining bus space to be distributed
2865 * equally between hotplug-capable bridges to allow future extension of the
2868 static unsigned int pci_scan_child_bus_extend(struct pci_bus
*bus
,
2869 unsigned int available_buses
)
2871 unsigned int used_buses
, normal_bridges
= 0, hotplug_bridges
= 0;
2872 unsigned int start
= bus
->busn_res
.start
;
2873 unsigned int devfn
, fn
, cmax
, max
= start
;
2874 struct pci_dev
*dev
;
2877 dev_dbg(&bus
->dev
, "scanning bus\n");
2879 /* Go find them, Rover! */
2880 for (devfn
= 0; devfn
< 256; devfn
+= 8) {
2881 nr_devs
= pci_scan_slot(bus
, devfn
);
2884 * The Jailhouse hypervisor may pass individual functions of a
2885 * multi-function device to a guest without passing function 0.
2886 * Look for them as well.
2888 if (jailhouse_paravirt() && nr_devs
== 0) {
2889 for (fn
= 1; fn
< 8; fn
++) {
2890 dev
= pci_scan_single_device(bus
, devfn
+ fn
);
2892 dev
->multifunction
= 1;
2897 /* Reserve buses for SR-IOV capability */
2898 used_buses
= pci_iov_bus_range(bus
);
2902 * After performing arch-dependent fixup of the bus, look behind
2903 * all PCI-to-PCI bridges on this bus.
2905 if (!bus
->is_added
) {
2906 dev_dbg(&bus
->dev
, "fixups for bus\n");
2907 pcibios_fixup_bus(bus
);
2912 * Calculate how many hotplug bridges and normal bridges there
2913 * are on this bus. We will distribute the additional available
2914 * buses between hotplug bridges.
2916 for_each_pci_bridge(dev
, bus
) {
2917 if (dev
->is_hotplug_bridge
)
2924 * Scan bridges that are already configured. We don't touch them
2925 * unless they are misconfigured (which will be done in the second
2928 for_each_pci_bridge(dev
, bus
) {
2930 max
= pci_scan_bridge_extend(bus
, dev
, max
, 0, 0);
2933 * Reserve one bus for each bridge now to avoid extending
2934 * hotplug bridges too much during the second scan below.
2938 used_buses
+= cmax
- max
- 1;
2941 /* Scan bridges that need to be reconfigured */
2942 for_each_pci_bridge(dev
, bus
) {
2943 unsigned int buses
= 0;
2945 if (!hotplug_bridges
&& normal_bridges
== 1) {
2948 * There is only one bridge on the bus (upstream
2949 * port) so it gets all available buses which it
2950 * can then distribute to the possible hotplug
2953 buses
= available_buses
;
2954 } else if (dev
->is_hotplug_bridge
) {
2957 * Distribute the extra buses between hotplug
2960 buses
= available_buses
/ hotplug_bridges
;
2961 buses
= min(buses
, available_buses
- used_buses
+ 1);
2965 max
= pci_scan_bridge_extend(bus
, dev
, cmax
, buses
, 1);
2966 /* One bus is already accounted so don't add it again */
2968 used_buses
+= max
- cmax
- 1;
2972 * Make sure a hotplug bridge has at least the minimum requested
2973 * number of buses but allow it to grow up to the maximum available
2974 * bus number of there is room.
2976 if (bus
->self
&& bus
->self
->is_hotplug_bridge
) {
2977 used_buses
= max_t(unsigned int, available_buses
,
2978 pci_hotplug_bus_size
- 1);
2979 if (max
- start
< used_buses
) {
2980 max
= start
+ used_buses
;
2982 /* Do not allocate more buses than we have room left */
2983 if (max
> bus
->busn_res
.end
)
2984 max
= bus
->busn_res
.end
;
2986 dev_dbg(&bus
->dev
, "%pR extended by %#02x\n",
2987 &bus
->busn_res
, max
- start
);
2992 * We've scanned the bus and so we know all about what's on
2993 * the other side of any bridges that may be on this bus plus
2996 * Return how far we've got finding sub-buses.
2998 dev_dbg(&bus
->dev
, "bus scan returning with max=%02x\n", max
);
3003 * pci_scan_child_bus() - Scan devices below a bus
3004 * @bus: Bus to scan for devices
3006 * Scans devices below @bus including subordinate buses. Returns new
3007 * subordinate number including all the found devices.
3009 unsigned int pci_scan_child_bus(struct pci_bus
*bus
)
3011 return pci_scan_child_bus_extend(bus
, 0);
3013 EXPORT_SYMBOL_GPL(pci_scan_child_bus
);
3016 * pcibios_root_bridge_prepare - Platform-specific host bridge setup
3017 * @bridge: Host bridge to set up
3019 * Default empty implementation. Replace with an architecture-specific setup
3020 * routine, if necessary.
3022 int __weak
pcibios_root_bridge_prepare(struct pci_host_bridge
*bridge
)
3027 void __weak
pcibios_add_bus(struct pci_bus
*bus
)
3031 void __weak
pcibios_remove_bus(struct pci_bus
*bus
)
3035 struct pci_bus
*pci_create_root_bus(struct device
*parent
, int bus
,
3036 struct pci_ops
*ops
, void *sysdata
, struct list_head
*resources
)
3039 struct pci_host_bridge
*bridge
;
3041 bridge
= pci_alloc_host_bridge(0);
3045 bridge
->dev
.parent
= parent
;
3047 list_splice_init(resources
, &bridge
->windows
);
3048 bridge
->sysdata
= sysdata
;
3049 bridge
->busnr
= bus
;
3052 error
= pci_register_host_bridge(bridge
);
3059 put_device(&bridge
->dev
);
3062 EXPORT_SYMBOL_GPL(pci_create_root_bus
);
3064 int pci_host_probe(struct pci_host_bridge
*bridge
)
3066 struct pci_bus
*bus
, *child
;
3069 ret
= pci_scan_root_bus_bridge(bridge
);
3071 dev_err(bridge
->dev
.parent
, "Scanning root bridge failed");
3078 * We insert PCI resources into the iomem_resource and
3079 * ioport_resource trees in either pci_bus_claim_resources()
3080 * or pci_bus_assign_resources().
3082 if (pci_has_flag(PCI_PROBE_ONLY
)) {
3083 pci_bus_claim_resources(bus
);
3085 pci_bus_size_bridges(bus
);
3086 pci_bus_assign_resources(bus
);
3088 list_for_each_entry(child
, &bus
->children
, node
)
3089 pcie_bus_configure_settings(child
);
3092 pci_bus_add_devices(bus
);
3095 EXPORT_SYMBOL_GPL(pci_host_probe
);
3097 int pci_bus_insert_busn_res(struct pci_bus
*b
, int bus
, int bus_max
)
3099 struct resource
*res
= &b
->busn_res
;
3100 struct resource
*parent_res
, *conflict
;
3104 res
->flags
= IORESOURCE_BUS
;
3106 if (!pci_is_root_bus(b
))
3107 parent_res
= &b
->parent
->busn_res
;
3109 parent_res
= get_pci_domain_busn_res(pci_domain_nr(b
));
3110 res
->flags
|= IORESOURCE_PCI_FIXED
;
3113 conflict
= request_resource_conflict(parent_res
, res
);
3117 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
3118 res
, pci_is_root_bus(b
) ? "domain " : "",
3119 parent_res
, conflict
->name
, conflict
);
3121 return conflict
== NULL
;
3124 int pci_bus_update_busn_res_end(struct pci_bus
*b
, int bus_max
)
3126 struct resource
*res
= &b
->busn_res
;
3127 struct resource old_res
= *res
;
3128 resource_size_t size
;
3131 if (res
->start
> bus_max
)
3134 size
= bus_max
- res
->start
+ 1;
3135 ret
= adjust_resource(res
, res
->start
, size
);
3136 dev_info(&b
->dev
, "busn_res: %pR end %s updated to %02x\n",
3137 &old_res
, ret
? "can not be" : "is", bus_max
);
3139 if (!ret
&& !res
->parent
)
3140 pci_bus_insert_busn_res(b
, res
->start
, res
->end
);
3145 void pci_bus_release_busn_res(struct pci_bus
*b
)
3147 struct resource
*res
= &b
->busn_res
;
3150 if (!res
->flags
|| !res
->parent
)
3153 ret
= release_resource(res
);
3154 dev_info(&b
->dev
, "busn_res: %pR %s released\n",
3155 res
, ret
? "can not be" : "is");
3158 int pci_scan_root_bus_bridge(struct pci_host_bridge
*bridge
)
3160 struct resource_entry
*window
;
3168 resource_list_for_each_entry(window
, &bridge
->windows
)
3169 if (window
->res
->flags
& IORESOURCE_BUS
) {
3170 bridge
->busnr
= window
->res
->start
;
3175 ret
= pci_register_host_bridge(bridge
);
3180 bus
= bridge
->busnr
;
3184 "No busn resource found for root bus, will use [bus %02x-ff]\n",
3186 pci_bus_insert_busn_res(b
, bus
, 255);
3189 max
= pci_scan_child_bus(b
);
3192 pci_bus_update_busn_res_end(b
, max
);
3196 EXPORT_SYMBOL(pci_scan_root_bus_bridge
);
3198 struct pci_bus
*pci_scan_root_bus(struct device
*parent
, int bus
,
3199 struct pci_ops
*ops
, void *sysdata
, struct list_head
*resources
)
3201 struct resource_entry
*window
;
3206 resource_list_for_each_entry(window
, resources
)
3207 if (window
->res
->flags
& IORESOURCE_BUS
) {
3212 b
= pci_create_root_bus(parent
, bus
, ops
, sysdata
, resources
);
3218 "No busn resource found for root bus, will use [bus %02x-ff]\n",
3220 pci_bus_insert_busn_res(b
, bus
, 255);
3223 max
= pci_scan_child_bus(b
);
3226 pci_bus_update_busn_res_end(b
, max
);
3230 EXPORT_SYMBOL(pci_scan_root_bus
);
3232 struct pci_bus
*pci_scan_bus(int bus
, struct pci_ops
*ops
,
3235 LIST_HEAD(resources
);
3238 pci_add_resource(&resources
, &ioport_resource
);
3239 pci_add_resource(&resources
, &iomem_resource
);
3240 pci_add_resource(&resources
, &busn_resource
);
3241 b
= pci_create_root_bus(NULL
, bus
, ops
, sysdata
, &resources
);
3243 pci_scan_child_bus(b
);
3245 pci_free_resource_list(&resources
);
3249 EXPORT_SYMBOL(pci_scan_bus
);
3252 * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices
3253 * @bridge: PCI bridge for the bus to scan
3255 * Scan a PCI bus and child buses for new devices, add them,
3256 * and enable them, resizing bridge mmio/io resource if necessary
3257 * and possible. The caller must ensure the child devices are already
3258 * removed for resizing to occur.
3260 * Returns the max number of subordinate bus discovered.
3262 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev
*bridge
)
3265 struct pci_bus
*bus
= bridge
->subordinate
;
3267 max
= pci_scan_child_bus(bus
);
3269 pci_assign_unassigned_bridge_resources(bridge
);
3271 pci_bus_add_devices(bus
);
3277 * pci_rescan_bus - Scan a PCI bus for devices
3278 * @bus: PCI bus to scan
3280 * Scan a PCI bus and child buses for new devices, add them,
3283 * Returns the max number of subordinate bus discovered.
3285 unsigned int pci_rescan_bus(struct pci_bus
*bus
)
3289 max
= pci_scan_child_bus(bus
);
3290 pci_assign_unassigned_bus_resources(bus
);
3291 pci_bus_add_devices(bus
);
3295 EXPORT_SYMBOL_GPL(pci_rescan_bus
);
3298 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
3299 * routines should always be executed under this mutex.
3301 static DEFINE_MUTEX(pci_rescan_remove_lock
);
3303 void pci_lock_rescan_remove(void)
3305 mutex_lock(&pci_rescan_remove_lock
);
3307 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove
);
3309 void pci_unlock_rescan_remove(void)
3311 mutex_unlock(&pci_rescan_remove_lock
);
3313 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove
);
3315 static int __init
pci_sort_bf_cmp(const struct device
*d_a
,
3316 const struct device
*d_b
)
3318 const struct pci_dev
*a
= to_pci_dev(d_a
);
3319 const struct pci_dev
*b
= to_pci_dev(d_b
);
3321 if (pci_domain_nr(a
->bus
) < pci_domain_nr(b
->bus
)) return -1;
3322 else if (pci_domain_nr(a
->bus
) > pci_domain_nr(b
->bus
)) return 1;
3324 if (a
->bus
->number
< b
->bus
->number
) return -1;
3325 else if (a
->bus
->number
> b
->bus
->number
) return 1;
3327 if (a
->devfn
< b
->devfn
) return -1;
3328 else if (a
->devfn
> b
->devfn
) return 1;
3333 void __init
pci_sort_breadthfirst(void)
3335 bus_sort_breadthfirst(&pci_bus_type
, &pci_sort_bf_cmp
);
3338 int pci_hp_add_bridge(struct pci_dev
*dev
)
3340 struct pci_bus
*parent
= dev
->bus
;
3341 int busnr
, start
= parent
->busn_res
.start
;
3342 unsigned int available_buses
= 0;
3343 int end
= parent
->busn_res
.end
;
3345 for (busnr
= start
; busnr
<= end
; busnr
++) {
3346 if (!pci_find_bus(pci_domain_nr(parent
), busnr
))
3349 if (busnr
-- > end
) {
3350 pci_err(dev
, "No bus number available for hot-added bridge\n");
3354 /* Scan bridges that are already configured */
3355 busnr
= pci_scan_bridge(parent
, dev
, busnr
, 0);
3358 * Distribute the available bus numbers between hotplug-capable
3359 * bridges to make extending the chain later possible.
3361 available_buses
= end
- busnr
;
3363 /* Scan bridges that need to be reconfigured */
3364 pci_scan_bridge_extend(parent
, dev
, busnr
, available_buses
, 1);
3366 if (!dev
->subordinate
)
3371 EXPORT_SYMBOL_GPL(pci_hp_add_bridge
);