2 * probe.c - PCI detection and setup code
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
9 #include <linux/pci_hotplug.h>
10 #include <linux/slab.h>
11 #include <linux/module.h>
12 #include <linux/cpumask.h>
13 #include <linux/pci-aspm.h>
14 #include <asm-generic/pci-bridge.h>
17 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
18 #define CARDBUS_RESERVE_BUSNR 3
20 static struct resource busn_resource
= {
24 .flags
= IORESOURCE_BUS
,
27 /* Ugh. Need to stop exporting this to modules. */
28 LIST_HEAD(pci_root_buses
);
29 EXPORT_SYMBOL(pci_root_buses
);
31 static LIST_HEAD(pci_domain_busn_res_list
);
33 struct pci_domain_busn_res
{
34 struct list_head list
;
39 static struct resource
*get_pci_domain_busn_res(int domain_nr
)
41 struct pci_domain_busn_res
*r
;
43 list_for_each_entry(r
, &pci_domain_busn_res_list
, list
)
44 if (r
->domain_nr
== domain_nr
)
47 r
= kzalloc(sizeof(*r
), GFP_KERNEL
);
51 r
->domain_nr
= domain_nr
;
54 r
->res
.flags
= IORESOURCE_BUS
| IORESOURCE_PCI_FIXED
;
56 list_add_tail(&r
->list
, &pci_domain_busn_res_list
);
61 static int find_anything(struct device
*dev
, void *data
)
67 * Some device drivers need know if pci is initiated.
68 * Basically, we think pci is not initiated when there
69 * is no device to be found on the pci_bus_type.
71 int no_pci_devices(void)
76 dev
= bus_find_device(&pci_bus_type
, NULL
, NULL
, find_anything
);
77 no_devices
= (dev
== NULL
);
81 EXPORT_SYMBOL(no_pci_devices
);
86 static void release_pcibus_dev(struct device
*dev
)
88 struct pci_bus
*pci_bus
= to_pci_bus(dev
);
91 put_device(pci_bus
->bridge
);
92 pci_bus_remove_resources(pci_bus
);
93 pci_release_bus_of_node(pci_bus
);
97 static struct class pcibus_class
= {
99 .dev_release
= &release_pcibus_dev
,
100 .dev_groups
= pcibus_groups
,
103 static int __init
pcibus_class_init(void)
105 return class_register(&pcibus_class
);
107 postcore_initcall(pcibus_class_init
);
109 static u64
pci_size(u64 base
, u64 maxbase
, u64 mask
)
111 u64 size
= mask
& maxbase
; /* Find the significant bits */
115 /* Get the lowest of them to find the decode size, and
116 from that the extent. */
117 size
= (size
& ~(size
-1)) - 1;
119 /* base == maxbase can be valid only if the BAR has
120 already been programmed with all 1s. */
121 if (base
== maxbase
&& ((base
| size
) & mask
) != mask
)
127 static inline unsigned long decode_bar(struct pci_dev
*dev
, u32 bar
)
132 if ((bar
& PCI_BASE_ADDRESS_SPACE
) == PCI_BASE_ADDRESS_SPACE_IO
) {
133 flags
= bar
& ~PCI_BASE_ADDRESS_IO_MASK
;
134 flags
|= IORESOURCE_IO
;
138 flags
= bar
& ~PCI_BASE_ADDRESS_MEM_MASK
;
139 flags
|= IORESOURCE_MEM
;
140 if (flags
& PCI_BASE_ADDRESS_MEM_PREFETCH
)
141 flags
|= IORESOURCE_PREFETCH
;
143 mem_type
= bar
& PCI_BASE_ADDRESS_MEM_TYPE_MASK
;
145 case PCI_BASE_ADDRESS_MEM_TYPE_32
:
147 case PCI_BASE_ADDRESS_MEM_TYPE_1M
:
148 /* 1M mem BAR treated as 32-bit BAR */
150 case PCI_BASE_ADDRESS_MEM_TYPE_64
:
151 flags
|= IORESOURCE_MEM_64
;
154 /* mem unknown type treated as 32-bit BAR */
160 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
163 * pci_read_base - read a PCI BAR
164 * @dev: the PCI device
165 * @type: type of the BAR
166 * @res: resource buffer to be filled in
167 * @pos: BAR position in the config space
169 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
171 int __pci_read_base(struct pci_dev
*dev
, enum pci_bar_type type
,
172 struct resource
*res
, unsigned int pos
)
175 u64 l64
, sz64
, mask64
;
177 struct pci_bus_region region
, inverted_region
;
178 bool bar_too_big
= false, bar_too_high
= false, bar_invalid
= false;
180 mask
= type
? PCI_ROM_ADDRESS_MASK
: ~0;
182 /* No printks while decoding is disabled! */
183 if (!dev
->mmio_always_on
) {
184 pci_read_config_word(dev
, PCI_COMMAND
, &orig_cmd
);
185 if (orig_cmd
& PCI_COMMAND_DECODE_ENABLE
) {
186 pci_write_config_word(dev
, PCI_COMMAND
,
187 orig_cmd
& ~PCI_COMMAND_DECODE_ENABLE
);
191 res
->name
= pci_name(dev
);
193 pci_read_config_dword(dev
, pos
, &l
);
194 pci_write_config_dword(dev
, pos
, l
| mask
);
195 pci_read_config_dword(dev
, pos
, &sz
);
196 pci_write_config_dword(dev
, pos
, l
);
199 * All bits set in sz means the device isn't working properly.
200 * If the BAR isn't implemented, all bits must be 0. If it's a
201 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
204 if (!sz
|| sz
== 0xffffffff)
208 * I don't know how l can have all bits set. Copied from old code.
209 * Maybe it fixes a bug on some ancient platform.
214 if (type
== pci_bar_unknown
) {
215 res
->flags
= decode_bar(dev
, l
);
216 res
->flags
|= IORESOURCE_SIZEALIGN
;
217 if (res
->flags
& IORESOURCE_IO
) {
218 l
&= PCI_BASE_ADDRESS_IO_MASK
;
219 mask
= PCI_BASE_ADDRESS_IO_MASK
& (u32
) IO_SPACE_LIMIT
;
221 l
&= PCI_BASE_ADDRESS_MEM_MASK
;
222 mask
= (u32
)PCI_BASE_ADDRESS_MEM_MASK
;
225 res
->flags
|= (l
& IORESOURCE_ROM_ENABLE
);
226 l
&= PCI_ROM_ADDRESS_MASK
;
227 mask
= (u32
)PCI_ROM_ADDRESS_MASK
;
230 if (res
->flags
& IORESOURCE_MEM_64
) {
233 mask64
= mask
| (u64
)~0 << 32;
235 pci_read_config_dword(dev
, pos
+ 4, &l
);
236 pci_write_config_dword(dev
, pos
+ 4, ~0);
237 pci_read_config_dword(dev
, pos
+ 4, &sz
);
238 pci_write_config_dword(dev
, pos
+ 4, l
);
240 l64
|= ((u64
)l
<< 32);
241 sz64
|= ((u64
)sz
<< 32);
243 sz64
= pci_size(l64
, sz64
, mask64
);
248 if ((sizeof(dma_addr_t
) < 8 || sizeof(resource_size_t
) < 8) &&
249 sz64
> 0x100000000ULL
) {
250 res
->flags
|= IORESOURCE_UNSET
| IORESOURCE_DISABLED
;
257 if ((sizeof(dma_addr_t
) < 8) && l
) {
258 /* Above 32-bit boundary; try to reallocate */
259 res
->flags
|= IORESOURCE_UNSET
;
266 region
.end
= l64
+ sz64
;
269 sz
= pci_size(l
, sz
, mask
);
278 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
279 pcibios_resource_to_bus(dev
->bus
, &inverted_region
, res
);
282 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
283 * the corresponding resource address (the physical address used by
284 * the CPU. Converting that resource address back to a bus address
285 * should yield the original BAR value:
287 * resource_to_bus(bus_to_resource(A)) == A
289 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
290 * be claimed by the device.
292 if (inverted_region
.start
!= region
.start
) {
293 res
->flags
|= IORESOURCE_UNSET
;
295 res
->end
= region
.end
- region
.start
;
305 if (!dev
->mmio_always_on
&&
306 (orig_cmd
& PCI_COMMAND_DECODE_ENABLE
))
307 pci_write_config_word(dev
, PCI_COMMAND
, orig_cmd
);
310 dev_err(&dev
->dev
, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
311 pos
, (unsigned long long) sz64
);
313 dev_info(&dev
->dev
, "reg 0x%x: can't handle BAR above 4G (bus address %#010llx)\n",
314 pos
, (unsigned long long) l64
);
316 dev_info(&dev
->dev
, "reg 0x%x: initial BAR value %#010llx invalid\n",
317 pos
, (unsigned long long) region
.start
);
319 dev_printk(KERN_DEBUG
, &dev
->dev
, "reg 0x%x: %pR\n", pos
, res
);
321 return (res
->flags
& IORESOURCE_MEM_64
) ? 1 : 0;
324 static void pci_read_bases(struct pci_dev
*dev
, unsigned int howmany
, int rom
)
326 unsigned int pos
, reg
;
328 for (pos
= 0; pos
< howmany
; pos
++) {
329 struct resource
*res
= &dev
->resource
[pos
];
330 reg
= PCI_BASE_ADDRESS_0
+ (pos
<< 2);
331 pos
+= __pci_read_base(dev
, pci_bar_unknown
, res
, reg
);
335 struct resource
*res
= &dev
->resource
[PCI_ROM_RESOURCE
];
336 dev
->rom_base_reg
= rom
;
337 res
->flags
= IORESOURCE_MEM
| IORESOURCE_PREFETCH
|
338 IORESOURCE_READONLY
| IORESOURCE_CACHEABLE
|
339 IORESOURCE_SIZEALIGN
;
340 __pci_read_base(dev
, pci_bar_mem32
, res
, rom
);
344 static void pci_read_bridge_io(struct pci_bus
*child
)
346 struct pci_dev
*dev
= child
->self
;
347 u8 io_base_lo
, io_limit_lo
;
348 unsigned long io_mask
, io_granularity
, base
, limit
;
349 struct pci_bus_region region
;
350 struct resource
*res
;
352 io_mask
= PCI_IO_RANGE_MASK
;
353 io_granularity
= 0x1000;
354 if (dev
->io_window_1k
) {
355 /* Support 1K I/O space granularity */
356 io_mask
= PCI_IO_1K_RANGE_MASK
;
357 io_granularity
= 0x400;
360 res
= child
->resource
[0];
361 pci_read_config_byte(dev
, PCI_IO_BASE
, &io_base_lo
);
362 pci_read_config_byte(dev
, PCI_IO_LIMIT
, &io_limit_lo
);
363 base
= (io_base_lo
& io_mask
) << 8;
364 limit
= (io_limit_lo
& io_mask
) << 8;
366 if ((io_base_lo
& PCI_IO_RANGE_TYPE_MASK
) == PCI_IO_RANGE_TYPE_32
) {
367 u16 io_base_hi
, io_limit_hi
;
369 pci_read_config_word(dev
, PCI_IO_BASE_UPPER16
, &io_base_hi
);
370 pci_read_config_word(dev
, PCI_IO_LIMIT_UPPER16
, &io_limit_hi
);
371 base
|= ((unsigned long) io_base_hi
<< 16);
372 limit
|= ((unsigned long) io_limit_hi
<< 16);
376 res
->flags
= (io_base_lo
& PCI_IO_RANGE_TYPE_MASK
) | IORESOURCE_IO
;
378 region
.end
= limit
+ io_granularity
- 1;
379 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
380 dev_printk(KERN_DEBUG
, &dev
->dev
, " bridge window %pR\n", res
);
384 static void pci_read_bridge_mmio(struct pci_bus
*child
)
386 struct pci_dev
*dev
= child
->self
;
387 u16 mem_base_lo
, mem_limit_lo
;
388 unsigned long base
, limit
;
389 struct pci_bus_region region
;
390 struct resource
*res
;
392 res
= child
->resource
[1];
393 pci_read_config_word(dev
, PCI_MEMORY_BASE
, &mem_base_lo
);
394 pci_read_config_word(dev
, PCI_MEMORY_LIMIT
, &mem_limit_lo
);
395 base
= ((unsigned long) mem_base_lo
& PCI_MEMORY_RANGE_MASK
) << 16;
396 limit
= ((unsigned long) mem_limit_lo
& PCI_MEMORY_RANGE_MASK
) << 16;
398 res
->flags
= (mem_base_lo
& PCI_MEMORY_RANGE_TYPE_MASK
) | IORESOURCE_MEM
;
400 region
.end
= limit
+ 0xfffff;
401 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
402 dev_printk(KERN_DEBUG
, &dev
->dev
, " bridge window %pR\n", res
);
406 static void pci_read_bridge_mmio_pref(struct pci_bus
*child
)
408 struct pci_dev
*dev
= child
->self
;
409 u16 mem_base_lo
, mem_limit_lo
;
411 dma_addr_t base
, limit
;
412 struct pci_bus_region region
;
413 struct resource
*res
;
415 res
= child
->resource
[2];
416 pci_read_config_word(dev
, PCI_PREF_MEMORY_BASE
, &mem_base_lo
);
417 pci_read_config_word(dev
, PCI_PREF_MEMORY_LIMIT
, &mem_limit_lo
);
418 base64
= (mem_base_lo
& PCI_PREF_RANGE_MASK
) << 16;
419 limit64
= (mem_limit_lo
& PCI_PREF_RANGE_MASK
) << 16;
421 if ((mem_base_lo
& PCI_PREF_RANGE_TYPE_MASK
) == PCI_PREF_RANGE_TYPE_64
) {
422 u32 mem_base_hi
, mem_limit_hi
;
424 pci_read_config_dword(dev
, PCI_PREF_BASE_UPPER32
, &mem_base_hi
);
425 pci_read_config_dword(dev
, PCI_PREF_LIMIT_UPPER32
, &mem_limit_hi
);
428 * Some bridges set the base > limit by default, and some
429 * (broken) BIOSes do not initialize them. If we find
430 * this, just assume they are not being used.
432 if (mem_base_hi
<= mem_limit_hi
) {
433 base64
|= (u64
) mem_base_hi
<< 32;
434 limit64
|= (u64
) mem_limit_hi
<< 32;
438 base
= (dma_addr_t
) base64
;
439 limit
= (dma_addr_t
) limit64
;
441 if (base
!= base64
) {
442 dev_err(&dev
->dev
, "can't handle bridge window above 4GB (bus address %#010llx)\n",
443 (unsigned long long) base64
);
448 res
->flags
= (mem_base_lo
& PCI_PREF_RANGE_TYPE_MASK
) |
449 IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
450 if (res
->flags
& PCI_PREF_RANGE_TYPE_64
)
451 res
->flags
|= IORESOURCE_MEM_64
;
453 region
.end
= limit
+ 0xfffff;
454 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
455 dev_printk(KERN_DEBUG
, &dev
->dev
, " bridge window %pR\n", res
);
459 void pci_read_bridge_bases(struct pci_bus
*child
)
461 struct pci_dev
*dev
= child
->self
;
462 struct resource
*res
;
465 if (pci_is_root_bus(child
)) /* It's a host bus, nothing to read */
468 dev_info(&dev
->dev
, "PCI bridge to %pR%s\n",
470 dev
->transparent
? " (subtractive decode)" : "");
472 pci_bus_remove_resources(child
);
473 for (i
= 0; i
< PCI_BRIDGE_RESOURCE_NUM
; i
++)
474 child
->resource
[i
] = &dev
->resource
[PCI_BRIDGE_RESOURCES
+i
];
476 pci_read_bridge_io(child
);
477 pci_read_bridge_mmio(child
);
478 pci_read_bridge_mmio_pref(child
);
480 if (dev
->transparent
) {
481 pci_bus_for_each_resource(child
->parent
, res
, i
) {
482 if (res
&& res
->flags
) {
483 pci_bus_add_resource(child
, res
,
484 PCI_SUBTRACTIVE_DECODE
);
485 dev_printk(KERN_DEBUG
, &dev
->dev
,
486 " bridge window %pR (subtractive decode)\n",
493 static struct pci_bus
*pci_alloc_bus(struct pci_bus
*parent
)
497 b
= kzalloc(sizeof(*b
), GFP_KERNEL
);
501 INIT_LIST_HEAD(&b
->node
);
502 INIT_LIST_HEAD(&b
->children
);
503 INIT_LIST_HEAD(&b
->devices
);
504 INIT_LIST_HEAD(&b
->slots
);
505 INIT_LIST_HEAD(&b
->resources
);
506 b
->max_bus_speed
= PCI_SPEED_UNKNOWN
;
507 b
->cur_bus_speed
= PCI_SPEED_UNKNOWN
;
508 #ifdef CONFIG_PCI_DOMAINS_GENERIC
510 b
->domain_nr
= parent
->domain_nr
;
515 static void pci_release_host_bridge_dev(struct device
*dev
)
517 struct pci_host_bridge
*bridge
= to_pci_host_bridge(dev
);
519 if (bridge
->release_fn
)
520 bridge
->release_fn(bridge
);
522 pci_free_resource_list(&bridge
->windows
);
527 static struct pci_host_bridge
*pci_alloc_host_bridge(struct pci_bus
*b
)
529 struct pci_host_bridge
*bridge
;
531 bridge
= kzalloc(sizeof(*bridge
), GFP_KERNEL
);
535 INIT_LIST_HEAD(&bridge
->windows
);
540 static const unsigned char pcix_bus_speed
[] = {
541 PCI_SPEED_UNKNOWN
, /* 0 */
542 PCI_SPEED_66MHz_PCIX
, /* 1 */
543 PCI_SPEED_100MHz_PCIX
, /* 2 */
544 PCI_SPEED_133MHz_PCIX
, /* 3 */
545 PCI_SPEED_UNKNOWN
, /* 4 */
546 PCI_SPEED_66MHz_PCIX_ECC
, /* 5 */
547 PCI_SPEED_100MHz_PCIX_ECC
, /* 6 */
548 PCI_SPEED_133MHz_PCIX_ECC
, /* 7 */
549 PCI_SPEED_UNKNOWN
, /* 8 */
550 PCI_SPEED_66MHz_PCIX_266
, /* 9 */
551 PCI_SPEED_100MHz_PCIX_266
, /* A */
552 PCI_SPEED_133MHz_PCIX_266
, /* B */
553 PCI_SPEED_UNKNOWN
, /* C */
554 PCI_SPEED_66MHz_PCIX_533
, /* D */
555 PCI_SPEED_100MHz_PCIX_533
, /* E */
556 PCI_SPEED_133MHz_PCIX_533
/* F */
559 const unsigned char pcie_link_speed
[] = {
560 PCI_SPEED_UNKNOWN
, /* 0 */
561 PCIE_SPEED_2_5GT
, /* 1 */
562 PCIE_SPEED_5_0GT
, /* 2 */
563 PCIE_SPEED_8_0GT
, /* 3 */
564 PCI_SPEED_UNKNOWN
, /* 4 */
565 PCI_SPEED_UNKNOWN
, /* 5 */
566 PCI_SPEED_UNKNOWN
, /* 6 */
567 PCI_SPEED_UNKNOWN
, /* 7 */
568 PCI_SPEED_UNKNOWN
, /* 8 */
569 PCI_SPEED_UNKNOWN
, /* 9 */
570 PCI_SPEED_UNKNOWN
, /* A */
571 PCI_SPEED_UNKNOWN
, /* B */
572 PCI_SPEED_UNKNOWN
, /* C */
573 PCI_SPEED_UNKNOWN
, /* D */
574 PCI_SPEED_UNKNOWN
, /* E */
575 PCI_SPEED_UNKNOWN
/* F */
578 void pcie_update_link_speed(struct pci_bus
*bus
, u16 linksta
)
580 bus
->cur_bus_speed
= pcie_link_speed
[linksta
& PCI_EXP_LNKSTA_CLS
];
582 EXPORT_SYMBOL_GPL(pcie_update_link_speed
);
584 static unsigned char agp_speeds
[] = {
592 static enum pci_bus_speed
agp_speed(int agp3
, int agpstat
)
598 else if (agpstat
& 2)
600 else if (agpstat
& 1)
612 return agp_speeds
[index
];
615 static void pci_set_bus_speed(struct pci_bus
*bus
)
617 struct pci_dev
*bridge
= bus
->self
;
620 pos
= pci_find_capability(bridge
, PCI_CAP_ID_AGP
);
622 pos
= pci_find_capability(bridge
, PCI_CAP_ID_AGP3
);
626 pci_read_config_dword(bridge
, pos
+ PCI_AGP_STATUS
, &agpstat
);
627 bus
->max_bus_speed
= agp_speed(agpstat
& 8, agpstat
& 7);
629 pci_read_config_dword(bridge
, pos
+ PCI_AGP_COMMAND
, &agpcmd
);
630 bus
->cur_bus_speed
= agp_speed(agpstat
& 8, agpcmd
& 7);
633 pos
= pci_find_capability(bridge
, PCI_CAP_ID_PCIX
);
636 enum pci_bus_speed max
;
638 pci_read_config_word(bridge
, pos
+ PCI_X_BRIDGE_SSTATUS
,
641 if (status
& PCI_X_SSTATUS_533MHZ
) {
642 max
= PCI_SPEED_133MHz_PCIX_533
;
643 } else if (status
& PCI_X_SSTATUS_266MHZ
) {
644 max
= PCI_SPEED_133MHz_PCIX_266
;
645 } else if (status
& PCI_X_SSTATUS_133MHZ
) {
646 if ((status
& PCI_X_SSTATUS_VERS
) == PCI_X_SSTATUS_V2
)
647 max
= PCI_SPEED_133MHz_PCIX_ECC
;
649 max
= PCI_SPEED_133MHz_PCIX
;
651 max
= PCI_SPEED_66MHz_PCIX
;
654 bus
->max_bus_speed
= max
;
655 bus
->cur_bus_speed
= pcix_bus_speed
[
656 (status
& PCI_X_SSTATUS_FREQ
) >> 6];
661 if (pci_is_pcie(bridge
)) {
665 pcie_capability_read_dword(bridge
, PCI_EXP_LNKCAP
, &linkcap
);
666 bus
->max_bus_speed
= pcie_link_speed
[linkcap
& PCI_EXP_LNKCAP_SLS
];
668 pcie_capability_read_word(bridge
, PCI_EXP_LNKSTA
, &linksta
);
669 pcie_update_link_speed(bus
, linksta
);
673 static struct pci_bus
*pci_alloc_child_bus(struct pci_bus
*parent
,
674 struct pci_dev
*bridge
, int busnr
)
676 struct pci_bus
*child
;
681 * Allocate a new bus, and inherit stuff from the parent..
683 child
= pci_alloc_bus(parent
);
687 child
->parent
= parent
;
688 child
->ops
= parent
->ops
;
689 child
->msi
= parent
->msi
;
690 child
->sysdata
= parent
->sysdata
;
691 child
->bus_flags
= parent
->bus_flags
;
693 /* initialize some portions of the bus device, but don't register it
694 * now as the parent is not properly set up yet.
696 child
->dev
.class = &pcibus_class
;
697 dev_set_name(&child
->dev
, "%04x:%02x", pci_domain_nr(child
), busnr
);
700 * Set up the primary, secondary and subordinate
703 child
->number
= child
->busn_res
.start
= busnr
;
704 child
->primary
= parent
->busn_res
.start
;
705 child
->busn_res
.end
= 0xff;
708 child
->dev
.parent
= parent
->bridge
;
712 child
->self
= bridge
;
713 child
->bridge
= get_device(&bridge
->dev
);
714 child
->dev
.parent
= child
->bridge
;
715 pci_set_bus_of_node(child
);
716 pci_set_bus_speed(child
);
718 /* Set up default resource pointers and names.. */
719 for (i
= 0; i
< PCI_BRIDGE_RESOURCE_NUM
; i
++) {
720 child
->resource
[i
] = &bridge
->resource
[PCI_BRIDGE_RESOURCES
+i
];
721 child
->resource
[i
]->name
= child
->name
;
723 bridge
->subordinate
= child
;
726 ret
= device_register(&child
->dev
);
729 pcibios_add_bus(child
);
731 /* Create legacy_io and legacy_mem files for this bus */
732 pci_create_legacy_files(child
);
737 struct pci_bus
*pci_add_new_bus(struct pci_bus
*parent
, struct pci_dev
*dev
,
740 struct pci_bus
*child
;
742 child
= pci_alloc_child_bus(parent
, dev
, busnr
);
744 down_write(&pci_bus_sem
);
745 list_add_tail(&child
->node
, &parent
->children
);
746 up_write(&pci_bus_sem
);
750 EXPORT_SYMBOL(pci_add_new_bus
);
752 static void pci_enable_crs(struct pci_dev
*pdev
)
756 /* Enable CRS Software Visibility if supported */
757 pcie_capability_read_word(pdev
, PCI_EXP_RTCAP
, &root_cap
);
758 if (root_cap
& PCI_EXP_RTCAP_CRSVIS
)
759 pcie_capability_set_word(pdev
, PCI_EXP_RTCTL
,
760 PCI_EXP_RTCTL_CRSSVE
);
764 * If it's a bridge, configure it and scan the bus behind it.
765 * For CardBus bridges, we don't scan behind as the devices will
766 * be handled by the bridge driver itself.
768 * We need to process bridges in two passes -- first we scan those
769 * already configured by the BIOS and after we are done with all of
770 * them, we proceed to assigning numbers to the remaining buses in
771 * order to avoid overlaps between old and new bus numbers.
773 int pci_scan_bridge(struct pci_bus
*bus
, struct pci_dev
*dev
, int max
, int pass
)
775 struct pci_bus
*child
;
776 int is_cardbus
= (dev
->hdr_type
== PCI_HEADER_TYPE_CARDBUS
);
779 u8 primary
, secondary
, subordinate
;
782 pci_read_config_dword(dev
, PCI_PRIMARY_BUS
, &buses
);
783 primary
= buses
& 0xFF;
784 secondary
= (buses
>> 8) & 0xFF;
785 subordinate
= (buses
>> 16) & 0xFF;
787 dev_dbg(&dev
->dev
, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
788 secondary
, subordinate
, pass
);
790 if (!primary
&& (primary
!= bus
->number
) && secondary
&& subordinate
) {
791 dev_warn(&dev
->dev
, "Primary bus is hard wired to 0\n");
792 primary
= bus
->number
;
795 /* Check if setup is sensible at all */
797 (primary
!= bus
->number
|| secondary
<= bus
->number
||
798 secondary
> subordinate
)) {
799 dev_info(&dev
->dev
, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
800 secondary
, subordinate
);
804 /* Disable MasterAbortMode during probing to avoid reporting
805 of bus errors (in some architectures) */
806 pci_read_config_word(dev
, PCI_BRIDGE_CONTROL
, &bctl
);
807 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
,
808 bctl
& ~PCI_BRIDGE_CTL_MASTER_ABORT
);
812 if ((secondary
|| subordinate
) && !pcibios_assign_all_busses() &&
813 !is_cardbus
&& !broken
) {
816 * Bus already configured by firmware, process it in the first
817 * pass and just note the configuration.
823 * The bus might already exist for two reasons: Either we are
824 * rescanning the bus or the bus is reachable through more than
825 * one bridge. The second case can happen with the i450NX
828 child
= pci_find_bus(pci_domain_nr(bus
), secondary
);
830 child
= pci_add_new_bus(bus
, dev
, secondary
);
833 child
->primary
= primary
;
834 pci_bus_insert_busn_res(child
, secondary
, subordinate
);
835 child
->bridge_ctl
= bctl
;
838 cmax
= pci_scan_child_bus(child
);
839 if (cmax
> subordinate
)
840 dev_warn(&dev
->dev
, "bridge has subordinate %02x but max busn %02x\n",
842 /* subordinate should equal child->busn_res.end */
843 if (subordinate
> max
)
847 * We need to assign a number to this bus which we always
848 * do in the second pass.
851 if (pcibios_assign_all_busses() || broken
|| is_cardbus
)
852 /* Temporarily disable forwarding of the
853 configuration cycles on all bridges in
854 this bus segment to avoid possible
855 conflicts in the second pass between two
856 bridges programmed with overlapping
858 pci_write_config_dword(dev
, PCI_PRIMARY_BUS
,
864 pci_write_config_word(dev
, PCI_STATUS
, 0xffff);
866 /* Prevent assigning a bus number that already exists.
867 * This can happen when a bridge is hot-plugged, so in
868 * this case we only re-scan this bus. */
869 child
= pci_find_bus(pci_domain_nr(bus
), max
+1);
871 child
= pci_add_new_bus(bus
, dev
, max
+1);
874 pci_bus_insert_busn_res(child
, max
+1, 0xff);
877 buses
= (buses
& 0xff000000)
878 | ((unsigned int)(child
->primary
) << 0)
879 | ((unsigned int)(child
->busn_res
.start
) << 8)
880 | ((unsigned int)(child
->busn_res
.end
) << 16);
883 * yenta.c forces a secondary latency timer of 176.
884 * Copy that behaviour here.
887 buses
&= ~0xff000000;
888 buses
|= CARDBUS_LATENCY_TIMER
<< 24;
892 * We need to blast all three values with a single write.
894 pci_write_config_dword(dev
, PCI_PRIMARY_BUS
, buses
);
897 child
->bridge_ctl
= bctl
;
898 max
= pci_scan_child_bus(child
);
901 * For CardBus bridges, we leave 4 bus numbers
902 * as cards with a PCI-to-PCI bridge can be
905 for (i
= 0; i
< CARDBUS_RESERVE_BUSNR
; i
++) {
906 struct pci_bus
*parent
= bus
;
907 if (pci_find_bus(pci_domain_nr(bus
),
910 while (parent
->parent
) {
911 if ((!pcibios_assign_all_busses()) &&
912 (parent
->busn_res
.end
> max
) &&
913 (parent
->busn_res
.end
<= max
+i
)) {
916 parent
= parent
->parent
;
920 * Often, there are two cardbus bridges
921 * -- try to leave one valid bus number
931 * Set the subordinate bus number to its real value.
933 pci_bus_update_busn_res_end(child
, max
);
934 pci_write_config_byte(dev
, PCI_SUBORDINATE_BUS
, max
);
938 (is_cardbus
? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
939 pci_domain_nr(bus
), child
->number
);
941 /* Has only triggered on CardBus, fixup is in yenta_socket */
942 while (bus
->parent
) {
943 if ((child
->busn_res
.end
> bus
->busn_res
.end
) ||
944 (child
->number
> bus
->busn_res
.end
) ||
945 (child
->number
< bus
->number
) ||
946 (child
->busn_res
.end
< bus
->number
)) {
947 dev_info(&child
->dev
, "%pR %s hidden behind%s bridge %s %pR\n",
949 (bus
->number
> child
->busn_res
.end
&&
950 bus
->busn_res
.end
< child
->number
) ?
951 "wholly" : "partially",
952 bus
->self
->transparent
? " transparent" : "",
960 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, bctl
);
964 EXPORT_SYMBOL(pci_scan_bridge
);
967 * Read interrupt line and base address registers.
968 * The architecture-dependent code can tweak these, of course.
970 static void pci_read_irq(struct pci_dev
*dev
)
974 pci_read_config_byte(dev
, PCI_INTERRUPT_PIN
, &irq
);
977 pci_read_config_byte(dev
, PCI_INTERRUPT_LINE
, &irq
);
981 void set_pcie_port_type(struct pci_dev
*pdev
)
986 pos
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
989 pdev
->pcie_cap
= pos
;
990 pci_read_config_word(pdev
, pos
+ PCI_EXP_FLAGS
, ®16
);
991 pdev
->pcie_flags_reg
= reg16
;
992 pci_read_config_word(pdev
, pos
+ PCI_EXP_DEVCAP
, ®16
);
993 pdev
->pcie_mpss
= reg16
& PCI_EXP_DEVCAP_PAYLOAD
;
996 void set_pcie_hotplug_bridge(struct pci_dev
*pdev
)
1000 pcie_capability_read_dword(pdev
, PCI_EXP_SLTCAP
, ®32
);
1001 if (reg32
& PCI_EXP_SLTCAP_HPC
)
1002 pdev
->is_hotplug_bridge
= 1;
1006 * pci_ext_cfg_is_aliased - is ext config space just an alias of std config?
1009 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1010 * when forwarding a type1 configuration request the bridge must check that
1011 * the extended register address field is zero. The bridge is not permitted
1012 * to forward the transactions and must handle it as an Unsupported Request.
1013 * Some bridges do not follow this rule and simply drop the extended register
1014 * bits, resulting in the standard config space being aliased, every 256
1015 * bytes across the entire configuration space. Test for this condition by
1016 * comparing the first dword of each potential alias to the vendor/device ID.
1018 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1019 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1021 static bool pci_ext_cfg_is_aliased(struct pci_dev
*dev
)
1023 #ifdef CONFIG_PCI_QUIRKS
1027 pci_read_config_dword(dev
, PCI_VENDOR_ID
, &header
);
1029 for (pos
= PCI_CFG_SPACE_SIZE
;
1030 pos
< PCI_CFG_SPACE_EXP_SIZE
; pos
+= PCI_CFG_SPACE_SIZE
) {
1031 if (pci_read_config_dword(dev
, pos
, &tmp
) != PCIBIOS_SUCCESSFUL
1043 * pci_cfg_space_size - get the configuration space size of the PCI device.
1046 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1047 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1048 * access it. Maybe we don't have a way to generate extended config space
1049 * accesses, or the device is behind a reverse Express bridge. So we try
1050 * reading the dword at 0x100 which must either be 0 or a valid extended
1051 * capability header.
1053 static int pci_cfg_space_size_ext(struct pci_dev
*dev
)
1056 int pos
= PCI_CFG_SPACE_SIZE
;
1058 if (pci_read_config_dword(dev
, pos
, &status
) != PCIBIOS_SUCCESSFUL
)
1060 if (status
== 0xffffffff || pci_ext_cfg_is_aliased(dev
))
1063 return PCI_CFG_SPACE_EXP_SIZE
;
1066 return PCI_CFG_SPACE_SIZE
;
1069 int pci_cfg_space_size(struct pci_dev
*dev
)
1075 class = dev
->class >> 8;
1076 if (class == PCI_CLASS_BRIDGE_HOST
)
1077 return pci_cfg_space_size_ext(dev
);
1079 if (!pci_is_pcie(dev
)) {
1080 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
1084 pci_read_config_dword(dev
, pos
+ PCI_X_STATUS
, &status
);
1085 if (!(status
& (PCI_X_STATUS_266MHZ
| PCI_X_STATUS_533MHZ
)))
1089 return pci_cfg_space_size_ext(dev
);
1092 return PCI_CFG_SPACE_SIZE
;
1095 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1098 * pci_setup_device - fill in class and map information of a device
1099 * @dev: the device structure to fill
1101 * Initialize the device structure with information about the device's
1102 * vendor,class,memory and IO-space addresses,IRQ lines etc.
1103 * Called at initialisation of the PCI subsystem and by CardBus services.
1104 * Returns 0 on success and negative if unknown type of device (not normal,
1105 * bridge or CardBus).
1107 int pci_setup_device(struct pci_dev
*dev
)
1111 struct pci_slot
*slot
;
1113 struct pci_bus_region region
;
1114 struct resource
*res
;
1116 if (pci_read_config_byte(dev
, PCI_HEADER_TYPE
, &hdr_type
))
1119 dev
->sysdata
= dev
->bus
->sysdata
;
1120 dev
->dev
.parent
= dev
->bus
->bridge
;
1121 dev
->dev
.bus
= &pci_bus_type
;
1122 dev
->hdr_type
= hdr_type
& 0x7f;
1123 dev
->multifunction
= !!(hdr_type
& 0x80);
1124 dev
->error_state
= pci_channel_io_normal
;
1125 set_pcie_port_type(dev
);
1127 list_for_each_entry(slot
, &dev
->bus
->slots
, list
)
1128 if (PCI_SLOT(dev
->devfn
) == slot
->number
)
1131 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1132 set this higher, assuming the system even supports it. */
1133 dev
->dma_mask
= 0xffffffff;
1135 dev_set_name(&dev
->dev
, "%04x:%02x:%02x.%d", pci_domain_nr(dev
->bus
),
1136 dev
->bus
->number
, PCI_SLOT(dev
->devfn
),
1137 PCI_FUNC(dev
->devfn
));
1139 pci_read_config_dword(dev
, PCI_CLASS_REVISION
, &class);
1140 dev
->revision
= class & 0xff;
1141 dev
->class = class >> 8; /* upper 3 bytes */
1143 dev_printk(KERN_DEBUG
, &dev
->dev
, "[%04x:%04x] type %02x class %#08x\n",
1144 dev
->vendor
, dev
->device
, dev
->hdr_type
, dev
->class);
1146 /* need to have dev->class ready */
1147 dev
->cfg_size
= pci_cfg_space_size(dev
);
1149 /* "Unknown power state" */
1150 dev
->current_state
= PCI_UNKNOWN
;
1152 /* Early fixups, before probing the BARs */
1153 pci_fixup_device(pci_fixup_early
, dev
);
1154 /* device class may be changed after fixup */
1155 class = dev
->class >> 8;
1157 switch (dev
->hdr_type
) { /* header type */
1158 case PCI_HEADER_TYPE_NORMAL
: /* standard header */
1159 if (class == PCI_CLASS_BRIDGE_PCI
)
1162 pci_read_bases(dev
, 6, PCI_ROM_ADDRESS
);
1163 pci_read_config_word(dev
, PCI_SUBSYSTEM_VENDOR_ID
, &dev
->subsystem_vendor
);
1164 pci_read_config_word(dev
, PCI_SUBSYSTEM_ID
, &dev
->subsystem_device
);
1167 * Do the ugly legacy mode stuff here rather than broken chip
1168 * quirk code. Legacy mode ATA controllers have fixed
1169 * addresses. These are not always echoed in BAR0-3, and
1170 * BAR0-3 in a few cases contain junk!
1172 if (class == PCI_CLASS_STORAGE_IDE
) {
1174 pci_read_config_byte(dev
, PCI_CLASS_PROG
, &progif
);
1175 if ((progif
& 1) == 0) {
1176 region
.start
= 0x1F0;
1178 res
= &dev
->resource
[0];
1179 res
->flags
= LEGACY_IO_RESOURCE
;
1180 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
1181 dev_info(&dev
->dev
, "legacy IDE quirk: reg 0x10: %pR\n",
1183 region
.start
= 0x3F6;
1185 res
= &dev
->resource
[1];
1186 res
->flags
= LEGACY_IO_RESOURCE
;
1187 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
1188 dev_info(&dev
->dev
, "legacy IDE quirk: reg 0x14: %pR\n",
1191 if ((progif
& 4) == 0) {
1192 region
.start
= 0x170;
1194 res
= &dev
->resource
[2];
1195 res
->flags
= LEGACY_IO_RESOURCE
;
1196 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
1197 dev_info(&dev
->dev
, "legacy IDE quirk: reg 0x18: %pR\n",
1199 region
.start
= 0x376;
1201 res
= &dev
->resource
[3];
1202 res
->flags
= LEGACY_IO_RESOURCE
;
1203 pcibios_bus_to_resource(dev
->bus
, res
, ®ion
);
1204 dev_info(&dev
->dev
, "legacy IDE quirk: reg 0x1c: %pR\n",
1210 case PCI_HEADER_TYPE_BRIDGE
: /* bridge header */
1211 if (class != PCI_CLASS_BRIDGE_PCI
)
1213 /* The PCI-to-PCI bridge spec requires that subtractive
1214 decoding (i.e. transparent) bridge must have programming
1215 interface code of 0x01. */
1217 dev
->transparent
= ((dev
->class & 0xff) == 1);
1218 pci_read_bases(dev
, 2, PCI_ROM_ADDRESS1
);
1219 set_pcie_hotplug_bridge(dev
);
1220 pos
= pci_find_capability(dev
, PCI_CAP_ID_SSVID
);
1222 pci_read_config_word(dev
, pos
+ PCI_SSVID_VENDOR_ID
, &dev
->subsystem_vendor
);
1223 pci_read_config_word(dev
, pos
+ PCI_SSVID_DEVICE_ID
, &dev
->subsystem_device
);
1227 case PCI_HEADER_TYPE_CARDBUS
: /* CardBus bridge header */
1228 if (class != PCI_CLASS_BRIDGE_CARDBUS
)
1231 pci_read_bases(dev
, 1, 0);
1232 pci_read_config_word(dev
, PCI_CB_SUBSYSTEM_VENDOR_ID
, &dev
->subsystem_vendor
);
1233 pci_read_config_word(dev
, PCI_CB_SUBSYSTEM_ID
, &dev
->subsystem_device
);
1236 default: /* unknown header */
1237 dev_err(&dev
->dev
, "unknown header type %02x, ignoring device\n",
1242 dev_err(&dev
->dev
, "ignoring class %#08x (doesn't match header type %02x)\n",
1243 dev
->class, dev
->hdr_type
);
1244 dev
->class = PCI_CLASS_NOT_DEFINED
;
1247 /* We found a fine healthy device, go go go... */
1251 static struct hpp_type0 pci_default_type0
= {
1253 .cache_line_size
= 8,
1254 .latency_timer
= 0x40,
1259 static void program_hpp_type0(struct pci_dev
*dev
, struct hpp_type0
*hpp
)
1261 u16 pci_cmd
, pci_bctl
;
1264 hpp
= &pci_default_type0
;
1266 if (hpp
->revision
> 1) {
1268 "PCI settings rev %d not supported; using defaults\n",
1270 hpp
= &pci_default_type0
;
1273 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, hpp
->cache_line_size
);
1274 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, hpp
->latency_timer
);
1275 pci_read_config_word(dev
, PCI_COMMAND
, &pci_cmd
);
1276 if (hpp
->enable_serr
)
1277 pci_cmd
|= PCI_COMMAND_SERR
;
1278 if (hpp
->enable_perr
)
1279 pci_cmd
|= PCI_COMMAND_PARITY
;
1280 pci_write_config_word(dev
, PCI_COMMAND
, pci_cmd
);
1282 /* Program bridge control value */
1283 if ((dev
->class >> 8) == PCI_CLASS_BRIDGE_PCI
) {
1284 pci_write_config_byte(dev
, PCI_SEC_LATENCY_TIMER
,
1285 hpp
->latency_timer
);
1286 pci_read_config_word(dev
, PCI_BRIDGE_CONTROL
, &pci_bctl
);
1287 if (hpp
->enable_serr
)
1288 pci_bctl
|= PCI_BRIDGE_CTL_SERR
;
1289 if (hpp
->enable_perr
)
1290 pci_bctl
|= PCI_BRIDGE_CTL_PARITY
;
1291 pci_write_config_word(dev
, PCI_BRIDGE_CONTROL
, pci_bctl
);
1295 static void program_hpp_type1(struct pci_dev
*dev
, struct hpp_type1
*hpp
)
1298 dev_warn(&dev
->dev
, "PCI-X settings not supported\n");
1301 static void program_hpp_type2(struct pci_dev
*dev
, struct hpp_type2
*hpp
)
1309 if (hpp
->revision
> 1) {
1310 dev_warn(&dev
->dev
, "PCIe settings rev %d not supported\n",
1316 * Don't allow _HPX to change MPS or MRRS settings. We manage
1317 * those to make sure they're consistent with the rest of the
1320 hpp
->pci_exp_devctl_and
|= PCI_EXP_DEVCTL_PAYLOAD
|
1321 PCI_EXP_DEVCTL_READRQ
;
1322 hpp
->pci_exp_devctl_or
&= ~(PCI_EXP_DEVCTL_PAYLOAD
|
1323 PCI_EXP_DEVCTL_READRQ
);
1325 /* Initialize Device Control Register */
1326 pcie_capability_clear_and_set_word(dev
, PCI_EXP_DEVCTL
,
1327 ~hpp
->pci_exp_devctl_and
, hpp
->pci_exp_devctl_or
);
1329 /* Initialize Link Control Register */
1330 if (pcie_cap_has_lnkctl(dev
))
1331 pcie_capability_clear_and_set_word(dev
, PCI_EXP_LNKCTL
,
1332 ~hpp
->pci_exp_lnkctl_and
, hpp
->pci_exp_lnkctl_or
);
1334 /* Find Advanced Error Reporting Enhanced Capability */
1335 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ERR
);
1339 /* Initialize Uncorrectable Error Mask Register */
1340 pci_read_config_dword(dev
, pos
+ PCI_ERR_UNCOR_MASK
, ®32
);
1341 reg32
= (reg32
& hpp
->unc_err_mask_and
) | hpp
->unc_err_mask_or
;
1342 pci_write_config_dword(dev
, pos
+ PCI_ERR_UNCOR_MASK
, reg32
);
1344 /* Initialize Uncorrectable Error Severity Register */
1345 pci_read_config_dword(dev
, pos
+ PCI_ERR_UNCOR_SEVER
, ®32
);
1346 reg32
= (reg32
& hpp
->unc_err_sever_and
) | hpp
->unc_err_sever_or
;
1347 pci_write_config_dword(dev
, pos
+ PCI_ERR_UNCOR_SEVER
, reg32
);
1349 /* Initialize Correctable Error Mask Register */
1350 pci_read_config_dword(dev
, pos
+ PCI_ERR_COR_MASK
, ®32
);
1351 reg32
= (reg32
& hpp
->cor_err_mask_and
) | hpp
->cor_err_mask_or
;
1352 pci_write_config_dword(dev
, pos
+ PCI_ERR_COR_MASK
, reg32
);
1354 /* Initialize Advanced Error Capabilities and Control Register */
1355 pci_read_config_dword(dev
, pos
+ PCI_ERR_CAP
, ®32
);
1356 reg32
= (reg32
& hpp
->adv_err_cap_and
) | hpp
->adv_err_cap_or
;
1357 pci_write_config_dword(dev
, pos
+ PCI_ERR_CAP
, reg32
);
1360 * FIXME: The following two registers are not supported yet.
1362 * o Secondary Uncorrectable Error Severity Register
1363 * o Secondary Uncorrectable Error Mask Register
1367 static void pci_configure_device(struct pci_dev
*dev
)
1369 struct hotplug_params hpp
;
1372 memset(&hpp
, 0, sizeof(hpp
));
1373 ret
= pci_get_hp_params(dev
, &hpp
);
1377 program_hpp_type2(dev
, hpp
.t2
);
1378 program_hpp_type1(dev
, hpp
.t1
);
1379 program_hpp_type0(dev
, hpp
.t0
);
1382 static void pci_release_capabilities(struct pci_dev
*dev
)
1384 pci_vpd_release(dev
);
1385 pci_iov_release(dev
);
1386 pci_free_cap_save_buffers(dev
);
1390 * pci_release_dev - free a pci device structure when all users of it are finished.
1391 * @dev: device that's been disconnected
1393 * Will be called only by the device core when all users of this pci device are
1396 static void pci_release_dev(struct device
*dev
)
1398 struct pci_dev
*pci_dev
;
1400 pci_dev
= to_pci_dev(dev
);
1401 pci_release_capabilities(pci_dev
);
1402 pci_release_of_node(pci_dev
);
1403 pcibios_release_device(pci_dev
);
1404 pci_bus_put(pci_dev
->bus
);
1405 kfree(pci_dev
->driver_override
);
1409 struct pci_dev
*pci_alloc_dev(struct pci_bus
*bus
)
1411 struct pci_dev
*dev
;
1413 dev
= kzalloc(sizeof(struct pci_dev
), GFP_KERNEL
);
1417 INIT_LIST_HEAD(&dev
->bus_list
);
1418 dev
->dev
.type
= &pci_dev_type
;
1419 dev
->bus
= pci_bus_get(bus
);
1423 EXPORT_SYMBOL(pci_alloc_dev
);
1425 bool pci_bus_read_dev_vendor_id(struct pci_bus
*bus
, int devfn
, u32
*l
,
1430 if (pci_bus_read_config_dword(bus
, devfn
, PCI_VENDOR_ID
, l
))
1433 /* some broken boards return 0 or ~0 if a slot is empty: */
1434 if (*l
== 0xffffffff || *l
== 0x00000000 ||
1435 *l
== 0x0000ffff || *l
== 0xffff0000)
1439 * Configuration Request Retry Status. Some root ports return the
1440 * actual device ID instead of the synthetic ID (0xFFFF) required
1441 * by the PCIe spec. Ignore the device ID and only check for
1444 while ((*l
& 0xffff) == 0x0001) {
1450 if (pci_bus_read_config_dword(bus
, devfn
, PCI_VENDOR_ID
, l
))
1452 /* Card hasn't responded in 60 seconds? Must be stuck. */
1453 if (delay
> crs_timeout
) {
1454 printk(KERN_WARNING
"pci %04x:%02x:%02x.%d: not responding\n",
1455 pci_domain_nr(bus
), bus
->number
, PCI_SLOT(devfn
),
1463 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id
);
1466 * Read the config data for a PCI device, sanity-check it
1467 * and fill in the dev structure...
1469 static struct pci_dev
*pci_scan_device(struct pci_bus
*bus
, int devfn
)
1471 struct pci_dev
*dev
;
1474 if (!pci_bus_read_dev_vendor_id(bus
, devfn
, &l
, 60*1000))
1477 dev
= pci_alloc_dev(bus
);
1482 dev
->vendor
= l
& 0xffff;
1483 dev
->device
= (l
>> 16) & 0xffff;
1485 pci_set_of_node(dev
);
1487 if (pci_setup_device(dev
)) {
1488 pci_bus_put(dev
->bus
);
1496 static void pci_init_capabilities(struct pci_dev
*dev
)
1498 /* MSI/MSI-X list */
1499 pci_msi_init_pci_dev(dev
);
1501 /* Buffers for saving PCIe and PCI-X capabilities */
1502 pci_allocate_cap_save_buffers(dev
);
1504 /* Power Management */
1507 /* Vital Product Data */
1508 pci_vpd_pci22_init(dev
);
1510 /* Alternative Routing-ID Forwarding */
1511 pci_configure_ari(dev
);
1513 /* Single Root I/O Virtualization */
1516 /* Enable ACS P2P upstream forwarding */
1517 pci_enable_acs(dev
);
1520 void pci_device_add(struct pci_dev
*dev
, struct pci_bus
*bus
)
1524 pci_configure_device(dev
);
1526 device_initialize(&dev
->dev
);
1527 dev
->dev
.release
= pci_release_dev
;
1529 set_dev_node(&dev
->dev
, pcibus_to_node(bus
));
1530 dev
->dev
.dma_mask
= &dev
->dma_mask
;
1531 dev
->dev
.dma_parms
= &dev
->dma_parms
;
1532 dev
->dev
.coherent_dma_mask
= 0xffffffffull
;
1534 pci_set_dma_max_seg_size(dev
, 65536);
1535 pci_set_dma_seg_boundary(dev
, 0xffffffff);
1537 /* Fix up broken headers */
1538 pci_fixup_device(pci_fixup_header
, dev
);
1540 /* moved out from quirk header fixup code */
1541 pci_reassigndev_resource_alignment(dev
);
1543 /* Clear the state_saved flag. */
1544 dev
->state_saved
= false;
1546 /* Initialize various capabilities */
1547 pci_init_capabilities(dev
);
1550 * Add the device to our list of discovered devices
1551 * and the bus list for fixup functions, etc.
1553 down_write(&pci_bus_sem
);
1554 list_add_tail(&dev
->bus_list
, &bus
->devices
);
1555 up_write(&pci_bus_sem
);
1557 ret
= pcibios_add_device(dev
);
1560 /* Notifier could use PCI capabilities */
1561 dev
->match_driver
= false;
1562 ret
= device_add(&dev
->dev
);
1566 struct pci_dev
*pci_scan_single_device(struct pci_bus
*bus
, int devfn
)
1568 struct pci_dev
*dev
;
1570 dev
= pci_get_slot(bus
, devfn
);
1576 dev
= pci_scan_device(bus
, devfn
);
1580 pci_device_add(dev
, bus
);
1584 EXPORT_SYMBOL(pci_scan_single_device
);
1586 static unsigned next_fn(struct pci_bus
*bus
, struct pci_dev
*dev
, unsigned fn
)
1592 if (pci_ari_enabled(bus
)) {
1595 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ARI
);
1599 pci_read_config_word(dev
, pos
+ PCI_ARI_CAP
, &cap
);
1600 next_fn
= PCI_ARI_CAP_NFN(cap
);
1602 return 0; /* protect against malformed list */
1607 /* dev may be NULL for non-contiguous multifunction devices */
1608 if (!dev
|| dev
->multifunction
)
1609 return (fn
+ 1) % 8;
1614 static int only_one_child(struct pci_bus
*bus
)
1616 struct pci_dev
*parent
= bus
->self
;
1618 if (!parent
|| !pci_is_pcie(parent
))
1620 if (pci_pcie_type(parent
) == PCI_EXP_TYPE_ROOT_PORT
)
1622 if (pci_pcie_type(parent
) == PCI_EXP_TYPE_DOWNSTREAM
&&
1623 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS
))
1629 * pci_scan_slot - scan a PCI slot on a bus for devices.
1630 * @bus: PCI bus to scan
1631 * @devfn: slot number to scan (must have zero function.)
1633 * Scan a PCI slot on the specified PCI bus for devices, adding
1634 * discovered devices to the @bus->devices list. New devices
1635 * will not have is_added set.
1637 * Returns the number of new devices found.
1639 int pci_scan_slot(struct pci_bus
*bus
, int devfn
)
1641 unsigned fn
, nr
= 0;
1642 struct pci_dev
*dev
;
1644 if (only_one_child(bus
) && (devfn
> 0))
1645 return 0; /* Already scanned the entire slot */
1647 dev
= pci_scan_single_device(bus
, devfn
);
1653 for (fn
= next_fn(bus
, dev
, 0); fn
> 0; fn
= next_fn(bus
, dev
, fn
)) {
1654 dev
= pci_scan_single_device(bus
, devfn
+ fn
);
1658 dev
->multifunction
= 1;
1662 /* only one slot has pcie device */
1663 if (bus
->self
&& nr
)
1664 pcie_aspm_init_link_state(bus
->self
);
1668 EXPORT_SYMBOL(pci_scan_slot
);
1670 static int pcie_find_smpss(struct pci_dev
*dev
, void *data
)
1674 if (!pci_is_pcie(dev
))
1678 * We don't have a way to change MPS settings on devices that have
1679 * drivers attached. A hot-added device might support only the minimum
1680 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
1681 * where devices may be hot-added, we limit the fabric MPS to 128 so
1682 * hot-added devices will work correctly.
1684 * However, if we hot-add a device to a slot directly below a Root
1685 * Port, it's impossible for there to be other existing devices below
1686 * the port. We don't limit the MPS in this case because we can
1687 * reconfigure MPS on both the Root Port and the hot-added device,
1688 * and there are no other devices involved.
1690 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
1692 if (dev
->is_hotplug_bridge
&&
1693 pci_pcie_type(dev
) != PCI_EXP_TYPE_ROOT_PORT
)
1696 if (*smpss
> dev
->pcie_mpss
)
1697 *smpss
= dev
->pcie_mpss
;
1702 static void pcie_write_mps(struct pci_dev
*dev
, int mps
)
1706 if (pcie_bus_config
== PCIE_BUS_PERFORMANCE
) {
1707 mps
= 128 << dev
->pcie_mpss
;
1709 if (pci_pcie_type(dev
) != PCI_EXP_TYPE_ROOT_PORT
&&
1711 /* For "Performance", the assumption is made that
1712 * downstream communication will never be larger than
1713 * the MRRS. So, the MPS only needs to be configured
1714 * for the upstream communication. This being the case,
1715 * walk from the top down and set the MPS of the child
1716 * to that of the parent bus.
1718 * Configure the device MPS with the smaller of the
1719 * device MPSS or the bridge MPS (which is assumed to be
1720 * properly configured at this point to the largest
1721 * allowable MPS based on its parent bus).
1723 mps
= min(mps
, pcie_get_mps(dev
->bus
->self
));
1726 rc
= pcie_set_mps(dev
, mps
);
1728 dev_err(&dev
->dev
, "Failed attempting to set the MPS\n");
1731 static void pcie_write_mrrs(struct pci_dev
*dev
)
1735 /* In the "safe" case, do not configure the MRRS. There appear to be
1736 * issues with setting MRRS to 0 on a number of devices.
1738 if (pcie_bus_config
!= PCIE_BUS_PERFORMANCE
)
1741 /* For Max performance, the MRRS must be set to the largest supported
1742 * value. However, it cannot be configured larger than the MPS the
1743 * device or the bus can support. This should already be properly
1744 * configured by a prior call to pcie_write_mps.
1746 mrrs
= pcie_get_mps(dev
);
1748 /* MRRS is a R/W register. Invalid values can be written, but a
1749 * subsequent read will verify if the value is acceptable or not.
1750 * If the MRRS value provided is not acceptable (e.g., too large),
1751 * shrink the value until it is acceptable to the HW.
1753 while (mrrs
!= pcie_get_readrq(dev
) && mrrs
>= 128) {
1754 rc
= pcie_set_readrq(dev
, mrrs
);
1758 dev_warn(&dev
->dev
, "Failed attempting to set the MRRS\n");
1763 dev_err(&dev
->dev
, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
1766 static void pcie_bus_detect_mps(struct pci_dev
*dev
)
1768 struct pci_dev
*bridge
= dev
->bus
->self
;
1774 mps
= pcie_get_mps(dev
);
1775 p_mps
= pcie_get_mps(bridge
);
1778 dev_warn(&dev
->dev
, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1779 mps
, pci_name(bridge
), p_mps
);
1782 static int pcie_bus_configure_set(struct pci_dev
*dev
, void *data
)
1786 if (!pci_is_pcie(dev
))
1789 if (pcie_bus_config
== PCIE_BUS_TUNE_OFF
) {
1790 pcie_bus_detect_mps(dev
);
1794 mps
= 128 << *(u8
*)data
;
1795 orig_mps
= pcie_get_mps(dev
);
1797 pcie_write_mps(dev
, mps
);
1798 pcie_write_mrrs(dev
);
1800 dev_info(&dev
->dev
, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
1801 pcie_get_mps(dev
), 128 << dev
->pcie_mpss
,
1802 orig_mps
, pcie_get_readrq(dev
));
1807 /* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
1808 * parents then children fashion. If this changes, then this code will not
1811 void pcie_bus_configure_settings(struct pci_bus
*bus
)
1818 if (!pci_is_pcie(bus
->self
))
1821 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
1822 * to be aware of the MPS of the destination. To work around this,
1823 * simply force the MPS of the entire system to the smallest possible.
1825 if (pcie_bus_config
== PCIE_BUS_PEER2PEER
)
1828 if (pcie_bus_config
== PCIE_BUS_SAFE
) {
1829 smpss
= bus
->self
->pcie_mpss
;
1831 pcie_find_smpss(bus
->self
, &smpss
);
1832 pci_walk_bus(bus
, pcie_find_smpss
, &smpss
);
1835 pcie_bus_configure_set(bus
->self
, &smpss
);
1836 pci_walk_bus(bus
, pcie_bus_configure_set
, &smpss
);
1838 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings
);
1840 unsigned int pci_scan_child_bus(struct pci_bus
*bus
)
1842 unsigned int devfn
, pass
, max
= bus
->busn_res
.start
;
1843 struct pci_dev
*dev
;
1845 dev_dbg(&bus
->dev
, "scanning bus\n");
1847 /* Go find them, Rover! */
1848 for (devfn
= 0; devfn
< 0x100; devfn
+= 8)
1849 pci_scan_slot(bus
, devfn
);
1851 /* Reserve buses for SR-IOV capability. */
1852 max
+= pci_iov_bus_range(bus
);
1855 * After performing arch-dependent fixup of the bus, look behind
1856 * all PCI-to-PCI bridges on this bus.
1858 if (!bus
->is_added
) {
1859 dev_dbg(&bus
->dev
, "fixups for bus\n");
1860 pcibios_fixup_bus(bus
);
1864 for (pass
= 0; pass
< 2; pass
++)
1865 list_for_each_entry(dev
, &bus
->devices
, bus_list
) {
1866 if (pci_is_bridge(dev
))
1867 max
= pci_scan_bridge(bus
, dev
, max
, pass
);
1871 * We've scanned the bus and so we know all about what's on
1872 * the other side of any bridges that may be on this bus plus
1875 * Return how far we've got finding sub-buses.
1877 dev_dbg(&bus
->dev
, "bus scan returning with max=%02x\n", max
);
1880 EXPORT_SYMBOL_GPL(pci_scan_child_bus
);
1883 * pcibios_root_bridge_prepare - Platform-specific host bridge setup.
1884 * @bridge: Host bridge to set up.
1886 * Default empty implementation. Replace with an architecture-specific setup
1887 * routine, if necessary.
1889 int __weak
pcibios_root_bridge_prepare(struct pci_host_bridge
*bridge
)
1894 void __weak
pcibios_add_bus(struct pci_bus
*bus
)
1898 void __weak
pcibios_remove_bus(struct pci_bus
*bus
)
1902 struct pci_bus
*pci_create_root_bus(struct device
*parent
, int bus
,
1903 struct pci_ops
*ops
, void *sysdata
, struct list_head
*resources
)
1906 struct pci_host_bridge
*bridge
;
1907 struct pci_bus
*b
, *b2
;
1908 struct pci_host_bridge_window
*window
, *n
;
1909 struct resource
*res
;
1910 resource_size_t offset
;
1914 b
= pci_alloc_bus(NULL
);
1918 b
->sysdata
= sysdata
;
1920 b
->number
= b
->busn_res
.start
= bus
;
1921 pci_bus_assign_domain_nr(b
, parent
);
1922 b2
= pci_find_bus(pci_domain_nr(b
), bus
);
1924 /* If we already got to this bus through a different bridge, ignore it */
1925 dev_dbg(&b2
->dev
, "bus already known\n");
1929 bridge
= pci_alloc_host_bridge(b
);
1933 bridge
->dev
.parent
= parent
;
1934 bridge
->dev
.release
= pci_release_host_bridge_dev
;
1935 dev_set_name(&bridge
->dev
, "pci%04x:%02x", pci_domain_nr(b
), bus
);
1936 error
= pcibios_root_bridge_prepare(bridge
);
1942 error
= device_register(&bridge
->dev
);
1944 put_device(&bridge
->dev
);
1947 b
->bridge
= get_device(&bridge
->dev
);
1948 device_enable_async_suspend(b
->bridge
);
1949 pci_set_bus_of_node(b
);
1952 set_dev_node(b
->bridge
, pcibus_to_node(b
));
1954 b
->dev
.class = &pcibus_class
;
1955 b
->dev
.parent
= b
->bridge
;
1956 dev_set_name(&b
->dev
, "%04x:%02x", pci_domain_nr(b
), bus
);
1957 error
= device_register(&b
->dev
);
1959 goto class_dev_reg_err
;
1963 /* Create legacy_io and legacy_mem files for this bus */
1964 pci_create_legacy_files(b
);
1967 dev_info(parent
, "PCI host bridge to bus %s\n", dev_name(&b
->dev
));
1969 printk(KERN_INFO
"PCI host bridge to bus %s\n", dev_name(&b
->dev
));
1971 /* Add initial resources to the bus */
1972 list_for_each_entry_safe(window
, n
, resources
, list
) {
1973 list_move_tail(&window
->list
, &bridge
->windows
);
1975 offset
= window
->offset
;
1976 if (res
->flags
& IORESOURCE_BUS
)
1977 pci_bus_insert_busn_res(b
, bus
, res
->end
);
1979 pci_bus_add_resource(b
, res
, 0);
1981 if (resource_type(res
) == IORESOURCE_IO
)
1982 fmt
= " (bus address [%#06llx-%#06llx])";
1984 fmt
= " (bus address [%#010llx-%#010llx])";
1985 snprintf(bus_addr
, sizeof(bus_addr
), fmt
,
1986 (unsigned long long) (res
->start
- offset
),
1987 (unsigned long long) (res
->end
- offset
));
1990 dev_info(&b
->dev
, "root bus resource %pR%s\n", res
, bus_addr
);
1993 down_write(&pci_bus_sem
);
1994 list_add_tail(&b
->node
, &pci_root_buses
);
1995 up_write(&pci_bus_sem
);
2000 put_device(&bridge
->dev
);
2001 device_unregister(&bridge
->dev
);
2007 int pci_bus_insert_busn_res(struct pci_bus
*b
, int bus
, int bus_max
)
2009 struct resource
*res
= &b
->busn_res
;
2010 struct resource
*parent_res
, *conflict
;
2014 res
->flags
= IORESOURCE_BUS
;
2016 if (!pci_is_root_bus(b
))
2017 parent_res
= &b
->parent
->busn_res
;
2019 parent_res
= get_pci_domain_busn_res(pci_domain_nr(b
));
2020 res
->flags
|= IORESOURCE_PCI_FIXED
;
2023 conflict
= request_resource_conflict(parent_res
, res
);
2026 dev_printk(KERN_DEBUG
, &b
->dev
,
2027 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
2028 res
, pci_is_root_bus(b
) ? "domain " : "",
2029 parent_res
, conflict
->name
, conflict
);
2031 return conflict
== NULL
;
2034 int pci_bus_update_busn_res_end(struct pci_bus
*b
, int bus_max
)
2036 struct resource
*res
= &b
->busn_res
;
2037 struct resource old_res
= *res
;
2038 resource_size_t size
;
2041 if (res
->start
> bus_max
)
2044 size
= bus_max
- res
->start
+ 1;
2045 ret
= adjust_resource(res
, res
->start
, size
);
2046 dev_printk(KERN_DEBUG
, &b
->dev
,
2047 "busn_res: %pR end %s updated to %02x\n",
2048 &old_res
, ret
? "can not be" : "is", bus_max
);
2050 if (!ret
&& !res
->parent
)
2051 pci_bus_insert_busn_res(b
, res
->start
, res
->end
);
2056 void pci_bus_release_busn_res(struct pci_bus
*b
)
2058 struct resource
*res
= &b
->busn_res
;
2061 if (!res
->flags
|| !res
->parent
)
2064 ret
= release_resource(res
);
2065 dev_printk(KERN_DEBUG
, &b
->dev
,
2066 "busn_res: %pR %s released\n",
2067 res
, ret
? "can not be" : "is");
2070 struct pci_bus
*pci_scan_root_bus(struct device
*parent
, int bus
,
2071 struct pci_ops
*ops
, void *sysdata
, struct list_head
*resources
)
2073 struct pci_host_bridge_window
*window
;
2078 list_for_each_entry(window
, resources
, list
)
2079 if (window
->res
->flags
& IORESOURCE_BUS
) {
2084 b
= pci_create_root_bus(parent
, bus
, ops
, sysdata
, resources
);
2090 "No busn resource found for root bus, will use [bus %02x-ff]\n",
2092 pci_bus_insert_busn_res(b
, bus
, 255);
2095 max
= pci_scan_child_bus(b
);
2098 pci_bus_update_busn_res_end(b
, max
);
2100 pci_bus_add_devices(b
);
2103 EXPORT_SYMBOL(pci_scan_root_bus
);
2105 /* Deprecated; use pci_scan_root_bus() instead */
2106 struct pci_bus
*pci_scan_bus_parented(struct device
*parent
,
2107 int bus
, struct pci_ops
*ops
, void *sysdata
)
2109 LIST_HEAD(resources
);
2112 pci_add_resource(&resources
, &ioport_resource
);
2113 pci_add_resource(&resources
, &iomem_resource
);
2114 pci_add_resource(&resources
, &busn_resource
);
2115 b
= pci_create_root_bus(parent
, bus
, ops
, sysdata
, &resources
);
2117 pci_scan_child_bus(b
);
2119 pci_free_resource_list(&resources
);
2122 EXPORT_SYMBOL(pci_scan_bus_parented
);
2124 struct pci_bus
*pci_scan_bus(int bus
, struct pci_ops
*ops
,
2127 LIST_HEAD(resources
);
2130 pci_add_resource(&resources
, &ioport_resource
);
2131 pci_add_resource(&resources
, &iomem_resource
);
2132 pci_add_resource(&resources
, &busn_resource
);
2133 b
= pci_create_root_bus(NULL
, bus
, ops
, sysdata
, &resources
);
2135 pci_scan_child_bus(b
);
2136 pci_bus_add_devices(b
);
2138 pci_free_resource_list(&resources
);
2142 EXPORT_SYMBOL(pci_scan_bus
);
2145 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
2146 * @bridge: PCI bridge for the bus to scan
2148 * Scan a PCI bus and child buses for new devices, add them,
2149 * and enable them, resizing bridge mmio/io resource if necessary
2150 * and possible. The caller must ensure the child devices are already
2151 * removed for resizing to occur.
2153 * Returns the max number of subordinate bus discovered.
2155 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev
*bridge
)
2158 struct pci_bus
*bus
= bridge
->subordinate
;
2160 max
= pci_scan_child_bus(bus
);
2162 pci_assign_unassigned_bridge_resources(bridge
);
2164 pci_bus_add_devices(bus
);
2170 * pci_rescan_bus - scan a PCI bus for devices.
2171 * @bus: PCI bus to scan
2173 * Scan a PCI bus and child buses for new devices, adds them,
2176 * Returns the max number of subordinate bus discovered.
2178 unsigned int pci_rescan_bus(struct pci_bus
*bus
)
2182 max
= pci_scan_child_bus(bus
);
2183 pci_assign_unassigned_bus_resources(bus
);
2184 pci_bus_add_devices(bus
);
2188 EXPORT_SYMBOL_GPL(pci_rescan_bus
);
2191 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
2192 * routines should always be executed under this mutex.
2194 static DEFINE_MUTEX(pci_rescan_remove_lock
);
2196 void pci_lock_rescan_remove(void)
2198 mutex_lock(&pci_rescan_remove_lock
);
2200 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove
);
2202 void pci_unlock_rescan_remove(void)
2204 mutex_unlock(&pci_rescan_remove_lock
);
2206 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove
);
2208 static int __init
pci_sort_bf_cmp(const struct device
*d_a
,
2209 const struct device
*d_b
)
2211 const struct pci_dev
*a
= to_pci_dev(d_a
);
2212 const struct pci_dev
*b
= to_pci_dev(d_b
);
2214 if (pci_domain_nr(a
->bus
) < pci_domain_nr(b
->bus
)) return -1;
2215 else if (pci_domain_nr(a
->bus
) > pci_domain_nr(b
->bus
)) return 1;
2217 if (a
->bus
->number
< b
->bus
->number
) return -1;
2218 else if (a
->bus
->number
> b
->bus
->number
) return 1;
2220 if (a
->devfn
< b
->devfn
) return -1;
2221 else if (a
->devfn
> b
->devfn
) return 1;
2226 void __init
pci_sort_breadthfirst(void)
2228 bus_sort_breadthfirst(&pci_bus_type
, &pci_sort_bf_cmp
);