drivers/pinctrl/pinctrl-ingenic.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Ingenic SoCs pinctrl driver
   4  *
   5  * Copyright (c) 2017 Paul Cercueil <paul@crapouillou.net>
   6  * Copyright (c) 2017, 2019 Paul Boddie <paul@boddie.org.uk>
   7  * Copyright (c) 2019, 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
   8  */
   9
  10 #include <linux/compiler.h>
  11 #include <linux/gpio/driver.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/io.h>
  14 #include <linux/kernel.h>
  15 #include <linux/of_device.h>
  16 #include <linux/of_irq.h>
  17 #include <linux/of_platform.h>
  18 #include <linux/pinctrl/pinctrl.h>
  19 #include <linux/pinctrl/pinmux.h>
  20 #include <linux/pinctrl/pinconf.h>
  21 #include <linux/pinctrl/pinconf-generic.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/regmap.h>
  24 #include <linux/slab.h>
  25
  26 #include "core.h"
  27 #include "pinconf.h"
  28 #include "pinmux.h"
  29
  30 #define GPIO_PIN                                        0x00
  31 #define GPIO_MSK                                        0x20
  32
  33 #define JZ4730_GPIO_DATA                        0x00
  34 #define JZ4730_GPIO_GPDIR                       0x04
  35 #define JZ4730_GPIO_GPPUR                       0x0c
  36 #define JZ4730_GPIO_GPALR                       0x10
  37 #define JZ4730_GPIO_GPAUR                       0x14
  38 #define JZ4730_GPIO_GPIDLR                      0x18
  39 #define JZ4730_GPIO_GPIDUR                      0x1c
  40 #define JZ4730_GPIO_GPIER                       0x20
  41 #define JZ4730_GPIO_GPIMR                       0x24
  42 #define JZ4730_GPIO_GPFR                        0x28
  43
  44 #define JZ4740_GPIO_DATA                        0x10
  45 #define JZ4740_GPIO_PULL_DIS            0x30
  46 #define JZ4740_GPIO_FUNC                        0x40
  47 #define JZ4740_GPIO_SELECT                      0x50
  48 #define JZ4740_GPIO_DIR                         0x60
  49 #define JZ4740_GPIO_TRIG                        0x70
  50 #define JZ4740_GPIO_FLAG                        0x80
  51
  52 #define JZ4770_GPIO_INT                         0x10
  53 #define JZ4770_GPIO_PAT1                        0x30
  54 #define JZ4770_GPIO_PAT0                        0x40
  55 #define JZ4770_GPIO_FLAG                        0x50
  56 #define JZ4770_GPIO_PEN                         0x70
  57
  58 #define X1830_GPIO_PEL                          0x110
  59 #define X1830_GPIO_PEH                          0x120
  60 #define X1830_GPIO_SR                           0x150
  61 #define X1830_GPIO_SMT                          0x160
  62
  63 #define X2000_GPIO_EDG                          0x70
  64 #define X2000_GPIO_PEPU                         0x80
  65 #define X2000_GPIO_PEPD                         0x90
  66 #define X2000_GPIO_SR                           0xd0
  67 #define X2000_GPIO_SMT                          0xe0
  68
  69 #define REG_SET(x)                                      ((x) + 0x4)
  70 #define REG_CLEAR(x)                            ((x) + 0x8)
  71
  72 #define REG_PZ_BASE(x)                          ((x) * 7)
  73 #define REG_PZ_GID2LD(x)                        ((x) * 7 + 0xf0)
  74
  75 #define GPIO_PULL_DIS                           0
  76 #define GPIO_PULL_UP                            1
  77 #define GPIO_PULL_DOWN                          2
  78
  79 #define PINS_PER_GPIO_CHIP                      32
  80 #define JZ4730_PINS_PER_PAIRED_REG      16
  81
  82 #define INGENIC_PIN_GROUP_FUNCS(name, id, funcs)                \
  83         {                                               \
  84                 name,                                   \
  85                 id##_pins,                              \
  86                 ARRAY_SIZE(id##_pins),                  \
  87                 funcs,                                  \
  88         }
  89
  90 #define INGENIC_PIN_GROUP(name, id, func)               \
  91         INGENIC_PIN_GROUP_FUNCS(name, id, (void *)(func))
  92
  93 enum jz_version {
  94         ID_JZ4730,
  95         ID_JZ4740,
  96         ID_JZ4725B,
  97         ID_JZ4750,
  98         ID_JZ4755,
  99         ID_JZ4760,
 100         ID_JZ4770,
 101         ID_JZ4775,
 102         ID_JZ4780,
 103         ID_X1000,
 104         ID_X1500,
 105         ID_X1830,
 106         ID_X2000,
 107         ID_X2100,
 108 };
 109
 110 struct ingenic_chip_info {
 111         unsigned int num_chips;
 112         unsigned int reg_offset;
 113         enum jz_version version;
 114
 115         const struct group_desc *groups;
 116         unsigned int num_groups;
 117
 118         const struct function_desc *functions;
 119         unsigned int num_functions;
 120
 121         const u32 *pull_ups, *pull_downs;
 122 };
 123
 124 struct ingenic_pinctrl {
 125         struct device *dev;
 126         struct regmap *map;
 127         struct pinctrl_dev *pctl;
 128         struct pinctrl_pin_desc *pdesc;
 129
 130         const struct ingenic_chip_info *info;
 131 };
 132
 133 struct ingenic_gpio_chip {
 134         struct ingenic_pinctrl *jzpc;
 135         struct gpio_chip gc;
 136         struct irq_chip irq_chip;
 137         unsigned int irq, reg_base;
 138 };
 139
 140 static const u32 jz4730_pull_ups[4] = {
 141         0x3fa3320f, 0xf200ffff, 0xffffffff, 0xffffffff,
 142 };
 143
 144 static const u32 jz4730_pull_downs[4] = {
 145         0x00000df0, 0x0dff0000, 0x00000000, 0x00000000,
 146 };
 147
 148 static int jz4730_mmc_1bit_pins[] = { 0x27, 0x26, 0x22, };
 149 static int jz4730_mmc_4bit_pins[] = { 0x23, 0x24, 0x25, };
 150 static int jz4730_uart0_data_pins[] = { 0x7e, 0x7f, };
 151 static int jz4730_uart1_data_pins[] = { 0x18, 0x19, };
 152 static int jz4730_uart2_data_pins[] = { 0x6f, 0x7d, };
 153 static int jz4730_uart3_data_pins[] = { 0x10, 0x15, };
 154 static int jz4730_uart3_hwflow_pins[] = { 0x11, 0x17, };
 155 static int jz4730_lcd_8bit_pins[] = {
 156         0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
 157         0x3a, 0x39, 0x38,
 158 };
 159 static int jz4730_lcd_16bit_pins[] = {
 160         0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
 161 };
 162 static int jz4730_lcd_special_pins[] = { 0x3d, 0x3c, 0x3e, 0x3f, };
 163 static int jz4730_lcd_generic_pins[] = { 0x3b, };
 164 static int jz4730_nand_cs1_pins[] = { 0x53, };
 165 static int jz4730_nand_cs2_pins[] = { 0x54, };
 166 static int jz4730_nand_cs3_pins[] = { 0x55, };
 167 static int jz4730_nand_cs4_pins[] = { 0x56, };
 168 static int jz4730_nand_cs5_pins[] = { 0x57, };
 169 static int jz4730_pwm_pwm0_pins[] = { 0x5e, };
 170 static int jz4730_pwm_pwm1_pins[] = { 0x5f, };
 171
 172 static u8 jz4730_lcd_8bit_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, };
 173
 174 static const struct group_desc jz4730_groups[] = {
 175         INGENIC_PIN_GROUP("mmc-1bit", jz4730_mmc_1bit, 1),
 176         INGENIC_PIN_GROUP("mmc-4bit", jz4730_mmc_4bit, 1),
 177         INGENIC_PIN_GROUP("uart0-data", jz4730_uart0_data, 1),
 178         INGENIC_PIN_GROUP("uart1-data", jz4730_uart1_data, 1),
 179         INGENIC_PIN_GROUP("uart2-data", jz4730_uart2_data, 1),
 180         INGENIC_PIN_GROUP("uart3-data", jz4730_uart3_data, 1),
 181         INGENIC_PIN_GROUP("uart3-hwflow", jz4730_uart3_hwflow, 1),
 182         INGENIC_PIN_GROUP_FUNCS("lcd-8bit", jz4730_lcd_8bit, jz4730_lcd_8bit_funcs),
 183         INGENIC_PIN_GROUP("lcd-16bit", jz4730_lcd_16bit, 1),
 184         INGENIC_PIN_GROUP("lcd-special", jz4730_lcd_special, 1),
 185         INGENIC_PIN_GROUP("lcd-generic", jz4730_lcd_generic, 1),
 186         INGENIC_PIN_GROUP("nand-cs1", jz4730_nand_cs1, 1),
 187         INGENIC_PIN_GROUP("nand-cs2", jz4730_nand_cs2, 1),
 188         INGENIC_PIN_GROUP("nand-cs3", jz4730_nand_cs3, 1),
 189         INGENIC_PIN_GROUP("nand-cs4", jz4730_nand_cs4, 1),
 190         INGENIC_PIN_GROUP("nand-cs5", jz4730_nand_cs5, 1),
 191         INGENIC_PIN_GROUP("pwm0", jz4730_pwm_pwm0, 1),
 192         INGENIC_PIN_GROUP("pwm1", jz4730_pwm_pwm1, 1),
 193 };
 194
 195 static const char *jz4730_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
 196 static const char *jz4730_uart0_groups[] = { "uart0-data", };
 197 static const char *jz4730_uart1_groups[] = { "uart1-data", };
 198 static const char *jz4730_uart2_groups[] = { "uart2-data", };
 199 static const char *jz4730_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
 200 static const char *jz4730_lcd_groups[] = {
 201         "lcd-8bit", "lcd-16bit", "lcd-special", "lcd-generic",
 202 };
 203 static const char *jz4730_nand_groups[] = {
 204         "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-cs5",
 205 };
 206 static const char *jz4730_pwm0_groups[] = { "pwm0", };
 207 static const char *jz4730_pwm1_groups[] = { "pwm1", };
 208
 209 static const struct function_desc jz4730_functions[] = {
 210         { "mmc", jz4730_mmc_groups, ARRAY_SIZE(jz4730_mmc_groups), },
 211         { "uart0", jz4730_uart0_groups, ARRAY_SIZE(jz4730_uart0_groups), },
 212         { "uart1", jz4730_uart1_groups, ARRAY_SIZE(jz4730_uart1_groups), },
 213         { "uart2", jz4730_uart2_groups, ARRAY_SIZE(jz4730_uart2_groups), },
 214         { "uart3", jz4730_uart3_groups, ARRAY_SIZE(jz4730_uart3_groups), },
 215         { "lcd", jz4730_lcd_groups, ARRAY_SIZE(jz4730_lcd_groups), },
 216         { "nand", jz4730_nand_groups, ARRAY_SIZE(jz4730_nand_groups), },
 217         { "pwm0", jz4730_pwm0_groups, ARRAY_SIZE(jz4730_pwm0_groups), },
 218         { "pwm1", jz4730_pwm1_groups, ARRAY_SIZE(jz4730_pwm1_groups), },
 219 };
 220
 221 static const struct ingenic_chip_info jz4730_chip_info = {
 222         .num_chips = 4,
 223         .reg_offset = 0x30,
 224         .version = ID_JZ4730,
 225         .groups = jz4730_groups,
 226         .num_groups = ARRAY_SIZE(jz4730_groups),
 227         .functions = jz4730_functions,
 228         .num_functions = ARRAY_SIZE(jz4730_functions),
 229         .pull_ups = jz4730_pull_ups,
 230         .pull_downs = jz4730_pull_downs,
 231 };
 232
 233 static const u32 jz4740_pull_ups[4] = {
 234         0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
 235 };
 236
 237 static const u32 jz4740_pull_downs[4] = {
 238         0x00000000, 0x00000000, 0x00000000, 0x00000000,
 239 };
 240
 241 static int jz4740_mmc_1bit_pins[] = { 0x69, 0x68, 0x6a, };
 242 static int jz4740_mmc_4bit_pins[] = { 0x6b, 0x6c, 0x6d, };
 243 static int jz4740_uart0_data_pins[] = { 0x7a, 0x79, };
 244 static int jz4740_uart0_hwflow_pins[] = { 0x7e, 0x7f, };
 245 static int jz4740_uart1_data_pins[] = { 0x7e, 0x7f, };
 246 static int jz4740_lcd_8bit_pins[] = {
 247         0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
 248         0x52, 0x53, 0x54,
 249 };
 250 static int jz4740_lcd_16bit_pins[] = {
 251         0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
 252 };
 253 static int jz4740_lcd_18bit_pins[] = { 0x50, 0x51, };
 254 static int jz4740_lcd_special_pins[] = { 0x31, 0x32, 0x56, 0x57, };
 255 static int jz4740_lcd_generic_pins[] = { 0x55, };
 256 static int jz4740_nand_cs1_pins[] = { 0x39, };
 257 static int jz4740_nand_cs2_pins[] = { 0x3a, };
 258 static int jz4740_nand_cs3_pins[] = { 0x3b, };
 259 static int jz4740_nand_cs4_pins[] = { 0x3c, };
 260 static int jz4740_nand_fre_fwe_pins[] = { 0x5c, 0x5d, };
 261 static int jz4740_pwm_pwm0_pins[] = { 0x77, };
 262 static int jz4740_pwm_pwm1_pins[] = { 0x78, };
 263 static int jz4740_pwm_pwm2_pins[] = { 0x79, };
 264 static int jz4740_pwm_pwm3_pins[] = { 0x7a, };
 265 static int jz4740_pwm_pwm4_pins[] = { 0x7b, };
 266 static int jz4740_pwm_pwm5_pins[] = { 0x7c, };
 267 static int jz4740_pwm_pwm6_pins[] = { 0x7e, };
 268 static int jz4740_pwm_pwm7_pins[] = { 0x7f, };
 269
 270 static const struct group_desc jz4740_groups[] = {
 271         INGENIC_PIN_GROUP("mmc-1bit", jz4740_mmc_1bit, 0),
 272         INGENIC_PIN_GROUP("mmc-4bit", jz4740_mmc_4bit, 0),
 273         INGENIC_PIN_GROUP("uart0-data", jz4740_uart0_data, 1),
 274         INGENIC_PIN_GROUP("uart0-hwflow", jz4740_uart0_hwflow, 1),
 275         INGENIC_PIN_GROUP("uart1-data", jz4740_uart1_data, 2),
 276         INGENIC_PIN_GROUP("lcd-8bit", jz4740_lcd_8bit, 0),
 277         INGENIC_PIN_GROUP("lcd-16bit", jz4740_lcd_16bit, 0),
 278         INGENIC_PIN_GROUP("lcd-18bit", jz4740_lcd_18bit, 0),
 279         INGENIC_PIN_GROUP("lcd-special", jz4740_lcd_special, 0),
 280         INGENIC_PIN_GROUP("lcd-generic", jz4740_lcd_generic, 0),
 281         INGENIC_PIN_GROUP("nand-cs1", jz4740_nand_cs1, 0),
 282         INGENIC_PIN_GROUP("nand-cs2", jz4740_nand_cs2, 0),
 283         INGENIC_PIN_GROUP("nand-cs3", jz4740_nand_cs3, 0),
 284         INGENIC_PIN_GROUP("nand-cs4", jz4740_nand_cs4, 0),
 285         INGENIC_PIN_GROUP("nand-fre-fwe", jz4740_nand_fre_fwe, 0),
 286         INGENIC_PIN_GROUP("pwm0", jz4740_pwm_pwm0, 0),
 287         INGENIC_PIN_GROUP("pwm1", jz4740_pwm_pwm1, 0),
 288         INGENIC_PIN_GROUP("pwm2", jz4740_pwm_pwm2, 0),
 289         INGENIC_PIN_GROUP("pwm3", jz4740_pwm_pwm3, 0),
 290         INGENIC_PIN_GROUP("pwm4", jz4740_pwm_pwm4, 0),
 291         INGENIC_PIN_GROUP("pwm5", jz4740_pwm_pwm5, 0),
 292         INGENIC_PIN_GROUP("pwm6", jz4740_pwm_pwm6, 0),
 293         INGENIC_PIN_GROUP("pwm7", jz4740_pwm_pwm7, 0),
 294 };
 295
 296 static const char *jz4740_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
 297 static const char *jz4740_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
 298 static const char *jz4740_uart1_groups[] = { "uart1-data", };
 299 static const char *jz4740_lcd_groups[] = {
 300         "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-special", "lcd-generic",
 301 };
 302 static const char *jz4740_nand_groups[] = {
 303         "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe",
 304 };
 305 static const char *jz4740_pwm0_groups[] = { "pwm0", };
 306 static const char *jz4740_pwm1_groups[] = { "pwm1", };
 307 static const char *jz4740_pwm2_groups[] = { "pwm2", };
 308 static const char *jz4740_pwm3_groups[] = { "pwm3", };
 309 static const char *jz4740_pwm4_groups[] = { "pwm4", };
 310 static const char *jz4740_pwm5_groups[] = { "pwm5", };
 311 static const char *jz4740_pwm6_groups[] = { "pwm6", };
 312 static const char *jz4740_pwm7_groups[] = { "pwm7", };
 313
 314 static const struct function_desc jz4740_functions[] = {
 315         { "mmc", jz4740_mmc_groups, ARRAY_SIZE(jz4740_mmc_groups), },
 316         { "uart0", jz4740_uart0_groups, ARRAY_SIZE(jz4740_uart0_groups), },
 317         { "uart1", jz4740_uart1_groups, ARRAY_SIZE(jz4740_uart1_groups), },
 318         { "lcd", jz4740_lcd_groups, ARRAY_SIZE(jz4740_lcd_groups), },
 319         { "nand", jz4740_nand_groups, ARRAY_SIZE(jz4740_nand_groups), },
 320         { "pwm0", jz4740_pwm0_groups, ARRAY_SIZE(jz4740_pwm0_groups), },
 321         { "pwm1", jz4740_pwm1_groups, ARRAY_SIZE(jz4740_pwm1_groups), },
 322         { "pwm2", jz4740_pwm2_groups, ARRAY_SIZE(jz4740_pwm2_groups), },
 323         { "pwm3", jz4740_pwm3_groups, ARRAY_SIZE(jz4740_pwm3_groups), },
 324         { "pwm4", jz4740_pwm4_groups, ARRAY_SIZE(jz4740_pwm4_groups), },
 325         { "pwm5", jz4740_pwm5_groups, ARRAY_SIZE(jz4740_pwm5_groups), },
 326         { "pwm6", jz4740_pwm6_groups, ARRAY_SIZE(jz4740_pwm6_groups), },
 327         { "pwm7", jz4740_pwm7_groups, ARRAY_SIZE(jz4740_pwm7_groups), },
 328 };
 329
 330 static const struct ingenic_chip_info jz4740_chip_info = {
 331         .num_chips = 4,
 332         .reg_offset = 0x100,
 333         .version = ID_JZ4740,
 334         .groups = jz4740_groups,
 335         .num_groups = ARRAY_SIZE(jz4740_groups),
 336         .functions = jz4740_functions,
 337         .num_functions = ARRAY_SIZE(jz4740_functions),
 338         .pull_ups = jz4740_pull_ups,
 339         .pull_downs = jz4740_pull_downs,
 340 };
 341
 342 static int jz4725b_mmc0_1bit_pins[] = { 0x48, 0x49, 0x5c, };
 343 static int jz4725b_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x56, };
 344 static int jz4725b_mmc1_1bit_pins[] = { 0x7a, 0x7b, 0x7c, };
 345 static int jz4725b_mmc1_4bit_pins[] = { 0x7d, 0x7e, 0x7f, };
 346 static int jz4725b_uart_data_pins[] = { 0x4c, 0x4d, };
 347 static int jz4725b_lcd_8bit_pins[] = {
 348         0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
 349         0x72, 0x73, 0x74,
 350 };
 351 static int jz4725b_lcd_16bit_pins[] = {
 352         0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
 353 };
 354 static int jz4725b_lcd_18bit_pins[] = { 0x70, 0x71, };
 355 static int jz4725b_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, };
 356 static int jz4725b_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, };
 357 static int jz4725b_lcd_generic_pins[] = { 0x75, };
 358 static int jz4725b_nand_cs1_pins[] = { 0x55, };
 359 static int jz4725b_nand_cs2_pins[] = { 0x56, };
 360 static int jz4725b_nand_cs3_pins[] = { 0x57, };
 361 static int jz4725b_nand_cs4_pins[] = { 0x58, };
 362 static int jz4725b_nand_cle_ale_pins[] = { 0x48, 0x49 };
 363 static int jz4725b_nand_fre_fwe_pins[] = { 0x5c, 0x5d };
 364 static int jz4725b_pwm_pwm0_pins[] = { 0x4a, };
 365 static int jz4725b_pwm_pwm1_pins[] = { 0x4b, };
 366 static int jz4725b_pwm_pwm2_pins[] = { 0x4c, };
 367 static int jz4725b_pwm_pwm3_pins[] = { 0x4d, };
 368 static int jz4725b_pwm_pwm4_pins[] = { 0x4e, };
 369 static int jz4725b_pwm_pwm5_pins[] = { 0x4f, };
 370
 371 static u8 jz4725b_mmc0_4bit_funcs[] = { 1, 0, 1, };
 372
 373 static const struct group_desc jz4725b_groups[] = {
 374         INGENIC_PIN_GROUP("mmc0-1bit", jz4725b_mmc0_1bit, 1),
 375         INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4725b_mmc0_4bit,
 376                                 jz4725b_mmc0_4bit_funcs),
 377         INGENIC_PIN_GROUP("mmc1-1bit", jz4725b_mmc1_1bit, 0),
 378         INGENIC_PIN_GROUP("mmc1-4bit", jz4725b_mmc1_4bit, 0),
 379         INGENIC_PIN_GROUP("uart-data", jz4725b_uart_data, 1),
 380         INGENIC_PIN_GROUP("lcd-8bit", jz4725b_lcd_8bit, 0),
 381         INGENIC_PIN_GROUP("lcd-16bit", jz4725b_lcd_16bit, 0),
 382         INGENIC_PIN_GROUP("lcd-18bit", jz4725b_lcd_18bit, 0),
 383         INGENIC_PIN_GROUP("lcd-24bit", jz4725b_lcd_24bit, 1),
 384         INGENIC_PIN_GROUP("lcd-special", jz4725b_lcd_special, 0),
 385         INGENIC_PIN_GROUP("lcd-generic", jz4725b_lcd_generic, 0),
 386         INGENIC_PIN_GROUP("nand-cs1", jz4725b_nand_cs1, 0),
 387         INGENIC_PIN_GROUP("nand-cs2", jz4725b_nand_cs2, 0),
 388         INGENIC_PIN_GROUP("nand-cs3", jz4725b_nand_cs3, 0),
 389         INGENIC_PIN_GROUP("nand-cs4", jz4725b_nand_cs4, 0),
 390         INGENIC_PIN_GROUP("nand-cle-ale", jz4725b_nand_cle_ale, 0),
 391         INGENIC_PIN_GROUP("nand-fre-fwe", jz4725b_nand_fre_fwe, 0),
 392         INGENIC_PIN_GROUP("pwm0", jz4725b_pwm_pwm0, 0),
 393         INGENIC_PIN_GROUP("pwm1", jz4725b_pwm_pwm1, 0),
 394         INGENIC_PIN_GROUP("pwm2", jz4725b_pwm_pwm2, 0),
 395         INGENIC_PIN_GROUP("pwm3", jz4725b_pwm_pwm3, 0),
 396         INGENIC_PIN_GROUP("pwm4", jz4725b_pwm_pwm4, 0),
 397         INGENIC_PIN_GROUP("pwm5", jz4725b_pwm_pwm5, 0),
 398 };
 399
 400 static const char *jz4725b_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
 401 static const char *jz4725b_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
 402 static const char *jz4725b_uart_groups[] = { "uart-data", };
 403 static const char *jz4725b_lcd_groups[] = {
 404         "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
 405         "lcd-special", "lcd-generic",
 406 };
 407 static const char *jz4725b_nand_groups[] = {
 408         "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4",
 409         "nand-cle-ale", "nand-fre-fwe",
 410 };
 411 static const char *jz4725b_pwm0_groups[] = { "pwm0", };
 412 static const char *jz4725b_pwm1_groups[] = { "pwm1", };
 413 static const char *jz4725b_pwm2_groups[] = { "pwm2", };
 414 static const char *jz4725b_pwm3_groups[] = { "pwm3", };
 415 static const char *jz4725b_pwm4_groups[] = { "pwm4", };
 416 static const char *jz4725b_pwm5_groups[] = { "pwm5", };
 417
 418 static const struct function_desc jz4725b_functions[] = {
 419         { "mmc0", jz4725b_mmc0_groups, ARRAY_SIZE(jz4725b_mmc0_groups), },
 420         { "mmc1", jz4725b_mmc1_groups, ARRAY_SIZE(jz4725b_mmc1_groups), },
 421         { "uart", jz4725b_uart_groups, ARRAY_SIZE(jz4725b_uart_groups), },
 422         { "nand", jz4725b_nand_groups, ARRAY_SIZE(jz4725b_nand_groups), },
 423         { "pwm0", jz4725b_pwm0_groups, ARRAY_SIZE(jz4725b_pwm0_groups), },
 424         { "pwm1", jz4725b_pwm1_groups, ARRAY_SIZE(jz4725b_pwm1_groups), },
 425         { "pwm2", jz4725b_pwm2_groups, ARRAY_SIZE(jz4725b_pwm2_groups), },
 426         { "pwm3", jz4725b_pwm3_groups, ARRAY_SIZE(jz4725b_pwm3_groups), },
 427         { "pwm4", jz4725b_pwm4_groups, ARRAY_SIZE(jz4725b_pwm4_groups), },
 428         { "pwm5", jz4725b_pwm5_groups, ARRAY_SIZE(jz4725b_pwm5_groups), },
 429         { "lcd", jz4725b_lcd_groups, ARRAY_SIZE(jz4725b_lcd_groups), },
 430 };
 431
 432 static const struct ingenic_chip_info jz4725b_chip_info = {
 433         .num_chips = 4,
 434         .reg_offset = 0x100,
 435         .version = ID_JZ4725B,
 436         .groups = jz4725b_groups,
 437         .num_groups = ARRAY_SIZE(jz4725b_groups),
 438         .functions = jz4725b_functions,
 439         .num_functions = ARRAY_SIZE(jz4725b_functions),
 440         .pull_ups = jz4740_pull_ups,
 441         .pull_downs = jz4740_pull_downs,
 442 };
 443
 444 static const u32 jz4750_pull_ups[6] = {
 445         0xffffffff, 0xffffffff, 0x3fffffff, 0x7fffffff, 0x1fff3fff, 0x00ffffff,
 446 };
 447
 448 static const u32 jz4750_pull_downs[6] = {
 449         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 450 };
 451
 452 static int jz4750_uart0_data_pins[] = { 0xa4, 0xa5, };
 453 static int jz4750_uart0_hwflow_pins[] = { 0xa6, 0xa7, };
 454 static int jz4750_uart1_data_pins[] = { 0x90, 0x91, };
 455 static int jz4750_uart1_hwflow_pins[] = { 0x92, 0x93, };
 456 static int jz4750_uart2_data_pins[] = { 0x9b, 0x9a, };
 457 static int jz4750_uart3_data_pins[] = { 0xb0, 0xb1, };
 458 static int jz4750_uart3_hwflow_pins[] = { 0xb2, 0xb3, };
 459 static int jz4750_mmc0_1bit_pins[] = { 0xa8, 0xa9, 0xa0, };
 460 static int jz4750_mmc0_4bit_pins[] = { 0xa1, 0xa2, 0xa3, };
 461 static int jz4750_mmc0_8bit_pins[] = { 0xa4, 0xa5, 0xa6, 0xa7, };
 462 static int jz4750_mmc1_1bit_pins[] = { 0xae, 0xaf, 0xaa, };
 463 static int jz4750_mmc1_4bit_pins[] = { 0xab, 0xac, 0xad, };
 464 static int jz4750_i2c_pins[] = { 0x8c, 0x8d, };
 465 static int jz4750_cim_pins[] = {
 466         0x89, 0x8b, 0x8a, 0x88,
 467         0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
 468 };
 469 static int jz4750_lcd_8bit_pins[] = {
 470         0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
 471         0x72, 0x73, 0x74,
 472 };
 473 static int jz4750_lcd_16bit_pins[] = {
 474         0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
 475 };
 476 static int jz4750_lcd_18bit_pins[] = { 0x70, 0x71, };
 477 static int jz4750_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, 0xb2, 0xb3, };
 478 static int jz4750_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, };
 479 static int jz4750_lcd_generic_pins[] = { 0x75, };
 480 static int jz4750_nand_cs1_pins[] = { 0x55, };
 481 static int jz4750_nand_cs2_pins[] = { 0x56, };
 482 static int jz4750_nand_cs3_pins[] = { 0x57, };
 483 static int jz4750_nand_cs4_pins[] = { 0x58, };
 484 static int jz4750_nand_fre_fwe_pins[] = { 0x5c, 0x5d, };
 485 static int jz4750_pwm_pwm0_pins[] = { 0x94, };
 486 static int jz4750_pwm_pwm1_pins[] = { 0x95, };
 487 static int jz4750_pwm_pwm2_pins[] = { 0x96, };
 488 static int jz4750_pwm_pwm3_pins[] = { 0x97, };
 489 static int jz4750_pwm_pwm4_pins[] = { 0x98, };
 490 static int jz4750_pwm_pwm5_pins[] = { 0x99, };
 491
 492 static const struct group_desc jz4750_groups[] = {
 493         INGENIC_PIN_GROUP("uart0-data", jz4750_uart0_data, 1),
 494         INGENIC_PIN_GROUP("uart0-hwflow", jz4750_uart0_hwflow, 1),
 495         INGENIC_PIN_GROUP("uart1-data", jz4750_uart1_data, 0),
 496         INGENIC_PIN_GROUP("uart1-hwflow", jz4750_uart1_hwflow, 0),
 497         INGENIC_PIN_GROUP("uart2-data", jz4750_uart2_data, 1),
 498         INGENIC_PIN_GROUP("uart3-data", jz4750_uart3_data, 0),
 499         INGENIC_PIN_GROUP("uart3-hwflow", jz4750_uart3_hwflow, 0),
 500         INGENIC_PIN_GROUP("mmc0-1bit", jz4750_mmc0_1bit, 0),
 501         INGENIC_PIN_GROUP("mmc0-4bit", jz4750_mmc0_4bit, 0),
 502         INGENIC_PIN_GROUP("mmc0-8bit", jz4750_mmc0_8bit, 0),
 503         INGENIC_PIN_GROUP("mmc1-1bit", jz4750_mmc1_1bit, 0),
 504         INGENIC_PIN_GROUP("mmc1-4bit", jz4750_mmc1_4bit, 0),
 505         INGENIC_PIN_GROUP("i2c-data", jz4750_i2c, 0),
 506         INGENIC_PIN_GROUP("cim-data", jz4750_cim, 0),
 507         INGENIC_PIN_GROUP("lcd-8bit", jz4750_lcd_8bit, 0),
 508         INGENIC_PIN_GROUP("lcd-16bit", jz4750_lcd_16bit, 0),
 509         INGENIC_PIN_GROUP("lcd-18bit", jz4750_lcd_18bit, 0),
 510         INGENIC_PIN_GROUP("lcd-24bit", jz4750_lcd_24bit, 1),
 511         INGENIC_PIN_GROUP("lcd-special", jz4750_lcd_special, 0),
 512         INGENIC_PIN_GROUP("lcd-generic", jz4750_lcd_generic, 0),
 513         INGENIC_PIN_GROUP("nand-cs1", jz4750_nand_cs1, 0),
 514         INGENIC_PIN_GROUP("nand-cs2", jz4750_nand_cs2, 0),
 515         INGENIC_PIN_GROUP("nand-cs3", jz4750_nand_cs3, 0),
 516         INGENIC_PIN_GROUP("nand-cs4", jz4750_nand_cs4, 0),
 517         INGENIC_PIN_GROUP("nand-fre-fwe", jz4750_nand_fre_fwe, 0),
 518         INGENIC_PIN_GROUP("pwm0", jz4750_pwm_pwm0, 0),
 519         INGENIC_PIN_GROUP("pwm1", jz4750_pwm_pwm1, 0),
 520         INGENIC_PIN_GROUP("pwm2", jz4750_pwm_pwm2, 0),
 521         INGENIC_PIN_GROUP("pwm3", jz4750_pwm_pwm3, 0),
 522         INGENIC_PIN_GROUP("pwm4", jz4750_pwm_pwm4, 0),
 523         INGENIC_PIN_GROUP("pwm5", jz4750_pwm_pwm5, 0),
 524 };
 525
 526 static const char *jz4750_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
 527 static const char *jz4750_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
 528 static const char *jz4750_uart2_groups[] = { "uart2-data", };
 529 static const char *jz4750_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
 530 static const char *jz4750_mmc0_groups[] = {
 531         "mmc0-1bit", "mmc0-4bit", "mmc0-8bit",
 532 };
 533 static const char *jz4750_mmc1_groups[] = { "mmc0-1bit", "mmc0-4bit", };
 534 static const char *jz4750_i2c_groups[] = { "i2c-data", };
 535 static const char *jz4750_cim_groups[] = { "cim-data", };
 536 static const char *jz4750_lcd_groups[] = {
 537         "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
 538         "lcd-special", "lcd-generic",
 539 };
 540 static const char *jz4750_nand_groups[] = {
 541         "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe",
 542 };
 543 static const char *jz4750_pwm0_groups[] = { "pwm0", };
 544 static const char *jz4750_pwm1_groups[] = { "pwm1", };
 545 static const char *jz4750_pwm2_groups[] = { "pwm2", };
 546 static const char *jz4750_pwm3_groups[] = { "pwm3", };
 547 static const char *jz4750_pwm4_groups[] = { "pwm4", };
 548 static const char *jz4750_pwm5_groups[] = { "pwm5", };
 549
 550 static const struct function_desc jz4750_functions[] = {
 551         { "uart0", jz4750_uart0_groups, ARRAY_SIZE(jz4750_uart0_groups), },
 552         { "uart1", jz4750_uart1_groups, ARRAY_SIZE(jz4750_uart1_groups), },
 553         { "uart2", jz4750_uart2_groups, ARRAY_SIZE(jz4750_uart2_groups), },
 554         { "uart3", jz4750_uart3_groups, ARRAY_SIZE(jz4750_uart3_groups), },
 555         { "mmc0", jz4750_mmc0_groups, ARRAY_SIZE(jz4750_mmc0_groups), },
 556         { "mmc1", jz4750_mmc1_groups, ARRAY_SIZE(jz4750_mmc1_groups), },
 557         { "i2c", jz4750_i2c_groups, ARRAY_SIZE(jz4750_i2c_groups), },
 558         { "cim", jz4750_cim_groups, ARRAY_SIZE(jz4750_cim_groups), },
 559         { "lcd", jz4750_lcd_groups, ARRAY_SIZE(jz4750_lcd_groups), },
 560         { "nand", jz4750_nand_groups, ARRAY_SIZE(jz4750_nand_groups), },
 561         { "pwm0", jz4750_pwm0_groups, ARRAY_SIZE(jz4750_pwm0_groups), },
 562         { "pwm1", jz4750_pwm1_groups, ARRAY_SIZE(jz4750_pwm1_groups), },
 563         { "pwm2", jz4750_pwm2_groups, ARRAY_SIZE(jz4750_pwm2_groups), },
 564         { "pwm3", jz4750_pwm3_groups, ARRAY_SIZE(jz4750_pwm3_groups), },
 565         { "pwm4", jz4750_pwm4_groups, ARRAY_SIZE(jz4750_pwm4_groups), },
 566         { "pwm5", jz4750_pwm5_groups, ARRAY_SIZE(jz4750_pwm5_groups), },
 567 };
 568
 569 static const struct ingenic_chip_info jz4750_chip_info = {
 570         .num_chips = 6,
 571         .reg_offset = 0x100,
 572         .version = ID_JZ4750,
 573         .groups = jz4750_groups,
 574         .num_groups = ARRAY_SIZE(jz4750_groups),
 575         .functions = jz4750_functions,
 576         .num_functions = ARRAY_SIZE(jz4750_functions),
 577         .pull_ups = jz4750_pull_ups,
 578         .pull_downs = jz4750_pull_downs,
 579 };
 580
 581 static const u32 jz4755_pull_ups[6] = {
 582         0xffffffff, 0xffffffff, 0x0fffffff, 0xffffffff, 0x33dc3fff, 0x0000fc00,
 583 };
 584
 585 static const u32 jz4755_pull_downs[6] = {
 586         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
 587 };
 588
 589 static int jz4755_uart0_data_pins[] = { 0x7c, 0x7d, };
 590 static int jz4755_uart0_hwflow_pins[] = { 0x7e, 0x7f, };
 591 static int jz4755_uart1_data_pins[] = { 0x97, 0x99, };
 592 static int jz4755_uart2_data_pins[] = { 0x9f, };
 593 static int jz4755_ssi_dt_b_pins[] = { 0x3b, };
 594 static int jz4755_ssi_dt_f_pins[] = { 0xa1, };
 595 static int jz4755_ssi_dr_b_pins[] = { 0x3c, };
 596 static int jz4755_ssi_dr_f_pins[] = { 0xa2, };
 597 static int jz4755_ssi_clk_b_pins[] = { 0x3a, };
 598 static int jz4755_ssi_clk_f_pins[] = { 0xa0, };
 599 static int jz4755_ssi_gpc_b_pins[] = { 0x3e, };
 600 static int jz4755_ssi_gpc_f_pins[] = { 0xa4, };
 601 static int jz4755_ssi_ce0_b_pins[] = { 0x3d, };
 602 static int jz4755_ssi_ce0_f_pins[] = { 0xa3, };
 603 static int jz4755_ssi_ce1_b_pins[] = { 0x3f, };
 604 static int jz4755_ssi_ce1_f_pins[] = { 0xa5, };
 605 static int jz4755_mmc0_1bit_pins[] = { 0x2f, 0x50, 0x5c, };
 606 static int jz4755_mmc0_4bit_pins[] = { 0x5d, 0x5b, 0x51, };
 607 static int jz4755_mmc1_1bit_pins[] = { 0x3a, 0x3d, 0x3c, };
 608 static int jz4755_mmc1_4bit_pins[] = { 0x3b, 0x3e, 0x3f, };
 609 static int jz4755_i2c_pins[] = { 0x8c, 0x8d, };
 610 static int jz4755_cim_pins[] = {
 611         0x89, 0x8b, 0x8a, 0x88,
 612         0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
 613 };
 614 static int jz4755_lcd_8bit_pins[] = {
 615         0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
 616         0x72, 0x73, 0x74,
 617 };
 618 static int jz4755_lcd_16bit_pins[] = {
 619         0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
 620 };
 621 static int jz4755_lcd_18bit_pins[] = { 0x70, 0x71, };
 622 static int jz4755_lcd_24bit_pins[] = { 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b, };
 623 static int jz4755_lcd_special_pins[] = { 0x76, 0x77, 0x78, 0x79, };
 624 static int jz4755_lcd_generic_pins[] = { 0x75, };
 625 static int jz4755_nand_cs1_pins[] = { 0x55, };
 626 static int jz4755_nand_cs2_pins[] = { 0x56, };
 627 static int jz4755_nand_cs3_pins[] = { 0x57, };
 628 static int jz4755_nand_cs4_pins[] = { 0x58, };
 629 static int jz4755_nand_fre_fwe_pins[] = { 0x5c, 0x5d, };
 630 static int jz4755_pwm_pwm0_pins[] = { 0x94, };
 631 static int jz4755_pwm_pwm1_pins[] = { 0xab, };
 632 static int jz4755_pwm_pwm2_pins[] = { 0x96, };
 633 static int jz4755_pwm_pwm3_pins[] = { 0x97, };
 634 static int jz4755_pwm_pwm4_pins[] = { 0x98, };
 635 static int jz4755_pwm_pwm5_pins[] = { 0x99, };
 636
 637 static u8 jz4755_mmc0_1bit_funcs[] = { 2, 2, 1, };
 638 static u8 jz4755_mmc0_4bit_funcs[] = { 1, 0, 1, };
 639 static u8 jz4755_lcd_24bit_funcs[] = { 1, 1, 1, 1, 0, 0, };
 640
 641 static const struct group_desc jz4755_groups[] = {
 642         INGENIC_PIN_GROUP("uart0-data", jz4755_uart0_data, 0),
 643         INGENIC_PIN_GROUP("uart0-hwflow", jz4755_uart0_hwflow, 0),
 644         INGENIC_PIN_GROUP("uart1-data", jz4755_uart1_data, 0),
 645         INGENIC_PIN_GROUP("uart2-data", jz4755_uart2_data, 1),
 646         INGENIC_PIN_GROUP("ssi-dt-b", jz4755_ssi_dt_b, 0),
 647         INGENIC_PIN_GROUP("ssi-dt-f", jz4755_ssi_dt_f, 0),
 648         INGENIC_PIN_GROUP("ssi-dr-b", jz4755_ssi_dr_b, 0),
 649         INGENIC_PIN_GROUP("ssi-dr-f", jz4755_ssi_dr_f, 0),
 650         INGENIC_PIN_GROUP("ssi-clk-b", jz4755_ssi_clk_b, 0),
 651         INGENIC_PIN_GROUP("ssi-clk-f", jz4755_ssi_clk_f, 0),
 652         INGENIC_PIN_GROUP("ssi-gpc-b", jz4755_ssi_gpc_b, 0),
 653         INGENIC_PIN_GROUP("ssi-gpc-f", jz4755_ssi_gpc_f, 0),
 654         INGENIC_PIN_GROUP("ssi-ce0-b", jz4755_ssi_ce0_b, 0),
 655         INGENIC_PIN_GROUP("ssi-ce0-f", jz4755_ssi_ce0_f, 0),
 656         INGENIC_PIN_GROUP("ssi-ce1-b", jz4755_ssi_ce1_b, 0),
 657         INGENIC_PIN_GROUP("ssi-ce1-f", jz4755_ssi_ce1_f, 0),
 658         INGENIC_PIN_GROUP_FUNCS("mmc0-1bit", jz4755_mmc0_1bit,
 659                                 jz4755_mmc0_1bit_funcs),
 660         INGENIC_PIN_GROUP_FUNCS("mmc0-4bit", jz4755_mmc0_4bit,
 661                                 jz4755_mmc0_4bit_funcs),
 662         INGENIC_PIN_GROUP("mmc1-1bit", jz4755_mmc1_1bit, 1),
 663         INGENIC_PIN_GROUP("mmc1-4bit", jz4755_mmc1_4bit, 1),
 664         INGENIC_PIN_GROUP("i2c-data", jz4755_i2c, 0),
 665         INGENIC_PIN_GROUP("cim-data", jz4755_cim, 0),
 666         INGENIC_PIN_GROUP("lcd-8bit", jz4755_lcd_8bit, 0),
 667         INGENIC_PIN_GROUP("lcd-16bit", jz4755_lcd_16bit, 0),
 668         INGENIC_PIN_GROUP("lcd-18bit", jz4755_lcd_18bit, 0),
 669         INGENIC_PIN_GROUP_FUNCS("lcd-24bit", jz4755_lcd_24bit,
 670                                 jz4755_lcd_24bit_funcs),
 671         INGENIC_PIN_GROUP("lcd-special", jz4755_lcd_special, 0),
 672         INGENIC_PIN_GROUP("lcd-generic", jz4755_lcd_generic, 0),
 673         INGENIC_PIN_GROUP("nand-cs1", jz4755_nand_cs1, 0),
 674         INGENIC_PIN_GROUP("nand-cs2", jz4755_nand_cs2, 0),
 675         INGENIC_PIN_GROUP("nand-cs3", jz4755_nand_cs3, 0),
 676         INGENIC_PIN_GROUP("nand-cs4", jz4755_nand_cs4, 0),
 677         INGENIC_PIN_GROUP("nand-fre-fwe", jz4755_nand_fre_fwe, 0),
 678         INGENIC_PIN_GROUP("pwm0", jz4755_pwm_pwm0, 0),
 679         INGENIC_PIN_GROUP("pwm1", jz4755_pwm_pwm1, 1),
 680         INGENIC_PIN_GROUP("pwm2", jz4755_pwm_pwm2, 0),
 681         INGENIC_PIN_GROUP("pwm3", jz4755_pwm_pwm3, 0),
 682         INGENIC_PIN_GROUP("pwm4", jz4755_pwm_pwm4, 0),
 683         INGENIC_PIN_GROUP("pwm5", jz4755_pwm_pwm5, 0),
 684 };
 685
 686 static const char *jz4755_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
 687 static const char *jz4755_uart1_groups[] = { "uart1-data", };
 688 static const char *jz4755_uart2_groups[] = { "uart2-data", };
 689 static const char *jz4755_ssi_groups[] = {
 690         "ssi-dt-b", "ssi-dt-f",
 691         "ssi-dr-b", "ssi-dr-f",
 692         "ssi-clk-b", "ssi-clk-f",
 693         "ssi-gpc-b", "ssi-gpc-f",
 694         "ssi-ce0-b", "ssi-ce0-f",
 695         "ssi-ce1-b", "ssi-ce1-f",
 696 };
 697 static const char *jz4755_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
 698 static const char *jz4755_mmc1_groups[] = { "mmc0-1bit", "mmc0-4bit", };
 699 static const char *jz4755_i2c_groups[] = { "i2c-data", };
 700 static const char *jz4755_cim_groups[] = { "cim-data", };
 701 static const char *jz4755_lcd_groups[] = {
 702         "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
 703         "lcd-special", "lcd-generic",
 704 };
 705 static const char *jz4755_nand_groups[] = {
 706         "nand-cs1", "nand-cs2", "nand-cs3", "nand-cs4", "nand-fre-fwe",
 707 };
 708 static const char *jz4755_pwm0_groups[] = { "pwm0", };
 709 static const char *jz4755_pwm1_groups[] = { "pwm1", };
 710 static const char *jz4755_pwm2_groups[] = { "pwm2", };
 711 static const char *jz4755_pwm3_groups[] = { "pwm3", };
 712 static const char *jz4755_pwm4_groups[] = { "pwm4", };
 713 static const char *jz4755_pwm5_groups[] = { "pwm5", };
 714
 715 static const struct function_desc jz4755_functions[] = {
 716         { "uart0", jz4755_uart0_groups, ARRAY_SIZE(jz4755_uart0_groups), },
 717         { "uart1", jz4755_uart1_groups, ARRAY_SIZE(jz4755_uart1_groups), },
 718         { "uart2", jz4755_uart2_groups, ARRAY_SIZE(jz4755_uart2_groups), },
 719         { "ssi", jz4755_ssi_groups, ARRAY_SIZE(jz4755_ssi_groups), },
 720         { "mmc0", jz4755_mmc0_groups, ARRAY_SIZE(jz4755_mmc0_groups), },
 721         { "mmc1", jz4755_mmc1_groups, ARRAY_SIZE(jz4755_mmc1_groups), },
 722         { "i2c", jz4755_i2c_groups, ARRAY_SIZE(jz4755_i2c_groups), },
 723         { "cim", jz4755_cim_groups, ARRAY_SIZE(jz4755_cim_groups), },
 724         { "lcd", jz4755_lcd_groups, ARRAY_SIZE(jz4755_lcd_groups), },
 725         { "nand", jz4755_nand_groups, ARRAY_SIZE(jz4755_nand_groups), },
 726         { "pwm0", jz4755_pwm0_groups, ARRAY_SIZE(jz4755_pwm0_groups), },
 727         { "pwm1", jz4755_pwm1_groups, ARRAY_SIZE(jz4755_pwm1_groups), },
 728         { "pwm2", jz4755_pwm2_groups, ARRAY_SIZE(jz4755_pwm2_groups), },
 729         { "pwm3", jz4755_pwm3_groups, ARRAY_SIZE(jz4755_pwm3_groups), },
 730         { "pwm4", jz4755_pwm4_groups, ARRAY_SIZE(jz4755_pwm4_groups), },
 731         { "pwm5", jz4755_pwm5_groups, ARRAY_SIZE(jz4755_pwm5_groups), },
 732 };
 733
 734 static const struct ingenic_chip_info jz4755_chip_info = {
 735         .num_chips = 6,
 736         .reg_offset = 0x100,
 737         .version = ID_JZ4755,
 738         .groups = jz4755_groups,
 739         .num_groups = ARRAY_SIZE(jz4755_groups),
 740         .functions = jz4755_functions,
 741         .num_functions = ARRAY_SIZE(jz4755_functions),
 742         .pull_ups = jz4755_pull_ups,
 743         .pull_downs = jz4755_pull_downs,
 744 };
 745
 746 static const u32 jz4760_pull_ups[6] = {
 747         0xffffffff, 0xfffcf3ff, 0xffffffff, 0xffffcfff, 0xfffffb7c, 0x0000000f,
 748 };
 749
 750 static const u32 jz4760_pull_downs[6] = {
 751         0x00000000, 0x00030c00, 0x00000000, 0x00003000, 0x00000483, 0x00000ff0,
 752 };
 753
 754 static int jz4760_uart0_data_pins[] = { 0xa0, 0xa3, };
 755 static int jz4760_uart0_hwflow_pins[] = { 0xa1, 0xa2, };
 756 static int jz4760_uart1_data_pins[] = { 0x7a, 0x7c, };
 757 static int jz4760_uart1_hwflow_pins[] = { 0x7b, 0x7d, };
 758 static int jz4760_uart2_data_pins[] = { 0x5c, 0x5e, };
 759 static int jz4760_uart2_hwflow_pins[] = { 0x5d, 0x5f, };
 760 static int jz4760_uart3_data_pins[] = { 0x6c, 0x85, };
 761 static int jz4760_uart3_hwflow_pins[] = { 0x88, 0x89, };
 762 static int jz4760_ssi0_dt_a_pins[] = { 0x15, };
 763 static int jz4760_ssi0_dt_b_pins[] = { 0x35, };
 764 static int jz4760_ssi0_dt_d_pins[] = { 0x75, };
 765 static int jz4760_ssi0_dt_e_pins[] = { 0x91, };
 766 static int jz4760_ssi0_dr_a_pins[] = { 0x14, };
 767 static int jz4760_ssi0_dr_b_pins[] = { 0x34, };
 768 static int jz4760_ssi0_dr_d_pins[] = { 0x74, };
 769 static int jz4760_ssi0_dr_e_pins[] = { 0x8e, };
 770 static int jz4760_ssi0_clk_a_pins[] = { 0x12, };
 771 static int jz4760_ssi0_clk_b_pins[] = { 0x3c, };
 772 static int jz4760_ssi0_clk_d_pins[] = { 0x78, };
 773 static int jz4760_ssi0_clk_e_pins[] = { 0x8f, };
 774 static int jz4760_ssi0_gpc_b_pins[] = { 0x3e, };
 775 static int jz4760_ssi0_gpc_d_pins[] = { 0x76, };
 776 static int jz4760_ssi0_gpc_e_pins[] = { 0x93, };
 777 static int jz4760_ssi0_ce0_a_pins[] = { 0x13, };
 778 static int jz4760_ssi0_ce0_b_pins[] = { 0x3d, };
 779 static int jz4760_ssi0_ce0_d_pins[] = { 0x79, };
 780 static int jz4760_ssi0_ce0_e_pins[] = { 0x90, };
 781 static int jz4760_ssi0_ce1_b_pins[] = { 0x3f, };
 782 static int jz4760_ssi0_ce1_d_pins[] = { 0x77, };
 783 static int jz4760_ssi0_ce1_e_pins[] = { 0x92, };
 784 static int jz4760_ssi1_dt_b_9_pins[] = { 0x29, };
 785 static int jz4760_ssi1_dt_b_21_pins[] = { 0x35, };
 786 static int jz4760_ssi1_dt_d_12_pins[] = { 0x6c, };
 787 static int jz4760_ssi1_dt_d_21_pins[] = { 0x75, };
 788 static int jz4760_ssi1_dt_e_pins[] = { 0x91, };
 789 static int jz4760_ssi1_dt_f_pins[] = { 0xa3, };
 790 static int jz4760_ssi1_dr_b_6_pins[] = { 0x26, };
 791 static int jz4760_ssi1_dr_b_20_pins[] = { 0x34, };
 792 static int jz4760_ssi1_dr_d_13_pins[] = { 0x6d, };
 793 static int jz4760_ssi1_dr_d_20_pins[] = { 0x74, };
 794 static int jz4760_ssi1_dr_e_pins[] = { 0x8e, };
 795 static int jz4760_ssi1_dr_f_pins[] = { 0xa0, };
 796 static int jz4760_ssi1_clk_b_7_pins[] = { 0x27, };
 797 static int jz4760_ssi1_clk_b_28_pins[] = { 0x3c, };
 798 static int jz4760_ssi1_clk_d_pins[] = { 0x78, };
 799 static int jz4760_ssi1_clk_e_7_pins[] = { 0x87, };
 800 static int jz4760_ssi1_clk_e_15_pins[] = { 0x8f, };
 801 static int jz4760_ssi1_clk_f_pins[] = { 0xa2, };
 802 static int jz4760_ssi1_gpc_b_pins[] = { 0x3e, };
 803 static int jz4760_ssi1_gpc_d_pins[] = { 0x76, };
 804 static int jz4760_ssi1_gpc_e_pins[] = { 0x93, };
 805 static int jz4760_ssi1_ce0_b_8_pins[] = { 0x28, };
 806 static int jz4760_ssi1_ce0_b_29_pins[] = { 0x3d, };
 807 static int jz4760_ssi1_ce0_d_pins[] = { 0x79, };
 808 static int jz4760_ssi1_ce0_e_6_pins[] = { 0x86, };
 809 static int jz4760_ssi1_ce0_e_16_pins[] = { 0x90, };
 810 static int jz4760_ssi1_ce0_f_pins[] = { 0xa1, };
 811 static int jz4760_ssi1_ce1_b_pins[] = { 0x3f, };
 812 static int jz4760_ssi1_ce1_d_pins[] = { 0x77, };
 813 static int jz4760_ssi1_ce1_e_pins[] = { 0x92, };
 814 static int jz4760_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
 815 static int jz4760_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
 816 static int jz4760_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
 817 static int jz4760_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
 818 static int jz4760_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
 819 static int jz4760_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };
 820 static int jz4760_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
 821 static int jz4760_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
 822 static int jz4760_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
 823 static int jz4760_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
 824 static int jz4760_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };
 825 static int jz4760_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };
 826 static int jz4760_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
 827 static int jz4760_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
 828 static int jz4760_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
 829 static int jz4760_nemc_8bit_data_pins[] = {
 830         0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
 831 };
 832 static int jz4760_nemc_16bit_data_pins[] = {
 833         0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
 834 };
 835 static int jz4760_nemc_cle_ale_pins[] = { 0x20, 0x21, };
 836 static int jz4760_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
 837 static int jz4760_nemc_rd_we_pins[] = { 0x10, 0x11, };
 838 static int jz4760_nemc_frd_fwe_pins[] = { 0x12, 0x13, };
 839 static int jz4760_nemc_wait_pins[] = { 0x1b, };
 840 static int jz4760_nemc_cs1_pins[] = { 0x15, };
 841 static int jz4760_nemc_cs2_pins[] = { 0x16, };
 842 static int jz4760_nemc_cs3_pins[] = { 0x17, };
 843 static int jz4760_nemc_cs4_pins[] = { 0x18, };
 844 static int jz4760_nemc_cs5_pins[] = { 0x19, };
 845 static int jz4760_nemc_cs6_pins[] = { 0x1a, };
 846 static int jz4760_i2c0_pins[] = { 0x7e, 0x7f, };
 847 static int jz4760_i2c1_pins[] = { 0x9e, 0x9f, };
 848 static int jz4760_cim_pins[] = {
 849         0x26, 0x27, 0x28, 0x29,
 850         0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
 851 };
 852 static int jz4760_lcd_8bit_pins[] = {
 853         0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x4c,
 854         0x4d, 0x52, 0x53,
 855 };
 856 static int jz4760_lcd_16bit_pins[] = {
 857         0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59,
 858 };
 859 static int jz4760_lcd_18bit_pins[] = {
 860         0x5a, 0x5b,
 861 };
 862 static int jz4760_lcd_24bit_pins[] = {
 863         0x40, 0x41, 0x4a, 0x4b, 0x54, 0x55,
 864 };
 865 static int jz4760_lcd_special_pins[] = { 0x54, 0x4a, 0x41, 0x40, };
 866 static int jz4760_lcd_generic_pins[] = { 0x49, };
 867 static int jz4760_pwm_pwm0_pins[] = { 0x80, };
 868 static int jz4760_pwm_pwm1_pins[] = { 0x81, };
 869 static int jz4760_pwm_pwm2_pins[] = { 0x82, };
 870 static int jz4760_pwm_pwm3_pins[] = { 0x83, };
 871 static int jz4760_pwm_pwm4_pins[] = { 0x84, };
 872 static int jz4760_pwm_pwm5_pins[] = { 0x85, };
 873 static int jz4760_pwm_pwm6_pins[] = { 0x6a, };
 874 static int jz4760_pwm_pwm7_pins[] = { 0x6b, };
 875 static int jz4760_otg_pins[] = { 0x8a, };
 876
 877 static u8 jz4760_uart3_data_funcs[] = { 0, 1, };
 878 static u8 jz4760_mmc0_1bit_a_funcs[] = { 1, 1, 0, };
 879
 880 static const struct group_desc jz4760_groups[] = {
 881         INGENIC_PIN_GROUP("uart0-data", jz4760_uart0_data, 0),
 882         INGENIC_PIN_GROUP("uart0-hwflow", jz4760_uart0_hwflow, 0),
 883         INGENIC_PIN_GROUP("uart1-data", jz4760_uart1_data, 0),
 884         INGENIC_PIN_GROUP("uart1-hwflow", jz4760_uart1_hwflow, 0),
 885         INGENIC_PIN_GROUP("uart2-data", jz4760_uart2_data, 0),
 886         INGENIC_PIN_GROUP("uart2-hwflow", jz4760_uart2_hwflow, 0),
 887         INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4760_uart3_data,
 888                                 jz4760_uart3_data_funcs),
 889         INGENIC_PIN_GROUP("uart3-hwflow", jz4760_uart3_hwflow, 0),
 890         INGENIC_PIN_GROUP("ssi0-dt-a", jz4760_ssi0_dt_a, 2),
 891         INGENIC_PIN_GROUP("ssi0-dt-b", jz4760_ssi0_dt_b, 1),
 892         INGENIC_PIN_GROUP("ssi0-dt-d", jz4760_ssi0_dt_d, 1),
 893         INGENIC_PIN_GROUP("ssi0-dt-e", jz4760_ssi0_dt_e, 0),
 894         INGENIC_PIN_GROUP("ssi0-dr-a", jz4760_ssi0_dr_a, 1),
 895         INGENIC_PIN_GROUP("ssi0-dr-b", jz4760_ssi0_dr_b, 1),
 896         INGENIC_PIN_GROUP("ssi0-dr-d", jz4760_ssi0_dr_d, 1),
 897         INGENIC_PIN_GROUP("ssi0-dr-e", jz4760_ssi0_dr_e, 0),
 898         INGENIC_PIN_GROUP("ssi0-clk-a", jz4760_ssi0_clk_a, 2),
 899         INGENIC_PIN_GROUP("ssi0-clk-b", jz4760_ssi0_clk_b, 1),
 900         INGENIC_PIN_GROUP("ssi0-clk-d", jz4760_ssi0_clk_d, 1),
 901         INGENIC_PIN_GROUP("ssi0-clk-e", jz4760_ssi0_clk_e, 0),
 902         INGENIC_PIN_GROUP("ssi0-gpc-b", jz4760_ssi0_gpc_b, 1),
 903         INGENIC_PIN_GROUP("ssi0-gpc-d", jz4760_ssi0_gpc_d, 1),
 904         INGENIC_PIN_GROUP("ssi0-gpc-e", jz4760_ssi0_gpc_e, 0),
 905         INGENIC_PIN_GROUP("ssi0-ce0-a", jz4760_ssi0_ce0_a, 2),
 906         INGENIC_PIN_GROUP("ssi0-ce0-b", jz4760_ssi0_ce0_b, 1),
 907         INGENIC_PIN_GROUP("ssi0-ce0-d", jz4760_ssi0_ce0_d, 1),
 908         INGENIC_PIN_GROUP("ssi0-ce0-e", jz4760_ssi0_ce0_e, 0),
 909         INGENIC_PIN_GROUP("ssi0-ce1-b", jz4760_ssi0_ce1_b, 1),
 910         INGENIC_PIN_GROUP("ssi0-ce1-d", jz4760_ssi0_ce1_d, 1),
 911         INGENIC_PIN_GROUP("ssi0-ce1-e", jz4760_ssi0_ce1_e, 0),
 912         INGENIC_PIN_GROUP("ssi1-dt-b-9", jz4760_ssi1_dt_b_9, 2),
 913         INGENIC_PIN_GROUP("ssi1-dt-b-21", jz4760_ssi1_dt_b_21, 2),
 914         INGENIC_PIN_GROUP("ssi1-dt-d-12", jz4760_ssi1_dt_d_12, 2),
 915         INGENIC_PIN_GROUP("ssi1-dt-d-21", jz4760_ssi1_dt_d_21, 2),
 916         INGENIC_PIN_GROUP("ssi1-dt-e", jz4760_ssi1_dt_e, 1),
 917         INGENIC_PIN_GROUP("ssi1-dt-f", jz4760_ssi1_dt_f, 2),
 918         INGENIC_PIN_GROUP("ssi1-dr-b-6", jz4760_ssi1_dr_b_6, 2),
 919         INGENIC_PIN_GROUP("ssi1-dr-b-20", jz4760_ssi1_dr_b_20, 2),
 920         INGENIC_PIN_GROUP("ssi1-dr-d-13", jz4760_ssi1_dr_d_13, 2),
 921         INGENIC_PIN_GROUP("ssi1-dr-d-20", jz4760_ssi1_dr_d_20, 2),
 922         INGENIC_PIN_GROUP("ssi1-dr-e", jz4760_ssi1_dr_e, 1),
 923         INGENIC_PIN_GROUP("ssi1-dr-f", jz4760_ssi1_dr_f, 2),
 924         INGENIC_PIN_GROUP("ssi1-clk-b-7", jz4760_ssi1_clk_b_7, 2),
 925         INGENIC_PIN_GROUP("ssi1-clk-b-28", jz4760_ssi1_clk_b_28, 2),
 926         INGENIC_PIN_GROUP("ssi1-clk-d", jz4760_ssi1_clk_d, 2),
 927         INGENIC_PIN_GROUP("ssi1-clk-e-7", jz4760_ssi1_clk_e_7, 2),
 928         INGENIC_PIN_GROUP("ssi1-clk-e-15", jz4760_ssi1_clk_e_15, 1),
 929         INGENIC_PIN_GROUP("ssi1-clk-f", jz4760_ssi1_clk_f, 2),
 930         INGENIC_PIN_GROUP("ssi1-gpc-b", jz4760_ssi1_gpc_b, 2),
 931         INGENIC_PIN_GROUP("ssi1-gpc-d", jz4760_ssi1_gpc_d, 2),
 932         INGENIC_PIN_GROUP("ssi1-gpc-e", jz4760_ssi1_gpc_e, 1),
 933         INGENIC_PIN_GROUP("ssi1-ce0-b-8", jz4760_ssi1_ce0_b_8, 2),
 934         INGENIC_PIN_GROUP("ssi1-ce0-b-29", jz4760_ssi1_ce0_b_29, 2),
 935         INGENIC_PIN_GROUP("ssi1-ce0-d", jz4760_ssi1_ce0_d, 2),
 936         INGENIC_PIN_GROUP("ssi1-ce0-e-6", jz4760_ssi1_ce0_e_6, 2),
 937         INGENIC_PIN_GROUP("ssi1-ce0-e-16", jz4760_ssi1_ce0_e_16, 1),
 938         INGENIC_PIN_GROUP("ssi1-ce0-f", jz4760_ssi1_ce0_f, 2),
 939         INGENIC_PIN_GROUP("ssi1-ce1-b", jz4760_ssi1_ce1_b, 2),
 940         INGENIC_PIN_GROUP("ssi1-ce1-d", jz4760_ssi1_ce1_d, 2),
 941         INGENIC_PIN_GROUP("ssi1-ce1-e", jz4760_ssi1_ce1_e, 1),
 942         INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4760_mmc0_1bit_a,
 943                                 jz4760_mmc0_1bit_a_funcs),
 944         INGENIC_PIN_GROUP("mmc0-4bit-a", jz4760_mmc0_4bit_a, 1),
 945         INGENIC_PIN_GROUP("mmc0-1bit-e", jz4760_mmc0_1bit_e, 0),
 946         INGENIC_PIN_GROUP("mmc0-4bit-e", jz4760_mmc0_4bit_e, 0),
 947         INGENIC_PIN_GROUP("mmc0-8bit-e", jz4760_mmc0_8bit_e, 0),
 948         INGENIC_PIN_GROUP("mmc1-1bit-d", jz4760_mmc1_1bit_d, 0),
 949         INGENIC_PIN_GROUP("mmc1-4bit-d", jz4760_mmc1_4bit_d, 0),
 950         INGENIC_PIN_GROUP("mmc1-1bit-e", jz4760_mmc1_1bit_e, 1),
 951         INGENIC_PIN_GROUP("mmc1-4bit-e", jz4760_mmc1_4bit_e, 1),
 952         INGENIC_PIN_GROUP("mmc1-8bit-e", jz4760_mmc1_8bit_e, 1),
 953         INGENIC_PIN_GROUP("mmc2-1bit-b", jz4760_mmc2_1bit_b, 0),
 954         INGENIC_PIN_GROUP("mmc2-4bit-b", jz4760_mmc2_4bit_b, 0),
 955         INGENIC_PIN_GROUP("mmc2-1bit-e", jz4760_mmc2_1bit_e, 2),
 956         INGENIC_PIN_GROUP("mmc2-4bit-e", jz4760_mmc2_4bit_e, 2),
 957         INGENIC_PIN_GROUP("mmc2-8bit-e", jz4760_mmc2_8bit_e, 2),
 958         INGENIC_PIN_GROUP("nemc-8bit-data", jz4760_nemc_8bit_data, 0),
 959         INGENIC_PIN_GROUP("nemc-16bit-data", jz4760_nemc_16bit_data, 0),
 960         INGENIC_PIN_GROUP("nemc-cle-ale", jz4760_nemc_cle_ale, 0),
 961         INGENIC_PIN_GROUP("nemc-addr", jz4760_nemc_addr, 0),
 962         INGENIC_PIN_GROUP("nemc-rd-we", jz4760_nemc_rd_we, 0),
 963         INGENIC_PIN_GROUP("nemc-frd-fwe", jz4760_nemc_frd_fwe, 0),
 964         INGENIC_PIN_GROUP("nemc-wait", jz4760_nemc_wait, 0),
 965         INGENIC_PIN_GROUP("nemc-cs1", jz4760_nemc_cs1, 0),
 966         INGENIC_PIN_GROUP("nemc-cs2", jz4760_nemc_cs2, 0),
 967         INGENIC_PIN_GROUP("nemc-cs3", jz4760_nemc_cs3, 0),
 968         INGENIC_PIN_GROUP("nemc-cs4", jz4760_nemc_cs4, 0),
 969         INGENIC_PIN_GROUP("nemc-cs5", jz4760_nemc_cs5, 0),
 970         INGENIC_PIN_GROUP("nemc-cs6", jz4760_nemc_cs6, 0),
 971         INGENIC_PIN_GROUP("i2c0-data", jz4760_i2c0, 0),
 972         INGENIC_PIN_GROUP("i2c1-data", jz4760_i2c1, 0),
 973         INGENIC_PIN_GROUP("cim-data", jz4760_cim, 0),
 974         INGENIC_PIN_GROUP("lcd-8bit", jz4760_lcd_8bit, 0),
 975         INGENIC_PIN_GROUP("lcd-16bit", jz4760_lcd_16bit, 0),
 976         INGENIC_PIN_GROUP("lcd-18bit", jz4760_lcd_18bit, 0),
 977         INGENIC_PIN_GROUP("lcd-24bit", jz4760_lcd_24bit, 0),
 978         INGENIC_PIN_GROUP("lcd-special", jz4760_lcd_special, 1),
 979         INGENIC_PIN_GROUP("lcd-generic", jz4760_lcd_generic, 0),
 980         INGENIC_PIN_GROUP("pwm0", jz4760_pwm_pwm0, 0),
 981         INGENIC_PIN_GROUP("pwm1", jz4760_pwm_pwm1, 0),
 982         INGENIC_PIN_GROUP("pwm2", jz4760_pwm_pwm2, 0),
 983         INGENIC_PIN_GROUP("pwm3", jz4760_pwm_pwm3, 0),
 984         INGENIC_PIN_GROUP("pwm4", jz4760_pwm_pwm4, 0),
 985         INGENIC_PIN_GROUP("pwm5", jz4760_pwm_pwm5, 0),
 986         INGENIC_PIN_GROUP("pwm6", jz4760_pwm_pwm6, 0),
 987         INGENIC_PIN_GROUP("pwm7", jz4760_pwm_pwm7, 0),
 988         INGENIC_PIN_GROUP("otg-vbus", jz4760_otg, 0),
 989 };
 990
 991 static const char *jz4760_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
 992 static const char *jz4760_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
 993 static const char *jz4760_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
 994 static const char *jz4760_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
 995 static const char *jz4760_ssi0_groups[] = {
 996         "ssi0-dt-a", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",
 997         "ssi0-dr-a", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",
 998         "ssi0-clk-a", "ssi0-clk-b", "ssi0-clk-d", "ssi0-clk-e",
 999         "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",
1000         "ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
1001         "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",
1002 };
1003 static const char *jz4760_ssi1_groups[] = {
1004         "ssi1-dt-b-9", "ssi1-dt-b-21", "ssi1-dt-d-12", "ssi1-dt-d-21", "ssi1-dt-e", "ssi1-dt-f",
1005         "ssi1-dr-b-6", "ssi1-dr-b-20", "ssi1-dr-d-13", "ssi1-dr-d-20", "ssi1-dr-e", "ssi1-dr-f",
1006         "ssi1-clk-b-7", "ssi1-clk-b-28", "ssi1-clk-d", "ssi1-clk-e-7", "ssi1-clk-e-15", "ssi1-clk-f",
1007         "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",
1008         "ssi1-ce0-b-8", "ssi1-ce0-b-29", "ssi1-ce0-d", "ssi1-ce0-e-6", "ssi1-ce0-e-16", "ssi1-ce0-f",
1009         "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",
1010 };
1011 static const char *jz4760_mmc0_groups[] = {
1012         "mmc0-1bit-a", "mmc0-4bit-a",
1013         "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
1014 };
1015 static const char *jz4760_mmc1_groups[] = {
1016         "mmc1-1bit-d", "mmc1-4bit-d",
1017         "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
1018 };
1019 static const char *jz4760_mmc2_groups[] = {
1020         "mmc2-1bit-b", "mmc2-4bit-b",
1021         "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
1022 };
1023 static const char *jz4760_nemc_groups[] = {
1024         "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
1025         "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
1026 };
1027 static const char *jz4760_cs1_groups[] = { "nemc-cs1", };
1028 static const char *jz4760_cs2_groups[] = { "nemc-cs2", };
1029 static const char *jz4760_cs3_groups[] = { "nemc-cs3", };
1030 static const char *jz4760_cs4_groups[] = { "nemc-cs4", };
1031 static const char *jz4760_cs5_groups[] = { "nemc-cs5", };
1032 static const char *jz4760_cs6_groups[] = { "nemc-cs6", };
1033 static const char *jz4760_i2c0_groups[] = { "i2c0-data", };
1034 static const char *jz4760_i2c1_groups[] = { "i2c1-data", };
1035 static const char *jz4760_cim_groups[] = { "cim-data", };
1036 static const char *jz4760_lcd_groups[] = {
1037         "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
1038         "lcd-special", "lcd-generic",
1039 };
1040 static const char *jz4760_pwm0_groups[] = { "pwm0", };
1041 static const char *jz4760_pwm1_groups[] = { "pwm1", };
1042 static const char *jz4760_pwm2_groups[] = { "pwm2", };
1043 static const char *jz4760_pwm3_groups[] = { "pwm3", };
1044 static const char *jz4760_pwm4_groups[] = { "pwm4", };
1045 static const char *jz4760_pwm5_groups[] = { "pwm5", };
1046 static const char *jz4760_pwm6_groups[] = { "pwm6", };
1047 static const char *jz4760_pwm7_groups[] = { "pwm7", };
1048 static const char *jz4760_otg_groups[] = { "otg-vbus", };
1049
1050 static const struct function_desc jz4760_functions[] = {
1051         { "uart0", jz4760_uart0_groups, ARRAY_SIZE(jz4760_uart0_groups), },
1052         { "uart1", jz4760_uart1_groups, ARRAY_SIZE(jz4760_uart1_groups), },
1053         { "uart2", jz4760_uart2_groups, ARRAY_SIZE(jz4760_uart2_groups), },
1054         { "uart3", jz4760_uart3_groups, ARRAY_SIZE(jz4760_uart3_groups), },
1055         { "ssi0", jz4760_ssi0_groups, ARRAY_SIZE(jz4760_ssi0_groups), },
1056         { "ssi1", jz4760_ssi1_groups, ARRAY_SIZE(jz4760_ssi1_groups), },
1057         { "mmc0", jz4760_mmc0_groups, ARRAY_SIZE(jz4760_mmc0_groups), },
1058         { "mmc1", jz4760_mmc1_groups, ARRAY_SIZE(jz4760_mmc1_groups), },
1059         { "mmc2", jz4760_mmc2_groups, ARRAY_SIZE(jz4760_mmc2_groups), },
1060         { "nemc", jz4760_nemc_groups, ARRAY_SIZE(jz4760_nemc_groups), },
1061         { "nemc-cs1", jz4760_cs1_groups, ARRAY_SIZE(jz4760_cs1_groups), },
1062         { "nemc-cs2", jz4760_cs2_groups, ARRAY_SIZE(jz4760_cs2_groups), },
1063         { "nemc-cs3", jz4760_cs3_groups, ARRAY_SIZE(jz4760_cs3_groups), },
1064         { "nemc-cs4", jz4760_cs4_groups, ARRAY_SIZE(jz4760_cs4_groups), },
1065         { "nemc-cs5", jz4760_cs5_groups, ARRAY_SIZE(jz4760_cs5_groups), },
1066         { "nemc-cs6", jz4760_cs6_groups, ARRAY_SIZE(jz4760_cs6_groups), },
1067         { "i2c0", jz4760_i2c0_groups, ARRAY_SIZE(jz4760_i2c0_groups), },
1068         { "i2c1", jz4760_i2c1_groups, ARRAY_SIZE(jz4760_i2c1_groups), },
1069         { "cim", jz4760_cim_groups, ARRAY_SIZE(jz4760_cim_groups), },
1070         { "lcd", jz4760_lcd_groups, ARRAY_SIZE(jz4760_lcd_groups), },
1071         { "pwm0", jz4760_pwm0_groups, ARRAY_SIZE(jz4760_pwm0_groups), },
1072         { "pwm1", jz4760_pwm1_groups, ARRAY_SIZE(jz4760_pwm1_groups), },
1073         { "pwm2", jz4760_pwm2_groups, ARRAY_SIZE(jz4760_pwm2_groups), },
1074         { "pwm3", jz4760_pwm3_groups, ARRAY_SIZE(jz4760_pwm3_groups), },
1075         { "pwm4", jz4760_pwm4_groups, ARRAY_SIZE(jz4760_pwm4_groups), },
1076         { "pwm5", jz4760_pwm5_groups, ARRAY_SIZE(jz4760_pwm5_groups), },
1077         { "pwm6", jz4760_pwm6_groups, ARRAY_SIZE(jz4760_pwm6_groups), },
1078         { "pwm7", jz4760_pwm7_groups, ARRAY_SIZE(jz4760_pwm7_groups), },
1079         { "otg", jz4760_otg_groups, ARRAY_SIZE(jz4760_otg_groups), },
1080 };
1081
1082 static const struct ingenic_chip_info jz4760_chip_info = {
1083         .num_chips = 6,
1084         .reg_offset = 0x100,
1085         .version = ID_JZ4760,
1086         .groups = jz4760_groups,
1087         .num_groups = ARRAY_SIZE(jz4760_groups),
1088         .functions = jz4760_functions,
1089         .num_functions = ARRAY_SIZE(jz4760_functions),
1090         .pull_ups = jz4760_pull_ups,
1091         .pull_downs = jz4760_pull_downs,
1092 };
1093
1094 static const u32 jz4770_pull_ups[6] = {
1095         0x3fffffff, 0xfff0f3fc, 0xffffffff, 0xffff4fff, 0xfffffb7c, 0x0024f00f,
1096 };
1097
1098 static const u32 jz4770_pull_downs[6] = {
1099         0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x005b0ff0,
1100 };
1101
1102 static int jz4770_uart0_data_pins[] = { 0xa0, 0xa3, };
1103 static int jz4770_uart0_hwflow_pins[] = { 0xa1, 0xa2, };
1104 static int jz4770_uart1_data_pins[] = { 0x7a, 0x7c, };
1105 static int jz4770_uart1_hwflow_pins[] = { 0x7b, 0x7d, };
1106 static int jz4770_uart2_data_pins[] = { 0x5c, 0x5e, };
1107 static int jz4770_uart2_hwflow_pins[] = { 0x5d, 0x5f, };
1108 static int jz4770_uart3_data_pins[] = { 0x6c, 0x85, };
1109 static int jz4770_uart3_hwflow_pins[] = { 0x88, 0x89, };
1110 static int jz4770_ssi0_dt_a_pins[] = { 0x15, };
1111 static int jz4770_ssi0_dt_b_pins[] = { 0x35, };
1112 static int jz4770_ssi0_dt_d_pins[] = { 0x75, };
1113 static int jz4770_ssi0_dt_e_pins[] = { 0x91, };
1114 static int jz4770_ssi0_dr_a_pins[] = { 0x14, };
1115 static int jz4770_ssi0_dr_b_pins[] = { 0x34, };
1116 static int jz4770_ssi0_dr_d_pins[] = { 0x74, };
1117 static int jz4770_ssi0_dr_e_pins[] = { 0x8e, };
1118 static int jz4770_ssi0_clk_a_pins[] = { 0x12, };
1119 static int jz4770_ssi0_clk_b_pins[] = { 0x3c, };
1120 static int jz4770_ssi0_clk_d_pins[] = { 0x78, };
1121 static int jz4770_ssi0_clk_e_pins[] = { 0x8f, };
1122 static int jz4770_ssi0_gpc_b_pins[] = { 0x3e, };
1123 static int jz4770_ssi0_gpc_d_pins[] = { 0x76, };
1124 static int jz4770_ssi0_gpc_e_pins[] = { 0x93, };
1125 static int jz4770_ssi0_ce0_a_pins[] = { 0x13, };
1126 static int jz4770_ssi0_ce0_b_pins[] = { 0x3d, };
1127 static int jz4770_ssi0_ce0_d_pins[] = { 0x79, };
1128 static int jz4770_ssi0_ce0_e_pins[] = { 0x90, };
1129 static int jz4770_ssi0_ce1_b_pins[] = { 0x3f, };
1130 static int jz4770_ssi0_ce1_d_pins[] = { 0x77, };
1131 static int jz4770_ssi0_ce1_e_pins[] = { 0x92, };
1132 static int jz4770_ssi1_dt_b_pins[] = { 0x35, };
1133 static int jz4770_ssi1_dt_d_pins[] = { 0x75, };
1134 static int jz4770_ssi1_dt_e_pins[] = { 0x91, };
1135 static int jz4770_ssi1_dr_b_pins[] = { 0x34, };
1136 static int jz4770_ssi1_dr_d_pins[] = { 0x74, };
1137 static int jz4770_ssi1_dr_e_pins[] = { 0x8e, };
1138 static int jz4770_ssi1_clk_b_pins[] = { 0x3c, };
1139 static int jz4770_ssi1_clk_d_pins[] = { 0x78, };
1140 static int jz4770_ssi1_clk_e_pins[] = { 0x8f, };
1141 static int jz4770_ssi1_gpc_b_pins[] = { 0x3e, };
1142 static int jz4770_ssi1_gpc_d_pins[] = { 0x76, };
1143 static int jz4770_ssi1_gpc_e_pins[] = { 0x93, };
1144 static int jz4770_ssi1_ce0_b_pins[] = { 0x3d, };
1145 static int jz4770_ssi1_ce0_d_pins[] = { 0x79, };
1146 static int jz4770_ssi1_ce0_e_pins[] = { 0x90, };
1147 static int jz4770_ssi1_ce1_b_pins[] = { 0x3f, };
1148 static int jz4770_ssi1_ce1_d_pins[] = { 0x77, };
1149 static int jz4770_ssi1_ce1_e_pins[] = { 0x92, };
1150 static int jz4770_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
1151 static int jz4770_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
1152 static int jz4770_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
1153 static int jz4770_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
1154 static int jz4770_mmc0_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
1155 static int jz4770_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };
1156 static int jz4770_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
1157 static int jz4770_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
1158 static int jz4770_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
1159 static int jz4770_mmc1_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
1160 static int jz4770_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };
1161 static int jz4770_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };
1162 static int jz4770_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
1163 static int jz4770_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
1164 static int jz4770_mmc2_8bit_e_pins[] = { 0x98, 0x99, 0x9a, 0x9b, };
1165 static int jz4770_nemc_8bit_data_pins[] = {
1166         0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
1167 };
1168 static int jz4770_nemc_16bit_data_pins[] = {
1169         0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
1170 };
1171 static int jz4770_nemc_cle_ale_pins[] = { 0x20, 0x21, };
1172 static int jz4770_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
1173 static int jz4770_nemc_rd_we_pins[] = { 0x10, 0x11, };
1174 static int jz4770_nemc_frd_fwe_pins[] = { 0x12, 0x13, };
1175 static int jz4770_nemc_wait_pins[] = { 0x1b, };
1176 static int jz4770_nemc_cs1_pins[] = { 0x15, };
1177 static int jz4770_nemc_cs2_pins[] = { 0x16, };
1178 static int jz4770_nemc_cs3_pins[] = { 0x17, };
1179 static int jz4770_nemc_cs4_pins[] = { 0x18, };
1180 static int jz4770_nemc_cs5_pins[] = { 0x19, };
1181 static int jz4770_nemc_cs6_pins[] = { 0x1a, };
1182 static int jz4770_i2c0_pins[] = { 0x7e, 0x7f, };
1183 static int jz4770_i2c1_pins[] = { 0x9e, 0x9f, };
1184 static int jz4770_i2c2_pins[] = { 0xb0, 0xb1, };
1185 static int jz4770_cim_8bit_pins[] = {
1186         0x26, 0x27, 0x28, 0x29,
1187         0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
1188 };
1189 static int jz4770_cim_12bit_pins[] = {
1190         0x32, 0x33, 0xb0, 0xb1,
1191 };
1192 static int jz4770_lcd_8bit_pins[] = {
1193         0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x4c, 0x4d,
1194         0x48, 0x52, 0x53,
1195 };
1196 static int jz4770_lcd_16bit_pins[] = {
1197         0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59,
1198 };
1199 static int jz4770_lcd_18bit_pins[] = {
1200         0x5a, 0x5b,
1201 };
1202 static int jz4770_lcd_24bit_pins[] = {
1203         0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
1204         0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
1205         0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
1206         0x58, 0x59, 0x5a, 0x5b,
1207 };
1208 static int jz4770_lcd_special_pins[] = { 0x54, 0x4a, 0x41, 0x40, };
1209 static int jz4770_lcd_generic_pins[] = { 0x49, };
1210 static int jz4770_pwm_pwm0_pins[] = { 0x80, };
1211 static int jz4770_pwm_pwm1_pins[] = { 0x81, };
1212 static int jz4770_pwm_pwm2_pins[] = { 0x82, };
1213 static int jz4770_pwm_pwm3_pins[] = { 0x83, };
1214 static int jz4770_pwm_pwm4_pins[] = { 0x84, };
1215 static int jz4770_pwm_pwm5_pins[] = { 0x85, };
1216 static int jz4770_pwm_pwm6_pins[] = { 0x6a, };
1217 static int jz4770_pwm_pwm7_pins[] = { 0x6b, };
1218 static int jz4770_mac_rmii_pins[] = {
1219         0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8,
1220 };
1221 static int jz4770_mac_mii_pins[] = {
1222         0x7b, 0x7a, 0x7d, 0x7c, 0xa7, 0x24, 0xaf,
1223 };
1224
1225 static const struct group_desc jz4770_groups[] = {
1226         INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0),
1227         INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0),
1228         INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data, 0),
1229         INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow, 0),
1230         INGENIC_PIN_GROUP("uart2-data", jz4770_uart2_data, 0),
1231         INGENIC_PIN_GROUP("uart2-hwflow", jz4770_uart2_hwflow, 0),
1232         INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4770_uart3_data,
1233                                 jz4760_uart3_data_funcs),
1234         INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow, 0),
1235         INGENIC_PIN_GROUP("ssi0-dt-a", jz4770_ssi0_dt_a, 2),
1236         INGENIC_PIN_GROUP("ssi0-dt-b", jz4770_ssi0_dt_b, 1),
1237         INGENIC_PIN_GROUP("ssi0-dt-d", jz4770_ssi0_dt_d, 1),
1238         INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e, 0),
1239         INGENIC_PIN_GROUP("ssi0-dr-a", jz4770_ssi0_dr_a, 1),
1240         INGENIC_PIN_GROUP("ssi0-dr-b", jz4770_ssi0_dr_b, 1),
1241         INGENIC_PIN_GROUP("ssi0-dr-d", jz4770_ssi0_dr_d, 1),
1242         INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e, 0),
1243         INGENIC_PIN_GROUP("ssi0-clk-a", jz4770_ssi0_clk_a, 2),
1244         INGENIC_PIN_GROUP("ssi0-clk-b", jz4770_ssi0_clk_b, 1),
1245         INGENIC_PIN_GROUP("ssi0-clk-d", jz4770_ssi0_clk_d, 1),
1246         INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e, 0),
1247         INGENIC_PIN_GROUP("ssi0-gpc-b", jz4770_ssi0_gpc_b, 1),
1248         INGENIC_PIN_GROUP("ssi0-gpc-d", jz4770_ssi0_gpc_d, 1),
1249         INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e, 0),
1250         INGENIC_PIN_GROUP("ssi0-ce0-a", jz4770_ssi0_ce0_a, 2),
1251         INGENIC_PIN_GROUP("ssi0-ce0-b", jz4770_ssi0_ce0_b, 1),
1252         INGENIC_PIN_GROUP("ssi0-ce0-d", jz4770_ssi0_ce0_d, 1),
1253         INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e, 0),
1254         INGENIC_PIN_GROUP("ssi0-ce1-b", jz4770_ssi0_ce1_b, 1),
1255         INGENIC_PIN_GROUP("ssi0-ce1-d", jz4770_ssi0_ce1_d, 1),
1256         INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e, 0),
1257         INGENIC_PIN_GROUP("ssi1-dt-b", jz4770_ssi1_dt_b, 2),
1258         INGENIC_PIN_GROUP("ssi1-dt-d", jz4770_ssi1_dt_d, 2),
1259         INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e, 1),
1260         INGENIC_PIN_GROUP("ssi1-dr-b", jz4770_ssi1_dr_b, 2),
1261         INGENIC_PIN_GROUP("ssi1-dr-d", jz4770_ssi1_dr_d, 2),
1262         INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e, 1),
1263         INGENIC_PIN_GROUP("ssi1-clk-b", jz4770_ssi1_clk_b, 2),
1264         INGENIC_PIN_GROUP("ssi1-clk-d", jz4770_ssi1_clk_d, 2),
1265         INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e, 1),
1266         INGENIC_PIN_GROUP("ssi1-gpc-b", jz4770_ssi1_gpc_b, 2),
1267         INGENIC_PIN_GROUP("ssi1-gpc-d", jz4770_ssi1_gpc_d, 2),
1268         INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e, 1),
1269         INGENIC_PIN_GROUP("ssi1-ce0-b", jz4770_ssi1_ce0_b, 2),
1270         INGENIC_PIN_GROUP("ssi1-ce0-d", jz4770_ssi1_ce0_d, 2),
1271         INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e, 1),
1272         INGENIC_PIN_GROUP("ssi1-ce1-b", jz4770_ssi1_ce1_b, 2),
1273         INGENIC_PIN_GROUP("ssi1-ce1-d", jz4770_ssi1_ce1_d, 2),
1274         INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e, 1),
1275         INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4770_mmc0_1bit_a,
1276                                 jz4760_mmc0_1bit_a_funcs),
1277         INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a, 1),
1278         INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e, 0),
1279         INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e, 0),
1280         INGENIC_PIN_GROUP("mmc0-8bit-e", jz4770_mmc0_8bit_e, 0),
1281         INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d, 0),
1282         INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d, 0),
1283         INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e, 1),
1284         INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e, 1),
1285         INGENIC_PIN_GROUP("mmc1-8bit-e", jz4770_mmc1_8bit_e, 1),
1286         INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b, 0),
1287         INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b, 0),
1288         INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e, 2),
1289         INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e, 2),
1290         INGENIC_PIN_GROUP("mmc2-8bit-e", jz4770_mmc2_8bit_e, 2),
1291         INGENIC_PIN_GROUP("nemc-8bit-data", jz4770_nemc_8bit_data, 0),
1292         INGENIC_PIN_GROUP("nemc-16bit-data", jz4770_nemc_16bit_data, 0),
1293         INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale, 0),
1294         INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr, 0),
1295         INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we, 0),
1296         INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe, 0),
1297         INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait, 0),
1298         INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1, 0),
1299         INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2, 0),
1300         INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3, 0),
1301         INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4, 0),
1302         INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5, 0),
1303         INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6, 0),
1304         INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0, 0),
1305         INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1, 0),
1306         INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2),
1307         INGENIC_PIN_GROUP("cim-data-8bit", jz4770_cim_8bit, 0),
1308         INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0),
1309         INGENIC_PIN_GROUP("lcd-8bit", jz4770_lcd_8bit, 0),
1310         INGENIC_PIN_GROUP("lcd-16bit", jz4770_lcd_16bit, 0),
1311         INGENIC_PIN_GROUP("lcd-18bit", jz4770_lcd_18bit, 0),
1312         INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0),
1313         INGENIC_PIN_GROUP("lcd-special", jz4770_lcd_special, 1),
1314         INGENIC_PIN_GROUP("lcd-generic", jz4770_lcd_generic, 0),
1315         INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0, 0),
1316         INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1, 0),
1317         INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2, 0),
1318         INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3, 0),
1319         INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4, 0),
1320         INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5, 0),
1321         INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6, 0),
1322         INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7, 0),
1323         INGENIC_PIN_GROUP("mac-rmii", jz4770_mac_rmii, 0),
1324         INGENIC_PIN_GROUP("mac-mii", jz4770_mac_mii, 0),
1325         INGENIC_PIN_GROUP("otg-vbus", jz4760_otg, 0),
1326 };
1327
1328 static const char *jz4770_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1329 static const char *jz4770_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
1330 static const char *jz4770_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
1331 static const char *jz4770_uart3_groups[] = { "uart3-data", "uart3-hwflow", };
1332 static const char *jz4770_ssi0_groups[] = {
1333         "ssi0-dt-a", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",
1334         "ssi0-dr-a", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",
1335         "ssi0-clk-a", "ssi0-clk-b", "ssi0-clk-d", "ssi0-clk-e",
1336         "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",
1337         "ssi0-ce0-a", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
1338         "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",
1339 };
1340 static const char *jz4770_ssi1_groups[] = {
1341         "ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e",
1342         "ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e",
1343         "ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e",
1344         "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",
1345         "ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e",
1346         "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",
1347 };
1348 static const char *jz4770_mmc0_groups[] = {
1349         "mmc0-1bit-a", "mmc0-4bit-a",
1350         "mmc0-1bit-e", "mmc0-4bit-e", "mmc0-8bit-e",
1351 };
1352 static const char *jz4770_mmc1_groups[] = {
1353         "mmc1-1bit-d", "mmc1-4bit-d",
1354         "mmc1-1bit-e", "mmc1-4bit-e", "mmc1-8bit-e",
1355 };
1356 static const char *jz4770_mmc2_groups[] = {
1357         "mmc2-1bit-b", "mmc2-4bit-b",
1358         "mmc2-1bit-e", "mmc2-4bit-e", "mmc2-8bit-e",
1359 };
1360 static const char *jz4770_nemc_groups[] = {
1361         "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
1362         "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
1363 };
1364 static const char *jz4770_cs1_groups[] = { "nemc-cs1", };
1365 static const char *jz4770_cs2_groups[] = { "nemc-cs2", };
1366 static const char *jz4770_cs3_groups[] = { "nemc-cs3", };
1367 static const char *jz4770_cs4_groups[] = { "nemc-cs4", };
1368 static const char *jz4770_cs5_groups[] = { "nemc-cs5", };
1369 static const char *jz4770_cs6_groups[] = { "nemc-cs6", };
1370 static const char *jz4770_i2c0_groups[] = { "i2c0-data", };
1371 static const char *jz4770_i2c1_groups[] = { "i2c1-data", };
1372 static const char *jz4770_i2c2_groups[] = { "i2c2-data", };
1373 static const char *jz4770_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", };
1374 static const char *jz4770_lcd_groups[] = {
1375         "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
1376         "lcd-special", "lcd-generic",
1377 };
1378 static const char *jz4770_pwm0_groups[] = { "pwm0", };
1379 static const char *jz4770_pwm1_groups[] = { "pwm1", };
1380 static const char *jz4770_pwm2_groups[] = { "pwm2", };
1381 static const char *jz4770_pwm3_groups[] = { "pwm3", };
1382 static const char *jz4770_pwm4_groups[] = { "pwm4", };
1383 static const char *jz4770_pwm5_groups[] = { "pwm5", };
1384 static const char *jz4770_pwm6_groups[] = { "pwm6", };
1385 static const char *jz4770_pwm7_groups[] = { "pwm7", };
1386 static const char *jz4770_mac_groups[] = { "mac-rmii", "mac-mii", };
1387
1388 static const struct function_desc jz4770_functions[] = {
1389         { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
1390         { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), },
1391         { "uart2", jz4770_uart2_groups, ARRAY_SIZE(jz4770_uart2_groups), },
1392         { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), },
1393         { "ssi0", jz4770_ssi0_groups, ARRAY_SIZE(jz4770_ssi0_groups), },
1394         { "ssi1", jz4770_ssi1_groups, ARRAY_SIZE(jz4770_ssi1_groups), },
1395         { "mmc0", jz4770_mmc0_groups, ARRAY_SIZE(jz4770_mmc0_groups), },
1396         { "mmc1", jz4770_mmc1_groups, ARRAY_SIZE(jz4770_mmc1_groups), },
1397         { "mmc2", jz4770_mmc2_groups, ARRAY_SIZE(jz4770_mmc2_groups), },
1398         { "nemc", jz4770_nemc_groups, ARRAY_SIZE(jz4770_nemc_groups), },
1399         { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
1400         { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
1401         { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), },
1402         { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), },
1403         { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), },
1404         { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), },
1405         { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), },
1406         { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), },
1407         { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), },
1408         { "cim", jz4770_cim_groups, ARRAY_SIZE(jz4770_cim_groups), },
1409         { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), },
1410         { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), },
1411         { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), },
1412         { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), },
1413         { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), },
1414         { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), },
1415         { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), },
1416         { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), },
1417         { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), },
1418         { "mac", jz4770_mac_groups, ARRAY_SIZE(jz4770_mac_groups), },
1419         { "otg", jz4760_otg_groups, ARRAY_SIZE(jz4760_otg_groups), },
1420 };
1421
1422 static const struct ingenic_chip_info jz4770_chip_info = {
1423         .num_chips = 6,
1424         .reg_offset = 0x100,
1425         .version = ID_JZ4770,
1426         .groups = jz4770_groups,
1427         .num_groups = ARRAY_SIZE(jz4770_groups),
1428         .functions = jz4770_functions,
1429         .num_functions = ARRAY_SIZE(jz4770_functions),
1430         .pull_ups = jz4770_pull_ups,
1431         .pull_downs = jz4770_pull_downs,
1432 };
1433
1434 static const u32 jz4775_pull_ups[7] = {
1435         0x28ff00ff, 0xf030f3fc, 0x0fffffff, 0xfffe4000, 0xf0f0000c, 0x0000f00f, 0x0000f3c0,
1436 };
1437
1438 static const u32 jz4775_pull_downs[7] = {
1439         0x00000000, 0x00030c03, 0x00000000, 0x00008000, 0x00000403, 0x00000ff0, 0x00030c00,
1440 };
1441
1442 static int jz4775_uart0_data_pins[] = { 0xa0, 0xa3, };
1443 static int jz4775_uart0_hwflow_pins[] = { 0xa1, 0xa2, };
1444 static int jz4775_uart1_data_pins[] = { 0x7a, 0x7c, };
1445 static int jz4775_uart1_hwflow_pins[] = { 0x7b, 0x7d, };
1446 static int jz4775_uart2_data_c_pins[] = { 0x54, 0x4a, };
1447 static int jz4775_uart2_data_f_pins[] = { 0xa5, 0xa4, };
1448 static int jz4775_uart3_data_pins[] = { 0x1e, 0x1f, };
1449 static int jz4775_ssi_dt_a_pins[] = { 0x13, };
1450 static int jz4775_ssi_dt_d_pins[] = { 0x75, };
1451 static int jz4775_ssi_dr_a_pins[] = { 0x14, };
1452 static int jz4775_ssi_dr_d_pins[] = { 0x74, };
1453 static int jz4775_ssi_clk_a_pins[] = { 0x12, };
1454 static int jz4775_ssi_clk_d_pins[] = { 0x78, };
1455 static int jz4775_ssi_gpc_pins[] = { 0x76, };
1456 static int jz4775_ssi_ce0_a_pins[] = { 0x17, };
1457 static int jz4775_ssi_ce0_d_pins[] = { 0x79, };
1458 static int jz4775_ssi_ce1_pins[] = { 0x77, };
1459 static int jz4775_mmc0_1bit_a_pins[] = { 0x12, 0x13, 0x14, };
1460 static int jz4775_mmc0_4bit_a_pins[] = { 0x15, 0x16, 0x17, };
1461 static int jz4775_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, };
1462 static int jz4775_mmc0_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
1463 static int jz4775_mmc0_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
1464 static int jz4775_mmc1_1bit_d_pins[] = { 0x78, 0x79, 0x74, };
1465 static int jz4775_mmc1_4bit_d_pins[] = { 0x75, 0x76, 0x77, };
1466 static int jz4775_mmc1_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
1467 static int jz4775_mmc1_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
1468 static int jz4775_mmc2_1bit_b_pins[] = { 0x3c, 0x3d, 0x34, };
1469 static int jz4775_mmc2_4bit_b_pins[] = { 0x35, 0x3e, 0x3f, };
1470 static int jz4775_mmc2_1bit_e_pins[] = { 0x9c, 0x9d, 0x94, };
1471 static int jz4775_mmc2_4bit_e_pins[] = { 0x95, 0x96, 0x97, };
1472 static int jz4775_nemc_8bit_data_pins[] = {
1473         0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
1474 };
1475 static int jz4775_nemc_16bit_data_pins[] = {
1476         0xca, 0xcb, 0xcc, 0xcd, 0xce, 0xcf, 0xd0, 0xd1,
1477 };
1478 static int jz4775_nemc_cle_ale_pins[] = { 0x20, 0x21, };
1479 static int jz4775_nemc_addr_pins[] = { 0x22, 0x23, 0x24, 0x25, };
1480 static int jz4775_nemc_rd_we_pins[] = { 0x10, 0x11, };
1481 static int jz4775_nemc_frd_fwe_pins[] = { 0x12, 0x13, };
1482 static int jz4775_nemc_wait_pins[] = { 0x1b, };
1483 static int jz4775_nemc_cs1_pins[] = { 0x15, };
1484 static int jz4775_nemc_cs2_pins[] = { 0x16, };
1485 static int jz4775_nemc_cs3_pins[] = { 0x17, };
1486 static int jz4775_i2c0_pins[] = { 0x7e, 0x7f, };
1487 static int jz4775_i2c1_pins[] = { 0x9e, 0x9f, };
1488 static int jz4775_i2c2_pins[] = { 0x80, 0x83, };
1489 static int jz4775_i2s_data_tx_pins[] = { 0xa3, };
1490 static int jz4775_i2s_data_rx_pins[] = { 0xa2, };
1491 static int jz4775_i2s_clk_txrx_pins[] = { 0xa0, 0xa1, };
1492 static int jz4775_i2s_sysclk_pins[] = { 0x83, };
1493 static int jz4775_dmic_pins[] = { 0xaa, 0xab, };
1494 static int jz4775_cim_pins[] = {
1495         0x26, 0x27, 0x28, 0x29,
1496         0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31,
1497 };
1498 static int jz4775_lcd_8bit_pins[] = {
1499         0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x4c, 0x4d,
1500         0x48, 0x52, 0x53,
1501 };
1502 static int jz4775_lcd_16bit_pins[] = {
1503         0x4e, 0x4f, 0x50, 0x51, 0x56, 0x57, 0x58, 0x59,
1504 };
1505 static int jz4775_lcd_18bit_pins[] = {
1506         0x5a, 0x5b,
1507 };
1508 static int jz4775_lcd_24bit_pins[] = {
1509         0x40, 0x41, 0x4a, 0x4b, 0x54, 0x55,
1510 };
1511 static int jz4775_lcd_special_pins[] = { 0x54, 0x4a, 0x41, 0x40, };
1512 static int jz4775_lcd_generic_pins[] = { 0x49, };
1513 static int jz4775_pwm_pwm0_pins[] = { 0x80, };
1514 static int jz4775_pwm_pwm1_pins[] = { 0x81, };
1515 static int jz4775_pwm_pwm2_pins[] = { 0x82, };
1516 static int jz4775_pwm_pwm3_pins[] = { 0x83, };
1517 static int jz4775_mac_rmii_pins[] = {
1518         0xa9, 0xab, 0xaa, 0xac, 0xa5, 0xa4, 0xad, 0xae, 0xa6, 0xa8,
1519 };
1520 static int jz4775_mac_mii_pins[] = {
1521         0x7b, 0x7a, 0x7d, 0x7c, 0xa7, 0x24, 0xaf,
1522 };
1523 static int jz4775_mac_rgmii_pins[] = {
1524         0xa9, 0x7b, 0x7a, 0xab, 0xaa, 0xac, 0x7d, 0x7c, 0xa5, 0xa4,
1525         0xad, 0xae, 0xa7, 0xa6,
1526 };
1527 static int jz4775_mac_gmii_pins[] = {
1528         0x31, 0x30, 0x2f, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a,
1529         0xa8, 0x28, 0x24, 0xaf,
1530 };
1531 static int jz4775_otg_pins[] = { 0x8a, };
1532
1533 static u8 jz4775_uart3_data_funcs[] = { 0, 1, };
1534 static u8 jz4775_mac_mii_funcs[] = { 1, 1, 1, 1, 0, 1, 0, };
1535 static u8 jz4775_mac_rgmii_funcs[] = {
1536         0, 1, 1, 0, 0, 0, 1, 1, 0, 0,
1537         0, 0, 0, 0,
1538 };
1539 static u8 jz4775_mac_gmii_funcs[] = {
1540         1, 1, 1, 1, 1, 1, 1, 1,
1541         0, 1, 1, 0,
1542 };
1543
1544 static const struct group_desc jz4775_groups[] = {
1545         INGENIC_PIN_GROUP("uart0-data", jz4775_uart0_data, 0),
1546         INGENIC_PIN_GROUP("uart0-hwflow", jz4775_uart0_hwflow, 0),
1547         INGENIC_PIN_GROUP("uart1-data", jz4775_uart1_data, 0),
1548         INGENIC_PIN_GROUP("uart1-hwflow", jz4775_uart1_hwflow, 0),
1549         INGENIC_PIN_GROUP("uart2-data-c", jz4775_uart2_data_c, 2),
1550         INGENIC_PIN_GROUP("uart2-data-f", jz4775_uart2_data_f, 1),
1551         INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4775_uart3_data,
1552                                 jz4775_uart3_data_funcs),
1553         INGENIC_PIN_GROUP("ssi-dt-a", jz4775_ssi_dt_a, 2),
1554         INGENIC_PIN_GROUP("ssi-dt-d", jz4775_ssi_dt_d, 1),
1555         INGENIC_PIN_GROUP("ssi-dr-a", jz4775_ssi_dr_a, 2),
1556         INGENIC_PIN_GROUP("ssi-dr-d", jz4775_ssi_dr_d, 1),
1557         INGENIC_PIN_GROUP("ssi-clk-a", jz4775_ssi_clk_a, 2),
1558         INGENIC_PIN_GROUP("ssi-clk-d", jz4775_ssi_clk_d, 1),
1559         INGENIC_PIN_GROUP("ssi-gpc", jz4775_ssi_gpc, 1),
1560         INGENIC_PIN_GROUP("ssi-ce0-a", jz4775_ssi_ce0_a, 2),
1561         INGENIC_PIN_GROUP("ssi-ce0-d", jz4775_ssi_ce0_d, 1),
1562         INGENIC_PIN_GROUP("ssi-ce1", jz4775_ssi_ce1, 1),
1563         INGENIC_PIN_GROUP("mmc0-1bit-a", jz4775_mmc0_1bit_a, 1),
1564         INGENIC_PIN_GROUP("mmc0-4bit-a", jz4775_mmc0_4bit_a, 1),
1565         INGENIC_PIN_GROUP("mmc0-8bit-a", jz4775_mmc0_8bit_a, 1),
1566         INGENIC_PIN_GROUP("mmc0-1bit-e", jz4775_mmc0_1bit_e, 0),
1567         INGENIC_PIN_GROUP("mmc0-4bit-e", jz4775_mmc0_4bit_e, 0),
1568         INGENIC_PIN_GROUP("mmc1-1bit-d", jz4775_mmc1_1bit_d, 0),
1569         INGENIC_PIN_GROUP("mmc1-4bit-d", jz4775_mmc1_4bit_d, 0),
1570         INGENIC_PIN_GROUP("mmc1-1bit-e", jz4775_mmc1_1bit_e, 1),
1571         INGENIC_PIN_GROUP("mmc1-4bit-e", jz4775_mmc1_4bit_e, 1),
1572         INGENIC_PIN_GROUP("mmc2-1bit-b", jz4775_mmc2_1bit_b, 0),
1573         INGENIC_PIN_GROUP("mmc2-4bit-b", jz4775_mmc2_4bit_b, 0),
1574         INGENIC_PIN_GROUP("mmc2-1bit-e", jz4775_mmc2_1bit_e, 2),
1575         INGENIC_PIN_GROUP("mmc2-4bit-e", jz4775_mmc2_4bit_e, 2),
1576         INGENIC_PIN_GROUP("nemc-8bit-data", jz4775_nemc_8bit_data, 0),
1577         INGENIC_PIN_GROUP("nemc-16bit-data", jz4775_nemc_16bit_data, 1),
1578         INGENIC_PIN_GROUP("nemc-cle-ale", jz4775_nemc_cle_ale, 0),
1579         INGENIC_PIN_GROUP("nemc-addr", jz4775_nemc_addr, 0),
1580         INGENIC_PIN_GROUP("nemc-rd-we", jz4775_nemc_rd_we, 0),
1581         INGENIC_PIN_GROUP("nemc-frd-fwe", jz4775_nemc_frd_fwe, 0),
1582         INGENIC_PIN_GROUP("nemc-wait", jz4775_nemc_wait, 0),
1583         INGENIC_PIN_GROUP("nemc-cs1", jz4775_nemc_cs1, 0),
1584         INGENIC_PIN_GROUP("nemc-cs2", jz4775_nemc_cs2, 0),
1585         INGENIC_PIN_GROUP("nemc-cs3", jz4775_nemc_cs3, 0),
1586         INGENIC_PIN_GROUP("i2c0-data", jz4775_i2c0, 0),
1587         INGENIC_PIN_GROUP("i2c1-data", jz4775_i2c1, 0),
1588         INGENIC_PIN_GROUP("i2c2-data", jz4775_i2c2, 1),
1589         INGENIC_PIN_GROUP("i2s-data-tx", jz4775_i2s_data_tx, 1),
1590         INGENIC_PIN_GROUP("i2s-data-rx", jz4775_i2s_data_rx, 1),
1591         INGENIC_PIN_GROUP("i2s-clk-txrx", jz4775_i2s_clk_txrx, 1),
1592         INGENIC_PIN_GROUP("i2s-sysclk", jz4775_i2s_sysclk, 2),
1593         INGENIC_PIN_GROUP("dmic", jz4775_dmic, 1),
1594         INGENIC_PIN_GROUP("cim-data", jz4775_cim, 0),
1595         INGENIC_PIN_GROUP("lcd-8bit", jz4775_lcd_8bit, 0),
1596         INGENIC_PIN_GROUP("lcd-16bit", jz4775_lcd_16bit, 0),
1597         INGENIC_PIN_GROUP("lcd-18bit", jz4775_lcd_18bit, 0),
1598         INGENIC_PIN_GROUP("lcd-24bit", jz4775_lcd_24bit, 0),
1599         INGENIC_PIN_GROUP("lcd-generic", jz4775_lcd_generic, 0),
1600         INGENIC_PIN_GROUP("lcd-special", jz4775_lcd_special, 1),
1601         INGENIC_PIN_GROUP("pwm0", jz4775_pwm_pwm0, 0),
1602         INGENIC_PIN_GROUP("pwm1", jz4775_pwm_pwm1, 0),
1603         INGENIC_PIN_GROUP("pwm2", jz4775_pwm_pwm2, 0),
1604         INGENIC_PIN_GROUP("pwm3", jz4775_pwm_pwm3, 0),
1605         INGENIC_PIN_GROUP("mac-rmii", jz4775_mac_rmii, 0),
1606         INGENIC_PIN_GROUP_FUNCS("mac-mii", jz4775_mac_mii,
1607                                 jz4775_mac_mii_funcs),
1608         INGENIC_PIN_GROUP_FUNCS("mac-rgmii", jz4775_mac_rgmii,
1609                                 jz4775_mac_rgmii_funcs),
1610         INGENIC_PIN_GROUP_FUNCS("mac-gmii", jz4775_mac_gmii,
1611                                 jz4775_mac_gmii_funcs),
1612         INGENIC_PIN_GROUP("otg-vbus", jz4775_otg, 0),
1613 };
1614
1615 static const char *jz4775_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
1616 static const char *jz4775_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
1617 static const char *jz4775_uart2_groups[] = { "uart2-data-c", "uart2-data-f", };
1618 static const char *jz4775_uart3_groups[] = { "uart3-data", };
1619 static const char *jz4775_ssi_groups[] = {
1620         "ssi-dt-a", "ssi-dt-d",
1621         "ssi-dr-a", "ssi-dr-d",
1622         "ssi-clk-a", "ssi-clk-d",
1623         "ssi-gpc",
1624         "ssi-ce0-a", "ssi-ce0-d",
1625         "ssi-ce1",
1626 };
1627 static const char *jz4775_mmc0_groups[] = {
1628         "mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a",
1629         "mmc0-1bit-e", "mmc0-4bit-e",
1630 };
1631 static const char *jz4775_mmc1_groups[] = {
1632         "mmc1-1bit-d", "mmc1-4bit-d",
1633         "mmc1-1bit-e", "mmc1-4bit-e",
1634 };
1635 static const char *jz4775_mmc2_groups[] = {
1636         "mmc2-1bit-b", "mmc2-4bit-b",
1637         "mmc2-1bit-e", "mmc2-4bit-e",
1638 };
1639 static const char *jz4775_nemc_groups[] = {
1640         "nemc-8bit-data", "nemc-16bit-data", "nemc-cle-ale",
1641         "nemc-addr", "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
1642 };
1643 static const char *jz4775_cs1_groups[] = { "nemc-cs1", };
1644 static const char *jz4775_cs2_groups[] = { "nemc-cs2", };
1645 static const char *jz4775_cs3_groups[] = { "nemc-cs3", };
1646 static const char *jz4775_i2c0_groups[] = { "i2c0-data", };
1647 static const char *jz4775_i2c1_groups[] = { "i2c1-data", };
1648 static const char *jz4775_i2c2_groups[] = { "i2c2-data", };
1649 static const char *jz4775_i2s_groups[] = {
1650         "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",
1651 };
1652 static const char *jz4775_dmic_groups[] = { "dmic", };
1653 static const char *jz4775_cim_groups[] = { "cim-data", };
1654 static const char *jz4775_lcd_groups[] = {
1655         "lcd-8bit", "lcd-16bit", "lcd-18bit", "lcd-24bit",
1656         "lcd-special", "lcd-generic",
1657 };
1658 static const char *jz4775_pwm0_groups[] = { "pwm0", };
1659 static const char *jz4775_pwm1_groups[] = { "pwm1", };
1660 static const char *jz4775_pwm2_groups[] = { "pwm2", };
1661 static const char *jz4775_pwm3_groups[] = { "pwm3", };
1662 static const char *jz4775_mac_groups[] = {
1663         "mac-rmii", "mac-mii", "mac-rgmii", "mac-gmii",
1664 };
1665 static const char *jz4775_otg_groups[] = { "otg-vbus", };
1666
1667 static const struct function_desc jz4775_functions[] = {
1668         { "uart0", jz4775_uart0_groups, ARRAY_SIZE(jz4775_uart0_groups), },
1669         { "uart1", jz4775_uart1_groups, ARRAY_SIZE(jz4775_uart1_groups), },
1670         { "uart2", jz4775_uart2_groups, ARRAY_SIZE(jz4775_uart2_groups), },
1671         { "uart3", jz4775_uart3_groups, ARRAY_SIZE(jz4775_uart3_groups), },
1672         { "ssi", jz4775_ssi_groups, ARRAY_SIZE(jz4775_ssi_groups), },
1673         { "mmc0", jz4775_mmc0_groups, ARRAY_SIZE(jz4775_mmc0_groups), },
1674         { "mmc1", jz4775_mmc1_groups, ARRAY_SIZE(jz4775_mmc1_groups), },
1675         { "mmc2", jz4775_mmc2_groups, ARRAY_SIZE(jz4775_mmc2_groups), },
1676         { "nemc", jz4775_nemc_groups, ARRAY_SIZE(jz4775_nemc_groups), },
1677         { "nemc-cs1", jz4775_cs1_groups, ARRAY_SIZE(jz4775_cs1_groups), },
1678         { "nemc-cs2", jz4775_cs2_groups, ARRAY_SIZE(jz4775_cs2_groups), },
1679         { "nemc-cs3", jz4775_cs3_groups, ARRAY_SIZE(jz4775_cs3_groups), },
1680         { "i2c0", jz4775_i2c0_groups, ARRAY_SIZE(jz4775_i2c0_groups), },
1681         { "i2c1", jz4775_i2c1_groups, ARRAY_SIZE(jz4775_i2c1_groups), },
1682         { "i2c2", jz4775_i2c2_groups, ARRAY_SIZE(jz4775_i2c2_groups), },
1683         { "i2s", jz4775_i2s_groups, ARRAY_SIZE(jz4775_i2s_groups), },
1684         { "dmic", jz4775_dmic_groups, ARRAY_SIZE(jz4775_dmic_groups), },
1685         { "cim", jz4775_cim_groups, ARRAY_SIZE(jz4775_cim_groups), },
1686         { "lcd", jz4775_lcd_groups, ARRAY_SIZE(jz4775_lcd_groups), },
1687         { "pwm0", jz4775_pwm0_groups, ARRAY_SIZE(jz4775_pwm0_groups), },
1688         { "pwm1", jz4775_pwm1_groups, ARRAY_SIZE(jz4775_pwm1_groups), },
1689         { "pwm2", jz4775_pwm2_groups, ARRAY_SIZE(jz4775_pwm2_groups), },
1690         { "pwm3", jz4775_pwm3_groups, ARRAY_SIZE(jz4775_pwm3_groups), },
1691         { "mac", jz4775_mac_groups, ARRAY_SIZE(jz4775_mac_groups), },
1692         { "otg", jz4775_otg_groups, ARRAY_SIZE(jz4775_otg_groups), },
1693 };
1694
1695 static const struct ingenic_chip_info jz4775_chip_info = {
1696         .num_chips = 7,
1697         .reg_offset = 0x100,
1698         .version = ID_JZ4775,
1699         .groups = jz4775_groups,
1700         .num_groups = ARRAY_SIZE(jz4775_groups),
1701         .functions = jz4775_functions,
1702         .num_functions = ARRAY_SIZE(jz4775_functions),
1703         .pull_ups = jz4775_pull_ups,
1704         .pull_downs = jz4775_pull_downs,
1705 };
1706
1707 static const u32 jz4780_pull_ups[6] = {
1708         0x3fffffff, 0xfff0f3fc, 0x0fffffff, 0xffff4fff, 0xfffffb7c, 0x7fa7f00f,
1709 };
1710
1711 static const u32 jz4780_pull_downs[6] = {
1712         0x00000000, 0x000f0c03, 0x00000000, 0x0000b000, 0x00000483, 0x00580ff0,
1713 };
1714
1715 static int jz4780_uart2_data_pins[] = { 0x66, 0x67, };
1716 static int jz4780_uart2_hwflow_pins[] = { 0x65, 0x64, };
1717 static int jz4780_uart4_data_pins[] = { 0x54, 0x4a, };
1718 static int jz4780_ssi0_dt_a_19_pins[] = { 0x13, };
1719 static int jz4780_ssi0_dt_a_21_pins[] = { 0x15, };
1720 static int jz4780_ssi0_dt_a_28_pins[] = { 0x1c, };
1721 static int jz4780_ssi0_dt_b_pins[] = { 0x3d, };
1722 static int jz4780_ssi0_dt_d_pins[] = { 0x79, };
1723 static int jz4780_ssi0_dr_a_20_pins[] = { 0x14, };
1724 static int jz4780_ssi0_dr_a_27_pins[] = { 0x1b, };
1725 static int jz4780_ssi0_dr_b_pins[] = { 0x34, };
1726 static int jz4780_ssi0_dr_d_pins[] = { 0x74, };
1727 static int jz4780_ssi0_clk_a_pins[] = { 0x12, };
1728 static int jz4780_ssi0_clk_b_5_pins[] = { 0x25, };
1729 static int jz4780_ssi0_clk_b_28_pins[] = { 0x3c, };
1730 static int jz4780_ssi0_clk_d_pins[] = { 0x78, };
1731 static int jz4780_ssi0_gpc_b_pins[] = { 0x3e, };
1732 static int jz4780_ssi0_gpc_d_pins[] = { 0x76, };
1733 static int jz4780_ssi0_ce0_a_23_pins[] = { 0x17, };
1734 static int jz4780_ssi0_ce0_a_25_pins[] = { 0x19, };
1735 static int jz4780_ssi0_ce0_b_pins[] = { 0x3f, };
1736 static int jz4780_ssi0_ce0_d_pins[] = { 0x77, };
1737 static int jz4780_ssi0_ce1_b_pins[] = { 0x35, };
1738 static int jz4780_ssi0_ce1_d_pins[] = { 0x75, };
1739 static int jz4780_ssi1_dt_b_pins[] = { 0x3d, };
1740 static int jz4780_ssi1_dt_d_pins[] = { 0x79, };
1741 static int jz4780_ssi1_dr_b_pins[] = { 0x34, };
1742 static int jz4780_ssi1_dr_d_pins[] = { 0x74, };
1743 static int jz4780_ssi1_clk_b_pins[] = { 0x3c, };
1744 static int jz4780_ssi1_clk_d_pins[] = { 0x78, };
1745 static int jz4780_ssi1_gpc_b_pins[] = { 0x3e, };
1746 static int jz4780_ssi1_gpc_d_pins[] = { 0x76, };
1747 static int jz4780_ssi1_ce0_b_pins[] = { 0x3f, };
1748 static int jz4780_ssi1_ce0_d_pins[] = { 0x77, };
1749 static int jz4780_ssi1_ce1_b_pins[] = { 0x35, };
1750 static int jz4780_ssi1_ce1_d_pins[] = { 0x75, };
1751 static int jz4780_mmc0_8bit_a_pins[] = { 0x04, 0x05, 0x06, 0x07, 0x18, };
1752 static int jz4780_i2c3_pins[] = { 0x6a, 0x6b, };
1753 static int jz4780_i2c4_e_pins[] = { 0x8c, 0x8d, };
1754 static int jz4780_i2c4_f_pins[] = { 0xb9, 0xb8, };
1755 static int jz4780_i2s_data_tx_pins[] = { 0x87, };
1756 static int jz4780_i2s_data_rx_pins[] = { 0x86, };
1757 static int jz4780_i2s_clk_txrx_pins[] = { 0x6c, 0x6d, };
1758 static int jz4780_i2s_clk_rx_pins[] = { 0x88, 0x89, };
1759 static int jz4780_i2s_sysclk_pins[] = { 0x85, };
1760 static int jz4780_dmic_pins[] = { 0x32, 0x33, };
1761 static int jz4780_hdmi_ddc_pins[] = { 0xb9, 0xb8, };
1762
1763 static u8 jz4780_i2s_clk_txrx_funcs[] = { 1, 0, };
1764
1765 static const struct group_desc jz4780_groups[] = {
1766         INGENIC_PIN_GROUP("uart0-data", jz4770_uart0_data, 0),
1767         INGENIC_PIN_GROUP("uart0-hwflow", jz4770_uart0_hwflow, 0),
1768         INGENIC_PIN_GROUP("uart1-data", jz4770_uart1_data, 0),
1769         INGENIC_PIN_GROUP("uart1-hwflow", jz4770_uart1_hwflow, 0),
1770         INGENIC_PIN_GROUP("uart2-data", jz4780_uart2_data, 1),
1771         INGENIC_PIN_GROUP("uart2-hwflow", jz4780_uart2_hwflow, 1),
1772         INGENIC_PIN_GROUP_FUNCS("uart3-data", jz4770_uart3_data,
1773                                 jz4760_uart3_data_funcs),
1774         INGENIC_PIN_GROUP("uart3-hwflow", jz4770_uart3_hwflow, 0),
1775         INGENIC_PIN_GROUP("uart4-data", jz4780_uart4_data, 2),
1776         INGENIC_PIN_GROUP("ssi0-dt-a-19", jz4780_ssi0_dt_a_19, 2),
1777         INGENIC_PIN_GROUP("ssi0-dt-a-21", jz4780_ssi0_dt_a_21, 2),
1778         INGENIC_PIN_GROUP("ssi0-dt-a-28", jz4780_ssi0_dt_a_28, 2),
1779         INGENIC_PIN_GROUP("ssi0-dt-b", jz4780_ssi0_dt_b, 1),
1780         INGENIC_PIN_GROUP("ssi0-dt-d", jz4780_ssi0_dt_d, 1),
1781         INGENIC_PIN_GROUP("ssi0-dt-e", jz4770_ssi0_dt_e, 0),
1782         INGENIC_PIN_GROUP("ssi0-dr-a-20", jz4780_ssi0_dr_a_20, 2),
1783         INGENIC_PIN_GROUP("ssi0-dr-a-27", jz4780_ssi0_dr_a_27, 2),
1784         INGENIC_PIN_GROUP("ssi0-dr-b", jz4780_ssi0_dr_b, 1),
1785         INGENIC_PIN_GROUP("ssi0-dr-d", jz4780_ssi0_dr_d, 1),
1786         INGENIC_PIN_GROUP("ssi0-dr-e", jz4770_ssi0_dr_e, 0),
1787         INGENIC_PIN_GROUP("ssi0-clk-a", jz4780_ssi0_clk_a, 2),
1788         INGENIC_PIN_GROUP("ssi0-clk-b-5", jz4780_ssi0_clk_b_5, 1),
1789         INGENIC_PIN_GROUP("ssi0-clk-b-28", jz4780_ssi0_clk_b_28, 1),
1790         INGENIC_PIN_GROUP("ssi0-clk-d", jz4780_ssi0_clk_d, 1),
1791         INGENIC_PIN_GROUP("ssi0-clk-e", jz4770_ssi0_clk_e, 0),
1792         INGENIC_PIN_GROUP("ssi0-gpc-b", jz4780_ssi0_gpc_b, 1),
1793         INGENIC_PIN_GROUP("ssi0-gpc-d", jz4780_ssi0_gpc_d, 1),
1794         INGENIC_PIN_GROUP("ssi0-gpc-e", jz4770_ssi0_gpc_e, 0),
1795         INGENIC_PIN_GROUP("ssi0-ce0-a-23", jz4780_ssi0_ce0_a_23, 2),
1796         INGENIC_PIN_GROUP("ssi0-ce0-a-25", jz4780_ssi0_ce0_a_25, 2),
1797         INGENIC_PIN_GROUP("ssi0-ce0-b", jz4780_ssi0_ce0_b, 1),
1798         INGENIC_PIN_GROUP("ssi0-ce0-d", jz4780_ssi0_ce0_d, 1),
1799         INGENIC_PIN_GROUP("ssi0-ce0-e", jz4770_ssi0_ce0_e, 0),
1800         INGENIC_PIN_GROUP("ssi0-ce1-b", jz4780_ssi0_ce1_b, 1),
1801         INGENIC_PIN_GROUP("ssi0-ce1-d", jz4780_ssi0_ce1_d, 1),
1802         INGENIC_PIN_GROUP("ssi0-ce1-e", jz4770_ssi0_ce1_e, 0),
1803         INGENIC_PIN_GROUP("ssi1-dt-b", jz4780_ssi1_dt_b, 2),
1804         INGENIC_PIN_GROUP("ssi1-dt-d", jz4780_ssi1_dt_d, 2),
1805         INGENIC_PIN_GROUP("ssi1-dt-e", jz4770_ssi1_dt_e, 1),
1806         INGENIC_PIN_GROUP("ssi1-dr-b", jz4780_ssi1_dr_b, 2),
1807         INGENIC_PIN_GROUP("ssi1-dr-d", jz4780_ssi1_dr_d, 2),
1808         INGENIC_PIN_GROUP("ssi1-dr-e", jz4770_ssi1_dr_e, 1),
1809         INGENIC_PIN_GROUP("ssi1-clk-b", jz4780_ssi1_clk_b, 2),
1810         INGENIC_PIN_GROUP("ssi1-clk-d", jz4780_ssi1_clk_d, 2),
1811         INGENIC_PIN_GROUP("ssi1-clk-e", jz4770_ssi1_clk_e, 1),
1812         INGENIC_PIN_GROUP("ssi1-gpc-b", jz4780_ssi1_gpc_b, 2),
1813         INGENIC_PIN_GROUP("ssi1-gpc-d", jz4780_ssi1_gpc_d, 2),
1814         INGENIC_PIN_GROUP("ssi1-gpc-e", jz4770_ssi1_gpc_e, 1),
1815         INGENIC_PIN_GROUP("ssi1-ce0-b", jz4780_ssi1_ce0_b, 2),
1816         INGENIC_PIN_GROUP("ssi1-ce0-d", jz4780_ssi1_ce0_d, 2),
1817         INGENIC_PIN_GROUP("ssi1-ce0-e", jz4770_ssi1_ce0_e, 1),
1818         INGENIC_PIN_GROUP("ssi1-ce1-b", jz4780_ssi1_ce1_b, 2),
1819         INGENIC_PIN_GROUP("ssi1-ce1-d", jz4780_ssi1_ce1_d, 2),
1820         INGENIC_PIN_GROUP("ssi1-ce1-e", jz4770_ssi1_ce1_e, 1),
1821         INGENIC_PIN_GROUP_FUNCS("mmc0-1bit-a", jz4770_mmc0_1bit_a,
1822                                 jz4760_mmc0_1bit_a_funcs),
1823         INGENIC_PIN_GROUP("mmc0-4bit-a", jz4770_mmc0_4bit_a, 1),
1824         INGENIC_PIN_GROUP("mmc0-8bit-a", jz4780_mmc0_8bit_a, 1),
1825         INGENIC_PIN_GROUP("mmc0-1bit-e", jz4770_mmc0_1bit_e, 0),
1826         INGENIC_PIN_GROUP("mmc0-4bit-e", jz4770_mmc0_4bit_e, 0),
1827         INGENIC_PIN_GROUP("mmc1-1bit-d", jz4770_mmc1_1bit_d, 0),
1828         INGENIC_PIN_GROUP("mmc1-4bit-d", jz4770_mmc1_4bit_d, 0),
1829         INGENIC_PIN_GROUP("mmc1-1bit-e", jz4770_mmc1_1bit_e, 1),
1830         INGENIC_PIN_GROUP("mmc1-4bit-e", jz4770_mmc1_4bit_e, 1),
1831         INGENIC_PIN_GROUP("mmc2-1bit-b", jz4770_mmc2_1bit_b, 0),
1832         INGENIC_PIN_GROUP("mmc2-4bit-b", jz4770_mmc2_4bit_b, 0),
1833         INGENIC_PIN_GROUP("mmc2-1bit-e", jz4770_mmc2_1bit_e, 2),
1834         INGENIC_PIN_GROUP("mmc2-4bit-e", jz4770_mmc2_4bit_e, 2),
1835         INGENIC_PIN_GROUP("nemc-data", jz4770_nemc_8bit_data, 0),
1836         INGENIC_PIN_GROUP("nemc-cle-ale", jz4770_nemc_cle_ale, 0),
1837         INGENIC_PIN_GROUP("nemc-addr", jz4770_nemc_addr, 0),
1838         INGENIC_PIN_GROUP("nemc-rd-we", jz4770_nemc_rd_we, 0),
1839         INGENIC_PIN_GROUP("nemc-frd-fwe", jz4770_nemc_frd_fwe, 0),
1840         INGENIC_PIN_GROUP("nemc-wait", jz4770_nemc_wait, 0),
1841         INGENIC_PIN_GROUP("nemc-cs1", jz4770_nemc_cs1, 0),
1842         INGENIC_PIN_GROUP("nemc-cs2", jz4770_nemc_cs2, 0),
1843         INGENIC_PIN_GROUP("nemc-cs3", jz4770_nemc_cs3, 0),
1844         INGENIC_PIN_GROUP("nemc-cs4", jz4770_nemc_cs4, 0),
1845         INGENIC_PIN_GROUP("nemc-cs5", jz4770_nemc_cs5, 0),
1846         INGENIC_PIN_GROUP("nemc-cs6", jz4770_nemc_cs6, 0),
1847         INGENIC_PIN_GROUP("i2c0-data", jz4770_i2c0, 0),
1848         INGENIC_PIN_GROUP("i2c1-data", jz4770_i2c1, 0),
1849         INGENIC_PIN_GROUP("i2c2-data", jz4770_i2c2, 2),
1850         INGENIC_PIN_GROUP("i2c3-data", jz4780_i2c3, 1),
1851         INGENIC_PIN_GROUP("i2c4-data-e", jz4780_i2c4_e, 1),
1852         INGENIC_PIN_GROUP("i2c4-data-f", jz4780_i2c4_f, 1),
1853         INGENIC_PIN_GROUP("i2s-data-tx", jz4780_i2s_data_tx, 0),
1854         INGENIC_PIN_GROUP("i2s-data-rx", jz4780_i2s_data_rx, 0),
1855         INGENIC_PIN_GROUP_FUNCS("i2s-clk-txrx", jz4780_i2s_clk_txrx,
1856                                 jz4780_i2s_clk_txrx_funcs),
1857         INGENIC_PIN_GROUP("i2s-clk-rx", jz4780_i2s_clk_rx, 1),
1858         INGENIC_PIN_GROUP("i2s-sysclk", jz4780_i2s_sysclk, 2),
1859         INGENIC_PIN_GROUP("dmic", jz4780_dmic, 1),
1860         INGENIC_PIN_GROUP("hdmi-ddc", jz4780_hdmi_ddc, 0),
1861         INGENIC_PIN_GROUP("cim-data", jz4770_cim_8bit, 0),
1862         INGENIC_PIN_GROUP("cim-data-12bit", jz4770_cim_12bit, 0),
1863         INGENIC_PIN_GROUP("lcd-8bit", jz4770_lcd_8bit, 0),
1864         INGENIC_PIN_GROUP("lcd-16bit", jz4770_lcd_16bit, 0),
1865         INGENIC_PIN_GROUP("lcd-18bit", jz4770_lcd_18bit, 0),
1866         INGENIC_PIN_GROUP("lcd-24bit", jz4770_lcd_24bit, 0),
1867         INGENIC_PIN_GROUP("lcd-special", jz4770_lcd_special, 1),
1868         INGENIC_PIN_GROUP("lcd-generic", jz4770_lcd_generic, 0),
1869         INGENIC_PIN_GROUP("pwm0", jz4770_pwm_pwm0, 0),
1870         INGENIC_PIN_GROUP("pwm1", jz4770_pwm_pwm1, 0),
1871         INGENIC_PIN_GROUP("pwm2", jz4770_pwm_pwm2, 0),
1872         INGENIC_PIN_GROUP("pwm3", jz4770_pwm_pwm3, 0),
1873         INGENIC_PIN_GROUP("pwm4", jz4770_pwm_pwm4, 0),
1874         INGENIC_PIN_GROUP("pwm5", jz4770_pwm_pwm5, 0),
1875         INGENIC_PIN_GROUP("pwm6", jz4770_pwm_pwm6, 0),
1876         INGENIC_PIN_GROUP("pwm7", jz4770_pwm_pwm7, 0),
1877 };
1878
1879 static const char *jz4780_uart2_groups[] = { "uart2-data", "uart2-hwflow", };
1880 static const char *jz4780_uart4_groups[] = { "uart4-data", };
1881 static const char *jz4780_ssi0_groups[] = {
1882         "ssi0-dt-a-19", "ssi0-dt-a-21", "ssi0-dt-a-28", "ssi0-dt-b", "ssi0-dt-d", "ssi0-dt-e",
1883         "ssi0-dr-a-20", "ssi0-dr-a-27", "ssi0-dr-b", "ssi0-dr-d", "ssi0-dr-e",
1884         "ssi0-clk-a", "ssi0-clk-b-5", "ssi0-clk-b-28", "ssi0-clk-d", "ssi0-clk-e",
1885         "ssi0-gpc-b", "ssi0-gpc-d", "ssi0-gpc-e",
1886         "ssi0-ce0-a-23", "ssi0-ce0-a-25", "ssi0-ce0-b", "ssi0-ce0-d", "ssi0-ce0-e",
1887         "ssi0-ce1-b", "ssi0-ce1-d", "ssi0-ce1-e",
1888 };
1889 static const char *jz4780_ssi1_groups[] = {
1890         "ssi1-dt-b", "ssi1-dt-d", "ssi1-dt-e",
1891         "ssi1-dr-b", "ssi1-dr-d", "ssi1-dr-e",
1892         "ssi1-clk-b", "ssi1-clk-d", "ssi1-clk-e",
1893         "ssi1-gpc-b", "ssi1-gpc-d", "ssi1-gpc-e",
1894         "ssi1-ce0-b", "ssi1-ce0-d", "ssi1-ce0-e",
1895         "ssi1-ce1-b", "ssi1-ce1-d", "ssi1-ce1-e",
1896 };
1897 static const char *jz4780_mmc0_groups[] = {
1898         "mmc0-1bit-a", "mmc0-4bit-a", "mmc0-8bit-a",
1899         "mmc0-1bit-e", "mmc0-4bit-e",
1900 };
1901 static const char *jz4780_mmc1_groups[] = {
1902         "mmc1-1bit-d", "mmc1-4bit-d", "mmc1-1bit-e", "mmc1-4bit-e",
1903 };
1904 static const char *jz4780_mmc2_groups[] = {
1905         "mmc2-1bit-b", "mmc2-4bit-b", "mmc2-1bit-e", "mmc2-4bit-e",
1906 };
1907 static const char *jz4780_nemc_groups[] = {
1908         "nemc-data", "nemc-cle-ale", "nemc-addr",
1909         "nemc-rd-we", "nemc-frd-fwe", "nemc-wait",
1910 };
1911 static const char *jz4780_i2c3_groups[] = { "i2c3-data", };
1912 static const char *jz4780_i2c4_groups[] = { "i2c4-data-e", "i2c4-data-f", };
1913 static const char *jz4780_i2s_groups[] = {
1914         "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk",
1915 };
1916 static const char *jz4780_dmic_groups[] = { "dmic", };
1917 static const char *jz4780_cim_groups[] = { "cim-data", };
1918 static const char *jz4780_hdmi_ddc_groups[] = { "hdmi-ddc", };
1919
1920 static const struct function_desc jz4780_functions[] = {
1921         { "uart0", jz4770_uart0_groups, ARRAY_SIZE(jz4770_uart0_groups), },
1922         { "uart1", jz4770_uart1_groups, ARRAY_SIZE(jz4770_uart1_groups), },
1923         { "uart2", jz4780_uart2_groups, ARRAY_SIZE(jz4780_uart2_groups), },
1924         { "uart3", jz4770_uart3_groups, ARRAY_SIZE(jz4770_uart3_groups), },
1925         { "uart4", jz4780_uart4_groups, ARRAY_SIZE(jz4780_uart4_groups), },
1926         { "ssi0", jz4780_ssi0_groups, ARRAY_SIZE(jz4780_ssi0_groups), },
1927         { "ssi1", jz4780_ssi1_groups, ARRAY_SIZE(jz4780_ssi1_groups), },
1928         { "mmc0", jz4780_mmc0_groups, ARRAY_SIZE(jz4780_mmc0_groups), },
1929         { "mmc1", jz4780_mmc1_groups, ARRAY_SIZE(jz4780_mmc1_groups), },
1930         { "mmc2", jz4780_mmc2_groups, ARRAY_SIZE(jz4780_mmc2_groups), },
1931         { "nemc", jz4780_nemc_groups, ARRAY_SIZE(jz4780_nemc_groups), },
1932         { "nemc-cs1", jz4770_cs1_groups, ARRAY_SIZE(jz4770_cs1_groups), },
1933         { "nemc-cs2", jz4770_cs2_groups, ARRAY_SIZE(jz4770_cs2_groups), },
1934         { "nemc-cs3", jz4770_cs3_groups, ARRAY_SIZE(jz4770_cs3_groups), },
1935         { "nemc-cs4", jz4770_cs4_groups, ARRAY_SIZE(jz4770_cs4_groups), },
1936         { "nemc-cs5", jz4770_cs5_groups, ARRAY_SIZE(jz4770_cs5_groups), },
1937         { "nemc-cs6", jz4770_cs6_groups, ARRAY_SIZE(jz4770_cs6_groups), },
1938         { "i2c0", jz4770_i2c0_groups, ARRAY_SIZE(jz4770_i2c0_groups), },
1939         { "i2c1", jz4770_i2c1_groups, ARRAY_SIZE(jz4770_i2c1_groups), },
1940         { "i2c2", jz4770_i2c2_groups, ARRAY_SIZE(jz4770_i2c2_groups), },
1941         { "i2c3", jz4780_i2c3_groups, ARRAY_SIZE(jz4780_i2c3_groups), },
1942         { "i2c4", jz4780_i2c4_groups, ARRAY_SIZE(jz4780_i2c4_groups), },
1943         { "i2s", jz4780_i2s_groups, ARRAY_SIZE(jz4780_i2s_groups), },
1944         { "dmic", jz4780_dmic_groups, ARRAY_SIZE(jz4780_dmic_groups), },
1945         { "cim", jz4780_cim_groups, ARRAY_SIZE(jz4780_cim_groups), },
1946         { "lcd", jz4770_lcd_groups, ARRAY_SIZE(jz4770_lcd_groups), },
1947         { "pwm0", jz4770_pwm0_groups, ARRAY_SIZE(jz4770_pwm0_groups), },
1948         { "pwm1", jz4770_pwm1_groups, ARRAY_SIZE(jz4770_pwm1_groups), },
1949         { "pwm2", jz4770_pwm2_groups, ARRAY_SIZE(jz4770_pwm2_groups), },
1950         { "pwm3", jz4770_pwm3_groups, ARRAY_SIZE(jz4770_pwm3_groups), },
1951         { "pwm4", jz4770_pwm4_groups, ARRAY_SIZE(jz4770_pwm4_groups), },
1952         { "pwm5", jz4770_pwm5_groups, ARRAY_SIZE(jz4770_pwm5_groups), },
1953         { "pwm6", jz4770_pwm6_groups, ARRAY_SIZE(jz4770_pwm6_groups), },
1954         { "pwm7", jz4770_pwm7_groups, ARRAY_SIZE(jz4770_pwm7_groups), },
1955         { "hdmi-ddc", jz4780_hdmi_ddc_groups,
1956                       ARRAY_SIZE(jz4780_hdmi_ddc_groups), },
1957 };
1958
1959 static const struct ingenic_chip_info jz4780_chip_info = {
1960         .num_chips = 6,
1961         .reg_offset = 0x100,
1962         .version = ID_JZ4780,
1963         .groups = jz4780_groups,
1964         .num_groups = ARRAY_SIZE(jz4780_groups),
1965         .functions = jz4780_functions,
1966         .num_functions = ARRAY_SIZE(jz4780_functions),
1967         .pull_ups = jz4780_pull_ups,
1968         .pull_downs = jz4780_pull_downs,
1969 };
1970
1971 static const u32 x1000_pull_ups[4] = {
1972         0xffffffff, 0xfdffffff, 0x0dffffff, 0x0000003f,
1973 };
1974
1975 static const u32 x1000_pull_downs[4] = {
1976         0x00000000, 0x02000000, 0x02000000, 0x00000000,
1977 };
1978
1979 static int x1000_uart0_data_pins[] = { 0x4a, 0x4b, };
1980 static int x1000_uart0_hwflow_pins[] = { 0x4c, 0x4d, };
1981 static int x1000_uart1_data_a_pins[] = { 0x04, 0x05, };
1982 static int x1000_uart1_data_d_pins[] = { 0x62, 0x63, };
1983 static int x1000_uart1_hwflow_pins[] = { 0x64, 0x65, };
1984 static int x1000_uart2_data_a_pins[] = { 0x02, 0x03, };
1985 static int x1000_uart2_data_d_pins[] = { 0x65, 0x64, };
1986 static int x1000_sfc_data_pins[] = { 0x1d, 0x1c, 0x1e, 0x1f, };
1987 static int x1000_sfc_clk_pins[] = { 0x1a, };
1988 static int x1000_sfc_ce_pins[] = { 0x1b, };
1989 static int x1000_ssi_dt_a_22_pins[] = { 0x16, };
1990 static int x1000_ssi_dt_a_29_pins[] = { 0x1d, };
1991 static int x1000_ssi_dt_d_pins[] = { 0x62, };
1992 static int x1000_ssi_dr_a_23_pins[] = { 0x17, };
1993 static int x1000_ssi_dr_a_28_pins[] = { 0x1c, };
1994 static int x1000_ssi_dr_d_pins[] = { 0x63, };
1995 static int x1000_ssi_clk_a_24_pins[] = { 0x18, };
1996 static int x1000_ssi_clk_a_26_pins[] = { 0x1a, };
1997 static int x1000_ssi_clk_d_pins[] = { 0x60, };
1998 static int x1000_ssi_gpc_a_20_pins[] = { 0x14, };
1999 static int x1000_ssi_gpc_a_31_pins[] = { 0x1f, };
2000 static int x1000_ssi_ce0_a_25_pins[] = { 0x19, };
2001 static int x1000_ssi_ce0_a_27_pins[] = { 0x1b, };
2002 static int x1000_ssi_ce0_d_pins[] = { 0x61, };
2003 static int x1000_ssi_ce1_a_21_pins[] = { 0x15, };
2004 static int x1000_ssi_ce1_a_30_pins[] = { 0x1e, };
2005 static int x1000_mmc0_1bit_pins[] = { 0x18, 0x19, 0x17, };
2006 static int x1000_mmc0_4bit_pins[] = { 0x16, 0x15, 0x14, };
2007 static int x1000_mmc0_8bit_pins[] = { 0x13, 0x12, 0x11, 0x10, };
2008 static int x1000_mmc1_1bit_pins[] = { 0x40, 0x41, 0x42, };
2009 static int x1000_mmc1_4bit_pins[] = { 0x43, 0x44, 0x45, };
2010 static int x1000_emc_8bit_data_pins[] = {
2011         0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
2012 };
2013 static int x1000_emc_16bit_data_pins[] = {
2014         0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
2015 };
2016 static int x1000_emc_addr_pins[] = {
2017         0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
2018         0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
2019 };
2020 static int x1000_emc_rd_we_pins[] = { 0x30, 0x31, };
2021 static int x1000_emc_wait_pins[] = { 0x34, };
2022 static int x1000_emc_cs1_pins[] = { 0x32, };
2023 static int x1000_emc_cs2_pins[] = { 0x33, };
2024 static int x1000_i2c0_pins[] = { 0x38, 0x37, };
2025 static int x1000_i2c1_a_pins[] = { 0x01, 0x00, };
2026 static int x1000_i2c1_c_pins[] = { 0x5b, 0x5a, };
2027 static int x1000_i2c2_pins[] = { 0x61, 0x60, };
2028 static int x1000_i2s_data_tx_pins[] = { 0x24, };
2029 static int x1000_i2s_data_rx_pins[] = { 0x23, };
2030 static int x1000_i2s_clk_txrx_pins[] = { 0x21, 0x22, };
2031 static int x1000_i2s_sysclk_pins[] = { 0x20, };
2032 static int x1000_dmic_if0_pins[] = { 0x35, 0x36, };
2033 static int x1000_dmic_if1_pins[] = { 0x25, };
2034 static int x1000_cim_pins[] = {
2035         0x08, 0x09, 0x0a, 0x0b,
2036         0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c,
2037 };
2038 static int x1000_lcd_8bit_pins[] = {
2039         0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
2040         0x30, 0x31, 0x32, 0x33, 0x34,
2041 };
2042 static int x1000_lcd_16bit_pins[] = {
2043         0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
2044 };
2045 static int x1000_pwm_pwm0_pins[] = { 0x59, };
2046 static int x1000_pwm_pwm1_pins[] = { 0x5a, };
2047 static int x1000_pwm_pwm2_pins[] = { 0x5b, };
2048 static int x1000_pwm_pwm3_pins[] = { 0x26, };
2049 static int x1000_pwm_pwm4_pins[] = { 0x58, };
2050 static int x1000_mac_pins[] = {
2051         0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f, 0x26,
2052 };
2053
2054 static const struct group_desc x1000_groups[] = {
2055         INGENIC_PIN_GROUP("uart0-data", x1000_uart0_data, 0),
2056         INGENIC_PIN_GROUP("uart0-hwflow", x1000_uart0_hwflow, 0),
2057         INGENIC_PIN_GROUP("uart1-data-a", x1000_uart1_data_a, 2),
2058         INGENIC_PIN_GROUP("uart1-data-d", x1000_uart1_data_d, 1),
2059         INGENIC_PIN_GROUP("uart1-hwflow", x1000_uart1_hwflow, 1),
2060         INGENIC_PIN_GROUP("uart2-data-a", x1000_uart2_data_a, 2),
2061         INGENIC_PIN_GROUP("uart2-data-d", x1000_uart2_data_d, 0),
2062         INGENIC_PIN_GROUP("sfc-data", x1000_sfc_data, 1),
2063         INGENIC_PIN_GROUP("sfc-clk", x1000_sfc_clk, 1),
2064         INGENIC_PIN_GROUP("sfc-ce", x1000_sfc_ce, 1),
2065         INGENIC_PIN_GROUP("ssi-dt-a-22", x1000_ssi_dt_a_22, 2),
2066         INGENIC_PIN_GROUP("ssi-dt-a-29", x1000_ssi_dt_a_29, 2),
2067         INGENIC_PIN_GROUP("ssi-dt-d", x1000_ssi_dt_d, 0),
2068         INGENIC_PIN_GROUP("ssi-dr-a-23", x1000_ssi_dr_a_23, 2),
2069         INGENIC_PIN_GROUP("ssi-dr-a-28", x1000_ssi_dr_a_28, 2),
2070         INGENIC_PIN_GROUP("ssi-dr-d", x1000_ssi_dr_d, 0),
2071         INGENIC_PIN_GROUP("ssi-clk-a-24", x1000_ssi_clk_a_24, 2),
2072         INGENIC_PIN_GROUP("ssi-clk-a-26", x1000_ssi_clk_a_26, 2),
2073         INGENIC_PIN_GROUP("ssi-clk-d", x1000_ssi_clk_d, 0),
2074         INGENIC_PIN_GROUP("ssi-gpc-a-20", x1000_ssi_gpc_a_20, 2),
2075         INGENIC_PIN_GROUP("ssi-gpc-a-31", x1000_ssi_gpc_a_31, 2),
2076         INGENIC_PIN_GROUP("ssi-ce0-a-25", x1000_ssi_ce0_a_25, 2),
2077         INGENIC_PIN_GROUP("ssi-ce0-a-27", x1000_ssi_ce0_a_27, 2),
2078         INGENIC_PIN_GROUP("ssi-ce0-d", x1000_ssi_ce0_d, 0),
2079         INGENIC_PIN_GROUP("ssi-ce1-a-21", x1000_ssi_ce1_a_21, 2),
2080         INGENIC_PIN_GROUP("ssi-ce1-a-30", x1000_ssi_ce1_a_30, 2),
2081         INGENIC_PIN_GROUP("mmc0-1bit", x1000_mmc0_1bit, 1),
2082         INGENIC_PIN_GROUP("mmc0-4bit", x1000_mmc0_4bit, 1),
2083         INGENIC_PIN_GROUP("mmc0-8bit", x1000_mmc0_8bit, 1),
2084         INGENIC_PIN_GROUP("mmc1-1bit", x1000_mmc1_1bit, 0),
2085         INGENIC_PIN_GROUP("mmc1-4bit", x1000_mmc1_4bit, 0),
2086         INGENIC_PIN_GROUP("emc-8bit-data", x1000_emc_8bit_data, 0),
2087         INGENIC_PIN_GROUP("emc-16bit-data", x1000_emc_16bit_data, 0),
2088         INGENIC_PIN_GROUP("emc-addr", x1000_emc_addr, 0),
2089         INGENIC_PIN_GROUP("emc-rd-we", x1000_emc_rd_we, 0),
2090         INGENIC_PIN_GROUP("emc-wait", x1000_emc_wait, 0),
2091         INGENIC_PIN_GROUP("emc-cs1", x1000_emc_cs1, 0),
2092         INGENIC_PIN_GROUP("emc-cs2", x1000_emc_cs2, 0),
2093         INGENIC_PIN_GROUP("i2c0-data", x1000_i2c0, 0),
2094         INGENIC_PIN_GROUP("i2c1-data-a", x1000_i2c1_a, 2),
2095         INGENIC_PIN_GROUP("i2c1-data-c", x1000_i2c1_c, 0),
2096         INGENIC_PIN_GROUP("i2c2-data", x1000_i2c2, 1),
2097         INGENIC_PIN_GROUP("i2s-data-tx", x1000_i2s_data_tx, 1),
2098         INGENIC_PIN_GROUP("i2s-data-rx", x1000_i2s_data_rx, 1),
2099         INGENIC_PIN_GROUP("i2s-clk-txrx", x1000_i2s_clk_txrx, 1),
2100         INGENIC_PIN_GROUP("i2s-sysclk", x1000_i2s_sysclk, 1),
2101         INGENIC_PIN_GROUP("dmic-if0", x1000_dmic_if0, 0),
2102         INGENIC_PIN_GROUP("dmic-if1", x1000_dmic_if1, 1),
2103         INGENIC_PIN_GROUP("cim-data", x1000_cim, 2),
2104         INGENIC_PIN_GROUP("lcd-8bit", x1000_lcd_8bit, 1),
2105         INGENIC_PIN_GROUP("lcd-16bit", x1000_lcd_16bit, 1),
2106         INGENIC_PIN_GROUP("pwm0", x1000_pwm_pwm0, 0),
2107         INGENIC_PIN_GROUP("pwm1", x1000_pwm_pwm1, 1),
2108         INGENIC_PIN_GROUP("pwm2", x1000_pwm_pwm2, 1),
2109         INGENIC_PIN_GROUP("pwm3", x1000_pwm_pwm3, 2),
2110         INGENIC_PIN_GROUP("pwm4", x1000_pwm_pwm4, 0),
2111         INGENIC_PIN_GROUP("mac", x1000_mac, 1),
2112 };
2113
2114 static const char *x1000_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
2115 static const char *x1000_uart1_groups[] = {
2116         "uart1-data-a", "uart1-data-d", "uart1-hwflow",
2117 };
2118 static const char *x1000_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };
2119 static const char *x1000_sfc_groups[] = { "sfc-data", "sfc-clk", "sfc-ce", };
2120 static const char *x1000_ssi_groups[] = {
2121         "ssi-dt-a-22", "ssi-dt-a-29", "ssi-dt-d",
2122         "ssi-dr-a-23", "ssi-dr-a-28", "ssi-dr-d",
2123         "ssi-clk-a-24", "ssi-clk-a-26", "ssi-clk-d",
2124         "ssi-gpc-a-20", "ssi-gpc-a-31",
2125         "ssi-ce0-a-25", "ssi-ce0-a-27", "ssi-ce0-d",
2126         "ssi-ce1-a-21", "ssi-ce1-a-30",
2127 };
2128 static const char *x1000_mmc0_groups[] = {
2129         "mmc0-1bit", "mmc0-4bit", "mmc0-8bit",
2130 };
2131 static const char *x1000_mmc1_groups[] = {
2132         "mmc1-1bit", "mmc1-4bit",
2133 };
2134 static const char *x1000_emc_groups[] = {
2135         "emc-8bit-data", "emc-16bit-data",
2136         "emc-addr", "emc-rd-we", "emc-wait",
2137 };
2138 static const char *x1000_cs1_groups[] = { "emc-cs1", };
2139 static const char *x1000_cs2_groups[] = { "emc-cs2", };
2140 static const char *x1000_i2c0_groups[] = { "i2c0-data", };
2141 static const char *x1000_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
2142 static const char *x1000_i2c2_groups[] = { "i2c2-data", };
2143 static const char *x1000_i2s_groups[] = {
2144         "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",
2145 };
2146 static const char *x1000_dmic_groups[] = { "dmic-if0", "dmic-if1", };
2147 static const char *x1000_cim_groups[] = { "cim-data", };
2148 static const char *x1000_lcd_groups[] = { "lcd-8bit", "lcd-16bit", };
2149 static const char *x1000_pwm0_groups[] = { "pwm0", };
2150 static const char *x1000_pwm1_groups[] = { "pwm1", };
2151 static const char *x1000_pwm2_groups[] = { "pwm2", };
2152 static const char *x1000_pwm3_groups[] = { "pwm3", };
2153 static const char *x1000_pwm4_groups[] = { "pwm4", };
2154 static const char *x1000_mac_groups[] = { "mac", };
2155
2156 static const struct function_desc x1000_functions[] = {
2157         { "uart0", x1000_uart0_groups, ARRAY_SIZE(x1000_uart0_groups), },
2158         { "uart1", x1000_uart1_groups, ARRAY_SIZE(x1000_uart1_groups), },
2159         { "uart2", x1000_uart2_groups, ARRAY_SIZE(x1000_uart2_groups), },
2160         { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), },
2161         { "ssi", x1000_ssi_groups, ARRAY_SIZE(x1000_ssi_groups), },
2162         { "mmc0", x1000_mmc0_groups, ARRAY_SIZE(x1000_mmc0_groups), },
2163         { "mmc1", x1000_mmc1_groups, ARRAY_SIZE(x1000_mmc1_groups), },
2164         { "emc", x1000_emc_groups, ARRAY_SIZE(x1000_emc_groups), },
2165         { "emc-cs1", x1000_cs1_groups, ARRAY_SIZE(x1000_cs1_groups), },
2166         { "emc-cs2", x1000_cs2_groups, ARRAY_SIZE(x1000_cs2_groups), },
2167         { "i2c0", x1000_i2c0_groups, ARRAY_SIZE(x1000_i2c0_groups), },
2168         { "i2c1", x1000_i2c1_groups, ARRAY_SIZE(x1000_i2c1_groups), },
2169         { "i2c2", x1000_i2c2_groups, ARRAY_SIZE(x1000_i2c2_groups), },
2170         { "i2s", x1000_i2s_groups, ARRAY_SIZE(x1000_i2s_groups), },
2171         { "dmic", x1000_dmic_groups, ARRAY_SIZE(x1000_dmic_groups), },
2172         { "cim", x1000_cim_groups, ARRAY_SIZE(x1000_cim_groups), },
2173         { "lcd", x1000_lcd_groups, ARRAY_SIZE(x1000_lcd_groups), },
2174         { "pwm0", x1000_pwm0_groups, ARRAY_SIZE(x1000_pwm0_groups), },
2175         { "pwm1", x1000_pwm1_groups, ARRAY_SIZE(x1000_pwm1_groups), },
2176         { "pwm2", x1000_pwm2_groups, ARRAY_SIZE(x1000_pwm2_groups), },
2177         { "pwm3", x1000_pwm3_groups, ARRAY_SIZE(x1000_pwm3_groups), },
2178         { "pwm4", x1000_pwm4_groups, ARRAY_SIZE(x1000_pwm4_groups), },
2179         { "mac", x1000_mac_groups, ARRAY_SIZE(x1000_mac_groups), },
2180 };
2181
2182 static const struct ingenic_chip_info x1000_chip_info = {
2183         .num_chips = 4,
2184         .reg_offset = 0x100,
2185         .version = ID_X1000,
2186         .groups = x1000_groups,
2187         .num_groups = ARRAY_SIZE(x1000_groups),
2188         .functions = x1000_functions,
2189         .num_functions = ARRAY_SIZE(x1000_functions),
2190         .pull_ups = x1000_pull_ups,
2191         .pull_downs = x1000_pull_downs,
2192 };
2193
2194 static int x1500_uart0_data_pins[] = { 0x4a, 0x4b, };
2195 static int x1500_uart0_hwflow_pins[] = { 0x4c, 0x4d, };
2196 static int x1500_uart1_data_a_pins[] = { 0x04, 0x05, };
2197 static int x1500_uart1_data_d_pins[] = { 0x62, 0x63, };
2198 static int x1500_uart1_hwflow_pins[] = { 0x64, 0x65, };
2199 static int x1500_uart2_data_a_pins[] = { 0x02, 0x03, };
2200 static int x1500_uart2_data_d_pins[] = { 0x65, 0x64, };
2201 static int x1500_mmc_1bit_pins[] = { 0x18, 0x19, 0x17, };
2202 static int x1500_mmc_4bit_pins[] = { 0x16, 0x15, 0x14, };
2203 static int x1500_i2c0_pins[] = { 0x38, 0x37, };
2204 static int x1500_i2c1_a_pins[] = { 0x01, 0x00, };
2205 static int x1500_i2c1_c_pins[] = { 0x5b, 0x5a, };
2206 static int x1500_i2c2_pins[] = { 0x61, 0x60, };
2207 static int x1500_i2s_data_tx_pins[] = { 0x24, };
2208 static int x1500_i2s_data_rx_pins[] = { 0x23, };
2209 static int x1500_i2s_clk_txrx_pins[] = { 0x21, 0x22, };
2210 static int x1500_i2s_sysclk_pins[] = { 0x20, };
2211 static int x1500_dmic_if0_pins[] = { 0x35, 0x36, };
2212 static int x1500_dmic_if1_pins[] = { 0x25, };
2213 static int x1500_cim_pins[] = {
2214         0x08, 0x09, 0x0a, 0x0b,
2215         0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e, 0x0d, 0x0c,
2216 };
2217 static int x1500_pwm_pwm0_pins[] = { 0x59, };
2218 static int x1500_pwm_pwm1_pins[] = { 0x5a, };
2219 static int x1500_pwm_pwm2_pins[] = { 0x5b, };
2220 static int x1500_pwm_pwm3_pins[] = { 0x26, };
2221 static int x1500_pwm_pwm4_pins[] = { 0x58, };
2222
2223 static const struct group_desc x1500_groups[] = {
2224         INGENIC_PIN_GROUP("uart0-data", x1500_uart0_data, 0),
2225         INGENIC_PIN_GROUP("uart0-hwflow", x1500_uart0_hwflow, 0),
2226         INGENIC_PIN_GROUP("uart1-data-a", x1500_uart1_data_a, 2),
2227         INGENIC_PIN_GROUP("uart1-data-d", x1500_uart1_data_d, 1),
2228         INGENIC_PIN_GROUP("uart1-hwflow", x1500_uart1_hwflow, 1),
2229         INGENIC_PIN_GROUP("uart2-data-a", x1500_uart2_data_a, 2),
2230         INGENIC_PIN_GROUP("uart2-data-d", x1500_uart2_data_d, 0),
2231         INGENIC_PIN_GROUP("sfc-data", x1000_sfc_data, 1),
2232         INGENIC_PIN_GROUP("sfc-clk", x1000_sfc_clk, 1),
2233         INGENIC_PIN_GROUP("sfc-ce", x1000_sfc_ce, 1),
2234         INGENIC_PIN_GROUP("mmc-1bit", x1500_mmc_1bit, 1),
2235         INGENIC_PIN_GROUP("mmc-4bit", x1500_mmc_4bit, 1),
2236         INGENIC_PIN_GROUP("i2c0-data", x1500_i2c0, 0),
2237         INGENIC_PIN_GROUP("i2c1-data-a", x1500_i2c1_a, 2),
2238         INGENIC_PIN_GROUP("i2c1-data-c", x1500_i2c1_c, 0),
2239         INGENIC_PIN_GROUP("i2c2-data", x1500_i2c2, 1),
2240         INGENIC_PIN_GROUP("i2s-data-tx", x1500_i2s_data_tx, 1),
2241         INGENIC_PIN_GROUP("i2s-data-rx", x1500_i2s_data_rx, 1),
2242         INGENIC_PIN_GROUP("i2s-clk-txrx", x1500_i2s_clk_txrx, 1),
2243         INGENIC_PIN_GROUP("i2s-sysclk", x1500_i2s_sysclk, 1),
2244         INGENIC_PIN_GROUP("dmic-if0", x1500_dmic_if0, 0),
2245         INGENIC_PIN_GROUP("dmic-if1", x1500_dmic_if1, 1),
2246         INGENIC_PIN_GROUP("cim-data", x1500_cim, 2),
2247         INGENIC_PIN_GROUP("pwm0", x1500_pwm_pwm0, 0),
2248         INGENIC_PIN_GROUP("pwm1", x1500_pwm_pwm1, 1),
2249         INGENIC_PIN_GROUP("pwm2", x1500_pwm_pwm2, 1),
2250         INGENIC_PIN_GROUP("pwm3", x1500_pwm_pwm3, 2),
2251         INGENIC_PIN_GROUP("pwm4", x1500_pwm_pwm4, 0),
2252 };
2253
2254 static const char *x1500_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
2255 static const char *x1500_uart1_groups[] = {
2256         "uart1-data-a", "uart1-data-d", "uart1-hwflow",
2257 };
2258 static const char *x1500_uart2_groups[] = { "uart2-data-a", "uart2-data-d", };
2259 static const char *x1500_mmc_groups[] = { "mmc-1bit", "mmc-4bit", };
2260 static const char *x1500_i2c0_groups[] = { "i2c0-data", };
2261 static const char *x1500_i2c1_groups[] = { "i2c1-data-a", "i2c1-data-c", };
2262 static const char *x1500_i2c2_groups[] = { "i2c2-data", };
2263 static const char *x1500_i2s_groups[] = {
2264         "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-sysclk",
2265 };
2266 static const char *x1500_dmic_groups[] = { "dmic-if0", "dmic-if1", };
2267 static const char *x1500_cim_groups[] = { "cim-data", };
2268 static const char *x1500_pwm0_groups[] = { "pwm0", };
2269 static const char *x1500_pwm1_groups[] = { "pwm1", };
2270 static const char *x1500_pwm2_groups[] = { "pwm2", };
2271 static const char *x1500_pwm3_groups[] = { "pwm3", };
2272 static const char *x1500_pwm4_groups[] = { "pwm4", };
2273
2274 static const struct function_desc x1500_functions[] = {
2275         { "uart0", x1500_uart0_groups, ARRAY_SIZE(x1500_uart0_groups), },
2276         { "uart1", x1500_uart1_groups, ARRAY_SIZE(x1500_uart1_groups), },
2277         { "uart2", x1500_uart2_groups, ARRAY_SIZE(x1500_uart2_groups), },
2278         { "sfc", x1000_sfc_groups, ARRAY_SIZE(x1000_sfc_groups), },
2279         { "mmc", x1500_mmc_groups, ARRAY_SIZE(x1500_mmc_groups), },
2280         { "i2c0", x1500_i2c0_groups, ARRAY_SIZE(x1500_i2c0_groups), },
2281         { "i2c1", x1500_i2c1_groups, ARRAY_SIZE(x1500_i2c1_groups), },
2282         { "i2c2", x1500_i2c2_groups, ARRAY_SIZE(x1500_i2c2_groups), },
2283         { "i2s", x1500_i2s_groups, ARRAY_SIZE(x1500_i2s_groups), },
2284         { "dmic", x1500_dmic_groups, ARRAY_SIZE(x1500_dmic_groups), },
2285         { "cim", x1500_cim_groups, ARRAY_SIZE(x1500_cim_groups), },
2286         { "pwm0", x1500_pwm0_groups, ARRAY_SIZE(x1500_pwm0_groups), },
2287         { "pwm1", x1500_pwm1_groups, ARRAY_SIZE(x1500_pwm1_groups), },
2288         { "pwm2", x1500_pwm2_groups, ARRAY_SIZE(x1500_pwm2_groups), },
2289         { "pwm3", x1500_pwm3_groups, ARRAY_SIZE(x1500_pwm3_groups), },
2290         { "pwm4", x1500_pwm4_groups, ARRAY_SIZE(x1500_pwm4_groups), },
2291 };
2292
2293 static const struct ingenic_chip_info x1500_chip_info = {
2294         .num_chips = 4,
2295         .reg_offset = 0x100,
2296         .version = ID_X1500,
2297         .groups = x1500_groups,
2298         .num_groups = ARRAY_SIZE(x1500_groups),
2299         .functions = x1500_functions,
2300         .num_functions = ARRAY_SIZE(x1500_functions),
2301         .pull_ups = x1000_pull_ups,
2302         .pull_downs = x1000_pull_downs,
2303 };
2304
2305 static const u32 x1830_pull_ups[4] = {
2306         0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc,
2307 };
2308
2309 static const u32 x1830_pull_downs[4] = {
2310         0x5fdfffc0, 0xffffefff, 0x1ffffbff, 0x0fcff3fc,
2311 };
2312
2313 static int x1830_uart0_data_pins[] = { 0x33, 0x36, };
2314 static int x1830_uart0_hwflow_pins[] = { 0x34, 0x35, };
2315 static int x1830_uart1_data_pins[] = { 0x38, 0x37, };
2316 static int x1830_sfc_data_pins[] = { 0x17, 0x18, 0x1a, 0x19, };
2317 static int x1830_sfc_clk_pins[] = { 0x1b, };
2318 static int x1830_sfc_ce_pins[] = { 0x1c, };
2319 static int x1830_ssi0_dt_pins[] = { 0x4c, };
2320 static int x1830_ssi0_dr_pins[] = { 0x4b, };
2321 static int x1830_ssi0_clk_pins[] = { 0x4f, };
2322 static int x1830_ssi0_gpc_pins[] = { 0x4d, };
2323 static int x1830_ssi0_ce0_pins[] = { 0x50, };
2324 static int x1830_ssi0_ce1_pins[] = { 0x4e, };
2325 static int x1830_ssi1_dt_c_pins[] = { 0x53, };
2326 static int x1830_ssi1_dt_d_pins[] = { 0x62, };
2327 static int x1830_ssi1_dr_c_pins[] = { 0x54, };
2328 static int x1830_ssi1_dr_d_pins[] = { 0x63, };
2329 static int x1830_ssi1_clk_c_pins[] = { 0x57, };
2330 static int x1830_ssi1_clk_d_pins[] = { 0x66, };
2331 static int x1830_ssi1_gpc_c_pins[] = { 0x55, };
2332 static int x1830_ssi1_gpc_d_pins[] = { 0x64, };
2333 static int x1830_ssi1_ce0_c_pins[] = { 0x58, };
2334 static int x1830_ssi1_ce0_d_pins[] = { 0x67, };
2335 static int x1830_ssi1_ce1_c_pins[] = { 0x56, };
2336 static int x1830_ssi1_ce1_d_pins[] = { 0x65, };
2337 static int x1830_mmc0_1bit_pins[] = { 0x24, 0x25, 0x20, };
2338 static int x1830_mmc0_4bit_pins[] = { 0x21, 0x22, 0x23, };
2339 static int x1830_mmc1_1bit_pins[] = { 0x42, 0x43, 0x44, };
2340 static int x1830_mmc1_4bit_pins[] = { 0x45, 0x46, 0x47, };
2341 static int x1830_i2c0_pins[] = { 0x0c, 0x0d, };
2342 static int x1830_i2c1_pins[] = { 0x39, 0x3a, };
2343 static int x1830_i2c2_pins[] = { 0x5b, 0x5c, };
2344 static int x1830_i2s_data_tx_pins[] = { 0x53, };
2345 static int x1830_i2s_data_rx_pins[] = { 0x54, };
2346 static int x1830_i2s_clk_txrx_pins[] = { 0x58, 0x52, };
2347 static int x1830_i2s_clk_rx_pins[] = { 0x56, 0x55, };
2348 static int x1830_i2s_sysclk_pins[] = { 0x57, };
2349 static int x1830_dmic_if0_pins[] = { 0x48, 0x59, };
2350 static int x1830_dmic_if1_pins[] = { 0x5a, };
2351 static int x1830_lcd_tft_8bit_pins[] = {
2352         0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
2353         0x68, 0x73, 0x72, 0x69,
2354 };
2355 static int x1830_lcd_tft_24bit_pins[] = {
2356         0x6c, 0x6d, 0x6e, 0x6f, 0x70, 0x71,
2357         0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b,
2358 };
2359 static int x1830_lcd_slcd_8bit_pins[] = {
2360         0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x6c, 0x6d,
2361         0x69, 0x72, 0x73, 0x7b, 0x7a,
2362 };
2363 static int x1830_lcd_slcd_16bit_pins[] = {
2364         0x6e, 0x6f, 0x70, 0x71, 0x76, 0x77, 0x78, 0x79,
2365 };
2366 static int x1830_pwm_pwm0_b_pins[] = { 0x31, };
2367 static int x1830_pwm_pwm0_c_pins[] = { 0x4b, };
2368 static int x1830_pwm_pwm1_b_pins[] = { 0x32, };
2369 static int x1830_pwm_pwm1_c_pins[] = { 0x4c, };
2370 static int x1830_pwm_pwm2_c_8_pins[] = { 0x48, };
2371 static int x1830_pwm_pwm2_c_13_pins[] = { 0x4d, };
2372 static int x1830_pwm_pwm3_c_9_pins[] = { 0x49, };
2373 static int x1830_pwm_pwm3_c_14_pins[] = { 0x4e, };
2374 static int x1830_pwm_pwm4_c_15_pins[] = { 0x4f, };
2375 static int x1830_pwm_pwm4_c_25_pins[] = { 0x59, };
2376 static int x1830_pwm_pwm5_c_16_pins[] = { 0x50, };
2377 static int x1830_pwm_pwm5_c_26_pins[] = { 0x5a, };
2378 static int x1830_pwm_pwm6_c_17_pins[] = { 0x51, };
2379 static int x1830_pwm_pwm6_c_27_pins[] = { 0x5b, };
2380 static int x1830_pwm_pwm7_c_18_pins[] = { 0x52, };
2381 static int x1830_pwm_pwm7_c_28_pins[] = { 0x5c, };
2382 static int x1830_mac_pins[] = {
2383         0x29, 0x30, 0x2f, 0x28, 0x2e, 0x2d, 0x2a, 0x2b, 0x26, 0x27,
2384 };
2385
2386 static const struct group_desc x1830_groups[] = {
2387         INGENIC_PIN_GROUP("uart0-data", x1830_uart0_data, 0),
2388         INGENIC_PIN_GROUP("uart0-hwflow", x1830_uart0_hwflow, 0),
2389         INGENIC_PIN_GROUP("uart1-data", x1830_uart1_data, 0),
2390         INGENIC_PIN_GROUP("sfc-data", x1830_sfc_data, 1),
2391         INGENIC_PIN_GROUP("sfc-clk", x1830_sfc_clk, 1),
2392         INGENIC_PIN_GROUP("sfc-ce", x1830_sfc_ce, 1),
2393         INGENIC_PIN_GROUP("ssi0-dt", x1830_ssi0_dt, 0),
2394         INGENIC_PIN_GROUP("ssi0-dr", x1830_ssi0_dr, 0),
2395         INGENIC_PIN_GROUP("ssi0-clk", x1830_ssi0_clk, 0),
2396         INGENIC_PIN_GROUP("ssi0-gpc", x1830_ssi0_gpc, 0),
2397         INGENIC_PIN_GROUP("ssi0-ce0", x1830_ssi0_ce0, 0),
2398         INGENIC_PIN_GROUP("ssi0-ce1", x1830_ssi0_ce1, 0),
2399         INGENIC_PIN_GROUP("ssi1-dt-c", x1830_ssi1_dt_c, 1),
2400         INGENIC_PIN_GROUP("ssi1-dr-c", x1830_ssi1_dr_c, 1),
2401         INGENIC_PIN_GROUP("ssi1-clk-c", x1830_ssi1_clk_c, 1),
2402         INGENIC_PIN_GROUP("ssi1-gpc-c", x1830_ssi1_gpc_c, 1),
2403         INGENIC_PIN_GROUP("ssi1-ce0-c", x1830_ssi1_ce0_c, 1),
2404         INGENIC_PIN_GROUP("ssi1-ce1-c", x1830_ssi1_ce1_c, 1),
2405         INGENIC_PIN_GROUP("ssi1-dt-d", x1830_ssi1_dt_d, 2),
2406         INGENIC_PIN_GROUP("ssi1-dr-d", x1830_ssi1_dr_d, 2),
2407         INGENIC_PIN_GROUP("ssi1-clk-d", x1830_ssi1_clk_d, 2),
2408         INGENIC_PIN_GROUP("ssi1-gpc-d", x1830_ssi1_gpc_d, 2),
2409         INGENIC_PIN_GROUP("ssi1-ce0-d", x1830_ssi1_ce0_d, 2),
2410         INGENIC_PIN_GROUP("ssi1-ce1-d", x1830_ssi1_ce1_d, 2),
2411         INGENIC_PIN_GROUP("mmc0-1bit", x1830_mmc0_1bit, 0),
2412         INGENIC_PIN_GROUP("mmc0-4bit", x1830_mmc0_4bit, 0),
2413         INGENIC_PIN_GROUP("mmc1-1bit", x1830_mmc1_1bit, 0),
2414         INGENIC_PIN_GROUP("mmc1-4bit", x1830_mmc1_4bit, 0),
2415         INGENIC_PIN_GROUP("i2c0-data", x1830_i2c0, 1),
2416         INGENIC_PIN_GROUP("i2c1-data", x1830_i2c1, 0),
2417         INGENIC_PIN_GROUP("i2c2-data", x1830_i2c2, 1),
2418         INGENIC_PIN_GROUP("i2s-data-tx", x1830_i2s_data_tx, 0),
2419         INGENIC_PIN_GROUP("i2s-data-rx", x1830_i2s_data_rx, 0),
2420         INGENIC_PIN_GROUP("i2s-clk-txrx", x1830_i2s_clk_txrx, 0),
2421         INGENIC_PIN_GROUP("i2s-clk-rx", x1830_i2s_clk_rx, 0),
2422         INGENIC_PIN_GROUP("i2s-sysclk", x1830_i2s_sysclk, 0),
2423         INGENIC_PIN_GROUP("dmic-if0", x1830_dmic_if0, 2),
2424         INGENIC_PIN_GROUP("dmic-if1", x1830_dmic_if1, 2),
2425         INGENIC_PIN_GROUP("lcd-tft-8bit", x1830_lcd_tft_8bit, 0),
2426         INGENIC_PIN_GROUP("lcd-tft-24bit", x1830_lcd_tft_24bit, 0),
2427         INGENIC_PIN_GROUP("lcd-slcd-8bit", x1830_lcd_slcd_8bit, 1),
2428         INGENIC_PIN_GROUP("lcd-slcd-16bit", x1830_lcd_slcd_16bit, 1),
2429         INGENIC_PIN_GROUP("pwm0-b", x1830_pwm_pwm0_b, 0),
2430         INGENIC_PIN_GROUP("pwm0-c", x1830_pwm_pwm0_c, 1),
2431         INGENIC_PIN_GROUP("pwm1-b", x1830_pwm_pwm1_b, 0),
2432         INGENIC_PIN_GROUP("pwm1-c", x1830_pwm_pwm1_c, 1),
2433         INGENIC_PIN_GROUP("pwm2-c-8", x1830_pwm_pwm2_c_8, 0),
2434         INGENIC_PIN_GROUP("pwm2-c-13", x1830_pwm_pwm2_c_13, 1),
2435         INGENIC_PIN_GROUP("pwm3-c-9", x1830_pwm_pwm3_c_9, 0),
2436         INGENIC_PIN_GROUP("pwm3-c-14", x1830_pwm_pwm3_c_14, 1),
2437         INGENIC_PIN_GROUP("pwm4-c-15", x1830_pwm_pwm4_c_15, 1),
2438         INGENIC_PIN_GROUP("pwm4-c-25", x1830_pwm_pwm4_c_25, 0),
2439         INGENIC_PIN_GROUP("pwm5-c-16", x1830_pwm_pwm5_c_16, 1),
2440         INGENIC_PIN_GROUP("pwm5-c-26", x1830_pwm_pwm5_c_26, 0),
2441         INGENIC_PIN_GROUP("pwm6-c-17", x1830_pwm_pwm6_c_17, 1),
2442         INGENIC_PIN_GROUP("pwm6-c-27", x1830_pwm_pwm6_c_27, 0),
2443         INGENIC_PIN_GROUP("pwm7-c-18", x1830_pwm_pwm7_c_18, 1),
2444         INGENIC_PIN_GROUP("pwm7-c-28", x1830_pwm_pwm7_c_28, 0),
2445         INGENIC_PIN_GROUP("mac", x1830_mac, 0),
2446 };
2447
2448 static const char *x1830_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
2449 static const char *x1830_uart1_groups[] = { "uart1-data", };
2450 static const char *x1830_sfc_groups[] = { "sfc-data", "sfc-clk", "sfc-ce", };
2451 static const char *x1830_ssi0_groups[] = {
2452         "ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-gpc", "ssi0-ce0", "ssi0-ce1",
2453 };
2454 static const char *x1830_ssi1_groups[] = {
2455         "ssi1-dt-c", "ssi1-dt-d",
2456         "ssi1-dr-c", "ssi1-dr-d",
2457         "ssi1-clk-c", "ssi1-clk-d",
2458         "ssi1-gpc-c", "ssi1-gpc-d",
2459         "ssi1-ce0-c", "ssi1-ce0-d",
2460         "ssi1-ce1-c", "ssi1-ce1-d",
2461 };
2462 static const char *x1830_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", };
2463 static const char *x1830_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
2464 static const char *x1830_i2c0_groups[] = { "i2c0-data", };
2465 static const char *x1830_i2c1_groups[] = { "i2c1-data", };
2466 static const char *x1830_i2c2_groups[] = { "i2c2-data", };
2467 static const char *x1830_i2s_groups[] = {
2468         "i2s-data-tx", "i2s-data-rx", "i2s-clk-txrx", "i2s-clk-rx", "i2s-sysclk",
2469 };
2470 static const char *x1830_dmic_groups[] = { "dmic-if0", "dmic-if1", };
2471 static const char *x1830_lcd_groups[] = {
2472         "lcd-tft-8bit", "lcd-tft-24bit", "lcd-slcd-8bit", "lcd-slcd-16bit",
2473 };
2474 static const char *x1830_pwm0_groups[] = { "pwm0-b", "pwm0-c", };
2475 static const char *x1830_pwm1_groups[] = { "pwm1-b", "pwm1-c", };
2476 static const char *x1830_pwm2_groups[] = { "pwm2-c-8", "pwm2-c-13", };
2477 static const char *x1830_pwm3_groups[] = { "pwm3-c-9", "pwm3-c-14", };
2478 static const char *x1830_pwm4_groups[] = { "pwm4-c-15", "pwm4-c-25", };
2479 static const char *x1830_pwm5_groups[] = { "pwm5-c-16", "pwm5-c-26", };
2480 static const char *x1830_pwm6_groups[] = { "pwm6-c-17", "pwm6-c-27", };
2481 static const char *x1830_pwm7_groups[] = { "pwm7-c-18", "pwm7-c-28", };
2482 static const char *x1830_mac_groups[] = { "mac", };
2483
2484 static const struct function_desc x1830_functions[] = {
2485         { "uart0", x1830_uart0_groups, ARRAY_SIZE(x1830_uart0_groups), },
2486         { "uart1", x1830_uart1_groups, ARRAY_SIZE(x1830_uart1_groups), },
2487         { "sfc", x1830_sfc_groups, ARRAY_SIZE(x1830_sfc_groups), },
2488         { "ssi0", x1830_ssi0_groups, ARRAY_SIZE(x1830_ssi0_groups), },
2489         { "ssi1", x1830_ssi1_groups, ARRAY_SIZE(x1830_ssi1_groups), },
2490         { "mmc0", x1830_mmc0_groups, ARRAY_SIZE(x1830_mmc0_groups), },
2491         { "mmc1", x1830_mmc1_groups, ARRAY_SIZE(x1830_mmc1_groups), },
2492         { "i2c0", x1830_i2c0_groups, ARRAY_SIZE(x1830_i2c0_groups), },
2493         { "i2c1", x1830_i2c1_groups, ARRAY_SIZE(x1830_i2c1_groups), },
2494         { "i2c2", x1830_i2c2_groups, ARRAY_SIZE(x1830_i2c2_groups), },
2495         { "i2s", x1830_i2s_groups, ARRAY_SIZE(x1830_i2s_groups), },
2496         { "dmic", x1830_dmic_groups, ARRAY_SIZE(x1830_dmic_groups), },
2497         { "lcd", x1830_lcd_groups, ARRAY_SIZE(x1830_lcd_groups), },
2498         { "pwm0", x1830_pwm0_groups, ARRAY_SIZE(x1830_pwm0_groups), },
2499         { "pwm1", x1830_pwm1_groups, ARRAY_SIZE(x1830_pwm1_groups), },
2500         { "pwm2", x1830_pwm2_groups, ARRAY_SIZE(x1830_pwm2_groups), },
2501         { "pwm3", x1830_pwm3_groups, ARRAY_SIZE(x1830_pwm3_groups), },
2502         { "pwm4", x1830_pwm4_groups, ARRAY_SIZE(x1830_pwm4_groups), },
2503         { "pwm5", x1830_pwm5_groups, ARRAY_SIZE(x1830_pwm4_groups), },
2504         { "pwm6", x1830_pwm6_groups, ARRAY_SIZE(x1830_pwm4_groups), },
2505         { "pwm7", x1830_pwm7_groups, ARRAY_SIZE(x1830_pwm4_groups), },
2506         { "mac", x1830_mac_groups, ARRAY_SIZE(x1830_mac_groups), },
2507 };
2508
2509 static const struct ingenic_chip_info x1830_chip_info = {
2510         .num_chips = 4,
2511         .reg_offset = 0x1000,
2512         .version = ID_X1830,
2513         .groups = x1830_groups,
2514         .num_groups = ARRAY_SIZE(x1830_groups),
2515         .functions = x1830_functions,
2516         .num_functions = ARRAY_SIZE(x1830_functions),
2517         .pull_ups = x1830_pull_ups,
2518         .pull_downs = x1830_pull_downs,
2519 };
2520
2521 static const u32 x2000_pull_ups[5] = {
2522         0x0003ffff, 0xffffffff, 0x1ff0ffff, 0xc7fe3f3f, 0x8fff003f,
2523 };
2524
2525 static const u32 x2000_pull_downs[5] = {
2526         0x0003ffff, 0xffffffff, 0x1ff0ffff, 0x00000000, 0x8fff003f,
2527 };
2528
2529 static int x2000_uart0_data_pins[] = { 0x77, 0x78, };
2530 static int x2000_uart0_hwflow_pins[] = { 0x79, 0x7a, };
2531 static int x2000_uart1_data_pins[] = { 0x57, 0x58, };
2532 static int x2000_uart1_hwflow_pins[] = { 0x55, 0x56, };
2533 static int x2000_uart2_data_pins[] = { 0x7e, 0x7f, };
2534 static int x2000_uart3_data_c_pins[] = { 0x59, 0x5a, };
2535 static int x2000_uart3_data_d_pins[] = { 0x62, 0x63, };
2536 static int x2000_uart3_hwflow_c_pins[] = { 0x5b, 0x5c, };
2537 static int x2000_uart3_hwflow_d_pins[] = { 0x60, 0x61, };
2538 static int x2000_uart4_data_a_pins[] = { 0x02, 0x03, };
2539 static int x2000_uart4_data_c_pins[] = { 0x4b, 0x4c, };
2540 static int x2000_uart4_hwflow_a_pins[] = { 0x00, 0x01, };
2541 static int x2000_uart4_hwflow_c_pins[] = { 0x49, 0x4a, };
2542 static int x2000_uart5_data_a_pins[] = { 0x04, 0x05, };
2543 static int x2000_uart5_data_c_pins[] = { 0x45, 0x46, };
2544 static int x2000_uart6_data_a_pins[] = { 0x06, 0x07, };
2545 static int x2000_uart6_data_c_pins[] = { 0x47, 0x48, };
2546 static int x2000_uart7_data_a_pins[] = { 0x08, 0x09, };
2547 static int x2000_uart7_data_c_pins[] = { 0x41, 0x42, };
2548 static int x2000_uart8_data_pins[] = { 0x3c, 0x3d, };
2549 static int x2000_uart9_data_pins[] = { 0x3e, 0x3f, };
2550 static int x2000_sfc_data_if0_d_pins[] = { 0x73, 0x74, 0x75, 0x76, };
2551 static int x2000_sfc_data_if0_e_pins[] = { 0x92, 0x93, 0x94, 0x95, };
2552 static int x2000_sfc_data_if1_pins[] = { 0x77, 0x78, 0x79, 0x7a, };
2553 static int x2000_sfc_clk_d_pins[] = { 0x71, };
2554 static int x2000_sfc_clk_e_pins[] = { 0x90, };
2555 static int x2000_sfc_ce_d_pins[] = { 0x72, };
2556 static int x2000_sfc_ce_e_pins[] = { 0x91, };
2557 static int x2000_ssi0_dt_b_pins[] = { 0x3e, };
2558 static int x2000_ssi0_dt_d_pins[] = { 0x69, };
2559 static int x2000_ssi0_dr_b_pins[] = { 0x3d, };
2560 static int x2000_ssi0_dr_d_pins[] = { 0x6a, };
2561 static int x2000_ssi0_clk_b_pins[] = { 0x3f, };
2562 static int x2000_ssi0_clk_d_pins[] = { 0x68, };
2563 static int x2000_ssi0_ce_b_pins[] = { 0x3c, };
2564 static int x2000_ssi0_ce_d_pins[] = { 0x6d, };
2565 static int x2000_ssi1_dt_c_pins[] = { 0x4b, };
2566 static int x2000_ssi1_dt_d_pins[] = { 0x72, };
2567 static int x2000_ssi1_dt_e_pins[] = { 0x91, };
2568 static int x2000_ssi1_dr_c_pins[] = { 0x4a, };
2569 static int x2000_ssi1_dr_d_pins[] = { 0x73, };
2570 static int x2000_ssi1_dr_e_pins[] = { 0x92, };
2571 static int x2000_ssi1_clk_c_pins[] = { 0x4c, };
2572 static int x2000_ssi1_clk_d_pins[] = { 0x71, };
2573 static int x2000_ssi1_clk_e_pins[] = { 0x90, };
2574 static int x2000_ssi1_ce_c_pins[] = { 0x49, };
2575 static int x2000_ssi1_ce_d_pins[] = { 0x76, };
2576 static int x2000_ssi1_ce_e_pins[] = { 0x95, };
2577 static int x2000_mmc0_1bit_pins[] = { 0x71, 0x72, 0x73, };
2578 static int x2000_mmc0_4bit_pins[] = { 0x74, 0x75, 0x75, };
2579 static int x2000_mmc0_8bit_pins[] = { 0x77, 0x78, 0x79, 0x7a, };
2580 static int x2000_mmc1_1bit_pins[] = { 0x68, 0x69, 0x6a, };
2581 static int x2000_mmc1_4bit_pins[] = { 0x6b, 0x6c, 0x6d, };
2582 static int x2000_mmc2_1bit_pins[] = { 0x80, 0x81, 0x82, };
2583 static int x2000_mmc2_4bit_pins[] = { 0x83, 0x84, 0x85, };
2584 static int x2000_emc_8bit_data_pins[] = {
2585         0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
2586 };
2587 static int x2000_emc_16bit_data_pins[] = {
2588         0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
2589 };
2590 static int x2000_emc_addr_pins[] = {
2591         0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
2592         0x28, 0x29, 0x2a, 0x2b, 0x2c,
2593 };
2594 static int x2000_emc_rd_we_pins[] = { 0x2d, 0x2e, };
2595 static int x2000_emc_wait_pins[] = { 0x2f, };
2596 static int x2000_emc_cs1_pins[] = { 0x57, };
2597 static int x2000_emc_cs2_pins[] = { 0x58, };
2598 static int x2000_i2c0_pins[] = { 0x4e, 0x4d, };
2599 static int x2000_i2c1_c_pins[] = { 0x58, 0x57, };
2600 static int x2000_i2c1_d_pins[] = { 0x6c, 0x6b, };
2601 static int x2000_i2c2_b_pins[] = { 0x37, 0x36, };
2602 static int x2000_i2c2_d_pins[] = { 0x75, 0x74, };
2603 static int x2000_i2c2_e_pins[] = { 0x94, 0x93, };
2604 static int x2000_i2c3_a_pins[] = { 0x11, 0x10, };
2605 static int x2000_i2c3_d_pins[] = { 0x7f, 0x7e, };
2606 static int x2000_i2c4_c_pins[] = { 0x5a, 0x59, };
2607 static int x2000_i2c4_d_pins[] = { 0x61, 0x60, };
2608 static int x2000_i2c5_c_pins[] = { 0x5c, 0x5b, };
2609 static int x2000_i2c5_d_pins[] = { 0x65, 0x64, };
2610 static int x2000_i2s1_data_tx_pins[] = { 0x47, };
2611 static int x2000_i2s1_data_rx_pins[] = { 0x44, };
2612 static int x2000_i2s1_clk_tx_pins[] = { 0x45, 0x46, };
2613 static int x2000_i2s1_clk_rx_pins[] = { 0x42, 0x43, };
2614 static int x2000_i2s1_sysclk_tx_pins[] = { 0x48, };
2615 static int x2000_i2s1_sysclk_rx_pins[] = { 0x41, };
2616 static int x2000_i2s2_data_rx0_pins[] = { 0x0a, };
2617 static int x2000_i2s2_data_rx1_pins[] = { 0x0b, };
2618 static int x2000_i2s2_data_rx2_pins[] = { 0x0c, };
2619 static int x2000_i2s2_data_rx3_pins[] = { 0x0d, };
2620 static int x2000_i2s2_clk_rx_pins[] = { 0x11, 0x09, };
2621 static int x2000_i2s2_sysclk_rx_pins[] = { 0x07, };
2622 static int x2000_i2s3_data_tx0_pins[] = { 0x03, };
2623 static int x2000_i2s3_data_tx1_pins[] = { 0x04, };
2624 static int x2000_i2s3_data_tx2_pins[] = { 0x05, };
2625 static int x2000_i2s3_data_tx3_pins[] = { 0x06, };
2626 static int x2000_i2s3_clk_tx_pins[] = { 0x10, 0x02, };
2627 static int x2000_i2s3_sysclk_tx_pins[] = { 0x00, };
2628 static int x2000_dmic_if0_pins[] = { 0x54, 0x55, };
2629 static int x2000_dmic_if1_pins[] = { 0x56, };
2630 static int x2000_dmic_if2_pins[] = { 0x57, };
2631 static int x2000_dmic_if3_pins[] = { 0x58, };
2632 static int x2000_cim_8bit_pins[] = {
2633         0x0e, 0x0c, 0x0d, 0x4f,
2634         0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
2635 };
2636 static int x2000_cim_12bit_pins[] = { 0x08, 0x09, 0x0a, 0x0b, };
2637 static int x2000_lcd_tft_8bit_pins[] = {
2638         0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
2639         0x38, 0x3a, 0x39, 0x3b,
2640 };
2641 static int x2000_lcd_tft_16bit_pins[] = {
2642         0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
2643 };
2644 static int x2000_lcd_tft_18bit_pins[] = {
2645         0x30, 0x31,
2646 };
2647 static int x2000_lcd_tft_24bit_pins[] = {
2648         0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
2649 };
2650 static int x2000_lcd_slcd_8bit_pins[] = {
2651         0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
2652         0x3a, 0x38, 0x3b, 0x30, 0x39,
2653 };
2654 static int x2000_pwm_pwm0_c_pins[] = { 0x40, };
2655 static int x2000_pwm_pwm0_d_pins[] = { 0x7e, };
2656 static int x2000_pwm_pwm1_c_pins[] = { 0x41, };
2657 static int x2000_pwm_pwm1_d_pins[] = { 0x7f, };
2658 static int x2000_pwm_pwm2_c_pins[] = { 0x42, };
2659 static int x2000_pwm_pwm2_e_pins[] = { 0x80, };
2660 static int x2000_pwm_pwm3_c_pins[] = { 0x43, };
2661 static int x2000_pwm_pwm3_e_pins[] = { 0x81, };
2662 static int x2000_pwm_pwm4_c_pins[] = { 0x44, };
2663 static int x2000_pwm_pwm4_e_pins[] = { 0x82, };
2664 static int x2000_pwm_pwm5_c_pins[] = { 0x45, };
2665 static int x2000_pwm_pwm5_e_pins[] = { 0x83, };
2666 static int x2000_pwm_pwm6_c_pins[] = { 0x46, };
2667 static int x2000_pwm_pwm6_e_pins[] = { 0x84, };
2668 static int x2000_pwm_pwm7_c_pins[] = { 0x47, };
2669 static int x2000_pwm_pwm7_e_pins[] = { 0x85, };
2670 static int x2000_pwm_pwm8_pins[] = { 0x48, };
2671 static int x2000_pwm_pwm9_pins[] = { 0x49, };
2672 static int x2000_pwm_pwm10_pins[] = { 0x4a, };
2673 static int x2000_pwm_pwm11_pins[] = { 0x4b, };
2674 static int x2000_pwm_pwm12_pins[] = { 0x4c, };
2675 static int x2000_pwm_pwm13_pins[] = { 0x4d, };
2676 static int x2000_pwm_pwm14_pins[] = { 0x4e, };
2677 static int x2000_pwm_pwm15_pins[] = { 0x4f, };
2678 static int x2000_mac0_rmii_pins[] = {
2679         0x4b, 0x47, 0x46, 0x4a, 0x43, 0x42, 0x4c, 0x4d, 0x4e, 0x41,
2680 };
2681 static int x2000_mac0_rgmii_pins[] = {
2682         0x4b, 0x49, 0x48, 0x47, 0x46, 0x4a, 0x45, 0x44, 0x43, 0x42,
2683         0x4c, 0x4d, 0x4f, 0x4e, 0x41,
2684 };
2685 static int x2000_mac1_rmii_pins[] = {
2686         0x32, 0x2d, 0x2c, 0x31, 0x29, 0x28, 0x33, 0x34, 0x35, 0x37,
2687 };
2688 static int x2000_mac1_rgmii_pins[] = {
2689         0x32, 0x2f, 0x2e, 0x2d, 0x2c, 0x31, 0x2b, 0x2a, 0x29, 0x28,
2690         0x33, 0x34, 0x36, 0x35, 0x37,
2691 };
2692 static int x2000_otg_pins[] = { 0x96, };
2693
2694 static u8 x2000_cim_8bit_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, };
2695
2696 static const struct group_desc x2000_groups[] = {
2697         INGENIC_PIN_GROUP("uart0-data", x2000_uart0_data, 2),
2698         INGENIC_PIN_GROUP("uart0-hwflow", x2000_uart0_hwflow, 2),
2699         INGENIC_PIN_GROUP("uart1-data", x2000_uart1_data, 1),
2700         INGENIC_PIN_GROUP("uart1-hwflow", x2000_uart1_hwflow, 1),
2701         INGENIC_PIN_GROUP("uart2-data", x2000_uart2_data, 0),
2702         INGENIC_PIN_GROUP("uart3-data-c", x2000_uart3_data_c, 0),
2703         INGENIC_PIN_GROUP("uart3-data-d", x2000_uart3_data_d, 1),
2704         INGENIC_PIN_GROUP("uart3-hwflow-c", x2000_uart3_hwflow_c, 0),
2705         INGENIC_PIN_GROUP("uart3-hwflow-d", x2000_uart3_hwflow_d, 1),
2706         INGENIC_PIN_GROUP("uart4-data-a", x2000_uart4_data_a, 1),
2707         INGENIC_PIN_GROUP("uart4-data-c", x2000_uart4_data_c, 3),
2708         INGENIC_PIN_GROUP("uart4-hwflow-a", x2000_uart4_hwflow_a, 1),
2709         INGENIC_PIN_GROUP("uart4-hwflow-c", x2000_uart4_hwflow_c, 3),
2710         INGENIC_PIN_GROUP("uart5-data-a", x2000_uart5_data_a, 1),
2711         INGENIC_PIN_GROUP("uart5-data-c", x2000_uart5_data_c, 3),
2712         INGENIC_PIN_GROUP("uart6-data-a", x2000_uart6_data_a, 1),
2713         INGENIC_PIN_GROUP("uart6-data-c", x2000_uart6_data_c, 3),
2714         INGENIC_PIN_GROUP("uart7-data-a", x2000_uart7_data_a, 1),
2715         INGENIC_PIN_GROUP("uart7-data-c", x2000_uart7_data_c, 3),
2716         INGENIC_PIN_GROUP("uart8-data", x2000_uart8_data, 3),
2717         INGENIC_PIN_GROUP("uart9-data", x2000_uart9_data, 3),
2718         INGENIC_PIN_GROUP("sfc-data-if0-d", x2000_sfc_data_if0_d, 1),
2719         INGENIC_PIN_GROUP("sfc-data-if0-e", x2000_sfc_data_if0_e, 0),
2720         INGENIC_PIN_GROUP("sfc-data-if1", x2000_sfc_data_if1, 1),
2721         INGENIC_PIN_GROUP("sfc-clk-d", x2000_sfc_clk_d, 1),
2722         INGENIC_PIN_GROUP("sfc-clk-e", x2000_sfc_clk_e, 0),
2723         INGENIC_PIN_GROUP("sfc-ce-d", x2000_sfc_ce_d, 1),
2724         INGENIC_PIN_GROUP("sfc-ce-e", x2000_sfc_ce_e, 0),
2725         INGENIC_PIN_GROUP("ssi0-dt-b", x2000_ssi0_dt_b, 1),
2726         INGENIC_PIN_GROUP("ssi0-dt-d", x2000_ssi0_dt_d, 1),
2727         INGENIC_PIN_GROUP("ssi0-dr-b", x2000_ssi0_dr_b, 1),
2728         INGENIC_PIN_GROUP("ssi0-dr-d", x2000_ssi0_dr_d, 1),
2729         INGENIC_PIN_GROUP("ssi0-clk-b", x2000_ssi0_clk_b, 1),
2730         INGENIC_PIN_GROUP("ssi0-clk-d", x2000_ssi0_clk_d, 1),
2731         INGENIC_PIN_GROUP("ssi0-ce-b", x2000_ssi0_ce_b, 1),
2732         INGENIC_PIN_GROUP("ssi0-ce-d", x2000_ssi0_ce_d, 1),
2733         INGENIC_PIN_GROUP("ssi1-dt-c", x2000_ssi1_dt_c, 2),
2734         INGENIC_PIN_GROUP("ssi1-dt-d", x2000_ssi1_dt_d, 2),
2735         INGENIC_PIN_GROUP("ssi1-dt-e", x2000_ssi1_dt_e, 1),
2736         INGENIC_PIN_GROUP("ssi1-dr-c", x2000_ssi1_dr_c, 2),
2737         INGENIC_PIN_GROUP("ssi1-dr-d", x2000_ssi1_dr_d, 2),
2738         INGENIC_PIN_GROUP("ssi1-dr-e", x2000_ssi1_dr_e, 1),
2739         INGENIC_PIN_GROUP("ssi1-clk-c", x2000_ssi1_clk_c, 2),
2740         INGENIC_PIN_GROUP("ssi1-clk-d", x2000_ssi1_clk_d, 2),
2741         INGENIC_PIN_GROUP("ssi1-clk-e", x2000_ssi1_clk_e, 1),
2742         INGENIC_PIN_GROUP("ssi1-ce-c", x2000_ssi1_ce_c, 2),
2743         INGENIC_PIN_GROUP("ssi1-ce-d", x2000_ssi1_ce_d, 2),
2744         INGENIC_PIN_GROUP("ssi1-ce-e", x2000_ssi1_ce_e, 1),
2745         INGENIC_PIN_GROUP("mmc0-1bit", x2000_mmc0_1bit, 0),
2746         INGENIC_PIN_GROUP("mmc0-4bit", x2000_mmc0_4bit, 0),
2747         INGENIC_PIN_GROUP("mmc0-8bit", x2000_mmc0_8bit, 0),
2748         INGENIC_PIN_GROUP("mmc1-1bit", x2000_mmc1_1bit, 0),
2749         INGENIC_PIN_GROUP("mmc1-4bit", x2000_mmc1_4bit, 0),
2750         INGENIC_PIN_GROUP("mmc2-1bit", x2000_mmc2_1bit, 0),
2751         INGENIC_PIN_GROUP("mmc2-4bit", x2000_mmc2_4bit, 0),
2752         INGENIC_PIN_GROUP("emc-8bit-data", x2000_emc_8bit_data, 0),
2753         INGENIC_PIN_GROUP("emc-16bit-data", x2000_emc_16bit_data, 0),
2754         INGENIC_PIN_GROUP("emc-addr", x2000_emc_addr, 0),
2755         INGENIC_PIN_GROUP("emc-rd-we", x2000_emc_rd_we, 0),
2756         INGENIC_PIN_GROUP("emc-wait", x2000_emc_wait, 0),
2757         INGENIC_PIN_GROUP("emc-cs1", x2000_emc_cs1, 3),
2758         INGENIC_PIN_GROUP("emc-cs2", x2000_emc_cs2, 3),
2759         INGENIC_PIN_GROUP("i2c0-data", x2000_i2c0, 3),
2760         INGENIC_PIN_GROUP("i2c1-data-c", x2000_i2c1_c, 2),
2761         INGENIC_PIN_GROUP("i2c1-data-d", x2000_i2c1_d, 1),
2762         INGENIC_PIN_GROUP("i2c2-data-b", x2000_i2c2_b, 2),
2763         INGENIC_PIN_GROUP("i2c2-data-d", x2000_i2c2_d, 2),
2764         INGENIC_PIN_GROUP("i2c2-data-e", x2000_i2c2_e, 1),
2765         INGENIC_PIN_GROUP("i2c3-data-a", x2000_i2c3_a, 0),
2766         INGENIC_PIN_GROUP("i2c3-data-d", x2000_i2c3_d, 1),
2767         INGENIC_PIN_GROUP("i2c4-data-c", x2000_i2c4_c, 1),
2768         INGENIC_PIN_GROUP("i2c4-data-d", x2000_i2c4_d, 2),
2769         INGENIC_PIN_GROUP("i2c5-data-c", x2000_i2c5_c, 1),
2770         INGENIC_PIN_GROUP("i2c5-data-d", x2000_i2c5_d, 1),
2771         INGENIC_PIN_GROUP("i2s1-data-tx", x2000_i2s1_data_tx, 2),
2772         INGENIC_PIN_GROUP("i2s1-data-rx", x2000_i2s1_data_rx, 2),
2773         INGENIC_PIN_GROUP("i2s1-clk-tx", x2000_i2s1_clk_tx, 2),
2774         INGENIC_PIN_GROUP("i2s1-clk-rx", x2000_i2s1_clk_rx, 2),
2775         INGENIC_PIN_GROUP("i2s1-sysclk-tx", x2000_i2s1_sysclk_tx, 2),
2776         INGENIC_PIN_GROUP("i2s1-sysclk-rx", x2000_i2s1_sysclk_rx, 2),
2777         INGENIC_PIN_GROUP("i2s2-data-rx0", x2000_i2s2_data_rx0, 2),
2778         INGENIC_PIN_GROUP("i2s2-data-rx1", x2000_i2s2_data_rx1, 2),
2779         INGENIC_PIN_GROUP("i2s2-data-rx2", x2000_i2s2_data_rx2, 2),
2780         INGENIC_PIN_GROUP("i2s2-data-rx3", x2000_i2s2_data_rx3, 2),
2781         INGENIC_PIN_GROUP("i2s2-clk-rx", x2000_i2s2_clk_rx, 2),
2782         INGENIC_PIN_GROUP("i2s2-sysclk-rx", x2000_i2s2_sysclk_rx, 2),
2783         INGENIC_PIN_GROUP("i2s3-data-tx0", x2000_i2s3_data_tx0, 2),
2784         INGENIC_PIN_GROUP("i2s3-data-tx1", x2000_i2s3_data_tx1, 2),
2785         INGENIC_PIN_GROUP("i2s3-data-tx2", x2000_i2s3_data_tx2, 2),
2786         INGENIC_PIN_GROUP("i2s3-data-tx3", x2000_i2s3_data_tx3, 2),
2787         INGENIC_PIN_GROUP("i2s3-clk-tx", x2000_i2s3_clk_tx, 2),
2788         INGENIC_PIN_GROUP("i2s3-sysclk-tx", x2000_i2s3_sysclk_tx, 2),
2789         INGENIC_PIN_GROUP("dmic-if0", x2000_dmic_if0, 0),
2790         INGENIC_PIN_GROUP("dmic-if1", x2000_dmic_if1, 0),
2791         INGENIC_PIN_GROUP("dmic-if2", x2000_dmic_if2, 0),
2792         INGENIC_PIN_GROUP("dmic-if3", x2000_dmic_if3, 0),
2793         INGENIC_PIN_GROUP_FUNCS("cim-data-8bit", x2000_cim_8bit,
2794                                 x2000_cim_8bit_funcs),
2795         INGENIC_PIN_GROUP("cim-data-12bit", x2000_cim_12bit, 0),
2796         INGENIC_PIN_GROUP("lcd-tft-8bit", x2000_lcd_tft_8bit, 1),
2797         INGENIC_PIN_GROUP("lcd-tft-16bit", x2000_lcd_tft_16bit, 1),
2798         INGENIC_PIN_GROUP("lcd-tft-18bit", x2000_lcd_tft_18bit, 1),
2799         INGENIC_PIN_GROUP("lcd-tft-24bit", x2000_lcd_tft_24bit, 1),
2800         INGENIC_PIN_GROUP("lcd-slcd-8bit", x2000_lcd_slcd_8bit, 2),
2801         INGENIC_PIN_GROUP("lcd-slcd-16bit", x2000_lcd_tft_16bit, 2),
2802         INGENIC_PIN_GROUP("pwm0-c", x2000_pwm_pwm0_c, 0),
2803         INGENIC_PIN_GROUP("pwm0-d", x2000_pwm_pwm0_d, 2),
2804         INGENIC_PIN_GROUP("pwm1-c", x2000_pwm_pwm1_c, 0),
2805         INGENIC_PIN_GROUP("pwm1-d", x2000_pwm_pwm1_d, 2),
2806         INGENIC_PIN_GROUP("pwm2-c", x2000_pwm_pwm2_c, 0),
2807         INGENIC_PIN_GROUP("pwm2-e", x2000_pwm_pwm2_e, 1),
2808         INGENIC_PIN_GROUP("pwm3-c", x2000_pwm_pwm3_c, 0),
2809         INGENIC_PIN_GROUP("pwm3-e", x2000_pwm_pwm3_e, 1),
2810         INGENIC_PIN_GROUP("pwm4-c", x2000_pwm_pwm4_c, 0),
2811         INGENIC_PIN_GROUP("pwm4-e", x2000_pwm_pwm4_e, 1),
2812         INGENIC_PIN_GROUP("pwm5-c", x2000_pwm_pwm5_c, 0),
2813         INGENIC_PIN_GROUP("pwm5-e", x2000_pwm_pwm5_e, 1),
2814         INGENIC_PIN_GROUP("pwm6-c", x2000_pwm_pwm6_c, 0),
2815         INGENIC_PIN_GROUP("pwm6-e", x2000_pwm_pwm6_e, 1),
2816         INGENIC_PIN_GROUP("pwm7-c", x2000_pwm_pwm7_c, 0),
2817         INGENIC_PIN_GROUP("pwm7-e", x2000_pwm_pwm7_e, 1),
2818         INGENIC_PIN_GROUP("pwm8", x2000_pwm_pwm8, 0),
2819         INGENIC_PIN_GROUP("pwm9", x2000_pwm_pwm9, 0),
2820         INGENIC_PIN_GROUP("pwm10", x2000_pwm_pwm10, 0),
2821         INGENIC_PIN_GROUP("pwm11", x2000_pwm_pwm11, 0),
2822         INGENIC_PIN_GROUP("pwm12", x2000_pwm_pwm12, 0),
2823         INGENIC_PIN_GROUP("pwm13", x2000_pwm_pwm13, 0),
2824         INGENIC_PIN_GROUP("pwm14", x2000_pwm_pwm14, 0),
2825         INGENIC_PIN_GROUP("pwm15", x2000_pwm_pwm15, 0),
2826         INGENIC_PIN_GROUP("mac0-rmii", x2000_mac0_rmii, 1),
2827         INGENIC_PIN_GROUP("mac0-rgmii", x2000_mac0_rgmii, 1),
2828         INGENIC_PIN_GROUP("mac1-rmii", x2000_mac1_rmii, 3),
2829         INGENIC_PIN_GROUP("mac1-rgmii", x2000_mac1_rgmii, 3),
2830         INGENIC_PIN_GROUP("otg-vbus", x2000_otg, 0),
2831 };
2832
2833 static const char *x2000_uart0_groups[] = { "uart0-data", "uart0-hwflow", };
2834 static const char *x2000_uart1_groups[] = { "uart1-data", "uart1-hwflow", };
2835 static const char *x2000_uart2_groups[] = { "uart2-data", };
2836 static const char *x2000_uart3_groups[] = {
2837         "uart3-data-c", "uart3-data-d", "uart3-hwflow-c", "uart3-hwflow-d",
2838 };
2839 static const char *x2000_uart4_groups[] = {
2840         "uart4-data-a", "uart4-data-c", "uart4-hwflow-a", "uart4-hwflow-c",
2841 };
2842 static const char *x2000_uart5_groups[] = { "uart5-data-a", "uart5-data-c", };
2843 static const char *x2000_uart6_groups[] = { "uart6-data-a", "uart6-data-c", };
2844 static const char *x2000_uart7_groups[] = { "uart7-data-a", "uart7-data-c", };
2845 static const char *x2000_uart8_groups[] = { "uart8-data", };
2846 static const char *x2000_uart9_groups[] = { "uart9-data", };
2847 static const char *x2000_sfc_groups[] = {
2848         "sfc-data-if0-d", "sfc-data-if0-e", "sfc-data-if1",
2849         "sfc-clk-d", "sfc-clk-e", "sfc-ce-d", "sfc-ce-e",
2850 };
2851 static const char *x2000_ssi0_groups[] = {
2852         "ssi0-dt-b", "ssi0-dt-d",
2853         "ssi0-dr-b", "ssi0-dr-d",
2854         "ssi0-clk-b", "ssi0-clk-d",
2855         "ssi0-ce-b", "ssi0-ce-d",
2856 };
2857 static const char *x2000_ssi1_groups[] = {
2858         "ssi1-dt-c", "ssi1-dt-d", "ssi1-dt-e",
2859         "ssi1-dr-c", "ssi1-dr-d", "ssi1-dr-e",
2860         "ssi1-clk-c", "ssi1-clk-d", "ssi1-clk-e",
2861         "ssi1-ce-c", "ssi1-ce-d", "ssi1-ce-e",
2862 };
2863 static const char *x2000_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", "mmc0-8bit", };
2864 static const char *x2000_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", };
2865 static const char *x2000_mmc2_groups[] = { "mmc2-1bit", "mmc2-4bit", };
2866 static const char *x2000_emc_groups[] = {
2867         "emc-8bit-data", "emc-16bit-data",
2868         "emc-addr", "emc-rd-we", "emc-wait",
2869 };
2870 static const char *x2000_cs1_groups[] = { "emc-cs1", };
2871 static const char *x2000_cs2_groups[] = { "emc-cs2", };
2872 static const char *x2000_i2c0_groups[] = { "i2c0-data", };
2873 static const char *x2000_i2c1_groups[] = { "i2c1-data-c", "i2c1-data-d", };
2874 static const char *x2000_i2c2_groups[] = { "i2c2-data-b", "i2c2-data-d", };
2875 static const char *x2000_i2c3_groups[] = { "i2c3-data-a", "i2c3-data-d", };
2876 static const char *x2000_i2c4_groups[] = { "i2c4-data-c", "i2c4-data-d", };
2877 static const char *x2000_i2c5_groups[] = { "i2c5-data-c", "i2c5-data-d", };
2878 static const char *x2000_i2s1_groups[] = {
2879         "i2s1-data-tx", "i2s1-data-rx",
2880         "i2s1-clk-tx", "i2s1-clk-rx",
2881         "i2s1-sysclk-tx", "i2s1-sysclk-rx",
2882 };
2883 static const char *x2000_i2s2_groups[] = {
2884         "i2s2-data-rx0", "i2s2-data-rx1", "i2s2-data-rx2", "i2s2-data-rx3",
2885         "i2s2-clk-rx", "i2s2-sysclk-rx",
2886 };
2887 static const char *x2000_i2s3_groups[] = {
2888         "i2s3-data-tx0", "i2s3-data-tx1", "i2s3-data-tx2", "i2s3-data-tx3",
2889         "i2s3-clk-tx", "i2s3-sysclk-tx",
2890 };
2891 static const char *x2000_dmic_groups[] = {
2892         "dmic-if0", "dmic-if1", "dmic-if2", "dmic-if3",
2893 };
2894 static const char *x2000_cim_groups[] = { "cim-data-8bit", "cim-data-12bit", };
2895 static const char *x2000_lcd_groups[] = {
2896         "lcd-tft-8bit", "lcd-tft-16bit", "lcd-tft-18bit", "lcd-tft-24bit",
2897         "lcd-slcd-8bit", "lcd-slcd-16bit",
2898 };
2899 static const char *x2000_pwm0_groups[] = { "pwm0-c", "pwm0-d", };
2900 static const char *x2000_pwm1_groups[] = { "pwm1-c", "pwm1-d", };
2901 static const char *x2000_pwm2_groups[] = { "pwm2-c", "pwm2-e", };
2902 static const char *x2000_pwm3_groups[] = { "pwm3-c", "pwm3-r", };
2903 static const char *x2000_pwm4_groups[] = { "pwm4-c", "pwm4-e", };
2904 static const char *x2000_pwm5_groups[] = { "pwm5-c", "pwm5-e", };
2905 static const char *x2000_pwm6_groups[] = { "pwm6-c", "pwm6-e", };
2906 static const char *x2000_pwm7_groups[] = { "pwm7-c", "pwm7-e", };
2907 static const char *x2000_pwm8_groups[] = { "pwm8", };
2908 static const char *x2000_pwm9_groups[] = { "pwm9", };
2909 static const char *x2000_pwm10_groups[] = { "pwm10", };
2910 static const char *x2000_pwm11_groups[] = { "pwm11", };
2911 static const char *x2000_pwm12_groups[] = { "pwm12", };
2912 static const char *x2000_pwm13_groups[] = { "pwm13", };
2913 static const char *x2000_pwm14_groups[] = { "pwm14", };
2914 static const char *x2000_pwm15_groups[] = { "pwm15", };
2915 static const char *x2000_mac0_groups[] = { "mac0-rmii", "mac0-rgmii", };
2916 static const char *x2000_mac1_groups[] = { "mac1-rmii", "mac1-rgmii", };
2917 static const char *x2000_otg_groups[] = { "otg-vbus", };
2918
2919 static const struct function_desc x2000_functions[] = {
2920         { "uart0", x2000_uart0_groups, ARRAY_SIZE(x2000_uart0_groups), },
2921         { "uart1", x2000_uart1_groups, ARRAY_SIZE(x2000_uart1_groups), },
2922         { "uart2", x2000_uart2_groups, ARRAY_SIZE(x2000_uart2_groups), },
2923         { "uart3", x2000_uart3_groups, ARRAY_SIZE(x2000_uart3_groups), },
2924         { "uart4", x2000_uart4_groups, ARRAY_SIZE(x2000_uart4_groups), },
2925         { "uart5", x2000_uart5_groups, ARRAY_SIZE(x2000_uart5_groups), },
2926         { "uart6", x2000_uart6_groups, ARRAY_SIZE(x2000_uart6_groups), },
2927         { "uart7", x2000_uart7_groups, ARRAY_SIZE(x2000_uart7_groups), },
2928         { "uart8", x2000_uart8_groups, ARRAY_SIZE(x2000_uart8_groups), },
2929         { "uart9", x2000_uart9_groups, ARRAY_SIZE(x2000_uart9_groups), },
2930         { "sfc", x2000_sfc_groups, ARRAY_SIZE(x2000_sfc_groups), },
2931         { "ssi0", x2000_ssi0_groups, ARRAY_SIZE(x2000_ssi0_groups), },
2932         { "ssi1", x2000_ssi1_groups, ARRAY_SIZE(x2000_ssi1_groups), },
2933         { "mmc0", x2000_mmc0_groups, ARRAY_SIZE(x2000_mmc0_groups), },
2934         { "mmc1", x2000_mmc1_groups, ARRAY_SIZE(x2000_mmc1_groups), },
2935         { "mmc2", x2000_mmc2_groups, ARRAY_SIZE(x2000_mmc2_groups), },
2936         { "emc", x2000_emc_groups, ARRAY_SIZE(x2000_emc_groups), },
2937         { "emc-cs1", x2000_cs1_groups, ARRAY_SIZE(x2000_cs1_groups), },
2938         { "emc-cs2", x2000_cs2_groups, ARRAY_SIZE(x2000_cs2_groups), },
2939         { "i2c0", x2000_i2c0_groups, ARRAY_SIZE(x2000_i2c0_groups), },
2940         { "i2c1", x2000_i2c1_groups, ARRAY_SIZE(x2000_i2c1_groups), },
2941         { "i2c2", x2000_i2c2_groups, ARRAY_SIZE(x2000_i2c2_groups), },
2942         { "i2c3", x2000_i2c3_groups, ARRAY_SIZE(x2000_i2c3_groups), },
2943         { "i2c4", x2000_i2c4_groups, ARRAY_SIZE(x2000_i2c4_groups), },
2944         { "i2c5", x2000_i2c5_groups, ARRAY_SIZE(x2000_i2c5_groups), },
2945         { "i2s1", x2000_i2s1_groups, ARRAY_SIZE(x2000_i2s1_groups), },
2946         { "i2s2", x2000_i2s2_groups, ARRAY_SIZE(x2000_i2s2_groups), },
2947         { "i2s3", x2000_i2s3_groups, ARRAY_SIZE(x2000_i2s3_groups), },
2948         { "dmic", x2000_dmic_groups, ARRAY_SIZE(x2000_dmic_groups), },
2949         { "cim", x2000_cim_groups, ARRAY_SIZE(x2000_cim_groups), },
2950         { "lcd", x2000_lcd_groups, ARRAY_SIZE(x2000_lcd_groups), },
2951         { "pwm0", x2000_pwm0_groups, ARRAY_SIZE(x2000_pwm0_groups), },
2952         { "pwm1", x2000_pwm1_groups, ARRAY_SIZE(x2000_pwm1_groups), },
2953         { "pwm2", x2000_pwm2_groups, ARRAY_SIZE(x2000_pwm2_groups), },
2954         { "pwm3", x2000_pwm3_groups, ARRAY_SIZE(x2000_pwm3_groups), },
2955         { "pwm4", x2000_pwm4_groups, ARRAY_SIZE(x2000_pwm4_groups), },
2956         { "pwm5", x2000_pwm5_groups, ARRAY_SIZE(x2000_pwm5_groups), },
2957         { "pwm6", x2000_pwm6_groups, ARRAY_SIZE(x2000_pwm6_groups), },
2958         { "pwm7", x2000_pwm7_groups, ARRAY_SIZE(x2000_pwm7_groups), },
2959         { "pwm8", x2000_pwm8_groups, ARRAY_SIZE(x2000_pwm8_groups), },
2960         { "pwm9", x2000_pwm9_groups, ARRAY_SIZE(x2000_pwm9_groups), },
2961         { "pwm10", x2000_pwm10_groups, ARRAY_SIZE(x2000_pwm10_groups), },
2962         { "pwm11", x2000_pwm11_groups, ARRAY_SIZE(x2000_pwm11_groups), },
2963         { "pwm12", x2000_pwm12_groups, ARRAY_SIZE(x2000_pwm12_groups), },
2964         { "pwm13", x2000_pwm13_groups, ARRAY_SIZE(x2000_pwm13_groups), },
2965         { "pwm14", x2000_pwm14_groups, ARRAY_SIZE(x2000_pwm14_groups), },
2966         { "pwm15", x2000_pwm15_groups, ARRAY_SIZE(x2000_pwm15_groups), },
2967         { "mac0", x2000_mac0_groups, ARRAY_SIZE(x2000_mac0_groups), },
2968         { "mac1", x2000_mac1_groups, ARRAY_SIZE(x2000_mac1_groups), },
2969         { "otg", x2000_otg_groups, ARRAY_SIZE(x2000_otg_groups), },
2970 };
2971
2972 static const struct ingenic_chip_info x2000_chip_info = {
2973         .num_chips = 5,
2974         .reg_offset = 0x100,
2975         .version = ID_X2000,
2976         .groups = x2000_groups,
2977         .num_groups = ARRAY_SIZE(x2000_groups),
2978         .functions = x2000_functions,
2979         .num_functions = ARRAY_SIZE(x2000_functions),
2980         .pull_ups = x2000_pull_ups,
2981         .pull_downs = x2000_pull_downs,
2982 };
2983
2984 static const u32 x2100_pull_ups[5] = {
2985         0x0003ffff, 0xffffffff, 0x1ff0ffff, 0xc7fe3f3f, 0x0fbf003f,
2986 };
2987
2988 static const u32 x2100_pull_downs[5] = {
2989         0x0003ffff, 0xffffffff, 0x1ff0ffff, 0x00000000, 0x0fbf003f,
2990 };
2991
2992 static int x2100_mac_pins[] = {
2993         0x4b, 0x47, 0x46, 0x4a, 0x43, 0x42, 0x4c, 0x4d, 0x4f, 0x41,
2994 };
2995
2996 static const struct group_desc x2100_groups[] = {
2997         INGENIC_PIN_GROUP("uart0-data", x2000_uart0_data, 2),
2998         INGENIC_PIN_GROUP("uart0-hwflow", x2000_uart0_hwflow, 2),
2999         INGENIC_PIN_GROUP("uart1-data", x2000_uart1_data, 1),
3000         INGENIC_PIN_GROUP("uart1-hwflow", x2000_uart1_hwflow, 1),
3001         INGENIC_PIN_GROUP("uart2-data", x2000_uart2_data, 0),
3002         INGENIC_PIN_GROUP("uart3-data-c", x2000_uart3_data_c, 0),
3003         INGENIC_PIN_GROUP("uart3-data-d", x2000_uart3_data_d, 1),
3004         INGENIC_PIN_GROUP("uart3-hwflow-c", x2000_uart3_hwflow_c, 0),
3005         INGENIC_PIN_GROUP("uart3-hwflow-d", x2000_uart3_hwflow_d, 1),
3006         INGENIC_PIN_GROUP("uart4-data-a", x2000_uart4_data_a, 1),
3007         INGENIC_PIN_GROUP("uart4-data-c", x2000_uart4_data_c, 3),
3008         INGENIC_PIN_GROUP("uart4-hwflow-a", x2000_uart4_hwflow_a, 1),
3009         INGENIC_PIN_GROUP("uart4-hwflow-c", x2000_uart4_hwflow_c, 3),
3010         INGENIC_PIN_GROUP("uart5-data-a", x2000_uart5_data_a, 1),
3011         INGENIC_PIN_GROUP("uart5-data-c", x2000_uart5_data_c, 3),
3012         INGENIC_PIN_GROUP("uart6-data-a", x2000_uart6_data_a, 1),
3013         INGENIC_PIN_GROUP("uart6-data-c", x2000_uart6_data_c, 3),
3014         INGENIC_PIN_GROUP("uart7-data-a", x2000_uart7_data_a, 1),
3015         INGENIC_PIN_GROUP("uart7-data-c", x2000_uart7_data_c, 3),
3016         INGENIC_PIN_GROUP("uart8-data", x2000_uart8_data, 3),
3017         INGENIC_PIN_GROUP("uart9-data", x2000_uart9_data, 3),
3018         INGENIC_PIN_GROUP("sfc-data-if0-d", x2000_sfc_data_if0_d, 1),
3019         INGENIC_PIN_GROUP("sfc-data-if0-e", x2000_sfc_data_if0_e, 0),
3020         INGENIC_PIN_GROUP("sfc-data-if1", x2000_sfc_data_if1, 1),
3021         INGENIC_PIN_GROUP("sfc-clk-d", x2000_sfc_clk_d, 1),
3022         INGENIC_PIN_GROUP("sfc-clk-e", x2000_sfc_clk_e, 0),
3023         INGENIC_PIN_GROUP("sfc-ce-d", x2000_sfc_ce_d, 1),
3024         INGENIC_PIN_GROUP("sfc-ce-e", x2000_sfc_ce_e, 0),
3025         INGENIC_PIN_GROUP("ssi0-dt-b", x2000_ssi0_dt_b, 1),
3026         INGENIC_PIN_GROUP("ssi0-dt-d", x2000_ssi0_dt_d, 1),
3027         INGENIC_PIN_GROUP("ssi0-dr-b", x2000_ssi0_dr_b, 1),
3028         INGENIC_PIN_GROUP("ssi0-dr-d", x2000_ssi0_dr_d, 1),
3029         INGENIC_PIN_GROUP("ssi0-clk-b", x2000_ssi0_clk_b, 1),
3030         INGENIC_PIN_GROUP("ssi0-clk-d", x2000_ssi0_clk_d, 1),
3031         INGENIC_PIN_GROUP("ssi0-ce-b", x2000_ssi0_ce_b, 1),
3032         INGENIC_PIN_GROUP("ssi0-ce-d", x2000_ssi0_ce_d, 1),
3033         INGENIC_PIN_GROUP("ssi1-dt-c", x2000_ssi1_dt_c, 2),
3034         INGENIC_PIN_GROUP("ssi1-dt-d", x2000_ssi1_dt_d, 2),
3035         INGENIC_PIN_GROUP("ssi1-dt-e", x2000_ssi1_dt_e, 1),
3036         INGENIC_PIN_GROUP("ssi1-dr-c", x2000_ssi1_dr_c, 2),
3037         INGENIC_PIN_GROUP("ssi1-dr-d", x2000_ssi1_dr_d, 2),
3038         INGENIC_PIN_GROUP("ssi1-dr-e", x2000_ssi1_dr_e, 1),
3039         INGENIC_PIN_GROUP("ssi1-clk-c", x2000_ssi1_clk_c, 2),
3040         INGENIC_PIN_GROUP("ssi1-clk-d", x2000_ssi1_clk_d, 2),
3041         INGENIC_PIN_GROUP("ssi1-clk-e", x2000_ssi1_clk_e, 1),
3042         INGENIC_PIN_GROUP("ssi1-ce-c", x2000_ssi1_ce_c, 2),
3043         INGENIC_PIN_GROUP("ssi1-ce-d", x2000_ssi1_ce_d, 2),
3044         INGENIC_PIN_GROUP("ssi1-ce-e", x2000_ssi1_ce_e, 1),
3045         INGENIC_PIN_GROUP("mmc0-1bit", x2000_mmc0_1bit, 0),
3046         INGENIC_PIN_GROUP("mmc0-4bit", x2000_mmc0_4bit, 0),
3047         INGENIC_PIN_GROUP("mmc0-8bit", x2000_mmc0_8bit, 0),
3048         INGENIC_PIN_GROUP("mmc1-1bit", x2000_mmc1_1bit, 0),
3049         INGENIC_PIN_GROUP("mmc1-4bit", x2000_mmc1_4bit, 0),
3050         INGENIC_PIN_GROUP("mmc2-1bit", x2000_mmc2_1bit, 0),
3051         INGENIC_PIN_GROUP("mmc2-4bit", x2000_mmc2_4bit, 0),
3052         INGENIC_PIN_GROUP("emc-8bit-data", x2000_emc_8bit_data, 0),
3053         INGENIC_PIN_GROUP("emc-16bit-data", x2000_emc_16bit_data, 0),
3054         INGENIC_PIN_GROUP("emc-addr", x2000_emc_addr, 0),
3055         INGENIC_PIN_GROUP("emc-rd-we", x2000_emc_rd_we, 0),
3056         INGENIC_PIN_GROUP("emc-wait", x2000_emc_wait, 0),
3057         INGENIC_PIN_GROUP("emc-cs1", x2000_emc_cs1, 3),
3058         INGENIC_PIN_GROUP("emc-cs2", x2000_emc_cs2, 3),
3059         INGENIC_PIN_GROUP("i2c0-data", x2000_i2c0, 3),
3060         INGENIC_PIN_GROUP("i2c1-data-c", x2000_i2c1_c, 2),
3061         INGENIC_PIN_GROUP("i2c1-data-d", x2000_i2c1_d, 1),
3062         INGENIC_PIN_GROUP("i2c2-data-b", x2000_i2c2_b, 2),
3063         INGENIC_PIN_GROUP("i2c2-data-d", x2000_i2c2_d, 2),
3064         INGENIC_PIN_GROUP("i2c2-data-e", x2000_i2c2_e, 1),
3065         INGENIC_PIN_GROUP("i2c3-data-a", x2000_i2c3_a, 0),
3066         INGENIC_PIN_GROUP("i2c3-data-d", x2000_i2c3_d, 1),
3067         INGENIC_PIN_GROUP("i2c4-data-c", x2000_i2c4_c, 1),
3068         INGENIC_PIN_GROUP("i2c4-data-d", x2000_i2c4_d, 2),
3069         INGENIC_PIN_GROUP("i2c5-data-c", x2000_i2c5_c, 1),
3070         INGENIC_PIN_GROUP("i2c5-data-d", x2000_i2c5_d, 1),
3071         INGENIC_PIN_GROUP("i2s1-data-tx", x2000_i2s1_data_tx, 2),
3072         INGENIC_PIN_GROUP("i2s1-data-rx", x2000_i2s1_data_rx, 2),
3073         INGENIC_PIN_GROUP("i2s1-clk-tx", x2000_i2s1_clk_tx, 2),
3074         INGENIC_PIN_GROUP("i2s1-clk-rx", x2000_i2s1_clk_rx, 2),
3075         INGENIC_PIN_GROUP("i2s1-sysclk-tx", x2000_i2s1_sysclk_tx, 2),
3076         INGENIC_PIN_GROUP("i2s1-sysclk-rx", x2000_i2s1_sysclk_rx, 2),
3077         INGENIC_PIN_GROUP("i2s2-data-rx0", x2000_i2s2_data_rx0, 2),
3078         INGENIC_PIN_GROUP("i2s2-data-rx1", x2000_i2s2_data_rx1, 2),
3079         INGENIC_PIN_GROUP("i2s2-data-rx2", x2000_i2s2_data_rx2, 2),
3080         INGENIC_PIN_GROUP("i2s2-data-rx3", x2000_i2s2_data_rx3, 2),
3081         INGENIC_PIN_GROUP("i2s2-clk-rx", x2000_i2s2_clk_rx, 2),
3082         INGENIC_PIN_GROUP("i2s2-sysclk-rx", x2000_i2s2_sysclk_rx, 2),
3083         INGENIC_PIN_GROUP("i2s3-data-tx0", x2000_i2s3_data_tx0, 2),
3084         INGENIC_PIN_GROUP("i2s3-data-tx1", x2000_i2s3_data_tx1, 2),
3085         INGENIC_PIN_GROUP("i2s3-data-tx2", x2000_i2s3_data_tx2, 2),
3086         INGENIC_PIN_GROUP("i2s3-data-tx3", x2000_i2s3_data_tx3, 2),
3087         INGENIC_PIN_GROUP("i2s3-clk-tx", x2000_i2s3_clk_tx, 2),
3088         INGENIC_PIN_GROUP("i2s3-sysclk-tx", x2000_i2s3_sysclk_tx, 2),
3089         INGENIC_PIN_GROUP("dmic-if0", x2000_dmic_if0, 0),
3090         INGENIC_PIN_GROUP("dmic-if1", x2000_dmic_if1, 0),
3091         INGENIC_PIN_GROUP("dmic-if2", x2000_dmic_if2, 0),
3092         INGENIC_PIN_GROUP("dmic-if3", x2000_dmic_if3, 0),
3093         INGENIC_PIN_GROUP_FUNCS("cim-data-8bit", x2000_cim_8bit,
3094                                 x2000_cim_8bit_funcs),
3095         INGENIC_PIN_GROUP("cim-data-12bit", x2000_cim_12bit, 0),
3096         INGENIC_PIN_GROUP("lcd-tft-8bit", x2000_lcd_tft_8bit, 1),
3097         INGENIC_PIN_GROUP("lcd-tft-16bit", x2000_lcd_tft_16bit, 1),
3098         INGENIC_PIN_GROUP("lcd-tft-18bit", x2000_lcd_tft_18bit, 1),
3099         INGENIC_PIN_GROUP("lcd-tft-24bit", x2000_lcd_tft_24bit, 1),
3100         INGENIC_PIN_GROUP("lcd-slcd-8bit", x2000_lcd_slcd_8bit, 2),
3101         INGENIC_PIN_GROUP("lcd-slcd-16bit", x2000_lcd_tft_16bit, 2),
3102         INGENIC_PIN_GROUP("pwm0-c", x2000_pwm_pwm0_c, 0),
3103         INGENIC_PIN_GROUP("pwm0-d", x2000_pwm_pwm0_d, 2),
3104         INGENIC_PIN_GROUP("pwm1-c", x2000_pwm_pwm1_c, 0),
3105         INGENIC_PIN_GROUP("pwm1-d", x2000_pwm_pwm1_d, 2),
3106         INGENIC_PIN_GROUP("pwm2-c", x2000_pwm_pwm2_c, 0),
3107         INGENIC_PIN_GROUP("pwm2-e", x2000_pwm_pwm2_e, 1),
3108         INGENIC_PIN_GROUP("pwm3-c", x2000_pwm_pwm3_c, 0),
3109         INGENIC_PIN_GROUP("pwm3-e", x2000_pwm_pwm3_e, 1),
3110         INGENIC_PIN_GROUP("pwm4-c", x2000_pwm_pwm4_c, 0),
3111         INGENIC_PIN_GROUP("pwm4-e", x2000_pwm_pwm4_e, 1),
3112         INGENIC_PIN_GROUP("pwm5-c", x2000_pwm_pwm5_c, 0),
3113         INGENIC_PIN_GROUP("pwm5-e", x2000_pwm_pwm5_e, 1),
3114         INGENIC_PIN_GROUP("pwm6-c", x2000_pwm_pwm6_c, 0),
3115         INGENIC_PIN_GROUP("pwm6-e", x2000_pwm_pwm6_e, 1),
3116         INGENIC_PIN_GROUP("pwm7-c", x2000_pwm_pwm7_c, 0),
3117         INGENIC_PIN_GROUP("pwm7-e", x2000_pwm_pwm7_e, 1),
3118         INGENIC_PIN_GROUP("pwm8", x2000_pwm_pwm8, 0),
3119         INGENIC_PIN_GROUP("pwm9", x2000_pwm_pwm9, 0),
3120         INGENIC_PIN_GROUP("pwm10", x2000_pwm_pwm10, 0),
3121         INGENIC_PIN_GROUP("pwm11", x2000_pwm_pwm11, 0),
3122         INGENIC_PIN_GROUP("pwm12", x2000_pwm_pwm12, 0),
3123         INGENIC_PIN_GROUP("pwm13", x2000_pwm_pwm13, 0),
3124         INGENIC_PIN_GROUP("pwm14", x2000_pwm_pwm14, 0),
3125         INGENIC_PIN_GROUP("pwm15", x2000_pwm_pwm15, 0),
3126         INGENIC_PIN_GROUP("mac", x2100_mac, 1),
3127 };
3128
3129 static const char *x2100_mac_groups[] = { "mac", };
3130
3131 static const struct function_desc x2100_functions[] = {
3132         { "uart0", x2000_uart0_groups, ARRAY_SIZE(x2000_uart0_groups), },
3133         { "uart1", x2000_uart1_groups, ARRAY_SIZE(x2000_uart1_groups), },
3134         { "uart2", x2000_uart2_groups, ARRAY_SIZE(x2000_uart2_groups), },
3135         { "uart3", x2000_uart3_groups, ARRAY_SIZE(x2000_uart3_groups), },
3136         { "uart4", x2000_uart4_groups, ARRAY_SIZE(x2000_uart4_groups), },
3137         { "uart5", x2000_uart5_groups, ARRAY_SIZE(x2000_uart5_groups), },
3138         { "uart6", x2000_uart6_groups, ARRAY_SIZE(x2000_uart6_groups), },
3139         { "uart7", x2000_uart7_groups, ARRAY_SIZE(x2000_uart7_groups), },
3140         { "uart8", x2000_uart8_groups, ARRAY_SIZE(x2000_uart8_groups), },
3141         { "uart9", x2000_uart9_groups, ARRAY_SIZE(x2000_uart9_groups), },
3142         { "sfc", x2000_sfc_groups, ARRAY_SIZE(x2000_sfc_groups), },
3143         { "ssi0", x2000_ssi0_groups, ARRAY_SIZE(x2000_ssi0_groups), },
3144         { "ssi1", x2000_ssi1_groups, ARRAY_SIZE(x2000_ssi1_groups), },
3145         { "mmc0", x2000_mmc0_groups, ARRAY_SIZE(x2000_mmc0_groups), },
3146         { "mmc1", x2000_mmc1_groups, ARRAY_SIZE(x2000_mmc1_groups), },
3147         { "mmc2", x2000_mmc2_groups, ARRAY_SIZE(x2000_mmc2_groups), },
3148         { "emc", x2000_emc_groups, ARRAY_SIZE(x2000_emc_groups), },
3149         { "emc-cs1", x2000_cs1_groups, ARRAY_SIZE(x2000_cs1_groups), },
3150         { "emc-cs2", x2000_cs2_groups, ARRAY_SIZE(x2000_cs2_groups), },
3151         { "i2c0", x2000_i2c0_groups, ARRAY_SIZE(x2000_i2c0_groups), },
3152         { "i2c1", x2000_i2c1_groups, ARRAY_SIZE(x2000_i2c1_groups), },
3153         { "i2c2", x2000_i2c2_groups, ARRAY_SIZE(x2000_i2c2_groups), },
3154         { "i2c3", x2000_i2c3_groups, ARRAY_SIZE(x2000_i2c3_groups), },
3155         { "i2c4", x2000_i2c4_groups, ARRAY_SIZE(x2000_i2c4_groups), },
3156         { "i2c5", x2000_i2c5_groups, ARRAY_SIZE(x2000_i2c5_groups), },
3157         { "i2s1", x2000_i2s1_groups, ARRAY_SIZE(x2000_i2s1_groups), },
3158         { "i2s2", x2000_i2s2_groups, ARRAY_SIZE(x2000_i2s2_groups), },
3159         { "i2s3", x2000_i2s3_groups, ARRAY_SIZE(x2000_i2s3_groups), },
3160         { "dmic", x2000_dmic_groups, ARRAY_SIZE(x2000_dmic_groups), },
3161         { "cim", x2000_cim_groups, ARRAY_SIZE(x2000_cim_groups), },
3162         { "lcd", x2000_lcd_groups, ARRAY_SIZE(x2000_lcd_groups), },
3163         { "pwm0", x2000_pwm0_groups, ARRAY_SIZE(x2000_pwm0_groups), },
3164         { "pwm1", x2000_pwm1_groups, ARRAY_SIZE(x2000_pwm1_groups), },
3165         { "pwm2", x2000_pwm2_groups, ARRAY_SIZE(x2000_pwm2_groups), },
3166         { "pwm3", x2000_pwm3_groups, ARRAY_SIZE(x2000_pwm3_groups), },
3167         { "pwm4", x2000_pwm4_groups, ARRAY_SIZE(x2000_pwm4_groups), },
3168         { "pwm5", x2000_pwm5_groups, ARRAY_SIZE(x2000_pwm5_groups), },
3169         { "pwm6", x2000_pwm6_groups, ARRAY_SIZE(x2000_pwm6_groups), },
3170         { "pwm7", x2000_pwm7_groups, ARRAY_SIZE(x2000_pwm7_groups), },
3171         { "pwm8", x2000_pwm8_groups, ARRAY_SIZE(x2000_pwm8_groups), },
3172         { "pwm9", x2000_pwm9_groups, ARRAY_SIZE(x2000_pwm9_groups), },
3173         { "pwm10", x2000_pwm10_groups, ARRAY_SIZE(x2000_pwm10_groups), },
3174         { "pwm11", x2000_pwm11_groups, ARRAY_SIZE(x2000_pwm11_groups), },
3175         { "pwm12", x2000_pwm12_groups, ARRAY_SIZE(x2000_pwm12_groups), },
3176         { "pwm13", x2000_pwm13_groups, ARRAY_SIZE(x2000_pwm13_groups), },
3177         { "pwm14", x2000_pwm14_groups, ARRAY_SIZE(x2000_pwm14_groups), },
3178         { "pwm15", x2000_pwm15_groups, ARRAY_SIZE(x2000_pwm15_groups), },
3179         { "mac", x2100_mac_groups, ARRAY_SIZE(x2100_mac_groups), },
3180 };
3181
3182 static const struct ingenic_chip_info x2100_chip_info = {
3183         .num_chips = 5,
3184         .reg_offset = 0x100,
3185         .version = ID_X2100,
3186         .groups = x2100_groups,
3187         .num_groups = ARRAY_SIZE(x2100_groups),
3188         .functions = x2100_functions,
3189         .num_functions = ARRAY_SIZE(x2100_functions),
3190         .pull_ups = x2100_pull_ups,
3191         .pull_downs = x2100_pull_downs,
3192 };
3193
3194 static u32 ingenic_gpio_read_reg(struct ingenic_gpio_chip *jzgc, u8 reg)
3195 {
3196         unsigned int val;
3197
3198         regmap_read(jzgc->jzpc->map, jzgc->reg_base + reg, &val);
3199
3200         return (u32) val;
3201 }
3202
3203 static void ingenic_gpio_set_bit(struct ingenic_gpio_chip *jzgc,
3204                 u8 reg, u8 offset, bool set)
3205 {
3206         if (jzgc->jzpc->info->version == ID_JZ4730) {
3207                 regmap_update_bits(jzgc->jzpc->map, jzgc->reg_base + reg,
3208                                 BIT(offset), set ? BIT(offset) : 0);
3209                 return;
3210         }
3211
3212         if (set)
3213                 reg = REG_SET(reg);
3214         else
3215                 reg = REG_CLEAR(reg);
3216
3217         regmap_write(jzgc->jzpc->map, jzgc->reg_base + reg, BIT(offset));
3218 }
3219
3220 static void ingenic_gpio_shadow_set_bit(struct ingenic_gpio_chip *jzgc,
3221                 u8 reg, u8 offset, bool set)
3222 {
3223         if (set)
3224                 reg = REG_SET(reg);
3225         else
3226                 reg = REG_CLEAR(reg);
3227
3228         regmap_write(jzgc->jzpc->map, REG_PZ_BASE(
3229                         jzgc->jzpc->info->reg_offset) + reg, BIT(offset));
3230 }
3231
3232 static void ingenic_gpio_shadow_set_bit_load(struct ingenic_gpio_chip *jzgc)
3233 {
3234         regmap_write(jzgc->jzpc->map, REG_PZ_GID2LD(
3235                         jzgc->jzpc->info->reg_offset),
3236                         jzgc->gc.base / PINS_PER_GPIO_CHIP);
3237 }
3238
3239 static void jz4730_gpio_set_bits(struct ingenic_gpio_chip *jzgc,
3240                 u8 reg_upper, u8 reg_lower, u8 offset, u8 value)
3241 {
3242         /*
3243          * JZ4730 function and IRQ registers support two-bits-per-pin
3244          * definitions, split into two groups of 16.
3245          */
3246         u8 reg = offset < JZ4730_PINS_PER_PAIRED_REG ? reg_lower : reg_upper;
3247         unsigned int idx = offset % JZ4730_PINS_PER_PAIRED_REG;
3248         unsigned int mask = GENMASK(1, 0) << idx * 2;
3249
3250         regmap_update_bits(jzgc->jzpc->map, jzgc->reg_base + reg, mask, value << (idx * 2));
3251 }
3252
3253 static inline bool ingenic_gpio_get_value(struct ingenic_gpio_chip *jzgc,
3254                                           u8 offset)
3255 {
3256         unsigned int val = ingenic_gpio_read_reg(jzgc, GPIO_PIN);
3257
3258         return !!(val & BIT(offset));
3259 }
3260
3261 static void ingenic_gpio_set_value(struct ingenic_gpio_chip *jzgc,
3262                                    u8 offset, int value)
3263 {
3264         if (jzgc->jzpc->info->version >= ID_JZ4770)
3265                 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_PAT0, offset, !!value);
3266         else if (jzgc->jzpc->info->version >= ID_JZ4740)
3267                 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, offset, !!value);
3268         else
3269                 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_DATA, offset, !!value);
3270 }
3271
3272 static void irq_set_type(struct ingenic_gpio_chip *jzgc,
3273                 u8 offset, unsigned int type)
3274 {
3275         u8 reg1, reg2;
3276         bool val1, val2, val3;
3277
3278         switch (type) {
3279         case IRQ_TYPE_EDGE_BOTH:
3280                 val1 = val2 = false;
3281                 val3 = true;
3282                 break;
3283         case IRQ_TYPE_EDGE_RISING:
3284                 val1 = val2 = true;
3285                 val3 = false;
3286                 break;
3287         case IRQ_TYPE_EDGE_FALLING:
3288                 val1 = val3 = false;
3289                 val2 = true;
3290                 break;
3291         case IRQ_TYPE_LEVEL_HIGH:
3292                 val1 = true;
3293                 val2 = val3 = false;
3294                 break;
3295         case IRQ_TYPE_LEVEL_LOW:
3296         default:
3297                 val1 = val2 = val3 = false;
3298                 break;
3299         }
3300
3301         if (jzgc->jzpc->info->version >= ID_JZ4770) {
3302                 reg1 = JZ4770_GPIO_PAT1;
3303                 reg2 = JZ4770_GPIO_PAT0;
3304         } else if (jzgc->jzpc->info->version >= ID_JZ4740) {
3305                 reg1 = JZ4740_GPIO_TRIG;
3306                 reg2 = JZ4740_GPIO_DIR;
3307         } else {
3308                 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPDIR, offset, false);
3309                 jz4730_gpio_set_bits(jzgc, JZ4730_GPIO_GPIDUR,
3310                                 JZ4730_GPIO_GPIDLR, offset, (val2 << 1) | val1);
3311                 return;
3312         }
3313
3314         if (jzgc->jzpc->info->version >= ID_X2000) {
3315                 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1);
3316                 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2);
3317                 ingenic_gpio_shadow_set_bit_load(jzgc);
3318                 ingenic_gpio_set_bit(jzgc, X2000_GPIO_EDG, offset, val3);
3319         } else if (jzgc->jzpc->info->version >= ID_X1000) {
3320                 ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, val1);
3321                 ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, val2);
3322                 ingenic_gpio_shadow_set_bit_load(jzgc);
3323         } else {
3324                 ingenic_gpio_set_bit(jzgc, reg2, offset, val1);
3325                 ingenic_gpio_set_bit(jzgc, reg1, offset, val2);
3326         }
3327 }
3328
3329 static void ingenic_gpio_irq_mask(struct irq_data *irqd)
3330 {
3331         struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
3332         struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3333         int irq = irqd->hwirq;
3334
3335         if (jzgc->jzpc->info->version >= ID_JZ4740)
3336                 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irq, true);
3337         else
3338                 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIMR, irq, true);
3339 }
3340
3341 static void ingenic_gpio_irq_unmask(struct irq_data *irqd)
3342 {
3343         struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
3344         struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3345         int irq = irqd->hwirq;
3346
3347         if (jzgc->jzpc->info->version >= ID_JZ4740)
3348                 ingenic_gpio_set_bit(jzgc, GPIO_MSK, irq, false);
3349         else
3350                 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIMR, irq, false);
3351 }
3352
3353 static void ingenic_gpio_irq_enable(struct irq_data *irqd)
3354 {
3355         struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
3356         struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3357         int irq = irqd->hwirq;
3358
3359         if (jzgc->jzpc->info->version >= ID_JZ4770)
3360                 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, true);
3361         else if (jzgc->jzpc->info->version >= ID_JZ4740)
3362                 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, true);
3363         else
3364                 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIER, irq, true);
3365
3366         ingenic_gpio_irq_unmask(irqd);
3367 }
3368
3369 static void ingenic_gpio_irq_disable(struct irq_data *irqd)
3370 {
3371         struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
3372         struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3373         int irq = irqd->hwirq;
3374
3375         ingenic_gpio_irq_mask(irqd);
3376
3377         if (jzgc->jzpc->info->version >= ID_JZ4770)
3378                 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_INT, irq, false);
3379         else if (jzgc->jzpc->info->version >= ID_JZ4740)
3380                 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_SELECT, irq, false);
3381         else
3382                 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPIER, irq, false);
3383 }
3384
3385 static void ingenic_gpio_irq_ack(struct irq_data *irqd)
3386 {
3387         struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
3388         struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3389         int irq = irqd->hwirq;
3390         bool high;
3391
3392         if ((irqd_get_trigger_type(irqd) == IRQ_TYPE_EDGE_BOTH) &&
3393                 (jzgc->jzpc->info->version < ID_X2000)) {
3394                 /*
3395                  * Switch to an interrupt for the opposite edge to the one that
3396                  * triggered the interrupt being ACKed.
3397                  */
3398                 high = ingenic_gpio_get_value(jzgc, irq);
3399                 if (high)
3400                         irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_LOW);
3401                 else
3402                         irq_set_type(jzgc, irq, IRQ_TYPE_LEVEL_HIGH);
3403         }
3404
3405         if (jzgc->jzpc->info->version >= ID_JZ4770)
3406                 ingenic_gpio_set_bit(jzgc, JZ4770_GPIO_FLAG, irq, false);
3407         else if (jzgc->jzpc->info->version >= ID_JZ4740)
3408                 ingenic_gpio_set_bit(jzgc, JZ4740_GPIO_DATA, irq, true);
3409         else
3410                 ingenic_gpio_set_bit(jzgc, JZ4730_GPIO_GPFR, irq, false);
3411 }
3412
3413 static int ingenic_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
3414 {
3415         struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
3416         struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3417
3418         switch (type) {
3419         case IRQ_TYPE_EDGE_BOTH:
3420         case IRQ_TYPE_EDGE_RISING:
3421         case IRQ_TYPE_EDGE_FALLING:
3422                 irq_set_handler_locked(irqd, handle_edge_irq);
3423                 break;
3424         case IRQ_TYPE_LEVEL_HIGH:
3425         case IRQ_TYPE_LEVEL_LOW:
3426                 irq_set_handler_locked(irqd, handle_level_irq);
3427                 break;
3428         default:
3429                 irq_set_handler_locked(irqd, handle_bad_irq);
3430         }
3431
3432         if ((type == IRQ_TYPE_EDGE_BOTH) && (jzgc->jzpc->info->version < ID_X2000)) {
3433                 /*
3434                  * The hardware does not support interrupts on both edges. The
3435                  * best we can do is to set up a single-edge interrupt and then
3436                  * switch to the opposing edge when ACKing the interrupt.
3437                  */
3438                 bool high = ingenic_gpio_get_value(jzgc, irqd->hwirq);
3439
3440                 type = high ? IRQ_TYPE_LEVEL_LOW : IRQ_TYPE_LEVEL_HIGH;
3441         }
3442
3443         irq_set_type(jzgc, irqd->hwirq, type);
3444         return 0;
3445 }
3446
3447 static int ingenic_gpio_irq_set_wake(struct irq_data *irqd, unsigned int on)
3448 {
3449         struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd);
3450         struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3451
3452         return irq_set_irq_wake(jzgc->irq, on);
3453 }
3454
3455 static void ingenic_gpio_irq_handler(struct irq_desc *desc)
3456 {
3457         struct gpio_chip *gc = irq_desc_get_handler_data(desc);
3458         struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3459         struct irq_chip *irq_chip = irq_data_get_irq_chip(&desc->irq_data);
3460         unsigned long flag, i;
3461
3462         chained_irq_enter(irq_chip, desc);
3463
3464         if (jzgc->jzpc->info->version >= ID_JZ4770)
3465                 flag = ingenic_gpio_read_reg(jzgc, JZ4770_GPIO_FLAG);
3466         else if (jzgc->jzpc->info->version >= ID_JZ4740)
3467                 flag = ingenic_gpio_read_reg(jzgc, JZ4740_GPIO_FLAG);
3468         else
3469                 flag = ingenic_gpio_read_reg(jzgc, JZ4730_GPIO_GPFR);
3470
3471         for_each_set_bit(i, &flag, 32)
3472                 generic_handle_domain_irq(gc->irq.domain, i);
3473         chained_irq_exit(irq_chip, desc);
3474 }
3475
3476 static void ingenic_gpio_set(struct gpio_chip *gc,
3477                 unsigned int offset, int value)
3478 {
3479         struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3480
3481         ingenic_gpio_set_value(jzgc, offset, value);
3482 }
3483
3484 static int ingenic_gpio_get(struct gpio_chip *gc, unsigned int offset)
3485 {
3486         struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3487
3488         return (int) ingenic_gpio_get_value(jzgc, offset);
3489 }
3490
3491 static int ingenic_gpio_direction_input(struct gpio_chip *gc,
3492                 unsigned int offset)
3493 {
3494         return pinctrl_gpio_direction_input(gc->base + offset);
3495 }
3496
3497 static int ingenic_gpio_direction_output(struct gpio_chip *gc,
3498                 unsigned int offset, int value)
3499 {
3500         ingenic_gpio_set(gc, offset, value);
3501         return pinctrl_gpio_direction_output(gc->base + offset);
3502 }
3503
3504 static inline void ingenic_config_pin(struct ingenic_pinctrl *jzpc,
3505                 unsigned int pin, unsigned int reg, bool set)
3506 {
3507         unsigned int idx = pin % PINS_PER_GPIO_CHIP;
3508         unsigned int offt = pin / PINS_PER_GPIO_CHIP;
3509
3510         if (set) {
3511                 if (jzpc->info->version >= ID_JZ4740)
3512                         regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
3513                                         REG_SET(reg), BIT(idx));
3514                 else
3515                         regmap_set_bits(jzpc->map, offt * jzpc->info->reg_offset +
3516                                         reg, BIT(idx));
3517         } else {
3518                 if (jzpc->info->version >= ID_JZ4740)
3519                         regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
3520                                         REG_CLEAR(reg), BIT(idx));
3521                 else
3522                         regmap_clear_bits(jzpc->map, offt * jzpc->info->reg_offset +
3523                                         reg, BIT(idx));
3524         }
3525 }
3526
3527 static inline void ingenic_shadow_config_pin(struct ingenic_pinctrl *jzpc,
3528                 unsigned int pin, u8 reg, bool set)
3529 {
3530         unsigned int idx = pin % PINS_PER_GPIO_CHIP;
3531
3532         regmap_write(jzpc->map, REG_PZ_BASE(jzpc->info->reg_offset) +
3533                         (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx));
3534 }
3535
3536 static inline void ingenic_shadow_config_pin_load(struct ingenic_pinctrl *jzpc,
3537                 unsigned int pin)
3538 {
3539         regmap_write(jzpc->map, REG_PZ_GID2LD(jzpc->info->reg_offset),
3540                         pin / PINS_PER_GPIO_CHIP);
3541 }
3542
3543 static inline void jz4730_config_pin_function(struct ingenic_pinctrl *jzpc,
3544                 unsigned int pin, u8 reg_upper, u8 reg_lower, u8 value)
3545 {
3546         /*
3547          * JZ4730 function and IRQ registers support two-bits-per-pin
3548          * definitions, split into two groups of 16.
3549          */
3550         unsigned int idx = pin % JZ4730_PINS_PER_PAIRED_REG;
3551         unsigned int mask = GENMASK(1, 0) << idx * 2;
3552         unsigned int offt = pin / PINS_PER_GPIO_CHIP;
3553         u8 reg = (pin % PINS_PER_GPIO_CHIP) < JZ4730_PINS_PER_PAIRED_REG ? reg_lower : reg_upper;
3554
3555         regmap_update_bits(jzpc->map, offt * jzpc->info->reg_offset + reg,
3556                         mask, value << (idx * 2));
3557 }
3558
3559 static inline bool ingenic_get_pin_config(struct ingenic_pinctrl *jzpc,
3560                 unsigned int pin, unsigned int reg)
3561 {
3562         unsigned int idx = pin % PINS_PER_GPIO_CHIP;
3563         unsigned int offt = pin / PINS_PER_GPIO_CHIP;
3564         unsigned int val;
3565
3566         regmap_read(jzpc->map, offt * jzpc->info->reg_offset + reg, &val);
3567
3568         return val & BIT(idx);
3569 }
3570
3571 static int ingenic_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
3572 {
3573         struct ingenic_gpio_chip *jzgc = gpiochip_get_data(gc);
3574         struct ingenic_pinctrl *jzpc = jzgc->jzpc;
3575         unsigned int pin = gc->base + offset;
3576
3577         if (jzpc->info->version >= ID_JZ4770) {
3578                 if (ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_INT) ||
3579                     ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PAT1))
3580                         return GPIO_LINE_DIRECTION_IN;
3581                 return GPIO_LINE_DIRECTION_OUT;
3582         } else if (jzpc->info->version == ID_JZ4730) {
3583                 if (!ingenic_get_pin_config(jzpc, pin, JZ4730_GPIO_GPDIR))
3584                         return GPIO_LINE_DIRECTION_IN;
3585                 return GPIO_LINE_DIRECTION_OUT;
3586         }
3587
3588         if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_SELECT))
3589                 return GPIO_LINE_DIRECTION_IN;
3590
3591         if (ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_DIR))
3592                 return GPIO_LINE_DIRECTION_OUT;
3593
3594         return GPIO_LINE_DIRECTION_IN;
3595 }
3596
3597 static const struct pinctrl_ops ingenic_pctlops = {
3598         .get_groups_count = pinctrl_generic_get_group_count,
3599         .get_group_name = pinctrl_generic_get_group_name,
3600         .get_group_pins = pinctrl_generic_get_group_pins,
3601         .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
3602         .dt_free_map = pinconf_generic_dt_free_map,
3603 };
3604
3605 static int ingenic_gpio_irq_request(struct irq_data *data)
3606 {
3607         struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
3608         int ret;
3609
3610         ret = ingenic_gpio_direction_input(gpio_chip, data->hwirq);
3611         if (ret)
3612                 return ret;
3613
3614         return gpiochip_reqres_irq(gpio_chip, data->hwirq);
3615 }
3616
3617 static void ingenic_gpio_irq_release(struct irq_data *data)
3618 {
3619         struct gpio_chip *gpio_chip = irq_data_get_irq_chip_data(data);
3620
3621         return gpiochip_relres_irq(gpio_chip, data->hwirq);
3622 }
3623
3624 static int ingenic_pinmux_set_pin_fn(struct ingenic_pinctrl *jzpc,
3625                 int pin, int func)
3626 {
3627         unsigned int idx = pin % PINS_PER_GPIO_CHIP;
3628         unsigned int offt = pin / PINS_PER_GPIO_CHIP;
3629
3630         dev_dbg(jzpc->dev, "set pin P%c%u to function %u\n",
3631                         'A' + offt, idx, func);
3632
3633         if (jzpc->info->version >= ID_X1000) {
3634                 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
3635                 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, false);
3636                 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, func & 0x2);
3637                 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, func & 0x1);
3638                 ingenic_shadow_config_pin_load(jzpc, pin);
3639         } else if (jzpc->info->version >= ID_JZ4770) {
3640                 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
3641                 ingenic_config_pin(jzpc, pin, GPIO_MSK, false);
3642                 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, func & 0x2);
3643                 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, func & 0x1);
3644         } else if (jzpc->info->version >= ID_JZ4740) {
3645                 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, true);
3646                 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_TRIG, func & 0x2);
3647                 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, func & 0x1);
3648         } else {
3649                 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPIER, false);
3650                 jz4730_config_pin_function(jzpc, pin, JZ4730_GPIO_GPAUR, JZ4730_GPIO_GPALR, func);
3651         }
3652
3653         return 0;
3654 }
3655
3656 static int ingenic_pinmux_set_mux(struct pinctrl_dev *pctldev,
3657                 unsigned int selector, unsigned int group)
3658 {
3659         struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
3660         struct function_desc *func;
3661         struct group_desc *grp;
3662         unsigned int i;
3663         uintptr_t mode;
3664         u8 *pin_modes;
3665
3666         func = pinmux_generic_get_function(pctldev, selector);
3667         if (!func)
3668                 return -EINVAL;
3669
3670         grp = pinctrl_generic_get_group(pctldev, group);
3671         if (!grp)
3672                 return -EINVAL;
3673
3674         dev_dbg(pctldev->dev, "enable function %s group %s\n",
3675                 func->name, grp->name);
3676
3677         mode = (uintptr_t)grp->data;
3678         if (mode <= 3) {
3679                 for (i = 0; i < grp->num_pins; i++)
3680                         ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], mode);
3681         } else {
3682                 pin_modes = grp->data;
3683
3684                 for (i = 0; i < grp->num_pins; i++)
3685                         ingenic_pinmux_set_pin_fn(jzpc, grp->pins[i], pin_modes[i]);
3686         }
3687
3688         return 0;
3689 }
3690
3691 static int ingenic_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
3692                 struct pinctrl_gpio_range *range,
3693                 unsigned int pin, bool input)
3694 {
3695         struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
3696         unsigned int idx = pin % PINS_PER_GPIO_CHIP;
3697         unsigned int offt = pin / PINS_PER_GPIO_CHIP;
3698
3699         dev_dbg(pctldev->dev, "set pin P%c%u to %sput\n",
3700                         'A' + offt, idx, input ? "in" : "out");
3701
3702         if (jzpc->info->version >= ID_X1000) {
3703                 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
3704                 ingenic_shadow_config_pin(jzpc, pin, GPIO_MSK, true);
3705                 ingenic_shadow_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, input);
3706                 ingenic_shadow_config_pin_load(jzpc, pin);
3707         } else if (jzpc->info->version >= ID_JZ4770) {
3708                 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_INT, false);
3709                 ingenic_config_pin(jzpc, pin, GPIO_MSK, true);
3710                 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT1, input);
3711         } else if (jzpc->info->version >= ID_JZ4740) {
3712                 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_SELECT, false);
3713                 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DIR, !input);
3714                 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_FUNC, false);
3715         } else {
3716                 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPIER, false);
3717                 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPDIR, !input);
3718                 jz4730_config_pin_function(jzpc, pin, JZ4730_GPIO_GPAUR, JZ4730_GPIO_GPALR, 0);
3719         }
3720
3721         return 0;
3722 }
3723
3724 static const struct pinmux_ops ingenic_pmxops = {
3725         .get_functions_count = pinmux_generic_get_function_count,
3726         .get_function_name = pinmux_generic_get_function_name,
3727         .get_function_groups = pinmux_generic_get_function_groups,
3728         .set_mux = ingenic_pinmux_set_mux,
3729         .gpio_set_direction = ingenic_pinmux_gpio_set_direction,
3730 };
3731
3732 static int ingenic_pinconf_get(struct pinctrl_dev *pctldev,
3733                 unsigned int pin, unsigned long *config)
3734 {
3735         struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
3736         enum pin_config_param param = pinconf_to_config_param(*config);
3737         unsigned int idx = pin % PINS_PER_GPIO_CHIP;
3738         unsigned int offt = pin / PINS_PER_GPIO_CHIP;
3739         unsigned int arg = 1;
3740         unsigned int bias, reg;
3741         bool pull, pullup, pulldown;
3742
3743         if (jzpc->info->version >= ID_X2000) {
3744                 pullup = ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPU) &&
3745                                 !ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPD) &&
3746                                 (jzpc->info->pull_ups[offt] & BIT(idx));
3747                 pulldown = ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPD) &&
3748                                 !ingenic_get_pin_config(jzpc, pin, X2000_GPIO_PEPU) &&
3749                                 (jzpc->info->pull_downs[offt] & BIT(idx));
3750
3751         } else if (jzpc->info->version >= ID_X1830) {
3752                 unsigned int half = PINS_PER_GPIO_CHIP / 2;
3753                 unsigned int idxh = (pin % half) * 2;
3754
3755                 if (idx < half)
3756                         regmap_read(jzpc->map, offt * jzpc->info->reg_offset +
3757                                         X1830_GPIO_PEL, &bias);
3758                 else
3759                         regmap_read(jzpc->map, offt * jzpc->info->reg_offset +
3760                                         X1830_GPIO_PEH, &bias);
3761
3762                 bias = (bias >> idxh) & (GPIO_PULL_UP | GPIO_PULL_DOWN);
3763
3764                 pullup = (bias == GPIO_PULL_UP) && (jzpc->info->pull_ups[offt] & BIT(idx));
3765                 pulldown = (bias == GPIO_PULL_DOWN) && (jzpc->info->pull_downs[offt] & BIT(idx));
3766
3767         } else {
3768                 if (jzpc->info->version >= ID_JZ4770)
3769                         pull = !ingenic_get_pin_config(jzpc, pin, JZ4770_GPIO_PEN);
3770                 else if (jzpc->info->version >= ID_JZ4740)
3771                         pull = !ingenic_get_pin_config(jzpc, pin, JZ4740_GPIO_PULL_DIS);
3772                 else
3773                         pull = ingenic_get_pin_config(jzpc, pin, JZ4730_GPIO_GPPUR);
3774
3775                 pullup = pull && (jzpc->info->pull_ups[offt] & BIT(idx));
3776                 pulldown = pull && (jzpc->info->pull_downs[offt] & BIT(idx));
3777         }
3778
3779         switch (param) {
3780         case PIN_CONFIG_BIAS_DISABLE:
3781                 if (pullup || pulldown)
3782                         return -EINVAL;
3783
3784                 break;
3785
3786         case PIN_CONFIG_BIAS_PULL_UP:
3787                 if (!pullup)
3788                         return -EINVAL;
3789
3790                 break;
3791
3792         case PIN_CONFIG_BIAS_PULL_DOWN:
3793                 if (!pulldown)
3794                         return -EINVAL;
3795
3796                 break;
3797
3798         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
3799                 if (jzpc->info->version >= ID_X2000)
3800                         reg = X2000_GPIO_SMT;
3801                 else if (jzpc->info->version >= ID_X1830)
3802                         reg = X1830_GPIO_SMT;
3803                 else
3804                         return -EINVAL;
3805
3806                 arg = !!ingenic_get_pin_config(jzpc, pin, reg);
3807                 break;
3808
3809         case PIN_CONFIG_SLEW_RATE:
3810                 if (jzpc->info->version >= ID_X2000)
3811                         reg = X2000_GPIO_SR;
3812                 else if (jzpc->info->version >= ID_X1830)
3813                         reg = X1830_GPIO_SR;
3814                 else
3815                         return -EINVAL;
3816
3817                 arg = !!ingenic_get_pin_config(jzpc, pin, reg);
3818                 break;
3819
3820         default:
3821                 return -ENOTSUPP;
3822         }
3823
3824         *config = pinconf_to_config_packed(param, arg);
3825         return 0;
3826 }
3827
3828 static void ingenic_set_bias(struct ingenic_pinctrl *jzpc,
3829                 unsigned int pin, unsigned int bias)
3830 {
3831         if (jzpc->info->version >= ID_X2000) {
3832                 switch (bias) {
3833                 case GPIO_PULL_UP:
3834                         ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, false);
3835                         ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, true);
3836                         break;
3837
3838                 case GPIO_PULL_DOWN:
3839                         ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, false);
3840                         ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, true);
3841                         break;
3842
3843                 case GPIO_PULL_DIS:
3844                 default:
3845                         ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPU, false);
3846                         ingenic_config_pin(jzpc, pin, X2000_GPIO_PEPD, false);
3847                 }
3848
3849         } else if (jzpc->info->version >= ID_X1830) {
3850                 unsigned int idx = pin % PINS_PER_GPIO_CHIP;
3851                 unsigned int half = PINS_PER_GPIO_CHIP / 2;
3852                 unsigned int idxh = (pin % half) * 2;
3853                 unsigned int offt = pin / PINS_PER_GPIO_CHIP;
3854
3855                 if (idx < half) {
3856                         regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
3857                                         REG_CLEAR(X1830_GPIO_PEL), 3 << idxh);
3858                         regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
3859                                         REG_SET(X1830_GPIO_PEL), bias << idxh);
3860                 } else {
3861                         regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
3862                                         REG_CLEAR(X1830_GPIO_PEH), 3 << idxh);
3863                         regmap_write(jzpc->map, offt * jzpc->info->reg_offset +
3864                                         REG_SET(X1830_GPIO_PEH), bias << idxh);
3865                 }
3866
3867         } else if (jzpc->info->version >= ID_JZ4770) {
3868                 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PEN, !bias);
3869         } else if (jzpc->info->version >= ID_JZ4740) {
3870                 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_PULL_DIS, !bias);
3871         } else {
3872                 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_GPPUR, bias);
3873         }
3874 }
3875
3876 static void ingenic_set_schmitt_trigger(struct ingenic_pinctrl *jzpc,
3877                 unsigned int pin, bool enable)
3878 {
3879         if (jzpc->info->version >= ID_X2000)
3880                 ingenic_config_pin(jzpc, pin, X2000_GPIO_SMT, enable);
3881         else
3882                 ingenic_config_pin(jzpc, pin, X1830_GPIO_SMT, enable);
3883 }
3884
3885 static void ingenic_set_output_level(struct ingenic_pinctrl *jzpc,
3886                                      unsigned int pin, bool high)
3887 {
3888         if (jzpc->info->version >= ID_JZ4770)
3889                 ingenic_config_pin(jzpc, pin, JZ4770_GPIO_PAT0, high);
3890         else if (jzpc->info->version >= ID_JZ4740)
3891                 ingenic_config_pin(jzpc, pin, JZ4740_GPIO_DATA, high);
3892         else
3893                 ingenic_config_pin(jzpc, pin, JZ4730_GPIO_DATA, high);
3894 }
3895
3896 static void ingenic_set_slew_rate(struct ingenic_pinctrl *jzpc,
3897                 unsigned int pin, unsigned int slew)
3898 {
3899         if (jzpc->info->version >= ID_X2000)
3900                 ingenic_config_pin(jzpc, pin, X2000_GPIO_SR, slew);
3901         else
3902                 ingenic_config_pin(jzpc, pin, X1830_GPIO_SR, slew);
3903 }
3904
3905 static int ingenic_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
3906                 unsigned long *configs, unsigned int num_configs)
3907 {
3908         struct ingenic_pinctrl *jzpc = pinctrl_dev_get_drvdata(pctldev);
3909         unsigned int idx = pin % PINS_PER_GPIO_CHIP;
3910         unsigned int offt = pin / PINS_PER_GPIO_CHIP;
3911         unsigned int cfg, arg;
3912         int ret;
3913
3914         for (cfg = 0; cfg < num_configs; cfg++) {
3915                 switch (pinconf_to_config_param(configs[cfg])) {
3916                 case PIN_CONFIG_BIAS_DISABLE:
3917                 case PIN_CONFIG_BIAS_PULL_UP:
3918                 case PIN_CONFIG_BIAS_PULL_DOWN:
3919                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
3920                 case PIN_CONFIG_OUTPUT:
3921                 case PIN_CONFIG_SLEW_RATE:
3922                         continue;
3923                 default:
3924                         return -ENOTSUPP;
3925                 }
3926         }
3927
3928         for (cfg = 0; cfg < num_configs; cfg++) {
3929                 arg = pinconf_to_config_argument(configs[cfg]);
3930
3931                 switch (pinconf_to_config_param(configs[cfg])) {
3932                 case PIN_CONFIG_BIAS_DISABLE:
3933                         dev_dbg(jzpc->dev, "disable pull-over for pin P%c%u\n",
3934                                         'A' + offt, idx);
3935                         ingenic_set_bias(jzpc, pin, GPIO_PULL_DIS);
3936                         break;
3937
3938                 case PIN_CONFIG_BIAS_PULL_UP:
3939                         if (!(jzpc->info->pull_ups[offt] & BIT(idx)))
3940                                 return -EINVAL;
3941                         dev_dbg(jzpc->dev, "set pull-up for pin P%c%u\n",
3942                                         'A' + offt, idx);
3943                         ingenic_set_bias(jzpc, pin, GPIO_PULL_UP);
3944                         break;
3945
3946                 case PIN_CONFIG_BIAS_PULL_DOWN:
3947                         if (!(jzpc->info->pull_downs[offt] & BIT(idx)))
3948                                 return -EINVAL;
3949                         dev_dbg(jzpc->dev, "set pull-down for pin P%c%u\n",
3950                                         'A' + offt, idx);
3951                         ingenic_set_bias(jzpc, pin, GPIO_PULL_DOWN);
3952                         break;
3953
3954                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
3955                         if (jzpc->info->version < ID_X1830)
3956                                 return -EINVAL;
3957
3958                         ingenic_set_schmitt_trigger(jzpc, pin, arg);
3959                         break;
3960
3961                 case PIN_CONFIG_OUTPUT:
3962                         ret = pinctrl_gpio_direction_output(pin);
3963                         if (ret)
3964                                 return ret;
3965
3966                         ingenic_set_output_level(jzpc, pin, arg);
3967                         break;
3968
3969                 case PIN_CONFIG_SLEW_RATE:
3970                         if (jzpc->info->version < ID_X1830)
3971                                 return -EINVAL;
3972
3973                         ingenic_set_slew_rate(jzpc, pin, arg);
3974                         break;
3975
3976                 default:
3977                         /* unreachable */
3978                         break;
3979                 }
3980         }
3981
3982         return 0;
3983 }
3984
3985 static int ingenic_pinconf_group_get(struct pinctrl_dev *pctldev,
3986                 unsigned int group, unsigned long *config)
3987 {
3988         const unsigned int *pins;
3989         unsigned int i, npins, old = 0;
3990         int ret;
3991
3992         ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
3993         if (ret)
3994                 return ret;
3995
3996         for (i = 0; i < npins; i++) {
3997                 if (ingenic_pinconf_get(pctldev, pins[i], config))
3998                         return -ENOTSUPP;
3999
4000                 /* configs do not match between two pins */
4001                 if (i && (old != *config))
4002                         return -ENOTSUPP;
4003
4004                 old = *config;
4005         }
4006
4007         return 0;
4008 }
4009
4010 static int ingenic_pinconf_group_set(struct pinctrl_dev *pctldev,
4011                 unsigned int group, unsigned long *configs,
4012                 unsigned int num_configs)
4013 {
4014         const unsigned int *pins;
4015         unsigned int i, npins;
4016         int ret;
4017
4018         ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
4019         if (ret)
4020                 return ret;
4021
4022         for (i = 0; i < npins; i++) {
4023                 ret = ingenic_pinconf_set(pctldev,
4024                                 pins[i], configs, num_configs);
4025                 if (ret)
4026                         return ret;
4027         }
4028
4029         return 0;
4030 }
4031
4032 static const struct pinconf_ops ingenic_confops = {
4033         .is_generic = true,
4034         .pin_config_get = ingenic_pinconf_get,
4035         .pin_config_set = ingenic_pinconf_set,
4036         .pin_config_group_get = ingenic_pinconf_group_get,
4037         .pin_config_group_set = ingenic_pinconf_group_set,
4038 };
4039
4040 static const struct regmap_config ingenic_pinctrl_regmap_config = {
4041         .reg_bits = 32,
4042         .val_bits = 32,
4043         .reg_stride = 4,
4044 };
4045
4046 static const struct of_device_id ingenic_gpio_of_matches[] __initconst = {
4047         { .compatible = "ingenic,jz4730-gpio" },
4048         { .compatible = "ingenic,jz4740-gpio" },
4049         { .compatible = "ingenic,jz4725b-gpio" },
4050         { .compatible = "ingenic,jz4750-gpio" },
4051         { .compatible = "ingenic,jz4755-gpio" },
4052         { .compatible = "ingenic,jz4760-gpio" },
4053         { .compatible = "ingenic,jz4770-gpio" },
4054         { .compatible = "ingenic,jz4775-gpio" },
4055         { .compatible = "ingenic,jz4780-gpio" },
4056         { .compatible = "ingenic,x1000-gpio" },
4057         { .compatible = "ingenic,x1830-gpio" },
4058         { .compatible = "ingenic,x2000-gpio" },
4059         { .compatible = "ingenic,x2100-gpio" },
4060         {},
4061 };
4062
4063 static int __init ingenic_gpio_probe(struct ingenic_pinctrl *jzpc,
4064                                      struct device_node *node)
4065 {
4066         struct ingenic_gpio_chip *jzgc;
4067         struct device *dev = jzpc->dev;
4068         struct gpio_irq_chip *girq;
4069         unsigned int bank;
4070         int err;
4071
4072         err = of_property_read_u32(node, "reg", &bank);
4073         if (err) {
4074                 dev_err(dev, "Cannot read \"reg\" property: %i\n", err);
4075                 return err;
4076         }
4077
4078         jzgc = devm_kzalloc(dev, sizeof(*jzgc), GFP_KERNEL);
4079         if (!jzgc)
4080                 return -ENOMEM;
4081
4082         jzgc->jzpc = jzpc;
4083         jzgc->reg_base = bank * jzpc->info->reg_offset;
4084
4085         jzgc->gc.label = devm_kasprintf(dev, GFP_KERNEL, "GPIO%c", 'A' + bank);
4086         if (!jzgc->gc.label)
4087                 return -ENOMEM;
4088
4089         /* DO NOT EXPAND THIS: FOR BACKWARD GPIO NUMBERSPACE COMPATIBIBILITY
4090          * ONLY: WORK TO TRANSITION CONSUMERS TO USE THE GPIO DESCRIPTOR API IN
4091          * <linux/gpio/consumer.h> INSTEAD.
4092          */
4093         jzgc->gc.base = bank * 32;
4094
4095         jzgc->gc.ngpio = 32;
4096         jzgc->gc.parent = dev;
4097         jzgc->gc.of_node = node;
4098         jzgc->gc.owner = THIS_MODULE;
4099
4100         jzgc->gc.set = ingenic_gpio_set;
4101         jzgc->gc.get = ingenic_gpio_get;
4102         jzgc->gc.direction_input = ingenic_gpio_direction_input;
4103         jzgc->gc.direction_output = ingenic_gpio_direction_output;
4104         jzgc->gc.get_direction = ingenic_gpio_get_direction;
4105         jzgc->gc.request = gpiochip_generic_request;
4106         jzgc->gc.free = gpiochip_generic_free;
4107
4108         jzgc->irq = irq_of_parse_and_map(node, 0);
4109         if (!jzgc->irq)
4110                 return -EINVAL;
4111
4112         jzgc->irq_chip.name = jzgc->gc.label;
4113         jzgc->irq_chip.irq_enable = ingenic_gpio_irq_enable;
4114         jzgc->irq_chip.irq_disable = ingenic_gpio_irq_disable;
4115         jzgc->irq_chip.irq_unmask = ingenic_gpio_irq_unmask;
4116         jzgc->irq_chip.irq_mask = ingenic_gpio_irq_mask;
4117         jzgc->irq_chip.irq_ack = ingenic_gpio_irq_ack;
4118         jzgc->irq_chip.irq_set_type = ingenic_gpio_irq_set_type;
4119         jzgc->irq_chip.irq_set_wake = ingenic_gpio_irq_set_wake;
4120         jzgc->irq_chip.irq_request_resources = ingenic_gpio_irq_request;
4121         jzgc->irq_chip.irq_release_resources = ingenic_gpio_irq_release;
4122         jzgc->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND;
4123
4124         girq = &jzgc->gc.irq;
4125         girq->chip = &jzgc->irq_chip;
4126         girq->parent_handler = ingenic_gpio_irq_handler;
4127         girq->num_parents = 1;
4128         girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents),
4129                                      GFP_KERNEL);
4130         if (!girq->parents)
4131                 return -ENOMEM;
4132
4133         girq->parents[0] = jzgc->irq;
4134         girq->default_type = IRQ_TYPE_NONE;
4135         girq->handler = handle_level_irq;
4136
4137         err = devm_gpiochip_add_data(dev, &jzgc->gc, jzgc);
4138         if (err)
4139                 return err;
4140
4141         return 0;
4142 }
4143
4144 static int __init ingenic_pinctrl_probe(struct platform_device *pdev)
4145 {
4146         struct device *dev = &pdev->dev;
4147         struct ingenic_pinctrl *jzpc;
4148         struct pinctrl_desc *pctl_desc;
4149         void __iomem *base;
4150         const struct ingenic_chip_info *chip_info;
4151         struct device_node *node;
4152         struct regmap_config regmap_config;
4153         unsigned int i;
4154         int err;
4155
4156         chip_info = of_device_get_match_data(dev);
4157         if (!chip_info) {
4158                 dev_err(dev, "Unsupported SoC\n");
4159                 return -EINVAL;
4160         }
4161
4162         jzpc = devm_kzalloc(dev, sizeof(*jzpc), GFP_KERNEL);
4163         if (!jzpc)
4164                 return -ENOMEM;
4165
4166         base = devm_platform_ioremap_resource(pdev, 0);
4167         if (IS_ERR(base))
4168                 return PTR_ERR(base);
4169
4170         regmap_config = ingenic_pinctrl_regmap_config;
4171         regmap_config.max_register = chip_info->num_chips * chip_info->reg_offset;
4172
4173         jzpc->map = devm_regmap_init_mmio(dev, base, &regmap_config);
4174         if (IS_ERR(jzpc->map)) {
4175                 dev_err(dev, "Failed to create regmap\n");
4176                 return PTR_ERR(jzpc->map);
4177         }
4178
4179         jzpc->dev = dev;
4180         jzpc->info = chip_info;
4181
4182         pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL);
4183         if (!pctl_desc)
4184                 return -ENOMEM;
4185
4186         /* fill in pinctrl_desc structure */
4187         pctl_desc->name = dev_name(dev);
4188         pctl_desc->owner = THIS_MODULE;
4189         pctl_desc->pctlops = &ingenic_pctlops;
4190         pctl_desc->pmxops = &ingenic_pmxops;
4191         pctl_desc->confops = &ingenic_confops;
4192         pctl_desc->npins = chip_info->num_chips * PINS_PER_GPIO_CHIP;
4193         pctl_desc->pins = jzpc->pdesc = devm_kcalloc(&pdev->dev,
4194                         pctl_desc->npins, sizeof(*jzpc->pdesc), GFP_KERNEL);
4195         if (!jzpc->pdesc)
4196                 return -ENOMEM;
4197
4198         for (i = 0; i < pctl_desc->npins; i++) {
4199                 jzpc->pdesc[i].number = i;
4200                 jzpc->pdesc[i].name = kasprintf(GFP_KERNEL, "P%c%d",
4201                                                 'A' + (i / PINS_PER_GPIO_CHIP),
4202                                                 i % PINS_PER_GPIO_CHIP);
4203         }
4204
4205         jzpc->pctl = devm_pinctrl_register(dev, pctl_desc, jzpc);
4206         if (IS_ERR(jzpc->pctl)) {
4207                 dev_err(dev, "Failed to register pinctrl\n");
4208                 return PTR_ERR(jzpc->pctl);
4209         }
4210
4211         for (i = 0; i < chip_info->num_groups; i++) {
4212                 const struct group_desc *group = &chip_info->groups[i];
4213
4214                 err = pinctrl_generic_add_group(jzpc->pctl, group->name,
4215                                 group->pins, group->num_pins, group->data);
4216                 if (err < 0) {
4217                         dev_err(dev, "Failed to register group %s\n",
4218                                         group->name);
4219                         return err;
4220                 }
4221         }
4222
4223         for (i = 0; i < chip_info->num_functions; i++) {
4224                 const struct function_desc *func = &chip_info->functions[i];
4225
4226                 err = pinmux_generic_add_function(jzpc->pctl, func->name,
4227                                 func->group_names, func->num_group_names,
4228                                 func->data);
4229                 if (err < 0) {
4230                         dev_err(dev, "Failed to register function %s\n",
4231                                         func->name);
4232                         return err;
4233                 }
4234         }
4235
4236         dev_set_drvdata(dev, jzpc->map);
4237
4238         for_each_child_of_node(dev->of_node, node) {
4239                 if (of_match_node(ingenic_gpio_of_matches, node)) {
4240                         err = ingenic_gpio_probe(jzpc, node);
4241                         if (err) {
4242                                 of_node_put(node);
4243                                 return err;
4244                         }
4245                 }
4246         }
4247
4248         return 0;
4249 }
4250
4251 #define IF_ENABLED(cfg, ptr)    PTR_IF(IS_ENABLED(cfg), (ptr))
4252
4253 static const struct of_device_id ingenic_pinctrl_of_matches[] = {
4254         {
4255                 .compatible = "ingenic,jz4730-pinctrl",
4256                 .data = IF_ENABLED(CONFIG_MACH_JZ4730, &jz4730_chip_info)
4257         },
4258         {
4259                 .compatible = "ingenic,jz4740-pinctrl",
4260                 .data = IF_ENABLED(CONFIG_MACH_JZ4740, &jz4740_chip_info)
4261         },
4262         {
4263                 .compatible = "ingenic,jz4725b-pinctrl",
4264                 .data = IF_ENABLED(CONFIG_MACH_JZ4725B, &jz4725b_chip_info)
4265         },
4266         {
4267                 .compatible = "ingenic,jz4750-pinctrl",
4268                 .data = IF_ENABLED(CONFIG_MACH_JZ4750, &jz4750_chip_info)
4269         },
4270         {
4271                 .compatible = "ingenic,jz4755-pinctrl",
4272                 .data = IF_ENABLED(CONFIG_MACH_JZ4755, &jz4755_chip_info)
4273         },
4274         {
4275                 .compatible = "ingenic,jz4760-pinctrl",
4276                 .data = IF_ENABLED(CONFIG_MACH_JZ4760, &jz4760_chip_info)
4277         },
4278         {
4279                 .compatible = "ingenic,jz4760b-pinctrl",
4280                 .data = IF_ENABLED(CONFIG_MACH_JZ4760, &jz4760_chip_info)
4281         },
4282         {
4283                 .compatible = "ingenic,jz4770-pinctrl",
4284                 .data = IF_ENABLED(CONFIG_MACH_JZ4770, &jz4770_chip_info)
4285         },
4286         {
4287                 .compatible = "ingenic,jz4775-pinctrl",
4288                 .data = IF_ENABLED(CONFIG_MACH_JZ4775, &jz4775_chip_info)
4289         },
4290         {
4291                 .compatible = "ingenic,jz4780-pinctrl",
4292                 .data = IF_ENABLED(CONFIG_MACH_JZ4780, &jz4780_chip_info)
4293         },
4294         {
4295                 .compatible = "ingenic,x1000-pinctrl",
4296                 .data = IF_ENABLED(CONFIG_MACH_X1000, &x1000_chip_info)
4297         },
4298         {
4299                 .compatible = "ingenic,x1000e-pinctrl",
4300                 .data = IF_ENABLED(CONFIG_MACH_X1000, &x1000_chip_info)
4301         },
4302         {
4303                 .compatible = "ingenic,x1500-pinctrl",
4304                 .data = IF_ENABLED(CONFIG_MACH_X1500, &x1500_chip_info)
4305         },
4306         {
4307                 .compatible = "ingenic,x1830-pinctrl",
4308                 .data = IF_ENABLED(CONFIG_MACH_X1830, &x1830_chip_info)
4309         },
4310         {
4311                 .compatible = "ingenic,x2000-pinctrl",
4312                 .data = IF_ENABLED(CONFIG_MACH_X2000, &x2000_chip_info)
4313         },
4314         {
4315                 .compatible = "ingenic,x2000e-pinctrl",
4316                 .data = IF_ENABLED(CONFIG_MACH_X2000, &x2000_chip_info)
4317         },
4318         {
4319                 .compatible = "ingenic,x2100-pinctrl",
4320                 .data = IF_ENABLED(CONFIG_MACH_X2100, &x2100_chip_info)
4321         },
4322         { /* sentinel */ },
4323 };
4324
4325 static struct platform_driver ingenic_pinctrl_driver = {
4326         .driver = {
4327                 .name = "pinctrl-ingenic",
4328                 .of_match_table = ingenic_pinctrl_of_matches,
4329         },
4330 };
4331
4332 static int __init ingenic_pinctrl_drv_register(void)
4333 {
4334         return platform_driver_probe(&ingenic_pinctrl_driver,
4335                                      ingenic_pinctrl_probe);
4336 }
4337 subsys_initcall(ingenic_pinctrl_drv_register);