2 * Copyright (c) 2016, BayLibre, SAS. All rights reserved.
3 * Author: Neil Armstrong <narmstrong@baylibre.com>
5 * Copyright (c) 2010, Code Aurora Forum. All rights reserved.
7 * Driver for Semtech SX150X I2C GPIO Expanders
8 * The handling of the 4-bit chips (SX1501/SX1504/SX1507) is untested.
10 * Author: Gregory Bean <gbean@codeaurora.org>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 and
14 * only version 2 as published by the Free Software Foundation.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
22 #include <linux/regmap.h>
23 #include <linux/i2c.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/irq.h>
27 #include <linux/mutex.h>
28 #include <linux/slab.h>
30 #include <linux/of_device.h>
31 #include <linux/gpio/driver.h>
32 #include <linux/pinctrl/pinconf.h>
33 #include <linux/pinctrl/pinctrl.h>
34 #include <linux/pinctrl/pinmux.h>
35 #include <linux/pinctrl/pinconf-generic.h>
39 #include "pinctrl-utils.h"
41 /* The chip models of sx150x */
48 SX150X_789_REG_MISC_AUTOCLEAR_OFF
= 1 << 0,
49 SX150X_MAX_REGISTER
= 0xad,
50 SX150X_IRQ_TYPE_EDGE_RISING
= 0x1,
51 SX150X_IRQ_TYPE_EDGE_FALLING
= 0x2,
52 SX150X_789_RESET_KEY1
= 0x12,
53 SX150X_789_RESET_KEY2
= 0x34,
56 struct sx150x_123_pri
{
66 struct sx150x_456_pri
{
76 struct sx150x_789_pri
{
85 struct sx150x_device_data
{
96 struct sx150x_123_pri x123
;
97 struct sx150x_456_pri x456
;
98 struct sx150x_789_pri x789
;
100 const struct pinctrl_pin_desc
*pins
;
104 struct sx150x_pinctrl
{
106 struct i2c_client
*client
;
107 struct pinctrl_dev
*pctldev
;
108 struct pinctrl_desc pinctrl_desc
;
109 struct gpio_chip gpio
;
110 struct irq_chip irq_chip
;
111 struct regmap
*regmap
;
117 const struct sx150x_device_data
*data
;
120 static const struct pinctrl_pin_desc sx150x_4_pins
[] = {
121 PINCTRL_PIN(0, "gpio0"),
122 PINCTRL_PIN(1, "gpio1"),
123 PINCTRL_PIN(2, "gpio2"),
124 PINCTRL_PIN(3, "gpio3"),
125 PINCTRL_PIN(4, "oscio"),
128 static const struct pinctrl_pin_desc sx150x_8_pins
[] = {
129 PINCTRL_PIN(0, "gpio0"),
130 PINCTRL_PIN(1, "gpio1"),
131 PINCTRL_PIN(2, "gpio2"),
132 PINCTRL_PIN(3, "gpio3"),
133 PINCTRL_PIN(4, "gpio4"),
134 PINCTRL_PIN(5, "gpio5"),
135 PINCTRL_PIN(6, "gpio6"),
136 PINCTRL_PIN(7, "gpio7"),
137 PINCTRL_PIN(8, "oscio"),
140 static const struct pinctrl_pin_desc sx150x_16_pins
[] = {
141 PINCTRL_PIN(0, "gpio0"),
142 PINCTRL_PIN(1, "gpio1"),
143 PINCTRL_PIN(2, "gpio2"),
144 PINCTRL_PIN(3, "gpio3"),
145 PINCTRL_PIN(4, "gpio4"),
146 PINCTRL_PIN(5, "gpio5"),
147 PINCTRL_PIN(6, "gpio6"),
148 PINCTRL_PIN(7, "gpio7"),
149 PINCTRL_PIN(8, "gpio8"),
150 PINCTRL_PIN(9, "gpio9"),
151 PINCTRL_PIN(10, "gpio10"),
152 PINCTRL_PIN(11, "gpio11"),
153 PINCTRL_PIN(12, "gpio12"),
154 PINCTRL_PIN(13, "gpio13"),
155 PINCTRL_PIN(14, "gpio14"),
156 PINCTRL_PIN(15, "gpio15"),
157 PINCTRL_PIN(16, "oscio"),
160 static const struct sx150x_device_data sx1501q_device_data
= {
166 .reg_irq_mask
= 0x05,
170 .reg_pld_mode
= 0x10,
171 .reg_pld_table0
= 0x11,
172 .reg_pld_table2
= 0x13,
173 .reg_advanced
= 0xad,
176 .pins
= sx150x_4_pins
,
177 .npins
= 4, /* oscio not available */
180 static const struct sx150x_device_data sx1502q_device_data
= {
186 .reg_irq_mask
= 0x05,
190 .reg_pld_mode
= 0x10,
191 .reg_pld_table0
= 0x11,
192 .reg_pld_table1
= 0x12,
193 .reg_pld_table2
= 0x13,
194 .reg_pld_table3
= 0x14,
195 .reg_pld_table4
= 0x15,
196 .reg_advanced
= 0xad,
199 .pins
= sx150x_8_pins
,
200 .npins
= 8, /* oscio not available */
203 static const struct sx150x_device_data sx1503q_device_data
= {
209 .reg_irq_mask
= 0x08,
213 .reg_pld_mode
= 0x20,
214 .reg_pld_table0
= 0x22,
215 .reg_pld_table1
= 0x24,
216 .reg_pld_table2
= 0x26,
217 .reg_pld_table3
= 0x28,
218 .reg_pld_table4
= 0x2a,
219 .reg_advanced
= 0xad,
222 .pins
= sx150x_16_pins
,
223 .npins
= 16, /* oscio not available */
226 static const struct sx150x_device_data sx1504q_device_data
= {
232 .reg_irq_mask
= 0x05,
236 .reg_pld_mode
= 0x10,
237 .reg_pld_table0
= 0x11,
238 .reg_pld_table2
= 0x13,
241 .pins
= sx150x_4_pins
,
242 .npins
= 4, /* oscio not available */
245 static const struct sx150x_device_data sx1505q_device_data
= {
251 .reg_irq_mask
= 0x05,
255 .reg_pld_mode
= 0x10,
256 .reg_pld_table0
= 0x11,
257 .reg_pld_table1
= 0x12,
258 .reg_pld_table2
= 0x13,
259 .reg_pld_table3
= 0x14,
260 .reg_pld_table4
= 0x15,
263 .pins
= sx150x_8_pins
,
264 .npins
= 8, /* oscio not available */
267 static const struct sx150x_device_data sx1506q_device_data
= {
273 .reg_irq_mask
= 0x08,
277 .reg_pld_mode
= 0x20,
278 .reg_pld_table0
= 0x22,
279 .reg_pld_table1
= 0x24,
280 .reg_pld_table2
= 0x26,
281 .reg_pld_table3
= 0x28,
282 .reg_pld_table4
= 0x2a,
283 .reg_advanced
= 0xad,
286 .pins
= sx150x_16_pins
,
287 .npins
= 16, /* oscio not available */
290 static const struct sx150x_device_data sx1507q_device_data
= {
296 .reg_irq_mask
= 0x09,
301 .reg_polarity
= 0x06,
307 .pins
= sx150x_4_pins
,
308 .npins
= ARRAY_SIZE(sx150x_4_pins
),
311 static const struct sx150x_device_data sx1508q_device_data
= {
317 .reg_irq_mask
= 0x09,
322 .reg_polarity
= 0x06,
328 .pins
= sx150x_8_pins
,
329 .npins
= ARRAY_SIZE(sx150x_8_pins
),
332 static const struct sx150x_device_data sx1509q_device_data
= {
338 .reg_irq_mask
= 0x12,
343 .reg_polarity
= 0x0c,
349 .pins
= sx150x_16_pins
,
350 .npins
= ARRAY_SIZE(sx150x_16_pins
),
353 static int sx150x_pinctrl_get_groups_count(struct pinctrl_dev
*pctldev
)
358 static const char *sx150x_pinctrl_get_group_name(struct pinctrl_dev
*pctldev
,
364 static int sx150x_pinctrl_get_group_pins(struct pinctrl_dev
*pctldev
,
366 const unsigned int **pins
,
367 unsigned int *num_pins
)
372 static const struct pinctrl_ops sx150x_pinctrl_ops
= {
373 .get_groups_count
= sx150x_pinctrl_get_groups_count
,
374 .get_group_name
= sx150x_pinctrl_get_group_name
,
375 .get_group_pins
= sx150x_pinctrl_get_group_pins
,
377 .dt_node_to_map
= pinconf_generic_dt_node_to_map_pin
,
378 .dt_free_map
= pinctrl_utils_free_map
,
382 static bool sx150x_pin_is_oscio(struct sx150x_pinctrl
*pctl
, unsigned int pin
)
384 if (pin
>= pctl
->data
->npins
)
387 /* OSCIO pin is only present in 789 devices */
388 if (pctl
->data
->model
!= SX150X_789
)
391 return !strcmp(pctl
->data
->pins
[pin
].name
, "oscio");
394 static int sx150x_gpio_get_direction(struct gpio_chip
*chip
,
397 struct sx150x_pinctrl
*pctl
= gpiochip_get_data(chip
);
401 if (sx150x_pin_is_oscio(pctl
, offset
))
404 ret
= regmap_read(pctl
->regmap
, pctl
->data
->reg_dir
, &value
);
408 return !!(value
& BIT(offset
));
411 static int sx150x_gpio_get(struct gpio_chip
*chip
, unsigned int offset
)
413 struct sx150x_pinctrl
*pctl
= gpiochip_get_data(chip
);
417 if (sx150x_pin_is_oscio(pctl
, offset
))
420 ret
= regmap_read(pctl
->regmap
, pctl
->data
->reg_data
, &value
);
424 return !!(value
& BIT(offset
));
427 static int sx150x_gpio_set_single_ended(struct gpio_chip
*chip
,
429 enum single_ended_mode mode
)
431 struct sx150x_pinctrl
*pctl
= gpiochip_get_data(chip
);
435 case LINE_MODE_PUSH_PULL
:
436 if (pctl
->data
->model
!= SX150X_789
||
437 sx150x_pin_is_oscio(pctl
, offset
))
440 ret
= regmap_write_bits(pctl
->regmap
,
441 pctl
->data
->pri
.x789
.reg_drain
,
445 case LINE_MODE_OPEN_DRAIN
:
446 if (pctl
->data
->model
!= SX150X_789
||
447 sx150x_pin_is_oscio(pctl
, offset
))
450 ret
= regmap_write_bits(pctl
->regmap
,
451 pctl
->data
->pri
.x789
.reg_drain
,
452 BIT(offset
), BIT(offset
));
462 static int __sx150x_gpio_set(struct sx150x_pinctrl
*pctl
, unsigned int offset
,
465 return regmap_write_bits(pctl
->regmap
, pctl
->data
->reg_data
,
466 BIT(offset
), value
? BIT(offset
) : 0);
469 static int sx150x_gpio_oscio_set(struct sx150x_pinctrl
*pctl
,
472 return regmap_write(pctl
->regmap
,
473 pctl
->data
->pri
.x789
.reg_clock
,
474 (value
? 0x1f : 0x10));
477 static void sx150x_gpio_set(struct gpio_chip
*chip
, unsigned int offset
,
480 struct sx150x_pinctrl
*pctl
= gpiochip_get_data(chip
);
482 if (sx150x_pin_is_oscio(pctl
, offset
))
483 sx150x_gpio_oscio_set(pctl
, value
);
485 __sx150x_gpio_set(pctl
, offset
, value
);
489 static void sx150x_gpio_set_multiple(struct gpio_chip
*chip
,
493 struct sx150x_pinctrl
*pctl
= gpiochip_get_data(chip
);
495 regmap_write_bits(pctl
->regmap
, pctl
->data
->reg_data
, *mask
, *bits
);
498 static int sx150x_gpio_direction_input(struct gpio_chip
*chip
,
501 struct sx150x_pinctrl
*pctl
= gpiochip_get_data(chip
);
503 if (sx150x_pin_is_oscio(pctl
, offset
))
506 return regmap_write_bits(pctl
->regmap
,
508 BIT(offset
), BIT(offset
));
511 static int sx150x_gpio_direction_output(struct gpio_chip
*chip
,
512 unsigned int offset
, int value
)
514 struct sx150x_pinctrl
*pctl
= gpiochip_get_data(chip
);
517 if (sx150x_pin_is_oscio(pctl
, offset
))
518 return sx150x_gpio_oscio_set(pctl
, value
);
520 ret
= __sx150x_gpio_set(pctl
, offset
, value
);
524 return regmap_write_bits(pctl
->regmap
,
529 static void sx150x_irq_mask(struct irq_data
*d
)
531 struct sx150x_pinctrl
*pctl
=
532 gpiochip_get_data(irq_data_get_irq_chip_data(d
));
533 unsigned int n
= d
->hwirq
;
535 pctl
->irq
.masked
|= BIT(n
);
538 static void sx150x_irq_unmask(struct irq_data
*d
)
540 struct sx150x_pinctrl
*pctl
=
541 gpiochip_get_data(irq_data_get_irq_chip_data(d
));
542 unsigned int n
= d
->hwirq
;
544 pctl
->irq
.masked
&= ~BIT(n
);
547 static void sx150x_irq_set_sense(struct sx150x_pinctrl
*pctl
,
548 unsigned int line
, unsigned int sense
)
551 * Every interrupt line is represented by two bits shifted
552 * proportionally to the line number
554 const unsigned int n
= line
* 2;
555 const unsigned int mask
= ~((SX150X_IRQ_TYPE_EDGE_RISING
|
556 SX150X_IRQ_TYPE_EDGE_FALLING
) << n
);
558 pctl
->irq
.sense
&= mask
;
559 pctl
->irq
.sense
|= sense
<< n
;
562 static int sx150x_irq_set_type(struct irq_data
*d
, unsigned int flow_type
)
564 struct sx150x_pinctrl
*pctl
=
565 gpiochip_get_data(irq_data_get_irq_chip_data(d
));
566 unsigned int n
, val
= 0;
568 if (flow_type
& (IRQ_TYPE_LEVEL_HIGH
| IRQ_TYPE_LEVEL_LOW
))
573 if (flow_type
& IRQ_TYPE_EDGE_RISING
)
574 val
|= SX150X_IRQ_TYPE_EDGE_RISING
;
575 if (flow_type
& IRQ_TYPE_EDGE_FALLING
)
576 val
|= SX150X_IRQ_TYPE_EDGE_FALLING
;
578 sx150x_irq_set_sense(pctl
, n
, val
);
582 static irqreturn_t
sx150x_irq_thread_fn(int irq
, void *dev_id
)
584 struct sx150x_pinctrl
*pctl
= (struct sx150x_pinctrl
*)dev_id
;
585 unsigned long n
, status
;
589 err
= regmap_read(pctl
->regmap
, pctl
->data
->reg_irq_src
, &val
);
593 err
= regmap_write(pctl
->regmap
, pctl
->data
->reg_irq_src
, val
);
598 for_each_set_bit(n
, &status
, pctl
->data
->ngpios
)
599 handle_nested_irq(irq_find_mapping(pctl
->gpio
.irqdomain
, n
));
604 static void sx150x_irq_bus_lock(struct irq_data
*d
)
606 struct sx150x_pinctrl
*pctl
=
607 gpiochip_get_data(irq_data_get_irq_chip_data(d
));
609 mutex_lock(&pctl
->lock
);
612 static void sx150x_irq_bus_sync_unlock(struct irq_data
*d
)
614 struct sx150x_pinctrl
*pctl
=
615 gpiochip_get_data(irq_data_get_irq_chip_data(d
));
617 regmap_write(pctl
->regmap
, pctl
->data
->reg_irq_mask
, pctl
->irq
.masked
);
618 regmap_write(pctl
->regmap
, pctl
->data
->reg_sense
, pctl
->irq
.sense
);
619 mutex_unlock(&pctl
->lock
);
622 static int sx150x_pinconf_get(struct pinctrl_dev
*pctldev
, unsigned int pin
,
623 unsigned long *config
)
625 struct sx150x_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
626 unsigned int param
= pinconf_to_config_param(*config
);
631 if (sx150x_pin_is_oscio(pctl
, pin
)) {
633 case PIN_CONFIG_DRIVE_PUSH_PULL
:
634 case PIN_CONFIG_OUTPUT
:
635 ret
= regmap_read(pctl
->regmap
,
636 pctl
->data
->pri
.x789
.reg_clock
,
641 if (param
== PIN_CONFIG_DRIVE_PUSH_PULL
)
642 arg
= (data
& 0x1f) ? 1 : 0;
644 if ((data
& 0x1f) == 0x1f)
646 else if ((data
& 0x1f) == 0x10)
661 case PIN_CONFIG_BIAS_PULL_DOWN
:
662 ret
= regmap_read(pctl
->regmap
,
663 pctl
->data
->reg_pulldn
,
676 case PIN_CONFIG_BIAS_PULL_UP
:
677 ret
= regmap_read(pctl
->regmap
,
678 pctl
->data
->reg_pullup
,
691 case PIN_CONFIG_DRIVE_OPEN_DRAIN
:
692 if (pctl
->data
->model
!= SX150X_789
)
695 ret
= regmap_read(pctl
->regmap
,
696 pctl
->data
->pri
.x789
.reg_drain
,
709 case PIN_CONFIG_DRIVE_PUSH_PULL
:
710 if (pctl
->data
->model
!= SX150X_789
)
713 ret
= regmap_read(pctl
->regmap
,
714 pctl
->data
->pri
.x789
.reg_drain
,
728 case PIN_CONFIG_OUTPUT
:
729 ret
= sx150x_gpio_get_direction(&pctl
->gpio
, pin
);
736 ret
= sx150x_gpio_get(&pctl
->gpio
, pin
);
748 *config
= pinconf_to_config_packed(param
, arg
);
753 static int sx150x_pinconf_set(struct pinctrl_dev
*pctldev
, unsigned int pin
,
754 unsigned long *configs
, unsigned int num_configs
)
756 struct sx150x_pinctrl
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
757 enum pin_config_param param
;
762 for (i
= 0; i
< num_configs
; i
++) {
763 param
= pinconf_to_config_param(configs
[i
]);
764 arg
= pinconf_to_config_argument(configs
[i
]);
766 if (sx150x_pin_is_oscio(pctl
, pin
)) {
767 if (param
== PIN_CONFIG_OUTPUT
) {
768 ret
= sx150x_gpio_direction_output(&pctl
->gpio
,
779 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
:
780 case PIN_CONFIG_BIAS_DISABLE
:
781 ret
= regmap_write_bits(pctl
->regmap
,
782 pctl
->data
->reg_pulldn
,
787 ret
= regmap_write_bits(pctl
->regmap
,
788 pctl
->data
->reg_pullup
,
795 case PIN_CONFIG_BIAS_PULL_UP
:
796 ret
= regmap_write_bits(pctl
->regmap
,
797 pctl
->data
->reg_pullup
,
804 case PIN_CONFIG_BIAS_PULL_DOWN
:
805 ret
= regmap_write_bits(pctl
->regmap
,
806 pctl
->data
->reg_pulldn
,
813 case PIN_CONFIG_DRIVE_OPEN_DRAIN
:
814 ret
= sx150x_gpio_set_single_ended(&pctl
->gpio
,
815 pin
, LINE_MODE_OPEN_DRAIN
);
821 case PIN_CONFIG_DRIVE_PUSH_PULL
:
822 ret
= sx150x_gpio_set_single_ended(&pctl
->gpio
,
823 pin
, LINE_MODE_PUSH_PULL
);
829 case PIN_CONFIG_OUTPUT
:
830 ret
= sx150x_gpio_direction_output(&pctl
->gpio
,
840 } /* for each config */
845 static const struct pinconf_ops sx150x_pinconf_ops
= {
846 .pin_config_get
= sx150x_pinconf_get
,
847 .pin_config_set
= sx150x_pinconf_set
,
851 static const struct i2c_device_id sx150x_id
[] = {
852 {"sx1501q", (kernel_ulong_t
) &sx1501q_device_data
},
853 {"sx1502q", (kernel_ulong_t
) &sx1502q_device_data
},
854 {"sx1503q", (kernel_ulong_t
) &sx1503q_device_data
},
855 {"sx1504q", (kernel_ulong_t
) &sx1504q_device_data
},
856 {"sx1505q", (kernel_ulong_t
) &sx1505q_device_data
},
857 {"sx1506q", (kernel_ulong_t
) &sx1506q_device_data
},
858 {"sx1507q", (kernel_ulong_t
) &sx1507q_device_data
},
859 {"sx1508q", (kernel_ulong_t
) &sx1508q_device_data
},
860 {"sx1509q", (kernel_ulong_t
) &sx1509q_device_data
},
864 static const struct of_device_id sx150x_of_match
[] = {
865 { .compatible
= "semtech,sx1501q", .data
= &sx1501q_device_data
},
866 { .compatible
= "semtech,sx1502q", .data
= &sx1502q_device_data
},
867 { .compatible
= "semtech,sx1503q", .data
= &sx1503q_device_data
},
868 { .compatible
= "semtech,sx1504q", .data
= &sx1504q_device_data
},
869 { .compatible
= "semtech,sx1505q", .data
= &sx1505q_device_data
},
870 { .compatible
= "semtech,sx1506q", .data
= &sx1506q_device_data
},
871 { .compatible
= "semtech,sx1507q", .data
= &sx1507q_device_data
},
872 { .compatible
= "semtech,sx1508q", .data
= &sx1508q_device_data
},
873 { .compatible
= "semtech,sx1509q", .data
= &sx1509q_device_data
},
877 static int sx150x_reset(struct sx150x_pinctrl
*pctl
)
881 err
= i2c_smbus_write_byte_data(pctl
->client
,
882 pctl
->data
->pri
.x789
.reg_reset
,
883 SX150X_789_RESET_KEY1
);
887 err
= i2c_smbus_write_byte_data(pctl
->client
,
888 pctl
->data
->pri
.x789
.reg_reset
,
889 SX150X_789_RESET_KEY2
);
893 static int sx150x_init_misc(struct sx150x_pinctrl
*pctl
)
897 switch (pctl
->data
->model
) {
899 reg
= pctl
->data
->pri
.x789
.reg_misc
;
900 value
= SX150X_789_REG_MISC_AUTOCLEAR_OFF
;
903 reg
= pctl
->data
->pri
.x456
.reg_advanced
;
907 * Only SX1506 has RegAdvanced, SX1504/5 are expected
908 * to initialize this offset to zero
914 reg
= pctl
->data
->pri
.x123
.reg_advanced
;
918 WARN(1, "Unknown chip model %d\n", pctl
->data
->model
);
922 return regmap_write(pctl
->regmap
, reg
, value
);
925 static int sx150x_init_hw(struct sx150x_pinctrl
*pctl
)
928 [SX150X_789
] = pctl
->data
->pri
.x789
.reg_polarity
,
929 [SX150X_456
] = pctl
->data
->pri
.x456
.reg_pld_mode
,
930 [SX150X_123
] = pctl
->data
->pri
.x123
.reg_pld_mode
,
934 if (pctl
->data
->model
== SX150X_789
&&
935 of_property_read_bool(pctl
->dev
->of_node
, "semtech,probe-reset")) {
936 err
= sx150x_reset(pctl
);
941 err
= sx150x_init_misc(pctl
);
945 /* Set all pins to work in normal mode */
946 return regmap_write(pctl
->regmap
, reg
[pctl
->data
->model
], 0);
949 static int sx150x_regmap_reg_width(struct sx150x_pinctrl
*pctl
,
952 const struct sx150x_device_data
*data
= pctl
->data
;
954 if (reg
== data
->reg_sense
) {
956 * RegSense packs two bits of configuration per GPIO,
957 * so we'd need to read twice as many bits as there
958 * are GPIO in our chip
960 return 2 * data
->ngpios
;
961 } else if ((data
->model
== SX150X_789
&&
962 (reg
== data
->pri
.x789
.reg_misc
||
963 reg
== data
->pri
.x789
.reg_clock
||
964 reg
== data
->pri
.x789
.reg_reset
))
966 (data
->model
== SX150X_123
&&
967 reg
== data
->pri
.x123
.reg_advanced
)
969 (data
->model
== SX150X_456
&&
970 data
->pri
.x456
.reg_advanced
&&
971 reg
== data
->pri
.x456
.reg_advanced
)) {
978 static unsigned int sx150x_maybe_swizzle(struct sx150x_pinctrl
*pctl
,
979 unsigned int reg
, unsigned int val
)
982 const struct sx150x_device_data
*data
= pctl
->data
;
985 * Whereas SX1509 presents RegSense in a simple layout as such:
986 * reg [ f f e e d d c c ]
987 * reg + 1 [ b b a a 9 9 8 8 ]
988 * reg + 2 [ 7 7 6 6 5 5 4 4 ]
989 * reg + 3 [ 3 3 2 2 1 1 0 0 ]
991 * SX1503 and SX1506 deviate from that data layout, instead storing
992 * their contents as follows:
994 * reg [ f f e e d d c c ]
995 * reg + 1 [ 7 7 6 6 5 5 4 4 ]
996 * reg + 2 [ b b a a 9 9 8 8 ]
997 * reg + 3 [ 3 3 2 2 1 1 0 0 ]
999 * so, taking that into account, we swap two
1000 * inner bytes of a 4-byte result
1003 if (reg
== data
->reg_sense
&&
1004 data
->ngpios
== 16 &&
1005 (data
->model
== SX150X_123
||
1006 data
->model
== SX150X_456
)) {
1007 a
= val
& 0x00ff0000;
1008 b
= val
& 0x0000ff00;
1019 * In order to mask the differences between 16 and 8 bit expander
1020 * devices we set up a sligthly ficticious regmap that pretends to be
1021 * a set of 32-bit (to accomodate RegSenseLow/RegSenseHigh
1022 * pair/quartet) registers and transparently reconstructs those
1023 * registers via multiple I2C/SMBus reads
1025 * This way the rest of the driver code, interfacing with the chip via
1026 * regmap API, can work assuming that each GPIO pin is represented by
1027 * a group of bits at an offset proportional to GPIO number within a
1030 static int sx150x_regmap_reg_read(void *context
, unsigned int reg
,
1031 unsigned int *result
)
1034 struct sx150x_pinctrl
*pctl
= context
;
1035 struct i2c_client
*i2c
= pctl
->client
;
1036 const int width
= sx150x_regmap_reg_width(pctl
, reg
);
1037 unsigned int idx
, val
;
1040 * There are four potential cases covered by this function:
1042 * 1) 8-pin chip, single configuration bit register
1044 * This is trivial the code below just needs to read:
1045 * reg [ 7 6 5 4 3 2 1 0 ]
1047 * 2) 8-pin chip, double configuration bit register (RegSense)
1049 * The read will be done as follows:
1050 * reg [ 7 7 6 6 5 5 4 4 ]
1051 * reg + 1 [ 3 3 2 2 1 1 0 0 ]
1053 * 3) 16-pin chip, single configuration bit register
1055 * The read will be done as follows:
1056 * reg [ f e d c b a 9 8 ]
1057 * reg + 1 [ 7 6 5 4 3 2 1 0 ]
1059 * 4) 16-pin chip, double configuration bit register (RegSense)
1061 * The read will be done as follows:
1062 * reg [ f f e e d d c c ]
1063 * reg + 1 [ b b a a 9 9 8 8 ]
1064 * reg + 2 [ 7 7 6 6 5 5 4 4 ]
1065 * reg + 3 [ 3 3 2 2 1 1 0 0 ]
1068 for (n
= width
, val
= 0, idx
= reg
; n
> 0; n
-= 8, idx
++) {
1071 ret
= i2c_smbus_read_byte_data(i2c
, idx
);
1078 *result
= sx150x_maybe_swizzle(pctl
, reg
, val
);
1083 static int sx150x_regmap_reg_write(void *context
, unsigned int reg
,
1087 struct sx150x_pinctrl
*pctl
= context
;
1088 struct i2c_client
*i2c
= pctl
->client
;
1089 const int width
= sx150x_regmap_reg_width(pctl
, reg
);
1091 val
= sx150x_maybe_swizzle(pctl
, reg
, val
);
1093 n
= (width
- 1) & ~7;
1095 const u8 byte
= (val
>> n
) & 0xff;
1097 ret
= i2c_smbus_write_byte_data(i2c
, reg
, byte
);
1108 static bool sx150x_reg_volatile(struct device
*dev
, unsigned int reg
)
1110 struct sx150x_pinctrl
*pctl
= i2c_get_clientdata(to_i2c_client(dev
));
1112 return reg
== pctl
->data
->reg_irq_src
|| reg
== pctl
->data
->reg_data
;
1115 const struct regmap_config sx150x_regmap_config
= {
1119 .cache_type
= REGCACHE_RBTREE
,
1121 .reg_read
= sx150x_regmap_reg_read
,
1122 .reg_write
= sx150x_regmap_reg_write
,
1124 .max_register
= SX150X_MAX_REGISTER
,
1125 .volatile_reg
= sx150x_reg_volatile
,
1128 static int sx150x_probe(struct i2c_client
*client
,
1129 const struct i2c_device_id
*id
)
1131 static const u32 i2c_funcs
= I2C_FUNC_SMBUS_BYTE_DATA
|
1132 I2C_FUNC_SMBUS_WRITE_WORD_DATA
;
1133 struct device
*dev
= &client
->dev
;
1134 struct sx150x_pinctrl
*pctl
;
1137 if (!i2c_check_functionality(client
->adapter
, i2c_funcs
))
1140 pctl
= devm_kzalloc(dev
, sizeof(*pctl
), GFP_KERNEL
);
1144 i2c_set_clientdata(client
, pctl
);
1147 pctl
->client
= client
;
1150 pctl
->data
= of_device_get_match_data(dev
);
1152 pctl
->data
= (struct sx150x_device_data
*)id
->driver_data
;
1157 pctl
->regmap
= devm_regmap_init(dev
, NULL
, pctl
,
1158 &sx150x_regmap_config
);
1159 if (IS_ERR(pctl
->regmap
)) {
1160 ret
= PTR_ERR(pctl
->regmap
);
1161 dev_err(dev
, "Failed to allocate register map: %d\n",
1166 mutex_init(&pctl
->lock
);
1168 ret
= sx150x_init_hw(pctl
);
1172 /* Register GPIO controller */
1173 pctl
->gpio
.label
= devm_kstrdup(dev
, client
->name
, GFP_KERNEL
);
1174 pctl
->gpio
.base
= -1;
1175 pctl
->gpio
.ngpio
= pctl
->data
->npins
;
1176 pctl
->gpio
.get_direction
= sx150x_gpio_get_direction
;
1177 pctl
->gpio
.direction_input
= sx150x_gpio_direction_input
;
1178 pctl
->gpio
.direction_output
= sx150x_gpio_direction_output
;
1179 pctl
->gpio
.get
= sx150x_gpio_get
;
1180 pctl
->gpio
.set
= sx150x_gpio_set
;
1181 pctl
->gpio
.set_single_ended
= sx150x_gpio_set_single_ended
;
1182 pctl
->gpio
.parent
= dev
;
1183 #ifdef CONFIG_OF_GPIO
1184 pctl
->gpio
.of_node
= dev
->of_node
;
1186 pctl
->gpio
.can_sleep
= true;
1188 * Setting multiple pins is not safe when all pins are not
1189 * handled by the same regmap register. The oscio pin (present
1190 * on the SX150X_789 chips) lives in its own register, so
1191 * would require locking that is not in place at this time.
1193 if (pctl
->data
->model
!= SX150X_789
)
1194 pctl
->gpio
.set_multiple
= sx150x_gpio_set_multiple
;
1196 ret
= devm_gpiochip_add_data(dev
, &pctl
->gpio
, pctl
);
1200 /* Add Interrupt support if an irq is specified */
1201 if (client
->irq
> 0) {
1202 pctl
->irq_chip
.name
= devm_kstrdup(dev
, client
->name
,
1204 pctl
->irq_chip
.irq_mask
= sx150x_irq_mask
;
1205 pctl
->irq_chip
.irq_unmask
= sx150x_irq_unmask
;
1206 pctl
->irq_chip
.irq_set_type
= sx150x_irq_set_type
;
1207 pctl
->irq_chip
.irq_bus_lock
= sx150x_irq_bus_lock
;
1208 pctl
->irq_chip
.irq_bus_sync_unlock
= sx150x_irq_bus_sync_unlock
;
1210 pctl
->irq
.masked
= ~0;
1211 pctl
->irq
.sense
= 0;
1214 * Because sx150x_irq_threaded_fn invokes all of the
1215 * nested interrrupt handlers via handle_nested_irq,
1216 * any "handler" passed to gpiochip_irqchip_add()
1217 * below is going to be ignored, so the choice of the
1218 * function does not matter that much.
1220 * We set it to handle_bad_irq to avoid confusion,
1221 * plus it will be instantly noticeable if it is ever
1222 * called (should not happen)
1224 ret
= gpiochip_irqchip_add_nested(&pctl
->gpio
,
1226 handle_bad_irq
, IRQ_TYPE_NONE
);
1228 dev_err(dev
, "could not connect irqchip to gpiochip\n");
1232 ret
= devm_request_threaded_irq(dev
, client
->irq
, NULL
,
1233 sx150x_irq_thread_fn
,
1234 IRQF_ONESHOT
| IRQF_SHARED
|
1235 IRQF_TRIGGER_FALLING
,
1236 pctl
->irq_chip
.name
, pctl
);
1240 gpiochip_set_nested_irqchip(&pctl
->gpio
,
1246 pctl
->pinctrl_desc
.name
= "sx150x-pinctrl";
1247 pctl
->pinctrl_desc
.pctlops
= &sx150x_pinctrl_ops
;
1248 pctl
->pinctrl_desc
.confops
= &sx150x_pinconf_ops
;
1249 pctl
->pinctrl_desc
.pins
= pctl
->data
->pins
;
1250 pctl
->pinctrl_desc
.npins
= pctl
->data
->npins
;
1251 pctl
->pinctrl_desc
.owner
= THIS_MODULE
;
1253 pctl
->pctldev
= pinctrl_register(&pctl
->pinctrl_desc
, dev
, pctl
);
1254 if (IS_ERR(pctl
->pctldev
)) {
1255 dev_err(dev
, "Failed to register pinctrl device\n");
1256 return PTR_ERR(pctl
->pctldev
);
1262 static struct i2c_driver sx150x_driver
= {
1264 .name
= "sx150x-pinctrl",
1265 .of_match_table
= of_match_ptr(sx150x_of_match
),
1267 .probe
= sx150x_probe
,
1268 .id_table
= sx150x_id
,
1271 static int __init
sx150x_init(void)
1273 return i2c_add_driver(&sx150x_driver
);
1275 subsys_initcall(sx150x_init
);