2 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 * Copyright (c) 2012 Linaro Ltd
7 * http://www.linaro.org
9 * Author: Thomas Abraham <thomas.ab@samsung.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
17 #ifndef __PINCTRL_SAMSUNG_H
18 #define __PINCTRL_SAMSUNG_H
20 #include <linux/pinctrl/pinctrl.h>
21 #include <linux/pinctrl/pinmux.h>
22 #include <linux/pinctrl/pinconf.h>
23 #include <linux/pinctrl/consumer.h>
24 #include <linux/pinctrl/machine.h>
26 #include <linux/gpio.h>
28 /* pinmux function number for pin as gpio output line */
29 #define FUNC_INPUT 0x0
30 #define FUNC_OUTPUT 0x1
33 * enum pincfg_type - possible pin configuration types supported.
34 * @PINCFG_TYPE_FUNC: Function configuration.
35 * @PINCFG_TYPE_DAT: Pin value configuration.
36 * @PINCFG_TYPE_PUD: Pull up/down configuration.
37 * @PINCFG_TYPE_DRV: Drive strength configuration.
38 * @PINCFG_TYPE_CON_PDN: Pin function in power down mode.
39 * @PINCFG_TYPE_PUD_PDN: Pull up/down configuration in power down mode.
53 * pin configuration (pull up/down and drive strength) type and its value are
54 * packed together into a 16-bits. The upper 8-bits represent the configuration
55 * type and the lower 8-bits hold the value of the configuration type.
57 #define PINCFG_TYPE_MASK 0xFF
58 #define PINCFG_VALUE_SHIFT 8
59 #define PINCFG_VALUE_MASK (0xFF << PINCFG_VALUE_SHIFT)
60 #define PINCFG_PACK(type, value) (((value) << PINCFG_VALUE_SHIFT) | type)
61 #define PINCFG_UNPACK_TYPE(cfg) ((cfg) & PINCFG_TYPE_MASK)
62 #define PINCFG_UNPACK_VALUE(cfg) (((cfg) & PINCFG_VALUE_MASK) >> \
65 * enum eint_type - possible external interrupt types.
66 * @EINT_TYPE_NONE: bank does not support external interrupts
67 * @EINT_TYPE_GPIO: bank supportes external gpio interrupts
68 * @EINT_TYPE_WKUP: bank supportes external wakeup interrupts
69 * @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts
71 * Samsung GPIO controller groups all the available pins into banks. The pins
72 * in a pin bank can support external gpio interrupts or external wakeup
73 * interrupts or no interrupts at all. From a software perspective, the only
74 * difference between external gpio and external wakeup interrupts is that
75 * the wakeup interrupts can additionally wakeup the system if it is in
85 /* maximum length of a pin in pin descriptor (example: "gpa0-0") */
86 #define PIN_NAME_LENGTH 10
88 #define PIN_GROUP(n, p, f) \
92 .num_pins = ARRAY_SIZE(p), \
96 #define PMX_FUNC(n, g) \
100 .num_groups = ARRAY_SIZE(g), \
103 struct samsung_pinctrl_drv_data
;
106 * struct samsung_pin_bank_type: pin bank type description
107 * @fld_width: widths of configuration bitfields (0 if unavailable)
108 * @reg_offset: offsets of configuration registers (don't care of width is 0)
110 struct samsung_pin_bank_type
{
111 u8 fld_width
[PINCFG_TYPE_NUM
];
112 u8 reg_offset
[PINCFG_TYPE_NUM
];
116 * struct samsung_pin_bank_data: represent a controller pin-bank (init data).
117 * @type: type of the bank (register offsets and bitfield widths)
118 * @pctl_offset: starting offset of the pin-bank registers.
119 * @pctl_res_idx: index of base address for pin-bank registers.
120 * @nr_pins: number of pins included in this bank.
121 * @eint_func: function to set in CON register to configure pin as EINT.
122 * @eint_type: type of the external interrupt supported by the bank.
123 * @eint_mask: bit mask of pins which support EINT function.
124 * @eint_offset: SoC-specific EINT register or interrupt offset of bank.
125 * @name: name to be prefixed for each pin in this pin bank.
127 struct samsung_pin_bank_data
{
128 const struct samsung_pin_bank_type
*type
;
133 enum eint_type eint_type
;
140 * struct samsung_pin_bank: represent a controller pin-bank.
141 * @type: type of the bank (register offsets and bitfield widths)
142 * @pctl_base: base address of the pin-bank registers
143 * @pctl_offset: starting offset of the pin-bank registers.
144 * @nr_pins: number of pins included in this bank.
145 * @eint_base: base address of the pin-bank EINT registers.
146 * @eint_func: function to set in CON register to configure pin as EINT.
147 * @eint_type: type of the external interrupt supported by the bank.
148 * @eint_mask: bit mask of pins which support EINT function.
149 * @eint_offset: SoC-specific EINT register or interrupt offset of bank.
150 * @name: name to be prefixed for each pin in this pin bank.
151 * @pin_base: starting pin number of the bank.
152 * @soc_priv: per-bank private data for SoC-specific code.
153 * @of_node: OF node of the bank.
154 * @drvdata: link to controller driver data
155 * @irq_domain: IRQ domain of the bank.
156 * @gpio_chip: GPIO chip of the bank.
157 * @grange: linux gpio pin range supported by this bank.
158 * @irq_chip: link to irq chip for external gpio and wakeup interrupts.
159 * @slock: spinlock protecting bank registers
160 * @pm_save: saved register values during suspend
162 struct samsung_pin_bank
{
163 const struct samsung_pin_bank_type
*type
;
164 void __iomem
*pctl_base
;
167 void __iomem
*eint_base
;
169 enum eint_type eint_type
;
176 struct device_node
*of_node
;
177 struct samsung_pinctrl_drv_data
*drvdata
;
178 struct irq_domain
*irq_domain
;
179 struct gpio_chip gpio_chip
;
180 struct pinctrl_gpio_range grange
;
181 struct exynos_irq_chip
*irq_chip
;
184 u32 pm_save
[PINCFG_TYPE_NUM
+ 1]; /* +1 to handle double CON registers*/
188 * struct samsung_pin_ctrl: represent a pin controller.
189 * @pin_banks: list of pin banks included in this controller.
190 * @nr_banks: number of pin banks.
191 * @nr_ext_resources: number of the extra base address for pin banks.
192 * @eint_gpio_init: platform specific callback to setup the external gpio
193 * interrupts for the controller.
194 * @eint_wkup_init: platform specific callback to setup the external wakeup
195 * interrupts for the controller.
197 struct samsung_pin_ctrl
{
198 const struct samsung_pin_bank_data
*pin_banks
;
200 int nr_ext_resources
;
202 int (*eint_gpio_init
)(struct samsung_pinctrl_drv_data
*);
203 int (*eint_wkup_init
)(struct samsung_pinctrl_drv_data
*);
204 void (*suspend
)(struct samsung_pinctrl_drv_data
*);
205 void (*resume
)(struct samsung_pinctrl_drv_data
*);
209 * struct samsung_pinctrl_drv_data: wrapper for holding driver data together.
210 * @node: global list node
211 * @dev: device instance representing the controller.
212 * @irq: interrpt number used by the controller to notify gpio interrupts.
213 * @ctrl: pin controller instance managed by the driver.
214 * @pctl: pin controller descriptor registered with the pinctrl subsystem.
215 * @pctl_dev: cookie representing pinctrl device instance.
216 * @pin_groups: list of pin groups available to the driver.
217 * @nr_groups: number of such pin groups.
218 * @pmx_functions: list of pin functions available to the driver.
219 * @nr_function: number of such pin functions.
220 * @pin_base: starting system wide pin number.
221 * @nr_pins: number of pins supported by the controller.
223 struct samsung_pinctrl_drv_data
{
224 struct list_head node
;
228 struct pinctrl_desc pctl
;
229 struct pinctrl_dev
*pctl_dev
;
231 const struct samsung_pin_group
*pin_groups
;
232 unsigned int nr_groups
;
233 const struct samsung_pmx_func
*pmx_functions
;
234 unsigned int nr_functions
;
236 struct samsung_pin_bank
*pin_banks
;
238 unsigned int pin_base
;
239 unsigned int nr_pins
;
241 void (*suspend
)(struct samsung_pinctrl_drv_data
*);
242 void (*resume
)(struct samsung_pinctrl_drv_data
*);
246 * struct samsung_pin_group: represent group of pins of a pinmux function.
247 * @name: name of the pin group, used to lookup the group.
248 * @pins: the pins included in this group.
249 * @num_pins: number of pins included in this group.
250 * @func: the function number to be programmed when selected.
252 struct samsung_pin_group
{
254 const unsigned int *pins
;
260 * struct samsung_pmx_func: represent a pin function.
261 * @name: name of the pin function, used to lookup the function.
262 * @groups: one or more names of pin groups that provide this function.
263 * @num_groups: number of groups included in @groups.
265 struct samsung_pmx_func
{
272 /* list of all exported SoC specific data */
273 extern const struct samsung_pin_ctrl exynos3250_pin_ctrl
[];
274 extern const struct samsung_pin_ctrl exynos4210_pin_ctrl
[];
275 extern const struct samsung_pin_ctrl exynos4x12_pin_ctrl
[];
276 extern const struct samsung_pin_ctrl exynos4415_pin_ctrl
[];
277 extern const struct samsung_pin_ctrl exynos5250_pin_ctrl
[];
278 extern const struct samsung_pin_ctrl exynos5260_pin_ctrl
[];
279 extern const struct samsung_pin_ctrl exynos5410_pin_ctrl
[];
280 extern const struct samsung_pin_ctrl exynos5420_pin_ctrl
[];
281 extern const struct samsung_pin_ctrl exynos5433_pin_ctrl
[];
282 extern const struct samsung_pin_ctrl exynos7_pin_ctrl
[];
283 extern const struct samsung_pin_ctrl s3c64xx_pin_ctrl
[];
284 extern const struct samsung_pin_ctrl s3c2412_pin_ctrl
[];
285 extern const struct samsung_pin_ctrl s3c2416_pin_ctrl
[];
286 extern const struct samsung_pin_ctrl s3c2440_pin_ctrl
[];
287 extern const struct samsung_pin_ctrl s3c2450_pin_ctrl
[];
288 extern const struct samsung_pin_ctrl s5pv210_pin_ctrl
[];
290 #endif /* __PINCTRL_SAMSUNG_H */