2 * Qualcomm Wireless Connectivity Subsystem Peripheral Image Loader
4 * Copyright (C) 2016 Linaro Ltd
5 * Copyright (C) 2014 Sony Mobile Communications AB
6 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/firmware.h>
21 #include <linux/interrupt.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
25 #include <linux/of_address.h>
26 #include <linux/of_device.h>
27 #include <linux/platform_device.h>
28 #include <linux/qcom_scm.h>
29 #include <linux/regulator/consumer.h>
30 #include <linux/remoteproc.h>
31 #include <linux/soc/qcom/smem.h>
32 #include <linux/soc/qcom/smem_state.h>
33 #include <linux/rpmsg/qcom_smd.h>
35 #include "qcom_mdt_loader.h"
36 #include "remoteproc_internal.h"
37 #include "qcom_wcnss.h"
39 #define WCNSS_CRASH_REASON_SMEM 422
40 #define WCNSS_FIRMWARE_NAME "wcnss.mdt"
41 #define WCNSS_PAS_ID 6
43 #define WCNSS_SPARE_NVBIN_DLND BIT(25)
45 #define WCNSS_PMU_IRIS_XO_CFG BIT(3)
46 #define WCNSS_PMU_IRIS_XO_EN BIT(4)
47 #define WCNSS_PMU_GC_BUS_MUX_SEL_TOP BIT(5)
48 #define WCNSS_PMU_IRIS_XO_CFG_STS BIT(6) /* 1: in progress, 0: done */
50 #define WCNSS_PMU_IRIS_RESET BIT(7)
51 #define WCNSS_PMU_IRIS_RESET_STS BIT(8) /* 1: in progress, 0: done */
52 #define WCNSS_PMU_IRIS_XO_READ BIT(9)
53 #define WCNSS_PMU_IRIS_XO_READ_STS BIT(10)
55 #define WCNSS_PMU_XO_MODE_MASK GENMASK(2, 1)
56 #define WCNSS_PMU_XO_MODE_19p2 0
57 #define WCNSS_PMU_XO_MODE_48 3
63 const struct wcnss_vreg_info
*vregs
;
71 void __iomem
*pmu_cfg
;
72 void __iomem
*spare_out
;
82 struct qcom_smem_state
*state
;
85 struct mutex iris_lock
;
86 struct qcom_iris
*iris
;
88 struct regulator_bulk_data
*vregs
;
91 struct completion start_done
;
92 struct completion stop_done
;
95 phys_addr_t mem_reloc
;
99 struct device_node
*smd_node
;
100 struct qcom_smd_edge
*smd_edge
;
101 struct rproc_subdev smd_subdev
;
104 static const struct wcnss_data riva_data
= {
106 .spare_offset
= 0xb4,
108 .vregs
= (struct wcnss_vreg_info
[]) {
109 { "vddmx", 1050000, 1150000, 0 },
110 { "vddcx", 1050000, 1150000, 0 },
111 { "vddpx", 1800000, 1800000, 0 },
116 static const struct wcnss_data pronto_v1_data
= {
117 .pmu_offset
= 0x1004,
118 .spare_offset
= 0x1088,
120 .vregs
= (struct wcnss_vreg_info
[]) {
121 { "vddmx", 950000, 1150000, 0 },
122 { "vddcx", .super_turbo
= true},
123 { "vddpx", 1800000, 1800000, 0 },
128 static const struct wcnss_data pronto_v2_data
= {
129 .pmu_offset
= 0x1004,
130 .spare_offset
= 0x1088,
132 .vregs
= (struct wcnss_vreg_info
[]) {
133 { "vddmx", 1287500, 1287500, 0 },
134 { "vddcx", .super_turbo
= true },
135 { "vddpx", 1800000, 1800000, 0 },
140 void qcom_wcnss_assign_iris(struct qcom_wcnss
*wcnss
,
141 struct qcom_iris
*iris
,
144 mutex_lock(&wcnss
->iris_lock
);
147 wcnss
->use_48mhz_xo
= use_48mhz_xo
;
149 mutex_unlock(&wcnss
->iris_lock
);
152 static int wcnss_load(struct rproc
*rproc
, const struct firmware
*fw
)
154 struct qcom_wcnss
*wcnss
= (struct qcom_wcnss
*)rproc
->priv
;
160 ret
= qcom_scm_pas_init_image(WCNSS_PAS_ID
, fw
->data
, fw
->size
);
162 dev_err(&rproc
->dev
, "invalid firmware metadata\n");
166 ret
= qcom_mdt_parse(fw
, &fw_addr
, &fw_size
, &relocate
);
168 dev_err(&rproc
->dev
, "failed to parse mdt header\n");
173 wcnss
->mem_reloc
= fw_addr
;
175 ret
= qcom_scm_pas_mem_setup(WCNSS_PAS_ID
, wcnss
->mem_phys
, fw_size
);
177 dev_err(&rproc
->dev
, "unable to setup memory for image\n");
182 return qcom_mdt_load(rproc
, fw
, rproc
->firmware
);
185 static const struct rproc_fw_ops wcnss_fw_ops
= {
186 .find_rsc_table
= qcom_mdt_find_rsc_table
,
190 static void wcnss_indicate_nv_download(struct qcom_wcnss
*wcnss
)
194 /* Indicate NV download capability */
195 val
= readl(wcnss
->spare_out
);
196 val
|= WCNSS_SPARE_NVBIN_DLND
;
197 writel(val
, wcnss
->spare_out
);
200 static void wcnss_configure_iris(struct qcom_wcnss
*wcnss
)
204 /* Clear PMU cfg register */
205 writel(0, wcnss
->pmu_cfg
);
207 val
= WCNSS_PMU_GC_BUS_MUX_SEL_TOP
| WCNSS_PMU_IRIS_XO_EN
;
208 writel(val
, wcnss
->pmu_cfg
);
211 val
&= ~WCNSS_PMU_XO_MODE_MASK
;
212 if (wcnss
->use_48mhz_xo
)
213 val
|= WCNSS_PMU_XO_MODE_48
<< 1;
215 val
|= WCNSS_PMU_XO_MODE_19p2
<< 1;
216 writel(val
, wcnss
->pmu_cfg
);
219 val
|= WCNSS_PMU_IRIS_RESET
;
220 writel(val
, wcnss
->pmu_cfg
);
222 /* Wait for PMU.iris_reg_reset_sts */
223 while (readl(wcnss
->pmu_cfg
) & WCNSS_PMU_IRIS_RESET_STS
)
226 /* Clear IRIS reset */
227 val
&= ~WCNSS_PMU_IRIS_RESET
;
228 writel(val
, wcnss
->pmu_cfg
);
230 /* Start IRIS XO configuration */
231 val
|= WCNSS_PMU_IRIS_XO_CFG
;
232 writel(val
, wcnss
->pmu_cfg
);
234 /* Wait for XO configuration to finish */
235 while (readl(wcnss
->pmu_cfg
) & WCNSS_PMU_IRIS_XO_CFG_STS
)
238 /* Stop IRIS XO configuration */
239 val
&= ~WCNSS_PMU_GC_BUS_MUX_SEL_TOP
;
240 val
&= ~WCNSS_PMU_IRIS_XO_CFG
;
241 writel(val
, wcnss
->pmu_cfg
);
243 /* Add some delay for XO to settle */
247 static int wcnss_start(struct rproc
*rproc
)
249 struct qcom_wcnss
*wcnss
= (struct qcom_wcnss
*)rproc
->priv
;
252 mutex_lock(&wcnss
->iris_lock
);
254 dev_err(wcnss
->dev
, "no iris registered\n");
256 goto release_iris_lock
;
259 ret
= regulator_bulk_enable(wcnss
->num_vregs
, wcnss
->vregs
);
261 goto release_iris_lock
;
263 ret
= qcom_iris_enable(wcnss
->iris
);
265 goto disable_regulators
;
267 wcnss_indicate_nv_download(wcnss
);
268 wcnss_configure_iris(wcnss
);
270 ret
= qcom_scm_pas_auth_and_reset(WCNSS_PAS_ID
);
273 "failed to authenticate image and release reset\n");
277 ret
= wait_for_completion_timeout(&wcnss
->start_done
,
278 msecs_to_jiffies(5000));
279 if (wcnss
->ready_irq
> 0 && ret
== 0) {
280 /* We have a ready_irq, but it didn't fire in time. */
281 dev_err(wcnss
->dev
, "start timed out\n");
282 qcom_scm_pas_shutdown(WCNSS_PAS_ID
);
290 qcom_iris_disable(wcnss
->iris
);
292 regulator_bulk_disable(wcnss
->num_vregs
, wcnss
->vregs
);
294 mutex_unlock(&wcnss
->iris_lock
);
299 static int wcnss_stop(struct rproc
*rproc
)
301 struct qcom_wcnss
*wcnss
= (struct qcom_wcnss
*)rproc
->priv
;
305 qcom_smem_state_update_bits(wcnss
->state
,
306 BIT(wcnss
->stop_bit
),
307 BIT(wcnss
->stop_bit
));
309 ret
= wait_for_completion_timeout(&wcnss
->stop_done
,
310 msecs_to_jiffies(5000));
312 dev_err(wcnss
->dev
, "timed out on wait\n");
314 qcom_smem_state_update_bits(wcnss
->state
,
315 BIT(wcnss
->stop_bit
),
319 ret
= qcom_scm_pas_shutdown(WCNSS_PAS_ID
);
321 dev_err(wcnss
->dev
, "failed to shutdown: %d\n", ret
);
326 static void *wcnss_da_to_va(struct rproc
*rproc
, u64 da
, int len
)
328 struct qcom_wcnss
*wcnss
= (struct qcom_wcnss
*)rproc
->priv
;
331 offset
= da
- wcnss
->mem_reloc
;
332 if (offset
< 0 || offset
+ len
> wcnss
->mem_size
)
335 return wcnss
->mem_region
+ offset
;
338 static const struct rproc_ops wcnss_ops
= {
339 .start
= wcnss_start
,
341 .da_to_va
= wcnss_da_to_va
,
344 static irqreturn_t
wcnss_wdog_interrupt(int irq
, void *dev
)
346 struct qcom_wcnss
*wcnss
= dev
;
348 rproc_report_crash(wcnss
->rproc
, RPROC_WATCHDOG
);
353 static irqreturn_t
wcnss_fatal_interrupt(int irq
, void *dev
)
355 struct qcom_wcnss
*wcnss
= dev
;
359 msg
= qcom_smem_get(QCOM_SMEM_HOST_ANY
, WCNSS_CRASH_REASON_SMEM
, &len
);
360 if (!IS_ERR(msg
) && len
> 0 && msg
[0])
361 dev_err(wcnss
->dev
, "fatal error received: %s\n", msg
);
363 rproc_report_crash(wcnss
->rproc
, RPROC_FATAL_ERROR
);
371 static irqreturn_t
wcnss_ready_interrupt(int irq
, void *dev
)
373 struct qcom_wcnss
*wcnss
= dev
;
375 complete(&wcnss
->start_done
);
380 static irqreturn_t
wcnss_handover_interrupt(int irq
, void *dev
)
383 * XXX: At this point we're supposed to release the resources that we
384 * have been holding on behalf of the WCNSS. Unfortunately this
385 * interrupt comes way before the other side seems to be done.
387 * So we're currently relying on the ready interrupt firing later then
388 * this and we just disable the resources at the end of wcnss_start().
394 static irqreturn_t
wcnss_stop_ack_interrupt(int irq
, void *dev
)
396 struct qcom_wcnss
*wcnss
= dev
;
398 complete(&wcnss
->stop_done
);
403 static int wcnss_smd_probe(struct rproc_subdev
*subdev
)
405 struct qcom_wcnss
*wcnss
= container_of(subdev
, struct qcom_wcnss
, smd_subdev
);
407 wcnss
->smd_edge
= qcom_smd_register_edge(wcnss
->dev
, wcnss
->smd_node
);
409 return IS_ERR(wcnss
->smd_edge
) ? PTR_ERR(wcnss
->smd_edge
) : 0;
412 static void wcnss_smd_remove(struct rproc_subdev
*subdev
)
414 struct qcom_wcnss
*wcnss
= container_of(subdev
, struct qcom_wcnss
, smd_subdev
);
416 qcom_smd_unregister_edge(wcnss
->smd_edge
);
417 wcnss
->smd_edge
= NULL
;
420 static int wcnss_init_regulators(struct qcom_wcnss
*wcnss
,
421 const struct wcnss_vreg_info
*info
,
424 struct regulator_bulk_data
*bulk
;
428 bulk
= devm_kcalloc(wcnss
->dev
,
429 num_vregs
, sizeof(struct regulator_bulk_data
),
434 for (i
= 0; i
< num_vregs
; i
++)
435 bulk
[i
].supply
= info
[i
].name
;
437 ret
= devm_regulator_bulk_get(wcnss
->dev
, num_vregs
, bulk
);
441 for (i
= 0; i
< num_vregs
; i
++) {
442 if (info
[i
].max_voltage
)
443 regulator_set_voltage(bulk
[i
].consumer
,
445 info
[i
].max_voltage
);
448 regulator_set_load(bulk
[i
].consumer
, info
[i
].load_uA
);
452 wcnss
->num_vregs
= num_vregs
;
457 static int wcnss_request_irq(struct qcom_wcnss
*wcnss
,
458 struct platform_device
*pdev
,
461 irq_handler_t thread_fn
)
465 ret
= platform_get_irq_byname(pdev
, name
);
466 if (ret
< 0 && optional
) {
467 dev_dbg(&pdev
->dev
, "no %s IRQ defined, ignoring\n", name
);
469 } else if (ret
< 0) {
470 dev_err(&pdev
->dev
, "no %s IRQ defined\n", name
);
474 ret
= devm_request_threaded_irq(&pdev
->dev
, ret
,
476 IRQF_TRIGGER_RISING
| IRQF_ONESHOT
,
479 dev_err(&pdev
->dev
, "request %s IRQ failed\n", name
);
484 static int wcnss_alloc_memory_region(struct qcom_wcnss
*wcnss
)
486 struct device_node
*node
;
490 node
= of_parse_phandle(wcnss
->dev
->of_node
, "memory-region", 0);
492 dev_err(wcnss
->dev
, "no memory-region specified\n");
496 ret
= of_address_to_resource(node
, 0, &r
);
500 wcnss
->mem_phys
= wcnss
->mem_reloc
= r
.start
;
501 wcnss
->mem_size
= resource_size(&r
);
502 wcnss
->mem_region
= devm_ioremap_wc(wcnss
->dev
, wcnss
->mem_phys
, wcnss
->mem_size
);
503 if (!wcnss
->mem_region
) {
504 dev_err(wcnss
->dev
, "unable to map memory region: %pa+%zx\n",
505 &r
.start
, wcnss
->mem_size
);
512 static int wcnss_probe(struct platform_device
*pdev
)
514 const struct wcnss_data
*data
;
515 struct qcom_wcnss
*wcnss
;
516 struct resource
*res
;
521 data
= of_device_get_match_data(&pdev
->dev
);
523 if (!qcom_scm_is_available())
524 return -EPROBE_DEFER
;
526 if (!qcom_scm_pas_supported(WCNSS_PAS_ID
)) {
527 dev_err(&pdev
->dev
, "PAS is not available for WCNSS\n");
531 rproc
= rproc_alloc(&pdev
->dev
, pdev
->name
, &wcnss_ops
,
532 WCNSS_FIRMWARE_NAME
, sizeof(*wcnss
));
534 dev_err(&pdev
->dev
, "unable to allocate remoteproc\n");
538 rproc
->fw_ops
= &wcnss_fw_ops
;
540 wcnss
= (struct qcom_wcnss
*)rproc
->priv
;
541 wcnss
->dev
= &pdev
->dev
;
542 wcnss
->rproc
= rproc
;
543 platform_set_drvdata(pdev
, wcnss
);
545 init_completion(&wcnss
->start_done
);
546 init_completion(&wcnss
->stop_done
);
548 mutex_init(&wcnss
->iris_lock
);
550 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "pmu");
551 mmio
= devm_ioremap_resource(&pdev
->dev
, res
);
557 ret
= wcnss_alloc_memory_region(wcnss
);
561 wcnss
->pmu_cfg
= mmio
+ data
->pmu_offset
;
562 wcnss
->spare_out
= mmio
+ data
->spare_offset
;
564 ret
= wcnss_init_regulators(wcnss
, data
->vregs
, data
->num_vregs
);
568 ret
= wcnss_request_irq(wcnss
, pdev
, "wdog", false, wcnss_wdog_interrupt
);
571 wcnss
->wdog_irq
= ret
;
573 ret
= wcnss_request_irq(wcnss
, pdev
, "fatal", false, wcnss_fatal_interrupt
);
576 wcnss
->fatal_irq
= ret
;
578 ret
= wcnss_request_irq(wcnss
, pdev
, "ready", true, wcnss_ready_interrupt
);
581 wcnss
->ready_irq
= ret
;
583 ret
= wcnss_request_irq(wcnss
, pdev
, "handover", true, wcnss_handover_interrupt
);
586 wcnss
->handover_irq
= ret
;
588 ret
= wcnss_request_irq(wcnss
, pdev
, "stop-ack", true, wcnss_stop_ack_interrupt
);
591 wcnss
->stop_ack_irq
= ret
;
593 if (wcnss
->stop_ack_irq
) {
594 wcnss
->state
= qcom_smem_state_get(&pdev
->dev
, "stop",
596 if (IS_ERR(wcnss
->state
)) {
597 ret
= PTR_ERR(wcnss
->state
);
602 wcnss
->smd_node
= of_get_child_by_name(pdev
->dev
.of_node
, "smd-edge");
604 rproc_add_subdev(rproc
, &wcnss
->smd_subdev
, wcnss_smd_probe
, wcnss_smd_remove
);
606 ret
= rproc_add(rproc
);
610 return of_platform_populate(pdev
->dev
.of_node
, NULL
, NULL
, &pdev
->dev
);
618 static int wcnss_remove(struct platform_device
*pdev
)
620 struct qcom_wcnss
*wcnss
= platform_get_drvdata(pdev
);
622 of_platform_depopulate(&pdev
->dev
);
624 of_node_put(wcnss
->smd_node
);
625 qcom_smem_state_put(wcnss
->state
);
626 rproc_del(wcnss
->rproc
);
627 rproc_free(wcnss
->rproc
);
632 static const struct of_device_id wcnss_of_match
[] = {
633 { .compatible
= "qcom,riva-pil", &riva_data
},
634 { .compatible
= "qcom,pronto-v1-pil", &pronto_v1_data
},
635 { .compatible
= "qcom,pronto-v2-pil", &pronto_v2_data
},
638 MODULE_DEVICE_TABLE(of
, wcnss_of_match
);
640 static struct platform_driver wcnss_driver
= {
641 .probe
= wcnss_probe
,
642 .remove
= wcnss_remove
,
644 .name
= "qcom-wcnss-pil",
645 .of_match_table
= wcnss_of_match
,
649 static int __init
wcnss_init(void)
653 ret
= platform_driver_register(&wcnss_driver
);
657 ret
= platform_driver_register(&qcom_iris_driver
);
659 platform_driver_unregister(&wcnss_driver
);
663 module_init(wcnss_init
);
665 static void __exit
wcnss_exit(void)
667 platform_driver_unregister(&qcom_iris_driver
);
668 platform_driver_unregister(&wcnss_driver
);
670 module_exit(wcnss_exit
);
672 MODULE_DESCRIPTION("Qualcomm Peripherial Image Loader for Wireless Subsystem");
673 MODULE_LICENSE("GPL v2");