1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright (c) 2013-2014 Samsung Electronics Co., Ltd
4 // http://www.samsung.com
6 // Copyright (C) 2013 Google, Inc
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10 #include <linux/module.h>
11 #include <linux/i2c.h>
12 #include <linux/bcd.h>
13 #include <linux/regmap.h>
14 #include <linux/rtc.h>
15 #include <linux/platform_device.h>
16 #include <linux/mfd/samsung/core.h>
17 #include <linux/mfd/samsung/irq.h>
18 #include <linux/mfd/samsung/rtc.h>
19 #include <linux/mfd/samsung/s2mps14.h>
22 * Maximum number of retries for checking changes in UDR field
23 * of S5M_RTC_UDR_CON register (to limit possible endless loop).
25 * After writing to RTC registers (setting time or alarm) read the UDR field
26 * in S5M_RTC_UDR_CON register. UDR is auto-cleared when data have
29 #define UDR_READ_RETRY_CNT 5
40 /* Make sure this is always the last enum name. */
45 * Registers used by the driver which are different between chipsets.
47 * Operations like read time and write alarm/time require updating
48 * specific fields in UDR register. These fields usually are auto-cleared
49 * (with some exceptions).
51 * Table of operations per device:
53 * Device | Write time | Read time | Write alarm
54 * =================================================
55 * S5M8767 | UDR + TIME | | UDR
56 * S2MPS11/14 | WUDR | RUDR | WUDR + RUDR
57 * S2MPS13 | WUDR | RUDR | WUDR + AUDR
58 * S2MPS15 | WUDR | RUDR | AUDR
60 struct s5m_rtc_reg_config
{
61 /* Number of registers used for setting time/alarm0/alarm1 */
62 unsigned int regs_count
;
63 /* First register for time, seconds */
65 /* RTC control register */
67 /* First register for alarm 0, seconds */
69 /* First register for alarm 1, seconds */
72 * Register for update flag (UDR). Typically setting UDR field to 1
73 * will enable update of time or alarm register. Then it will be
74 * auto-cleared after successful update.
76 unsigned int udr_update
;
77 /* Auto-cleared mask in UDR field for writing time and alarm */
78 unsigned int autoclear_udr_mask
;
80 * Masks in UDR field for time and alarm operations.
81 * The read time mask can be 0. Rest should not.
83 unsigned int read_time_udr_mask
;
84 unsigned int write_time_udr_mask
;
85 unsigned int write_alarm_udr_mask
;
88 /* Register map for S5M8763 and S5M8767 */
89 static const struct s5m_rtc_reg_config s5m_rtc_regs
= {
92 .ctrl
= S5M_ALARM1_CONF
,
93 .alarm0
= S5M_ALARM0_SEC
,
94 .alarm1
= S5M_ALARM1_SEC
,
95 .udr_update
= S5M_RTC_UDR_CON
,
96 .autoclear_udr_mask
= S5M_RTC_UDR_MASK
,
97 .read_time_udr_mask
= 0, /* Not needed */
98 .write_time_udr_mask
= S5M_RTC_UDR_MASK
| S5M_RTC_TIME_EN_MASK
,
99 .write_alarm_udr_mask
= S5M_RTC_UDR_MASK
,
102 /* Register map for S2MPS13 */
103 static const struct s5m_rtc_reg_config s2mps13_rtc_regs
= {
105 .time
= S2MPS_RTC_SEC
,
106 .ctrl
= S2MPS_RTC_CTRL
,
107 .alarm0
= S2MPS_ALARM0_SEC
,
108 .alarm1
= S2MPS_ALARM1_SEC
,
109 .udr_update
= S2MPS_RTC_UDR_CON
,
110 .autoclear_udr_mask
= S2MPS_RTC_WUDR_MASK
,
111 .read_time_udr_mask
= S2MPS_RTC_RUDR_MASK
,
112 .write_time_udr_mask
= S2MPS_RTC_WUDR_MASK
,
113 .write_alarm_udr_mask
= S2MPS_RTC_WUDR_MASK
| S2MPS13_RTC_AUDR_MASK
,
116 /* Register map for S2MPS11/14 */
117 static const struct s5m_rtc_reg_config s2mps14_rtc_regs
= {
119 .time
= S2MPS_RTC_SEC
,
120 .ctrl
= S2MPS_RTC_CTRL
,
121 .alarm0
= S2MPS_ALARM0_SEC
,
122 .alarm1
= S2MPS_ALARM1_SEC
,
123 .udr_update
= S2MPS_RTC_UDR_CON
,
124 .autoclear_udr_mask
= S2MPS_RTC_WUDR_MASK
,
125 .read_time_udr_mask
= S2MPS_RTC_RUDR_MASK
,
126 .write_time_udr_mask
= S2MPS_RTC_WUDR_MASK
,
127 .write_alarm_udr_mask
= S2MPS_RTC_WUDR_MASK
| S2MPS_RTC_RUDR_MASK
,
131 * Register map for S2MPS15 - in comparison to S2MPS14 the WUDR and AUDR bits
134 static const struct s5m_rtc_reg_config s2mps15_rtc_regs
= {
136 .time
= S2MPS_RTC_SEC
,
137 .ctrl
= S2MPS_RTC_CTRL
,
138 .alarm0
= S2MPS_ALARM0_SEC
,
139 .alarm1
= S2MPS_ALARM1_SEC
,
140 .udr_update
= S2MPS_RTC_UDR_CON
,
141 .autoclear_udr_mask
= S2MPS_RTC_WUDR_MASK
,
142 .read_time_udr_mask
= S2MPS_RTC_RUDR_MASK
,
143 .write_time_udr_mask
= S2MPS15_RTC_WUDR_MASK
,
144 .write_alarm_udr_mask
= S2MPS15_RTC_AUDR_MASK
,
147 struct s5m_rtc_info
{
149 struct i2c_client
*i2c
;
150 struct sec_pmic_dev
*s5m87xx
;
151 struct regmap
*regmap
;
152 struct rtc_device
*rtc_dev
;
154 enum sec_device_type device_type
;
156 const struct s5m_rtc_reg_config
*regs
;
159 static const struct regmap_config s5m_rtc_regmap_config
= {
163 .max_register
= S5M_RTC_REG_MAX
,
166 static const struct regmap_config s2mps14_rtc_regmap_config
= {
170 .max_register
= S2MPS_RTC_REG_MAX
,
173 static void s5m8767_data_to_tm(u8
*data
, struct rtc_time
*tm
,
176 tm
->tm_sec
= data
[RTC_SEC
] & 0x7f;
177 tm
->tm_min
= data
[RTC_MIN
] & 0x7f;
179 tm
->tm_hour
= data
[RTC_HOUR
] & 0x1f;
181 tm
->tm_hour
= data
[RTC_HOUR
] & 0x0f;
182 if (data
[RTC_HOUR
] & HOUR_PM_MASK
)
186 tm
->tm_wday
= ffs(data
[RTC_WEEKDAY
] & 0x7f);
187 tm
->tm_mday
= data
[RTC_DATE
] & 0x1f;
188 tm
->tm_mon
= (data
[RTC_MONTH
] & 0x0f) - 1;
189 tm
->tm_year
= (data
[RTC_YEAR1
] & 0x7f) + 100;
194 static int s5m8767_tm_to_data(struct rtc_time
*tm
, u8
*data
)
196 data
[RTC_SEC
] = tm
->tm_sec
;
197 data
[RTC_MIN
] = tm
->tm_min
;
199 if (tm
->tm_hour
>= 12)
200 data
[RTC_HOUR
] = tm
->tm_hour
| HOUR_PM_MASK
;
202 data
[RTC_HOUR
] = tm
->tm_hour
& ~HOUR_PM_MASK
;
204 data
[RTC_WEEKDAY
] = 1 << tm
->tm_wday
;
205 data
[RTC_DATE
] = tm
->tm_mday
;
206 data
[RTC_MONTH
] = tm
->tm_mon
+ 1;
207 data
[RTC_YEAR1
] = tm
->tm_year
- 100;
213 * Read RTC_UDR_CON register and wait till UDR field is cleared.
214 * This indicates that time/alarm update ended.
216 static int s5m8767_wait_for_udr_update(struct s5m_rtc_info
*info
)
218 int ret
, retry
= UDR_READ_RETRY_CNT
;
222 ret
= regmap_read(info
->regmap
, info
->regs
->udr_update
, &data
);
223 } while (--retry
&& (data
& info
->regs
->autoclear_udr_mask
) && !ret
);
226 dev_err(info
->dev
, "waiting for UDR update, reached max number of retries\n");
231 static int s5m_check_peding_alarm_interrupt(struct s5m_rtc_info
*info
,
232 struct rtc_wkalrm
*alarm
)
237 switch (info
->device_type
) {
240 ret
= regmap_read(info
->regmap
, S5M_RTC_STATUS
, &val
);
241 val
&= S5M_ALARM0_STATUS
;
246 ret
= regmap_read(info
->s5m87xx
->regmap_pmic
, S2MPS14_REG_ST2
,
248 val
&= S2MPS_ALARM0_STATUS
;
264 static int s5m8767_rtc_set_time_reg(struct s5m_rtc_info
*info
)
269 ret
= regmap_read(info
->regmap
, info
->regs
->udr_update
, &data
);
271 dev_err(info
->dev
, "failed to read update reg(%d)\n", ret
);
275 data
|= info
->regs
->write_time_udr_mask
;
277 ret
= regmap_write(info
->regmap
, info
->regs
->udr_update
, data
);
279 dev_err(info
->dev
, "failed to write update reg(%d)\n", ret
);
283 ret
= s5m8767_wait_for_udr_update(info
);
288 static int s5m8767_rtc_set_alarm_reg(struct s5m_rtc_info
*info
)
293 ret
= regmap_read(info
->regmap
, info
->regs
->udr_update
, &data
);
295 dev_err(info
->dev
, "%s: fail to read update reg(%d)\n",
300 data
|= info
->regs
->write_alarm_udr_mask
;
301 switch (info
->device_type
) {
304 data
&= ~S5M_RTC_TIME_EN_MASK
;
309 /* No exceptions needed */
315 ret
= regmap_write(info
->regmap
, info
->regs
->udr_update
, data
);
317 dev_err(info
->dev
, "%s: fail to write update reg(%d)\n",
322 ret
= s5m8767_wait_for_udr_update(info
);
324 /* On S2MPS13 the AUDR is not auto-cleared */
325 if (info
->device_type
== S2MPS13X
)
326 regmap_update_bits(info
->regmap
, info
->regs
->udr_update
,
327 S2MPS13_RTC_AUDR_MASK
, 0);
332 static void s5m8763_data_to_tm(u8
*data
, struct rtc_time
*tm
)
334 tm
->tm_sec
= bcd2bin(data
[RTC_SEC
]);
335 tm
->tm_min
= bcd2bin(data
[RTC_MIN
]);
337 if (data
[RTC_HOUR
] & HOUR_12
) {
338 tm
->tm_hour
= bcd2bin(data
[RTC_HOUR
] & 0x1f);
339 if (data
[RTC_HOUR
] & HOUR_PM
)
342 tm
->tm_hour
= bcd2bin(data
[RTC_HOUR
] & 0x3f);
345 tm
->tm_wday
= data
[RTC_WEEKDAY
] & 0x07;
346 tm
->tm_mday
= bcd2bin(data
[RTC_DATE
]);
347 tm
->tm_mon
= bcd2bin(data
[RTC_MONTH
]);
348 tm
->tm_year
= bcd2bin(data
[RTC_YEAR1
]) + bcd2bin(data
[RTC_YEAR2
]) * 100;
352 static void s5m8763_tm_to_data(struct rtc_time
*tm
, u8
*data
)
354 data
[RTC_SEC
] = bin2bcd(tm
->tm_sec
);
355 data
[RTC_MIN
] = bin2bcd(tm
->tm_min
);
356 data
[RTC_HOUR
] = bin2bcd(tm
->tm_hour
);
357 data
[RTC_WEEKDAY
] = tm
->tm_wday
;
358 data
[RTC_DATE
] = bin2bcd(tm
->tm_mday
);
359 data
[RTC_MONTH
] = bin2bcd(tm
->tm_mon
);
360 data
[RTC_YEAR1
] = bin2bcd(tm
->tm_year
% 100);
361 data
[RTC_YEAR2
] = bin2bcd((tm
->tm_year
+ 1900) / 100);
364 static int s5m_rtc_read_time(struct device
*dev
, struct rtc_time
*tm
)
366 struct s5m_rtc_info
*info
= dev_get_drvdata(dev
);
367 u8 data
[RTC_MAX_NUM_TIME_REGS
];
370 if (info
->regs
->read_time_udr_mask
) {
371 ret
= regmap_update_bits(info
->regmap
,
372 info
->regs
->udr_update
,
373 info
->regs
->read_time_udr_mask
,
374 info
->regs
->read_time_udr_mask
);
377 "Failed to prepare registers for time reading: %d\n",
382 ret
= regmap_bulk_read(info
->regmap
, info
->regs
->time
, data
,
383 info
->regs
->regs_count
);
387 switch (info
->device_type
) {
389 s5m8763_data_to_tm(data
, tm
);
396 s5m8767_data_to_tm(data
, tm
, info
->rtc_24hr_mode
);
403 dev_dbg(dev
, "%s: %ptR(%d)\n", __func__
, tm
, tm
->tm_wday
);
408 static int s5m_rtc_set_time(struct device
*dev
, struct rtc_time
*tm
)
410 struct s5m_rtc_info
*info
= dev_get_drvdata(dev
);
411 u8 data
[RTC_MAX_NUM_TIME_REGS
];
414 switch (info
->device_type
) {
416 s5m8763_tm_to_data(tm
, data
);
422 ret
= s5m8767_tm_to_data(tm
, data
);
431 dev_dbg(dev
, "%s: %ptR(%d)\n", __func__
, tm
, tm
->tm_wday
);
433 ret
= regmap_raw_write(info
->regmap
, info
->regs
->time
, data
,
434 info
->regs
->regs_count
);
438 ret
= s5m8767_rtc_set_time_reg(info
);
443 static int s5m_rtc_read_alarm(struct device
*dev
, struct rtc_wkalrm
*alrm
)
445 struct s5m_rtc_info
*info
= dev_get_drvdata(dev
);
446 u8 data
[RTC_MAX_NUM_TIME_REGS
];
450 ret
= regmap_bulk_read(info
->regmap
, info
->regs
->alarm0
, data
,
451 info
->regs
->regs_count
);
455 switch (info
->device_type
) {
457 s5m8763_data_to_tm(data
, &alrm
->time
);
458 ret
= regmap_read(info
->regmap
, S5M_ALARM0_CONF
, &val
);
462 alrm
->enabled
= !!val
;
469 s5m8767_data_to_tm(data
, &alrm
->time
, info
->rtc_24hr_mode
);
471 for (i
= 0; i
< info
->regs
->regs_count
; i
++) {
472 if (data
[i
] & ALARM_ENABLE_MASK
) {
483 dev_dbg(dev
, "%s: %ptR(%d)\n", __func__
, &alrm
->time
, alrm
->time
.tm_wday
);
485 return s5m_check_peding_alarm_interrupt(info
, alrm
);
488 static int s5m_rtc_stop_alarm(struct s5m_rtc_info
*info
)
490 u8 data
[RTC_MAX_NUM_TIME_REGS
];
494 ret
= regmap_bulk_read(info
->regmap
, info
->regs
->alarm0
, data
,
495 info
->regs
->regs_count
);
499 s5m8767_data_to_tm(data
, &tm
, info
->rtc_24hr_mode
);
500 dev_dbg(info
->dev
, "%s: %ptR(%d)\n", __func__
, &tm
, tm
.tm_wday
);
502 switch (info
->device_type
) {
504 ret
= regmap_write(info
->regmap
, S5M_ALARM0_CONF
, 0);
511 for (i
= 0; i
< info
->regs
->regs_count
; i
++)
512 data
[i
] &= ~ALARM_ENABLE_MASK
;
514 ret
= regmap_raw_write(info
->regmap
, info
->regs
->alarm0
, data
,
515 info
->regs
->regs_count
);
519 ret
= s5m8767_rtc_set_alarm_reg(info
);
530 static int s5m_rtc_start_alarm(struct s5m_rtc_info
*info
)
533 u8 data
[RTC_MAX_NUM_TIME_REGS
];
537 ret
= regmap_bulk_read(info
->regmap
, info
->regs
->alarm0
, data
,
538 info
->regs
->regs_count
);
542 s5m8767_data_to_tm(data
, &tm
, info
->rtc_24hr_mode
);
543 dev_dbg(info
->dev
, "%s: %ptR(%d)\n", __func__
, &tm
, tm
.tm_wday
);
545 switch (info
->device_type
) {
548 ret
= regmap_write(info
->regmap
, S5M_ALARM0_CONF
, alarm0_conf
);
555 data
[RTC_SEC
] |= ALARM_ENABLE_MASK
;
556 data
[RTC_MIN
] |= ALARM_ENABLE_MASK
;
557 data
[RTC_HOUR
] |= ALARM_ENABLE_MASK
;
558 data
[RTC_WEEKDAY
] &= ~ALARM_ENABLE_MASK
;
559 if (data
[RTC_DATE
] & 0x1f)
560 data
[RTC_DATE
] |= ALARM_ENABLE_MASK
;
561 if (data
[RTC_MONTH
] & 0xf)
562 data
[RTC_MONTH
] |= ALARM_ENABLE_MASK
;
563 if (data
[RTC_YEAR1
] & 0x7f)
564 data
[RTC_YEAR1
] |= ALARM_ENABLE_MASK
;
566 ret
= regmap_raw_write(info
->regmap
, info
->regs
->alarm0
, data
,
567 info
->regs
->regs_count
);
570 ret
= s5m8767_rtc_set_alarm_reg(info
);
581 static int s5m_rtc_set_alarm(struct device
*dev
, struct rtc_wkalrm
*alrm
)
583 struct s5m_rtc_info
*info
= dev_get_drvdata(dev
);
584 u8 data
[RTC_MAX_NUM_TIME_REGS
];
587 switch (info
->device_type
) {
589 s5m8763_tm_to_data(&alrm
->time
, data
);
596 s5m8767_tm_to_data(&alrm
->time
, data
);
603 dev_dbg(dev
, "%s: %ptR(%d)\n", __func__
, &alrm
->time
, alrm
->time
.tm_wday
);
605 ret
= s5m_rtc_stop_alarm(info
);
609 ret
= regmap_raw_write(info
->regmap
, info
->regs
->alarm0
, data
,
610 info
->regs
->regs_count
);
614 ret
= s5m8767_rtc_set_alarm_reg(info
);
619 ret
= s5m_rtc_start_alarm(info
);
624 static int s5m_rtc_alarm_irq_enable(struct device
*dev
,
625 unsigned int enabled
)
627 struct s5m_rtc_info
*info
= dev_get_drvdata(dev
);
630 return s5m_rtc_start_alarm(info
);
632 return s5m_rtc_stop_alarm(info
);
635 static irqreturn_t
s5m_rtc_alarm_irq(int irq
, void *data
)
637 struct s5m_rtc_info
*info
= data
;
639 rtc_update_irq(info
->rtc_dev
, 1, RTC_IRQF
| RTC_AF
);
644 static const struct rtc_class_ops s5m_rtc_ops
= {
645 .read_time
= s5m_rtc_read_time
,
646 .set_time
= s5m_rtc_set_time
,
647 .read_alarm
= s5m_rtc_read_alarm
,
648 .set_alarm
= s5m_rtc_set_alarm
,
649 .alarm_irq_enable
= s5m_rtc_alarm_irq_enable
,
652 static int s5m8767_rtc_init_reg(struct s5m_rtc_info
*info
)
657 switch (info
->device_type
) {
660 /* UDR update time. Default of 7.32 ms is too long. */
661 ret
= regmap_update_bits(info
->regmap
, S5M_RTC_UDR_CON
,
662 S5M_RTC_UDR_T_MASK
, S5M_RTC_UDR_T_450_US
);
664 dev_err(info
->dev
, "%s: fail to change UDR time: %d\n",
667 /* Set RTC control register : Binary mode, 24hour mode */
668 data
[0] = (1 << BCD_EN_SHIFT
) | (1 << MODEL24_SHIFT
);
669 data
[1] = (0 << BCD_EN_SHIFT
) | (1 << MODEL24_SHIFT
);
671 ret
= regmap_raw_write(info
->regmap
, S5M_ALARM0_CONF
, data
, 2);
677 data
[0] = (0 << BCD_EN_SHIFT
) | (1 << MODEL24_SHIFT
);
678 ret
= regmap_write(info
->regmap
, info
->regs
->ctrl
, data
[0]);
683 * Should set WUDR & (RUDR or AUDR) bits to high after writing
684 * RTC_CTRL register like writing Alarm registers. We can't find
685 * the description from datasheet but vendor code does that
688 ret
= s5m8767_rtc_set_alarm_reg(info
);
695 info
->rtc_24hr_mode
= 1;
697 dev_err(info
->dev
, "%s: fail to write controlm reg(%d)\n",
705 static int s5m_rtc_probe(struct platform_device
*pdev
)
707 struct sec_pmic_dev
*s5m87xx
= dev_get_drvdata(pdev
->dev
.parent
);
708 struct s5m_rtc_info
*info
;
709 const struct regmap_config
*regmap_cfg
;
712 info
= devm_kzalloc(&pdev
->dev
, sizeof(*info
), GFP_KERNEL
);
716 switch (platform_get_device_id(pdev
)->driver_data
) {
718 regmap_cfg
= &s2mps14_rtc_regmap_config
;
719 info
->regs
= &s2mps15_rtc_regs
;
720 alarm_irq
= S2MPS14_IRQ_RTCA0
;
723 regmap_cfg
= &s2mps14_rtc_regmap_config
;
724 info
->regs
= &s2mps14_rtc_regs
;
725 alarm_irq
= S2MPS14_IRQ_RTCA0
;
728 regmap_cfg
= &s2mps14_rtc_regmap_config
;
729 info
->regs
= &s2mps13_rtc_regs
;
730 alarm_irq
= S2MPS14_IRQ_RTCA0
;
733 regmap_cfg
= &s5m_rtc_regmap_config
;
734 info
->regs
= &s5m_rtc_regs
;
735 alarm_irq
= S5M8763_IRQ_ALARM0
;
738 regmap_cfg
= &s5m_rtc_regmap_config
;
739 info
->regs
= &s5m_rtc_regs
;
740 alarm_irq
= S5M8767_IRQ_RTCA1
;
744 "Device type %lu is not supported by RTC driver\n",
745 platform_get_device_id(pdev
)->driver_data
);
749 info
->i2c
= devm_i2c_new_dummy_device(&pdev
->dev
, s5m87xx
->i2c
->adapter
,
751 if (IS_ERR(info
->i2c
)) {
752 dev_err(&pdev
->dev
, "Failed to allocate I2C for RTC\n");
753 return PTR_ERR(info
->i2c
);
756 info
->regmap
= devm_regmap_init_i2c(info
->i2c
, regmap_cfg
);
757 if (IS_ERR(info
->regmap
)) {
758 ret
= PTR_ERR(info
->regmap
);
759 dev_err(&pdev
->dev
, "Failed to allocate RTC register map: %d\n",
764 info
->dev
= &pdev
->dev
;
765 info
->s5m87xx
= s5m87xx
;
766 info
->device_type
= platform_get_device_id(pdev
)->driver_data
;
768 if (s5m87xx
->irq_data
) {
769 info
->irq
= regmap_irq_get_virq(s5m87xx
->irq_data
, alarm_irq
);
770 if (info
->irq
<= 0) {
771 dev_err(&pdev
->dev
, "Failed to get virtual IRQ %d\n",
777 platform_set_drvdata(pdev
, info
);
779 ret
= s5m8767_rtc_init_reg(info
);
783 info
->rtc_dev
= devm_rtc_allocate_device(&pdev
->dev
);
784 if (IS_ERR(info
->rtc_dev
))
785 return PTR_ERR(info
->rtc_dev
);
787 info
->rtc_dev
->ops
= &s5m_rtc_ops
;
789 if (info
->device_type
== S5M8763X
) {
790 info
->rtc_dev
->range_min
= RTC_TIMESTAMP_BEGIN_0000
;
791 info
->rtc_dev
->range_max
= RTC_TIMESTAMP_END_9999
;
793 info
->rtc_dev
->range_min
= RTC_TIMESTAMP_BEGIN_2000
;
794 info
->rtc_dev
->range_max
= RTC_TIMESTAMP_END_2099
;
798 clear_bit(RTC_FEATURE_ALARM
, info
->rtc_dev
->features
);
800 ret
= devm_request_threaded_irq(&pdev
->dev
, info
->irq
, NULL
,
801 s5m_rtc_alarm_irq
, 0, "rtc-alarm0",
804 dev_err(&pdev
->dev
, "Failed to request alarm IRQ: %d: %d\n",
808 device_init_wakeup(&pdev
->dev
, 1);
811 return devm_rtc_register_device(info
->rtc_dev
);
814 #ifdef CONFIG_PM_SLEEP
815 static int s5m_rtc_resume(struct device
*dev
)
817 struct s5m_rtc_info
*info
= dev_get_drvdata(dev
);
820 if (info
->irq
&& device_may_wakeup(dev
))
821 ret
= disable_irq_wake(info
->irq
);
826 static int s5m_rtc_suspend(struct device
*dev
)
828 struct s5m_rtc_info
*info
= dev_get_drvdata(dev
);
831 if (info
->irq
&& device_may_wakeup(dev
))
832 ret
= enable_irq_wake(info
->irq
);
836 #endif /* CONFIG_PM_SLEEP */
838 static SIMPLE_DEV_PM_OPS(s5m_rtc_pm_ops
, s5m_rtc_suspend
, s5m_rtc_resume
);
840 static const struct platform_device_id s5m_rtc_id
[] = {
841 { "s5m-rtc", S5M8767X
},
842 { "s2mps13-rtc", S2MPS13X
},
843 { "s2mps14-rtc", S2MPS14X
},
844 { "s2mps15-rtc", S2MPS15X
},
847 MODULE_DEVICE_TABLE(platform
, s5m_rtc_id
);
849 static struct platform_driver s5m_rtc_driver
= {
852 .pm
= &s5m_rtc_pm_ops
,
854 .probe
= s5m_rtc_probe
,
855 .id_table
= s5m_rtc_id
,
858 module_platform_driver(s5m_rtc_driver
);
860 /* Module information */
861 MODULE_AUTHOR("Sangbeom Kim <sbkim73@samsung.com>");
862 MODULE_DESCRIPTION("Samsung S5M/S2MPS14 RTC driver");
863 MODULE_LICENSE("GPL");
864 MODULE_ALIAS("platform:s5m-rtc");