2 * ahci.c - AHCI SATA support
4 * Copyright 2004 Red Hat, Inc.
6 * The contents of this file are subject to the Open
7 * Software License version 1.1 that can be found at
8 * http://www.opensource.org/licenses/osl-1.1.txt and is included herein
11 * Alternatively, the contents of this file may be used under the terms
12 * of the GNU General Public License version 2 (the "GPL") as distributed
13 * in the kernel source COPYING file, in which case the provisions of
14 * the GPL are applicable instead of the above. If you wish to allow
15 * the use of your version of this file only under the terms of the
16 * GPL and not to allow others to use your version of this file under
17 * the OSL, indicate your decision by deleting the provisions above and
18 * replace them with the notice and other provisions required by the GPL.
19 * If you do not delete the provisions above, a recipient may use your
20 * version of this file under either the OSL or the GPL.
22 * Version 1.0 of the AHCI specification:
23 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/pci.h>
30 #include <linux/init.h>
31 #include <linux/blkdev.h>
32 #include <linux/delay.h>
33 #include <linux/interrupt.h>
34 #include <linux/sched.h>
36 #include <scsi/scsi_host.h>
37 #include <linux/libata.h>
40 #define DRV_NAME "ahci"
41 #define DRV_VERSION "1.00"
46 AHCI_MAX_SG
= 168, /* hardware max is 64K */
47 AHCI_DMA_BOUNDARY
= 0xffffffff,
48 AHCI_USE_CLUSTERING
= 0,
49 AHCI_CMD_SLOT_SZ
= 32 * 32,
51 AHCI_CMD_TBL_HDR
= 0x80,
52 AHCI_CMD_TBL_SZ
= AHCI_CMD_TBL_HDR
+ (AHCI_MAX_SG
* 16),
53 AHCI_PORT_PRIV_DMA_SZ
= AHCI_CMD_SLOT_SZ
+ AHCI_CMD_TBL_SZ
+
55 AHCI_IRQ_ON_SG
= (1 << 31),
56 AHCI_CMD_ATAPI
= (1 << 5),
57 AHCI_CMD_WRITE
= (1 << 6),
59 RX_FIS_D2H_REG
= 0x40, /* offset of D2H Register FIS data */
63 /* global controller registers */
64 HOST_CAP
= 0x00, /* host capabilities */
65 HOST_CTL
= 0x04, /* global host control */
66 HOST_IRQ_STAT
= 0x08, /* interrupt status */
67 HOST_PORTS_IMPL
= 0x0c, /* bitmap of implemented ports */
68 HOST_VERSION
= 0x10, /* AHCI spec. version compliancy */
71 HOST_RESET
= (1 << 0), /* reset controller; self-clear */
72 HOST_IRQ_EN
= (1 << 1), /* global IRQ enable */
73 HOST_AHCI_EN
= (1 << 31), /* AHCI enabled */
76 HOST_CAP_64
= (1 << 31), /* PCI DAC (64-bit DMA) support */
78 /* registers for each SATA port */
79 PORT_LST_ADDR
= 0x00, /* command list DMA addr */
80 PORT_LST_ADDR_HI
= 0x04, /* command list DMA addr hi */
81 PORT_FIS_ADDR
= 0x08, /* FIS rx buf addr */
82 PORT_FIS_ADDR_HI
= 0x0c, /* FIS rx buf addr hi */
83 PORT_IRQ_STAT
= 0x10, /* interrupt status */
84 PORT_IRQ_MASK
= 0x14, /* interrupt enable/disable mask */
85 PORT_CMD
= 0x18, /* port command */
86 PORT_TFDATA
= 0x20, /* taskfile data */
87 PORT_SIG
= 0x24, /* device TF signature */
88 PORT_CMD_ISSUE
= 0x38, /* command issue */
89 PORT_SCR
= 0x28, /* SATA phy register block */
90 PORT_SCR_STAT
= 0x28, /* SATA phy register: SStatus */
91 PORT_SCR_CTL
= 0x2c, /* SATA phy register: SControl */
92 PORT_SCR_ERR
= 0x30, /* SATA phy register: SError */
93 PORT_SCR_ACT
= 0x34, /* SATA phy register: SActive */
95 /* PORT_IRQ_{STAT,MASK} bits */
96 PORT_IRQ_COLD_PRES
= (1 << 31), /* cold presence detect */
97 PORT_IRQ_TF_ERR
= (1 << 30), /* task file error */
98 PORT_IRQ_HBUS_ERR
= (1 << 29), /* host bus fatal error */
99 PORT_IRQ_HBUS_DATA_ERR
= (1 << 28), /* host bus data error */
100 PORT_IRQ_IF_ERR
= (1 << 27), /* interface fatal error */
101 PORT_IRQ_IF_NONFATAL
= (1 << 26), /* interface non-fatal error */
102 PORT_IRQ_OVERFLOW
= (1 << 24), /* xfer exhausted available S/G */
103 PORT_IRQ_BAD_PMP
= (1 << 23), /* incorrect port multiplier */
105 PORT_IRQ_PHYRDY
= (1 << 22), /* PhyRdy changed */
106 PORT_IRQ_DEV_ILCK
= (1 << 7), /* device interlock */
107 PORT_IRQ_CONNECT
= (1 << 6), /* port connect change status */
108 PORT_IRQ_SG_DONE
= (1 << 5), /* descriptor processed */
109 PORT_IRQ_UNK_FIS
= (1 << 4), /* unknown FIS rx'd */
110 PORT_IRQ_SDB_FIS
= (1 << 3), /* Set Device Bits FIS rx'd */
111 PORT_IRQ_DMAS_FIS
= (1 << 2), /* DMA Setup FIS rx'd */
112 PORT_IRQ_PIOS_FIS
= (1 << 1), /* PIO Setup FIS rx'd */
113 PORT_IRQ_D2H_REG_FIS
= (1 << 0), /* D2H Register FIS rx'd */
115 PORT_IRQ_FATAL
= PORT_IRQ_TF_ERR
|
117 PORT_IRQ_HBUS_DATA_ERR
|
119 DEF_PORT_IRQ
= PORT_IRQ_FATAL
| PORT_IRQ_PHYRDY
|
120 PORT_IRQ_CONNECT
| PORT_IRQ_SG_DONE
|
121 PORT_IRQ_UNK_FIS
| PORT_IRQ_SDB_FIS
|
122 PORT_IRQ_DMAS_FIS
| PORT_IRQ_PIOS_FIS
|
123 PORT_IRQ_D2H_REG_FIS
,
126 PORT_CMD_LIST_ON
= (1 << 15), /* cmd list DMA engine running */
127 PORT_CMD_FIS_ON
= (1 << 14), /* FIS DMA engine running */
128 PORT_CMD_FIS_RX
= (1 << 4), /* Enable FIS receive DMA engine */
129 PORT_CMD_POWER_ON
= (1 << 2), /* Power up device */
130 PORT_CMD_SPIN_UP
= (1 << 1), /* Spin up device */
131 PORT_CMD_START
= (1 << 0), /* Enable port DMA engine */
133 PORT_CMD_ICC_ACTIVE
= (0x1 << 28), /* Put i/f in active state */
134 PORT_CMD_ICC_PARTIAL
= (0x2 << 28), /* Put i/f in partial state */
135 PORT_CMD_ICC_SLUMBER
= (0x6 << 28), /* Put i/f in slumber state */
138 struct ahci_cmd_hdr
{
153 struct ahci_host_priv
{
155 u32 cap
; /* cache of HOST_CAP register */
156 u32 port_map
; /* cache of HOST_PORTS_IMPL reg */
159 struct ahci_port_priv
{
160 struct ahci_cmd_hdr
*cmd_slot
;
161 dma_addr_t cmd_slot_dma
;
163 dma_addr_t cmd_tbl_dma
;
164 struct ahci_sg
*cmd_tbl_sg
;
166 dma_addr_t rx_fis_dma
;
169 static u32
ahci_scr_read (struct ata_port
*ap
, unsigned int sc_reg
);
170 static void ahci_scr_write (struct ata_port
*ap
, unsigned int sc_reg
, u32 val
);
171 static int ahci_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
);
172 static int ahci_qc_issue(struct ata_queued_cmd
*qc
);
173 static irqreturn_t
ahci_interrupt (int irq
, void *dev_instance
, struct pt_regs
*regs
);
174 static void ahci_phy_reset(struct ata_port
*ap
);
175 static void ahci_irq_clear(struct ata_port
*ap
);
176 static void ahci_eng_timeout(struct ata_port
*ap
);
177 static int ahci_port_start(struct ata_port
*ap
);
178 static void ahci_port_stop(struct ata_port
*ap
);
179 static void ahci_host_stop(struct ata_host_set
*host_set
);
180 static void ahci_tf_read(struct ata_port
*ap
, struct ata_taskfile
*tf
);
181 static void ahci_qc_prep(struct ata_queued_cmd
*qc
);
182 static u8
ahci_check_status(struct ata_port
*ap
);
183 static u8
ahci_check_err(struct ata_port
*ap
);
184 static inline int ahci_host_intr(struct ata_port
*ap
, struct ata_queued_cmd
*qc
);
186 static Scsi_Host_Template ahci_sht
= {
187 .module
= THIS_MODULE
,
189 .ioctl
= ata_scsi_ioctl
,
190 .queuecommand
= ata_scsi_queuecmd
,
191 .eh_strategy_handler
= ata_scsi_error
,
192 .can_queue
= ATA_DEF_QUEUE
,
193 .this_id
= ATA_SHT_THIS_ID
,
194 .sg_tablesize
= AHCI_MAX_SG
,
195 .max_sectors
= ATA_MAX_SECTORS
,
196 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
197 .emulated
= ATA_SHT_EMULATED
,
198 .use_clustering
= AHCI_USE_CLUSTERING
,
199 .proc_name
= DRV_NAME
,
200 .dma_boundary
= AHCI_DMA_BOUNDARY
,
201 .slave_configure
= ata_scsi_slave_config
,
202 .bios_param
= ata_std_bios_param
,
206 static struct ata_port_operations ahci_ops
= {
207 .port_disable
= ata_port_disable
,
209 .check_status
= ahci_check_status
,
210 .check_altstatus
= ahci_check_status
,
211 .check_err
= ahci_check_err
,
212 .dev_select
= ata_noop_dev_select
,
214 .tf_read
= ahci_tf_read
,
216 .phy_reset
= ahci_phy_reset
,
218 .qc_prep
= ahci_qc_prep
,
219 .qc_issue
= ahci_qc_issue
,
221 .eng_timeout
= ahci_eng_timeout
,
223 .irq_handler
= ahci_interrupt
,
224 .irq_clear
= ahci_irq_clear
,
226 .scr_read
= ahci_scr_read
,
227 .scr_write
= ahci_scr_write
,
229 .port_start
= ahci_port_start
,
230 .port_stop
= ahci_port_stop
,
231 .host_stop
= ahci_host_stop
,
234 static struct ata_port_info ahci_port_info
[] = {
238 .host_flags
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
239 ATA_FLAG_SATA_RESET
| ATA_FLAG_MMIO
|
241 .pio_mask
= 0x03, /* pio3-4 */
242 .udma_mask
= 0x7f, /* udma0-6 ; FIXME */
243 .port_ops
= &ahci_ops
,
247 static struct pci_device_id ahci_pci_tbl
[] = {
248 { PCI_VENDOR_ID_INTEL
, 0x2652, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
249 board_ahci
}, /* ICH6 */
250 { PCI_VENDOR_ID_INTEL
, 0x2653, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
251 board_ahci
}, /* ICH6M */
252 { PCI_VENDOR_ID_INTEL
, 0x27c1, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
253 board_ahci
}, /* ICH7 */
254 { PCI_VENDOR_ID_INTEL
, 0x27c5, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
255 board_ahci
}, /* ICH7M */
256 { PCI_VENDOR_ID_INTEL
, 0x27c3, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
257 board_ahci
}, /* ICH7R */
258 { PCI_VENDOR_ID_AL
, 0x5288, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
259 board_ahci
}, /* ULi M5288 */
260 { } /* terminate list */
264 static struct pci_driver ahci_pci_driver
= {
266 .id_table
= ahci_pci_tbl
,
267 .probe
= ahci_init_one
,
268 .remove
= ata_pci_remove_one
,
272 static inline unsigned long ahci_port_base_ul (unsigned long base
, unsigned int port
)
274 return base
+ 0x100 + (port
* 0x80);
277 static inline void *ahci_port_base (void *base
, unsigned int port
)
279 return (void *) ahci_port_base_ul((unsigned long)base
, port
);
282 static void ahci_host_stop(struct ata_host_set
*host_set
)
284 struct ahci_host_priv
*hpriv
= host_set
->private_data
;
288 static int ahci_port_start(struct ata_port
*ap
)
290 struct device
*dev
= ap
->host_set
->dev
;
291 struct ahci_host_priv
*hpriv
= ap
->host_set
->private_data
;
292 struct ahci_port_priv
*pp
;
294 void *mem
, *mmio
= ap
->host_set
->mmio_base
;
295 void *port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
298 rc
= ata_port_start(ap
);
302 pp
= kmalloc(sizeof(*pp
), GFP_KERNEL
);
307 memset(pp
, 0, sizeof(*pp
));
309 mem
= dma_alloc_coherent(dev
, AHCI_PORT_PRIV_DMA_SZ
, &mem_dma
, GFP_KERNEL
);
314 memset(mem
, 0, AHCI_PORT_PRIV_DMA_SZ
);
317 * First item in chunk of DMA memory: 32-slot command table,
318 * 32 bytes each in size
321 pp
->cmd_slot_dma
= mem_dma
;
323 mem
+= AHCI_CMD_SLOT_SZ
;
324 mem_dma
+= AHCI_CMD_SLOT_SZ
;
327 * Second item: Received-FIS area
330 pp
->rx_fis_dma
= mem_dma
;
332 mem
+= AHCI_RX_FIS_SZ
;
333 mem_dma
+= AHCI_RX_FIS_SZ
;
336 * Third item: data area for storing a single command
337 * and its scatter-gather table
340 pp
->cmd_tbl_dma
= mem_dma
;
342 pp
->cmd_tbl_sg
= mem
+ AHCI_CMD_TBL_HDR
;
344 ap
->private_data
= pp
;
346 if (hpriv
->cap
& HOST_CAP_64
)
347 writel((pp
->cmd_slot_dma
>> 16) >> 16, port_mmio
+ PORT_LST_ADDR_HI
);
348 writel(pp
->cmd_slot_dma
& 0xffffffff, port_mmio
+ PORT_LST_ADDR
);
349 readl(port_mmio
+ PORT_LST_ADDR
); /* flush */
351 if (hpriv
->cap
& HOST_CAP_64
)
352 writel((pp
->rx_fis_dma
>> 16) >> 16, port_mmio
+ PORT_FIS_ADDR_HI
);
353 writel(pp
->rx_fis_dma
& 0xffffffff, port_mmio
+ PORT_FIS_ADDR
);
354 readl(port_mmio
+ PORT_FIS_ADDR
); /* flush */
356 writel(PORT_CMD_ICC_ACTIVE
| PORT_CMD_FIS_RX
|
357 PORT_CMD_POWER_ON
| PORT_CMD_SPIN_UP
|
358 PORT_CMD_START
, port_mmio
+ PORT_CMD
);
359 readl(port_mmio
+ PORT_CMD
); /* flush */
371 static void ahci_port_stop(struct ata_port
*ap
)
373 struct device
*dev
= ap
->host_set
->dev
;
374 struct ahci_port_priv
*pp
= ap
->private_data
;
375 void *mmio
= ap
->host_set
->mmio_base
;
376 void *port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
379 tmp
= readl(port_mmio
+ PORT_CMD
);
380 tmp
&= ~(PORT_CMD_START
| PORT_CMD_FIS_RX
);
381 writel(tmp
, port_mmio
+ PORT_CMD
);
382 readl(port_mmio
+ PORT_CMD
); /* flush */
384 /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so
385 * this is slightly incorrect.
389 ap
->private_data
= NULL
;
390 dma_free_coherent(dev
, AHCI_PORT_PRIV_DMA_SZ
,
391 pp
->cmd_slot
, pp
->cmd_slot_dma
);
396 static u32
ahci_scr_read (struct ata_port
*ap
, unsigned int sc_reg_in
)
401 case SCR_STATUS
: sc_reg
= 0; break;
402 case SCR_CONTROL
: sc_reg
= 1; break;
403 case SCR_ERROR
: sc_reg
= 2; break;
404 case SCR_ACTIVE
: sc_reg
= 3; break;
409 return readl((void *) ap
->ioaddr
.scr_addr
+ (sc_reg
* 4));
413 static void ahci_scr_write (struct ata_port
*ap
, unsigned int sc_reg_in
,
419 case SCR_STATUS
: sc_reg
= 0; break;
420 case SCR_CONTROL
: sc_reg
= 1; break;
421 case SCR_ERROR
: sc_reg
= 2; break;
422 case SCR_ACTIVE
: sc_reg
= 3; break;
427 writel(val
, (void *) ap
->ioaddr
.scr_addr
+ (sc_reg
* 4));
430 static void ahci_phy_reset(struct ata_port
*ap
)
432 void __iomem
*port_mmio
= (void __iomem
*) ap
->ioaddr
.cmd_addr
;
433 struct ata_taskfile tf
;
434 struct ata_device
*dev
= &ap
->device
[0];
437 __sata_phy_reset(ap
);
439 if (ap
->flags
& ATA_FLAG_PORT_DISABLED
)
442 tmp
= readl(port_mmio
+ PORT_SIG
);
443 tf
.lbah
= (tmp
>> 24) & 0xff;
444 tf
.lbam
= (tmp
>> 16) & 0xff;
445 tf
.lbal
= (tmp
>> 8) & 0xff;
446 tf
.nsect
= (tmp
) & 0xff;
448 dev
->class = ata_dev_classify(&tf
);
449 if (!ata_dev_present(dev
))
450 ata_port_disable(ap
);
453 static u8
ahci_check_status(struct ata_port
*ap
)
455 void *mmio
= (void *) ap
->ioaddr
.cmd_addr
;
457 return readl(mmio
+ PORT_TFDATA
) & 0xFF;
460 static u8
ahci_check_err(struct ata_port
*ap
)
462 void *mmio
= (void *) ap
->ioaddr
.cmd_addr
;
464 return (readl(mmio
+ PORT_TFDATA
) >> 8) & 0xFF;
467 static void ahci_tf_read(struct ata_port
*ap
, struct ata_taskfile
*tf
)
469 struct ahci_port_priv
*pp
= ap
->private_data
;
470 u8
*d2h_fis
= pp
->rx_fis
+ RX_FIS_D2H_REG
;
472 ata_tf_from_fis(d2h_fis
, tf
);
475 static void ahci_fill_sg(struct ata_queued_cmd
*qc
)
477 struct ahci_port_priv
*pp
= qc
->ap
->private_data
;
483 * Next, the S/G list.
485 for (i
= 0; i
< qc
->n_elem
; i
++) {
489 addr
= sg_dma_address(&qc
->sg
[i
]);
490 sg_len
= sg_dma_len(&qc
->sg
[i
]);
492 pp
->cmd_tbl_sg
[i
].addr
= cpu_to_le32(addr
& 0xffffffff);
493 pp
->cmd_tbl_sg
[i
].addr_hi
= cpu_to_le32((addr
>> 16) >> 16);
494 pp
->cmd_tbl_sg
[i
].flags_size
= cpu_to_le32(sg_len
- 1);
498 static void ahci_qc_prep(struct ata_queued_cmd
*qc
)
500 struct ahci_port_priv
*pp
= qc
->ap
->private_data
;
502 const u32 cmd_fis_len
= 5; /* five dwords */
505 * Fill in command slot information (currently only one slot,
506 * slot 0, is currently since we don't do queueing)
509 opts
= (qc
->n_elem
<< 16) | cmd_fis_len
;
510 if (qc
->tf
.flags
& ATA_TFLAG_WRITE
)
511 opts
|= AHCI_CMD_WRITE
;
513 switch (qc
->tf
.protocol
) {
515 case ATA_PROT_ATAPI_NODATA
:
516 case ATA_PROT_ATAPI_DMA
:
517 opts
|= AHCI_CMD_ATAPI
;
525 pp
->cmd_slot
[0].opts
= cpu_to_le32(opts
);
526 pp
->cmd_slot
[0].status
= 0;
527 pp
->cmd_slot
[0].tbl_addr
= cpu_to_le32(pp
->cmd_tbl_dma
& 0xffffffff);
528 pp
->cmd_slot
[0].tbl_addr_hi
= cpu_to_le32((pp
->cmd_tbl_dma
>> 16) >> 16);
531 * Fill in command table information. First, the header,
532 * a SATA Register - Host to Device command FIS.
534 ata_tf_to_fis(&qc
->tf
, pp
->cmd_tbl
, 0);
536 if (!(qc
->flags
& ATA_QCFLAG_DMAMAP
))
542 static void ahci_intr_error(struct ata_port
*ap
, u32 irq_stat
)
544 void *mmio
= ap
->host_set
->mmio_base
;
545 void *port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
550 tmp
= readl(port_mmio
+ PORT_CMD
);
551 tmp
&= ~PORT_CMD_START
;
552 writel(tmp
, port_mmio
+ PORT_CMD
);
554 /* wait for engine to stop. TODO: this could be
555 * as long as 500 msec
559 tmp
= readl(port_mmio
+ PORT_CMD
);
560 if ((tmp
& PORT_CMD_LIST_ON
) == 0)
565 /* clear SATA phy error, if any */
566 tmp
= readl(port_mmio
+ PORT_SCR_ERR
);
567 writel(tmp
, port_mmio
+ PORT_SCR_ERR
);
569 /* if DRQ/BSY is set, device needs to be reset.
570 * if so, issue COMRESET
572 tmp
= readl(port_mmio
+ PORT_TFDATA
);
573 if (tmp
& (ATA_BUSY
| ATA_DRQ
)) {
574 writel(0x301, port_mmio
+ PORT_SCR_CTL
);
575 readl(port_mmio
+ PORT_SCR_CTL
); /* flush */
577 writel(0x300, port_mmio
+ PORT_SCR_CTL
);
578 readl(port_mmio
+ PORT_SCR_CTL
); /* flush */
582 tmp
= readl(port_mmio
+ PORT_CMD
);
583 tmp
|= PORT_CMD_START
;
584 writel(tmp
, port_mmio
+ PORT_CMD
);
585 readl(port_mmio
+ PORT_CMD
); /* flush */
587 printk(KERN_WARNING
"ata%u: error occurred, port reset\n", ap
->id
);
590 static void ahci_eng_timeout(struct ata_port
*ap
)
592 void *mmio
= ap
->host_set
->mmio_base
;
593 void *port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
594 struct ata_queued_cmd
*qc
;
598 ahci_intr_error(ap
, readl(port_mmio
+ PORT_IRQ_STAT
));
600 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
602 printk(KERN_ERR
"ata%u: BUG: timeout without command\n",
605 /* hack alert! We cannot use the supplied completion
606 * function from inside the ->eh_strategy_handler() thread.
607 * libata is the only user of ->eh_strategy_handler() in
608 * any kernel, so the default scsi_done() assumes it is
609 * not being called from the SCSI EH.
611 qc
->scsidone
= scsi_finish_command
;
612 ata_qc_complete(qc
, ATA_ERR
);
617 static inline int ahci_host_intr(struct ata_port
*ap
, struct ata_queued_cmd
*qc
)
619 void *mmio
= ap
->host_set
->mmio_base
;
620 void *port_mmio
= ahci_port_base(mmio
, ap
->port_no
);
621 u32 status
, serr
, ci
;
623 serr
= readl(port_mmio
+ PORT_SCR_ERR
);
624 writel(serr
, port_mmio
+ PORT_SCR_ERR
);
626 status
= readl(port_mmio
+ PORT_IRQ_STAT
);
627 writel(status
, port_mmio
+ PORT_IRQ_STAT
);
629 ci
= readl(port_mmio
+ PORT_CMD_ISSUE
);
630 if (likely((ci
& 0x1) == 0)) {
632 ata_qc_complete(qc
, 0);
637 if (status
& PORT_IRQ_FATAL
) {
638 ahci_intr_error(ap
, status
);
640 ata_qc_complete(qc
, ATA_ERR
);
646 static void ahci_irq_clear(struct ata_port
*ap
)
651 static irqreturn_t
ahci_interrupt (int irq
, void *dev_instance
, struct pt_regs
*regs
)
653 struct ata_host_set
*host_set
= dev_instance
;
654 struct ahci_host_priv
*hpriv
;
655 unsigned int i
, handled
= 0;
657 u32 irq_stat
, irq_ack
= 0;
661 hpriv
= host_set
->private_data
;
662 mmio
= host_set
->mmio_base
;
664 /* sigh. 0xffffffff is a valid return from h/w */
665 irq_stat
= readl(mmio
+ HOST_IRQ_STAT
);
666 irq_stat
&= hpriv
->port_map
;
670 spin_lock(&host_set
->lock
);
672 for (i
= 0; i
< host_set
->n_ports
; i
++) {
676 VPRINTK("port %u\n", i
);
677 ap
= host_set
->ports
[i
];
678 tmp
= irq_stat
& (1 << i
);
680 struct ata_queued_cmd
*qc
;
681 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
682 if (ahci_host_intr(ap
, qc
))
688 writel(irq_ack
, mmio
+ HOST_IRQ_STAT
);
692 spin_unlock(&host_set
->lock
);
696 return IRQ_RETVAL(handled
);
699 static int ahci_qc_issue(struct ata_queued_cmd
*qc
)
701 struct ata_port
*ap
= qc
->ap
;
702 void *port_mmio
= (void *) ap
->ioaddr
.cmd_addr
;
704 writel(1, port_mmio
+ PORT_SCR_ACT
);
705 readl(port_mmio
+ PORT_SCR_ACT
); /* flush */
707 writel(1, port_mmio
+ PORT_CMD_ISSUE
);
708 readl(port_mmio
+ PORT_CMD_ISSUE
); /* flush */
713 static void ahci_setup_port(struct ata_ioports
*port
, unsigned long base
,
714 unsigned int port_idx
)
716 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base
, port_idx
);
717 base
= ahci_port_base_ul(base
, port_idx
);
718 VPRINTK("base now==0x%lx\n", base
);
720 port
->cmd_addr
= base
;
721 port
->scr_addr
= base
+ PORT_SCR
;
726 static int ahci_host_init(struct ata_probe_ent
*probe_ent
)
728 struct ahci_host_priv
*hpriv
= probe_ent
->private_data
;
729 struct pci_dev
*pdev
= to_pci_dev(probe_ent
->dev
);
730 void __iomem
*mmio
= probe_ent
->mmio_base
;
733 unsigned int i
, j
, using_dac
;
735 void __iomem
*port_mmio
;
737 cap_save
= readl(mmio
+ HOST_CAP
);
738 cap_save
&= ( (1<<28) | (1<<17) );
739 cap_save
|= (1 << 27);
741 /* global controller reset */
742 tmp
= readl(mmio
+ HOST_CTL
);
743 if ((tmp
& HOST_RESET
) == 0) {
744 writel(tmp
| HOST_RESET
, mmio
+ HOST_CTL
);
745 readl(mmio
+ HOST_CTL
); /* flush */
748 /* reset must complete within 1 second, or
749 * the hardware should be considered fried.
753 tmp
= readl(mmio
+ HOST_CTL
);
754 if (tmp
& HOST_RESET
) {
755 printk(KERN_ERR DRV_NAME
"(%s): controller reset failed (0x%x)\n",
756 pci_name(pdev
), tmp
);
760 writel(HOST_AHCI_EN
, mmio
+ HOST_CTL
);
761 (void) readl(mmio
+ HOST_CTL
); /* flush */
762 writel(cap_save
, mmio
+ HOST_CAP
);
763 writel(0xf, mmio
+ HOST_PORTS_IMPL
);
764 (void) readl(mmio
+ HOST_PORTS_IMPL
); /* flush */
766 pci_read_config_word(pdev
, 0x92, &tmp16
);
768 pci_write_config_word(pdev
, 0x92, tmp16
);
770 hpriv
->cap
= readl(mmio
+ HOST_CAP
);
771 hpriv
->port_map
= readl(mmio
+ HOST_PORTS_IMPL
);
772 probe_ent
->n_ports
= (hpriv
->cap
& 0x1f) + 1;
774 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
775 hpriv
->cap
, hpriv
->port_map
, probe_ent
->n_ports
);
777 using_dac
= hpriv
->cap
& HOST_CAP_64
;
779 !pci_set_dma_mask(pdev
, DMA_64BIT_MASK
)) {
780 rc
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
782 rc
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
784 printk(KERN_ERR DRV_NAME
"(%s): 64-bit DMA enable failed\n",
790 hpriv
->flags
|= HOST_CAP_64
;
792 rc
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
794 printk(KERN_ERR DRV_NAME
"(%s): 32-bit DMA enable failed\n",
798 rc
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
800 printk(KERN_ERR DRV_NAME
"(%s): 32-bit consistent DMA enable failed\n",
806 for (i
= 0; i
< probe_ent
->n_ports
; i
++) {
807 #if 0 /* BIOSen initialize this incorrectly */
808 if (!(hpriv
->port_map
& (1 << i
)))
812 port_mmio
= ahci_port_base(mmio
, i
);
813 VPRINTK("mmio %p port_mmio %p\n", mmio
, port_mmio
);
815 ahci_setup_port(&probe_ent
->port
[i
],
816 (unsigned long) mmio
, i
);
818 /* make sure port is not active */
819 tmp
= readl(port_mmio
+ PORT_CMD
);
820 VPRINTK("PORT_CMD 0x%x\n", tmp
);
821 if (tmp
& (PORT_CMD_LIST_ON
| PORT_CMD_FIS_ON
|
822 PORT_CMD_FIS_RX
| PORT_CMD_START
)) {
823 tmp
&= ~(PORT_CMD_LIST_ON
| PORT_CMD_FIS_ON
|
824 PORT_CMD_FIS_RX
| PORT_CMD_START
);
825 writel(tmp
, port_mmio
+ PORT_CMD
);
826 readl(port_mmio
+ PORT_CMD
); /* flush */
828 /* spec says 500 msecs for each bit, so
829 * this is slightly incorrect.
834 writel(PORT_CMD_SPIN_UP
, port_mmio
+ PORT_CMD
);
839 tmp
= readl(port_mmio
+ PORT_SCR_STAT
);
840 if ((tmp
& 0xf) == 0x3)
845 tmp
= readl(port_mmio
+ PORT_SCR_ERR
);
846 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp
);
847 writel(tmp
, port_mmio
+ PORT_SCR_ERR
);
849 /* ack any pending irq events for this port */
850 tmp
= readl(port_mmio
+ PORT_IRQ_STAT
);
851 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp
);
853 writel(tmp
, port_mmio
+ PORT_IRQ_STAT
);
855 writel(1 << i
, mmio
+ HOST_IRQ_STAT
);
857 /* set irq mask (enables interrupts) */
858 writel(DEF_PORT_IRQ
, port_mmio
+ PORT_IRQ_MASK
);
861 tmp
= readl(mmio
+ HOST_CTL
);
862 VPRINTK("HOST_CTL 0x%x\n", tmp
);
863 writel(tmp
| HOST_IRQ_EN
, mmio
+ HOST_CTL
);
864 tmp
= readl(mmio
+ HOST_CTL
);
865 VPRINTK("HOST_CTL 0x%x\n", tmp
);
867 pci_set_master(pdev
);
872 /* move to PCI layer, integrate w/ MSI stuff */
873 static void pci_enable_intx(struct pci_dev
*pdev
)
877 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_command
);
878 if (pci_command
& PCI_COMMAND_INTX_DISABLE
) {
879 pci_command
&= ~PCI_COMMAND_INTX_DISABLE
;
880 pci_write_config_word(pdev
, PCI_COMMAND
, pci_command
);
884 static void ahci_print_info(struct ata_probe_ent
*probe_ent
)
886 struct ahci_host_priv
*hpriv
= probe_ent
->private_data
;
887 struct pci_dev
*pdev
= to_pci_dev(probe_ent
->dev
);
888 void *mmio
= probe_ent
->mmio_base
;
889 u32 vers
, cap
, impl
, speed
;
894 vers
= readl(mmio
+ HOST_VERSION
);
896 impl
= hpriv
->port_map
;
898 speed
= (cap
>> 20) & 0xf;
906 pci_read_config_word(pdev
, 0x0a, &cc
);
909 else if (cc
== 0x0106)
911 else if (cc
== 0x0104)
916 printk(KERN_INFO DRV_NAME
"(%s) AHCI %02x%02x.%02x%02x "
917 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
926 ((cap
>> 8) & 0x1f) + 1,
932 printk(KERN_INFO DRV_NAME
"(%s) flags: "
938 cap
& (1 << 31) ? "64bit " : "",
939 cap
& (1 << 30) ? "ncq " : "",
940 cap
& (1 << 28) ? "ilck " : "",
941 cap
& (1 << 27) ? "stag " : "",
942 cap
& (1 << 26) ? "pm " : "",
943 cap
& (1 << 25) ? "led " : "",
945 cap
& (1 << 24) ? "clo " : "",
946 cap
& (1 << 19) ? "nz " : "",
947 cap
& (1 << 18) ? "only " : "",
948 cap
& (1 << 17) ? "pmp " : "",
949 cap
& (1 << 15) ? "pio " : "",
950 cap
& (1 << 14) ? "slum " : "",
951 cap
& (1 << 13) ? "part " : ""
955 static int ahci_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
957 static int printed_version
;
958 struct ata_probe_ent
*probe_ent
= NULL
;
959 struct ahci_host_priv
*hpriv
;
962 unsigned int board_idx
= (unsigned int) ent
->driver_data
;
963 int pci_dev_busy
= 0;
968 if (!printed_version
++)
969 printk(KERN_DEBUG DRV_NAME
" version " DRV_VERSION
"\n");
971 rc
= pci_enable_device(pdev
);
975 rc
= pci_request_regions(pdev
, DRV_NAME
);
981 pci_enable_intx(pdev
);
983 probe_ent
= kmalloc(sizeof(*probe_ent
), GFP_KERNEL
);
984 if (probe_ent
== NULL
) {
986 goto err_out_regions
;
989 memset(probe_ent
, 0, sizeof(*probe_ent
));
990 probe_ent
->dev
= pci_dev_to_dev(pdev
);
991 INIT_LIST_HEAD(&probe_ent
->node
);
993 mmio_base
= ioremap(pci_resource_start(pdev
, AHCI_PCI_BAR
),
994 pci_resource_len(pdev
, AHCI_PCI_BAR
));
995 if (mmio_base
== NULL
) {
997 goto err_out_free_ent
;
999 base
= (unsigned long) mmio_base
;
1001 hpriv
= kmalloc(sizeof(*hpriv
), GFP_KERNEL
);
1004 goto err_out_iounmap
;
1006 memset(hpriv
, 0, sizeof(*hpriv
));
1008 probe_ent
->sht
= ahci_port_info
[board_idx
].sht
;
1009 probe_ent
->host_flags
= ahci_port_info
[board_idx
].host_flags
;
1010 probe_ent
->pio_mask
= ahci_port_info
[board_idx
].pio_mask
;
1011 probe_ent
->udma_mask
= ahci_port_info
[board_idx
].udma_mask
;
1012 probe_ent
->port_ops
= ahci_port_info
[board_idx
].port_ops
;
1014 probe_ent
->irq
= pdev
->irq
;
1015 probe_ent
->irq_flags
= SA_SHIRQ
;
1016 probe_ent
->mmio_base
= mmio_base
;
1017 probe_ent
->private_data
= hpriv
;
1019 /* initialize adapter */
1020 rc
= ahci_host_init(probe_ent
);
1024 ahci_print_info(probe_ent
);
1026 /* FIXME: check ata_device_add return value */
1027 ata_device_add(probe_ent
);
1039 pci_release_regions(pdev
);
1042 pci_disable_device(pdev
);
1047 static int __init
ahci_init(void)
1049 return pci_module_init(&ahci_pci_driver
);
1053 static void __exit
ahci_exit(void)
1055 pci_unregister_driver(&ahci_pci_driver
);
1059 MODULE_AUTHOR("Jeff Garzik");
1060 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1061 MODULE_LICENSE("GPL");
1062 MODULE_DEVICE_TABLE(pci
, ahci_pci_tbl
);
1064 module_init(ahci_init
);
1065 module_exit(ahci_exit
);