2 * CXL Flash Device Driver
4 * Written by: Manoj N. Kumar <manoj@linux.vnet.ibm.com>, IBM Corporation
5 * Matthew R. Ochs <mrochs@linux.vnet.ibm.com>, IBM Corporation
7 * Copyright (C) 2015 IBM Corporation
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
15 #ifndef _CXLFLASH_COMMON_H
16 #define _CXLFLASH_COMMON_H
18 #include <linux/irq_poll.h>
19 #include <linux/list.h>
20 #include <linux/rwsem.h>
21 #include <linux/types.h>
22 #include <scsi/scsi.h>
23 #include <scsi/scsi_cmnd.h>
24 #include <scsi/scsi_device.h>
26 extern const struct file_operations cxlflash_cxl_fops
;
28 #define MAX_CONTEXT CXLFLASH_MAX_CONTEXT /* num contexts per afu */
29 #define MAX_FC_PORTS CXLFLASH_MAX_FC_PORTS /* max ports per AFU */
30 #define LEGACY_FC_PORTS 2 /* legacy ports per AFU */
32 #define CHAN2PORTBANK(_x) ((_x) >> ilog2(CXLFLASH_NUM_FC_PORTS_PER_BANK))
33 #define CHAN2BANKPORT(_x) ((_x) & (CXLFLASH_NUM_FC_PORTS_PER_BANK - 1))
35 #define CHAN2PORTMASK(_x) (1 << (_x)) /* channel to port mask */
36 #define PORTMASK2CHAN(_x) (ilog2((_x))) /* port mask to channel */
37 #define PORTNUM2CHAN(_x) ((_x) - 1) /* port number to channel */
39 #define CXLFLASH_BLOCK_SIZE 4096 /* 4K blocks */
40 #define CXLFLASH_MAX_XFER_SIZE 16777216 /* 16MB transfer */
41 #define CXLFLASH_MAX_SECTORS (CXLFLASH_MAX_XFER_SIZE/512) /* SCSI wants
48 #define MAX_RHT_PER_CONTEXT (PAGE_SIZE / sizeof(struct sisl_rht_entry))
50 /* AFU command retry limit */
51 #define MC_RETRY_CNT 5 /* Sufficient for SCSI and certain AFU errors */
53 /* Command management definitions */
54 #define CXLFLASH_MAX_CMDS 256
55 #define CXLFLASH_MAX_CMDS_PER_LUN CXLFLASH_MAX_CMDS
57 /* RRQ for master issued cmds */
58 #define NUM_RRQ_ENTRY CXLFLASH_MAX_CMDS
60 /* SQ for master issued cmds */
61 #define NUM_SQ_ENTRY CXLFLASH_MAX_CMDS
63 /* Hardware queue definitions */
64 #define CXLFLASH_DEF_HWQS 1
65 #define CXLFLASH_MAX_HWQS 8
69 static inline void check_sizes(void)
71 BUILD_BUG_ON_NOT_POWER_OF_2(CXLFLASH_NUM_FC_PORTS_PER_BANK
);
72 BUILD_BUG_ON_NOT_POWER_OF_2(CXLFLASH_MAX_CMDS
);
75 /* AFU defines a fixed size of 4K for command buffers (borrow 4K page define) */
76 #define CMD_BUFSIZE SIZE_4K
78 enum cxlflash_lr_state
{
84 enum cxlflash_init_state
{
92 STATE_PROBING
, /* Initial state during probe */
93 STATE_PROBED
, /* Temporary state, probe completed but EEH occurred */
94 STATE_NORMAL
, /* Normal running state, everything good */
95 STATE_RESET
, /* Reset state, trying to reset/recover */
96 STATE_FAILTERM
/* Failed/terminating state, error out users/threads */
99 enum cxlflash_hwq_mode
{
100 HWQ_MODE_RR
, /* Roundrobin (default) */
101 HWQ_MODE_TAG
, /* Distribute based on block MQ tag */
102 HWQ_MODE_CPU
, /* CPU affinity */
107 * Each context has its own set of resource handles that is visible
108 * only from that context.
111 struct cxlflash_cfg
{
115 struct pci_device_id
*dev_id
;
116 struct Scsi_Host
*host
;
119 ulong cxlflash_regs_pci
;
121 struct work_struct work_q
;
122 enum cxlflash_init_state init_state
;
123 enum cxlflash_lr_state lr_state
;
125 atomic_t scan_host_needed
;
127 struct cxl_afu
*cxl_afu
;
129 atomic_t recovery_threads
;
130 struct mutex ctx_recovery_mutex
;
131 struct mutex ctx_tbl_list_mutex
;
132 struct rw_semaphore ioctl_rwsem
;
133 struct ctx_info
*ctx_tbl
[MAX_CONTEXT
];
134 struct list_head ctx_err_recovery
; /* contexts w/ recovery pending */
135 struct file_operations cxl_fops
;
137 /* Parameters that are LUN table related */
138 int last_lun_index
[MAX_FC_PORTS
];
139 int promote_lun_index
;
140 struct list_head lluns
; /* list of llun_info structs */
142 wait_queue_head_t tmf_waitq
;
143 spinlock_t tmf_slock
;
145 wait_queue_head_t reset_waitq
;
146 enum cxlflash_state state
;
150 struct sisl_ioarcb rcb
; /* IOARCB (cache line aligned) */
151 struct sisl_ioasa sa
; /* IOASA must follow IOARCB */
153 struct scsi_cmnd
*scp
;
154 struct completion cevent
;
155 struct list_head queue
;
160 /* As per the SISLITE spec the IOARCB EA has to be 16-byte aligned.
161 * However for performance reasons the IOARCB/IOASA should be
162 * cache line aligned.
164 } __aligned(cache_line_size());
166 static inline struct afu_cmd
*sc_to_afuc(struct scsi_cmnd
*sc
)
168 return PTR_ALIGN(scsi_cmd_priv(sc
), __alignof__(struct afu_cmd
));
171 static inline struct afu_cmd
*sc_to_afucz(struct scsi_cmnd
*sc
)
173 struct afu_cmd
*afuc
= sc_to_afuc(sc
);
175 memset(afuc
, 0, sizeof(*afuc
));
180 /* Stuff requiring alignment go first. */
181 struct sisl_ioarcb sq
[NUM_SQ_ENTRY
]; /* 16K SQ */
182 u64 rrq_entry
[NUM_RRQ_ENTRY
]; /* 2K RRQ */
184 /* Beware of alignment till here. Preferably introduce new
185 * fields after this point
188 struct cxl_context
*ctx
;
189 struct cxl_ioctl_start_work work
;
190 struct sisl_host_map __iomem
*host_map
; /* MC host map */
191 struct sisl_ctrl_map __iomem
*ctrl_map
; /* MC control map */
192 ctx_hndl_t ctx_hndl
; /* master's context handle */
193 u32 index
; /* Index of this hwq */
195 atomic_t hsq_credits
;
196 spinlock_t hsq_slock
; /* Hardware send queue lock */
197 struct sisl_ioarcb
*hsq_start
;
198 struct sisl_ioarcb
*hsq_end
;
199 struct sisl_ioarcb
*hsq_curr
;
200 spinlock_t hrrq_slock
;
208 struct irq_poll irqpoll
;
209 } __aligned(cache_line_size());
212 struct hwq hwqs
[CXLFLASH_MAX_HWQS
];
213 int (*send_cmd
)(struct afu
*, struct afu_cmd
*);
214 void (*context_reset
)(struct afu_cmd
*);
217 struct cxlflash_afu_map __iomem
*afu_map
; /* entire MMIO map */
219 atomic_t cmds_active
; /* Number of currently active AFU commands */
221 u32 internal_lun
; /* User-desired LUN mode for this AFU */
223 u32 num_hwqs
; /* Number of hardware queues */
224 u32 desired_hwqs
; /* Desired h/w queues, effective on AFU reset */
225 enum cxlflash_hwq_mode hwq_mode
; /* Steering mode for h/w queues */
226 u32 hwq_rr_count
; /* Count to distribute traffic for roundrobin */
229 u64 interface_version
;
232 struct cxlflash_cfg
*parent
; /* Pointer back to parent cxlflash_cfg */
235 static inline struct hwq
*get_hwq(struct afu
*afu
, u32 index
)
237 WARN_ON(index
>= CXLFLASH_MAX_HWQS
);
239 return &afu
->hwqs
[index
];
242 static inline bool afu_is_irqpoll_enabled(struct afu
*afu
)
244 return !!afu
->irqpoll_weight
;
247 static inline bool afu_is_cmd_mode(struct afu
*afu
, u64 cmd_mode
)
249 u64 afu_cap
= afu
->interface_version
>> SISL_INTVER_CAP_SHIFT
;
251 return afu_cap
& cmd_mode
;
254 static inline bool afu_is_sq_cmd_mode(struct afu
*afu
)
256 return afu_is_cmd_mode(afu
, SISL_INTVER_CAP_SQ_CMD_MODE
);
259 static inline bool afu_is_ioarrin_cmd_mode(struct afu
*afu
)
261 return afu_is_cmd_mode(afu
, SISL_INTVER_CAP_IOARRIN_CMD_MODE
);
264 static inline u64
lun_to_lunid(u64 lun
)
268 int_to_scsilun(lun
, (struct scsi_lun
*)&lun_id
);
269 return be64_to_cpu(lun_id
);
272 static inline struct fc_port_bank __iomem
*get_fc_port_bank(
273 struct cxlflash_cfg
*cfg
, int i
)
275 struct afu
*afu
= cfg
->afu
;
277 return &afu
->afu_map
->global
.bank
[CHAN2PORTBANK(i
)];
280 static inline __be64 __iomem
*get_fc_port_regs(struct cxlflash_cfg
*cfg
, int i
)
282 struct fc_port_bank __iomem
*fcpb
= get_fc_port_bank(cfg
, i
);
284 return &fcpb
->fc_port_regs
[CHAN2BANKPORT(i
)][0];
287 static inline __be64 __iomem
*get_fc_port_luns(struct cxlflash_cfg
*cfg
, int i
)
289 struct fc_port_bank __iomem
*fcpb
= get_fc_port_bank(cfg
, i
);
291 return &fcpb
->fc_port_luns
[CHAN2BANKPORT(i
)][0];
294 int cxlflash_afu_sync(struct afu
*afu
, ctx_hndl_t c
, res_hndl_t r
, u8 mode
);
295 void cxlflash_list_init(void);
296 void cxlflash_term_global_luns(void);
297 void cxlflash_free_errpage(void);
298 int cxlflash_ioctl(struct scsi_device
*sdev
, int cmd
, void __user
*arg
);
299 void cxlflash_stop_term_user_contexts(struct cxlflash_cfg
*cfg
);
300 int cxlflash_mark_contexts_error(struct cxlflash_cfg
*cfg
);
301 void cxlflash_term_local_luns(struct cxlflash_cfg
*cfg
);
302 void cxlflash_restore_luntable(struct cxlflash_cfg
*cfg
);
304 #endif /* ifndef _CXLFLASH_COMMON_H */