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[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / hisi_sas / hisi_sas_v3_hw.c
1 /*
2 * Copyright (c) 2017 Hisilicon Limited.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11 #include "hisi_sas.h"
12 #define DRV_NAME "hisi_sas_v3_hw"
13
14 /* global registers need init*/
15 #define DLVRY_QUEUE_ENABLE 0x0
16 #define IOST_BASE_ADDR_LO 0x8
17 #define IOST_BASE_ADDR_HI 0xc
18 #define ITCT_BASE_ADDR_LO 0x10
19 #define ITCT_BASE_ADDR_HI 0x14
20 #define IO_BROKEN_MSG_ADDR_LO 0x18
21 #define IO_BROKEN_MSG_ADDR_HI 0x1c
22 #define PHY_CONTEXT 0x20
23 #define PHY_STATE 0x24
24 #define PHY_PORT_NUM_MA 0x28
25 #define PHY_CONN_RATE 0x30
26 #define ITCT_CLR 0x44
27 #define ITCT_CLR_EN_OFF 16
28 #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
29 #define ITCT_DEV_OFF 0
30 #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
31 #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
32 #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
33 #define SATA_INITI_D2H_STORE_ADDR_LO 0x60
34 #define SATA_INITI_D2H_STORE_ADDR_HI 0x64
35 #define CFG_MAX_TAG 0x68
36 #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
37 #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
38 #define HGC_GET_ITV_TIME 0x90
39 #define DEVICE_MSG_WORK_MODE 0x94
40 #define OPENA_WT_CONTI_TIME 0x9c
41 #define I_T_NEXUS_LOSS_TIME 0xa0
42 #define MAX_CON_TIME_LIMIT_TIME 0xa4
43 #define BUS_INACTIVE_LIMIT_TIME 0xa8
44 #define REJECT_TO_OPEN_LIMIT_TIME 0xac
45 #define CFG_AGING_TIME 0xbc
46 #define HGC_DFX_CFG2 0xc0
47 #define CFG_ABT_SET_QUERY_IPTT 0xd4
48 #define CFG_SET_ABORTED_IPTT_OFF 0
49 #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF)
50 #define CFG_SET_ABORTED_EN_OFF 12
51 #define CFG_ABT_SET_IPTT_DONE 0xd8
52 #define CFG_ABT_SET_IPTT_DONE_OFF 0
53 #define HGC_IOMB_PROC1_STATUS 0x104
54 #define CFG_1US_TIMER_TRSH 0xcc
55 #define CHNL_INT_STATUS 0x148
56 #define INT_COAL_EN 0x19c
57 #define OQ_INT_COAL_TIME 0x1a0
58 #define OQ_INT_COAL_CNT 0x1a4
59 #define ENT_INT_COAL_TIME 0x1a8
60 #define ENT_INT_COAL_CNT 0x1ac
61 #define OQ_INT_SRC 0x1b0
62 #define OQ_INT_SRC_MSK 0x1b4
63 #define ENT_INT_SRC1 0x1b8
64 #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
65 #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
66 #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
67 #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
68 #define ENT_INT_SRC2 0x1bc
69 #define ENT_INT_SRC3 0x1c0
70 #define ENT_INT_SRC3_WP_DEPTH_OFF 8
71 #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
72 #define ENT_INT_SRC3_RP_DEPTH_OFF 10
73 #define ENT_INT_SRC3_AXI_OFF 11
74 #define ENT_INT_SRC3_FIFO_OFF 12
75 #define ENT_INT_SRC3_LM_OFF 14
76 #define ENT_INT_SRC3_ITC_INT_OFF 15
77 #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
78 #define ENT_INT_SRC3_ABT_OFF 16
79 #define ENT_INT_SRC_MSK1 0x1c4
80 #define ENT_INT_SRC_MSK2 0x1c8
81 #define ENT_INT_SRC_MSK3 0x1cc
82 #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
83 #define CHNL_PHYUPDOWN_INT_MSK 0x1d0
84 #define CHNL_ENT_INT_MSK 0x1d4
85 #define HGC_COM_INT_MSK 0x1d8
86 #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
87 #define SAS_ECC_INTR 0x1e8
88 #define SAS_ECC_INTR_MSK 0x1ec
89 #define HGC_ERR_STAT_EN 0x238
90 #define DLVRY_Q_0_BASE_ADDR_LO 0x260
91 #define DLVRY_Q_0_BASE_ADDR_HI 0x264
92 #define DLVRY_Q_0_DEPTH 0x268
93 #define DLVRY_Q_0_WR_PTR 0x26c
94 #define DLVRY_Q_0_RD_PTR 0x270
95 #define HYPER_STREAM_ID_EN_CFG 0xc80
96 #define OQ0_INT_SRC_MSK 0xc90
97 #define COMPL_Q_0_BASE_ADDR_LO 0x4e0
98 #define COMPL_Q_0_BASE_ADDR_HI 0x4e4
99 #define COMPL_Q_0_DEPTH 0x4e8
100 #define COMPL_Q_0_WR_PTR 0x4ec
101 #define COMPL_Q_0_RD_PTR 0x4f0
102 #define AWQOS_AWCACHE_CFG 0xc84
103 #define ARQOS_ARCACHE_CFG 0xc88
104
105 /* phy registers requiring init */
106 #define PORT_BASE (0x2000)
107 #define PHY_CFG (PORT_BASE + 0x0)
108 #define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
109 #define PHY_CFG_ENA_OFF 0
110 #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
111 #define PHY_CFG_DC_OPT_OFF 2
112 #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
113 #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
114 #define PHY_CTRL (PORT_BASE + 0x14)
115 #define PHY_CTRL_RESET_OFF 0
116 #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
117 #define SL_CFG (PORT_BASE + 0x84)
118 #define SL_CONTROL (PORT_BASE + 0x94)
119 #define SL_CONTROL_NOTIFY_EN_OFF 0
120 #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
121 #define SL_CTA_OFF 17
122 #define SL_CTA_MSK (0x1 << SL_CTA_OFF)
123 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)
124 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)
125 #define TX_ID_DWORD2 (PORT_BASE + 0xa4)
126 #define TX_ID_DWORD3 (PORT_BASE + 0xa8)
127 #define TX_ID_DWORD4 (PORT_BASE + 0xaC)
128 #define TX_ID_DWORD5 (PORT_BASE + 0xb0)
129 #define TX_ID_DWORD6 (PORT_BASE + 0xb4)
130 #define TXID_AUTO (PORT_BASE + 0xb8)
131 #define CT3_OFF 1
132 #define CT3_MSK (0x1 << CT3_OFF)
133 #define TX_HARDRST_OFF 2
134 #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF)
135 #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
136 #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
137 #define STP_LINK_TIMER (PORT_BASE + 0x120)
138 #define CON_CFG_DRIVER (PORT_BASE + 0x130)
139 #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134)
140 #define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138)
141 #define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c)
142 #define CHL_INT0 (PORT_BASE + 0x1b4)
143 #define CHL_INT0_HOTPLUG_TOUT_OFF 0
144 #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
145 #define CHL_INT0_SL_RX_BCST_ACK_OFF 1
146 #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
147 #define CHL_INT0_SL_PHY_ENABLE_OFF 2
148 #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
149 #define CHL_INT0_NOT_RDY_OFF 4
150 #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
151 #define CHL_INT0_PHY_RDY_OFF 5
152 #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
153 #define CHL_INT1 (PORT_BASE + 0x1b8)
154 #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
155 #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
156 #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
157 #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
158 #define CHL_INT2 (PORT_BASE + 0x1bc)
159 #define CHL_INT0_MSK (PORT_BASE + 0x1c0)
160 #define CHL_INT1_MSK (PORT_BASE + 0x1c4)
161 #define CHL_INT2_MSK (PORT_BASE + 0x1c8)
162 #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
163 #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
164 #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
165 #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
166 #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
167 #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
168 #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
169 #define DMA_TX_STATUS (PORT_BASE + 0x2d0)
170 #define DMA_TX_STATUS_BUSY_OFF 0
171 #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
172 #define DMA_RX_STATUS (PORT_BASE + 0x2e8)
173 #define DMA_RX_STATUS_BUSY_OFF 0
174 #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
175
176 #define DEFAULT_ITCT_HW 2048 /* reset value, not reprogrammed */
177 #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW)
178 #error Max ITCT exceeded
179 #endif
180
181 #define AXI_MASTER_CFG_BASE (0x5000)
182 #define AM_CTRL_GLOBAL (0x0)
183 #define AM_CURR_TRANS_RETURN (0x150)
184
185 #define AM_CFG_MAX_TRANS (0x5010)
186 #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
187 #define AXI_CFG (0x5100)
188 #define AM_ROB_ECC_ERR_ADDR (0x510c)
189 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF 0
190 #define AM_ROB_ECC_ONEBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF)
191 #define AM_ROB_ECC_MULBIT_ERR_ADDR_OFF 8
192 #define AM_ROB_ECC_MULBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_MULBIT_ERR_ADDR_OFF)
193
194 /* HW dma structures */
195 /* Delivery queue header */
196 /* dw0 */
197 #define CMD_HDR_ABORT_FLAG_OFF 0
198 #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
199 #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
200 #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
201 #define CMD_HDR_RESP_REPORT_OFF 5
202 #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
203 #define CMD_HDR_TLR_CTRL_OFF 6
204 #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
205 #define CMD_HDR_PORT_OFF 18
206 #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
207 #define CMD_HDR_PRIORITY_OFF 27
208 #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
209 #define CMD_HDR_CMD_OFF 29
210 #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
211 /* dw1 */
212 #define CMD_HDR_UNCON_CMD_OFF 3
213 #define CMD_HDR_DIR_OFF 5
214 #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
215 #define CMD_HDR_RESET_OFF 7
216 #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
217 #define CMD_HDR_VDTL_OFF 10
218 #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
219 #define CMD_HDR_FRAME_TYPE_OFF 11
220 #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
221 #define CMD_HDR_DEV_ID_OFF 16
222 #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
223 /* dw2 */
224 #define CMD_HDR_CFL_OFF 0
225 #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
226 #define CMD_HDR_NCQ_TAG_OFF 10
227 #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
228 #define CMD_HDR_MRFL_OFF 15
229 #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
230 #define CMD_HDR_SG_MOD_OFF 24
231 #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
232 /* dw3 */
233 #define CMD_HDR_IPTT_OFF 0
234 #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
235 /* dw6 */
236 #define CMD_HDR_DIF_SGL_LEN_OFF 0
237 #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
238 #define CMD_HDR_DATA_SGL_LEN_OFF 16
239 #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
240 /* dw7 */
241 #define CMD_HDR_ADDR_MODE_SEL_OFF 15
242 #define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF)
243 #define CMD_HDR_ABORT_IPTT_OFF 16
244 #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
245
246 /* Completion header */
247 /* dw0 */
248 #define CMPLT_HDR_CMPLT_OFF 0
249 #define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF)
250 #define CMPLT_HDR_ERROR_PHASE_OFF 2
251 #define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF)
252 #define CMPLT_HDR_RSPNS_XFRD_OFF 10
253 #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
254 #define CMPLT_HDR_ERX_OFF 12
255 #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
256 #define CMPLT_HDR_ABORT_STAT_OFF 13
257 #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
258 /* abort_stat */
259 #define STAT_IO_NOT_VALID 0x1
260 #define STAT_IO_NO_DEVICE 0x2
261 #define STAT_IO_COMPLETE 0x3
262 #define STAT_IO_ABORTED 0x4
263 /* dw1 */
264 #define CMPLT_HDR_IPTT_OFF 0
265 #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
266 #define CMPLT_HDR_DEV_ID_OFF 16
267 #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
268 /* dw3 */
269 #define CMPLT_HDR_IO_IN_TARGET_OFF 17
270 #define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF)
271
272 /* ITCT header */
273 /* qw0 */
274 #define ITCT_HDR_DEV_TYPE_OFF 0
275 #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
276 #define ITCT_HDR_VALID_OFF 2
277 #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
278 #define ITCT_HDR_MCR_OFF 5
279 #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
280 #define ITCT_HDR_VLN_OFF 9
281 #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
282 #define ITCT_HDR_SMP_TIMEOUT_OFF 16
283 #define ITCT_HDR_AWT_CONTINUE_OFF 25
284 #define ITCT_HDR_PORT_ID_OFF 28
285 #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
286 /* qw2 */
287 #define ITCT_HDR_INLT_OFF 0
288 #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
289 #define ITCT_HDR_RTOLT_OFF 48
290 #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
291
292 struct hisi_sas_complete_v3_hdr {
293 __le32 dw0;
294 __le32 dw1;
295 __le32 act;
296 __le32 dw3;
297 };
298
299 struct hisi_sas_err_record_v3 {
300 /* dw0 */
301 __le32 trans_tx_fail_type;
302
303 /* dw1 */
304 __le32 trans_rx_fail_type;
305
306 /* dw2 */
307 __le16 dma_tx_err_type;
308 __le16 sipc_rx_err_type;
309
310 /* dw3 */
311 __le32 dma_rx_err_type;
312 };
313
314 #define RX_DATA_LEN_UNDERFLOW_OFF 6
315 #define RX_DATA_LEN_UNDERFLOW_MSK (1 << RX_DATA_LEN_UNDERFLOW_OFF)
316
317 #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096
318 #define HISI_SAS_MSI_COUNT_V3_HW 32
319
320 enum {
321 HISI_SAS_PHY_PHY_UPDOWN,
322 HISI_SAS_PHY_CHNL_INT,
323 HISI_SAS_PHY_INT_NR
324 };
325
326 #define DIR_NO_DATA 0
327 #define DIR_TO_INI 1
328 #define DIR_TO_DEVICE 2
329 #define DIR_RESERVED 3
330
331 #define CMD_IS_UNCONSTRAINT(cmd) \
332 ((cmd == ATA_CMD_READ_LOG_EXT) || \
333 (cmd == ATA_CMD_READ_LOG_DMA_EXT) || \
334 (cmd == ATA_CMD_DEV_RESET))
335
336 static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
337 {
338 void __iomem *regs = hisi_hba->regs + off;
339
340 return readl(regs);
341 }
342
343 static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
344 {
345 void __iomem *regs = hisi_hba->regs + off;
346
347 return readl_relaxed(regs);
348 }
349
350 static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
351 {
352 void __iomem *regs = hisi_hba->regs + off;
353
354 writel(val, regs);
355 }
356
357 static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
358 u32 off, u32 val)
359 {
360 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
361
362 writel(val, regs);
363 }
364
365 static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
366 int phy_no, u32 off)
367 {
368 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
369
370 return readl(regs);
371 }
372
373 static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
374 {
375 int i;
376
377 /* Global registers init */
378 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
379 (u32)((1ULL << hisi_hba->queue_count) - 1));
380 hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400);
381 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
382 hisi_sas_write32(hisi_hba, CFG_1US_TIMER_TRSH, 0xd);
383 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
384 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
385 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
386 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff);
387 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
388 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
389 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
390 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe);
391 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe);
392 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
393 hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0);
394 hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0);
395 hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0);
396 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0x0);
397 hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0);
398 hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0);
399 for (i = 0; i < hisi_hba->queue_count; i++)
400 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
401
402 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
403 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE, 0x30000);
404
405 for (i = 0; i < hisi_hba->n_phy; i++) {
406 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x801);
407 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
408 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
409 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
410 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
411 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
412 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbff);
413 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
414 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
415 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
416 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
417 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
418 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
419 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199b4fa);
420 hisi_sas_phy_write32(hisi_hba, i, SAS_SSP_CON_TIMER_CFG,
421 0xa03e8);
422 hisi_sas_phy_write32(hisi_hba, i, SAS_STP_CON_TIMER_CFG,
423 0xa03e8);
424 hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER,
425 0x7f7a120);
426 hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER,
427 0x2a0a80);
428 }
429 for (i = 0; i < hisi_hba->queue_count; i++) {
430 /* Delivery queue */
431 hisi_sas_write32(hisi_hba,
432 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
433 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
434
435 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
436 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
437
438 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
439 HISI_SAS_QUEUE_SLOTS);
440
441 /* Completion queue */
442 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
443 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
444
445 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
446 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
447
448 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
449 HISI_SAS_QUEUE_SLOTS);
450 }
451
452 /* itct */
453 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
454 lower_32_bits(hisi_hba->itct_dma));
455
456 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
457 upper_32_bits(hisi_hba->itct_dma));
458
459 /* iost */
460 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
461 lower_32_bits(hisi_hba->iost_dma));
462
463 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
464 upper_32_bits(hisi_hba->iost_dma));
465
466 /* breakpoint */
467 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
468 lower_32_bits(hisi_hba->breakpoint_dma));
469
470 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
471 upper_32_bits(hisi_hba->breakpoint_dma));
472
473 /* SATA broken msg */
474 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
475 lower_32_bits(hisi_hba->sata_breakpoint_dma));
476
477 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
478 upper_32_bits(hisi_hba->sata_breakpoint_dma));
479
480 /* SATA initial fis */
481 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
482 lower_32_bits(hisi_hba->initial_fis_dma));
483
484 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
485 upper_32_bits(hisi_hba->initial_fis_dma));
486 }
487
488 static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
489 {
490 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
491
492 cfg &= ~PHY_CFG_DC_OPT_MSK;
493 cfg |= 1 << PHY_CFG_DC_OPT_OFF;
494 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
495 }
496
497 static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
498 {
499 struct sas_identify_frame identify_frame;
500 u32 *identify_buffer;
501
502 memset(&identify_frame, 0, sizeof(identify_frame));
503 identify_frame.dev_type = SAS_END_DEVICE;
504 identify_frame.frame_type = 0;
505 identify_frame._un1 = 1;
506 identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
507 identify_frame.target_bits = SAS_PROTOCOL_NONE;
508 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
509 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
510 identify_frame.phy_id = phy_no;
511 identify_buffer = (u32 *)(&identify_frame);
512
513 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
514 __swab32(identify_buffer[0]));
515 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
516 __swab32(identify_buffer[1]));
517 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
518 __swab32(identify_buffer[2]));
519 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
520 __swab32(identify_buffer[3]));
521 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
522 __swab32(identify_buffer[4]));
523 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
524 __swab32(identify_buffer[5]));
525 }
526
527 static void setup_itct_v3_hw(struct hisi_hba *hisi_hba,
528 struct hisi_sas_device *sas_dev)
529 {
530 struct domain_device *device = sas_dev->sas_device;
531 struct device *dev = hisi_hba->dev;
532 u64 qw0, device_id = sas_dev->device_id;
533 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
534 struct domain_device *parent_dev = device->parent;
535 struct asd_sas_port *sas_port = device->port;
536 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
537
538 memset(itct, 0, sizeof(*itct));
539
540 /* qw0 */
541 qw0 = 0;
542 switch (sas_dev->dev_type) {
543 case SAS_END_DEVICE:
544 case SAS_EDGE_EXPANDER_DEVICE:
545 case SAS_FANOUT_EXPANDER_DEVICE:
546 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
547 break;
548 case SAS_SATA_DEV:
549 case SAS_SATA_PENDING:
550 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
551 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
552 else
553 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
554 break;
555 default:
556 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
557 sas_dev->dev_type);
558 }
559
560 qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
561 (device->linkrate << ITCT_HDR_MCR_OFF) |
562 (1 << ITCT_HDR_VLN_OFF) |
563 (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) |
564 (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
565 (port->id << ITCT_HDR_PORT_ID_OFF));
566 itct->qw0 = cpu_to_le64(qw0);
567
568 /* qw1 */
569 memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
570 itct->sas_addr = __swab64(itct->sas_addr);
571
572 /* qw2 */
573 if (!dev_is_sata(device))
574 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
575 (0x1ULL << ITCT_HDR_RTOLT_OFF));
576 }
577
578 static void free_device_v3_hw(struct hisi_hba *hisi_hba,
579 struct hisi_sas_device *sas_dev)
580 {
581 u64 dev_id = sas_dev->device_id;
582 struct device *dev = hisi_hba->dev;
583 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
584 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
585
586 /* clear the itct interrupt state */
587 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
588 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
589 ENT_INT_SRC3_ITC_INT_MSK);
590
591 /* clear the itct table*/
592 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
593 reg_val |= ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
594 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
595
596 udelay(10);
597 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
598 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) {
599 dev_dbg(dev, "got clear ITCT done interrupt\n");
600
601 /* invalid the itct state*/
602 memset(itct, 0, sizeof(struct hisi_sas_itct));
603 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
604 ENT_INT_SRC3_ITC_INT_MSK);
605
606 /* clear the itct */
607 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
608 dev_dbg(dev, "clear ITCT ok\n");
609 }
610 }
611
612 static void dereg_device_v3_hw(struct hisi_hba *hisi_hba,
613 struct domain_device *device)
614 {
615 struct hisi_sas_slot *slot, *slot2;
616 struct hisi_sas_device *sas_dev = device->lldd_dev;
617 u32 cfg_abt_set_query_iptt;
618
619 cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba,
620 CFG_ABT_SET_QUERY_IPTT);
621 list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) {
622 cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK;
623 cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) |
624 (slot->idx << CFG_SET_ABORTED_IPTT_OFF);
625 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
626 cfg_abt_set_query_iptt);
627 }
628 cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF);
629 hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT,
630 cfg_abt_set_query_iptt);
631 hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE,
632 1 << CFG_ABT_SET_IPTT_DONE_OFF);
633 }
634
635 static int reset_hw_v3_hw(struct hisi_hba *hisi_hba)
636 {
637 struct device *dev = hisi_hba->dev;
638 int ret;
639 u32 val;
640
641 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
642
643 /* Disable all of the PHYs */
644 hisi_sas_stop_phys(hisi_hba);
645 udelay(50);
646
647 /* Ensure axi bus idle */
648 ret = readl_poll_timeout(hisi_hba->regs + AXI_CFG, val, !val,
649 20000, 1000000);
650 if (ret) {
651 dev_err(dev, "axi bus is not idle, ret = %d!\n", ret);
652 return -EIO;
653 }
654
655 if (ACPI_HANDLE(dev)) {
656 acpi_status s;
657
658 s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL);
659 if (ACPI_FAILURE(s)) {
660 dev_err(dev, "Reset failed\n");
661 return -EIO;
662 }
663 } else
664 dev_err(dev, "no reset method!\n");
665
666 return 0;
667 }
668
669 static int hw_init_v3_hw(struct hisi_hba *hisi_hba)
670 {
671 struct device *dev = hisi_hba->dev;
672 int rc;
673
674 rc = reset_hw_v3_hw(hisi_hba);
675 if (rc) {
676 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
677 return rc;
678 }
679
680 msleep(100);
681 init_reg_v3_hw(hisi_hba);
682
683 return 0;
684 }
685
686 static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
687 {
688 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
689
690 cfg |= PHY_CFG_ENA_MSK;
691 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
692 }
693
694 static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
695 {
696 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
697
698 cfg &= ~PHY_CFG_ENA_MSK;
699 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
700 }
701
702 static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
703 {
704 config_id_frame_v3_hw(hisi_hba, phy_no);
705 config_phy_opt_mode_v3_hw(hisi_hba, phy_no);
706 enable_phy_v3_hw(hisi_hba, phy_no);
707 }
708
709 static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
710 {
711 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
712 u32 txid_auto;
713
714 disable_phy_v3_hw(hisi_hba, phy_no);
715 if (phy->identify.device_type == SAS_END_DEVICE) {
716 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
717 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
718 txid_auto | TX_HARDRST_MSK);
719 }
720 msleep(100);
721 start_phy_v3_hw(hisi_hba, phy_no);
722 }
723
724 enum sas_linkrate phy_get_max_linkrate_v3_hw(void)
725 {
726 return SAS_LINK_RATE_12_0_GBPS;
727 }
728
729 static void phys_init_v3_hw(struct hisi_hba *hisi_hba)
730 {
731 int i;
732
733 for (i = 0; i < hisi_hba->n_phy; i++) {
734 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
735 struct asd_sas_phy *sas_phy = &phy->sas_phy;
736
737 if (!sas_phy->phy->enabled)
738 continue;
739
740 start_phy_v3_hw(hisi_hba, i);
741 }
742 }
743
744 static void sl_notify_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
745 {
746 u32 sl_control;
747
748 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
749 sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
750 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
751 msleep(1);
752 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
753 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
754 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
755 }
756
757 static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id)
758 {
759 int i, bitmap = 0;
760 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
761 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
762
763 for (i = 0; i < hisi_hba->n_phy; i++)
764 if (phy_state & BIT(i))
765 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
766 bitmap |= BIT(i);
767
768 return bitmap;
769 }
770
771 /**
772 * The callpath to this function and upto writing the write
773 * queue pointer should be safe from interruption.
774 */
775 static int
776 get_free_slot_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
777 {
778 struct device *dev = hisi_hba->dev;
779 int queue = dq->id;
780 u32 r, w;
781
782 w = dq->wr_point;
783 r = hisi_sas_read32_relaxed(hisi_hba,
784 DLVRY_Q_0_RD_PTR + (queue * 0x14));
785 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
786 dev_warn(dev, "full queue=%d r=%d w=%d\n\n",
787 queue, r, w);
788 return -EAGAIN;
789 }
790
791 return 0;
792 }
793
794 static void start_delivery_v3_hw(struct hisi_sas_dq *dq)
795 {
796 struct hisi_hba *hisi_hba = dq->hisi_hba;
797 int dlvry_queue = dq->slot_prep->dlvry_queue;
798 int dlvry_queue_slot = dq->slot_prep->dlvry_queue_slot;
799
800 dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS;
801 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14),
802 dq->wr_point);
803 }
804
805 static int prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba,
806 struct hisi_sas_slot *slot,
807 struct hisi_sas_cmd_hdr *hdr,
808 struct scatterlist *scatter,
809 int n_elem)
810 {
811 struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot);
812 struct device *dev = hisi_hba->dev;
813 struct scatterlist *sg;
814 int i;
815
816 if (n_elem > HISI_SAS_SGE_PAGE_CNT) {
817 dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
818 n_elem);
819 return -EINVAL;
820 }
821
822 for_each_sg(scatter, sg, n_elem, i) {
823 struct hisi_sas_sge *entry = &sge_page->sge[i];
824
825 entry->addr = cpu_to_le64(sg_dma_address(sg));
826 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
827 entry->data_len = cpu_to_le32(sg_dma_len(sg));
828 entry->data_off = 0;
829 }
830
831 hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot));
832
833 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
834
835 return 0;
836 }
837
838 static int prep_ssp_v3_hw(struct hisi_hba *hisi_hba,
839 struct hisi_sas_slot *slot, int is_tmf,
840 struct hisi_sas_tmf_task *tmf)
841 {
842 struct sas_task *task = slot->task;
843 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
844 struct domain_device *device = task->dev;
845 struct hisi_sas_device *sas_dev = device->lldd_dev;
846 struct hisi_sas_port *port = slot->port;
847 struct sas_ssp_task *ssp_task = &task->ssp_task;
848 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
849 int has_data = 0, rc, priority = is_tmf;
850 u8 *buf_cmd;
851 u32 dw1 = 0, dw2 = 0;
852
853 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
854 (2 << CMD_HDR_TLR_CTRL_OFF) |
855 (port->id << CMD_HDR_PORT_OFF) |
856 (priority << CMD_HDR_PRIORITY_OFF) |
857 (1 << CMD_HDR_CMD_OFF)); /* ssp */
858
859 dw1 = 1 << CMD_HDR_VDTL_OFF;
860 if (is_tmf) {
861 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
862 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
863 } else {
864 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
865 switch (scsi_cmnd->sc_data_direction) {
866 case DMA_TO_DEVICE:
867 has_data = 1;
868 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
869 break;
870 case DMA_FROM_DEVICE:
871 has_data = 1;
872 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
873 break;
874 default:
875 dw1 &= ~CMD_HDR_DIR_MSK;
876 }
877 }
878
879 /* map itct entry */
880 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
881 hdr->dw1 = cpu_to_le32(dw1);
882
883 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
884 + 3) / 4) << CMD_HDR_CFL_OFF) |
885 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
886 (2 << CMD_HDR_SG_MOD_OFF);
887 hdr->dw2 = cpu_to_le32(dw2);
888 hdr->transfer_tags = cpu_to_le32(slot->idx);
889
890 if (has_data) {
891 rc = prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
892 slot->n_elem);
893 if (rc)
894 return rc;
895 }
896
897 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
898 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
899 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
900
901 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) +
902 sizeof(struct ssp_frame_hdr);
903
904 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
905 if (!is_tmf) {
906 buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3);
907 memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len);
908 } else {
909 buf_cmd[10] = tmf->tmf;
910 switch (tmf->tmf) {
911 case TMF_ABORT_TASK:
912 case TMF_QUERY_TASK:
913 buf_cmd[12] =
914 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
915 buf_cmd[13] =
916 tmf->tag_of_task_to_be_managed & 0xff;
917 break;
918 default:
919 break;
920 }
921 }
922
923 return 0;
924 }
925
926 static int prep_smp_v3_hw(struct hisi_hba *hisi_hba,
927 struct hisi_sas_slot *slot)
928 {
929 struct sas_task *task = slot->task;
930 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
931 struct domain_device *device = task->dev;
932 struct device *dev = hisi_hba->dev;
933 struct hisi_sas_port *port = slot->port;
934 struct scatterlist *sg_req, *sg_resp;
935 struct hisi_sas_device *sas_dev = device->lldd_dev;
936 dma_addr_t req_dma_addr;
937 unsigned int req_len, resp_len;
938 int elem, rc;
939
940 /*
941 * DMA-map SMP request, response buffers
942 */
943 /* req */
944 sg_req = &task->smp_task.smp_req;
945 elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE);
946 if (!elem)
947 return -ENOMEM;
948 req_len = sg_dma_len(sg_req);
949 req_dma_addr = sg_dma_address(sg_req);
950
951 /* resp */
952 sg_resp = &task->smp_task.smp_resp;
953 elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE);
954 if (!elem) {
955 rc = -ENOMEM;
956 goto err_out_req;
957 }
958 resp_len = sg_dma_len(sg_resp);
959 if ((req_len & 0x3) || (resp_len & 0x3)) {
960 rc = -EINVAL;
961 goto err_out_resp;
962 }
963
964 /* create header */
965 /* dw0 */
966 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
967 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
968 (2 << CMD_HDR_CMD_OFF)); /* smp */
969
970 /* map itct entry */
971 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
972 (1 << CMD_HDR_FRAME_TYPE_OFF) |
973 (DIR_NO_DATA << CMD_HDR_DIR_OFF));
974
975 /* dw2 */
976 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
977 (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
978 CMD_HDR_MRFL_OFF));
979
980 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
981
982 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
983 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
984
985 return 0;
986
987 err_out_resp:
988 dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1,
989 DMA_FROM_DEVICE);
990 err_out_req:
991 dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1,
992 DMA_TO_DEVICE);
993 return rc;
994 }
995
996 static int prep_ata_v3_hw(struct hisi_hba *hisi_hba,
997 struct hisi_sas_slot *slot)
998 {
999 struct sas_task *task = slot->task;
1000 struct domain_device *device = task->dev;
1001 struct domain_device *parent_dev = device->parent;
1002 struct hisi_sas_device *sas_dev = device->lldd_dev;
1003 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1004 struct asd_sas_port *sas_port = device->port;
1005 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
1006 u8 *buf_cmd;
1007 int has_data = 0, rc = 0, hdr_tag = 0;
1008 u32 dw1 = 0, dw2 = 0;
1009
1010 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
1011 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
1012 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
1013 else
1014 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
1015
1016 switch (task->data_dir) {
1017 case DMA_TO_DEVICE:
1018 has_data = 1;
1019 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
1020 break;
1021 case DMA_FROM_DEVICE:
1022 has_data = 1;
1023 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
1024 break;
1025 default:
1026 dw1 &= ~CMD_HDR_DIR_MSK;
1027 }
1028
1029 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
1030 (task->ata_task.fis.control & ATA_SRST))
1031 dw1 |= 1 << CMD_HDR_RESET_OFF;
1032
1033 dw1 |= (hisi_sas_get_ata_protocol(
1034 task->ata_task.fis.command, task->data_dir))
1035 << CMD_HDR_FRAME_TYPE_OFF;
1036 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
1037
1038 if (CMD_IS_UNCONSTRAINT(task->ata_task.fis.command))
1039 dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF;
1040
1041 hdr->dw1 = cpu_to_le32(dw1);
1042
1043 /* dw2 */
1044 if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) {
1045 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
1046 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
1047 }
1048
1049 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
1050 2 << CMD_HDR_SG_MOD_OFF;
1051 hdr->dw2 = cpu_to_le32(dw2);
1052
1053 /* dw3 */
1054 hdr->transfer_tags = cpu_to_le32(slot->idx);
1055
1056 if (has_data) {
1057 rc = prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
1058 slot->n_elem);
1059 if (rc)
1060 return rc;
1061 }
1062
1063 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
1064 hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot));
1065 hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot));
1066
1067 buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot);
1068
1069 if (likely(!task->ata_task.device_control_reg_update))
1070 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
1071 /* fill in command FIS */
1072 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
1073
1074 return 0;
1075 }
1076
1077 static int prep_abort_v3_hw(struct hisi_hba *hisi_hba,
1078 struct hisi_sas_slot *slot,
1079 int device_id, int abort_flag, int tag_to_abort)
1080 {
1081 struct sas_task *task = slot->task;
1082 struct domain_device *dev = task->dev;
1083 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
1084 struct hisi_sas_port *port = slot->port;
1085
1086 /* dw0 */
1087 hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/
1088 (port->id << CMD_HDR_PORT_OFF) |
1089 ((dev_is_sata(dev) ? 1:0)
1090 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
1091 (abort_flag
1092 << CMD_HDR_ABORT_FLAG_OFF));
1093
1094 /* dw1 */
1095 hdr->dw1 = cpu_to_le32(device_id
1096 << CMD_HDR_DEV_ID_OFF);
1097
1098 /* dw7 */
1099 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
1100 hdr->transfer_tags = cpu_to_le32(slot->idx);
1101
1102 return 0;
1103 }
1104
1105 static int phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1106 {
1107 int i, res = 0;
1108 u32 context, port_id, link_rate, hard_phy_linkrate;
1109 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1110 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1111 struct device *dev = hisi_hba->dev;
1112
1113 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
1114
1115 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1116 port_id = (port_id >> (4 * phy_no)) & 0xf;
1117 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1118 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1119
1120 if (port_id == 0xf) {
1121 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
1122 res = IRQ_NONE;
1123 goto end;
1124 }
1125 sas_phy->linkrate = link_rate;
1126 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
1127 HARD_PHY_LINKRATE);
1128 phy->maximum_linkrate = hard_phy_linkrate & 0xf;
1129 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
1130 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1131
1132 /* Check for SATA dev */
1133 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1134 if (context & (1 << phy_no)) {
1135 struct hisi_sas_initial_fis *initial_fis;
1136 struct dev_to_host_fis *fis;
1137 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
1138
1139 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
1140 initial_fis = &hisi_hba->initial_fis[phy_no];
1141 fis = &initial_fis->fis;
1142 sas_phy->oob_mode = SATA_OOB_MODE;
1143 attached_sas_addr[0] = 0x50;
1144 attached_sas_addr[7] = phy_no;
1145 memcpy(sas_phy->attached_sas_addr,
1146 attached_sas_addr,
1147 SAS_ADDR_SIZE);
1148 memcpy(sas_phy->frame_rcvd, fis,
1149 sizeof(struct dev_to_host_fis));
1150 phy->phy_type |= PORT_TYPE_SATA;
1151 phy->identify.device_type = SAS_SATA_DEV;
1152 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
1153 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
1154 } else {
1155 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
1156 struct sas_identify_frame *id =
1157 (struct sas_identify_frame *)frame_rcvd;
1158
1159 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
1160 for (i = 0; i < 6; i++) {
1161 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
1162 RX_IDAF_DWORD0 + (i * 4));
1163 frame_rcvd[i] = __swab32(idaf);
1164 }
1165 sas_phy->oob_mode = SAS_OOB_MODE;
1166 memcpy(sas_phy->attached_sas_addr,
1167 &id->sas_addr,
1168 SAS_ADDR_SIZE);
1169 phy->phy_type |= PORT_TYPE_SAS;
1170 phy->identify.device_type = id->dev_type;
1171 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
1172 if (phy->identify.device_type == SAS_END_DEVICE)
1173 phy->identify.target_port_protocols =
1174 SAS_PROTOCOL_SSP;
1175 else if (phy->identify.device_type != SAS_PHY_UNUSED)
1176 phy->identify.target_port_protocols =
1177 SAS_PROTOCOL_SMP;
1178 }
1179
1180 phy->port_id = port_id;
1181 phy->phy_attached = 1;
1182 queue_work(hisi_hba->wq, &phy->phyup_ws);
1183
1184 end:
1185 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1186 CHL_INT0_SL_PHY_ENABLE_MSK);
1187 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
1188
1189 return res;
1190 }
1191
1192 static int phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1193 {
1194 u32 phy_state, sl_ctrl, txid_auto;
1195 struct device *dev = hisi_hba->dev;
1196
1197 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
1198
1199 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1200 dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
1201 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
1202
1203 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1204 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
1205 sl_ctrl&(~SL_CTA_MSK));
1206
1207 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1208 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1209 txid_auto | CT3_MSK);
1210
1211 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
1212 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
1213
1214 return 0;
1215 }
1216
1217 static void phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1218 {
1219 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1220 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1221 struct sas_ha_struct *sas_ha = &hisi_hba->sha;
1222
1223 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
1224 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
1225 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1226 CHL_INT0_SL_RX_BCST_ACK_MSK);
1227 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
1228 }
1229
1230 static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p)
1231 {
1232 struct hisi_hba *hisi_hba = p;
1233 u32 irq_msk;
1234 int phy_no = 0;
1235 irqreturn_t res = IRQ_NONE;
1236
1237 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1238 & 0x11111111;
1239 while (irq_msk) {
1240 if (irq_msk & 1) {
1241 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1242 CHL_INT0);
1243 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1244 int rdy = phy_state & (1 << phy_no);
1245
1246 if (rdy) {
1247 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK)
1248 /* phy up */
1249 if (phy_up_v3_hw(phy_no, hisi_hba)
1250 == IRQ_HANDLED)
1251 res = IRQ_HANDLED;
1252 if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK)
1253 /* phy bcast */
1254 phy_bcast_v3_hw(phy_no, hisi_hba);
1255 } else {
1256 if (irq_value & CHL_INT0_NOT_RDY_MSK)
1257 /* phy down */
1258 if (phy_down_v3_hw(phy_no, hisi_hba)
1259 == IRQ_HANDLED)
1260 res = IRQ_HANDLED;
1261 }
1262 }
1263 irq_msk >>= 4;
1264 phy_no++;
1265 }
1266
1267 return res;
1268 }
1269
1270 static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p)
1271 {
1272 struct hisi_hba *hisi_hba = p;
1273 struct device *dev = hisi_hba->dev;
1274 u32 ent_msk, ent_tmp, irq_msk;
1275 int phy_no = 0;
1276
1277 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
1278 ent_tmp = ent_msk;
1279 ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK;
1280 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk);
1281
1282 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1283 & 0xeeeeeeee;
1284
1285 while (irq_msk) {
1286 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
1287 CHL_INT0);
1288 u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
1289 CHL_INT1);
1290 u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
1291 CHL_INT2);
1292
1293 if ((irq_msk & (4 << (phy_no * 4))) &&
1294 irq_value1) {
1295 if (irq_value1 & (CHL_INT1_DMAC_RX_ECC_ERR_MSK |
1296 CHL_INT1_DMAC_TX_ECC_ERR_MSK))
1297 panic("%s: DMAC RX/TX ecc bad error! (0x%x)",
1298 dev_name(dev), irq_value1);
1299
1300 hisi_sas_phy_write32(hisi_hba, phy_no,
1301 CHL_INT1, irq_value1);
1302 }
1303
1304 if (irq_msk & (8 << (phy_no * 4)) && irq_value2)
1305 hisi_sas_phy_write32(hisi_hba, phy_no,
1306 CHL_INT2, irq_value2);
1307
1308
1309 if (irq_msk & (2 << (phy_no * 4)) && irq_value0) {
1310 hisi_sas_phy_write32(hisi_hba, phy_no,
1311 CHL_INT0, irq_value0
1312 & (~CHL_INT0_SL_RX_BCST_ACK_MSK)
1313 & (~CHL_INT0_SL_PHY_ENABLE_MSK)
1314 & (~CHL_INT0_NOT_RDY_MSK));
1315 }
1316 irq_msk &= ~(0xe << (phy_no * 4));
1317 phy_no++;
1318 }
1319
1320 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp);
1321
1322 return IRQ_HANDLED;
1323 }
1324
1325 static void
1326 slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task,
1327 struct hisi_sas_slot *slot)
1328 {
1329 struct task_status_struct *ts = &task->task_status;
1330 struct hisi_sas_complete_v3_hdr *complete_queue =
1331 hisi_hba->complete_hdr[slot->cmplt_queue];
1332 struct hisi_sas_complete_v3_hdr *complete_hdr =
1333 &complete_queue[slot->cmplt_queue_slot];
1334 struct hisi_sas_err_record_v3 *record =
1335 hisi_sas_status_buf_addr_mem(slot);
1336 u32 dma_rx_err_type = record->dma_rx_err_type;
1337 u32 trans_tx_fail_type = record->trans_tx_fail_type;
1338
1339 switch (task->task_proto) {
1340 case SAS_PROTOCOL_SSP:
1341 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
1342 ts->residual = trans_tx_fail_type;
1343 ts->stat = SAS_DATA_UNDERRUN;
1344 } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
1345 ts->stat = SAS_QUEUE_FULL;
1346 slot->abort = 1;
1347 } else {
1348 ts->stat = SAS_OPEN_REJECT;
1349 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1350 }
1351 break;
1352 case SAS_PROTOCOL_SATA:
1353 case SAS_PROTOCOL_STP:
1354 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1355 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
1356 ts->residual = trans_tx_fail_type;
1357 ts->stat = SAS_DATA_UNDERRUN;
1358 } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
1359 ts->stat = SAS_PHY_DOWN;
1360 slot->abort = 1;
1361 } else {
1362 ts->stat = SAS_OPEN_REJECT;
1363 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1364 }
1365 hisi_sas_sata_done(task, slot);
1366 break;
1367 case SAS_PROTOCOL_SMP:
1368 ts->stat = SAM_STAT_CHECK_CONDITION;
1369 break;
1370 default:
1371 break;
1372 }
1373 }
1374
1375 static int
1376 slot_complete_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot)
1377 {
1378 struct sas_task *task = slot->task;
1379 struct hisi_sas_device *sas_dev;
1380 struct device *dev = hisi_hba->dev;
1381 struct task_status_struct *ts;
1382 struct domain_device *device;
1383 enum exec_status sts;
1384 struct hisi_sas_complete_v3_hdr *complete_queue =
1385 hisi_hba->complete_hdr[slot->cmplt_queue];
1386 struct hisi_sas_complete_v3_hdr *complete_hdr =
1387 &complete_queue[slot->cmplt_queue_slot];
1388 int aborted;
1389 unsigned long flags;
1390
1391 if (unlikely(!task || !task->lldd_task || !task->dev))
1392 return -EINVAL;
1393
1394 ts = &task->task_status;
1395 device = task->dev;
1396 sas_dev = device->lldd_dev;
1397
1398 spin_lock_irqsave(&task->task_state_lock, flags);
1399 aborted = task->task_state_flags & SAS_TASK_STATE_ABORTED;
1400 task->task_state_flags &=
1401 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
1402 spin_unlock_irqrestore(&task->task_state_lock, flags);
1403
1404 memset(ts, 0, sizeof(*ts));
1405 ts->resp = SAS_TASK_COMPLETE;
1406 if (unlikely(aborted)) {
1407 ts->stat = SAS_ABORTED_TASK;
1408 spin_lock_irqsave(&hisi_hba->lock, flags);
1409 hisi_sas_slot_task_free(hisi_hba, task, slot);
1410 spin_unlock_irqrestore(&hisi_hba->lock, flags);
1411 return -1;
1412 }
1413
1414 if (unlikely(!sas_dev)) {
1415 dev_dbg(dev, "slot complete: port has not device\n");
1416 ts->stat = SAS_PHY_DOWN;
1417 goto out;
1418 }
1419
1420 /*
1421 * Use SAS+TMF status codes
1422 */
1423 switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK)
1424 >> CMPLT_HDR_ABORT_STAT_OFF) {
1425 case STAT_IO_ABORTED:
1426 /* this IO has been aborted by abort command */
1427 ts->stat = SAS_ABORTED_TASK;
1428 goto out;
1429 case STAT_IO_COMPLETE:
1430 /* internal abort command complete */
1431 ts->stat = TMF_RESP_FUNC_SUCC;
1432 goto out;
1433 case STAT_IO_NO_DEVICE:
1434 ts->stat = TMF_RESP_FUNC_COMPLETE;
1435 goto out;
1436 case STAT_IO_NOT_VALID:
1437 /*
1438 * abort single IO, the controller can't find the IO
1439 */
1440 ts->stat = TMF_RESP_FUNC_FAILED;
1441 goto out;
1442 default:
1443 break;
1444 }
1445
1446 /* check for erroneous completion */
1447 if ((complete_hdr->dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) {
1448 slot_err_v3_hw(hisi_hba, task, slot);
1449 if (unlikely(slot->abort))
1450 return ts->stat;
1451 goto out;
1452 }
1453
1454 switch (task->task_proto) {
1455 case SAS_PROTOCOL_SSP: {
1456 struct ssp_response_iu *iu =
1457 hisi_sas_status_buf_addr_mem(slot) +
1458 sizeof(struct hisi_sas_err_record);
1459
1460 sas_ssp_task_response(dev, task, iu);
1461 break;
1462 }
1463 case SAS_PROTOCOL_SMP: {
1464 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
1465 void *to;
1466
1467 ts->stat = SAM_STAT_GOOD;
1468 to = kmap_atomic(sg_page(sg_resp));
1469
1470 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
1471 DMA_FROM_DEVICE);
1472 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
1473 DMA_TO_DEVICE);
1474 memcpy(to + sg_resp->offset,
1475 hisi_sas_status_buf_addr_mem(slot) +
1476 sizeof(struct hisi_sas_err_record),
1477 sg_dma_len(sg_resp));
1478 kunmap_atomic(to);
1479 break;
1480 }
1481 case SAS_PROTOCOL_SATA:
1482 case SAS_PROTOCOL_STP:
1483 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1484 ts->stat = SAM_STAT_GOOD;
1485 hisi_sas_sata_done(task, slot);
1486 break;
1487 default:
1488 ts->stat = SAM_STAT_CHECK_CONDITION;
1489 break;
1490 }
1491
1492 if (!slot->port->port_attached) {
1493 dev_err(dev, "slot complete: port %d has removed\n",
1494 slot->port->sas_port.id);
1495 ts->stat = SAS_PHY_DOWN;
1496 }
1497
1498 out:
1499 spin_lock_irqsave(&task->task_state_lock, flags);
1500 task->task_state_flags |= SAS_TASK_STATE_DONE;
1501 spin_unlock_irqrestore(&task->task_state_lock, flags);
1502 spin_lock_irqsave(&hisi_hba->lock, flags);
1503 hisi_sas_slot_task_free(hisi_hba, task, slot);
1504 spin_unlock_irqrestore(&hisi_hba->lock, flags);
1505 sts = ts->stat;
1506
1507 if (task->task_done)
1508 task->task_done(task);
1509
1510 return sts;
1511 }
1512
1513 static void cq_tasklet_v3_hw(unsigned long val)
1514 {
1515 struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val;
1516 struct hisi_hba *hisi_hba = cq->hisi_hba;
1517 struct hisi_sas_slot *slot;
1518 struct hisi_sas_itct *itct;
1519 struct hisi_sas_complete_v3_hdr *complete_queue;
1520 u32 rd_point = cq->rd_point, wr_point, dev_id;
1521 int queue = cq->id;
1522 struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
1523
1524 complete_queue = hisi_hba->complete_hdr[queue];
1525
1526 spin_lock(&dq->lock);
1527 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
1528 (0x14 * queue));
1529
1530 while (rd_point != wr_point) {
1531 struct hisi_sas_complete_v3_hdr *complete_hdr;
1532 int iptt;
1533
1534 complete_hdr = &complete_queue[rd_point];
1535
1536 /* Check for NCQ completion */
1537 if (complete_hdr->act) {
1538 u32 act_tmp = complete_hdr->act;
1539 int ncq_tag_count = ffs(act_tmp);
1540
1541 dev_id = (complete_hdr->dw1 & CMPLT_HDR_DEV_ID_MSK) >>
1542 CMPLT_HDR_DEV_ID_OFF;
1543 itct = &hisi_hba->itct[dev_id];
1544
1545 /* The NCQ tags are held in the itct header */
1546 while (ncq_tag_count) {
1547 __le64 *ncq_tag = &itct->qw4_15[0];
1548
1549 ncq_tag_count -= 1;
1550 iptt = (ncq_tag[ncq_tag_count / 5]
1551 >> (ncq_tag_count % 5) * 12) & 0xfff;
1552
1553 slot = &hisi_hba->slot_info[iptt];
1554 slot->cmplt_queue_slot = rd_point;
1555 slot->cmplt_queue = queue;
1556 slot_complete_v3_hw(hisi_hba, slot);
1557
1558 act_tmp &= ~(1 << ncq_tag_count);
1559 ncq_tag_count = ffs(act_tmp);
1560 }
1561 } else {
1562 iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
1563 slot = &hisi_hba->slot_info[iptt];
1564 slot->cmplt_queue_slot = rd_point;
1565 slot->cmplt_queue = queue;
1566 slot_complete_v3_hw(hisi_hba, slot);
1567 }
1568
1569 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
1570 rd_point = 0;
1571 }
1572
1573 /* update rd_point */
1574 cq->rd_point = rd_point;
1575 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
1576 spin_unlock(&dq->lock);
1577 }
1578
1579 static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p)
1580 {
1581 struct hisi_sas_cq *cq = p;
1582 struct hisi_hba *hisi_hba = cq->hisi_hba;
1583 int queue = cq->id;
1584
1585 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
1586
1587 tasklet_schedule(&cq->tasklet);
1588
1589 return IRQ_HANDLED;
1590 }
1591
1592 static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba)
1593 {
1594 struct device *dev = hisi_hba->dev;
1595 struct pci_dev *pdev = hisi_hba->pci_dev;
1596 int vectors, rc;
1597 int i, k;
1598 int max_msi = HISI_SAS_MSI_COUNT_V3_HW;
1599
1600 vectors = pci_alloc_irq_vectors(hisi_hba->pci_dev, 1,
1601 max_msi, PCI_IRQ_MSI);
1602 if (vectors < max_msi) {
1603 dev_err(dev, "could not allocate all msi (%d)\n", vectors);
1604 return -ENOENT;
1605 }
1606
1607 rc = devm_request_irq(dev, pci_irq_vector(pdev, 1),
1608 int_phy_up_down_bcast_v3_hw, 0,
1609 DRV_NAME " phy", hisi_hba);
1610 if (rc) {
1611 dev_err(dev, "could not request phy interrupt, rc=%d\n", rc);
1612 rc = -ENOENT;
1613 goto free_irq_vectors;
1614 }
1615
1616 rc = devm_request_irq(dev, pci_irq_vector(pdev, 2),
1617 int_chnl_int_v3_hw, 0,
1618 DRV_NAME " channel", hisi_hba);
1619 if (rc) {
1620 dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc);
1621 rc = -ENOENT;
1622 goto free_phy_irq;
1623 }
1624
1625 /* Init tasklets for cq only */
1626 for (i = 0; i < hisi_hba->queue_count; i++) {
1627 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
1628 struct tasklet_struct *t = &cq->tasklet;
1629
1630 rc = devm_request_irq(dev, pci_irq_vector(pdev, i+16),
1631 cq_interrupt_v3_hw, 0,
1632 DRV_NAME " cq", cq);
1633 if (rc) {
1634 dev_err(dev,
1635 "could not request cq%d interrupt, rc=%d\n",
1636 i, rc);
1637 rc = -ENOENT;
1638 goto free_cq_irqs;
1639 }
1640
1641 tasklet_init(t, cq_tasklet_v3_hw, (unsigned long)cq);
1642 }
1643
1644 return 0;
1645
1646 free_cq_irqs:
1647 for (k = 0; k < i; k++) {
1648 struct hisi_sas_cq *cq = &hisi_hba->cq[k];
1649
1650 free_irq(pci_irq_vector(pdev, k+16), cq);
1651 }
1652 free_irq(pci_irq_vector(pdev, 2), hisi_hba);
1653 free_phy_irq:
1654 free_irq(pci_irq_vector(pdev, 1), hisi_hba);
1655 free_irq_vectors:
1656 pci_free_irq_vectors(pdev);
1657 return rc;
1658 }
1659
1660 static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
1661 {
1662 int rc;
1663
1664 rc = hw_init_v3_hw(hisi_hba);
1665 if (rc)
1666 return rc;
1667
1668 rc = interrupt_init_v3_hw(hisi_hba);
1669 if (rc)
1670 return rc;
1671
1672 return 0;
1673 }
1674
1675 static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no,
1676 struct sas_phy_linkrates *r)
1677 {
1678 u32 prog_phy_link_rate =
1679 hisi_sas_phy_read32(hisi_hba, phy_no, PROG_PHY_LINK_RATE);
1680 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1681 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1682 int i;
1683 enum sas_linkrate min, max;
1684 u32 rate_mask = 0;
1685
1686 if (r->maximum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1687 max = sas_phy->phy->maximum_linkrate;
1688 min = r->minimum_linkrate;
1689 } else if (r->minimum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1690 max = r->maximum_linkrate;
1691 min = sas_phy->phy->minimum_linkrate;
1692 } else
1693 return;
1694
1695 sas_phy->phy->maximum_linkrate = max;
1696 sas_phy->phy->minimum_linkrate = min;
1697
1698 min -= SAS_LINK_RATE_1_5_GBPS;
1699 max -= SAS_LINK_RATE_1_5_GBPS;
1700
1701 for (i = 0; i <= max; i++)
1702 rate_mask |= 1 << (i * 2);
1703
1704 prog_phy_link_rate &= ~0xff;
1705 prog_phy_link_rate |= rate_mask;
1706
1707 hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE,
1708 prog_phy_link_rate);
1709
1710 phy_hard_reset_v3_hw(hisi_hba, phy_no);
1711 }
1712
1713 static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba)
1714 {
1715 struct pci_dev *pdev = hisi_hba->pci_dev;
1716 int i;
1717
1718 synchronize_irq(pci_irq_vector(pdev, 1));
1719 synchronize_irq(pci_irq_vector(pdev, 2));
1720 synchronize_irq(pci_irq_vector(pdev, 11));
1721 for (i = 0; i < hisi_hba->queue_count; i++) {
1722 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1);
1723 synchronize_irq(pci_irq_vector(pdev, i + 16));
1724 }
1725
1726 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff);
1727 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff);
1728 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
1729 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff);
1730
1731 for (i = 0; i < hisi_hba->n_phy; i++) {
1732 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
1733 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff);
1734 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x1);
1735 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x1);
1736 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x1);
1737 }
1738 }
1739
1740 static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba)
1741 {
1742 return hisi_sas_read32(hisi_hba, PHY_STATE);
1743 }
1744
1745 static int soft_reset_v3_hw(struct hisi_hba *hisi_hba)
1746 {
1747 struct device *dev = hisi_hba->dev;
1748 int rc;
1749 u32 status;
1750
1751 interrupt_disable_v3_hw(hisi_hba);
1752 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0);
1753
1754 hisi_sas_stop_phys(hisi_hba);
1755
1756 mdelay(10);
1757
1758 hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + AM_CTRL_GLOBAL, 0x1);
1759
1760 /* wait until bus idle */
1761 rc = readl_poll_timeout(hisi_hba->regs + AXI_MASTER_CFG_BASE +
1762 AM_CURR_TRANS_RETURN, status, status == 0x3, 10, 100);
1763 if (rc) {
1764 dev_err(dev, "axi bus is not idle, rc = %d\n", rc);
1765 return rc;
1766 }
1767
1768 hisi_sas_init_mem(hisi_hba);
1769
1770 return hw_init_v3_hw(hisi_hba);
1771 }
1772
1773 static const struct hisi_sas_hw hisi_sas_v3_hw = {
1774 .hw_init = hisi_sas_v3_init,
1775 .setup_itct = setup_itct_v3_hw,
1776 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW,
1777 .get_wideport_bitmap = get_wideport_bitmap_v3_hw,
1778 .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
1779 .free_device = free_device_v3_hw,
1780 .sl_notify = sl_notify_v3_hw,
1781 .prep_ssp = prep_ssp_v3_hw,
1782 .prep_smp = prep_smp_v3_hw,
1783 .prep_stp = prep_ata_v3_hw,
1784 .prep_abort = prep_abort_v3_hw,
1785 .get_free_slot = get_free_slot_v3_hw,
1786 .start_delivery = start_delivery_v3_hw,
1787 .slot_complete = slot_complete_v3_hw,
1788 .phys_init = phys_init_v3_hw,
1789 .phy_start = start_phy_v3_hw,
1790 .phy_disable = disable_phy_v3_hw,
1791 .phy_hard_reset = phy_hard_reset_v3_hw,
1792 .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw,
1793 .phy_set_linkrate = phy_set_linkrate_v3_hw,
1794 .dereg_device = dereg_device_v3_hw,
1795 .soft_reset = soft_reset_v3_hw,
1796 .get_phys_state = get_phys_state_v3_hw,
1797 };
1798
1799 static struct Scsi_Host *
1800 hisi_sas_shost_alloc_pci(struct pci_dev *pdev)
1801 {
1802 struct Scsi_Host *shost;
1803 struct hisi_hba *hisi_hba;
1804 struct device *dev = &pdev->dev;
1805
1806 shost = scsi_host_alloc(hisi_sas_sht, sizeof(*hisi_hba));
1807 if (!shost) {
1808 dev_err(dev, "shost alloc failed\n");
1809 return NULL;
1810 }
1811 hisi_hba = shost_priv(shost);
1812
1813 hisi_hba->hw = &hisi_sas_v3_hw;
1814 hisi_hba->pci_dev = pdev;
1815 hisi_hba->dev = dev;
1816 hisi_hba->shost = shost;
1817 SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;
1818
1819 init_timer(&hisi_hba->timer);
1820
1821 if (hisi_sas_get_fw_info(hisi_hba) < 0)
1822 goto err_out;
1823
1824 if (hisi_sas_alloc(hisi_hba, shost)) {
1825 hisi_sas_free(hisi_hba);
1826 goto err_out;
1827 }
1828
1829 return shost;
1830 err_out:
1831 scsi_host_put(shost);
1832 dev_err(dev, "shost alloc failed\n");
1833 return NULL;
1834 }
1835
1836 static int
1837 hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1838 {
1839 struct Scsi_Host *shost;
1840 struct hisi_hba *hisi_hba;
1841 struct device *dev = &pdev->dev;
1842 struct asd_sas_phy **arr_phy;
1843 struct asd_sas_port **arr_port;
1844 struct sas_ha_struct *sha;
1845 int rc, phy_nr, port_nr, i;
1846
1847 rc = pci_enable_device(pdev);
1848 if (rc)
1849 goto err_out;
1850
1851 pci_set_master(pdev);
1852
1853 rc = pci_request_regions(pdev, DRV_NAME);
1854 if (rc)
1855 goto err_out_disable_device;
1856
1857 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) ||
1858 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) {
1859 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
1860 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) {
1861 dev_err(dev, "No usable DMA addressing method\n");
1862 rc = -EIO;
1863 goto err_out_regions;
1864 }
1865 }
1866
1867 shost = hisi_sas_shost_alloc_pci(pdev);
1868 if (!shost) {
1869 rc = -ENOMEM;
1870 goto err_out_regions;
1871 }
1872
1873 sha = SHOST_TO_SAS_HA(shost);
1874 hisi_hba = shost_priv(shost);
1875 dev_set_drvdata(dev, sha);
1876
1877 hisi_hba->regs = pcim_iomap(pdev, 5, 0);
1878 if (!hisi_hba->regs) {
1879 dev_err(dev, "cannot map register.\n");
1880 rc = -ENOMEM;
1881 goto err_out_ha;
1882 }
1883
1884 phy_nr = port_nr = hisi_hba->n_phy;
1885
1886 arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL);
1887 arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL);
1888 if (!arr_phy || !arr_port) {
1889 rc = -ENOMEM;
1890 goto err_out_ha;
1891 }
1892
1893 sha->sas_phy = arr_phy;
1894 sha->sas_port = arr_port;
1895 sha->core.shost = shost;
1896 sha->lldd_ha = hisi_hba;
1897
1898 shost->transportt = hisi_sas_stt;
1899 shost->max_id = HISI_SAS_MAX_DEVICES;
1900 shost->max_lun = ~0;
1901 shost->max_channel = 1;
1902 shost->max_cmd_len = 16;
1903 shost->sg_tablesize = min_t(u16, SG_ALL, HISI_SAS_SGE_PAGE_CNT);
1904 shost->can_queue = hisi_hba->hw->max_command_entries;
1905 shost->cmd_per_lun = hisi_hba->hw->max_command_entries;
1906
1907 sha->sas_ha_name = DRV_NAME;
1908 sha->dev = dev;
1909 sha->lldd_module = THIS_MODULE;
1910 sha->sas_addr = &hisi_hba->sas_addr[0];
1911 sha->num_phys = hisi_hba->n_phy;
1912 sha->core.shost = hisi_hba->shost;
1913
1914 for (i = 0; i < hisi_hba->n_phy; i++) {
1915 sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy;
1916 sha->sas_port[i] = &hisi_hba->port[i].sas_port;
1917 }
1918
1919 hisi_sas_init_add(hisi_hba);
1920
1921 rc = scsi_add_host(shost, dev);
1922 if (rc)
1923 goto err_out_ha;
1924
1925 rc = sas_register_ha(sha);
1926 if (rc)
1927 goto err_out_register_ha;
1928
1929 rc = hisi_hba->hw->hw_init(hisi_hba);
1930 if (rc)
1931 goto err_out_register_ha;
1932
1933 scsi_scan_host(shost);
1934
1935 return 0;
1936
1937 err_out_register_ha:
1938 scsi_remove_host(shost);
1939 err_out_ha:
1940 scsi_host_put(shost);
1941 err_out_regions:
1942 pci_release_regions(pdev);
1943 err_out_disable_device:
1944 pci_disable_device(pdev);
1945 err_out:
1946 return rc;
1947 }
1948
1949 static void
1950 hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba)
1951 {
1952 int i;
1953
1954 free_irq(pci_irq_vector(pdev, 1), hisi_hba);
1955 free_irq(pci_irq_vector(pdev, 2), hisi_hba);
1956 for (i = 0; i < hisi_hba->queue_count; i++) {
1957 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
1958
1959 free_irq(pci_irq_vector(pdev, i+16), cq);
1960 tasklet_kill(&cq->tasklet);
1961 }
1962 pci_free_irq_vectors(pdev);
1963 }
1964
1965 static void hisi_sas_v3_remove(struct pci_dev *pdev)
1966 {
1967 struct device *dev = &pdev->dev;
1968 struct sas_ha_struct *sha = dev_get_drvdata(dev);
1969 struct hisi_hba *hisi_hba = sha->lldd_ha;
1970 struct Scsi_Host *shost = sha->core.shost;
1971
1972 sas_unregister_ha(sha);
1973 sas_remove_host(sha->core.shost);
1974
1975 hisi_sas_v3_destroy_irqs(pdev, hisi_hba);
1976 pci_release_regions(pdev);
1977 pci_disable_device(pdev);
1978 hisi_sas_free(hisi_hba);
1979 scsi_host_put(shost);
1980 }
1981
1982 enum {
1983 /* instances of the controller */
1984 hip08,
1985 };
1986
1987 static const struct pci_device_id sas_v3_pci_table[] = {
1988 { PCI_VDEVICE(HUAWEI, 0xa230), hip08 },
1989 {}
1990 };
1991
1992 static struct pci_driver sas_v3_pci_driver = {
1993 .name = DRV_NAME,
1994 .id_table = sas_v3_pci_table,
1995 .probe = hisi_sas_v3_probe,
1996 .remove = hisi_sas_v3_remove,
1997 };
1998
1999 module_pci_driver(sas_v3_pci_driver);
2000
2001 MODULE_LICENSE("GPL");
2002 MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
2003 MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device");
2004 MODULE_ALIAS("platform:" DRV_NAME);
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