2 * Marvell Armada-3700 SPI controller driver
4 * Copyright (C) 2016 Marvell Ltd.
6 * Author: Wilson Ding <dingwei@marvell.com>
7 * Author: Romain Perier <romain.perier@free-electrons.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/clk.h>
15 #include <linux/completion.h>
16 #include <linux/delay.h>
17 #include <linux/err.h>
18 #include <linux/interrupt.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
23 #include <linux/of_irq.h>
24 #include <linux/of_device.h>
25 #include <linux/pinctrl/consumer.h>
26 #include <linux/spi/spi.h>
28 #define DRIVER_NAME "armada_3700_spi"
30 #define A3700_SPI_TIMEOUT 10
32 /* SPI Register Offest */
33 #define A3700_SPI_IF_CTRL_REG 0x00
34 #define A3700_SPI_IF_CFG_REG 0x04
35 #define A3700_SPI_DATA_OUT_REG 0x08
36 #define A3700_SPI_DATA_IN_REG 0x0C
37 #define A3700_SPI_IF_INST_REG 0x10
38 #define A3700_SPI_IF_ADDR_REG 0x14
39 #define A3700_SPI_IF_RMODE_REG 0x18
40 #define A3700_SPI_IF_HDR_CNT_REG 0x1C
41 #define A3700_SPI_IF_DIN_CNT_REG 0x20
42 #define A3700_SPI_IF_TIME_REG 0x24
43 #define A3700_SPI_INT_STAT_REG 0x28
44 #define A3700_SPI_INT_MASK_REG 0x2C
46 /* A3700_SPI_IF_CTRL_REG */
47 #define A3700_SPI_EN BIT(16)
48 #define A3700_SPI_ADDR_NOT_CONFIG BIT(12)
49 #define A3700_SPI_WFIFO_OVERFLOW BIT(11)
50 #define A3700_SPI_WFIFO_UNDERFLOW BIT(10)
51 #define A3700_SPI_RFIFO_OVERFLOW BIT(9)
52 #define A3700_SPI_RFIFO_UNDERFLOW BIT(8)
53 #define A3700_SPI_WFIFO_FULL BIT(7)
54 #define A3700_SPI_WFIFO_EMPTY BIT(6)
55 #define A3700_SPI_RFIFO_FULL BIT(5)
56 #define A3700_SPI_RFIFO_EMPTY BIT(4)
57 #define A3700_SPI_WFIFO_RDY BIT(3)
58 #define A3700_SPI_RFIFO_RDY BIT(2)
59 #define A3700_SPI_XFER_RDY BIT(1)
60 #define A3700_SPI_XFER_DONE BIT(0)
62 /* A3700_SPI_IF_CFG_REG */
63 #define A3700_SPI_WFIFO_THRS BIT(28)
64 #define A3700_SPI_RFIFO_THRS BIT(24)
65 #define A3700_SPI_AUTO_CS BIT(20)
66 #define A3700_SPI_DMA_RD_EN BIT(18)
67 #define A3700_SPI_FIFO_MODE BIT(17)
68 #define A3700_SPI_SRST BIT(16)
69 #define A3700_SPI_XFER_START BIT(15)
70 #define A3700_SPI_XFER_STOP BIT(14)
71 #define A3700_SPI_INST_PIN BIT(13)
72 #define A3700_SPI_ADDR_PIN BIT(12)
73 #define A3700_SPI_DATA_PIN1 BIT(11)
74 #define A3700_SPI_DATA_PIN0 BIT(10)
75 #define A3700_SPI_FIFO_FLUSH BIT(9)
76 #define A3700_SPI_RW_EN BIT(8)
77 #define A3700_SPI_CLK_POL BIT(7)
78 #define A3700_SPI_CLK_PHA BIT(6)
79 #define A3700_SPI_BYTE_LEN BIT(5)
80 #define A3700_SPI_CLK_PRESCALE BIT(0)
81 #define A3700_SPI_CLK_PRESCALE_MASK (0x1f)
83 #define A3700_SPI_WFIFO_THRS_BIT 28
84 #define A3700_SPI_RFIFO_THRS_BIT 24
85 #define A3700_SPI_FIFO_THRS_MASK 0x7
87 #define A3700_SPI_DATA_PIN_MASK 0x3
89 /* A3700_SPI_IF_HDR_CNT_REG */
90 #define A3700_SPI_DUMMY_CNT_BIT 12
91 #define A3700_SPI_DUMMY_CNT_MASK 0x7
92 #define A3700_SPI_RMODE_CNT_BIT 8
93 #define A3700_SPI_RMODE_CNT_MASK 0x3
94 #define A3700_SPI_ADDR_CNT_BIT 4
95 #define A3700_SPI_ADDR_CNT_MASK 0x7
96 #define A3700_SPI_INSTR_CNT_BIT 0
97 #define A3700_SPI_INSTR_CNT_MASK 0x3
99 /* A3700_SPI_IF_TIME_REG */
100 #define A3700_SPI_CLK_CAPT_EDGE BIT(7)
102 /* Flags and macros for struct a3700_spi */
103 #define A3700_INSTR_CNT 1
104 #define A3700_ADDR_CNT 3
105 #define A3700_DUMMY_CNT 1
108 struct spi_master
*master
;
119 struct completion done
;
125 static u32
spireg_read(struct a3700_spi
*a3700_spi
, u32 offset
)
127 return readl(a3700_spi
->base
+ offset
);
130 static void spireg_write(struct a3700_spi
*a3700_spi
, u32 offset
, u32 data
)
132 writel(data
, a3700_spi
->base
+ offset
);
135 static void a3700_spi_auto_cs_unset(struct a3700_spi
*a3700_spi
)
139 val
= spireg_read(a3700_spi
, A3700_SPI_IF_CFG_REG
);
140 val
&= ~A3700_SPI_AUTO_CS
;
141 spireg_write(a3700_spi
, A3700_SPI_IF_CFG_REG
, val
);
144 static void a3700_spi_activate_cs(struct a3700_spi
*a3700_spi
, unsigned int cs
)
148 val
= spireg_read(a3700_spi
, A3700_SPI_IF_CTRL_REG
);
149 val
|= (A3700_SPI_EN
<< cs
);
150 spireg_write(a3700_spi
, A3700_SPI_IF_CTRL_REG
, val
);
153 static void a3700_spi_deactivate_cs(struct a3700_spi
*a3700_spi
,
158 val
= spireg_read(a3700_spi
, A3700_SPI_IF_CTRL_REG
);
159 val
&= ~(A3700_SPI_EN
<< cs
);
160 spireg_write(a3700_spi
, A3700_SPI_IF_CTRL_REG
, val
);
163 static int a3700_spi_pin_mode_set(struct a3700_spi
*a3700_spi
,
164 unsigned int pin_mode
)
168 val
= spireg_read(a3700_spi
, A3700_SPI_IF_CFG_REG
);
169 val
&= ~(A3700_SPI_INST_PIN
| A3700_SPI_ADDR_PIN
);
170 val
&= ~(A3700_SPI_DATA_PIN0
| A3700_SPI_DATA_PIN1
);
173 case SPI_NBITS_SINGLE
:
176 val
|= A3700_SPI_DATA_PIN0
;
179 val
|= A3700_SPI_DATA_PIN1
;
182 dev_err(&a3700_spi
->master
->dev
, "wrong pin mode %u", pin_mode
);
186 spireg_write(a3700_spi
, A3700_SPI_IF_CFG_REG
, val
);
191 static void a3700_spi_fifo_mode_set(struct a3700_spi
*a3700_spi
)
195 val
= spireg_read(a3700_spi
, A3700_SPI_IF_CFG_REG
);
196 val
|= A3700_SPI_FIFO_MODE
;
197 spireg_write(a3700_spi
, A3700_SPI_IF_CFG_REG
, val
);
200 static void a3700_spi_mode_set(struct a3700_spi
*a3700_spi
,
201 unsigned int mode_bits
)
205 val
= spireg_read(a3700_spi
, A3700_SPI_IF_CFG_REG
);
207 if (mode_bits
& SPI_CPOL
)
208 val
|= A3700_SPI_CLK_POL
;
210 val
&= ~A3700_SPI_CLK_POL
;
212 if (mode_bits
& SPI_CPHA
)
213 val
|= A3700_SPI_CLK_PHA
;
215 val
&= ~A3700_SPI_CLK_PHA
;
217 spireg_write(a3700_spi
, A3700_SPI_IF_CFG_REG
, val
);
220 static void a3700_spi_clock_set(struct a3700_spi
*a3700_spi
,
221 unsigned int speed_hz
, u16 mode
)
226 prescale
= DIV_ROUND_UP(clk_get_rate(a3700_spi
->clk
), speed_hz
);
228 val
= spireg_read(a3700_spi
, A3700_SPI_IF_CFG_REG
);
229 val
= val
& ~A3700_SPI_CLK_PRESCALE_MASK
;
231 val
= val
| (prescale
& A3700_SPI_CLK_PRESCALE_MASK
);
232 spireg_write(a3700_spi
, A3700_SPI_IF_CFG_REG
, val
);
235 val
= spireg_read(a3700_spi
, A3700_SPI_IF_TIME_REG
);
236 val
|= A3700_SPI_CLK_CAPT_EDGE
;
237 spireg_write(a3700_spi
, A3700_SPI_IF_TIME_REG
, val
);
240 val
= spireg_read(a3700_spi
, A3700_SPI_IF_CFG_REG
);
241 val
&= ~(A3700_SPI_CLK_POL
| A3700_SPI_CLK_PHA
);
244 val
|= A3700_SPI_CLK_POL
;
247 val
|= A3700_SPI_CLK_PHA
;
249 spireg_write(a3700_spi
, A3700_SPI_IF_CFG_REG
, val
);
252 static void a3700_spi_bytelen_set(struct a3700_spi
*a3700_spi
, unsigned int len
)
256 val
= spireg_read(a3700_spi
, A3700_SPI_IF_CFG_REG
);
258 val
|= A3700_SPI_BYTE_LEN
;
260 val
&= ~A3700_SPI_BYTE_LEN
;
261 spireg_write(a3700_spi
, A3700_SPI_IF_CFG_REG
, val
);
263 a3700_spi
->byte_len
= len
;
266 static int a3700_spi_fifo_flush(struct a3700_spi
*a3700_spi
)
268 int timeout
= A3700_SPI_TIMEOUT
;
271 val
= spireg_read(a3700_spi
, A3700_SPI_IF_CFG_REG
);
272 val
|= A3700_SPI_FIFO_FLUSH
;
273 spireg_write(a3700_spi
, A3700_SPI_IF_CFG_REG
, val
);
276 val
= spireg_read(a3700_spi
, A3700_SPI_IF_CFG_REG
);
277 if (!(val
& A3700_SPI_FIFO_FLUSH
))
285 static int a3700_spi_init(struct a3700_spi
*a3700_spi
)
287 struct spi_master
*master
= a3700_spi
->master
;
292 val
= spireg_read(a3700_spi
, A3700_SPI_IF_CFG_REG
);
293 val
|= A3700_SPI_SRST
;
294 spireg_write(a3700_spi
, A3700_SPI_IF_CFG_REG
, val
);
296 udelay(A3700_SPI_TIMEOUT
);
298 val
= spireg_read(a3700_spi
, A3700_SPI_IF_CFG_REG
);
299 val
&= ~A3700_SPI_SRST
;
300 spireg_write(a3700_spi
, A3700_SPI_IF_CFG_REG
, val
);
302 /* Disable AUTO_CS and deactivate all chip-selects */
303 a3700_spi_auto_cs_unset(a3700_spi
);
304 for (i
= 0; i
< master
->num_chipselect
; i
++)
305 a3700_spi_deactivate_cs(a3700_spi
, i
);
307 /* Enable FIFO mode */
308 a3700_spi_fifo_mode_set(a3700_spi
);
311 a3700_spi_mode_set(a3700_spi
, master
->mode_bits
);
314 spireg_write(a3700_spi
, A3700_SPI_IF_HDR_CNT_REG
, 0);
315 spireg_write(a3700_spi
, A3700_SPI_IF_DIN_CNT_REG
, 0);
317 /* Mask the interrupts and clear cause bits */
318 spireg_write(a3700_spi
, A3700_SPI_INT_MASK_REG
, 0);
319 spireg_write(a3700_spi
, A3700_SPI_INT_STAT_REG
, ~0U);
324 static irqreturn_t
a3700_spi_interrupt(int irq
, void *dev_id
)
326 struct spi_master
*master
= dev_id
;
327 struct a3700_spi
*a3700_spi
;
330 a3700_spi
= spi_master_get_devdata(master
);
332 /* Get interrupt causes */
333 cause
= spireg_read(a3700_spi
, A3700_SPI_INT_STAT_REG
);
335 if (!cause
|| !(a3700_spi
->wait_mask
& cause
))
338 /* mask and acknowledge the SPI interrupts */
339 spireg_write(a3700_spi
, A3700_SPI_INT_MASK_REG
, 0);
340 spireg_write(a3700_spi
, A3700_SPI_INT_STAT_REG
, cause
);
342 /* Wake up the transfer */
343 complete(&a3700_spi
->done
);
348 static bool a3700_spi_wait_completion(struct spi_device
*spi
)
350 struct a3700_spi
*a3700_spi
;
351 unsigned int timeout
;
352 unsigned int ctrl_reg
;
353 unsigned long timeout_jiffies
;
355 a3700_spi
= spi_master_get_devdata(spi
->master
);
357 /* SPI interrupt is edge-triggered, which means an interrupt will
358 * be generated only when detecting a specific status bit changed
359 * from '0' to '1'. So when we start waiting for a interrupt, we
360 * need to check status bit in control reg first, if it is already 1,
361 * then we do not need to wait for interrupt
363 ctrl_reg
= spireg_read(a3700_spi
, A3700_SPI_IF_CTRL_REG
);
364 if (a3700_spi
->wait_mask
& ctrl_reg
)
367 reinit_completion(&a3700_spi
->done
);
369 spireg_write(a3700_spi
, A3700_SPI_INT_MASK_REG
,
370 a3700_spi
->wait_mask
);
372 timeout_jiffies
= msecs_to_jiffies(A3700_SPI_TIMEOUT
);
373 timeout
= wait_for_completion_timeout(&a3700_spi
->done
,
376 a3700_spi
->wait_mask
= 0;
381 /* there might be the case that right after we checked the
382 * status bits in this routine and before start to wait for
383 * interrupt by wait_for_completion_timeout, the interrupt
384 * happens, to avoid missing it we need to double check
385 * status bits in control reg, if it is already 1, then
386 * consider that we have the interrupt successfully and
389 ctrl_reg
= spireg_read(a3700_spi
, A3700_SPI_IF_CTRL_REG
);
390 if (a3700_spi
->wait_mask
& ctrl_reg
)
393 spireg_write(a3700_spi
, A3700_SPI_INT_MASK_REG
, 0);
398 static bool a3700_spi_transfer_wait(struct spi_device
*spi
,
399 unsigned int bit_mask
)
401 struct a3700_spi
*a3700_spi
;
403 a3700_spi
= spi_master_get_devdata(spi
->master
);
404 a3700_spi
->wait_mask
= bit_mask
;
406 return a3700_spi_wait_completion(spi
);
409 static void a3700_spi_fifo_thres_set(struct a3700_spi
*a3700_spi
,
414 val
= spireg_read(a3700_spi
, A3700_SPI_IF_CFG_REG
);
415 val
&= ~(A3700_SPI_FIFO_THRS_MASK
<< A3700_SPI_RFIFO_THRS_BIT
);
416 val
|= (bytes
- 1) << A3700_SPI_RFIFO_THRS_BIT
;
417 val
&= ~(A3700_SPI_FIFO_THRS_MASK
<< A3700_SPI_WFIFO_THRS_BIT
);
418 val
|= (7 - bytes
) << A3700_SPI_WFIFO_THRS_BIT
;
419 spireg_write(a3700_spi
, A3700_SPI_IF_CFG_REG
, val
);
422 static void a3700_spi_transfer_setup(struct spi_device
*spi
,
423 struct spi_transfer
*xfer
)
425 struct a3700_spi
*a3700_spi
;
426 unsigned int byte_len
;
428 a3700_spi
= spi_master_get_devdata(spi
->master
);
430 a3700_spi_clock_set(a3700_spi
, xfer
->speed_hz
, spi
->mode
);
432 byte_len
= xfer
->bits_per_word
>> 3;
434 a3700_spi_fifo_thres_set(a3700_spi
, byte_len
);
437 static void a3700_spi_set_cs(struct spi_device
*spi
, bool enable
)
439 struct a3700_spi
*a3700_spi
= spi_master_get_devdata(spi
->master
);
442 a3700_spi_activate_cs(a3700_spi
, spi
->chip_select
);
444 a3700_spi_deactivate_cs(a3700_spi
, spi
->chip_select
);
447 static void a3700_spi_header_set(struct a3700_spi
*a3700_spi
)
449 u32 instr_cnt
= 0, addr_cnt
= 0, dummy_cnt
= 0;
452 /* Clear the header registers */
453 spireg_write(a3700_spi
, A3700_SPI_IF_INST_REG
, 0);
454 spireg_write(a3700_spi
, A3700_SPI_IF_ADDR_REG
, 0);
455 spireg_write(a3700_spi
, A3700_SPI_IF_RMODE_REG
, 0);
457 /* Set header counters */
458 if (a3700_spi
->tx_buf
) {
459 if (a3700_spi
->buf_len
<= a3700_spi
->instr_cnt
) {
460 instr_cnt
= a3700_spi
->buf_len
;
461 } else if (a3700_spi
->buf_len
<= (a3700_spi
->instr_cnt
+
462 a3700_spi
->addr_cnt
)) {
463 instr_cnt
= a3700_spi
->instr_cnt
;
464 addr_cnt
= a3700_spi
->buf_len
- instr_cnt
;
465 } else if (a3700_spi
->buf_len
<= a3700_spi
->hdr_cnt
) {
466 instr_cnt
= a3700_spi
->instr_cnt
;
467 addr_cnt
= a3700_spi
->addr_cnt
;
468 /* Need to handle the normal write case with 1 byte
471 if (!a3700_spi
->tx_buf
[instr_cnt
+ addr_cnt
])
472 dummy_cnt
= a3700_spi
->buf_len
- instr_cnt
-
475 val
|= ((instr_cnt
& A3700_SPI_INSTR_CNT_MASK
)
476 << A3700_SPI_INSTR_CNT_BIT
);
477 val
|= ((addr_cnt
& A3700_SPI_ADDR_CNT_MASK
)
478 << A3700_SPI_ADDR_CNT_BIT
);
479 val
|= ((dummy_cnt
& A3700_SPI_DUMMY_CNT_MASK
)
480 << A3700_SPI_DUMMY_CNT_BIT
);
482 spireg_write(a3700_spi
, A3700_SPI_IF_HDR_CNT_REG
, val
);
484 /* Update the buffer length to be transferred */
485 a3700_spi
->buf_len
-= (instr_cnt
+ addr_cnt
+ dummy_cnt
);
487 /* Set Instruction */
489 while (instr_cnt
--) {
490 val
= (val
<< 8) | a3700_spi
->tx_buf
[0];
493 spireg_write(a3700_spi
, A3700_SPI_IF_INST_REG
, val
);
498 val
= (val
<< 8) | a3700_spi
->tx_buf
[0];
501 spireg_write(a3700_spi
, A3700_SPI_IF_ADDR_REG
, val
);
504 static int a3700_is_wfifo_full(struct a3700_spi
*a3700_spi
)
508 val
= spireg_read(a3700_spi
, A3700_SPI_IF_CTRL_REG
);
509 return (val
& A3700_SPI_WFIFO_FULL
);
512 static int a3700_spi_fifo_write(struct a3700_spi
*a3700_spi
)
517 while (!a3700_is_wfifo_full(a3700_spi
) && a3700_spi
->buf_len
) {
519 if (a3700_spi
->buf_len
>= 4) {
520 val
= cpu_to_le32(*(u32
*)a3700_spi
->tx_buf
);
521 spireg_write(a3700_spi
, A3700_SPI_DATA_OUT_REG
, val
);
523 a3700_spi
->buf_len
-= 4;
524 a3700_spi
->tx_buf
+= 4;
527 * If the remained buffer length is less than 4-bytes,
528 * we should pad the write buffer with all ones. So that
529 * it avoids overwrite the unexpected bytes following
532 val
= GENMASK(31, 0);
533 while (a3700_spi
->buf_len
) {
534 val
&= ~(0xff << (8 * i
));
535 val
|= *a3700_spi
->tx_buf
++ << (8 * i
);
537 a3700_spi
->buf_len
--;
539 spireg_write(a3700_spi
, A3700_SPI_DATA_OUT_REG
,
549 static int a3700_is_rfifo_empty(struct a3700_spi
*a3700_spi
)
551 u32 val
= spireg_read(a3700_spi
, A3700_SPI_IF_CTRL_REG
);
553 return (val
& A3700_SPI_RFIFO_EMPTY
);
556 static int a3700_spi_fifo_read(struct a3700_spi
*a3700_spi
)
560 while (!a3700_is_rfifo_empty(a3700_spi
) && a3700_spi
->buf_len
) {
561 val
= spireg_read(a3700_spi
, A3700_SPI_DATA_IN_REG
);
562 if (a3700_spi
->buf_len
>= 4) {
563 u32 data
= le32_to_cpu(val
);
565 memcpy(a3700_spi
->rx_buf
, &data
, 4);
567 a3700_spi
->buf_len
-= 4;
568 a3700_spi
->rx_buf
+= 4;
571 * When remain bytes is not larger than 4, we should
572 * avoid memory overwriting and just write the left rx
575 while (a3700_spi
->buf_len
) {
576 *a3700_spi
->rx_buf
= val
& 0xff;
579 a3700_spi
->buf_len
--;
588 static void a3700_spi_transfer_abort_fifo(struct a3700_spi
*a3700_spi
)
590 int timeout
= A3700_SPI_TIMEOUT
;
593 val
= spireg_read(a3700_spi
, A3700_SPI_IF_CFG_REG
);
594 val
|= A3700_SPI_XFER_STOP
;
595 spireg_write(a3700_spi
, A3700_SPI_IF_CFG_REG
, val
);
598 val
= spireg_read(a3700_spi
, A3700_SPI_IF_CFG_REG
);
599 if (!(val
& A3700_SPI_XFER_START
))
604 a3700_spi_fifo_flush(a3700_spi
);
606 val
&= ~A3700_SPI_XFER_STOP
;
607 spireg_write(a3700_spi
, A3700_SPI_IF_CFG_REG
, val
);
610 static int a3700_spi_prepare_message(struct spi_master
*master
,
611 struct spi_message
*message
)
613 struct a3700_spi
*a3700_spi
= spi_master_get_devdata(master
);
614 struct spi_device
*spi
= message
->spi
;
617 ret
= clk_enable(a3700_spi
->clk
);
619 dev_err(&spi
->dev
, "failed to enable clk with error %d\n", ret
);
623 /* Flush the FIFOs */
624 ret
= a3700_spi_fifo_flush(a3700_spi
);
628 a3700_spi_bytelen_set(a3700_spi
, 4);
633 static int a3700_spi_transfer_one(struct spi_master
*master
,
634 struct spi_device
*spi
,
635 struct spi_transfer
*xfer
)
637 struct a3700_spi
*a3700_spi
= spi_master_get_devdata(master
);
638 int ret
= 0, timeout
= A3700_SPI_TIMEOUT
;
639 unsigned int nbits
= 0;
642 a3700_spi_transfer_setup(spi
, xfer
);
644 a3700_spi
->tx_buf
= xfer
->tx_buf
;
645 a3700_spi
->rx_buf
= xfer
->rx_buf
;
646 a3700_spi
->buf_len
= xfer
->len
;
648 /* SPI transfer headers */
649 a3700_spi_header_set(a3700_spi
);
652 nbits
= xfer
->tx_nbits
;
653 else if (xfer
->rx_buf
)
654 nbits
= xfer
->rx_nbits
;
656 a3700_spi_pin_mode_set(a3700_spi
, nbits
);
659 /* Set read data length */
660 spireg_write(a3700_spi
, A3700_SPI_IF_DIN_CNT_REG
,
662 /* Start READ transfer */
663 val
= spireg_read(a3700_spi
, A3700_SPI_IF_CFG_REG
);
664 val
&= ~A3700_SPI_RW_EN
;
665 val
|= A3700_SPI_XFER_START
;
666 spireg_write(a3700_spi
, A3700_SPI_IF_CFG_REG
, val
);
667 } else if (xfer
->tx_buf
) {
668 /* Start Write transfer */
669 val
= spireg_read(a3700_spi
, A3700_SPI_IF_CFG_REG
);
670 val
|= (A3700_SPI_XFER_START
| A3700_SPI_RW_EN
);
671 spireg_write(a3700_spi
, A3700_SPI_IF_CFG_REG
, val
);
674 * If there are data to be written to the SPI device, xmit_data
675 * flag is set true; otherwise the instruction in SPI_INSTR does
676 * not require data to be written to the SPI device, then
677 * xmit_data flag is set false.
679 a3700_spi
->xmit_data
= (a3700_spi
->buf_len
!= 0);
682 while (a3700_spi
->buf_len
) {
683 if (a3700_spi
->tx_buf
) {
684 /* Wait wfifo ready */
685 if (!a3700_spi_transfer_wait(spi
,
686 A3700_SPI_WFIFO_RDY
)) {
688 "wait wfifo ready timed out\n");
692 /* Fill up the wfifo */
693 ret
= a3700_spi_fifo_write(a3700_spi
);
696 } else if (a3700_spi
->rx_buf
) {
697 /* Wait rfifo ready */
698 if (!a3700_spi_transfer_wait(spi
,
699 A3700_SPI_RFIFO_RDY
)) {
701 "wait rfifo ready timed out\n");
705 /* Drain out the rfifo */
706 ret
= a3700_spi_fifo_read(a3700_spi
);
713 * Stop a write transfer in fifo mode:
714 * - wait all the bytes in wfifo to be shifted out
715 * - set XFER_STOP bit
716 * - wait XFER_START bit clear
717 * - clear XFER_STOP bit
718 * Stop a read transfer in fifo mode:
719 * - the hardware is to reset the XFER_START bit
720 * after the number of bytes indicated in DIN_CNT
722 * - just wait XFER_START bit clear
724 if (a3700_spi
->tx_buf
) {
725 if (a3700_spi
->xmit_data
) {
727 * If there are data written to the SPI device, wait
728 * until SPI_WFIFO_EMPTY is 1 to wait for all data to
729 * transfer out of write FIFO.
731 if (!a3700_spi_transfer_wait(spi
,
732 A3700_SPI_WFIFO_EMPTY
)) {
733 dev_err(&spi
->dev
, "wait wfifo empty timed out\n");
738 * If the instruction in SPI_INSTR does not require data
739 * to be written to the SPI device, wait until SPI_RDY
740 * is 1 for the SPI interface to be in idle.
742 if (!a3700_spi_transfer_wait(spi
, A3700_SPI_XFER_RDY
)) {
743 dev_err(&spi
->dev
, "wait xfer ready timed out\n");
748 val
= spireg_read(a3700_spi
, A3700_SPI_IF_CFG_REG
);
749 val
|= A3700_SPI_XFER_STOP
;
750 spireg_write(a3700_spi
, A3700_SPI_IF_CFG_REG
, val
);
754 val
= spireg_read(a3700_spi
, A3700_SPI_IF_CFG_REG
);
755 if (!(val
& A3700_SPI_XFER_START
))
761 dev_err(&spi
->dev
, "wait transfer start clear timed out\n");
766 val
&= ~A3700_SPI_XFER_STOP
;
767 spireg_write(a3700_spi
, A3700_SPI_IF_CFG_REG
, val
);
771 a3700_spi_transfer_abort_fifo(a3700_spi
);
773 spi_finalize_current_transfer(master
);
778 static int a3700_spi_unprepare_message(struct spi_master
*master
,
779 struct spi_message
*message
)
781 struct a3700_spi
*a3700_spi
= spi_master_get_devdata(master
);
783 clk_disable(a3700_spi
->clk
);
788 static const struct of_device_id a3700_spi_dt_ids
[] = {
789 { .compatible
= "marvell,armada-3700-spi", .data
= NULL
},
793 MODULE_DEVICE_TABLE(of
, a3700_spi_dt_ids
);
795 static int a3700_spi_probe(struct platform_device
*pdev
)
797 struct device
*dev
= &pdev
->dev
;
798 struct device_node
*of_node
= dev
->of_node
;
799 struct resource
*res
;
800 struct spi_master
*master
;
801 struct a3700_spi
*spi
;
805 master
= spi_alloc_master(dev
, sizeof(*spi
));
807 dev_err(dev
, "master allocation failed\n");
812 if (of_property_read_u32(of_node
, "num-cs", &num_cs
)) {
813 dev_err(dev
, "could not find num-cs\n");
818 master
->bus_num
= pdev
->id
;
819 master
->dev
.of_node
= of_node
;
820 master
->mode_bits
= SPI_MODE_3
;
821 master
->num_chipselect
= num_cs
;
822 master
->bits_per_word_mask
= SPI_BPW_MASK(8) | SPI_BPW_MASK(32);
823 master
->prepare_message
= a3700_spi_prepare_message
;
824 master
->transfer_one
= a3700_spi_transfer_one
;
825 master
->unprepare_message
= a3700_spi_unprepare_message
;
826 master
->set_cs
= a3700_spi_set_cs
;
827 master
->flags
= SPI_MASTER_HALF_DUPLEX
;
828 master
->mode_bits
|= (SPI_RX_DUAL
| SPI_TX_DUAL
|
829 SPI_RX_QUAD
| SPI_TX_QUAD
);
831 platform_set_drvdata(pdev
, master
);
833 spi
= spi_master_get_devdata(master
);
834 memset(spi
, 0, sizeof(struct a3700_spi
));
836 spi
->master
= master
;
837 spi
->instr_cnt
= A3700_INSTR_CNT
;
838 spi
->addr_cnt
= A3700_ADDR_CNT
;
839 spi
->hdr_cnt
= A3700_INSTR_CNT
+ A3700_ADDR_CNT
+
842 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
843 spi
->base
= devm_ioremap_resource(dev
, res
);
844 if (IS_ERR(spi
->base
)) {
845 ret
= PTR_ERR(spi
->base
);
849 irq
= platform_get_irq(pdev
, 0);
851 dev_err(dev
, "could not get irq: %d\n", irq
);
857 init_completion(&spi
->done
);
859 spi
->clk
= devm_clk_get(dev
, NULL
);
860 if (IS_ERR(spi
->clk
)) {
861 dev_err(dev
, "could not find clk: %ld\n", PTR_ERR(spi
->clk
));
865 ret
= clk_prepare(spi
->clk
);
867 dev_err(dev
, "could not prepare clk: %d\n", ret
);
871 ret
= a3700_spi_init(spi
);
875 ret
= devm_request_irq(dev
, spi
->irq
, a3700_spi_interrupt
, 0,
876 dev_name(dev
), master
);
878 dev_err(dev
, "could not request IRQ: %d\n", ret
);
882 ret
= devm_spi_register_master(dev
, master
);
884 dev_err(dev
, "Failed to register master\n");
891 clk_disable_unprepare(spi
->clk
);
893 spi_master_put(master
);
898 static int a3700_spi_remove(struct platform_device
*pdev
)
900 struct spi_master
*master
= platform_get_drvdata(pdev
);
901 struct a3700_spi
*spi
= spi_master_get_devdata(master
);
903 clk_unprepare(spi
->clk
);
908 static struct platform_driver a3700_spi_driver
= {
911 .of_match_table
= of_match_ptr(a3700_spi_dt_ids
),
913 .probe
= a3700_spi_probe
,
914 .remove
= a3700_spi_remove
,
917 module_platform_driver(a3700_spi_driver
);
919 MODULE_DESCRIPTION("Armada-3700 SPI driver");
920 MODULE_AUTHOR("Wilson Ding <dingwei@marvell.com>");
921 MODULE_LICENSE("GPL");
922 MODULE_ALIAS("platform:" DRIVER_NAME
);