2 * Driver for Atmel AT32 and AT91 SPI Controllers
4 * Copyright (C) 2006 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/clk.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/err.h>
19 #include <linux/interrupt.h>
20 #include <linux/spi/spi.h>
21 #include <linux/slab.h>
22 #include <linux/platform_data/atmel.h>
26 #include <linux/gpio.h>
28 /* SPI register offsets */
31 #define SPI_RDR 0x0008
32 #define SPI_TDR 0x000c
34 #define SPI_IER 0x0014
35 #define SPI_IDR 0x0018
36 #define SPI_IMR 0x001c
37 #define SPI_CSR0 0x0030
38 #define SPI_CSR1 0x0034
39 #define SPI_CSR2 0x0038
40 #define SPI_CSR3 0x003c
41 #define SPI_VERSION 0x00fc
42 #define SPI_RPR 0x0100
43 #define SPI_RCR 0x0104
44 #define SPI_TPR 0x0108
45 #define SPI_TCR 0x010c
46 #define SPI_RNPR 0x0110
47 #define SPI_RNCR 0x0114
48 #define SPI_TNPR 0x0118
49 #define SPI_TNCR 0x011c
50 #define SPI_PTCR 0x0120
51 #define SPI_PTSR 0x0124
54 #define SPI_SPIEN_OFFSET 0
55 #define SPI_SPIEN_SIZE 1
56 #define SPI_SPIDIS_OFFSET 1
57 #define SPI_SPIDIS_SIZE 1
58 #define SPI_SWRST_OFFSET 7
59 #define SPI_SWRST_SIZE 1
60 #define SPI_LASTXFER_OFFSET 24
61 #define SPI_LASTXFER_SIZE 1
64 #define SPI_MSTR_OFFSET 0
65 #define SPI_MSTR_SIZE 1
66 #define SPI_PS_OFFSET 1
68 #define SPI_PCSDEC_OFFSET 2
69 #define SPI_PCSDEC_SIZE 1
70 #define SPI_FDIV_OFFSET 3
71 #define SPI_FDIV_SIZE 1
72 #define SPI_MODFDIS_OFFSET 4
73 #define SPI_MODFDIS_SIZE 1
74 #define SPI_WDRBT_OFFSET 5
75 #define SPI_WDRBT_SIZE 1
76 #define SPI_LLB_OFFSET 7
77 #define SPI_LLB_SIZE 1
78 #define SPI_PCS_OFFSET 16
79 #define SPI_PCS_SIZE 4
80 #define SPI_DLYBCS_OFFSET 24
81 #define SPI_DLYBCS_SIZE 8
83 /* Bitfields in RDR */
84 #define SPI_RD_OFFSET 0
85 #define SPI_RD_SIZE 16
87 /* Bitfields in TDR */
88 #define SPI_TD_OFFSET 0
89 #define SPI_TD_SIZE 16
92 #define SPI_RDRF_OFFSET 0
93 #define SPI_RDRF_SIZE 1
94 #define SPI_TDRE_OFFSET 1
95 #define SPI_TDRE_SIZE 1
96 #define SPI_MODF_OFFSET 2
97 #define SPI_MODF_SIZE 1
98 #define SPI_OVRES_OFFSET 3
99 #define SPI_OVRES_SIZE 1
100 #define SPI_ENDRX_OFFSET 4
101 #define SPI_ENDRX_SIZE 1
102 #define SPI_ENDTX_OFFSET 5
103 #define SPI_ENDTX_SIZE 1
104 #define SPI_RXBUFF_OFFSET 6
105 #define SPI_RXBUFF_SIZE 1
106 #define SPI_TXBUFE_OFFSET 7
107 #define SPI_TXBUFE_SIZE 1
108 #define SPI_NSSR_OFFSET 8
109 #define SPI_NSSR_SIZE 1
110 #define SPI_TXEMPTY_OFFSET 9
111 #define SPI_TXEMPTY_SIZE 1
112 #define SPI_SPIENS_OFFSET 16
113 #define SPI_SPIENS_SIZE 1
115 /* Bitfields in CSR0 */
116 #define SPI_CPOL_OFFSET 0
117 #define SPI_CPOL_SIZE 1
118 #define SPI_NCPHA_OFFSET 1
119 #define SPI_NCPHA_SIZE 1
120 #define SPI_CSAAT_OFFSET 3
121 #define SPI_CSAAT_SIZE 1
122 #define SPI_BITS_OFFSET 4
123 #define SPI_BITS_SIZE 4
124 #define SPI_SCBR_OFFSET 8
125 #define SPI_SCBR_SIZE 8
126 #define SPI_DLYBS_OFFSET 16
127 #define SPI_DLYBS_SIZE 8
128 #define SPI_DLYBCT_OFFSET 24
129 #define SPI_DLYBCT_SIZE 8
131 /* Bitfields in RCR */
132 #define SPI_RXCTR_OFFSET 0
133 #define SPI_RXCTR_SIZE 16
135 /* Bitfields in TCR */
136 #define SPI_TXCTR_OFFSET 0
137 #define SPI_TXCTR_SIZE 16
139 /* Bitfields in RNCR */
140 #define SPI_RXNCR_OFFSET 0
141 #define SPI_RXNCR_SIZE 16
143 /* Bitfields in TNCR */
144 #define SPI_TXNCR_OFFSET 0
145 #define SPI_TXNCR_SIZE 16
147 /* Bitfields in PTCR */
148 #define SPI_RXTEN_OFFSET 0
149 #define SPI_RXTEN_SIZE 1
150 #define SPI_RXTDIS_OFFSET 1
151 #define SPI_RXTDIS_SIZE 1
152 #define SPI_TXTEN_OFFSET 8
153 #define SPI_TXTEN_SIZE 1
154 #define SPI_TXTDIS_OFFSET 9
155 #define SPI_TXTDIS_SIZE 1
157 /* Constants for BITS */
158 #define SPI_BITS_8_BPT 0
159 #define SPI_BITS_9_BPT 1
160 #define SPI_BITS_10_BPT 2
161 #define SPI_BITS_11_BPT 3
162 #define SPI_BITS_12_BPT 4
163 #define SPI_BITS_13_BPT 5
164 #define SPI_BITS_14_BPT 6
165 #define SPI_BITS_15_BPT 7
166 #define SPI_BITS_16_BPT 8
168 /* Bit manipulation macros */
169 #define SPI_BIT(name) \
170 (1 << SPI_##name##_OFFSET)
171 #define SPI_BF(name,value) \
172 (((value) & ((1 << SPI_##name##_SIZE) - 1)) << SPI_##name##_OFFSET)
173 #define SPI_BFEXT(name,value) \
174 (((value) >> SPI_##name##_OFFSET) & ((1 << SPI_##name##_SIZE) - 1))
175 #define SPI_BFINS(name,value,old) \
176 ( ((old) & ~(((1 << SPI_##name##_SIZE) - 1) << SPI_##name##_OFFSET)) \
177 | SPI_BF(name,value))
179 /* Register access macros */
180 #define spi_readl(port,reg) \
181 __raw_readl((port)->regs + SPI_##reg)
182 #define spi_writel(port,reg,value) \
183 __raw_writel((value), (port)->regs + SPI_##reg)
185 struct atmel_spi_caps
{
188 bool has_dma_support
;
192 * The core SPI transfer engine just talks to a register bank to set up
193 * DMA transfers; transfer queue progress is driven by IRQs. The clock
194 * framework provides the base clock, subdivided for each spi_device.
202 struct platform_device
*pdev
;
203 struct spi_device
*stay
;
206 struct list_head queue
;
207 struct spi_transfer
*current_transfer
;
208 unsigned long current_remaining_bytes
;
209 struct spi_transfer
*next_transfer
;
210 unsigned long next_remaining_bytes
;
213 dma_addr_t buffer_dma
;
215 struct atmel_spi_caps caps
;
218 /* Controller-specific per-slave state */
219 struct atmel_spi_device
{
220 unsigned int npcs_pin
;
224 #define BUFFER_SIZE PAGE_SIZE
225 #define INVALID_DMA_ADDRESS 0xffffffff
228 * Version 2 of the SPI controller has
230 * - SPI_MR.DIV32 may become FDIV or must-be-zero (here: always zero)
231 * - SPI_SR.TXEMPTY, SPI_SR.NSSR (and corresponding irqs)
233 * - SPI_CSRx.SBCR allows faster clocking
235 static bool atmel_spi_is_v2(struct atmel_spi
*as
)
237 return as
->caps
.is_spi2
;
241 * Earlier SPI controllers (e.g. on at91rm9200) have a design bug whereby
242 * they assume that spi slave device state will not change on deselect, so
243 * that automagic deselection is OK. ("NPCSx rises if no data is to be
244 * transmitted") Not so! Workaround uses nCSx pins as GPIOs; or newer
245 * controllers have CSAAT and friends.
247 * Since the CSAAT functionality is a bit weird on newer controllers as
248 * well, we use GPIO to control nCSx pins on all controllers, updating
249 * MR.PCS to avoid confusing the controller. Using GPIOs also lets us
250 * support active-high chipselects despite the controller's belief that
251 * only active-low devices/systems exists.
253 * However, at91rm9200 has a second erratum whereby nCS0 doesn't work
254 * right when driven with GPIO. ("Mode Fault does not allow more than one
255 * Master on Chip Select 0.") No workaround exists for that ... so for
256 * nCS0 on that chip, we (a) don't use the GPIO, (b) can't support CS_HIGH,
257 * and (c) will trigger that first erratum in some cases.
259 * TODO: Test if the atmel_spi_is_v2() branch below works on
260 * AT91RM9200 if we use some other register than CSR0. However, don't
261 * do this unconditionally since AP7000 has an errata where the BITS
262 * field in CSR0 overrides all other CSRs.
265 static void cs_activate(struct atmel_spi
*as
, struct spi_device
*spi
)
267 struct atmel_spi_device
*asd
= spi
->controller_state
;
268 unsigned active
= spi
->mode
& SPI_CS_HIGH
;
271 if (atmel_spi_is_v2(as
)) {
273 * Always use CSR0. This ensures that the clock
274 * switches to the correct idle polarity before we
277 spi_writel(as
, CSR0
, asd
->csr
);
278 if (as
->caps
.has_wdrbt
) {
279 spi_writel(as
, MR
, SPI_BF(PCS
, 0x0e) | SPI_BIT(WDRBT
)
280 | SPI_BIT(MODFDIS
) | SPI_BIT(MSTR
));
282 spi_writel(as
, MR
, SPI_BF(PCS
, 0x0e) | SPI_BIT(MODFDIS
)
285 mr
= spi_readl(as
, MR
);
286 gpio_set_value(asd
->npcs_pin
, active
);
288 u32 cpol
= (spi
->mode
& SPI_CPOL
) ? SPI_BIT(CPOL
) : 0;
292 /* Make sure clock polarity is correct */
293 for (i
= 0; i
< spi
->master
->num_chipselect
; i
++) {
294 csr
= spi_readl(as
, CSR0
+ 4 * i
);
295 if ((csr
^ cpol
) & SPI_BIT(CPOL
))
296 spi_writel(as
, CSR0
+ 4 * i
,
297 csr
^ SPI_BIT(CPOL
));
300 mr
= spi_readl(as
, MR
);
301 mr
= SPI_BFINS(PCS
, ~(1 << spi
->chip_select
), mr
);
302 if (spi
->chip_select
!= 0)
303 gpio_set_value(asd
->npcs_pin
, active
);
304 spi_writel(as
, MR
, mr
);
307 dev_dbg(&spi
->dev
, "activate %u%s, mr %08x\n",
308 asd
->npcs_pin
, active
? " (high)" : "",
312 static void cs_deactivate(struct atmel_spi
*as
, struct spi_device
*spi
)
314 struct atmel_spi_device
*asd
= spi
->controller_state
;
315 unsigned active
= spi
->mode
& SPI_CS_HIGH
;
318 /* only deactivate *this* device; sometimes transfers to
319 * another device may be active when this routine is called.
321 mr
= spi_readl(as
, MR
);
322 if (~SPI_BFEXT(PCS
, mr
) & (1 << spi
->chip_select
)) {
323 mr
= SPI_BFINS(PCS
, 0xf, mr
);
324 spi_writel(as
, MR
, mr
);
327 dev_dbg(&spi
->dev
, "DEactivate %u%s, mr %08x\n",
328 asd
->npcs_pin
, active
? " (low)" : "",
331 if (atmel_spi_is_v2(as
) || spi
->chip_select
!= 0)
332 gpio_set_value(asd
->npcs_pin
, !active
);
335 static inline int atmel_spi_xfer_is_last(struct spi_message
*msg
,
336 struct spi_transfer
*xfer
)
338 return msg
->transfers
.prev
== &xfer
->transfer_list
;
341 static inline int atmel_spi_xfer_can_be_chained(struct spi_transfer
*xfer
)
343 return xfer
->delay_usecs
== 0 && !xfer
->cs_change
;
346 static void atmel_spi_next_xfer_data(struct spi_master
*master
,
347 struct spi_transfer
*xfer
,
352 struct atmel_spi
*as
= spi_master_get_devdata(master
);
355 /* use scratch buffer only when rx or tx data is unspecified */
357 *rx_dma
= xfer
->rx_dma
+ xfer
->len
- *plen
;
359 *rx_dma
= as
->buffer_dma
;
360 if (len
> BUFFER_SIZE
)
364 *tx_dma
= xfer
->tx_dma
+ xfer
->len
- *plen
;
366 *tx_dma
= as
->buffer_dma
;
367 if (len
> BUFFER_SIZE
)
369 memset(as
->buffer
, 0, len
);
370 dma_sync_single_for_device(&as
->pdev
->dev
,
371 as
->buffer_dma
, len
, DMA_TO_DEVICE
);
378 * Submit next transfer for DMA.
379 * lock is held, spi irq is blocked
381 static void atmel_spi_next_xfer(struct spi_master
*master
,
382 struct spi_message
*msg
)
384 struct atmel_spi
*as
= spi_master_get_devdata(master
);
385 struct spi_transfer
*xfer
;
388 dma_addr_t tx_dma
, rx_dma
;
390 if (!as
->current_transfer
)
391 xfer
= list_entry(msg
->transfers
.next
,
392 struct spi_transfer
, transfer_list
);
393 else if (!as
->next_transfer
)
394 xfer
= list_entry(as
->current_transfer
->transfer_list
.next
,
395 struct spi_transfer
, transfer_list
);
400 spi_writel(as
, PTCR
, SPI_BIT(RXTDIS
) | SPI_BIT(TXTDIS
));
403 atmel_spi_next_xfer_data(master
, xfer
, &tx_dma
, &rx_dma
, &len
);
404 remaining
= xfer
->len
- len
;
406 spi_writel(as
, RPR
, rx_dma
);
407 spi_writel(as
, TPR
, tx_dma
);
409 if (msg
->spi
->bits_per_word
> 8)
411 spi_writel(as
, RCR
, len
);
412 spi_writel(as
, TCR
, len
);
414 dev_dbg(&msg
->spi
->dev
,
415 " start xfer %p: len %u tx %p/%08x rx %p/%08x\n",
416 xfer
, xfer
->len
, xfer
->tx_buf
, xfer
->tx_dma
,
417 xfer
->rx_buf
, xfer
->rx_dma
);
419 xfer
= as
->next_transfer
;
420 remaining
= as
->next_remaining_bytes
;
423 as
->current_transfer
= xfer
;
424 as
->current_remaining_bytes
= remaining
;
428 else if (!atmel_spi_xfer_is_last(msg
, xfer
)
429 && atmel_spi_xfer_can_be_chained(xfer
)) {
430 xfer
= list_entry(xfer
->transfer_list
.next
,
431 struct spi_transfer
, transfer_list
);
436 as
->next_transfer
= xfer
;
442 atmel_spi_next_xfer_data(master
, xfer
, &tx_dma
, &rx_dma
, &len
);
443 as
->next_remaining_bytes
= total
- len
;
445 spi_writel(as
, RNPR
, rx_dma
);
446 spi_writel(as
, TNPR
, tx_dma
);
448 if (msg
->spi
->bits_per_word
> 8)
450 spi_writel(as
, RNCR
, len
);
451 spi_writel(as
, TNCR
, len
);
453 dev_dbg(&msg
->spi
->dev
,
454 " next xfer %p: len %u tx %p/%08x rx %p/%08x\n",
455 xfer
, xfer
->len
, xfer
->tx_buf
, xfer
->tx_dma
,
456 xfer
->rx_buf
, xfer
->rx_dma
);
457 ieval
= SPI_BIT(ENDRX
) | SPI_BIT(OVRES
);
459 spi_writel(as
, RNCR
, 0);
460 spi_writel(as
, TNCR
, 0);
461 ieval
= SPI_BIT(RXBUFF
) | SPI_BIT(ENDRX
) | SPI_BIT(OVRES
);
464 /* REVISIT: We're waiting for ENDRX before we start the next
465 * transfer because we need to handle some difficult timing
466 * issues otherwise. If we wait for ENDTX in one transfer and
467 * then starts waiting for ENDRX in the next, it's difficult
468 * to tell the difference between the ENDRX interrupt we're
469 * actually waiting for and the ENDRX interrupt of the
472 * It should be doable, though. Just not now...
474 spi_writel(as
, IER
, ieval
);
475 spi_writel(as
, PTCR
, SPI_BIT(TXTEN
) | SPI_BIT(RXTEN
));
478 static void atmel_spi_next_message(struct spi_master
*master
)
480 struct atmel_spi
*as
= spi_master_get_devdata(master
);
481 struct spi_message
*msg
;
482 struct spi_device
*spi
;
484 BUG_ON(as
->current_transfer
);
486 msg
= list_entry(as
->queue
.next
, struct spi_message
, queue
);
489 dev_dbg(master
->dev
.parent
, "start message %p for %s\n",
490 msg
, dev_name(&spi
->dev
));
492 /* select chip if it's not still active */
494 if (as
->stay
!= spi
) {
495 cs_deactivate(as
, as
->stay
);
496 cs_activate(as
, spi
);
500 cs_activate(as
, spi
);
502 atmel_spi_next_xfer(master
, msg
);
506 * For DMA, tx_buf/tx_dma have the same relationship as rx_buf/rx_dma:
507 * - The buffer is either valid for CPU access, else NULL
508 * - If the buffer is valid, so is its DMA address
510 * This driver manages the dma address unless message->is_dma_mapped.
513 atmel_spi_dma_map_xfer(struct atmel_spi
*as
, struct spi_transfer
*xfer
)
515 struct device
*dev
= &as
->pdev
->dev
;
517 xfer
->tx_dma
= xfer
->rx_dma
= INVALID_DMA_ADDRESS
;
519 /* tx_buf is a const void* where we need a void * for the dma
521 void *nonconst_tx
= (void *)xfer
->tx_buf
;
523 xfer
->tx_dma
= dma_map_single(dev
,
524 nonconst_tx
, xfer
->len
,
526 if (dma_mapping_error(dev
, xfer
->tx_dma
))
530 xfer
->rx_dma
= dma_map_single(dev
,
531 xfer
->rx_buf
, xfer
->len
,
533 if (dma_mapping_error(dev
, xfer
->rx_dma
)) {
535 dma_unmap_single(dev
,
536 xfer
->tx_dma
, xfer
->len
,
544 static void atmel_spi_dma_unmap_xfer(struct spi_master
*master
,
545 struct spi_transfer
*xfer
)
547 if (xfer
->tx_dma
!= INVALID_DMA_ADDRESS
)
548 dma_unmap_single(master
->dev
.parent
, xfer
->tx_dma
,
549 xfer
->len
, DMA_TO_DEVICE
);
550 if (xfer
->rx_dma
!= INVALID_DMA_ADDRESS
)
551 dma_unmap_single(master
->dev
.parent
, xfer
->rx_dma
,
552 xfer
->len
, DMA_FROM_DEVICE
);
556 atmel_spi_msg_done(struct spi_master
*master
, struct atmel_spi
*as
,
557 struct spi_message
*msg
, int status
, int stay
)
559 if (!stay
|| status
< 0)
560 cs_deactivate(as
, msg
->spi
);
564 list_del(&msg
->queue
);
565 msg
->status
= status
;
567 dev_dbg(master
->dev
.parent
,
568 "xfer complete: %u bytes transferred\n",
571 spin_unlock(&as
->lock
);
572 msg
->complete(msg
->context
);
573 spin_lock(&as
->lock
);
575 as
->current_transfer
= NULL
;
576 as
->next_transfer
= NULL
;
578 /* continue if needed */
579 if (list_empty(&as
->queue
) || as
->stopping
)
580 spi_writel(as
, PTCR
, SPI_BIT(RXTDIS
) | SPI_BIT(TXTDIS
));
582 atmel_spi_next_message(master
);
586 atmel_spi_interrupt(int irq
, void *dev_id
)
588 struct spi_master
*master
= dev_id
;
589 struct atmel_spi
*as
= spi_master_get_devdata(master
);
590 struct spi_message
*msg
;
591 struct spi_transfer
*xfer
;
592 u32 status
, pending
, imr
;
595 spin_lock(&as
->lock
);
597 xfer
= as
->current_transfer
;
598 msg
= list_entry(as
->queue
.next
, struct spi_message
, queue
);
600 imr
= spi_readl(as
, IMR
);
601 status
= spi_readl(as
, SR
);
602 pending
= status
& imr
;
604 if (pending
& SPI_BIT(OVRES
)) {
609 spi_writel(as
, IDR
, (SPI_BIT(RXBUFF
) | SPI_BIT(ENDRX
)
613 * When we get an overrun, we disregard the current
614 * transfer. Data will not be copied back from any
615 * bounce buffer and msg->actual_len will not be
616 * updated with the last xfer.
618 * We will also not process any remaning transfers in
621 * First, stop the transfer and unmap the DMA buffers.
623 spi_writel(as
, PTCR
, SPI_BIT(RXTDIS
) | SPI_BIT(TXTDIS
));
624 if (!msg
->is_dma_mapped
)
625 atmel_spi_dma_unmap_xfer(master
, xfer
);
627 /* REVISIT: udelay in irq is unfriendly */
628 if (xfer
->delay_usecs
)
629 udelay(xfer
->delay_usecs
);
631 dev_warn(master
->dev
.parent
, "overrun (%u/%u remaining)\n",
632 spi_readl(as
, TCR
), spi_readl(as
, RCR
));
635 * Clean up DMA registers and make sure the data
636 * registers are empty.
638 spi_writel(as
, RNCR
, 0);
639 spi_writel(as
, TNCR
, 0);
640 spi_writel(as
, RCR
, 0);
641 spi_writel(as
, TCR
, 0);
642 for (timeout
= 1000; timeout
; timeout
--)
643 if (spi_readl(as
, SR
) & SPI_BIT(TXEMPTY
))
646 dev_warn(master
->dev
.parent
,
647 "timeout waiting for TXEMPTY");
648 while (spi_readl(as
, SR
) & SPI_BIT(RDRF
))
651 /* Clear any overrun happening while cleaning up */
654 atmel_spi_msg_done(master
, as
, msg
, -EIO
, 0);
655 } else if (pending
& (SPI_BIT(RXBUFF
) | SPI_BIT(ENDRX
))) {
658 spi_writel(as
, IDR
, pending
);
660 if (as
->current_remaining_bytes
== 0) {
661 msg
->actual_length
+= xfer
->len
;
663 if (!msg
->is_dma_mapped
)
664 atmel_spi_dma_unmap_xfer(master
, xfer
);
666 /* REVISIT: udelay in irq is unfriendly */
667 if (xfer
->delay_usecs
)
668 udelay(xfer
->delay_usecs
);
670 if (atmel_spi_xfer_is_last(msg
, xfer
)) {
671 /* report completed message */
672 atmel_spi_msg_done(master
, as
, msg
, 0,
675 if (xfer
->cs_change
) {
676 cs_deactivate(as
, msg
->spi
);
678 cs_activate(as
, msg
->spi
);
682 * Not done yet. Submit the next transfer.
684 * FIXME handle protocol options for xfer
686 atmel_spi_next_xfer(master
, msg
);
690 * Keep going, we still have data to send in
691 * the current transfer.
693 atmel_spi_next_xfer(master
, msg
);
697 spin_unlock(&as
->lock
);
702 static int atmel_spi_setup(struct spi_device
*spi
)
704 struct atmel_spi
*as
;
705 struct atmel_spi_device
*asd
;
707 unsigned int bits
= spi
->bits_per_word
;
708 unsigned long bus_hz
;
709 unsigned int npcs_pin
;
712 as
= spi_master_get_devdata(spi
->master
);
717 if (spi
->chip_select
> spi
->master
->num_chipselect
) {
719 "setup: invalid chipselect %u (%u defined)\n",
720 spi
->chip_select
, spi
->master
->num_chipselect
);
724 if (bits
< 8 || bits
> 16) {
726 "setup: invalid bits_per_word %u (8 to 16)\n",
731 /* see notes above re chipselect */
732 if (!atmel_spi_is_v2(as
)
733 && spi
->chip_select
== 0
734 && (spi
->mode
& SPI_CS_HIGH
)) {
735 dev_dbg(&spi
->dev
, "setup: can't be active-high\n");
739 /* v1 chips start out at half the peripheral bus speed. */
740 bus_hz
= clk_get_rate(as
->clk
);
741 if (!atmel_spi_is_v2(as
))
744 if (spi
->max_speed_hz
) {
746 * Calculate the lowest divider that satisfies the
747 * constraint, assuming div32/fdiv/mbz == 0.
749 scbr
= DIV_ROUND_UP(bus_hz
, spi
->max_speed_hz
);
752 * If the resulting divider doesn't fit into the
753 * register bitfield, we can't satisfy the constraint.
755 if (scbr
>= (1 << SPI_SCBR_SIZE
)) {
757 "setup: %d Hz too slow, scbr %u; min %ld Hz\n",
758 spi
->max_speed_hz
, scbr
, bus_hz
/255);
762 /* speed zero means "as slow as possible" */
765 csr
= SPI_BF(SCBR
, scbr
) | SPI_BF(BITS
, bits
- 8);
766 if (spi
->mode
& SPI_CPOL
)
767 csr
|= SPI_BIT(CPOL
);
768 if (!(spi
->mode
& SPI_CPHA
))
769 csr
|= SPI_BIT(NCPHA
);
771 /* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
773 * DLYBCT would add delays between words, slowing down transfers.
774 * It could potentially be useful to cope with DMA bottlenecks, but
775 * in those cases it's probably best to just use a lower bitrate.
777 csr
|= SPI_BF(DLYBS
, 0);
778 csr
|= SPI_BF(DLYBCT
, 0);
780 /* chipselect must have been muxed as GPIO (e.g. in board setup) */
781 npcs_pin
= (unsigned int)spi
->controller_data
;
783 if (gpio_is_valid(spi
->cs_gpio
))
784 npcs_pin
= spi
->cs_gpio
;
786 asd
= spi
->controller_state
;
788 asd
= kzalloc(sizeof(struct atmel_spi_device
), GFP_KERNEL
);
792 ret
= gpio_request(npcs_pin
, dev_name(&spi
->dev
));
798 asd
->npcs_pin
= npcs_pin
;
799 spi
->controller_state
= asd
;
800 gpio_direction_output(npcs_pin
, !(spi
->mode
& SPI_CS_HIGH
));
804 spin_lock_irqsave(&as
->lock
, flags
);
807 cs_deactivate(as
, spi
);
808 spin_unlock_irqrestore(&as
->lock
, flags
);
814 "setup: %lu Hz bpw %u mode 0x%x -> csr%d %08x\n",
815 bus_hz
/ scbr
, bits
, spi
->mode
, spi
->chip_select
, csr
);
817 if (!atmel_spi_is_v2(as
))
818 spi_writel(as
, CSR0
+ 4 * spi
->chip_select
, csr
);
823 static int atmel_spi_transfer(struct spi_device
*spi
, struct spi_message
*msg
)
825 struct atmel_spi
*as
;
826 struct spi_transfer
*xfer
;
828 struct device
*controller
= spi
->master
->dev
.parent
;
830 struct atmel_spi_device
*asd
;
832 as
= spi_master_get_devdata(spi
->master
);
834 dev_dbg(controller
, "new message %p submitted for %s\n",
835 msg
, dev_name(&spi
->dev
));
837 if (unlikely(list_empty(&msg
->transfers
)))
843 list_for_each_entry(xfer
, &msg
->transfers
, transfer_list
) {
844 if (!(xfer
->tx_buf
|| xfer
->rx_buf
) && xfer
->len
) {
845 dev_dbg(&spi
->dev
, "missing rx or tx buf\n");
849 if (xfer
->bits_per_word
) {
850 asd
= spi
->controller_state
;
851 bits
= (asd
->csr
>> 4) & 0xf;
852 if (bits
!= xfer
->bits_per_word
- 8) {
853 dev_dbg(&spi
->dev
, "you can't yet change "
854 "bits_per_word in transfers\n");
859 /* FIXME implement these protocol options!! */
860 if (xfer
->speed_hz
) {
861 dev_dbg(&spi
->dev
, "no protocol options yet\n");
866 * DMA map early, for performance (empties dcache ASAP) and
867 * better fault reporting. This is a DMA-only driver.
869 * NOTE that if dma_unmap_single() ever starts to do work on
870 * platforms supported by this driver, we would need to clean
871 * up mappings for previously-mapped transfers.
873 if (!msg
->is_dma_mapped
) {
874 if (atmel_spi_dma_map_xfer(as
, xfer
) < 0)
880 list_for_each_entry(xfer
, &msg
->transfers
, transfer_list
) {
882 " xfer %p: len %u tx %p/%08x rx %p/%08x\n",
884 xfer
->tx_buf
, xfer
->tx_dma
,
885 xfer
->rx_buf
, xfer
->rx_dma
);
889 msg
->status
= -EINPROGRESS
;
890 msg
->actual_length
= 0;
892 spin_lock_irqsave(&as
->lock
, flags
);
893 list_add_tail(&msg
->queue
, &as
->queue
);
894 if (!as
->current_transfer
)
895 atmel_spi_next_message(spi
->master
);
896 spin_unlock_irqrestore(&as
->lock
, flags
);
901 static void atmel_spi_cleanup(struct spi_device
*spi
)
903 struct atmel_spi
*as
= spi_master_get_devdata(spi
->master
);
904 struct atmel_spi_device
*asd
= spi
->controller_state
;
905 unsigned gpio
= (unsigned) spi
->controller_data
;
911 spin_lock_irqsave(&as
->lock
, flags
);
912 if (as
->stay
== spi
) {
914 cs_deactivate(as
, spi
);
916 spin_unlock_irqrestore(&as
->lock
, flags
);
918 spi
->controller_state
= NULL
;
923 static inline unsigned int atmel_get_version(struct atmel_spi
*as
)
925 return spi_readl(as
, VERSION
) & 0x00000fff;
928 static void atmel_get_caps(struct atmel_spi
*as
)
930 unsigned int version
;
932 version
= atmel_get_version(as
);
933 dev_info(&as
->pdev
->dev
, "version: 0x%x\n", version
);
935 as
->caps
.is_spi2
= version
> 0x121;
936 as
->caps
.has_wdrbt
= version
>= 0x210;
937 as
->caps
.has_dma_support
= version
>= 0x212;
940 /*-------------------------------------------------------------------------*/
942 static int atmel_spi_probe(struct platform_device
*pdev
)
944 struct resource
*regs
;
948 struct spi_master
*master
;
949 struct atmel_spi
*as
;
951 regs
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
955 irq
= platform_get_irq(pdev
, 0);
959 clk
= clk_get(&pdev
->dev
, "spi_clk");
963 /* setup spi core then atmel-specific driver state */
965 master
= spi_alloc_master(&pdev
->dev
, sizeof *as
);
969 /* the spi->mode bits understood by this driver: */
970 master
->mode_bits
= SPI_CPOL
| SPI_CPHA
| SPI_CS_HIGH
;
972 master
->dev
.of_node
= pdev
->dev
.of_node
;
973 master
->bus_num
= pdev
->id
;
974 master
->num_chipselect
= master
->dev
.of_node
? 0 : 4;
975 master
->setup
= atmel_spi_setup
;
976 master
->transfer
= atmel_spi_transfer
;
977 master
->cleanup
= atmel_spi_cleanup
;
978 platform_set_drvdata(pdev
, master
);
980 as
= spi_master_get_devdata(master
);
983 * Scratch buffer is used for throwaway rx and tx data.
984 * It's coherent to minimize dcache pollution.
986 as
->buffer
= dma_alloc_coherent(&pdev
->dev
, BUFFER_SIZE
,
987 &as
->buffer_dma
, GFP_KERNEL
);
991 spin_lock_init(&as
->lock
);
992 INIT_LIST_HEAD(&as
->queue
);
994 as
->regs
= ioremap(regs
->start
, resource_size(regs
));
996 goto out_free_buffer
;
1002 ret
= request_irq(irq
, atmel_spi_interrupt
, 0,
1003 dev_name(&pdev
->dev
), master
);
1005 goto out_unmap_regs
;
1007 /* Initialize the hardware */
1009 spi_writel(as
, CR
, SPI_BIT(SWRST
));
1010 spi_writel(as
, CR
, SPI_BIT(SWRST
)); /* AT91SAM9263 Rev B workaround */
1011 if (as
->caps
.has_wdrbt
) {
1012 spi_writel(as
, MR
, SPI_BIT(WDRBT
) | SPI_BIT(MODFDIS
)
1015 spi_writel(as
, MR
, SPI_BIT(MSTR
) | SPI_BIT(MODFDIS
));
1017 spi_writel(as
, PTCR
, SPI_BIT(RXTDIS
) | SPI_BIT(TXTDIS
));
1018 spi_writel(as
, CR
, SPI_BIT(SPIEN
));
1021 dev_info(&pdev
->dev
, "Atmel SPI Controller at 0x%08lx (irq %d)\n",
1022 (unsigned long)regs
->start
, irq
);
1024 ret
= spi_register_master(master
);
1031 spi_writel(as
, CR
, SPI_BIT(SWRST
));
1032 spi_writel(as
, CR
, SPI_BIT(SWRST
)); /* AT91SAM9263 Rev B workaround */
1034 free_irq(irq
, master
);
1038 dma_free_coherent(&pdev
->dev
, BUFFER_SIZE
, as
->buffer
,
1042 spi_master_put(master
);
1046 static int atmel_spi_remove(struct platform_device
*pdev
)
1048 struct spi_master
*master
= platform_get_drvdata(pdev
);
1049 struct atmel_spi
*as
= spi_master_get_devdata(master
);
1050 struct spi_message
*msg
;
1052 /* reset the hardware and block queue progress */
1053 spin_lock_irq(&as
->lock
);
1055 spi_writel(as
, CR
, SPI_BIT(SWRST
));
1056 spi_writel(as
, CR
, SPI_BIT(SWRST
)); /* AT91SAM9263 Rev B workaround */
1058 spin_unlock_irq(&as
->lock
);
1060 /* Terminate remaining queued transfers */
1061 list_for_each_entry(msg
, &as
->queue
, queue
) {
1062 /* REVISIT unmapping the dma is a NOP on ARM and AVR32
1063 * but we shouldn't depend on that...
1065 msg
->status
= -ESHUTDOWN
;
1066 msg
->complete(msg
->context
);
1069 dma_free_coherent(&pdev
->dev
, BUFFER_SIZE
, as
->buffer
,
1072 clk_disable(as
->clk
);
1074 free_irq(as
->irq
, master
);
1077 spi_unregister_master(master
);
1084 static int atmel_spi_suspend(struct platform_device
*pdev
, pm_message_t mesg
)
1086 struct spi_master
*master
= platform_get_drvdata(pdev
);
1087 struct atmel_spi
*as
= spi_master_get_devdata(master
);
1089 clk_disable(as
->clk
);
1093 static int atmel_spi_resume(struct platform_device
*pdev
)
1095 struct spi_master
*master
= platform_get_drvdata(pdev
);
1096 struct atmel_spi
*as
= spi_master_get_devdata(master
);
1098 clk_enable(as
->clk
);
1103 #define atmel_spi_suspend NULL
1104 #define atmel_spi_resume NULL
1107 #if defined(CONFIG_OF)
1108 static const struct of_device_id atmel_spi_dt_ids
[] = {
1109 { .compatible
= "atmel,at91rm9200-spi" },
1113 MODULE_DEVICE_TABLE(of
, atmel_spi_dt_ids
);
1116 static struct platform_driver atmel_spi_driver
= {
1118 .name
= "atmel_spi",
1119 .owner
= THIS_MODULE
,
1120 .of_match_table
= of_match_ptr(atmel_spi_dt_ids
),
1122 .suspend
= atmel_spi_suspend
,
1123 .resume
= atmel_spi_resume
,
1124 .probe
= atmel_spi_probe
,
1125 .remove
= atmel_spi_remove
,
1127 module_platform_driver(atmel_spi_driver
);
1129 MODULE_DESCRIPTION("Atmel AT32/AT91 SPI Controller driver");
1130 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1131 MODULE_LICENSE("GPL");
1132 MODULE_ALIAS("platform:atmel_spi");