1 // SPDX-License-Identifier: GPL-2.0-only
3 * Marvell Orion SPI controller driver
5 * Author: Shadi Ammouri <shadi@marvell.com>
6 * Copyright (C) 2007-2008 Marvell Ltd.
9 #include <linux/interrupt.h>
10 #include <linux/delay.h>
11 #include <linux/platform_device.h>
12 #include <linux/err.h>
14 #include <linux/spi/spi.h>
15 #include <linux/module.h>
16 #include <linux/pm_runtime.h>
18 #include <linux/of_address.h>
19 #include <linux/of_device.h>
20 #include <linux/clk.h>
21 #include <linux/sizes.h>
22 #include <asm/unaligned.h>
24 #define DRIVER_NAME "orion_spi"
26 /* Runtime PM autosuspend timeout: PM is fairly light on this driver */
27 #define SPI_AUTOSUSPEND_TIMEOUT 200
29 /* Some SoCs using this driver support up to 8 chip selects.
30 * It is up to the implementer to only use the chip selects
33 #define ORION_NUM_CHIPSELECTS 8
35 #define ORION_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */
37 #define ORION_SPI_IF_CTRL_REG 0x00
38 #define ORION_SPI_IF_CONFIG_REG 0x04
39 #define ORION_SPI_IF_RXLSBF BIT(14)
40 #define ORION_SPI_IF_TXLSBF BIT(13)
41 #define ORION_SPI_DATA_OUT_REG 0x08
42 #define ORION_SPI_DATA_IN_REG 0x0c
43 #define ORION_SPI_INT_CAUSE_REG 0x10
44 #define ORION_SPI_TIMING_PARAMS_REG 0x18
46 /* Register for the "Direct Mode" */
47 #define SPI_DIRECT_WRITE_CONFIG_REG 0x20
49 #define ORION_SPI_TMISO_SAMPLE_MASK (0x3 << 6)
50 #define ORION_SPI_TMISO_SAMPLE_1 (1 << 6)
51 #define ORION_SPI_TMISO_SAMPLE_2 (2 << 6)
53 #define ORION_SPI_MODE_CPOL (1 << 11)
54 #define ORION_SPI_MODE_CPHA (1 << 12)
55 #define ORION_SPI_IF_8_16_BIT_MODE (1 << 5)
56 #define ORION_SPI_CLK_PRESCALE_MASK 0x1F
57 #define ARMADA_SPI_CLK_PRESCALE_MASK 0xDF
58 #define ORION_SPI_MODE_MASK (ORION_SPI_MODE_CPOL | \
60 #define ORION_SPI_CS_MASK 0x1C
61 #define ORION_SPI_CS_SHIFT 2
62 #define ORION_SPI_CS(cs) ((cs << ORION_SPI_CS_SHIFT) & \
70 struct orion_spi_dev
{
71 enum orion_spi_type typ
;
73 * min_divisor and max_hz should be exclusive, the only we can
74 * have both is for managing the armada-370-spi case with old
78 unsigned int min_divisor
;
79 unsigned int max_divisor
;
81 bool is_errata_50mhz_ac
;
84 struct orion_direct_acc
{
89 struct orion_child_options
{
90 struct orion_direct_acc direct_access
;
94 struct spi_master
*master
;
98 const struct orion_spi_dev
*devdata
;
101 struct orion_child_options child
[ORION_NUM_CHIPSELECTS
];
105 static int orion_spi_runtime_suspend(struct device
*dev
);
106 static int orion_spi_runtime_resume(struct device
*dev
);
109 static inline void __iomem
*spi_reg(struct orion_spi
*orion_spi
, u32 reg
)
111 return orion_spi
->base
+ reg
;
115 orion_spi_setbits(struct orion_spi
*orion_spi
, u32 reg
, u32 mask
)
117 void __iomem
*reg_addr
= spi_reg(orion_spi
, reg
);
120 val
= readl(reg_addr
);
122 writel(val
, reg_addr
);
126 orion_spi_clrbits(struct orion_spi
*orion_spi
, u32 reg
, u32 mask
)
128 void __iomem
*reg_addr
= spi_reg(orion_spi
, reg
);
131 val
= readl(reg_addr
);
133 writel(val
, reg_addr
);
136 static int orion_spi_baudrate_set(struct spi_device
*spi
, unsigned int speed
)
142 struct orion_spi
*orion_spi
;
143 const struct orion_spi_dev
*devdata
;
145 orion_spi
= spi_master_get_devdata(spi
->master
);
146 devdata
= orion_spi
->devdata
;
148 tclk_hz
= clk_get_rate(orion_spi
->clk
);
150 if (devdata
->typ
== ARMADA_SPI
) {
152 * Given the core_clk (tclk_hz) and the target rate (speed) we
153 * determine the best values for SPR (in [0 .. 15]) and SPPR (in
156 * core_clk / (SPR * 2 ** SPPR)
158 * is as big as possible but not bigger than speed.
161 /* best integer divider: */
162 unsigned divider
= DIV_ROUND_UP(tclk_hz
, speed
);
166 /* This is the easy case, divider is less than 16 */
171 unsigned two_pow_sppr
;
173 * Find the highest bit set in divider. This and the
174 * three next bits define SPR (apart from rounding).
175 * SPPR is then the number of zero bits that must be
178 sppr
= fls(divider
) - 4;
181 * As SPR only has 4 bits, we have to round divider up
182 * to the next multiple of 2 ** sppr.
184 two_pow_sppr
= 1 << sppr
;
185 divider
= (divider
+ two_pow_sppr
- 1) & -two_pow_sppr
;
188 * recalculate sppr as rounding up divider might have
189 * increased it enough to change the position of the
190 * highest set bit. In this case the bit that now
191 * doesn't make it into SPR is 0, so there is no need to
194 sppr
= fls(divider
) - 4;
195 spr
= divider
>> sppr
;
198 * Now do range checking. SPR is constructed to have a
199 * width of 4 bits, so this is fine for sure. So we
200 * still need to check for sppr to fit into 3 bits:
206 prescale
= ((sppr
& 0x6) << 5) | ((sppr
& 0x1) << 4) | spr
;
209 * the supported rates are: 4,6,8...30
210 * round up as we look for equal or less speed
212 rate
= DIV_ROUND_UP(tclk_hz
, speed
);
213 rate
= roundup(rate
, 2);
215 /* check if requested speed is too small */
222 /* Convert the rate to SPI clock divisor value. */
223 prescale
= 0x10 + rate
/2;
226 reg
= readl(spi_reg(orion_spi
, ORION_SPI_IF_CONFIG_REG
));
227 reg
= ((reg
& ~devdata
->prescale_mask
) | prescale
);
228 writel(reg
, spi_reg(orion_spi
, ORION_SPI_IF_CONFIG_REG
));
234 orion_spi_mode_set(struct spi_device
*spi
)
237 struct orion_spi
*orion_spi
;
239 orion_spi
= spi_master_get_devdata(spi
->master
);
241 reg
= readl(spi_reg(orion_spi
, ORION_SPI_IF_CONFIG_REG
));
242 reg
&= ~ORION_SPI_MODE_MASK
;
243 if (spi
->mode
& SPI_CPOL
)
244 reg
|= ORION_SPI_MODE_CPOL
;
245 if (spi
->mode
& SPI_CPHA
)
246 reg
|= ORION_SPI_MODE_CPHA
;
247 if (spi
->mode
& SPI_LSB_FIRST
)
248 reg
|= ORION_SPI_IF_RXLSBF
| ORION_SPI_IF_TXLSBF
;
250 reg
&= ~(ORION_SPI_IF_RXLSBF
| ORION_SPI_IF_TXLSBF
);
252 writel(reg
, spi_reg(orion_spi
, ORION_SPI_IF_CONFIG_REG
));
256 orion_spi_50mhz_ac_timing_erratum(struct spi_device
*spi
, unsigned int speed
)
259 struct orion_spi
*orion_spi
;
261 orion_spi
= spi_master_get_devdata(spi
->master
);
264 * Erratum description: (Erratum NO. FE-9144572) The device
265 * SPI interface supports frequencies of up to 50 MHz.
266 * However, due to this erratum, when the device core clock is
267 * 250 MHz and the SPI interfaces is configured for 50MHz SPI
268 * clock and CPOL=CPHA=1 there might occur data corruption on
269 * reads from the SPI device.
270 * Erratum Workaround:
271 * Work in one of the following configurations:
272 * 1. Set CPOL=CPHA=0 in "SPI Interface Configuration
274 * 2. Set TMISO_SAMPLE value to 0x2 in "SPI Timing Parameters 1
275 * Register" before setting the interface.
277 reg
= readl(spi_reg(orion_spi
, ORION_SPI_TIMING_PARAMS_REG
));
278 reg
&= ~ORION_SPI_TMISO_SAMPLE_MASK
;
280 if (clk_get_rate(orion_spi
->clk
) == 250000000 &&
281 speed
== 50000000 && spi
->mode
& SPI_CPOL
&&
282 spi
->mode
& SPI_CPHA
)
283 reg
|= ORION_SPI_TMISO_SAMPLE_2
;
285 reg
|= ORION_SPI_TMISO_SAMPLE_1
; /* This is the default value */
287 writel(reg
, spi_reg(orion_spi
, ORION_SPI_TIMING_PARAMS_REG
));
291 * called only when no transfer is active on the bus
294 orion_spi_setup_transfer(struct spi_device
*spi
, struct spi_transfer
*t
)
296 struct orion_spi
*orion_spi
;
297 unsigned int speed
= spi
->max_speed_hz
;
298 unsigned int bits_per_word
= spi
->bits_per_word
;
301 orion_spi
= spi_master_get_devdata(spi
->master
);
303 if ((t
!= NULL
) && t
->speed_hz
)
306 if ((t
!= NULL
) && t
->bits_per_word
)
307 bits_per_word
= t
->bits_per_word
;
309 orion_spi_mode_set(spi
);
311 if (orion_spi
->devdata
->is_errata_50mhz_ac
)
312 orion_spi_50mhz_ac_timing_erratum(spi
, speed
);
314 rc
= orion_spi_baudrate_set(spi
, speed
);
318 if (bits_per_word
== 16)
319 orion_spi_setbits(orion_spi
, ORION_SPI_IF_CONFIG_REG
,
320 ORION_SPI_IF_8_16_BIT_MODE
);
322 orion_spi_clrbits(orion_spi
, ORION_SPI_IF_CONFIG_REG
,
323 ORION_SPI_IF_8_16_BIT_MODE
);
328 static void orion_spi_set_cs(struct spi_device
*spi
, bool enable
)
330 struct orion_spi
*orion_spi
;
331 void __iomem
*ctrl_reg
;
334 orion_spi
= spi_master_get_devdata(spi
->master
);
335 ctrl_reg
= spi_reg(orion_spi
, ORION_SPI_IF_CTRL_REG
);
337 val
= readl(ctrl_reg
);
339 /* Clear existing chip-select and assertion state */
340 val
&= ~(ORION_SPI_CS_MASK
| 0x1);
343 * If this line is using a GPIO to control chip select, this internal
344 * .set_cs() function will still be called, so we clear any previous
345 * chip select. The CS we activate will not have any elecrical effect,
346 * as it is handled by a GPIO, but that doesn't matter. What we need
347 * is to deassert the old chip select and assert some other chip select.
349 val
|= ORION_SPI_CS(spi
->chip_select
);
352 * Chip select logic is inverted from spi_set_cs(). For lines using a
353 * GPIO to do chip select SPI_CS_HIGH is enforced and inversion happens
354 * in the GPIO library, but we don't care about that, because in those
355 * cases we are dealing with an unused native CS anyways so the polarity
362 * To avoid toggling unwanted chip selects update the register
363 * with a single write.
365 writel(val
, ctrl_reg
);
368 static inline int orion_spi_wait_till_ready(struct orion_spi
*orion_spi
)
372 for (i
= 0; i
< ORION_SPI_WAIT_RDY_MAX_LOOP
; i
++) {
373 if (readl(spi_reg(orion_spi
, ORION_SPI_INT_CAUSE_REG
)))
383 orion_spi_write_read_8bit(struct spi_device
*spi
,
384 const u8
**tx_buf
, u8
**rx_buf
)
386 void __iomem
*tx_reg
, *rx_reg
, *int_reg
;
387 struct orion_spi
*orion_spi
;
390 cs_single_byte
= spi
->mode
& SPI_CS_WORD
;
392 orion_spi
= spi_master_get_devdata(spi
->master
);
395 orion_spi_set_cs(spi
, 0);
397 tx_reg
= spi_reg(orion_spi
, ORION_SPI_DATA_OUT_REG
);
398 rx_reg
= spi_reg(orion_spi
, ORION_SPI_DATA_IN_REG
);
399 int_reg
= spi_reg(orion_spi
, ORION_SPI_INT_CAUSE_REG
);
401 /* clear the interrupt cause register */
402 writel(0x0, int_reg
);
404 if (tx_buf
&& *tx_buf
)
405 writel(*(*tx_buf
)++, tx_reg
);
409 if (orion_spi_wait_till_ready(orion_spi
) < 0) {
410 if (cs_single_byte
) {
411 orion_spi_set_cs(spi
, 1);
412 /* Satisfy some SLIC devices requirements */
415 dev_err(&spi
->dev
, "TXS timed out\n");
419 if (rx_buf
&& *rx_buf
)
420 *(*rx_buf
)++ = readl(rx_reg
);
422 if (cs_single_byte
) {
423 orion_spi_set_cs(spi
, 1);
424 /* Satisfy some SLIC devices requirements */
432 orion_spi_write_read_16bit(struct spi_device
*spi
,
433 const u16
**tx_buf
, u16
**rx_buf
)
435 void __iomem
*tx_reg
, *rx_reg
, *int_reg
;
436 struct orion_spi
*orion_spi
;
438 if (spi
->mode
& SPI_CS_WORD
) {
439 dev_err(&spi
->dev
, "SPI_CS_WORD is only supported for 8 bit words\n");
443 orion_spi
= spi_master_get_devdata(spi
->master
);
444 tx_reg
= spi_reg(orion_spi
, ORION_SPI_DATA_OUT_REG
);
445 rx_reg
= spi_reg(orion_spi
, ORION_SPI_DATA_IN_REG
);
446 int_reg
= spi_reg(orion_spi
, ORION_SPI_INT_CAUSE_REG
);
448 /* clear the interrupt cause register */
449 writel(0x0, int_reg
);
451 if (tx_buf
&& *tx_buf
)
452 writel(__cpu_to_le16(get_unaligned((*tx_buf
)++)), tx_reg
);
456 if (orion_spi_wait_till_ready(orion_spi
) < 0) {
457 dev_err(&spi
->dev
, "TXS timed out\n");
461 if (rx_buf
&& *rx_buf
)
462 put_unaligned(__le16_to_cpu(readl(rx_reg
)), (*rx_buf
)++);
468 orion_spi_write_read(struct spi_device
*spi
, struct spi_transfer
*xfer
)
472 struct orion_spi
*orion_spi
;
473 int cs
= spi
->chip_select
;
476 word_len
= spi
->bits_per_word
;
479 orion_spi
= spi_master_get_devdata(spi
->master
);
482 * Use SPI direct write mode if base address is available
483 * and SPI_CS_WORD flag is not set.
484 * Otherwise fall back to PIO mode for this transfer.
486 vaddr
= orion_spi
->child
[cs
].direct_access
.vaddr
;
488 if (vaddr
&& xfer
->tx_buf
&& word_len
== 8 && (spi
->mode
& SPI_CS_WORD
) == 0) {
489 unsigned int cnt
= count
/ 4;
490 unsigned int rem
= count
% 4;
493 * Send the TX-data to the SPI device via the direct
494 * mapped address window
496 iowrite32_rep(vaddr
, xfer
->tx_buf
, cnt
);
498 u32
*buf
= (u32
*)xfer
->tx_buf
;
500 iowrite8_rep(vaddr
, &buf
[cnt
], rem
);
507 const u8
*tx
= xfer
->tx_buf
;
508 u8
*rx
= xfer
->rx_buf
;
511 if (orion_spi_write_read_8bit(spi
, &tx
, &rx
) < 0)
514 spi_delay_exec(&xfer
->word_delay
, xfer
);
516 } else if (word_len
== 16) {
517 const u16
*tx
= xfer
->tx_buf
;
518 u16
*rx
= xfer
->rx_buf
;
521 if (orion_spi_write_read_16bit(spi
, &tx
, &rx
) < 0)
524 spi_delay_exec(&xfer
->word_delay
, xfer
);
529 return xfer
->len
- count
;
532 static int orion_spi_transfer_one(struct spi_master
*master
,
533 struct spi_device
*spi
,
534 struct spi_transfer
*t
)
538 status
= orion_spi_setup_transfer(spi
, t
);
543 orion_spi_write_read(spi
, t
);
548 static int orion_spi_setup(struct spi_device
*spi
)
552 struct orion_spi
*orion_spi
= spi_master_get_devdata(spi
->master
);
553 struct device
*dev
= orion_spi
->dev
;
555 orion_spi_runtime_resume(dev
);
558 ret
= orion_spi_setup_transfer(spi
, NULL
);
561 orion_spi_runtime_suspend(dev
);
567 static int orion_spi_reset(struct orion_spi
*orion_spi
)
569 /* Verify that the CS is deasserted */
570 orion_spi_clrbits(orion_spi
, ORION_SPI_IF_CTRL_REG
, 0x1);
572 /* Don't deassert CS between the direct mapped SPI transfers */
573 writel(0, spi_reg(orion_spi
, SPI_DIRECT_WRITE_CONFIG_REG
));
578 static const struct orion_spi_dev orion_spi_dev_data
= {
582 .prescale_mask
= ORION_SPI_CLK_PRESCALE_MASK
,
585 static const struct orion_spi_dev armada_370_spi_dev_data
= {
590 .prescale_mask
= ARMADA_SPI_CLK_PRESCALE_MASK
,
593 static const struct orion_spi_dev armada_xp_spi_dev_data
= {
597 .prescale_mask
= ARMADA_SPI_CLK_PRESCALE_MASK
,
600 static const struct orion_spi_dev armada_375_spi_dev_data
= {
604 .prescale_mask
= ARMADA_SPI_CLK_PRESCALE_MASK
,
607 static const struct orion_spi_dev armada_380_spi_dev_data
= {
611 .prescale_mask
= ARMADA_SPI_CLK_PRESCALE_MASK
,
612 .is_errata_50mhz_ac
= true,
615 static const struct of_device_id orion_spi_of_match_table
[] = {
617 .compatible
= "marvell,orion-spi",
618 .data
= &orion_spi_dev_data
,
621 .compatible
= "marvell,armada-370-spi",
622 .data
= &armada_370_spi_dev_data
,
625 .compatible
= "marvell,armada-375-spi",
626 .data
= &armada_375_spi_dev_data
,
629 .compatible
= "marvell,armada-380-spi",
630 .data
= &armada_380_spi_dev_data
,
633 .compatible
= "marvell,armada-390-spi",
634 .data
= &armada_xp_spi_dev_data
,
637 .compatible
= "marvell,armada-xp-spi",
638 .data
= &armada_xp_spi_dev_data
,
643 MODULE_DEVICE_TABLE(of
, orion_spi_of_match_table
);
645 static int orion_spi_probe(struct platform_device
*pdev
)
647 const struct orion_spi_dev
*devdata
;
648 struct spi_master
*master
;
649 struct orion_spi
*spi
;
651 unsigned long tclk_hz
;
653 struct device_node
*np
;
655 master
= spi_alloc_master(&pdev
->dev
, sizeof(*spi
));
656 if (master
== NULL
) {
657 dev_dbg(&pdev
->dev
, "master allocation failed\n");
662 master
->bus_num
= pdev
->id
;
663 if (pdev
->dev
.of_node
) {
666 if (!of_property_read_u32(pdev
->dev
.of_node
, "cell-index",
668 master
->bus_num
= cell_index
;
671 /* we support all 4 SPI modes and LSB first option */
672 master
->mode_bits
= SPI_CPHA
| SPI_CPOL
| SPI_LSB_FIRST
| SPI_CS_WORD
;
673 master
->set_cs
= orion_spi_set_cs
;
674 master
->transfer_one
= orion_spi_transfer_one
;
675 master
->num_chipselect
= ORION_NUM_CHIPSELECTS
;
676 master
->setup
= orion_spi_setup
;
677 master
->bits_per_word_mask
= SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
678 master
->auto_runtime_pm
= true;
679 master
->use_gpio_descriptors
= true;
680 master
->flags
= SPI_MASTER_GPIO_SS
;
682 platform_set_drvdata(pdev
, master
);
684 spi
= spi_master_get_devdata(master
);
685 spi
->master
= master
;
686 spi
->dev
= &pdev
->dev
;
688 devdata
= device_get_match_data(&pdev
->dev
);
689 devdata
= devdata
? devdata
: &orion_spi_dev_data
;
690 spi
->devdata
= devdata
;
692 spi
->clk
= devm_clk_get(&pdev
->dev
, NULL
);
693 if (IS_ERR(spi
->clk
)) {
694 status
= PTR_ERR(spi
->clk
);
698 status
= clk_prepare_enable(spi
->clk
);
702 /* The following clock is only used by some SoCs */
703 spi
->axi_clk
= devm_clk_get(&pdev
->dev
, "axi");
704 if (PTR_ERR(spi
->axi_clk
) == -EPROBE_DEFER
) {
705 status
= -EPROBE_DEFER
;
708 if (!IS_ERR(spi
->axi_clk
))
709 clk_prepare_enable(spi
->axi_clk
);
711 tclk_hz
= clk_get_rate(spi
->clk
);
714 * With old device tree, armada-370-spi could be used with
715 * Armada XP, however for this SoC the maximum frequency is
716 * 50MHz instead of tclk/4. On Armada 370, tclk cannot be
717 * higher than 200MHz. So, in order to be able to handle both
718 * SoCs, we can take the minimum of 50MHz and tclk/4.
720 if (of_device_is_compatible(pdev
->dev
.of_node
,
721 "marvell,armada-370-spi"))
722 master
->max_speed_hz
= min(devdata
->max_hz
,
723 DIV_ROUND_UP(tclk_hz
, devdata
->min_divisor
));
724 else if (devdata
->min_divisor
)
725 master
->max_speed_hz
=
726 DIV_ROUND_UP(tclk_hz
, devdata
->min_divisor
);
728 master
->max_speed_hz
= devdata
->max_hz
;
729 master
->min_speed_hz
= DIV_ROUND_UP(tclk_hz
, devdata
->max_divisor
);
731 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
732 spi
->base
= devm_ioremap_resource(&pdev
->dev
, r
);
733 if (IS_ERR(spi
->base
)) {
734 status
= PTR_ERR(spi
->base
);
735 goto out_rel_axi_clk
;
738 for_each_available_child_of_node(pdev
->dev
.of_node
, np
) {
739 struct orion_direct_acc
*dir_acc
;
742 /* Get chip-select number from the "reg" property */
743 status
= of_property_read_u32(np
, "reg", &cs
);
746 "%pOF has no valid 'reg' property (%d)\n",
752 * Check if an address is configured for this SPI device. If
753 * not, the MBus mapping via the 'ranges' property in the 'soc'
754 * node is not configured and this device should not use the
755 * direct mode. In this case, just continue with the next
758 status
= of_address_to_resource(pdev
->dev
.of_node
, cs
+ 1, r
);
763 * Only map one page for direct access. This is enough for the
764 * simple TX transfer which only writes to the first word.
765 * This needs to get extended for the direct SPI NOR / SPI NAND
766 * support, once this gets implemented.
768 dir_acc
= &spi
->child
[cs
].direct_access
;
769 dir_acc
->vaddr
= devm_ioremap(&pdev
->dev
, r
->start
, PAGE_SIZE
);
770 if (!dir_acc
->vaddr
) {
772 goto out_rel_axi_clk
;
774 dir_acc
->size
= PAGE_SIZE
;
776 dev_info(&pdev
->dev
, "CS%d configured for direct access\n", cs
);
779 pm_runtime_set_active(&pdev
->dev
);
780 pm_runtime_use_autosuspend(&pdev
->dev
);
781 pm_runtime_set_autosuspend_delay(&pdev
->dev
, SPI_AUTOSUSPEND_TIMEOUT
);
782 pm_runtime_enable(&pdev
->dev
);
784 status
= orion_spi_reset(spi
);
788 master
->dev
.of_node
= pdev
->dev
.of_node
;
789 status
= spi_register_master(master
);
796 pm_runtime_disable(&pdev
->dev
);
798 clk_disable_unprepare(spi
->axi_clk
);
800 clk_disable_unprepare(spi
->clk
);
802 spi_master_put(master
);
807 static int orion_spi_remove(struct platform_device
*pdev
)
809 struct spi_master
*master
= platform_get_drvdata(pdev
);
810 struct orion_spi
*spi
= spi_master_get_devdata(master
);
812 pm_runtime_get_sync(&pdev
->dev
);
813 clk_disable_unprepare(spi
->axi_clk
);
814 clk_disable_unprepare(spi
->clk
);
816 spi_unregister_master(master
);
817 pm_runtime_disable(&pdev
->dev
);
822 MODULE_ALIAS("platform:" DRIVER_NAME
);
825 static int orion_spi_runtime_suspend(struct device
*dev
)
827 struct spi_master
*master
= dev_get_drvdata(dev
);
828 struct orion_spi
*spi
= spi_master_get_devdata(master
);
830 clk_disable_unprepare(spi
->axi_clk
);
831 clk_disable_unprepare(spi
->clk
);
835 static int orion_spi_runtime_resume(struct device
*dev
)
837 struct spi_master
*master
= dev_get_drvdata(dev
);
838 struct orion_spi
*spi
= spi_master_get_devdata(master
);
840 if (!IS_ERR(spi
->axi_clk
))
841 clk_prepare_enable(spi
->axi_clk
);
842 return clk_prepare_enable(spi
->clk
);
846 static const struct dev_pm_ops orion_spi_pm_ops
= {
847 SET_RUNTIME_PM_OPS(orion_spi_runtime_suspend
,
848 orion_spi_runtime_resume
,
852 static struct platform_driver orion_spi_driver
= {
855 .pm
= &orion_spi_pm_ops
,
856 .of_match_table
= of_match_ptr(orion_spi_of_match_table
),
858 .probe
= orion_spi_probe
,
859 .remove
= orion_spi_remove
,
862 module_platform_driver(orion_spi_driver
);
864 MODULE_DESCRIPTION("Orion SPI driver");
865 MODULE_AUTHOR("Shadi Ammouri <shadi@marvell.com>");
866 MODULE_LICENSE("GPL");