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spi: bcm-qspi: Always read and set BSPI_MAST_N_BOOT_CTRL
[mirror_ubuntu-bionic-kernel.git] / drivers / spi / spi-sh-msiof.c
1 /*
2 * SuperH MSIOF SPI Master Interface
3 *
4 * Copyright (c) 2009 Magnus Damm
5 * Copyright (C) 2014 Renesas Electronics Corporation
6 * Copyright (C) 2014-2017 Glider bvba
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13
14 #include <linux/bitmap.h>
15 #include <linux/clk.h>
16 #include <linux/completion.h>
17 #include <linux/delay.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/dmaengine.h>
20 #include <linux/err.h>
21 #include <linux/gpio.h>
22 #include <linux/interrupt.h>
23 #include <linux/io.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/of.h>
27 #include <linux/of_device.h>
28 #include <linux/platform_device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/sh_dma.h>
31
32 #include <linux/spi/sh_msiof.h>
33 #include <linux/spi/spi.h>
34
35 #include <asm/unaligned.h>
36
37 struct sh_msiof_chipdata {
38 u16 tx_fifo_size;
39 u16 rx_fifo_size;
40 u16 master_flags;
41 u16 min_div;
42 };
43
44 struct sh_msiof_spi_priv {
45 struct spi_master *master;
46 void __iomem *mapbase;
47 struct clk *clk;
48 struct platform_device *pdev;
49 struct sh_msiof_spi_info *info;
50 struct completion done;
51 unsigned int tx_fifo_size;
52 unsigned int rx_fifo_size;
53 unsigned int min_div;
54 void *tx_dma_page;
55 void *rx_dma_page;
56 dma_addr_t tx_dma_addr;
57 dma_addr_t rx_dma_addr;
58 bool native_cs_inited;
59 bool native_cs_high;
60 bool slave_aborted;
61 };
62
63 #define TMDR1 0x00 /* Transmit Mode Register 1 */
64 #define TMDR2 0x04 /* Transmit Mode Register 2 */
65 #define TMDR3 0x08 /* Transmit Mode Register 3 */
66 #define RMDR1 0x10 /* Receive Mode Register 1 */
67 #define RMDR2 0x14 /* Receive Mode Register 2 */
68 #define RMDR3 0x18 /* Receive Mode Register 3 */
69 #define TSCR 0x20 /* Transmit Clock Select Register */
70 #define RSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */
71 #define CTR 0x28 /* Control Register */
72 #define FCTR 0x30 /* FIFO Control Register */
73 #define STR 0x40 /* Status Register */
74 #define IER 0x44 /* Interrupt Enable Register */
75 #define TDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */
76 #define TDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */
77 #define TFDR 0x50 /* Transmit FIFO Data Register */
78 #define RDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */
79 #define RDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */
80 #define RFDR 0x60 /* Receive FIFO Data Register */
81
82 /* TMDR1 and RMDR1 */
83 #define MDR1_TRMD 0x80000000 /* Transfer Mode (1 = Master mode) */
84 #define MDR1_SYNCMD_MASK 0x30000000 /* SYNC Mode */
85 #define MDR1_SYNCMD_SPI 0x20000000 /* Level mode/SPI */
86 #define MDR1_SYNCMD_LR 0x30000000 /* L/R mode */
87 #define MDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */
88 #define MDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */
89 #define MDR1_DTDL_SHIFT 20 /* Data Pin Bit Delay for MSIOF_SYNC */
90 #define MDR1_SYNCDL_SHIFT 16 /* Frame Sync Signal Timing Delay */
91 #define MDR1_FLD_MASK 0x0000000c /* Frame Sync Signal Interval (0-3) */
92 #define MDR1_FLD_SHIFT 2
93 #define MDR1_XXSTP 0x00000001 /* Transmission/Reception Stop on FIFO */
94 /* TMDR1 */
95 #define TMDR1_PCON 0x40000000 /* Transfer Signal Connection */
96
97 /* TMDR2 and RMDR2 */
98 #define MDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */
99 #define MDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */
100 #define MDR2_GRPMASK1 0x00000001 /* Group Output Mask 1 (SH, A1) */
101
102 /* TSCR and RSCR */
103 #define SCR_BRPS_MASK 0x1f00 /* Prescaler Setting (1-32) */
104 #define SCR_BRPS(i) (((i) - 1) << 8)
105 #define SCR_BRDV_MASK 0x0007 /* Baud Rate Generator's Division Ratio */
106 #define SCR_BRDV_DIV_2 0x0000
107 #define SCR_BRDV_DIV_4 0x0001
108 #define SCR_BRDV_DIV_8 0x0002
109 #define SCR_BRDV_DIV_16 0x0003
110 #define SCR_BRDV_DIV_32 0x0004
111 #define SCR_BRDV_DIV_1 0x0007
112
113 /* CTR */
114 #define CTR_TSCKIZ_MASK 0xc0000000 /* Transmit Clock I/O Polarity Select */
115 #define CTR_TSCKIZ_SCK 0x80000000 /* Disable SCK when TX disabled */
116 #define CTR_TSCKIZ_POL_SHIFT 30 /* Transmit Clock Polarity */
117 #define CTR_RSCKIZ_MASK 0x30000000 /* Receive Clock Polarity Select */
118 #define CTR_RSCKIZ_SCK 0x20000000 /* Must match CTR_TSCKIZ_SCK */
119 #define CTR_RSCKIZ_POL_SHIFT 28 /* Receive Clock Polarity */
120 #define CTR_TEDG_SHIFT 27 /* Transmit Timing (1 = falling edge) */
121 #define CTR_REDG_SHIFT 26 /* Receive Timing (1 = falling edge) */
122 #define CTR_TXDIZ_MASK 0x00c00000 /* Pin Output When TX is Disabled */
123 #define CTR_TXDIZ_LOW 0x00000000 /* 0 */
124 #define CTR_TXDIZ_HIGH 0x00400000 /* 1 */
125 #define CTR_TXDIZ_HIZ 0x00800000 /* High-impedance */
126 #define CTR_TSCKE 0x00008000 /* Transmit Serial Clock Output Enable */
127 #define CTR_TFSE 0x00004000 /* Transmit Frame Sync Signal Output Enable */
128 #define CTR_TXE 0x00000200 /* Transmit Enable */
129 #define CTR_RXE 0x00000100 /* Receive Enable */
130
131 /* FCTR */
132 #define FCTR_TFWM_MASK 0xe0000000 /* Transmit FIFO Watermark */
133 #define FCTR_TFWM_64 0x00000000 /* Transfer Request when 64 empty stages */
134 #define FCTR_TFWM_32 0x20000000 /* Transfer Request when 32 empty stages */
135 #define FCTR_TFWM_24 0x40000000 /* Transfer Request when 24 empty stages */
136 #define FCTR_TFWM_16 0x60000000 /* Transfer Request when 16 empty stages */
137 #define FCTR_TFWM_12 0x80000000 /* Transfer Request when 12 empty stages */
138 #define FCTR_TFWM_8 0xa0000000 /* Transfer Request when 8 empty stages */
139 #define FCTR_TFWM_4 0xc0000000 /* Transfer Request when 4 empty stages */
140 #define FCTR_TFWM_1 0xe0000000 /* Transfer Request when 1 empty stage */
141 #define FCTR_TFUA_MASK 0x07f00000 /* Transmit FIFO Usable Area */
142 #define FCTR_TFUA_SHIFT 20
143 #define FCTR_TFUA(i) ((i) << FCTR_TFUA_SHIFT)
144 #define FCTR_RFWM_MASK 0x0000e000 /* Receive FIFO Watermark */
145 #define FCTR_RFWM_1 0x00000000 /* Transfer Request when 1 valid stages */
146 #define FCTR_RFWM_4 0x00002000 /* Transfer Request when 4 valid stages */
147 #define FCTR_RFWM_8 0x00004000 /* Transfer Request when 8 valid stages */
148 #define FCTR_RFWM_16 0x00006000 /* Transfer Request when 16 valid stages */
149 #define FCTR_RFWM_32 0x00008000 /* Transfer Request when 32 valid stages */
150 #define FCTR_RFWM_64 0x0000a000 /* Transfer Request when 64 valid stages */
151 #define FCTR_RFWM_128 0x0000c000 /* Transfer Request when 128 valid stages */
152 #define FCTR_RFWM_256 0x0000e000 /* Transfer Request when 256 valid stages */
153 #define FCTR_RFUA_MASK 0x00001ff0 /* Receive FIFO Usable Area (0x40 = full) */
154 #define FCTR_RFUA_SHIFT 4
155 #define FCTR_RFUA(i) ((i) << FCTR_RFUA_SHIFT)
156
157 /* STR */
158 #define STR_TFEMP 0x20000000 /* Transmit FIFO Empty */
159 #define STR_TDREQ 0x10000000 /* Transmit Data Transfer Request */
160 #define STR_TEOF 0x00800000 /* Frame Transmission End */
161 #define STR_TFSERR 0x00200000 /* Transmit Frame Synchronization Error */
162 #define STR_TFOVF 0x00100000 /* Transmit FIFO Overflow */
163 #define STR_TFUDF 0x00080000 /* Transmit FIFO Underflow */
164 #define STR_RFFUL 0x00002000 /* Receive FIFO Full */
165 #define STR_RDREQ 0x00001000 /* Receive Data Transfer Request */
166 #define STR_REOF 0x00000080 /* Frame Reception End */
167 #define STR_RFSERR 0x00000020 /* Receive Frame Synchronization Error */
168 #define STR_RFUDF 0x00000010 /* Receive FIFO Underflow */
169 #define STR_RFOVF 0x00000008 /* Receive FIFO Overflow */
170
171 /* IER */
172 #define IER_TDMAE 0x80000000 /* Transmit Data DMA Transfer Req. Enable */
173 #define IER_TFEMPE 0x20000000 /* Transmit FIFO Empty Enable */
174 #define IER_TDREQE 0x10000000 /* Transmit Data Transfer Request Enable */
175 #define IER_TEOFE 0x00800000 /* Frame Transmission End Enable */
176 #define IER_TFSERRE 0x00200000 /* Transmit Frame Sync Error Enable */
177 #define IER_TFOVFE 0x00100000 /* Transmit FIFO Overflow Enable */
178 #define IER_TFUDFE 0x00080000 /* Transmit FIFO Underflow Enable */
179 #define IER_RDMAE 0x00008000 /* Receive Data DMA Transfer Req. Enable */
180 #define IER_RFFULE 0x00002000 /* Receive FIFO Full Enable */
181 #define IER_RDREQE 0x00001000 /* Receive Data Transfer Request Enable */
182 #define IER_REOFE 0x00000080 /* Frame Reception End Enable */
183 #define IER_RFSERRE 0x00000020 /* Receive Frame Sync Error Enable */
184 #define IER_RFUDFE 0x00000010 /* Receive FIFO Underflow Enable */
185 #define IER_RFOVFE 0x00000008 /* Receive FIFO Overflow Enable */
186
187
188 static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs)
189 {
190 switch (reg_offs) {
191 case TSCR:
192 case RSCR:
193 return ioread16(p->mapbase + reg_offs);
194 default:
195 return ioread32(p->mapbase + reg_offs);
196 }
197 }
198
199 static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs,
200 u32 value)
201 {
202 switch (reg_offs) {
203 case TSCR:
204 case RSCR:
205 iowrite16(value, p->mapbase + reg_offs);
206 break;
207 default:
208 iowrite32(value, p->mapbase + reg_offs);
209 break;
210 }
211 }
212
213 static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p,
214 u32 clr, u32 set)
215 {
216 u32 mask = clr | set;
217 u32 data;
218 int k;
219
220 data = sh_msiof_read(p, CTR);
221 data &= ~clr;
222 data |= set;
223 sh_msiof_write(p, CTR, data);
224
225 for (k = 100; k > 0; k--) {
226 if ((sh_msiof_read(p, CTR) & mask) == set)
227 break;
228
229 udelay(10);
230 }
231
232 return k > 0 ? 0 : -ETIMEDOUT;
233 }
234
235 static irqreturn_t sh_msiof_spi_irq(int irq, void *data)
236 {
237 struct sh_msiof_spi_priv *p = data;
238
239 /* just disable the interrupt and wake up */
240 sh_msiof_write(p, IER, 0);
241 complete(&p->done);
242
243 return IRQ_HANDLED;
244 }
245
246 static struct {
247 unsigned short div;
248 unsigned short brdv;
249 } const sh_msiof_spi_div_table[] = {
250 { 1, SCR_BRDV_DIV_1 },
251 { 2, SCR_BRDV_DIV_2 },
252 { 4, SCR_BRDV_DIV_4 },
253 { 8, SCR_BRDV_DIV_8 },
254 { 16, SCR_BRDV_DIV_16 },
255 { 32, SCR_BRDV_DIV_32 },
256 };
257
258 static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
259 unsigned long parent_rate, u32 spi_hz)
260 {
261 unsigned long div = 1024;
262 u32 brps, scr;
263 size_t k;
264
265 if (!WARN_ON(!spi_hz || !parent_rate))
266 div = DIV_ROUND_UP(parent_rate, spi_hz);
267
268 div = max_t(unsigned long, div, p->min_div);
269
270 for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_div_table); k++) {
271 brps = DIV_ROUND_UP(div, sh_msiof_spi_div_table[k].div);
272 /* SCR_BRDV_DIV_1 is valid only if BRPS is x 1/1 or x 1/2 */
273 if (sh_msiof_spi_div_table[k].div == 1 && brps > 2)
274 continue;
275 if (brps <= 32) /* max of brdv is 32 */
276 break;
277 }
278
279 k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_div_table) - 1);
280
281 scr = sh_msiof_spi_div_table[k].brdv | SCR_BRPS(brps);
282 sh_msiof_write(p, TSCR, scr);
283 if (!(p->master->flags & SPI_MASTER_MUST_TX))
284 sh_msiof_write(p, RSCR, scr);
285 }
286
287 static u32 sh_msiof_get_delay_bit(u32 dtdl_or_syncdl)
288 {
289 /*
290 * DTDL/SYNCDL bit : p->info->dtdl or p->info->syncdl
291 * b'000 : 0
292 * b'001 : 100
293 * b'010 : 200
294 * b'011 (SYNCDL only) : 300
295 * b'101 : 50
296 * b'110 : 150
297 */
298 if (dtdl_or_syncdl % 100)
299 return dtdl_or_syncdl / 100 + 5;
300 else
301 return dtdl_or_syncdl / 100;
302 }
303
304 static u32 sh_msiof_spi_get_dtdl_and_syncdl(struct sh_msiof_spi_priv *p)
305 {
306 u32 val;
307
308 if (!p->info)
309 return 0;
310
311 /* check if DTDL and SYNCDL is allowed value */
312 if (p->info->dtdl > 200 || p->info->syncdl > 300) {
313 dev_warn(&p->pdev->dev, "DTDL or SYNCDL is too large\n");
314 return 0;
315 }
316
317 /* check if the sum of DTDL and SYNCDL becomes an integer value */
318 if ((p->info->dtdl + p->info->syncdl) % 100) {
319 dev_warn(&p->pdev->dev, "the sum of DTDL/SYNCDL is not good\n");
320 return 0;
321 }
322
323 val = sh_msiof_get_delay_bit(p->info->dtdl) << MDR1_DTDL_SHIFT;
324 val |= sh_msiof_get_delay_bit(p->info->syncdl) << MDR1_SYNCDL_SHIFT;
325
326 return val;
327 }
328
329 static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p,
330 u32 cpol, u32 cpha,
331 u32 tx_hi_z, u32 lsb_first, u32 cs_high)
332 {
333 u32 tmp;
334 int edge;
335
336 /*
337 * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG
338 * 0 0 10 10 1 1
339 * 0 1 10 10 0 0
340 * 1 0 11 11 0 0
341 * 1 1 11 11 1 1
342 */
343 tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP;
344 tmp |= !cs_high << MDR1_SYNCAC_SHIFT;
345 tmp |= lsb_first << MDR1_BITLSB_SHIFT;
346 tmp |= sh_msiof_spi_get_dtdl_and_syncdl(p);
347 if (spi_controller_is_slave(p->master))
348 sh_msiof_write(p, TMDR1, tmp | TMDR1_PCON);
349 else
350 sh_msiof_write(p, TMDR1, tmp | MDR1_TRMD | TMDR1_PCON);
351 if (p->master->flags & SPI_MASTER_MUST_TX) {
352 /* These bits are reserved if RX needs TX */
353 tmp &= ~0x0000ffff;
354 }
355 sh_msiof_write(p, RMDR1, tmp);
356
357 tmp = 0;
358 tmp |= CTR_TSCKIZ_SCK | cpol << CTR_TSCKIZ_POL_SHIFT;
359 tmp |= CTR_RSCKIZ_SCK | cpol << CTR_RSCKIZ_POL_SHIFT;
360
361 edge = cpol ^ !cpha;
362
363 tmp |= edge << CTR_TEDG_SHIFT;
364 tmp |= edge << CTR_REDG_SHIFT;
365 tmp |= tx_hi_z ? CTR_TXDIZ_HIZ : CTR_TXDIZ_LOW;
366 sh_msiof_write(p, CTR, tmp);
367 }
368
369 static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p,
370 const void *tx_buf, void *rx_buf,
371 u32 bits, u32 words)
372 {
373 u32 dr2 = MDR2_BITLEN1(bits) | MDR2_WDLEN1(words);
374
375 if (tx_buf || (p->master->flags & SPI_MASTER_MUST_TX))
376 sh_msiof_write(p, TMDR2, dr2);
377 else
378 sh_msiof_write(p, TMDR2, dr2 | MDR2_GRPMASK1);
379
380 if (rx_buf)
381 sh_msiof_write(p, RMDR2, dr2);
382 }
383
384 static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p)
385 {
386 sh_msiof_write(p, STR, sh_msiof_read(p, STR));
387 }
388
389 static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p,
390 const void *tx_buf, int words, int fs)
391 {
392 const u8 *buf_8 = tx_buf;
393 int k;
394
395 for (k = 0; k < words; k++)
396 sh_msiof_write(p, TFDR, buf_8[k] << fs);
397 }
398
399 static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p,
400 const void *tx_buf, int words, int fs)
401 {
402 const u16 *buf_16 = tx_buf;
403 int k;
404
405 for (k = 0; k < words; k++)
406 sh_msiof_write(p, TFDR, buf_16[k] << fs);
407 }
408
409 static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p,
410 const void *tx_buf, int words, int fs)
411 {
412 const u16 *buf_16 = tx_buf;
413 int k;
414
415 for (k = 0; k < words; k++)
416 sh_msiof_write(p, TFDR, get_unaligned(&buf_16[k]) << fs);
417 }
418
419 static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p,
420 const void *tx_buf, int words, int fs)
421 {
422 const u32 *buf_32 = tx_buf;
423 int k;
424
425 for (k = 0; k < words; k++)
426 sh_msiof_write(p, TFDR, buf_32[k] << fs);
427 }
428
429 static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p,
430 const void *tx_buf, int words, int fs)
431 {
432 const u32 *buf_32 = tx_buf;
433 int k;
434
435 for (k = 0; k < words; k++)
436 sh_msiof_write(p, TFDR, get_unaligned(&buf_32[k]) << fs);
437 }
438
439 static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p,
440 const void *tx_buf, int words, int fs)
441 {
442 const u32 *buf_32 = tx_buf;
443 int k;
444
445 for (k = 0; k < words; k++)
446 sh_msiof_write(p, TFDR, swab32(buf_32[k] << fs));
447 }
448
449 static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p,
450 const void *tx_buf, int words, int fs)
451 {
452 const u32 *buf_32 = tx_buf;
453 int k;
454
455 for (k = 0; k < words; k++)
456 sh_msiof_write(p, TFDR, swab32(get_unaligned(&buf_32[k]) << fs));
457 }
458
459 static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p,
460 void *rx_buf, int words, int fs)
461 {
462 u8 *buf_8 = rx_buf;
463 int k;
464
465 for (k = 0; k < words; k++)
466 buf_8[k] = sh_msiof_read(p, RFDR) >> fs;
467 }
468
469 static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p,
470 void *rx_buf, int words, int fs)
471 {
472 u16 *buf_16 = rx_buf;
473 int k;
474
475 for (k = 0; k < words; k++)
476 buf_16[k] = sh_msiof_read(p, RFDR) >> fs;
477 }
478
479 static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p,
480 void *rx_buf, int words, int fs)
481 {
482 u16 *buf_16 = rx_buf;
483 int k;
484
485 for (k = 0; k < words; k++)
486 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_16[k]);
487 }
488
489 static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p,
490 void *rx_buf, int words, int fs)
491 {
492 u32 *buf_32 = rx_buf;
493 int k;
494
495 for (k = 0; k < words; k++)
496 buf_32[k] = sh_msiof_read(p, RFDR) >> fs;
497 }
498
499 static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p,
500 void *rx_buf, int words, int fs)
501 {
502 u32 *buf_32 = rx_buf;
503 int k;
504
505 for (k = 0; k < words; k++)
506 put_unaligned(sh_msiof_read(p, RFDR) >> fs, &buf_32[k]);
507 }
508
509 static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p,
510 void *rx_buf, int words, int fs)
511 {
512 u32 *buf_32 = rx_buf;
513 int k;
514
515 for (k = 0; k < words; k++)
516 buf_32[k] = swab32(sh_msiof_read(p, RFDR) >> fs);
517 }
518
519 static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p,
520 void *rx_buf, int words, int fs)
521 {
522 u32 *buf_32 = rx_buf;
523 int k;
524
525 for (k = 0; k < words; k++)
526 put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]);
527 }
528
529 static int sh_msiof_spi_setup(struct spi_device *spi)
530 {
531 struct device_node *np = spi->master->dev.of_node;
532 struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master);
533 u32 clr, set, tmp;
534
535 if (!np) {
536 /*
537 * Use spi->controller_data for CS (same strategy as spi_gpio),
538 * if any. otherwise let HW control CS
539 */
540 spi->cs_gpio = (uintptr_t)spi->controller_data;
541 }
542
543 if (spi->cs_gpio >= 0) {
544 gpio_set_value(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
545 return 0;
546 }
547
548 if (spi_controller_is_slave(p->master))
549 return 0;
550
551 if (p->native_cs_inited &&
552 (p->native_cs_high == !!(spi->mode & SPI_CS_HIGH)))
553 return 0;
554
555 /* Configure native chip select mode/polarity early */
556 clr = MDR1_SYNCMD_MASK;
557 set = MDR1_TRMD | TMDR1_PCON | MDR1_SYNCMD_SPI;
558 if (spi->mode & SPI_CS_HIGH)
559 clr |= BIT(MDR1_SYNCAC_SHIFT);
560 else
561 set |= BIT(MDR1_SYNCAC_SHIFT);
562 pm_runtime_get_sync(&p->pdev->dev);
563 tmp = sh_msiof_read(p, TMDR1) & ~clr;
564 sh_msiof_write(p, TMDR1, tmp | set);
565 pm_runtime_put(&p->pdev->dev);
566 p->native_cs_high = spi->mode & SPI_CS_HIGH;
567 p->native_cs_inited = true;
568 return 0;
569 }
570
571 static int sh_msiof_prepare_message(struct spi_master *master,
572 struct spi_message *msg)
573 {
574 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
575 const struct spi_device *spi = msg->spi;
576
577 /* Configure pins before asserting CS */
578 sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL),
579 !!(spi->mode & SPI_CPHA),
580 !!(spi->mode & SPI_3WIRE),
581 !!(spi->mode & SPI_LSB_FIRST),
582 !!(spi->mode & SPI_CS_HIGH));
583 return 0;
584 }
585
586 static int sh_msiof_spi_start(struct sh_msiof_spi_priv *p, void *rx_buf)
587 {
588 bool slave = spi_controller_is_slave(p->master);
589 int ret = 0;
590
591 /* setup clock and rx/tx signals */
592 if (!slave)
593 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TSCKE);
594 if (rx_buf && !ret)
595 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_RXE);
596 if (!ret)
597 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TXE);
598
599 /* start by setting frame bit */
600 if (!ret && !slave)
601 ret = sh_msiof_modify_ctr_wait(p, 0, CTR_TFSE);
602
603 return ret;
604 }
605
606 static int sh_msiof_spi_stop(struct sh_msiof_spi_priv *p, void *rx_buf)
607 {
608 bool slave = spi_controller_is_slave(p->master);
609 int ret = 0;
610
611 /* shut down frame, rx/tx and clock signals */
612 if (!slave)
613 ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0);
614 if (!ret)
615 ret = sh_msiof_modify_ctr_wait(p, CTR_TXE, 0);
616 if (rx_buf && !ret)
617 ret = sh_msiof_modify_ctr_wait(p, CTR_RXE, 0);
618 if (!ret && !slave)
619 ret = sh_msiof_modify_ctr_wait(p, CTR_TSCKE, 0);
620
621 return ret;
622 }
623
624 static int sh_msiof_slave_abort(struct spi_master *master)
625 {
626 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
627
628 p->slave_aborted = true;
629 complete(&p->done);
630 return 0;
631 }
632
633 static int sh_msiof_wait_for_completion(struct sh_msiof_spi_priv *p)
634 {
635 if (spi_controller_is_slave(p->master)) {
636 if (wait_for_completion_interruptible(&p->done) ||
637 p->slave_aborted) {
638 dev_dbg(&p->pdev->dev, "interrupted\n");
639 return -EINTR;
640 }
641 } else {
642 if (!wait_for_completion_timeout(&p->done, HZ)) {
643 dev_err(&p->pdev->dev, "timeout\n");
644 return -ETIMEDOUT;
645 }
646 }
647
648 return 0;
649 }
650
651 static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p,
652 void (*tx_fifo)(struct sh_msiof_spi_priv *,
653 const void *, int, int),
654 void (*rx_fifo)(struct sh_msiof_spi_priv *,
655 void *, int, int),
656 const void *tx_buf, void *rx_buf,
657 int words, int bits)
658 {
659 int fifo_shift;
660 int ret;
661
662 /* limit maximum word transfer to rx/tx fifo size */
663 if (tx_buf)
664 words = min_t(int, words, p->tx_fifo_size);
665 if (rx_buf)
666 words = min_t(int, words, p->rx_fifo_size);
667
668 /* the fifo contents need shifting */
669 fifo_shift = 32 - bits;
670
671 /* default FIFO watermarks for PIO */
672 sh_msiof_write(p, FCTR, 0);
673
674 /* setup msiof transfer mode registers */
675 sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words);
676 sh_msiof_write(p, IER, IER_TEOFE | IER_REOFE);
677
678 /* write tx fifo */
679 if (tx_buf)
680 tx_fifo(p, tx_buf, words, fifo_shift);
681
682 reinit_completion(&p->done);
683 p->slave_aborted = false;
684
685 ret = sh_msiof_spi_start(p, rx_buf);
686 if (ret) {
687 dev_err(&p->pdev->dev, "failed to start hardware\n");
688 goto stop_ier;
689 }
690
691 /* wait for tx fifo to be emptied / rx fifo to be filled */
692 ret = sh_msiof_wait_for_completion(p);
693 if (ret)
694 goto stop_reset;
695
696 /* read rx fifo */
697 if (rx_buf)
698 rx_fifo(p, rx_buf, words, fifo_shift);
699
700 /* clear status bits */
701 sh_msiof_reset_str(p);
702
703 ret = sh_msiof_spi_stop(p, rx_buf);
704 if (ret) {
705 dev_err(&p->pdev->dev, "failed to shut down hardware\n");
706 return ret;
707 }
708
709 return words;
710
711 stop_reset:
712 sh_msiof_reset_str(p);
713 sh_msiof_spi_stop(p, rx_buf);
714 stop_ier:
715 sh_msiof_write(p, IER, 0);
716 return ret;
717 }
718
719 static void sh_msiof_dma_complete(void *arg)
720 {
721 struct sh_msiof_spi_priv *p = arg;
722
723 sh_msiof_write(p, IER, 0);
724 complete(&p->done);
725 }
726
727 static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx,
728 void *rx, unsigned int len)
729 {
730 u32 ier_bits = 0;
731 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL;
732 dma_cookie_t cookie;
733 int ret;
734
735 /* First prepare and submit the DMA request(s), as this may fail */
736 if (rx) {
737 ier_bits |= IER_RDREQE | IER_RDMAE;
738 desc_rx = dmaengine_prep_slave_single(p->master->dma_rx,
739 p->rx_dma_addr, len, DMA_FROM_DEVICE,
740 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
741 if (!desc_rx)
742 return -EAGAIN;
743
744 desc_rx->callback = sh_msiof_dma_complete;
745 desc_rx->callback_param = p;
746 cookie = dmaengine_submit(desc_rx);
747 if (dma_submit_error(cookie))
748 return cookie;
749 }
750
751 if (tx) {
752 ier_bits |= IER_TDREQE | IER_TDMAE;
753 dma_sync_single_for_device(p->master->dma_tx->device->dev,
754 p->tx_dma_addr, len, DMA_TO_DEVICE);
755 desc_tx = dmaengine_prep_slave_single(p->master->dma_tx,
756 p->tx_dma_addr, len, DMA_TO_DEVICE,
757 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
758 if (!desc_tx) {
759 ret = -EAGAIN;
760 goto no_dma_tx;
761 }
762
763 if (rx) {
764 /* No callback */
765 desc_tx->callback = NULL;
766 } else {
767 desc_tx->callback = sh_msiof_dma_complete;
768 desc_tx->callback_param = p;
769 }
770 cookie = dmaengine_submit(desc_tx);
771 if (dma_submit_error(cookie)) {
772 ret = cookie;
773 goto no_dma_tx;
774 }
775 }
776
777 /* 1 stage FIFO watermarks for DMA */
778 sh_msiof_write(p, FCTR, FCTR_TFWM_1 | FCTR_RFWM_1);
779
780 /* setup msiof transfer mode registers (32-bit words) */
781 sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4);
782
783 sh_msiof_write(p, IER, ier_bits);
784
785 reinit_completion(&p->done);
786 p->slave_aborted = false;
787
788 /* Now start DMA */
789 if (rx)
790 dma_async_issue_pending(p->master->dma_rx);
791 if (tx)
792 dma_async_issue_pending(p->master->dma_tx);
793
794 ret = sh_msiof_spi_start(p, rx);
795 if (ret) {
796 dev_err(&p->pdev->dev, "failed to start hardware\n");
797 goto stop_dma;
798 }
799
800 /* wait for tx/rx DMA completion */
801 ret = sh_msiof_wait_for_completion(p);
802 if (ret)
803 goto stop_reset;
804
805 if (!rx) {
806 reinit_completion(&p->done);
807 sh_msiof_write(p, IER, IER_TEOFE);
808
809 /* wait for tx fifo to be emptied */
810 ret = sh_msiof_wait_for_completion(p);
811 if (ret)
812 goto stop_reset;
813 }
814
815 /* clear status bits */
816 sh_msiof_reset_str(p);
817
818 ret = sh_msiof_spi_stop(p, rx);
819 if (ret) {
820 dev_err(&p->pdev->dev, "failed to shut down hardware\n");
821 return ret;
822 }
823
824 if (rx)
825 dma_sync_single_for_cpu(p->master->dma_rx->device->dev,
826 p->rx_dma_addr, len,
827 DMA_FROM_DEVICE);
828
829 return 0;
830
831 stop_reset:
832 sh_msiof_reset_str(p);
833 sh_msiof_spi_stop(p, rx);
834 stop_dma:
835 if (tx)
836 dmaengine_terminate_all(p->master->dma_tx);
837 no_dma_tx:
838 if (rx)
839 dmaengine_terminate_all(p->master->dma_rx);
840 sh_msiof_write(p, IER, 0);
841 return ret;
842 }
843
844 static void copy_bswap32(u32 *dst, const u32 *src, unsigned int words)
845 {
846 /* src or dst can be unaligned, but not both */
847 if ((unsigned long)src & 3) {
848 while (words--) {
849 *dst++ = swab32(get_unaligned(src));
850 src++;
851 }
852 } else if ((unsigned long)dst & 3) {
853 while (words--) {
854 put_unaligned(swab32(*src++), dst);
855 dst++;
856 }
857 } else {
858 while (words--)
859 *dst++ = swab32(*src++);
860 }
861 }
862
863 static void copy_wswap32(u32 *dst, const u32 *src, unsigned int words)
864 {
865 /* src or dst can be unaligned, but not both */
866 if ((unsigned long)src & 3) {
867 while (words--) {
868 *dst++ = swahw32(get_unaligned(src));
869 src++;
870 }
871 } else if ((unsigned long)dst & 3) {
872 while (words--) {
873 put_unaligned(swahw32(*src++), dst);
874 dst++;
875 }
876 } else {
877 while (words--)
878 *dst++ = swahw32(*src++);
879 }
880 }
881
882 static void copy_plain32(u32 *dst, const u32 *src, unsigned int words)
883 {
884 memcpy(dst, src, words * 4);
885 }
886
887 static int sh_msiof_transfer_one(struct spi_master *master,
888 struct spi_device *spi,
889 struct spi_transfer *t)
890 {
891 struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
892 void (*copy32)(u32 *, const u32 *, unsigned int);
893 void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int);
894 void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int);
895 const void *tx_buf = t->tx_buf;
896 void *rx_buf = t->rx_buf;
897 unsigned int len = t->len;
898 unsigned int bits = t->bits_per_word;
899 unsigned int bytes_per_word;
900 unsigned int words;
901 int n;
902 bool swab;
903 int ret;
904
905 /* setup clocks (clock already enabled in chipselect()) */
906 if (!spi_controller_is_slave(p->master))
907 sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz);
908
909 while (master->dma_tx && len > 15) {
910 /*
911 * DMA supports 32-bit words only, hence pack 8-bit and 16-bit
912 * words, with byte resp. word swapping.
913 */
914 unsigned int l = 0;
915
916 if (tx_buf)
917 l = min(len, p->tx_fifo_size * 4);
918 if (rx_buf)
919 l = min(len, p->rx_fifo_size * 4);
920
921 if (bits <= 8) {
922 if (l & 3)
923 break;
924 copy32 = copy_bswap32;
925 } else if (bits <= 16) {
926 if (l & 3)
927 break;
928 copy32 = copy_wswap32;
929 } else {
930 copy32 = copy_plain32;
931 }
932
933 if (tx_buf)
934 copy32(p->tx_dma_page, tx_buf, l / 4);
935
936 ret = sh_msiof_dma_once(p, tx_buf, rx_buf, l);
937 if (ret == -EAGAIN) {
938 pr_warn_once("%s %s: DMA not available, falling back to PIO\n",
939 dev_driver_string(&p->pdev->dev),
940 dev_name(&p->pdev->dev));
941 break;
942 }
943 if (ret)
944 return ret;
945
946 if (rx_buf) {
947 copy32(rx_buf, p->rx_dma_page, l / 4);
948 rx_buf += l;
949 }
950 if (tx_buf)
951 tx_buf += l;
952
953 len -= l;
954 if (!len)
955 return 0;
956 }
957
958 if (bits <= 8 && len > 15 && !(len & 3)) {
959 bits = 32;
960 swab = true;
961 } else {
962 swab = false;
963 }
964
965 /* setup bytes per word and fifo read/write functions */
966 if (bits <= 8) {
967 bytes_per_word = 1;
968 tx_fifo = sh_msiof_spi_write_fifo_8;
969 rx_fifo = sh_msiof_spi_read_fifo_8;
970 } else if (bits <= 16) {
971 bytes_per_word = 2;
972 if ((unsigned long)tx_buf & 0x01)
973 tx_fifo = sh_msiof_spi_write_fifo_16u;
974 else
975 tx_fifo = sh_msiof_spi_write_fifo_16;
976
977 if ((unsigned long)rx_buf & 0x01)
978 rx_fifo = sh_msiof_spi_read_fifo_16u;
979 else
980 rx_fifo = sh_msiof_spi_read_fifo_16;
981 } else if (swab) {
982 bytes_per_word = 4;
983 if ((unsigned long)tx_buf & 0x03)
984 tx_fifo = sh_msiof_spi_write_fifo_s32u;
985 else
986 tx_fifo = sh_msiof_spi_write_fifo_s32;
987
988 if ((unsigned long)rx_buf & 0x03)
989 rx_fifo = sh_msiof_spi_read_fifo_s32u;
990 else
991 rx_fifo = sh_msiof_spi_read_fifo_s32;
992 } else {
993 bytes_per_word = 4;
994 if ((unsigned long)tx_buf & 0x03)
995 tx_fifo = sh_msiof_spi_write_fifo_32u;
996 else
997 tx_fifo = sh_msiof_spi_write_fifo_32;
998
999 if ((unsigned long)rx_buf & 0x03)
1000 rx_fifo = sh_msiof_spi_read_fifo_32u;
1001 else
1002 rx_fifo = sh_msiof_spi_read_fifo_32;
1003 }
1004
1005 /* transfer in fifo sized chunks */
1006 words = len / bytes_per_word;
1007
1008 while (words > 0) {
1009 n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo, tx_buf, rx_buf,
1010 words, bits);
1011 if (n < 0)
1012 return n;
1013
1014 if (tx_buf)
1015 tx_buf += n * bytes_per_word;
1016 if (rx_buf)
1017 rx_buf += n * bytes_per_word;
1018 words -= n;
1019 }
1020
1021 return 0;
1022 }
1023
1024 static const struct sh_msiof_chipdata sh_data = {
1025 .tx_fifo_size = 64,
1026 .rx_fifo_size = 64,
1027 .master_flags = 0,
1028 .min_div = 1,
1029 };
1030
1031 static const struct sh_msiof_chipdata rcar_gen2_data = {
1032 .tx_fifo_size = 64,
1033 .rx_fifo_size = 64,
1034 .master_flags = SPI_MASTER_MUST_TX,
1035 .min_div = 1,
1036 };
1037
1038 static const struct sh_msiof_chipdata rcar_gen3_data = {
1039 .tx_fifo_size = 64,
1040 .rx_fifo_size = 64,
1041 .master_flags = SPI_MASTER_MUST_TX,
1042 .min_div = 2,
1043 };
1044
1045 static const struct of_device_id sh_msiof_match[] = {
1046 { .compatible = "renesas,sh-mobile-msiof", .data = &sh_data },
1047 { .compatible = "renesas,msiof-r8a7743", .data = &rcar_gen2_data },
1048 { .compatible = "renesas,msiof-r8a7745", .data = &rcar_gen2_data },
1049 { .compatible = "renesas,msiof-r8a7790", .data = &rcar_gen2_data },
1050 { .compatible = "renesas,msiof-r8a7791", .data = &rcar_gen2_data },
1051 { .compatible = "renesas,msiof-r8a7792", .data = &rcar_gen2_data },
1052 { .compatible = "renesas,msiof-r8a7793", .data = &rcar_gen2_data },
1053 { .compatible = "renesas,msiof-r8a7794", .data = &rcar_gen2_data },
1054 { .compatible = "renesas,rcar-gen2-msiof", .data = &rcar_gen2_data },
1055 { .compatible = "renesas,msiof-r8a7796", .data = &rcar_gen3_data },
1056 { .compatible = "renesas,rcar-gen3-msiof", .data = &rcar_gen3_data },
1057 { .compatible = "renesas,sh-msiof", .data = &sh_data }, /* Deprecated */
1058 {},
1059 };
1060 MODULE_DEVICE_TABLE(of, sh_msiof_match);
1061
1062 #ifdef CONFIG_OF
1063 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
1064 {
1065 struct sh_msiof_spi_info *info;
1066 struct device_node *np = dev->of_node;
1067 u32 num_cs = 1;
1068
1069 info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL);
1070 if (!info)
1071 return NULL;
1072
1073 info->mode = of_property_read_bool(np, "spi-slave") ? MSIOF_SPI_SLAVE
1074 : MSIOF_SPI_MASTER;
1075
1076 /* Parse the MSIOF properties */
1077 if (info->mode == MSIOF_SPI_MASTER)
1078 of_property_read_u32(np, "num-cs", &num_cs);
1079 of_property_read_u32(np, "renesas,tx-fifo-size",
1080 &info->tx_fifo_override);
1081 of_property_read_u32(np, "renesas,rx-fifo-size",
1082 &info->rx_fifo_override);
1083 of_property_read_u32(np, "renesas,dtdl", &info->dtdl);
1084 of_property_read_u32(np, "renesas,syncdl", &info->syncdl);
1085
1086 info->num_chipselect = num_cs;
1087
1088 return info;
1089 }
1090 #else
1091 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
1092 {
1093 return NULL;
1094 }
1095 #endif
1096
1097 static struct dma_chan *sh_msiof_request_dma_chan(struct device *dev,
1098 enum dma_transfer_direction dir, unsigned int id, dma_addr_t port_addr)
1099 {
1100 dma_cap_mask_t mask;
1101 struct dma_chan *chan;
1102 struct dma_slave_config cfg;
1103 int ret;
1104
1105 dma_cap_zero(mask);
1106 dma_cap_set(DMA_SLAVE, mask);
1107
1108 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter,
1109 (void *)(unsigned long)id, dev,
1110 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1111 if (!chan) {
1112 dev_warn(dev, "dma_request_slave_channel_compat failed\n");
1113 return NULL;
1114 }
1115
1116 memset(&cfg, 0, sizeof(cfg));
1117 cfg.direction = dir;
1118 if (dir == DMA_MEM_TO_DEV) {
1119 cfg.dst_addr = port_addr;
1120 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1121 } else {
1122 cfg.src_addr = port_addr;
1123 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1124 }
1125
1126 ret = dmaengine_slave_config(chan, &cfg);
1127 if (ret) {
1128 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret);
1129 dma_release_channel(chan);
1130 return NULL;
1131 }
1132
1133 return chan;
1134 }
1135
1136 static int sh_msiof_request_dma(struct sh_msiof_spi_priv *p)
1137 {
1138 struct platform_device *pdev = p->pdev;
1139 struct device *dev = &pdev->dev;
1140 const struct sh_msiof_spi_info *info = dev_get_platdata(dev);
1141 unsigned int dma_tx_id, dma_rx_id;
1142 const struct resource *res;
1143 struct spi_master *master;
1144 struct device *tx_dev, *rx_dev;
1145
1146 if (dev->of_node) {
1147 /* In the OF case we will get the slave IDs from the DT */
1148 dma_tx_id = 0;
1149 dma_rx_id = 0;
1150 } else if (info && info->dma_tx_id && info->dma_rx_id) {
1151 dma_tx_id = info->dma_tx_id;
1152 dma_rx_id = info->dma_rx_id;
1153 } else {
1154 /* The driver assumes no error */
1155 return 0;
1156 }
1157
1158 /* The DMA engine uses the second register set, if present */
1159 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1160 if (!res)
1161 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1162
1163 master = p->master;
1164 master->dma_tx = sh_msiof_request_dma_chan(dev, DMA_MEM_TO_DEV,
1165 dma_tx_id,
1166 res->start + TFDR);
1167 if (!master->dma_tx)
1168 return -ENODEV;
1169
1170 master->dma_rx = sh_msiof_request_dma_chan(dev, DMA_DEV_TO_MEM,
1171 dma_rx_id,
1172 res->start + RFDR);
1173 if (!master->dma_rx)
1174 goto free_tx_chan;
1175
1176 p->tx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
1177 if (!p->tx_dma_page)
1178 goto free_rx_chan;
1179
1180 p->rx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA);
1181 if (!p->rx_dma_page)
1182 goto free_tx_page;
1183
1184 tx_dev = master->dma_tx->device->dev;
1185 p->tx_dma_addr = dma_map_single(tx_dev, p->tx_dma_page, PAGE_SIZE,
1186 DMA_TO_DEVICE);
1187 if (dma_mapping_error(tx_dev, p->tx_dma_addr))
1188 goto free_rx_page;
1189
1190 rx_dev = master->dma_rx->device->dev;
1191 p->rx_dma_addr = dma_map_single(rx_dev, p->rx_dma_page, PAGE_SIZE,
1192 DMA_FROM_DEVICE);
1193 if (dma_mapping_error(rx_dev, p->rx_dma_addr))
1194 goto unmap_tx_page;
1195
1196 dev_info(dev, "DMA available");
1197 return 0;
1198
1199 unmap_tx_page:
1200 dma_unmap_single(tx_dev, p->tx_dma_addr, PAGE_SIZE, DMA_TO_DEVICE);
1201 free_rx_page:
1202 free_page((unsigned long)p->rx_dma_page);
1203 free_tx_page:
1204 free_page((unsigned long)p->tx_dma_page);
1205 free_rx_chan:
1206 dma_release_channel(master->dma_rx);
1207 free_tx_chan:
1208 dma_release_channel(master->dma_tx);
1209 master->dma_tx = NULL;
1210 return -ENODEV;
1211 }
1212
1213 static void sh_msiof_release_dma(struct sh_msiof_spi_priv *p)
1214 {
1215 struct spi_master *master = p->master;
1216
1217 if (!master->dma_tx)
1218 return;
1219
1220 dma_unmap_single(master->dma_rx->device->dev, p->rx_dma_addr,
1221 PAGE_SIZE, DMA_FROM_DEVICE);
1222 dma_unmap_single(master->dma_tx->device->dev, p->tx_dma_addr,
1223 PAGE_SIZE, DMA_TO_DEVICE);
1224 free_page((unsigned long)p->rx_dma_page);
1225 free_page((unsigned long)p->tx_dma_page);
1226 dma_release_channel(master->dma_rx);
1227 dma_release_channel(master->dma_tx);
1228 }
1229
1230 static int sh_msiof_spi_probe(struct platform_device *pdev)
1231 {
1232 struct resource *r;
1233 struct spi_master *master;
1234 const struct sh_msiof_chipdata *chipdata;
1235 struct sh_msiof_spi_info *info;
1236 struct sh_msiof_spi_priv *p;
1237 int i;
1238 int ret;
1239
1240 chipdata = of_device_get_match_data(&pdev->dev);
1241 if (chipdata) {
1242 info = sh_msiof_spi_parse_dt(&pdev->dev);
1243 } else {
1244 chipdata = (const void *)pdev->id_entry->driver_data;
1245 info = dev_get_platdata(&pdev->dev);
1246 }
1247
1248 if (!info) {
1249 dev_err(&pdev->dev, "failed to obtain device info\n");
1250 return -ENXIO;
1251 }
1252
1253 if (info->mode == MSIOF_SPI_SLAVE)
1254 master = spi_alloc_slave(&pdev->dev,
1255 sizeof(struct sh_msiof_spi_priv));
1256 else
1257 master = spi_alloc_master(&pdev->dev,
1258 sizeof(struct sh_msiof_spi_priv));
1259 if (master == NULL)
1260 return -ENOMEM;
1261
1262 p = spi_master_get_devdata(master);
1263
1264 platform_set_drvdata(pdev, p);
1265 p->master = master;
1266 p->info = info;
1267 p->min_div = chipdata->min_div;
1268
1269 init_completion(&p->done);
1270
1271 p->clk = devm_clk_get(&pdev->dev, NULL);
1272 if (IS_ERR(p->clk)) {
1273 dev_err(&pdev->dev, "cannot get clock\n");
1274 ret = PTR_ERR(p->clk);
1275 goto err1;
1276 }
1277
1278 i = platform_get_irq(pdev, 0);
1279 if (i < 0) {
1280 dev_err(&pdev->dev, "cannot get platform IRQ\n");
1281 ret = -ENOENT;
1282 goto err1;
1283 }
1284
1285 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1286 p->mapbase = devm_ioremap_resource(&pdev->dev, r);
1287 if (IS_ERR(p->mapbase)) {
1288 ret = PTR_ERR(p->mapbase);
1289 goto err1;
1290 }
1291
1292 ret = devm_request_irq(&pdev->dev, i, sh_msiof_spi_irq, 0,
1293 dev_name(&pdev->dev), p);
1294 if (ret) {
1295 dev_err(&pdev->dev, "unable to request irq\n");
1296 goto err1;
1297 }
1298
1299 p->pdev = pdev;
1300 pm_runtime_enable(&pdev->dev);
1301
1302 /* Platform data may override FIFO sizes */
1303 p->tx_fifo_size = chipdata->tx_fifo_size;
1304 p->rx_fifo_size = chipdata->rx_fifo_size;
1305 if (p->info->tx_fifo_override)
1306 p->tx_fifo_size = p->info->tx_fifo_override;
1307 if (p->info->rx_fifo_override)
1308 p->rx_fifo_size = p->info->rx_fifo_override;
1309
1310 /* init master code */
1311 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1312 master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE;
1313 master->flags = chipdata->master_flags;
1314 master->bus_num = pdev->id;
1315 master->dev.of_node = pdev->dev.of_node;
1316 master->num_chipselect = p->info->num_chipselect;
1317 master->setup = sh_msiof_spi_setup;
1318 master->prepare_message = sh_msiof_prepare_message;
1319 master->slave_abort = sh_msiof_slave_abort;
1320 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
1321 master->auto_runtime_pm = true;
1322 master->transfer_one = sh_msiof_transfer_one;
1323
1324 ret = sh_msiof_request_dma(p);
1325 if (ret < 0)
1326 dev_warn(&pdev->dev, "DMA not available, using PIO\n");
1327
1328 ret = devm_spi_register_master(&pdev->dev, master);
1329 if (ret < 0) {
1330 dev_err(&pdev->dev, "spi_register_master error.\n");
1331 goto err2;
1332 }
1333
1334 return 0;
1335
1336 err2:
1337 sh_msiof_release_dma(p);
1338 pm_runtime_disable(&pdev->dev);
1339 err1:
1340 spi_master_put(master);
1341 return ret;
1342 }
1343
1344 static int sh_msiof_spi_remove(struct platform_device *pdev)
1345 {
1346 struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
1347
1348 sh_msiof_release_dma(p);
1349 pm_runtime_disable(&pdev->dev);
1350 return 0;
1351 }
1352
1353 static const struct platform_device_id spi_driver_ids[] = {
1354 { "spi_sh_msiof", (kernel_ulong_t)&sh_data },
1355 {},
1356 };
1357 MODULE_DEVICE_TABLE(platform, spi_driver_ids);
1358
1359 static struct platform_driver sh_msiof_spi_drv = {
1360 .probe = sh_msiof_spi_probe,
1361 .remove = sh_msiof_spi_remove,
1362 .id_table = spi_driver_ids,
1363 .driver = {
1364 .name = "spi_sh_msiof",
1365 .of_match_table = of_match_ptr(sh_msiof_match),
1366 },
1367 };
1368 module_platform_driver(sh_msiof_spi_drv);
1369
1370 MODULE_DESCRIPTION("SuperH MSIOF SPI Master Interface Driver");
1371 MODULE_AUTHOR("Magnus Damm");
1372 MODULE_LICENSE("GPL v2");
1373 MODULE_ALIAS("platform:spi_sh_msiof");
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