2 * Blackfin On-Chip SPI Driver
4 * Copyright 2004-2007 Analog Devices Inc.
6 * Enter bugs at http://blackfin.uclinux.org/
8 * Licensed under the GPL-2 or later.
11 #include <linux/init.h>
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/slab.h>
17 #include <linux/ioport.h>
18 #include <linux/irq.h>
19 #include <linux/errno.h>
20 #include <linux/interrupt.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/spi/spi.h>
24 #include <linux/workqueue.h>
27 #include <asm/portmux.h>
28 #include <asm/bfin5xx_spi.h>
29 #include <asm/cacheflush.h>
31 #define DRV_NAME "bfin-spi"
32 #define DRV_AUTHOR "Bryan Wu, Luke Yang"
33 #define DRV_DESC "Blackfin on-chip SPI Controller Driver"
34 #define DRV_VERSION "1.0"
36 MODULE_AUTHOR(DRV_AUTHOR
);
37 MODULE_DESCRIPTION(DRV_DESC
);
38 MODULE_LICENSE("GPL");
40 #define START_STATE ((void *)0)
41 #define RUNNING_STATE ((void *)1)
42 #define DONE_STATE ((void *)2)
43 #define ERROR_STATE ((void *)-1)
48 void (*write
) (struct master_data
*);
49 void (*read
) (struct master_data
*);
50 void (*duplex
) (struct master_data
*);
54 /* Driver model hookup */
55 struct platform_device
*pdev
;
57 /* SPI framework hookup */
58 struct spi_master
*master
;
60 /* Regs base of SPI controller */
61 void __iomem
*regs_base
;
63 /* Pin request list */
67 struct bfin5xx_spi_master
*master_info
;
69 /* Driver message queue */
70 struct workqueue_struct
*workqueue
;
71 struct work_struct pump_messages
;
73 struct list_head queue
;
77 /* Message Transfer pump */
78 struct tasklet_struct pump_transfers
;
80 /* Current message transfer state info */
81 struct spi_message
*cur_msg
;
82 struct spi_transfer
*cur_transfer
;
83 struct slave_data
*cur_chip
;
108 const struct transfer_ops
*ops
;
118 u16 cs_chg_udelay
; /* Some devices require > 255usec delay */
121 u8 pio_interrupt
; /* use spi data irq */
122 const struct transfer_ops
*ops
;
125 #define DEFINE_SPI_REG(reg, off) \
126 static inline u16 read_##reg(struct master_data *drv_data) \
127 { return bfin_read16(drv_data->regs_base + off); } \
128 static inline void write_##reg(struct master_data *drv_data, u16 v) \
129 { bfin_write16(drv_data->regs_base + off, v); }
131 DEFINE_SPI_REG(CTRL
, 0x00)
132 DEFINE_SPI_REG(FLAG
, 0x04)
133 DEFINE_SPI_REG(STAT
, 0x08)
134 DEFINE_SPI_REG(TDBR
, 0x0C)
135 DEFINE_SPI_REG(RDBR
, 0x10)
136 DEFINE_SPI_REG(BAUD
, 0x14)
137 DEFINE_SPI_REG(SHAW
, 0x18)
139 static void bfin_spi_enable(struct master_data
*drv_data
)
143 cr
= read_CTRL(drv_data
);
144 write_CTRL(drv_data
, (cr
| BIT_CTL_ENABLE
));
147 static void bfin_spi_disable(struct master_data
*drv_data
)
151 cr
= read_CTRL(drv_data
);
152 write_CTRL(drv_data
, (cr
& (~BIT_CTL_ENABLE
)));
155 /* Caculate the SPI_BAUD register value based on input HZ */
156 static u16
hz_to_spi_baud(u32 speed_hz
)
158 u_long sclk
= get_sclk();
159 u16 spi_baud
= (sclk
/ (2 * speed_hz
));
161 if ((sclk
% (2 * speed_hz
)) > 0)
164 if (spi_baud
< MIN_SPI_BAUD_VAL
)
165 spi_baud
= MIN_SPI_BAUD_VAL
;
170 static int bfin_spi_flush(struct master_data
*drv_data
)
172 unsigned long limit
= loops_per_jiffy
<< 1;
174 /* wait for stop and clear stat */
175 while (!(read_STAT(drv_data
) & BIT_STAT_SPIF
) && --limit
)
178 write_STAT(drv_data
, BIT_STAT_CLR
);
183 /* Chip select operation functions for cs_change flag */
184 static void bfin_spi_cs_active(struct master_data
*drv_data
, struct slave_data
*chip
)
186 if (likely(chip
->chip_select_num
< MAX_CTRL_CS
)) {
187 u16 flag
= read_FLAG(drv_data
);
191 write_FLAG(drv_data
, flag
);
193 gpio_set_value(chip
->cs_gpio
, 0);
197 static void bfin_spi_cs_deactive(struct master_data
*drv_data
, struct slave_data
*chip
)
199 if (likely(chip
->chip_select_num
< MAX_CTRL_CS
)) {
200 u16 flag
= read_FLAG(drv_data
);
204 write_FLAG(drv_data
, flag
);
206 gpio_set_value(chip
->cs_gpio
, 1);
209 /* Move delay here for consistency */
210 if (chip
->cs_chg_udelay
)
211 udelay(chip
->cs_chg_udelay
);
214 /* enable or disable the pin muxed by GPIO and SPI CS to work as SPI CS */
215 static inline void bfin_spi_cs_enable(struct master_data
*drv_data
, struct slave_data
*chip
)
217 if (chip
->chip_select_num
< MAX_CTRL_CS
) {
218 u16 flag
= read_FLAG(drv_data
);
220 flag
|= (chip
->flag
>> 8);
222 write_FLAG(drv_data
, flag
);
226 static inline void bfin_spi_cs_disable(struct master_data
*drv_data
, struct slave_data
*chip
)
228 if (chip
->chip_select_num
< MAX_CTRL_CS
) {
229 u16 flag
= read_FLAG(drv_data
);
231 flag
&= ~(chip
->flag
>> 8);
233 write_FLAG(drv_data
, flag
);
237 /* stop controller and re-config current chip*/
238 static void bfin_spi_restore_state(struct master_data
*drv_data
)
240 struct slave_data
*chip
= drv_data
->cur_chip
;
242 /* Clear status and disable clock */
243 write_STAT(drv_data
, BIT_STAT_CLR
);
244 bfin_spi_disable(drv_data
);
245 dev_dbg(&drv_data
->pdev
->dev
, "restoring spi ctl state\n");
249 /* Load the registers */
250 write_CTRL(drv_data
, chip
->ctl_reg
);
251 write_BAUD(drv_data
, chip
->baud
);
253 bfin_spi_enable(drv_data
);
254 bfin_spi_cs_active(drv_data
, chip
);
257 /* used to kick off transfer in rx mode and read unwanted RX data */
258 static inline void bfin_spi_dummy_read(struct master_data
*drv_data
)
260 (void) read_RDBR(drv_data
);
263 static void bfin_spi_u8_writer(struct master_data
*drv_data
)
265 /* clear RXS (we check for RXS inside the loop) */
266 bfin_spi_dummy_read(drv_data
);
268 while (drv_data
->tx
< drv_data
->tx_end
) {
269 write_TDBR(drv_data
, (*(u8
*) (drv_data
->tx
++)));
270 /* wait until transfer finished.
271 checking SPIF or TXS may not guarantee transfer completion */
272 while (!(read_STAT(drv_data
) & BIT_STAT_RXS
))
274 /* discard RX data and clear RXS */
275 bfin_spi_dummy_read(drv_data
);
279 static void bfin_spi_u8_reader(struct master_data
*drv_data
)
281 u16 tx_val
= drv_data
->cur_chip
->idle_tx_val
;
283 /* discard old RX data and clear RXS */
284 bfin_spi_dummy_read(drv_data
);
286 while (drv_data
->rx
< drv_data
->rx_end
) {
287 write_TDBR(drv_data
, tx_val
);
288 while (!(read_STAT(drv_data
) & BIT_STAT_RXS
))
290 *(u8
*) (drv_data
->rx
++) = read_RDBR(drv_data
);
294 static void bfin_spi_u8_duplex(struct master_data
*drv_data
)
296 /* discard old RX data and clear RXS */
297 bfin_spi_dummy_read(drv_data
);
299 while (drv_data
->rx
< drv_data
->rx_end
) {
300 write_TDBR(drv_data
, (*(u8
*) (drv_data
->tx
++)));
301 while (!(read_STAT(drv_data
) & BIT_STAT_RXS
))
303 *(u8
*) (drv_data
->rx
++) = read_RDBR(drv_data
);
307 static const struct transfer_ops bfin_transfer_ops_u8
= {
308 .write
= bfin_spi_u8_writer
,
309 .read
= bfin_spi_u8_reader
,
310 .duplex
= bfin_spi_u8_duplex
,
313 static void bfin_spi_u16_writer(struct master_data
*drv_data
)
315 /* clear RXS (we check for RXS inside the loop) */
316 bfin_spi_dummy_read(drv_data
);
318 while (drv_data
->tx
< drv_data
->tx_end
) {
319 write_TDBR(drv_data
, (*(u16
*) (drv_data
->tx
)));
321 /* wait until transfer finished.
322 checking SPIF or TXS may not guarantee transfer completion */
323 while (!(read_STAT(drv_data
) & BIT_STAT_RXS
))
325 /* discard RX data and clear RXS */
326 bfin_spi_dummy_read(drv_data
);
330 static void bfin_spi_u16_reader(struct master_data
*drv_data
)
332 u16 tx_val
= drv_data
->cur_chip
->idle_tx_val
;
334 /* discard old RX data and clear RXS */
335 bfin_spi_dummy_read(drv_data
);
337 while (drv_data
->rx
< drv_data
->rx_end
) {
338 write_TDBR(drv_data
, tx_val
);
339 while (!(read_STAT(drv_data
) & BIT_STAT_RXS
))
341 *(u16
*) (drv_data
->rx
) = read_RDBR(drv_data
);
346 static void bfin_spi_u16_duplex(struct master_data
*drv_data
)
348 /* discard old RX data and clear RXS */
349 bfin_spi_dummy_read(drv_data
);
351 while (drv_data
->rx
< drv_data
->rx_end
) {
352 write_TDBR(drv_data
, (*(u16
*) (drv_data
->tx
)));
354 while (!(read_STAT(drv_data
) & BIT_STAT_RXS
))
356 *(u16
*) (drv_data
->rx
) = read_RDBR(drv_data
);
361 static const struct transfer_ops bfin_transfer_ops_u16
= {
362 .write
= bfin_spi_u16_writer
,
363 .read
= bfin_spi_u16_reader
,
364 .duplex
= bfin_spi_u16_duplex
,
367 /* test if ther is more transfer to be done */
368 static void *bfin_spi_next_transfer(struct master_data
*drv_data
)
370 struct spi_message
*msg
= drv_data
->cur_msg
;
371 struct spi_transfer
*trans
= drv_data
->cur_transfer
;
373 /* Move to next transfer */
374 if (trans
->transfer_list
.next
!= &msg
->transfers
) {
375 drv_data
->cur_transfer
=
376 list_entry(trans
->transfer_list
.next
,
377 struct spi_transfer
, transfer_list
);
378 return RUNNING_STATE
;
384 * caller already set message->status;
385 * dma and pio irqs are blocked give finished message back
387 static void bfin_spi_giveback(struct master_data
*drv_data
)
389 struct slave_data
*chip
= drv_data
->cur_chip
;
390 struct spi_transfer
*last_transfer
;
392 struct spi_message
*msg
;
394 spin_lock_irqsave(&drv_data
->lock
, flags
);
395 msg
= drv_data
->cur_msg
;
396 drv_data
->cur_msg
= NULL
;
397 drv_data
->cur_transfer
= NULL
;
398 drv_data
->cur_chip
= NULL
;
399 queue_work(drv_data
->workqueue
, &drv_data
->pump_messages
);
400 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
402 last_transfer
= list_entry(msg
->transfers
.prev
,
403 struct spi_transfer
, transfer_list
);
407 if (!drv_data
->cs_change
)
408 bfin_spi_cs_deactive(drv_data
, chip
);
410 /* Not stop spi in autobuffer mode */
411 if (drv_data
->tx_dma
!= 0xFFFF)
412 bfin_spi_disable(drv_data
);
415 msg
->complete(msg
->context
);
418 /* spi data irq handler */
419 static irqreturn_t
bfin_spi_pio_irq_handler(int irq
, void *dev_id
)
421 struct master_data
*drv_data
= dev_id
;
422 struct slave_data
*chip
= drv_data
->cur_chip
;
423 struct spi_message
*msg
= drv_data
->cur_msg
;
424 int n_bytes
= drv_data
->n_bytes
;
426 /* wait until transfer finished. */
427 while (!(read_STAT(drv_data
) & BIT_STAT_RXS
))
430 if ((drv_data
->tx
&& drv_data
->tx
>= drv_data
->tx_end
) ||
431 (drv_data
->rx
&& drv_data
->rx
>= (drv_data
->rx_end
- n_bytes
))) {
434 dev_dbg(&drv_data
->pdev
->dev
, "last read\n");
436 *(u16
*) (drv_data
->rx
) = read_RDBR(drv_data
);
437 else if (n_bytes
== 1)
438 *(u8
*) (drv_data
->rx
) = read_RDBR(drv_data
);
439 drv_data
->rx
+= n_bytes
;
442 msg
->actual_length
+= drv_data
->len_in_bytes
;
443 if (drv_data
->cs_change
)
444 bfin_spi_cs_deactive(drv_data
, chip
);
445 /* Move to next transfer */
446 msg
->state
= bfin_spi_next_transfer(drv_data
);
448 disable_irq_nosync(drv_data
->spi_irq
);
450 /* Schedule transfer tasklet */
451 tasklet_schedule(&drv_data
->pump_transfers
);
455 if (drv_data
->rx
&& drv_data
->tx
) {
457 dev_dbg(&drv_data
->pdev
->dev
, "duplex: write_TDBR\n");
458 if (drv_data
->n_bytes
== 2) {
459 *(u16
*) (drv_data
->rx
) = read_RDBR(drv_data
);
460 write_TDBR(drv_data
, (*(u16
*) (drv_data
->tx
)));
461 } else if (drv_data
->n_bytes
== 1) {
462 *(u8
*) (drv_data
->rx
) = read_RDBR(drv_data
);
463 write_TDBR(drv_data
, (*(u8
*) (drv_data
->tx
)));
465 } else if (drv_data
->rx
) {
467 dev_dbg(&drv_data
->pdev
->dev
, "read: write_TDBR\n");
468 if (drv_data
->n_bytes
== 2)
469 *(u16
*) (drv_data
->rx
) = read_RDBR(drv_data
);
470 else if (drv_data
->n_bytes
== 1)
471 *(u8
*) (drv_data
->rx
) = read_RDBR(drv_data
);
472 write_TDBR(drv_data
, chip
->idle_tx_val
);
473 } else if (drv_data
->tx
) {
475 dev_dbg(&drv_data
->pdev
->dev
, "write: write_TDBR\n");
476 bfin_spi_dummy_read(drv_data
);
477 if (drv_data
->n_bytes
== 2)
478 write_TDBR(drv_data
, (*(u16
*) (drv_data
->tx
)));
479 else if (drv_data
->n_bytes
== 1)
480 write_TDBR(drv_data
, (*(u8
*) (drv_data
->tx
)));
484 drv_data
->tx
+= n_bytes
;
486 drv_data
->rx
+= n_bytes
;
491 static irqreturn_t
bfin_spi_dma_irq_handler(int irq
, void *dev_id
)
493 struct master_data
*drv_data
= dev_id
;
494 struct slave_data
*chip
= drv_data
->cur_chip
;
495 struct spi_message
*msg
= drv_data
->cur_msg
;
496 unsigned long timeout
;
497 unsigned short dmastat
= get_dma_curr_irqstat(drv_data
->dma_channel
);
498 u16 spistat
= read_STAT(drv_data
);
500 dev_dbg(&drv_data
->pdev
->dev
,
501 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
504 clear_dma_irqstat(drv_data
->dma_channel
);
507 * wait for the last transaction shifted out. HRM states:
508 * at this point there may still be data in the SPI DMA FIFO waiting
509 * to be transmitted ... software needs to poll TXS in the SPI_STAT
510 * register until it goes low for 2 successive reads
512 if (drv_data
->tx
!= NULL
) {
513 while ((read_STAT(drv_data
) & BIT_STAT_TXS
) ||
514 (read_STAT(drv_data
) & BIT_STAT_TXS
))
518 dev_dbg(&drv_data
->pdev
->dev
,
519 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
520 dmastat
, read_STAT(drv_data
));
522 timeout
= jiffies
+ HZ
;
523 while (!(read_STAT(drv_data
) & BIT_STAT_SPIF
))
524 if (!time_before(jiffies
, timeout
)) {
525 dev_warn(&drv_data
->pdev
->dev
, "timeout waiting for SPIF");
530 if ((dmastat
& DMA_ERR
) && (spistat
& BIT_STAT_RBSY
)) {
531 msg
->state
= ERROR_STATE
;
532 dev_err(&drv_data
->pdev
->dev
, "dma receive: fifo/buffer overflow\n");
534 msg
->actual_length
+= drv_data
->len_in_bytes
;
536 if (drv_data
->cs_change
)
537 bfin_spi_cs_deactive(drv_data
, chip
);
539 /* Move to next transfer */
540 msg
->state
= bfin_spi_next_transfer(drv_data
);
543 /* Schedule transfer tasklet */
544 tasklet_schedule(&drv_data
->pump_transfers
);
546 /* free the irq handler before next transfer */
547 dev_dbg(&drv_data
->pdev
->dev
,
548 "disable dma channel irq%d\n",
549 drv_data
->dma_channel
);
550 dma_disable_irq(drv_data
->dma_channel
);
555 static void bfin_spi_pump_transfers(unsigned long data
)
557 struct master_data
*drv_data
= (struct master_data
*)data
;
558 struct spi_message
*message
= NULL
;
559 struct spi_transfer
*transfer
= NULL
;
560 struct spi_transfer
*previous
= NULL
;
561 struct slave_data
*chip
= NULL
;
562 unsigned int bits_per_word
;
564 u16 cr
, dma_width
, dma_config
;
565 u32 tranf_success
= 1;
568 /* Get current state information */
569 message
= drv_data
->cur_msg
;
570 transfer
= drv_data
->cur_transfer
;
571 chip
= drv_data
->cur_chip
;
574 * if msg is error or done, report it back using complete() callback
577 /* Handle for abort */
578 if (message
->state
== ERROR_STATE
) {
579 dev_dbg(&drv_data
->pdev
->dev
, "transfer: we've hit an error\n");
580 message
->status
= -EIO
;
581 bfin_spi_giveback(drv_data
);
585 /* Handle end of message */
586 if (message
->state
== DONE_STATE
) {
587 dev_dbg(&drv_data
->pdev
->dev
, "transfer: all done!\n");
589 bfin_spi_giveback(drv_data
);
593 /* Delay if requested at end of transfer */
594 if (message
->state
== RUNNING_STATE
) {
595 dev_dbg(&drv_data
->pdev
->dev
, "transfer: still running ...\n");
596 previous
= list_entry(transfer
->transfer_list
.prev
,
597 struct spi_transfer
, transfer_list
);
598 if (previous
->delay_usecs
)
599 udelay(previous
->delay_usecs
);
602 /* Flush any existing transfers that may be sitting in the hardware */
603 if (bfin_spi_flush(drv_data
) == 0) {
604 dev_err(&drv_data
->pdev
->dev
, "pump_transfers: flush failed\n");
605 message
->status
= -EIO
;
606 bfin_spi_giveback(drv_data
);
610 if (transfer
->len
== 0) {
611 /* Move to next transfer of this msg */
612 message
->state
= bfin_spi_next_transfer(drv_data
);
613 /* Schedule next transfer tasklet */
614 tasklet_schedule(&drv_data
->pump_transfers
);
617 if (transfer
->tx_buf
!= NULL
) {
618 drv_data
->tx
= (void *)transfer
->tx_buf
;
619 drv_data
->tx_end
= drv_data
->tx
+ transfer
->len
;
620 dev_dbg(&drv_data
->pdev
->dev
, "tx_buf is %p, tx_end is %p\n",
621 transfer
->tx_buf
, drv_data
->tx_end
);
626 if (transfer
->rx_buf
!= NULL
) {
627 full_duplex
= transfer
->tx_buf
!= NULL
;
628 drv_data
->rx
= transfer
->rx_buf
;
629 drv_data
->rx_end
= drv_data
->rx
+ transfer
->len
;
630 dev_dbg(&drv_data
->pdev
->dev
, "rx_buf is %p, rx_end is %p\n",
631 transfer
->rx_buf
, drv_data
->rx_end
);
636 drv_data
->rx_dma
= transfer
->rx_dma
;
637 drv_data
->tx_dma
= transfer
->tx_dma
;
638 drv_data
->len_in_bytes
= transfer
->len
;
639 drv_data
->cs_change
= transfer
->cs_change
;
641 /* Bits per word setup */
642 bits_per_word
= transfer
->bits_per_word
? : message
->spi
->bits_per_word
;
643 if (bits_per_word
== 8) {
644 drv_data
->n_bytes
= 1;
645 width
= CFG_SPI_WORDSIZE8
;
646 drv_data
->ops
= &bfin_transfer_ops_u8
;
648 drv_data
->n_bytes
= 2;
649 width
= CFG_SPI_WORDSIZE16
;
650 drv_data
->ops
= &bfin_transfer_ops_u16
;
652 cr
= (read_CTRL(drv_data
) & (~BIT_CTL_TIMOD
));
654 write_CTRL(drv_data
, cr
);
656 if (width
== CFG_SPI_WORDSIZE16
) {
657 drv_data
->len
= (transfer
->len
) >> 1;
659 drv_data
->len
= transfer
->len
;
661 dev_dbg(&drv_data
->pdev
->dev
,
662 "transfer: drv_data->ops is %p, chip->ops is %p, u8_ops is %p\n",
663 drv_data
->ops
, chip
->ops
, &bfin_transfer_ops_u8
);
665 message
->state
= RUNNING_STATE
;
668 /* Speed setup (surely valid because already checked) */
669 if (transfer
->speed_hz
)
670 write_BAUD(drv_data
, hz_to_spi_baud(transfer
->speed_hz
));
672 write_BAUD(drv_data
, chip
->baud
);
674 write_STAT(drv_data
, BIT_STAT_CLR
);
675 cr
= (read_CTRL(drv_data
) & (~BIT_CTL_TIMOD
));
676 if (drv_data
->cs_change
)
677 bfin_spi_cs_active(drv_data
, chip
);
679 dev_dbg(&drv_data
->pdev
->dev
,
680 "now pumping a transfer: width is %d, len is %d\n",
681 width
, transfer
->len
);
684 * Try to map dma buffer and do a dma transfer. If successful use,
685 * different way to r/w according to the enable_dma settings and if
686 * we are not doing a full duplex transfer (since the hardware does
687 * not support full duplex DMA transfers).
689 if (!full_duplex
&& drv_data
->cur_chip
->enable_dma
690 && drv_data
->len
> 6) {
692 unsigned long dma_start_addr
, flags
;
694 disable_dma(drv_data
->dma_channel
);
695 clear_dma_irqstat(drv_data
->dma_channel
);
697 /* config dma channel */
698 dev_dbg(&drv_data
->pdev
->dev
, "doing dma transfer\n");
699 set_dma_x_count(drv_data
->dma_channel
, drv_data
->len
);
700 if (width
== CFG_SPI_WORDSIZE16
) {
701 set_dma_x_modify(drv_data
->dma_channel
, 2);
702 dma_width
= WDSIZE_16
;
704 set_dma_x_modify(drv_data
->dma_channel
, 1);
705 dma_width
= WDSIZE_8
;
708 /* poll for SPI completion before start */
709 while (!(read_STAT(drv_data
) & BIT_STAT_SPIF
))
712 /* dirty hack for autobuffer DMA mode */
713 if (drv_data
->tx_dma
== 0xFFFF) {
714 dev_dbg(&drv_data
->pdev
->dev
,
715 "doing autobuffer DMA out.\n");
717 /* no irq in autobuffer mode */
719 (DMAFLOW_AUTO
| RESTART
| dma_width
| DI_EN
);
720 set_dma_config(drv_data
->dma_channel
, dma_config
);
721 set_dma_start_addr(drv_data
->dma_channel
,
722 (unsigned long)drv_data
->tx
);
723 enable_dma(drv_data
->dma_channel
);
725 /* start SPI transfer */
726 write_CTRL(drv_data
, cr
| BIT_CTL_TIMOD_DMA_TX
);
728 /* just return here, there can only be one transfer
732 bfin_spi_giveback(drv_data
);
736 /* In dma mode, rx or tx must be NULL in one transfer */
737 dma_config
= (RESTART
| dma_width
| DI_EN
);
738 if (drv_data
->rx
!= NULL
) {
739 /* set transfer mode, and enable SPI */
740 dev_dbg(&drv_data
->pdev
->dev
, "doing DMA in to %p (size %zx)\n",
741 drv_data
->rx
, drv_data
->len_in_bytes
);
743 /* invalidate caches, if needed */
744 if (bfin_addr_dcacheable((unsigned long) drv_data
->rx
))
745 invalidate_dcache_range((unsigned long) drv_data
->rx
,
746 (unsigned long) (drv_data
->rx
+
747 drv_data
->len_in_bytes
));
750 dma_start_addr
= (unsigned long)drv_data
->rx
;
751 cr
|= BIT_CTL_TIMOD_DMA_RX
| BIT_CTL_SENDOPT
;
753 } else if (drv_data
->tx
!= NULL
) {
754 dev_dbg(&drv_data
->pdev
->dev
, "doing DMA out.\n");
756 /* flush caches, if needed */
757 if (bfin_addr_dcacheable((unsigned long) drv_data
->tx
))
758 flush_dcache_range((unsigned long) drv_data
->tx
,
759 (unsigned long) (drv_data
->tx
+
760 drv_data
->len_in_bytes
));
762 dma_start_addr
= (unsigned long)drv_data
->tx
;
763 cr
|= BIT_CTL_TIMOD_DMA_TX
;
768 /* oh man, here there be monsters ... and i dont mean the
769 * fluffy cute ones from pixar, i mean the kind that'll eat
770 * your data, kick your dog, and love it all. do *not* try
771 * and change these lines unless you (1) heavily test DMA
772 * with SPI flashes on a loaded system (e.g. ping floods),
773 * (2) know just how broken the DMA engine interaction with
774 * the SPI peripheral is, and (3) have someone else to blame
775 * when you screw it all up anyways.
777 set_dma_start_addr(drv_data
->dma_channel
, dma_start_addr
);
778 set_dma_config(drv_data
->dma_channel
, dma_config
);
779 local_irq_save(flags
);
781 write_CTRL(drv_data
, cr
);
782 enable_dma(drv_data
->dma_channel
);
783 dma_enable_irq(drv_data
->dma_channel
);
784 local_irq_restore(flags
);
789 if (chip
->pio_interrupt
) {
790 /* use write mode. spi irq should have been disabled */
791 cr
= (read_CTRL(drv_data
) & (~BIT_CTL_TIMOD
));
792 write_CTRL(drv_data
, (cr
| CFG_SPI_WRITE
));
794 /* discard old RX data and clear RXS */
795 bfin_spi_dummy_read(drv_data
);
798 if (drv_data
->tx
== NULL
)
799 write_TDBR(drv_data
, chip
->idle_tx_val
);
801 if (bits_per_word
== 8)
802 write_TDBR(drv_data
, (*(u8
*) (drv_data
->tx
)));
804 write_TDBR(drv_data
, (*(u16
*) (drv_data
->tx
)));
805 drv_data
->tx
+= drv_data
->n_bytes
;
808 /* once TDBR is empty, interrupt is triggered */
809 enable_irq(drv_data
->spi_irq
);
814 dev_dbg(&drv_data
->pdev
->dev
, "doing IO transfer\n");
816 /* we always use SPI_WRITE mode. SPI_READ mode
817 seems to have problems with setting up the
818 output value in TDBR prior to the transfer. */
819 write_CTRL(drv_data
, (cr
| CFG_SPI_WRITE
));
822 /* full duplex mode */
823 BUG_ON((drv_data
->tx_end
- drv_data
->tx
) !=
824 (drv_data
->rx_end
- drv_data
->rx
));
825 dev_dbg(&drv_data
->pdev
->dev
,
826 "IO duplex: cr is 0x%x\n", cr
);
828 drv_data
->ops
->duplex(drv_data
);
830 if (drv_data
->tx
!= drv_data
->tx_end
)
832 } else if (drv_data
->tx
!= NULL
) {
833 /* write only half duplex */
834 dev_dbg(&drv_data
->pdev
->dev
,
835 "IO write: cr is 0x%x\n", cr
);
837 drv_data
->ops
->write(drv_data
);
839 if (drv_data
->tx
!= drv_data
->tx_end
)
841 } else if (drv_data
->rx
!= NULL
) {
842 /* read only half duplex */
843 dev_dbg(&drv_data
->pdev
->dev
,
844 "IO read: cr is 0x%x\n", cr
);
846 drv_data
->ops
->read(drv_data
);
847 if (drv_data
->rx
!= drv_data
->rx_end
)
851 if (!tranf_success
) {
852 dev_dbg(&drv_data
->pdev
->dev
,
853 "IO write error!\n");
854 message
->state
= ERROR_STATE
;
856 /* Update total byte transfered */
857 message
->actual_length
+= drv_data
->len_in_bytes
;
858 /* Move to next transfer of this msg */
859 message
->state
= bfin_spi_next_transfer(drv_data
);
860 if (drv_data
->cs_change
)
861 bfin_spi_cs_deactive(drv_data
, chip
);
864 /* Schedule next transfer tasklet */
865 tasklet_schedule(&drv_data
->pump_transfers
);
868 /* pop a msg from queue and kick off real transfer */
869 static void bfin_spi_pump_messages(struct work_struct
*work
)
871 struct master_data
*drv_data
;
874 drv_data
= container_of(work
, struct master_data
, pump_messages
);
876 /* Lock queue and check for queue work */
877 spin_lock_irqsave(&drv_data
->lock
, flags
);
878 if (list_empty(&drv_data
->queue
) || !drv_data
->running
) {
879 /* pumper kicked off but no work to do */
881 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
885 /* Make sure we are not already running a message */
886 if (drv_data
->cur_msg
) {
887 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
891 /* Extract head of queue */
892 drv_data
->cur_msg
= list_entry(drv_data
->queue
.next
,
893 struct spi_message
, queue
);
895 /* Setup the SSP using the per chip configuration */
896 drv_data
->cur_chip
= spi_get_ctldata(drv_data
->cur_msg
->spi
);
897 bfin_spi_restore_state(drv_data
);
899 list_del_init(&drv_data
->cur_msg
->queue
);
901 /* Initial message state */
902 drv_data
->cur_msg
->state
= START_STATE
;
903 drv_data
->cur_transfer
= list_entry(drv_data
->cur_msg
->transfers
.next
,
904 struct spi_transfer
, transfer_list
);
906 dev_dbg(&drv_data
->pdev
->dev
, "got a message to pump, "
907 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
908 drv_data
->cur_chip
->baud
, drv_data
->cur_chip
->flag
,
909 drv_data
->cur_chip
->ctl_reg
);
911 dev_dbg(&drv_data
->pdev
->dev
,
912 "the first transfer len is %d\n",
913 drv_data
->cur_transfer
->len
);
915 /* Mark as busy and launch transfers */
916 tasklet_schedule(&drv_data
->pump_transfers
);
919 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
923 * got a msg to transfer, queue it in drv_data->queue.
924 * And kick off message pumper
926 static int bfin_spi_transfer(struct spi_device
*spi
, struct spi_message
*msg
)
928 struct master_data
*drv_data
= spi_master_get_devdata(spi
->master
);
931 spin_lock_irqsave(&drv_data
->lock
, flags
);
933 if (!drv_data
->running
) {
934 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
938 msg
->actual_length
= 0;
939 msg
->status
= -EINPROGRESS
;
940 msg
->state
= START_STATE
;
942 dev_dbg(&spi
->dev
, "adding an msg in transfer() \n");
943 list_add_tail(&msg
->queue
, &drv_data
->queue
);
945 if (drv_data
->running
&& !drv_data
->busy
)
946 queue_work(drv_data
->workqueue
, &drv_data
->pump_messages
);
948 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
953 #define MAX_SPI_SSEL 7
955 static u16 ssel
[][MAX_SPI_SSEL
] = {
956 {P_SPI0_SSEL1
, P_SPI0_SSEL2
, P_SPI0_SSEL3
,
957 P_SPI0_SSEL4
, P_SPI0_SSEL5
,
958 P_SPI0_SSEL6
, P_SPI0_SSEL7
},
960 {P_SPI1_SSEL1
, P_SPI1_SSEL2
, P_SPI1_SSEL3
,
961 P_SPI1_SSEL4
, P_SPI1_SSEL5
,
962 P_SPI1_SSEL6
, P_SPI1_SSEL7
},
964 {P_SPI2_SSEL1
, P_SPI2_SSEL2
, P_SPI2_SSEL3
,
965 P_SPI2_SSEL4
, P_SPI2_SSEL5
,
966 P_SPI2_SSEL6
, P_SPI2_SSEL7
},
969 /* setup for devices (may be called multiple times -- not just first setup) */
970 static int bfin_spi_setup(struct spi_device
*spi
)
972 struct bfin5xx_spi_chip
*chip_info
;
973 struct slave_data
*chip
= NULL
;
974 struct master_data
*drv_data
= spi_master_get_devdata(spi
->master
);
977 /* Only alloc (or use chip_info) on first setup */
979 chip
= spi_get_ctldata(spi
);
981 chip
= kzalloc(sizeof(*chip
), GFP_KERNEL
);
983 dev_err(&spi
->dev
, "cannot allocate chip data\n");
988 chip
->enable_dma
= 0;
989 chip_info
= spi
->controller_data
;
992 /* chip_info isn't always needed */
994 /* Make sure people stop trying to set fields via ctl_reg
995 * when they should actually be using common SPI framework.
996 * Currently we let through: WOM EMISO PSSE GM SZ.
997 * Not sure if a user actually needs/uses any of these,
998 * but let's assume (for now) they do.
1000 if (chip_info
->ctl_reg
& ~(BIT_CTL_OPENDRAIN
| BIT_CTL_EMISO
| \
1001 BIT_CTL_PSSE
| BIT_CTL_GM
| BIT_CTL_SZ
)) {
1002 dev_err(&spi
->dev
, "do not set bits in ctl_reg "
1003 "that the SPI framework manages\n");
1007 chip
->enable_dma
= chip_info
->enable_dma
!= 0
1008 && drv_data
->master_info
->enable_dma
;
1009 chip
->ctl_reg
= chip_info
->ctl_reg
;
1010 chip
->cs_chg_udelay
= chip_info
->cs_chg_udelay
;
1011 chip
->idle_tx_val
= chip_info
->idle_tx_val
;
1012 chip
->pio_interrupt
= chip_info
->pio_interrupt
;
1013 spi
->bits_per_word
= chip_info
->bits_per_word
;
1016 if (spi
->bits_per_word
!= 8 && spi
->bits_per_word
!= 16) {
1017 dev_err(&spi
->dev
, "%d bits_per_word is not supported\n",
1018 spi
->bits_per_word
);
1022 /* translate common spi framework into our register */
1023 if (spi
->mode
& SPI_CPOL
)
1024 chip
->ctl_reg
|= BIT_CTL_CPOL
;
1025 if (spi
->mode
& SPI_CPHA
)
1026 chip
->ctl_reg
|= BIT_CTL_CPHA
;
1027 if (spi
->mode
& SPI_LSB_FIRST
)
1028 chip
->ctl_reg
|= BIT_CTL_LSBF
;
1029 /* we dont support running in slave mode (yet?) */
1030 chip
->ctl_reg
|= BIT_CTL_MASTER
;
1033 * Notice: for blackfin, the speed_hz is the value of register
1034 * SPI_BAUD, not the real baudrate
1036 chip
->baud
= hz_to_spi_baud(spi
->max_speed_hz
);
1037 chip
->chip_select_num
= spi
->chip_select
;
1038 if (chip
->chip_select_num
< MAX_CTRL_CS
)
1039 chip
->flag
= (1 << spi
->chip_select
) << 8;
1041 chip
->cs_gpio
= chip
->chip_select_num
- MAX_CTRL_CS
;
1043 if (chip
->enable_dma
&& chip
->pio_interrupt
) {
1044 dev_err(&spi
->dev
, "enable_dma is set, "
1045 "do not set pio_interrupt\n");
1049 * if any one SPI chip is registered and wants DMA, request the
1050 * DMA channel for it
1052 if (chip
->enable_dma
&& !drv_data
->dma_requested
) {
1053 /* register dma irq handler */
1054 ret
= request_dma(drv_data
->dma_channel
, "BFIN_SPI_DMA");
1057 "Unable to request BlackFin SPI DMA channel\n");
1060 drv_data
->dma_requested
= 1;
1062 ret
= set_dma_callback(drv_data
->dma_channel
,
1063 bfin_spi_dma_irq_handler
, drv_data
);
1065 dev_err(&spi
->dev
, "Unable to set dma callback\n");
1068 dma_disable_irq(drv_data
->dma_channel
);
1071 if (chip
->pio_interrupt
&& !drv_data
->irq_requested
) {
1072 ret
= request_irq(drv_data
->spi_irq
, bfin_spi_pio_irq_handler
,
1073 IRQF_DISABLED
, "BFIN_SPI", drv_data
);
1075 dev_err(&spi
->dev
, "Unable to register spi IRQ\n");
1078 drv_data
->irq_requested
= 1;
1079 /* we use write mode, spi irq has to be disabled here */
1080 disable_irq(drv_data
->spi_irq
);
1083 if (chip
->chip_select_num
>= MAX_CTRL_CS
) {
1084 ret
= gpio_request(chip
->cs_gpio
, spi
->modalias
);
1086 dev_err(&spi
->dev
, "gpio_request() error\n");
1089 gpio_direction_output(chip
->cs_gpio
, 1);
1092 dev_dbg(&spi
->dev
, "setup spi chip %s, width is %d, dma is %d\n",
1093 spi
->modalias
, spi
->bits_per_word
, chip
->enable_dma
);
1094 dev_dbg(&spi
->dev
, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
1095 chip
->ctl_reg
, chip
->flag
);
1097 spi_set_ctldata(spi
, chip
);
1099 dev_dbg(&spi
->dev
, "chip select number is %d\n", chip
->chip_select_num
);
1100 if (chip
->chip_select_num
< MAX_CTRL_CS
) {
1101 ret
= peripheral_request(ssel
[spi
->master
->bus_num
]
1102 [chip
->chip_select_num
-1], spi
->modalias
);
1104 dev_err(&spi
->dev
, "peripheral_request() error\n");
1109 bfin_spi_cs_enable(drv_data
, chip
);
1110 bfin_spi_cs_deactive(drv_data
, chip
);
1115 if (chip
->chip_select_num
>= MAX_CTRL_CS
)
1116 gpio_free(chip
->cs_gpio
);
1118 peripheral_free(ssel
[spi
->master
->bus_num
]
1119 [chip
->chip_select_num
- 1]);
1122 if (drv_data
->dma_requested
)
1123 free_dma(drv_data
->dma_channel
);
1124 drv_data
->dma_requested
= 0;
1127 /* prevent free 'chip' twice */
1128 spi_set_ctldata(spi
, NULL
);
1135 * callback for spi framework.
1136 * clean driver specific data
1138 static void bfin_spi_cleanup(struct spi_device
*spi
)
1140 struct slave_data
*chip
= spi_get_ctldata(spi
);
1141 struct master_data
*drv_data
= spi_master_get_devdata(spi
->master
);
1146 if (chip
->chip_select_num
< MAX_CTRL_CS
) {
1147 peripheral_free(ssel
[spi
->master
->bus_num
]
1148 [chip
->chip_select_num
-1]);
1149 bfin_spi_cs_disable(drv_data
, chip
);
1151 gpio_free(chip
->cs_gpio
);
1154 /* prevent free 'chip' twice */
1155 spi_set_ctldata(spi
, NULL
);
1158 static inline int bfin_spi_init_queue(struct master_data
*drv_data
)
1160 INIT_LIST_HEAD(&drv_data
->queue
);
1161 spin_lock_init(&drv_data
->lock
);
1163 drv_data
->running
= false;
1166 /* init transfer tasklet */
1167 tasklet_init(&drv_data
->pump_transfers
,
1168 bfin_spi_pump_transfers
, (unsigned long)drv_data
);
1170 /* init messages workqueue */
1171 INIT_WORK(&drv_data
->pump_messages
, bfin_spi_pump_messages
);
1172 drv_data
->workqueue
= create_singlethread_workqueue(
1173 dev_name(drv_data
->master
->dev
.parent
));
1174 if (drv_data
->workqueue
== NULL
)
1180 static inline int bfin_spi_start_queue(struct master_data
*drv_data
)
1182 unsigned long flags
;
1184 spin_lock_irqsave(&drv_data
->lock
, flags
);
1186 if (drv_data
->running
|| drv_data
->busy
) {
1187 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
1191 drv_data
->running
= true;
1192 drv_data
->cur_msg
= NULL
;
1193 drv_data
->cur_transfer
= NULL
;
1194 drv_data
->cur_chip
= NULL
;
1195 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
1197 queue_work(drv_data
->workqueue
, &drv_data
->pump_messages
);
1202 static inline int bfin_spi_stop_queue(struct master_data
*drv_data
)
1204 unsigned long flags
;
1205 unsigned limit
= 500;
1208 spin_lock_irqsave(&drv_data
->lock
, flags
);
1211 * This is a bit lame, but is optimized for the common execution path.
1212 * A wait_queue on the drv_data->busy could be used, but then the common
1213 * execution path (pump_messages) would be required to call wake_up or
1214 * friends on every SPI message. Do this instead
1216 drv_data
->running
= false;
1217 while (!list_empty(&drv_data
->queue
) && drv_data
->busy
&& limit
--) {
1218 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
1220 spin_lock_irqsave(&drv_data
->lock
, flags
);
1223 if (!list_empty(&drv_data
->queue
) || drv_data
->busy
)
1226 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
1231 static inline int bfin_spi_destroy_queue(struct master_data
*drv_data
)
1235 status
= bfin_spi_stop_queue(drv_data
);
1239 destroy_workqueue(drv_data
->workqueue
);
1244 static int __init
bfin_spi_probe(struct platform_device
*pdev
)
1246 struct device
*dev
= &pdev
->dev
;
1247 struct bfin5xx_spi_master
*platform_info
;
1248 struct spi_master
*master
;
1249 struct master_data
*drv_data
;
1250 struct resource
*res
;
1253 platform_info
= dev
->platform_data
;
1255 /* Allocate master with space for drv_data */
1256 master
= spi_alloc_master(dev
, sizeof(*drv_data
));
1258 dev_err(&pdev
->dev
, "can not alloc spi_master\n");
1262 drv_data
= spi_master_get_devdata(master
);
1263 drv_data
->master
= master
;
1264 drv_data
->master_info
= platform_info
;
1265 drv_data
->pdev
= pdev
;
1266 drv_data
->pin_req
= platform_info
->pin_req
;
1268 /* the spi->mode bits supported by this driver: */
1269 master
->mode_bits
= SPI_CPOL
| SPI_CPHA
| SPI_LSB_FIRST
;
1271 master
->bus_num
= pdev
->id
;
1272 master
->num_chipselect
= platform_info
->num_chipselect
;
1273 master
->cleanup
= bfin_spi_cleanup
;
1274 master
->setup
= bfin_spi_setup
;
1275 master
->transfer
= bfin_spi_transfer
;
1277 /* Find and map our resources */
1278 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1280 dev_err(dev
, "Cannot get IORESOURCE_MEM\n");
1282 goto out_error_get_res
;
1285 drv_data
->regs_base
= ioremap(res
->start
, resource_size(res
));
1286 if (drv_data
->regs_base
== NULL
) {
1287 dev_err(dev
, "Cannot map IO\n");
1289 goto out_error_ioremap
;
1292 res
= platform_get_resource(pdev
, IORESOURCE_DMA
, 0);
1294 dev_err(dev
, "No DMA channel specified\n");
1296 goto out_error_free_io
;
1298 drv_data
->dma_channel
= res
->start
;
1300 drv_data
->spi_irq
= platform_get_irq(pdev
, 0);
1301 if (drv_data
->spi_irq
< 0) {
1302 dev_err(dev
, "No spi pio irq specified\n");
1304 goto out_error_free_io
;
1307 /* Initial and start queue */
1308 status
= bfin_spi_init_queue(drv_data
);
1310 dev_err(dev
, "problem initializing queue\n");
1311 goto out_error_queue_alloc
;
1314 status
= bfin_spi_start_queue(drv_data
);
1316 dev_err(dev
, "problem starting queue\n");
1317 goto out_error_queue_alloc
;
1320 status
= peripheral_request_list(drv_data
->pin_req
, DRV_NAME
);
1322 dev_err(&pdev
->dev
, ": Requesting Peripherals failed\n");
1323 goto out_error_queue_alloc
;
1326 /* Reset SPI registers. If these registers were used by the boot loader,
1327 * the sky may fall on your head if you enable the dma controller.
1329 write_CTRL(drv_data
, BIT_CTL_CPHA
| BIT_CTL_MASTER
);
1330 write_FLAG(drv_data
, 0xFF00);
1332 /* Register with the SPI framework */
1333 platform_set_drvdata(pdev
, drv_data
);
1334 status
= spi_register_master(master
);
1336 dev_err(dev
, "problem registering spi master\n");
1337 goto out_error_queue_alloc
;
1340 dev_info(dev
, "%s, Version %s, regs_base@%p, dma channel@%d\n",
1341 DRV_DESC
, DRV_VERSION
, drv_data
->regs_base
,
1342 drv_data
->dma_channel
);
1345 out_error_queue_alloc
:
1346 bfin_spi_destroy_queue(drv_data
);
1348 iounmap((void *) drv_data
->regs_base
);
1351 spi_master_put(master
);
1356 /* stop hardware and remove the driver */
1357 static int __devexit
bfin_spi_remove(struct platform_device
*pdev
)
1359 struct master_data
*drv_data
= platform_get_drvdata(pdev
);
1365 /* Remove the queue */
1366 status
= bfin_spi_destroy_queue(drv_data
);
1370 /* Disable the SSP at the peripheral and SOC level */
1371 bfin_spi_disable(drv_data
);
1374 if (drv_data
->master_info
->enable_dma
) {
1375 if (dma_channel_active(drv_data
->dma_channel
))
1376 free_dma(drv_data
->dma_channel
);
1379 if (drv_data
->irq_requested
) {
1380 free_irq(drv_data
->spi_irq
, drv_data
);
1381 drv_data
->irq_requested
= 0;
1384 /* Disconnect from the SPI framework */
1385 spi_unregister_master(drv_data
->master
);
1387 peripheral_free_list(drv_data
->pin_req
);
1389 /* Prevent double remove */
1390 platform_set_drvdata(pdev
, NULL
);
1396 static int bfin_spi_suspend(struct platform_device
*pdev
, pm_message_t state
)
1398 struct master_data
*drv_data
= platform_get_drvdata(pdev
);
1401 status
= bfin_spi_stop_queue(drv_data
);
1405 drv_data
->ctrl_reg
= read_CTRL(drv_data
);
1406 drv_data
->flag_reg
= read_FLAG(drv_data
);
1409 * reset SPI_CTL and SPI_FLG registers
1411 write_CTRL(drv_data
, BIT_CTL_CPHA
| BIT_CTL_MASTER
);
1412 write_FLAG(drv_data
, 0xFF00);
1417 static int bfin_spi_resume(struct platform_device
*pdev
)
1419 struct master_data
*drv_data
= platform_get_drvdata(pdev
);
1422 write_CTRL(drv_data
, drv_data
->ctrl_reg
);
1423 write_FLAG(drv_data
, drv_data
->flag_reg
);
1425 /* Start the queue running */
1426 status
= bfin_spi_start_queue(drv_data
);
1428 dev_err(&pdev
->dev
, "problem starting queue (%d)\n", status
);
1435 #define bfin_spi_suspend NULL
1436 #define bfin_spi_resume NULL
1437 #endif /* CONFIG_PM */
1439 MODULE_ALIAS("platform:bfin-spi");
1440 static struct platform_driver bfin_spi_driver
= {
1443 .owner
= THIS_MODULE
,
1445 .suspend
= bfin_spi_suspend
,
1446 .resume
= bfin_spi_resume
,
1447 .remove
= __devexit_p(bfin_spi_remove
),
1450 static int __init
bfin_spi_init(void)
1452 return platform_driver_probe(&bfin_spi_driver
, bfin_spi_probe
);
1454 module_init(bfin_spi_init
);
1456 static void __exit
bfin_spi_exit(void)
1458 platform_driver_unregister(&bfin_spi_driver
);
1460 module_exit(bfin_spi_exit
);