3 * Support for Intel Camera Imaging ISP subsystem.
4 * Copyright (c) 2015, Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 Support for Intel Camera Imaging ISP subsystem.
18 Copyright (c) 2010 - 2015, Intel Corporation.
20 This program is free software; you can redistribute it and/or modify it
21 under the terms and conditions of the GNU General Public License,
22 version 2, as published by the Free Software Foundation.
24 This program is distributed in the hope it will be useful, but WITHOUT
25 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
26 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
31 #define __INLINE_INPUT_SYSTEM__
32 #include "input_system.h"
33 #include "assert_support.h"
34 #include "ia_css_isys.h"
35 #include "ia_css_irq.h"
36 #include "sh_css_internal.h"
38 #if !defined(USE_INPUT_SYSTEM_VERSION_2401)
39 void ia_css_isys_rx_enable_all_interrupts(mipi_port_ID_t port
)
41 hrt_data bits
= receiver_port_reg_load(RX0_ID
,
43 _HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX
);
45 bits
|= (1U << _HRT_CSS_RECEIVER_IRQ_OVERRUN_BIT
) |
46 #if defined(HAS_RX_VERSION_2)
47 (1U << _HRT_CSS_RECEIVER_IRQ_INIT_TIMEOUT_BIT
) |
49 (1U << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_ENTRY_BIT
) |
50 (1U << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_EXIT_BIT
) |
51 (1U << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_HS_BIT
) |
52 (1U << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_SYNC_HS_BIT
) |
53 (1U << _HRT_CSS_RECEIVER_IRQ_ERR_CONTROL_BIT
) |
54 (1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_DOUBLE_BIT
) |
55 (1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_CORRECTED_BIT
) |
56 /*(1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_NO_CORRECTION_BIT) | */
57 (1U << _HRT_CSS_RECEIVER_IRQ_ERR_CRC_BIT
) |
58 (1U << _HRT_CSS_RECEIVER_IRQ_ERR_ID_BIT
) |
59 (1U << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_SYNC_BIT
) |
60 (1U << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_DATA_BIT
) |
61 (1U << _HRT_CSS_RECEIVER_IRQ_DATA_TIMEOUT_BIT
) |
62 (1U << _HRT_CSS_RECEIVER_IRQ_ERR_ESCAPE_BIT
);
63 /*(1U << _HRT_CSS_RECEIVER_IRQ_ERR_LINE_SYNC_BIT); */
65 receiver_port_reg_store(RX0_ID
,
67 _HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX
, bits
);
70 * The CSI is nested into the Iunit IRQ's
72 ia_css_irq_enable(IA_CSS_IRQ_INFO_CSS_RECEIVER_ERROR
, true);
77 /* This function converts between the enum used on the CSS API and the
78 * internal DLI enum type.
79 * We do not use an array for this since we cannot use named array
80 * initializers in Windows. Without that there is no easy way to guarantee
81 * that the array values would be in the correct order.
83 mipi_port_ID_t
ia_css_isys_port_to_mipi_port(enum ia_css_csi2_port api_port
)
85 /* In this module the validity of the inptu variable should
86 * have been checked already, so we do not check for erroneous
88 mipi_port_ID_t port
= MIPI_PORT0_ID
;
90 if (api_port
== IA_CSS_CSI2_PORT1
)
92 else if (api_port
== IA_CSS_CSI2_PORT2
)
98 unsigned int ia_css_isys_rx_get_interrupt_reg(mipi_port_ID_t port
)
100 return receiver_port_reg_load(RX0_ID
,
102 _HRT_CSS_RECEIVER_IRQ_STATUS_REG_IDX
);
105 void ia_css_rx_get_irq_info(unsigned int *irq_infos
)
107 ia_css_rx_port_get_irq_info(IA_CSS_CSI2_PORT1
, irq_infos
);
110 void ia_css_rx_port_get_irq_info(enum ia_css_csi2_port api_port
,
111 unsigned int *irq_infos
)
113 mipi_port_ID_t port
= ia_css_isys_port_to_mipi_port(api_port
);
114 ia_css_isys_rx_get_irq_info(port
, irq_infos
);
117 void ia_css_isys_rx_get_irq_info(mipi_port_ID_t port
,
118 unsigned int *irq_infos
)
122 assert(irq_infos
!= NULL
);
123 bits
= ia_css_isys_rx_get_interrupt_reg(port
);
124 *irq_infos
= ia_css_isys_rx_translate_irq_infos(bits
);
127 /* Translate register bits to CSS API enum mask */
128 unsigned int ia_css_isys_rx_translate_irq_infos(unsigned int bits
)
130 unsigned int infos
= 0;
132 if (bits
& (1U << _HRT_CSS_RECEIVER_IRQ_OVERRUN_BIT
))
133 infos
|= IA_CSS_RX_IRQ_INFO_BUFFER_OVERRUN
;
134 #if defined(HAS_RX_VERSION_2)
135 if (bits
& (1U << _HRT_CSS_RECEIVER_IRQ_INIT_TIMEOUT_BIT
))
136 infos
|= IA_CSS_RX_IRQ_INFO_INIT_TIMEOUT
;
138 if (bits
& (1U << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_ENTRY_BIT
))
139 infos
|= IA_CSS_RX_IRQ_INFO_ENTER_SLEEP_MODE
;
140 if (bits
& (1U << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_EXIT_BIT
))
141 infos
|= IA_CSS_RX_IRQ_INFO_EXIT_SLEEP_MODE
;
142 if (bits
& (1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_CORRECTED_BIT
))
143 infos
|= IA_CSS_RX_IRQ_INFO_ECC_CORRECTED
;
144 if (bits
& (1U << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_HS_BIT
))
145 infos
|= IA_CSS_RX_IRQ_INFO_ERR_SOT
;
146 if (bits
& (1U << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_SYNC_HS_BIT
))
147 infos
|= IA_CSS_RX_IRQ_INFO_ERR_SOT_SYNC
;
148 if (bits
& (1U << _HRT_CSS_RECEIVER_IRQ_ERR_CONTROL_BIT
))
149 infos
|= IA_CSS_RX_IRQ_INFO_ERR_CONTROL
;
150 if (bits
& (1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_DOUBLE_BIT
))
151 infos
|= IA_CSS_RX_IRQ_INFO_ERR_ECC_DOUBLE
;
152 if (bits
& (1U << _HRT_CSS_RECEIVER_IRQ_ERR_CRC_BIT
))
153 infos
|= IA_CSS_RX_IRQ_INFO_ERR_CRC
;
154 if (bits
& (1U << _HRT_CSS_RECEIVER_IRQ_ERR_ID_BIT
))
155 infos
|= IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ID
;
156 if (bits
& (1U << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_SYNC_BIT
))
157 infos
|= IA_CSS_RX_IRQ_INFO_ERR_FRAME_SYNC
;
158 if (bits
& (1U << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_DATA_BIT
))
159 infos
|= IA_CSS_RX_IRQ_INFO_ERR_FRAME_DATA
;
160 if (bits
& (1U << _HRT_CSS_RECEIVER_IRQ_DATA_TIMEOUT_BIT
))
161 infos
|= IA_CSS_RX_IRQ_INFO_ERR_DATA_TIMEOUT
;
162 if (bits
& (1U << _HRT_CSS_RECEIVER_IRQ_ERR_ESCAPE_BIT
))
163 infos
|= IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ESC
;
164 if (bits
& (1U << _HRT_CSS_RECEIVER_IRQ_ERR_LINE_SYNC_BIT
))
165 infos
|= IA_CSS_RX_IRQ_INFO_ERR_LINE_SYNC
;
170 void ia_css_rx_clear_irq_info(unsigned int irq_infos
)
172 ia_css_rx_port_clear_irq_info(IA_CSS_CSI2_PORT1
, irq_infos
);
175 void ia_css_rx_port_clear_irq_info(enum ia_css_csi2_port api_port
, unsigned int irq_infos
)
177 mipi_port_ID_t port
= ia_css_isys_port_to_mipi_port(api_port
);
178 ia_css_isys_rx_clear_irq_info(port
, irq_infos
);
181 void ia_css_isys_rx_clear_irq_info(mipi_port_ID_t port
, unsigned int irq_infos
)
183 hrt_data bits
= receiver_port_reg_load(RX0_ID
,
185 _HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX
);
187 /* MW: Why do we remap the receiver bitmap */
188 if (irq_infos
& IA_CSS_RX_IRQ_INFO_BUFFER_OVERRUN
)
189 bits
|= 1U << _HRT_CSS_RECEIVER_IRQ_OVERRUN_BIT
;
190 #if defined(HAS_RX_VERSION_2)
191 if (irq_infos
& IA_CSS_RX_IRQ_INFO_INIT_TIMEOUT
)
192 bits
|= 1U << _HRT_CSS_RECEIVER_IRQ_INIT_TIMEOUT_BIT
;
194 if (irq_infos
& IA_CSS_RX_IRQ_INFO_ENTER_SLEEP_MODE
)
195 bits
|= 1U << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_ENTRY_BIT
;
196 if (irq_infos
& IA_CSS_RX_IRQ_INFO_EXIT_SLEEP_MODE
)
197 bits
|= 1U << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_EXIT_BIT
;
198 if (irq_infos
& IA_CSS_RX_IRQ_INFO_ECC_CORRECTED
)
199 bits
|= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_CORRECTED_BIT
;
200 if (irq_infos
& IA_CSS_RX_IRQ_INFO_ERR_SOT
)
201 bits
|= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_HS_BIT
;
202 if (irq_infos
& IA_CSS_RX_IRQ_INFO_ERR_SOT_SYNC
)
203 bits
|= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_SYNC_HS_BIT
;
204 if (irq_infos
& IA_CSS_RX_IRQ_INFO_ERR_CONTROL
)
205 bits
|= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_CONTROL_BIT
;
206 if (irq_infos
& IA_CSS_RX_IRQ_INFO_ERR_ECC_DOUBLE
)
207 bits
|= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_DOUBLE_BIT
;
208 if (irq_infos
& IA_CSS_RX_IRQ_INFO_ERR_CRC
)
209 bits
|= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_CRC_BIT
;
210 if (irq_infos
& IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ID
)
211 bits
|= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_ID_BIT
;
212 if (irq_infos
& IA_CSS_RX_IRQ_INFO_ERR_FRAME_SYNC
)
213 bits
|= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_SYNC_BIT
;
214 if (irq_infos
& IA_CSS_RX_IRQ_INFO_ERR_FRAME_DATA
)
215 bits
|= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_DATA_BIT
;
216 if (irq_infos
& IA_CSS_RX_IRQ_INFO_ERR_DATA_TIMEOUT
)
217 bits
|= 1U << _HRT_CSS_RECEIVER_IRQ_DATA_TIMEOUT_BIT
;
218 if (irq_infos
& IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ESC
)
219 bits
|= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_ESCAPE_BIT
;
220 if (irq_infos
& IA_CSS_RX_IRQ_INFO_ERR_LINE_SYNC
)
221 bits
|= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_LINE_SYNC_BIT
;
223 receiver_port_reg_store(RX0_ID
,
225 _HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX
, bits
);
229 #endif /* #if !defined(USE_INPUT_SYSTEM_VERSION_2401) */
231 enum ia_css_err
ia_css_isys_convert_stream_format_to_mipi_format(
232 enum ia_css_stream_format input_format
,
233 mipi_predictor_t compression
,
234 unsigned int *fmt_type
)
236 assert(fmt_type
!= NULL
);
238 * Custom (user defined) modes. Used for compressed
241 * Checkpatch thinks the indent before "if" is suspect
242 * I think the only suspect part is the missing "else"
243 * because of the return.
245 if (compression
!= MIPI_PREDICTOR_NONE
) {
246 switch (input_format
) {
247 case IA_CSS_STREAM_FORMAT_RAW_6
:
250 case IA_CSS_STREAM_FORMAT_RAW_7
:
253 case IA_CSS_STREAM_FORMAT_RAW_8
:
256 case IA_CSS_STREAM_FORMAT_RAW_10
:
259 case IA_CSS_STREAM_FORMAT_RAW_12
:
262 case IA_CSS_STREAM_FORMAT_RAW_14
:
265 case IA_CSS_STREAM_FORMAT_RAW_16
:
269 return IA_CSS_ERR_INTERNAL_ERROR
;
271 return IA_CSS_SUCCESS
;
274 * This mapping comes from the Arasan CSS function spec
275 * (CSS_func_spec1.08_ahb_sep29_08.pdf).
277 * MW: For some reason the mapping is not 1-to-1
279 switch (input_format
) {
280 case IA_CSS_STREAM_FORMAT_RGB_888
:
281 *fmt_type
= MIPI_FORMAT_RGB888
;
283 case IA_CSS_STREAM_FORMAT_RGB_555
:
284 *fmt_type
= MIPI_FORMAT_RGB555
;
286 case IA_CSS_STREAM_FORMAT_RGB_444
:
287 *fmt_type
= MIPI_FORMAT_RGB444
;
289 case IA_CSS_STREAM_FORMAT_RGB_565
:
290 *fmt_type
= MIPI_FORMAT_RGB565
;
292 case IA_CSS_STREAM_FORMAT_RGB_666
:
293 *fmt_type
= MIPI_FORMAT_RGB666
;
295 case IA_CSS_STREAM_FORMAT_RAW_8
:
296 *fmt_type
= MIPI_FORMAT_RAW8
;
298 case IA_CSS_STREAM_FORMAT_RAW_10
:
299 *fmt_type
= MIPI_FORMAT_RAW10
;
301 case IA_CSS_STREAM_FORMAT_RAW_6
:
302 *fmt_type
= MIPI_FORMAT_RAW6
;
304 case IA_CSS_STREAM_FORMAT_RAW_7
:
305 *fmt_type
= MIPI_FORMAT_RAW7
;
307 case IA_CSS_STREAM_FORMAT_RAW_12
:
308 *fmt_type
= MIPI_FORMAT_RAW12
;
310 case IA_CSS_STREAM_FORMAT_RAW_14
:
311 *fmt_type
= MIPI_FORMAT_RAW14
;
313 case IA_CSS_STREAM_FORMAT_YUV420_8
:
314 *fmt_type
= MIPI_FORMAT_YUV420_8
;
316 case IA_CSS_STREAM_FORMAT_YUV420_10
:
317 *fmt_type
= MIPI_FORMAT_YUV420_10
;
319 case IA_CSS_STREAM_FORMAT_YUV422_8
:
320 *fmt_type
= MIPI_FORMAT_YUV422_8
;
322 case IA_CSS_STREAM_FORMAT_YUV422_10
:
323 *fmt_type
= MIPI_FORMAT_YUV422_10
;
325 case IA_CSS_STREAM_FORMAT_YUV420_8_LEGACY
:
326 *fmt_type
= MIPI_FORMAT_YUV420_8_LEGACY
;
328 case IA_CSS_STREAM_FORMAT_EMBEDDED
:
329 *fmt_type
= MIPI_FORMAT_EMBEDDED
;
331 #ifndef USE_INPUT_SYSTEM_VERSION_2401
332 case IA_CSS_STREAM_FORMAT_RAW_16
:
333 /* This is not specified by Arasan, so we use
336 *fmt_type
= MIPI_FORMAT_RAW16
;
338 case IA_CSS_STREAM_FORMAT_BINARY_8
:
339 *fmt_type
= MIPI_FORMAT_BINARY_8
;
342 case IA_CSS_STREAM_FORMAT_USER_DEF1
:
343 *fmt_type
= MIPI_FORMAT_CUSTOM0
;
345 case IA_CSS_STREAM_FORMAT_USER_DEF2
:
346 *fmt_type
= MIPI_FORMAT_CUSTOM1
;
348 case IA_CSS_STREAM_FORMAT_USER_DEF3
:
349 *fmt_type
= MIPI_FORMAT_CUSTOM2
;
351 case IA_CSS_STREAM_FORMAT_USER_DEF4
:
352 *fmt_type
= MIPI_FORMAT_CUSTOM3
;
354 case IA_CSS_STREAM_FORMAT_USER_DEF5
:
355 *fmt_type
= MIPI_FORMAT_CUSTOM4
;
357 case IA_CSS_STREAM_FORMAT_USER_DEF6
:
358 *fmt_type
= MIPI_FORMAT_CUSTOM5
;
360 case IA_CSS_STREAM_FORMAT_USER_DEF7
:
361 *fmt_type
= MIPI_FORMAT_CUSTOM6
;
363 case IA_CSS_STREAM_FORMAT_USER_DEF8
:
364 *fmt_type
= MIPI_FORMAT_CUSTOM7
;
368 case IA_CSS_STREAM_FORMAT_YUV420_16
:
369 case IA_CSS_STREAM_FORMAT_YUV422_16
:
371 return IA_CSS_ERR_INTERNAL_ERROR
;
373 return IA_CSS_SUCCESS
;
375 #if defined(USE_INPUT_SYSTEM_VERSION_2401)
376 static mipi_predictor_t
sh_css_csi2_compression_type_2_mipi_predictor(enum ia_css_csi2_compression_type type
)
378 mipi_predictor_t predictor
= MIPI_PREDICTOR_NONE
;
381 case IA_CSS_CSI2_COMPRESSION_TYPE_1
:
382 predictor
= MIPI_PREDICTOR_TYPE1
-1;
384 case IA_CSS_CSI2_COMPRESSION_TYPE_2
:
385 predictor
= MIPI_PREDICTOR_TYPE2
-1;
391 enum ia_css_err
ia_css_isys_convert_compressed_format(
392 struct ia_css_csi2_compression
*comp
,
393 struct input_system_cfg_s
*cfg
)
395 enum ia_css_err err
= IA_CSS_SUCCESS
;
396 assert(comp
!= NULL
);
399 if (comp
->type
!= IA_CSS_CSI2_COMPRESSION_TYPE_NONE
) {
400 /* compression register bit slicing
401 4 bit for each user defined data type
402 3 bit indicate compression scheme
411 1 bit indicate predictor
413 if (comp
->uncompressed_bits_per_pixel
== UNCOMPRESSED_BITS_PER_PIXEL_10
) {
414 switch (comp
->compressed_bits_per_pixel
) {
415 case COMPRESSED_BITS_PER_PIXEL_6
:
416 cfg
->csi_port_attr
.comp_scheme
= MIPI_COMPRESSOR_10_6_10
;
418 case COMPRESSED_BITS_PER_PIXEL_7
:
419 cfg
->csi_port_attr
.comp_scheme
= MIPI_COMPRESSOR_10_7_10
;
421 case COMPRESSED_BITS_PER_PIXEL_8
:
422 cfg
->csi_port_attr
.comp_scheme
= MIPI_COMPRESSOR_10_8_10
;
425 err
= IA_CSS_ERR_INVALID_ARGUMENTS
;
427 } else if (comp
->uncompressed_bits_per_pixel
== UNCOMPRESSED_BITS_PER_PIXEL_12
) {
428 switch (comp
->compressed_bits_per_pixel
) {
429 case COMPRESSED_BITS_PER_PIXEL_6
:
430 cfg
->csi_port_attr
.comp_scheme
= MIPI_COMPRESSOR_12_6_12
;
432 case COMPRESSED_BITS_PER_PIXEL_7
:
433 cfg
->csi_port_attr
.comp_scheme
= MIPI_COMPRESSOR_12_7_12
;
435 case COMPRESSED_BITS_PER_PIXEL_8
:
436 cfg
->csi_port_attr
.comp_scheme
= MIPI_COMPRESSOR_12_8_12
;
439 err
= IA_CSS_ERR_INVALID_ARGUMENTS
;
442 err
= IA_CSS_ERR_INVALID_ARGUMENTS
;
443 cfg
->csi_port_attr
.comp_predictor
= sh_css_csi2_compression_type_2_mipi_predictor(comp
->type
);
444 cfg
->csi_port_attr
.comp_enable
= true;
445 } else /* No compression */
446 cfg
->csi_port_attr
.comp_enable
= false;
450 unsigned int ia_css_csi2_calculate_input_system_alignment(
451 enum ia_css_stream_format fmt_type
)
453 unsigned int memory_alignment_in_bytes
= HIVE_ISP_DDR_WORD_BYTES
;
456 case IA_CSS_STREAM_FORMAT_RAW_6
:
457 case IA_CSS_STREAM_FORMAT_RAW_7
:
458 case IA_CSS_STREAM_FORMAT_RAW_8
:
459 case IA_CSS_STREAM_FORMAT_RAW_10
:
460 case IA_CSS_STREAM_FORMAT_RAW_12
:
461 case IA_CSS_STREAM_FORMAT_RAW_14
:
462 memory_alignment_in_bytes
= 2 * ISP_VEC_NELEMS
;
464 case IA_CSS_STREAM_FORMAT_YUV420_8
:
465 case IA_CSS_STREAM_FORMAT_YUV422_8
:
466 case IA_CSS_STREAM_FORMAT_USER_DEF1
:
467 case IA_CSS_STREAM_FORMAT_USER_DEF2
:
468 case IA_CSS_STREAM_FORMAT_USER_DEF3
:
469 case IA_CSS_STREAM_FORMAT_USER_DEF4
:
470 case IA_CSS_STREAM_FORMAT_USER_DEF5
:
471 case IA_CSS_STREAM_FORMAT_USER_DEF6
:
472 case IA_CSS_STREAM_FORMAT_USER_DEF7
:
473 case IA_CSS_STREAM_FORMAT_USER_DEF8
:
474 /* Planar YUV formats need to have all planes aligned, this means
475 * double the alignment for the Y plane if the horizontal decimation is 2. */
476 memory_alignment_in_bytes
= 2 * HIVE_ISP_DDR_WORD_BYTES
;
478 case IA_CSS_STREAM_FORMAT_EMBEDDED
:
480 memory_alignment_in_bytes
= HIVE_ISP_DDR_WORD_BYTES
;
483 return memory_alignment_in_bytes
;
488 #if !defined(USE_INPUT_SYSTEM_VERSION_2401)
489 void ia_css_isys_rx_configure(const rx_cfg_t
*config
,
490 const enum ia_css_input_mode input_mode
)
492 #if defined(HAS_RX_VERSION_2)
493 bool port_enabled
[N_MIPI_PORT_ID
];
494 bool any_port_enabled
= false;
498 || (config
->mode
>= N_RX_MODE
)
499 || (config
->port
>= N_MIPI_PORT_ID
)) {
503 for (port
= (mipi_port_ID_t
) 0; port
< N_MIPI_PORT_ID
; port
++) {
504 if (is_receiver_port_enabled(RX0_ID
, port
))
505 any_port_enabled
= true;
507 /* AM: Check whether this is a problem with multiple
508 * streams. MS: This is the case. */
511 receiver_port_enable(RX0_ID
, port
, false);
515 /* AM: Check whether this is a problem with multiple streams. */
516 if (MIPI_PORT_LANES
[config
->mode
][port
] != MIPI_0LANE_CFG
) {
517 receiver_port_reg_store(RX0_ID
, port
,
518 _HRT_CSS_RECEIVER_FUNC_PROG_REG_IDX
,
520 receiver_port_reg_store(RX0_ID
, port
,
521 _HRT_CSS_RECEIVER_2400_INIT_COUNT_REG_IDX
,
523 receiver_port_reg_store(RX0_ID
, port
,
524 _HRT_CSS_RECEIVER_2400_SYNC_COUNT_REG_IDX
,
526 receiver_port_reg_store(RX0_ID
, port
,
527 _HRT_CSS_RECEIVER_2400_RX_COUNT_REG_IDX
,
530 port_enabled
[port
] = true;
532 if (input_mode
!= IA_CSS_INPUT_MODE_BUFFERED_SENSOR
) {
534 /* MW: A bit of a hack, straight wiring of the capture
535 * units,assuming they are linearly enumerated. */
536 input_system_sub_system_reg_store(INPUT_SYSTEM0_ID
,
538 HIVE_ISYS_GPREG_MULTICAST_A_IDX
539 + (unsigned int)port
,
540 INPUT_SYSTEM_CSI_BACKEND
);
541 /* MW: Like the integration test example we overwite,
542 * the GPREG_MUX register */
543 input_system_sub_system_reg_store(INPUT_SYSTEM0_ID
,
545 HIVE_ISYS_GPREG_MUX_IDX
,
546 (input_system_multiplex_t
) port
);
549 * AM: A bit of a hack, wiring the input system.
551 input_system_sub_system_reg_store(INPUT_SYSTEM0_ID
,
553 HIVE_ISYS_GPREG_MULTICAST_A_IDX
554 + (unsigned int)port
,
555 INPUT_SYSTEM_INPUT_BUFFER
);
556 input_system_sub_system_reg_store(INPUT_SYSTEM0_ID
,
558 HIVE_ISYS_GPREG_MUX_IDX
,
559 INPUT_SYSTEM_ACQUISITION_UNIT
);
563 * The 2ppc is shared for all ports, so we cannot
564 * disable->configure->enable individual ports
566 /* AM: Check whether this is a problem with multiple streams. */
567 /* MS: 2ppc should be a property per binary and should be
568 * enabled/disabled per binary.
569 * Currently it is implemented as a system wide setting due
570 * to effort and risks. */
571 if (!any_port_enabled
) {
572 receiver_reg_store(RX0_ID
,
573 _HRT_CSS_RECEIVER_TWO_PIXEL_EN_REG_IDX
,
575 receiver_reg_store(RX0_ID
, _HRT_CSS_RECEIVER_BE_TWO_PPC_REG_IDX
,
578 receiver_port_enable(RX0_ID
, port
, true);
579 /* TODO: JB: need to add the beneath used define to mizuchi */
580 /* sh_css_sw_hive_isp_css_2400_system_20121224_0125\css
581 * \hrt\input_system_defs.h
582 * #define INPUT_SYSTEM_CSI_RECEIVER_SELECT_BACKENG 0X207
584 /* TODO: need better name for define
585 * input_system_reg_store(INPUT_SYSTEM0_ID,
586 * INPUT_SYSTEM_CSI_RECEIVER_SELECT_BACKENG, 1);
588 input_system_reg_store(INPUT_SYSTEM0_ID
, 0x207, 1);
590 #error "rx.c: RX version must be one of {RX_VERSION_2}"
596 void ia_css_isys_rx_disable(void)
599 for (port
= (mipi_port_ID_t
) 0; port
< N_MIPI_PORT_ID
; port
++) {
600 receiver_port_reg_store(RX0_ID
, port
,
601 _HRT_CSS_RECEIVER_DEVICE_READY_REG_IDX
,
606 #endif /* if !defined(USE_INPUT_SYSTEM_VERSION_2401) */