drivers/staging/media/omap4iss/iss.h

   1 /*
   2  * TI OMAP4 ISS V4L2 Driver
   3  *
   4  * Copyright (C) 2012 Texas Instruments.
   5  *
   6  * Author: Sergio Aguirre <sergio.a.aguirre@gmail.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #ifndef _OMAP4_ISS_H_
  15 #define _OMAP4_ISS_H_
  16
  17 #include <media/v4l2-device.h>
  18 #include <linux/device.h>
  19 #include <linux/io.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/wait.h>
  22
  23 #include <media/omap4iss.h>
  24
  25 #include "iss_regs.h"
  26 #include "iss_csiphy.h"
  27 #include "iss_csi2.h"
  28 #include "iss_ipipeif.h"
  29 #include "iss_ipipe.h"
  30 #include "iss_resizer.h"
  31
  32 #define to_iss_device(ptr_module)                               \
  33         container_of(ptr_module, struct iss_device, ptr_module)
  34 #define to_device(ptr_module)                                           \
  35         (to_iss_device(ptr_module)->dev)
  36
  37 enum iss_mem_resources {
  38         OMAP4_ISS_MEM_TOP,
  39         OMAP4_ISS_MEM_CSI2_A_REGS1,
  40         OMAP4_ISS_MEM_CAMERARX_CORE1,
  41         OMAP4_ISS_MEM_CSI2_B_REGS1,
  42         OMAP4_ISS_MEM_CAMERARX_CORE2,
  43         OMAP4_ISS_MEM_BTE,
  44         OMAP4_ISS_MEM_ISP_SYS1,
  45         OMAP4_ISS_MEM_ISP_RESIZER,
  46         OMAP4_ISS_MEM_ISP_IPIPE,
  47         OMAP4_ISS_MEM_ISP_ISIF,
  48         OMAP4_ISS_MEM_ISP_IPIPEIF,
  49         OMAP4_ISS_MEM_LAST,
  50 };
  51
  52 enum iss_subclk_resource {
  53         OMAP4_ISS_SUBCLK_SIMCOP         = (1 << 0),
  54         OMAP4_ISS_SUBCLK_ISP            = (1 << 1),
  55         OMAP4_ISS_SUBCLK_CSI2_A         = (1 << 2),
  56         OMAP4_ISS_SUBCLK_CSI2_B         = (1 << 3),
  57         OMAP4_ISS_SUBCLK_CCP2           = (1 << 4),
  58 };
  59
  60 enum iss_isp_subclk_resource {
  61         OMAP4_ISS_ISP_SUBCLK_BL         = (1 << 0),
  62         OMAP4_ISS_ISP_SUBCLK_ISIF       = (1 << 1),
  63         OMAP4_ISS_ISP_SUBCLK_H3A        = (1 << 2),
  64         OMAP4_ISS_ISP_SUBCLK_RSZ        = (1 << 3),
  65         OMAP4_ISS_ISP_SUBCLK_IPIPE      = (1 << 4),
  66         OMAP4_ISS_ISP_SUBCLK_IPIPEIF    = (1 << 5),
  67 };
  68
  69 /*
  70  * struct iss_reg - Structure for ISS register values.
  71  * @reg: 32-bit Register address.
  72  * @val: 32-bit Register value.
  73  */
  74 struct iss_reg {
  75         enum iss_mem_resources mmio_range;
  76         u32 reg;
  77         u32 val;
  78 };
  79
  80 /*
  81  * struct iss_device - ISS device structure.
  82  * @crashed: Bitmask of crashed entities (indexed by entity ID)
  83  */
  84 struct iss_device {
  85         struct v4l2_device v4l2_dev;
  86         struct media_device media_dev;
  87         struct device *dev;
  88         u32 revision;
  89
  90         /* platform HW resources */
  91         struct iss_platform_data *pdata;
  92         unsigned int irq_num;
  93
  94         struct resource *res[OMAP4_ISS_MEM_LAST];
  95         void __iomem *regs[OMAP4_ISS_MEM_LAST];
  96
  97         u64 raw_dmamask;
  98
  99         struct mutex iss_mutex; /* For handling ref_count field */
 100         unsigned int crashed;
 101         int has_context;
 102         int ref_count;
 103
 104         struct clk *iss_fck;
 105         struct clk *iss_ctrlclk;
 106
 107         /* ISS modules */
 108         struct iss_csi2_device csi2a;
 109         struct iss_csi2_device csi2b;
 110         struct iss_csiphy csiphy1;
 111         struct iss_csiphy csiphy2;
 112         struct iss_ipipeif_device ipipeif;
 113         struct iss_ipipe_device ipipe;
 114         struct iss_resizer_device resizer;
 115
 116         unsigned int subclk_resources;
 117         unsigned int isp_subclk_resources;
 118 };
 119
 120 #define v4l2_dev_to_iss_device(dev) \
 121         container_of(dev, struct iss_device, v4l2_dev)
 122
 123 int omap4iss_get_external_info(struct iss_pipeline *pipe,
 124                                struct media_link *link);
 125
 126 int omap4iss_module_sync_idle(struct media_entity *me, wait_queue_head_t *wait,
 127                               atomic_t *stopping);
 128
 129 int omap4iss_module_sync_is_stopping(wait_queue_head_t *wait,
 130                                      atomic_t *stopping);
 131
 132 int omap4iss_pipeline_set_stream(struct iss_pipeline *pipe,
 133                                  enum iss_pipeline_stream_state state);
 134 void omap4iss_pipeline_cancel_stream(struct iss_pipeline *pipe);
 135
 136 void omap4iss_configure_bridge(struct iss_device *iss,
 137                                enum ipipeif_input_entity input);
 138
 139 struct iss_device *omap4iss_get(struct iss_device *iss);
 140 void omap4iss_put(struct iss_device *iss);
 141 int omap4iss_subclk_enable(struct iss_device *iss,
 142                            enum iss_subclk_resource res);
 143 int omap4iss_subclk_disable(struct iss_device *iss,
 144                             enum iss_subclk_resource res);
 145 void omap4iss_isp_subclk_enable(struct iss_device *iss,
 146                                 enum iss_isp_subclk_resource res);
 147 void omap4iss_isp_subclk_disable(struct iss_device *iss,
 148                                  enum iss_isp_subclk_resource res);
 149
 150 int omap4iss_pipeline_pm_use(struct media_entity *entity, int use);
 151
 152 int omap4iss_register_entities(struct platform_device *pdev,
 153                                struct v4l2_device *v4l2_dev);
 154 void omap4iss_unregister_entities(struct platform_device *pdev);
 155
 156 /*
 157  * iss_reg_read - Read the value of an OMAP4 ISS register
 158  * @iss: the ISS device
 159  * @res: memory resource in which the register is located
 160  * @offset: register offset in the memory resource
 161  *
 162  * Return the register value.
 163  */
 164 static inline
 165 u32 iss_reg_read(struct iss_device *iss, enum iss_mem_resources res,
 166                  u32 offset)
 167 {
 168         return readl(iss->regs[res] + offset);
 169 }
 170
 171 /*
 172  * iss_reg_write - Write a value to an OMAP4 ISS register
 173  * @iss: the ISS device
 174  * @res: memory resource in which the register is located
 175  * @offset: register offset in the memory resource
 176  * @value: value to be written
 177  */
 178 static inline
 179 void iss_reg_write(struct iss_device *iss, enum iss_mem_resources res,
 180                    u32 offset, u32 value)
 181 {
 182         writel(value, iss->regs[res] + offset);
 183 }
 184
 185 /*
 186  * iss_reg_clr - Clear bits in an OMAP4 ISS register
 187  * @iss: the ISS device
 188  * @res: memory resource in which the register is located
 189  * @offset: register offset in the memory resource
 190  * @clr: bit mask to be cleared
 191  */
 192 static inline
 193 void iss_reg_clr(struct iss_device *iss, enum iss_mem_resources res,
 194                  u32 offset, u32 clr)
 195 {
 196         u32 v = iss_reg_read(iss, res, offset);
 197
 198         iss_reg_write(iss, res, offset, v & ~clr);
 199 }
 200
 201 /*
 202  * iss_reg_set - Set bits in an OMAP4 ISS register
 203  * @iss: the ISS device
 204  * @res: memory resource in which the register is located
 205  * @offset: register offset in the memory resource
 206  * @set: bit mask to be set
 207  */
 208 static inline
 209 void iss_reg_set(struct iss_device *iss, enum iss_mem_resources res,
 210                  u32 offset, u32 set)
 211 {
 212         u32 v = iss_reg_read(iss, res, offset);
 213
 214         iss_reg_write(iss, res, offset, v | set);
 215 }
 216
 217 /*
 218  * iss_reg_update - Clear and set bits in an OMAP4 ISS register
 219  * @iss: the ISS device
 220  * @res: memory resource in which the register is located
 221  * @offset: register offset in the memory resource
 222  * @clr: bit mask to be cleared
 223  * @set: bit mask to be set
 224  *
 225  * Clear the clr mask first and then set the set mask.
 226  */
 227 static inline
 228 void iss_reg_update(struct iss_device *iss, enum iss_mem_resources res,
 229                     u32 offset, u32 clr, u32 set)
 230 {
 231         u32 v = iss_reg_read(iss, res, offset);
 232
 233         iss_reg_write(iss, res, offset, (v & ~clr) | set);
 234 }
 235
 236 #define iss_poll_condition_timeout(cond, timeout, min_ival, max_ival)   \
 237 ({                                                                      \
 238         unsigned long __timeout = jiffies + usecs_to_jiffies(timeout);  \
 239         unsigned int __min_ival = (min_ival);                           \
 240         unsigned int __max_ival = (max_ival);                           \
 241         bool __cond;                                                    \
 242         while (!(__cond = (cond))) {                                    \
 243                 if (time_after(jiffies, __timeout))                     \
 244                         break;                                          \
 245                 usleep_range(__min_ival, __max_ival);                   \
 246         }                                                               \
 247         !__cond;                                                        \
 248 })
 249
 250 #endif /* _OMAP4_ISS_H_ */