drivers/staging/rtl8723bs/hal/odm_RegDefine11N.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  ******************************************************************************/
  15
  16 #ifndef __ODM_REGDEFINE11N_H__
  17 #define __ODM_REGDEFINE11N_H__
  18
  19
  20 /* 2 RF REG LIST */
  21 #define ODM_REG_RF_MODE_11N                             0x00
  22 #define ODM_REG_RF_0B_11N                               0x0B
  23 #define ODM_REG_CHNBW_11N                               0x18
  24 #define ODM_REG_T_METER_11N                             0x24
  25 #define ODM_REG_RF_25_11N                               0x25
  26 #define ODM_REG_RF_26_11N                               0x26
  27 #define ODM_REG_RF_27_11N                               0x27
  28 #define ODM_REG_RF_2B_11N                               0x2B
  29 #define ODM_REG_RF_2C_11N                               0x2C
  30 #define ODM_REG_RXRF_A3_11N                             0x3C
  31 #define ODM_REG_T_METER_92D_11N                 0x42
  32 #define ODM_REG_T_METER_88E_11N                 0x42
  33
  34 /* 2 BB REG LIST */
  35 /* PAGE 8 */
  36 #define ODM_REG_BB_CTRL_11N                             0x800
  37 #define ODM_REG_RF_PIN_11N                              0x804
  38 #define ODM_REG_PSD_CTRL_11N                            0x808
  39 #define ODM_REG_TX_ANT_CTRL_11N                 0x80C
  40 #define ODM_REG_BB_PWR_SAV5_11N         0x818
  41 #define ODM_REG_CCK_RPT_FORMAT_11N              0x824
  42 #define ODM_REG_RX_DEFUALT_A_11N                0x858
  43 #define ODM_REG_RX_DEFUALT_B_11N                0x85A
  44 #define ODM_REG_BB_PWR_SAV3_11N         0x85C
  45 #define ODM_REG_ANTSEL_CTRL_11N                 0x860
  46 #define ODM_REG_RX_ANT_CTRL_11N                 0x864
  47 #define ODM_REG_PIN_CTRL_11N                            0x870
  48 #define ODM_REG_BB_PWR_SAV1_11N         0x874
  49 #define ODM_REG_ANTSEL_PATH_11N                 0x878
  50 #define ODM_REG_BB_3WIRE_11N                    0x88C
  51 #define ODM_REG_SC_CNT_11N                              0x8C4
  52 #define ODM_REG_PSD_DATA_11N                            0x8B4
  53 #define ODM_REG_PSD_DATA_11N                            0x8B4
  54 #define ODM_REG_NHM_TIMER_11N                   0x894
  55 #define ODM_REG_NHM_TH9_TH10_11N                0x890
  56 #define ODM_REG_NHM_TH3_TO_TH0_11N              0x898
  57 #define ODM_REG_NHM_TH7_TO_TH4_11N              0x89c
  58 #define ODM_REG_NHM_CNT_11N                             0x8d8
  59 /* PAGE 9 */
  60 #define ODM_REG_DBG_RPT_11N                             0x908
  61 #define ODM_REG_ANT_MAPPING1_11N                0x914
  62 #define ODM_REG_ANT_MAPPING2_11N                0x918
  63 /* PAGE A */
  64 #define ODM_REG_CCK_ANTDIV_PARA1_11N    0xA00
  65 #define ODM_REG_CCK_CCA_11N                             0xA0A
  66 #define ODM_REG_CCK_ANTDIV_PARA2_11N    0xA0C
  67 #define ODM_REG_CCK_ANTDIV_PARA3_11N    0xA10
  68 #define ODM_REG_CCK_ANTDIV_PARA4_11N    0xA14
  69 #define ODM_REG_CCK_FILTER_PARA1_11N    0xA22
  70 #define ODM_REG_CCK_FILTER_PARA2_11N    0xA23
  71 #define ODM_REG_CCK_FILTER_PARA3_11N    0xA24
  72 #define ODM_REG_CCK_FILTER_PARA4_11N    0xA25
  73 #define ODM_REG_CCK_FILTER_PARA5_11N    0xA26
  74 #define ODM_REG_CCK_FILTER_PARA6_11N    0xA27
  75 #define ODM_REG_CCK_FILTER_PARA7_11N    0xA28
  76 #define ODM_REG_CCK_FILTER_PARA8_11N    0xA29
  77 #define ODM_REG_CCK_FA_RST_11N                  0xA2C
  78 #define ODM_REG_CCK_FA_MSB_11N                  0xA58
  79 #define ODM_REG_CCK_FA_LSB_11N                  0xA5C
  80 #define ODM_REG_CCK_CCA_CNT_11N                 0xA60
  81 #define ODM_REG_BB_PWR_SAV4_11N         0xA74
  82 /* PAGE B */
  83 #define ODM_REG_LNA_SWITCH_11N                  0xB2C
  84 #define ODM_REG_PATH_SWITCH_11N                 0xB30
  85 #define ODM_REG_RSSI_CTRL_11N                   0xB38
  86 #define ODM_REG_CONFIG_ANTA_11N                 0xB68
  87 #define ODM_REG_RSSI_BT_11N                             0xB9C
  88 /* PAGE C */
  89 #define ODM_REG_OFDM_FA_HOLDC_11N               0xC00
  90 #define ODM_REG_BB_RX_PATH_11N                  0xC04
  91 #define ODM_REG_TRMUX_11N                               0xC08
  92 #define ODM_REG_OFDM_FA_RSTC_11N                0xC0C
  93 #define ODM_REG_RXIQI_MATRIX_11N                        0xC14
  94 #define ODM_REG_TXIQK_MATRIX_LSB1_11N   0xC4C
  95 #define ODM_REG_IGI_A_11N                                       0xC50
  96 #define ODM_REG_ANTDIV_PARA2_11N                0xC54
  97 #define ODM_REG_IGI_B_11N                                       0xC58
  98 #define ODM_REG_ANTDIV_PARA3_11N                0xC5C
  99 #define   ODM_REG_L1SBD_PD_CH_11N                       0XC6C
 100 #define ODM_REG_BB_PWR_SAV2_11N         0xC70
 101 #define ODM_REG_RX_OFF_11N                              0xC7C
 102 #define ODM_REG_TXIQK_MATRIXA_11N               0xC80
 103 #define ODM_REG_TXIQK_MATRIXB_11N               0xC88
 104 #define ODM_REG_TXIQK_MATRIXA_LSB2_11N  0xC94
 105 #define ODM_REG_TXIQK_MATRIXB_LSB2_11N  0xC9C
 106 #define ODM_REG_RXIQK_MATRIX_LSB_11N    0xCA0
 107 #define ODM_REG_ANTDIV_PARA1_11N                0xCA4
 108 #define ODM_REG_OFDM_FA_TYPE1_11N               0xCF0
 109 /* PAGE D */
 110 #define ODM_REG_OFDM_FA_RSTD_11N                0xD00
 111 #define ODM_REG_BB_ATC_11N                              0xD2C
 112 #define ODM_REG_OFDM_FA_TYPE2_11N               0xDA0
 113 #define ODM_REG_OFDM_FA_TYPE3_11N               0xDA4
 114 #define ODM_REG_OFDM_FA_TYPE4_11N               0xDA8
 115 #define ODM_REG_RPT_11N                                 0xDF4
 116 /* PAGE E */
 117 #define ODM_REG_TXAGC_A_6_18_11N                0xE00
 118 #define ODM_REG_TXAGC_A_24_54_11N               0xE04
 119 #define ODM_REG_TXAGC_A_1_MCS32_11N     0xE08
 120 #define ODM_REG_TXAGC_A_MCS0_3_11N              0xE10
 121 #define ODM_REG_TXAGC_A_MCS4_7_11N              0xE14
 122 #define ODM_REG_TXAGC_A_MCS8_11_11N     0xE18
 123 #define ODM_REG_TXAGC_A_MCS12_15_11N    0xE1C
 124 #define ODM_REG_FPGA0_IQK_11N                   0xE28
 125 #define ODM_REG_TXIQK_TONE_A_11N                0xE30
 126 #define ODM_REG_RXIQK_TONE_A_11N                0xE34
 127 #define ODM_REG_TXIQK_PI_A_11N                  0xE38
 128 #define ODM_REG_RXIQK_PI_A_11N                  0xE3C
 129 #define ODM_REG_TXIQK_11N                               0xE40
 130 #define ODM_REG_RXIQK_11N                               0xE44
 131 #define ODM_REG_IQK_AGC_PTS_11N                 0xE48
 132 #define ODM_REG_IQK_AGC_RSP_11N                 0xE4C
 133 #define ODM_REG_BLUETOOTH_11N                   0xE6C
 134 #define ODM_REG_RX_WAIT_CCA_11N                 0xE70
 135 #define ODM_REG_TX_CCK_RFON_11N                 0xE74
 136 #define ODM_REG_TX_CCK_BBON_11N                 0xE78
 137 #define ODM_REG_OFDM_RFON_11N                   0xE7C
 138 #define ODM_REG_OFDM_BBON_11N                   0xE80
 139 #define         ODM_REG_TX2RX_11N                               0xE84
 140 #define ODM_REG_TX2TX_11N                               0xE88
 141 #define ODM_REG_RX_CCK_11N                              0xE8C
 142 #define ODM_REG_RX_OFDM_11N                             0xED0
 143 #define ODM_REG_RX_WAIT_RIFS_11N                0xED4
 144 #define ODM_REG_RX2RX_11N                               0xED8
 145 #define ODM_REG_STANDBY_11N                             0xEDC
 146 #define ODM_REG_SLEEP_11N                               0xEE0
 147 #define ODM_REG_PMPD_ANAEN_11N                  0xEEC
 148 #define ODM_REG_IGI_C_11N                                       0xF84
 149 #define ODM_REG_IGI_D_11N                                       0xF88
 150
 151 /* 2 MAC REG LIST */
 152 #define ODM_REG_BB_RST_11N                              0x02
 153 #define ODM_REG_ANTSEL_PIN_11N                  0x4C
 154 #define ODM_REG_EARLY_MODE_11N                  0x4D0
 155 #define ODM_REG_RSSI_MONITOR_11N                0x4FE
 156 #define ODM_REG_EDCA_VO_11N                             0x500
 157 #define ODM_REG_EDCA_VI_11N                             0x504
 158 #define ODM_REG_EDCA_BE_11N                             0x508
 159 #define ODM_REG_EDCA_BK_11N                             0x50C
 160 #define ODM_REG_TXPAUSE_11N                             0x522
 161 #define ODM_REG_RESP_TX_11N                             0x6D8
 162 #define ODM_REG_ANT_TRAIN_PARA1_11N             0x7b0
 163 #define ODM_REG_ANT_TRAIN_PARA2_11N             0x7b4
 164
 165
 166 /* DIG Related */
 167 #define ODM_BIT_IGI_11N                                 0x0000007F
 168 #define ODM_BIT_CCK_RPT_FORMAT_11N              BIT9
 169 #define ODM_BIT_BB_RX_PATH_11N                  0xF
 170 #define ODM_BIT_BB_ATC_11N                              BIT11
 171
 172 #endif