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[mirror_ubuntu-bionic-kernel.git] / drivers / tty / serial / max310x.c
1 /*
2 * Maxim (Dallas) MAX3107/8/9, MAX14830 serial driver
3 *
4 * Copyright (C) 2012-2014 Alexander Shiyan <shc_work@mail.ru>
5 *
6 * Based on max3100.c, by Christian Pellegrin <chripell@evolware.org>
7 * Based on max3110.c, by Feng Tang <feng.tang@intel.com>
8 * Based on max3107.c, by Aavamobile
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16 #include <linux/bitops.h>
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/device.h>
20 #include <linux/gpio.h>
21 #include <linux/module.h>
22 #include <linux/of.h>
23 #include <linux/of_device.h>
24 #include <linux/regmap.h>
25 #include <linux/serial_core.h>
26 #include <linux/serial.h>
27 #include <linux/tty.h>
28 #include <linux/tty_flip.h>
29 #include <linux/spi/spi.h>
30
31 #define MAX310X_NAME "max310x"
32 #define MAX310X_MAJOR 204
33 #define MAX310X_MINOR 209
34
35 /* MAX310X register definitions */
36 #define MAX310X_RHR_REG (0x00) /* RX FIFO */
37 #define MAX310X_THR_REG (0x00) /* TX FIFO */
38 #define MAX310X_IRQEN_REG (0x01) /* IRQ enable */
39 #define MAX310X_IRQSTS_REG (0x02) /* IRQ status */
40 #define MAX310X_LSR_IRQEN_REG (0x03) /* LSR IRQ enable */
41 #define MAX310X_LSR_IRQSTS_REG (0x04) /* LSR IRQ status */
42 #define MAX310X_REG_05 (0x05)
43 #define MAX310X_SPCHR_IRQEN_REG MAX310X_REG_05 /* Special char IRQ en */
44 #define MAX310X_SPCHR_IRQSTS_REG (0x06) /* Special char IRQ status */
45 #define MAX310X_STS_IRQEN_REG (0x07) /* Status IRQ enable */
46 #define MAX310X_STS_IRQSTS_REG (0x08) /* Status IRQ status */
47 #define MAX310X_MODE1_REG (0x09) /* MODE1 */
48 #define MAX310X_MODE2_REG (0x0a) /* MODE2 */
49 #define MAX310X_LCR_REG (0x0b) /* LCR */
50 #define MAX310X_RXTO_REG (0x0c) /* RX timeout */
51 #define MAX310X_HDPIXDELAY_REG (0x0d) /* Auto transceiver delays */
52 #define MAX310X_IRDA_REG (0x0e) /* IRDA settings */
53 #define MAX310X_FLOWLVL_REG (0x0f) /* Flow control levels */
54 #define MAX310X_FIFOTRIGLVL_REG (0x10) /* FIFO IRQ trigger levels */
55 #define MAX310X_TXFIFOLVL_REG (0x11) /* TX FIFO level */
56 #define MAX310X_RXFIFOLVL_REG (0x12) /* RX FIFO level */
57 #define MAX310X_FLOWCTRL_REG (0x13) /* Flow control */
58 #define MAX310X_XON1_REG (0x14) /* XON1 character */
59 #define MAX310X_XON2_REG (0x15) /* XON2 character */
60 #define MAX310X_XOFF1_REG (0x16) /* XOFF1 character */
61 #define MAX310X_XOFF2_REG (0x17) /* XOFF2 character */
62 #define MAX310X_GPIOCFG_REG (0x18) /* GPIO config */
63 #define MAX310X_GPIODATA_REG (0x19) /* GPIO data */
64 #define MAX310X_PLLCFG_REG (0x1a) /* PLL config */
65 #define MAX310X_BRGCFG_REG (0x1b) /* Baud rate generator conf */
66 #define MAX310X_BRGDIVLSB_REG (0x1c) /* Baud rate divisor LSB */
67 #define MAX310X_BRGDIVMSB_REG (0x1d) /* Baud rate divisor MSB */
68 #define MAX310X_CLKSRC_REG (0x1e) /* Clock source */
69 #define MAX310X_REG_1F (0x1f)
70
71 #define MAX310X_REVID_REG MAX310X_REG_1F /* Revision ID */
72
73 #define MAX310X_GLOBALIRQ_REG MAX310X_REG_1F /* Global IRQ (RO) */
74 #define MAX310X_GLOBALCMD_REG MAX310X_REG_1F /* Global Command (WO) */
75
76 /* Extended registers */
77 #define MAX310X_REVID_EXTREG MAX310X_REG_05 /* Revision ID */
78
79 /* IRQ register bits */
80 #define MAX310X_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */
81 #define MAX310X_IRQ_SPCHR_BIT (1 << 1) /* Special char interrupt */
82 #define MAX310X_IRQ_STS_BIT (1 << 2) /* Status interrupt */
83 #define MAX310X_IRQ_RXFIFO_BIT (1 << 3) /* RX FIFO interrupt */
84 #define MAX310X_IRQ_TXFIFO_BIT (1 << 4) /* TX FIFO interrupt */
85 #define MAX310X_IRQ_TXEMPTY_BIT (1 << 5) /* TX FIFO empty interrupt */
86 #define MAX310X_IRQ_RXEMPTY_BIT (1 << 6) /* RX FIFO empty interrupt */
87 #define MAX310X_IRQ_CTS_BIT (1 << 7) /* CTS interrupt */
88
89 /* LSR register bits */
90 #define MAX310X_LSR_RXTO_BIT (1 << 0) /* RX timeout */
91 #define MAX310X_LSR_RXOVR_BIT (1 << 1) /* RX overrun */
92 #define MAX310X_LSR_RXPAR_BIT (1 << 2) /* RX parity error */
93 #define MAX310X_LSR_FRERR_BIT (1 << 3) /* Frame error */
94 #define MAX310X_LSR_RXBRK_BIT (1 << 4) /* RX break */
95 #define MAX310X_LSR_RXNOISE_BIT (1 << 5) /* RX noise */
96 #define MAX310X_LSR_CTS_BIT (1 << 7) /* CTS pin state */
97
98 /* Special character register bits */
99 #define MAX310X_SPCHR_XON1_BIT (1 << 0) /* XON1 character */
100 #define MAX310X_SPCHR_XON2_BIT (1 << 1) /* XON2 character */
101 #define MAX310X_SPCHR_XOFF1_BIT (1 << 2) /* XOFF1 character */
102 #define MAX310X_SPCHR_XOFF2_BIT (1 << 3) /* XOFF2 character */
103 #define MAX310X_SPCHR_BREAK_BIT (1 << 4) /* RX break */
104 #define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */
105
106 /* Status register bits */
107 #define MAX310X_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */
108 #define MAX310X_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */
109 #define MAX310X_STS_GPIO2_BIT (1 << 2) /* GPIO 2 interrupt */
110 #define MAX310X_STS_GPIO3_BIT (1 << 3) /* GPIO 3 interrupt */
111 #define MAX310X_STS_CLKREADY_BIT (1 << 5) /* Clock ready */
112 #define MAX310X_STS_SLEEP_BIT (1 << 6) /* Sleep interrupt */
113
114 /* MODE1 register bits */
115 #define MAX310X_MODE1_RXDIS_BIT (1 << 0) /* RX disable */
116 #define MAX310X_MODE1_TXDIS_BIT (1 << 1) /* TX disable */
117 #define MAX310X_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */
118 #define MAX310X_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */
119 #define MAX310X_MODE1_TRNSCVCTRL_BIT (1 << 4) /* Transceiver ctrl enable */
120 #define MAX310X_MODE1_FORCESLEEP_BIT (1 << 5) /* Force sleep mode */
121 #define MAX310X_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */
122 #define MAX310X_MODE1_IRQSEL_BIT (1 << 7) /* IRQ pin enable */
123
124 /* MODE2 register bits */
125 #define MAX310X_MODE2_RST_BIT (1 << 0) /* Chip reset */
126 #define MAX310X_MODE2_FIFORST_BIT (1 << 1) /* FIFO reset */
127 #define MAX310X_MODE2_RXTRIGINV_BIT (1 << 2) /* RX FIFO INT invert */
128 #define MAX310X_MODE2_RXEMPTINV_BIT (1 << 3) /* RX FIFO empty INT invert */
129 #define MAX310X_MODE2_SPCHR_BIT (1 << 4) /* Special chr detect enable */
130 #define MAX310X_MODE2_LOOPBACK_BIT (1 << 5) /* Internal loopback enable */
131 #define MAX310X_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */
132 #define MAX310X_MODE2_ECHOSUPR_BIT (1 << 7) /* ECHO suppression enable */
133
134 /* LCR register bits */
135 #define MAX310X_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */
136 #define MAX310X_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1
137 *
138 * Word length bits table:
139 * 00 -> 5 bit words
140 * 01 -> 6 bit words
141 * 10 -> 7 bit words
142 * 11 -> 8 bit words
143 */
144 #define MAX310X_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit
145 *
146 * STOP length bit table:
147 * 0 -> 1 stop bit
148 * 1 -> 1-1.5 stop bits if
149 * word length is 5,
150 * 2 stop bits otherwise
151 */
152 #define MAX310X_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */
153 #define MAX310X_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */
154 #define MAX310X_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */
155 #define MAX310X_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */
156 #define MAX310X_LCR_RTS_BIT (1 << 7) /* RTS pin control */
157 #define MAX310X_LCR_WORD_LEN_5 (0x00)
158 #define MAX310X_LCR_WORD_LEN_6 (0x01)
159 #define MAX310X_LCR_WORD_LEN_7 (0x02)
160 #define MAX310X_LCR_WORD_LEN_8 (0x03)
161
162 /* IRDA register bits */
163 #define MAX310X_IRDA_IRDAEN_BIT (1 << 0) /* IRDA mode enable */
164 #define MAX310X_IRDA_SIR_BIT (1 << 1) /* SIR mode enable */
165
166 /* Flow control trigger level register masks */
167 #define MAX310X_FLOWLVL_HALT_MASK (0x000f) /* Flow control halt level */
168 #define MAX310X_FLOWLVL_RES_MASK (0x00f0) /* Flow control resume level */
169 #define MAX310X_FLOWLVL_HALT(words) ((words / 8) & 0x0f)
170 #define MAX310X_FLOWLVL_RES(words) (((words / 8) & 0x0f) << 4)
171
172 /* FIFO interrupt trigger level register masks */
173 #define MAX310X_FIFOTRIGLVL_TX_MASK (0x0f) /* TX FIFO trigger level */
174 #define MAX310X_FIFOTRIGLVL_RX_MASK (0xf0) /* RX FIFO trigger level */
175 #define MAX310X_FIFOTRIGLVL_TX(words) ((words / 8) & 0x0f)
176 #define MAX310X_FIFOTRIGLVL_RX(words) (((words / 8) & 0x0f) << 4)
177
178 /* Flow control register bits */
179 #define MAX310X_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */
180 #define MAX310X_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */
181 #define MAX310X_FLOWCTRL_GPIADDR_BIT (1 << 2) /* Enables that GPIO inputs
182 * are used in conjunction with
183 * XOFF2 for definition of
184 * special character */
185 #define MAX310X_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */
186 #define MAX310X_FLOWCTRL_SWFLOW0_BIT (1 << 4) /* SWFLOW bit 0 */
187 #define MAX310X_FLOWCTRL_SWFLOW1_BIT (1 << 5) /* SWFLOW bit 1
188 *
189 * SWFLOW bits 1 & 0 table:
190 * 00 -> no transmitter flow
191 * control
192 * 01 -> receiver compares
193 * XON2 and XOFF2
194 * and controls
195 * transmitter
196 * 10 -> receiver compares
197 * XON1 and XOFF1
198 * and controls
199 * transmitter
200 * 11 -> receiver compares
201 * XON1, XON2, XOFF1 and
202 * XOFF2 and controls
203 * transmitter
204 */
205 #define MAX310X_FLOWCTRL_SWFLOW2_BIT (1 << 6) /* SWFLOW bit 2 */
206 #define MAX310X_FLOWCTRL_SWFLOW3_BIT (1 << 7) /* SWFLOW bit 3
207 *
208 * SWFLOW bits 3 & 2 table:
209 * 00 -> no received flow
210 * control
211 * 01 -> transmitter generates
212 * XON2 and XOFF2
213 * 10 -> transmitter generates
214 * XON1 and XOFF1
215 * 11 -> transmitter generates
216 * XON1, XON2, XOFF1 and
217 * XOFF2
218 */
219
220 /* PLL configuration register masks */
221 #define MAX310X_PLLCFG_PREDIV_MASK (0x3f) /* PLL predivision value */
222 #define MAX310X_PLLCFG_PLLFACTOR_MASK (0xc0) /* PLL multiplication factor */
223
224 /* Baud rate generator configuration register bits */
225 #define MAX310X_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */
226 #define MAX310X_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */
227
228 /* Clock source register bits */
229 #define MAX310X_CLKSRC_CRYST_BIT (1 << 1) /* Crystal osc enable */
230 #define MAX310X_CLKSRC_PLL_BIT (1 << 2) /* PLL enable */
231 #define MAX310X_CLKSRC_PLLBYP_BIT (1 << 3) /* PLL bypass */
232 #define MAX310X_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */
233 #define MAX310X_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */
234
235 /* Global commands */
236 #define MAX310X_EXTREG_ENBL (0xce)
237 #define MAX310X_EXTREG_DSBL (0xcd)
238
239 /* Misc definitions */
240 #define MAX310X_FIFO_SIZE (128)
241 #define MAX310x_REV_MASK (0xfc)
242
243 /* MAX3107 specific */
244 #define MAX3107_REV_ID (0xa0)
245
246 /* MAX3109 specific */
247 #define MAX3109_REV_ID (0xc0)
248
249 /* MAX14830 specific */
250 #define MAX14830_BRGCFG_CLKDIS_BIT (1 << 6) /* Clock Disable */
251 #define MAX14830_REV_ID (0xb0)
252
253 struct max310x_devtype {
254 char name[9];
255 int nr;
256 int (*detect)(struct device *);
257 void (*power)(struct uart_port *, int);
258 };
259
260 struct max310x_one {
261 struct uart_port port;
262 struct work_struct tx_work;
263 struct work_struct md_work;
264 };
265
266 struct max310x_port {
267 struct uart_driver uart;
268 struct max310x_devtype *devtype;
269 struct regmap *regmap;
270 struct mutex mutex;
271 struct clk *clk;
272 #ifdef CONFIG_GPIOLIB
273 struct gpio_chip gpio;
274 #endif
275 struct max310x_one p[0];
276 };
277
278 static u8 max310x_port_read(struct uart_port *port, u8 reg)
279 {
280 struct max310x_port *s = dev_get_drvdata(port->dev);
281 unsigned int val = 0;
282
283 regmap_read(s->regmap, port->iobase + reg, &val);
284
285 return val;
286 }
287
288 static void max310x_port_write(struct uart_port *port, u8 reg, u8 val)
289 {
290 struct max310x_port *s = dev_get_drvdata(port->dev);
291
292 regmap_write(s->regmap, port->iobase + reg, val);
293 }
294
295 static void max310x_port_update(struct uart_port *port, u8 reg, u8 mask, u8 val)
296 {
297 struct max310x_port *s = dev_get_drvdata(port->dev);
298
299 regmap_update_bits(s->regmap, port->iobase + reg, mask, val);
300 }
301
302 static int max3107_detect(struct device *dev)
303 {
304 struct max310x_port *s = dev_get_drvdata(dev);
305 unsigned int val = 0;
306 int ret;
307
308 ret = regmap_read(s->regmap, MAX310X_REVID_REG, &val);
309 if (ret)
310 return ret;
311
312 if (((val & MAX310x_REV_MASK) != MAX3107_REV_ID)) {
313 dev_err(dev,
314 "%s ID 0x%02x does not match\n", s->devtype->name, val);
315 return -ENODEV;
316 }
317
318 return 0;
319 }
320
321 static int max3108_detect(struct device *dev)
322 {
323 struct max310x_port *s = dev_get_drvdata(dev);
324 unsigned int val = 0;
325 int ret;
326
327 /* MAX3108 have not REV ID register, we just check default value
328 * from clocksource register to make sure everything works.
329 */
330 ret = regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val);
331 if (ret)
332 return ret;
333
334 if (val != (MAX310X_CLKSRC_EXTCLK_BIT | MAX310X_CLKSRC_PLLBYP_BIT)) {
335 dev_err(dev, "%s not present\n", s->devtype->name);
336 return -ENODEV;
337 }
338
339 return 0;
340 }
341
342 static int max3109_detect(struct device *dev)
343 {
344 struct max310x_port *s = dev_get_drvdata(dev);
345 unsigned int val = 0;
346 int ret;
347
348 ret = regmap_read(s->regmap, MAX310X_REVID_REG, &val);
349 if (ret)
350 return ret;
351
352 if (((val & MAX310x_REV_MASK) != MAX3109_REV_ID)) {
353 dev_err(dev,
354 "%s ID 0x%02x does not match\n", s->devtype->name, val);
355 return -ENODEV;
356 }
357
358 return 0;
359 }
360
361 static void max310x_power(struct uart_port *port, int on)
362 {
363 max310x_port_update(port, MAX310X_MODE1_REG,
364 MAX310X_MODE1_FORCESLEEP_BIT,
365 on ? 0 : MAX310X_MODE1_FORCESLEEP_BIT);
366 if (on)
367 msleep(50);
368 }
369
370 static int max14830_detect(struct device *dev)
371 {
372 struct max310x_port *s = dev_get_drvdata(dev);
373 unsigned int val = 0;
374 int ret;
375
376 ret = regmap_write(s->regmap, MAX310X_GLOBALCMD_REG,
377 MAX310X_EXTREG_ENBL);
378 if (ret)
379 return ret;
380
381 regmap_read(s->regmap, MAX310X_REVID_EXTREG, &val);
382 regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, MAX310X_EXTREG_DSBL);
383 if (((val & MAX310x_REV_MASK) != MAX14830_REV_ID)) {
384 dev_err(dev,
385 "%s ID 0x%02x does not match\n", s->devtype->name, val);
386 return -ENODEV;
387 }
388
389 return 0;
390 }
391
392 static void max14830_power(struct uart_port *port, int on)
393 {
394 max310x_port_update(port, MAX310X_BRGCFG_REG,
395 MAX14830_BRGCFG_CLKDIS_BIT,
396 on ? 0 : MAX14830_BRGCFG_CLKDIS_BIT);
397 if (on)
398 msleep(50);
399 }
400
401 static const struct max310x_devtype max3107_devtype = {
402 .name = "MAX3107",
403 .nr = 1,
404 .detect = max3107_detect,
405 .power = max310x_power,
406 };
407
408 static const struct max310x_devtype max3108_devtype = {
409 .name = "MAX3108",
410 .nr = 1,
411 .detect = max3108_detect,
412 .power = max310x_power,
413 };
414
415 static const struct max310x_devtype max3109_devtype = {
416 .name = "MAX3109",
417 .nr = 2,
418 .detect = max3109_detect,
419 .power = max310x_power,
420 };
421
422 static const struct max310x_devtype max14830_devtype = {
423 .name = "MAX14830",
424 .nr = 4,
425 .detect = max14830_detect,
426 .power = max14830_power,
427 };
428
429 static bool max310x_reg_writeable(struct device *dev, unsigned int reg)
430 {
431 switch (reg & 0x1f) {
432 case MAX310X_IRQSTS_REG:
433 case MAX310X_LSR_IRQSTS_REG:
434 case MAX310X_SPCHR_IRQSTS_REG:
435 case MAX310X_STS_IRQSTS_REG:
436 case MAX310X_TXFIFOLVL_REG:
437 case MAX310X_RXFIFOLVL_REG:
438 return false;
439 default:
440 break;
441 }
442
443 return true;
444 }
445
446 static bool max310x_reg_volatile(struct device *dev, unsigned int reg)
447 {
448 switch (reg & 0x1f) {
449 case MAX310X_RHR_REG:
450 case MAX310X_IRQSTS_REG:
451 case MAX310X_LSR_IRQSTS_REG:
452 case MAX310X_SPCHR_IRQSTS_REG:
453 case MAX310X_STS_IRQSTS_REG:
454 case MAX310X_TXFIFOLVL_REG:
455 case MAX310X_RXFIFOLVL_REG:
456 case MAX310X_GPIODATA_REG:
457 case MAX310X_BRGDIVLSB_REG:
458 case MAX310X_REG_05:
459 case MAX310X_REG_1F:
460 return true;
461 default:
462 break;
463 }
464
465 return false;
466 }
467
468 static bool max310x_reg_precious(struct device *dev, unsigned int reg)
469 {
470 switch (reg & 0x1f) {
471 case MAX310X_RHR_REG:
472 case MAX310X_IRQSTS_REG:
473 case MAX310X_SPCHR_IRQSTS_REG:
474 case MAX310X_STS_IRQSTS_REG:
475 return true;
476 default:
477 break;
478 }
479
480 return false;
481 }
482
483 static int max310x_set_baud(struct uart_port *port, int baud)
484 {
485 unsigned int mode = 0, clk = port->uartclk, div = clk / baud;
486
487 /* Check for minimal value for divider */
488 if (div < 16)
489 div = 16;
490
491 if (clk % baud && (div / 16) < 0x8000) {
492 /* Mode x2 */
493 mode = MAX310X_BRGCFG_2XMODE_BIT;
494 clk = port->uartclk * 2;
495 div = clk / baud;
496
497 if (clk % baud && (div / 16) < 0x8000) {
498 /* Mode x4 */
499 mode = MAX310X_BRGCFG_4XMODE_BIT;
500 clk = port->uartclk * 4;
501 div = clk / baud;
502 }
503 }
504
505 max310x_port_write(port, MAX310X_BRGDIVMSB_REG, (div / 16) >> 8);
506 max310x_port_write(port, MAX310X_BRGDIVLSB_REG, div / 16);
507 max310x_port_write(port, MAX310X_BRGCFG_REG, (div % 16) | mode);
508
509 return DIV_ROUND_CLOSEST(clk, div);
510 }
511
512 static int max310x_update_best_err(unsigned long f, long *besterr)
513 {
514 /* Use baudrate 115200 for calculate error */
515 long err = f % (115200 * 16);
516
517 if ((*besterr < 0) || (*besterr > err)) {
518 *besterr = err;
519 return 0;
520 }
521
522 return 1;
523 }
524
525 static int max310x_set_ref_clk(struct max310x_port *s, unsigned long freq,
526 bool xtal)
527 {
528 unsigned int div, clksrc, pllcfg = 0;
529 long besterr = -1;
530 unsigned long fdiv, fmul, bestfreq = freq;
531
532 /* First, update error without PLL */
533 max310x_update_best_err(freq, &besterr);
534
535 /* Try all possible PLL dividers */
536 for (div = 1; (div <= 63) && besterr; div++) {
537 fdiv = DIV_ROUND_CLOSEST(freq, div);
538
539 /* Try multiplier 6 */
540 fmul = fdiv * 6;
541 if ((fdiv >= 500000) && (fdiv <= 800000))
542 if (!max310x_update_best_err(fmul, &besterr)) {
543 pllcfg = (0 << 6) | div;
544 bestfreq = fmul;
545 }
546 /* Try multiplier 48 */
547 fmul = fdiv * 48;
548 if ((fdiv >= 850000) && (fdiv <= 1200000))
549 if (!max310x_update_best_err(fmul, &besterr)) {
550 pllcfg = (1 << 6) | div;
551 bestfreq = fmul;
552 }
553 /* Try multiplier 96 */
554 fmul = fdiv * 96;
555 if ((fdiv >= 425000) && (fdiv <= 1000000))
556 if (!max310x_update_best_err(fmul, &besterr)) {
557 pllcfg = (2 << 6) | div;
558 bestfreq = fmul;
559 }
560 /* Try multiplier 144 */
561 fmul = fdiv * 144;
562 if ((fdiv >= 390000) && (fdiv <= 667000))
563 if (!max310x_update_best_err(fmul, &besterr)) {
564 pllcfg = (3 << 6) | div;
565 bestfreq = fmul;
566 }
567 }
568
569 /* Configure clock source */
570 clksrc = xtal ? MAX310X_CLKSRC_CRYST_BIT : MAX310X_CLKSRC_EXTCLK_BIT;
571
572 /* Configure PLL */
573 if (pllcfg) {
574 clksrc |= MAX310X_CLKSRC_PLL_BIT;
575 regmap_write(s->regmap, MAX310X_PLLCFG_REG, pllcfg);
576 } else
577 clksrc |= MAX310X_CLKSRC_PLLBYP_BIT;
578
579 regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc);
580
581 /* Wait for crystal */
582 if (pllcfg && xtal)
583 msleep(10);
584
585 return (int)bestfreq;
586 }
587
588 static void max310x_handle_rx(struct uart_port *port, unsigned int rxlen)
589 {
590 unsigned int sts, ch, flag;
591
592 if (unlikely(rxlen >= port->fifosize)) {
593 dev_warn_ratelimited(port->dev,
594 "Port %i: Possible RX FIFO overrun\n",
595 port->line);
596 port->icount.buf_overrun++;
597 /* Ensure sanity of RX level */
598 rxlen = port->fifosize;
599 }
600
601 while (rxlen--) {
602 ch = max310x_port_read(port, MAX310X_RHR_REG);
603 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
604
605 sts &= MAX310X_LSR_RXPAR_BIT | MAX310X_LSR_FRERR_BIT |
606 MAX310X_LSR_RXOVR_BIT | MAX310X_LSR_RXBRK_BIT;
607
608 port->icount.rx++;
609 flag = TTY_NORMAL;
610
611 if (unlikely(sts)) {
612 if (sts & MAX310X_LSR_RXBRK_BIT) {
613 port->icount.brk++;
614 if (uart_handle_break(port))
615 continue;
616 } else if (sts & MAX310X_LSR_RXPAR_BIT)
617 port->icount.parity++;
618 else if (sts & MAX310X_LSR_FRERR_BIT)
619 port->icount.frame++;
620 else if (sts & MAX310X_LSR_RXOVR_BIT)
621 port->icount.overrun++;
622
623 sts &= port->read_status_mask;
624 if (sts & MAX310X_LSR_RXBRK_BIT)
625 flag = TTY_BREAK;
626 else if (sts & MAX310X_LSR_RXPAR_BIT)
627 flag = TTY_PARITY;
628 else if (sts & MAX310X_LSR_FRERR_BIT)
629 flag = TTY_FRAME;
630 else if (sts & MAX310X_LSR_RXOVR_BIT)
631 flag = TTY_OVERRUN;
632 }
633
634 if (uart_handle_sysrq_char(port, ch))
635 continue;
636
637 if (sts & port->ignore_status_mask)
638 continue;
639
640 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, ch, flag);
641 }
642
643 tty_flip_buffer_push(&port->state->port);
644 }
645
646 static void max310x_handle_tx(struct uart_port *port)
647 {
648 struct circ_buf *xmit = &port->state->xmit;
649 unsigned int txlen, to_send;
650
651 if (unlikely(port->x_char)) {
652 max310x_port_write(port, MAX310X_THR_REG, port->x_char);
653 port->icount.tx++;
654 port->x_char = 0;
655 return;
656 }
657
658 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
659 return;
660
661 /* Get length of data pending in circular buffer */
662 to_send = uart_circ_chars_pending(xmit);
663 if (likely(to_send)) {
664 /* Limit to size of TX FIFO */
665 txlen = max310x_port_read(port, MAX310X_TXFIFOLVL_REG);
666 txlen = port->fifosize - txlen;
667 to_send = (to_send > txlen) ? txlen : to_send;
668
669 /* Add data to send */
670 port->icount.tx += to_send;
671 while (to_send--) {
672 max310x_port_write(port, MAX310X_THR_REG,
673 xmit->buf[xmit->tail]);
674 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
675 }
676 }
677
678 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
679 uart_write_wakeup(port);
680 }
681
682 static void max310x_port_irq(struct max310x_port *s, int portno)
683 {
684 struct uart_port *port = &s->p[portno].port;
685
686 do {
687 unsigned int ists, lsr, rxlen;
688
689 /* Read IRQ status & RX FIFO level */
690 ists = max310x_port_read(port, MAX310X_IRQSTS_REG);
691 rxlen = max310x_port_read(port, MAX310X_RXFIFOLVL_REG);
692 if (!ists && !rxlen)
693 break;
694
695 if (ists & MAX310X_IRQ_CTS_BIT) {
696 lsr = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
697 uart_handle_cts_change(port,
698 !!(lsr & MAX310X_LSR_CTS_BIT));
699 }
700 if (rxlen)
701 max310x_handle_rx(port, rxlen);
702 if (ists & MAX310X_IRQ_TXEMPTY_BIT) {
703 mutex_lock(&s->mutex);
704 max310x_handle_tx(port);
705 mutex_unlock(&s->mutex);
706 }
707 } while (1);
708 }
709
710 static irqreturn_t max310x_ist(int irq, void *dev_id)
711 {
712 struct max310x_port *s = (struct max310x_port *)dev_id;
713
714 if (s->uart.nr > 1) {
715 do {
716 unsigned int val = ~0;
717
718 WARN_ON_ONCE(regmap_read(s->regmap,
719 MAX310X_GLOBALIRQ_REG, &val));
720 val = ((1 << s->uart.nr) - 1) & ~val;
721 if (!val)
722 break;
723 max310x_port_irq(s, fls(val) - 1);
724 } while (1);
725 } else
726 max310x_port_irq(s, 0);
727
728 return IRQ_HANDLED;
729 }
730
731 static void max310x_wq_proc(struct work_struct *ws)
732 {
733 struct max310x_one *one = container_of(ws, struct max310x_one, tx_work);
734 struct max310x_port *s = dev_get_drvdata(one->port.dev);
735
736 mutex_lock(&s->mutex);
737 max310x_handle_tx(&one->port);
738 mutex_unlock(&s->mutex);
739 }
740
741 static void max310x_start_tx(struct uart_port *port)
742 {
743 struct max310x_one *one = container_of(port, struct max310x_one, port);
744
745 if (!work_pending(&one->tx_work))
746 schedule_work(&one->tx_work);
747 }
748
749 static unsigned int max310x_tx_empty(struct uart_port *port)
750 {
751 unsigned int lvl, sts;
752
753 lvl = max310x_port_read(port, MAX310X_TXFIFOLVL_REG);
754 sts = max310x_port_read(port, MAX310X_IRQSTS_REG);
755
756 return ((sts & MAX310X_IRQ_TXEMPTY_BIT) && !lvl) ? TIOCSER_TEMT : 0;
757 }
758
759 static unsigned int max310x_get_mctrl(struct uart_port *port)
760 {
761 /* DCD and DSR are not wired and CTS/RTS is handled automatically
762 * so just indicate DSR and CAR asserted
763 */
764 return TIOCM_DSR | TIOCM_CAR;
765 }
766
767 static void max310x_md_proc(struct work_struct *ws)
768 {
769 struct max310x_one *one = container_of(ws, struct max310x_one, md_work);
770
771 max310x_port_update(&one->port, MAX310X_MODE2_REG,
772 MAX310X_MODE2_LOOPBACK_BIT,
773 (one->port.mctrl & TIOCM_LOOP) ?
774 MAX310X_MODE2_LOOPBACK_BIT : 0);
775 }
776
777 static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl)
778 {
779 struct max310x_one *one = container_of(port, struct max310x_one, port);
780
781 schedule_work(&one->md_work);
782 }
783
784 static void max310x_break_ctl(struct uart_port *port, int break_state)
785 {
786 max310x_port_update(port, MAX310X_LCR_REG,
787 MAX310X_LCR_TXBREAK_BIT,
788 break_state ? MAX310X_LCR_TXBREAK_BIT : 0);
789 }
790
791 static void max310x_set_termios(struct uart_port *port,
792 struct ktermios *termios,
793 struct ktermios *old)
794 {
795 unsigned int lcr, flow = 0;
796 int baud;
797
798 /* Mask termios capabilities we don't support */
799 termios->c_cflag &= ~CMSPAR;
800
801 /* Word size */
802 switch (termios->c_cflag & CSIZE) {
803 case CS5:
804 lcr = MAX310X_LCR_WORD_LEN_5;
805 break;
806 case CS6:
807 lcr = MAX310X_LCR_WORD_LEN_6;
808 break;
809 case CS7:
810 lcr = MAX310X_LCR_WORD_LEN_7;
811 break;
812 case CS8:
813 default:
814 lcr = MAX310X_LCR_WORD_LEN_8;
815 break;
816 }
817
818 /* Parity */
819 if (termios->c_cflag & PARENB) {
820 lcr |= MAX310X_LCR_PARITY_BIT;
821 if (!(termios->c_cflag & PARODD))
822 lcr |= MAX310X_LCR_EVENPARITY_BIT;
823 }
824
825 /* Stop bits */
826 if (termios->c_cflag & CSTOPB)
827 lcr |= MAX310X_LCR_STOPLEN_BIT; /* 2 stops */
828
829 /* Update LCR register */
830 max310x_port_write(port, MAX310X_LCR_REG, lcr);
831
832 /* Set read status mask */
833 port->read_status_mask = MAX310X_LSR_RXOVR_BIT;
834 if (termios->c_iflag & INPCK)
835 port->read_status_mask |= MAX310X_LSR_RXPAR_BIT |
836 MAX310X_LSR_FRERR_BIT;
837 if (termios->c_iflag & (BRKINT | PARMRK))
838 port->read_status_mask |= MAX310X_LSR_RXBRK_BIT;
839
840 /* Set status ignore mask */
841 port->ignore_status_mask = 0;
842 if (termios->c_iflag & IGNBRK)
843 port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT;
844 if (!(termios->c_cflag & CREAD))
845 port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT |
846 MAX310X_LSR_RXOVR_BIT |
847 MAX310X_LSR_FRERR_BIT |
848 MAX310X_LSR_RXBRK_BIT;
849
850 /* Configure flow control */
851 max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]);
852 max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]);
853 if (termios->c_cflag & CRTSCTS)
854 flow |= MAX310X_FLOWCTRL_AUTOCTS_BIT |
855 MAX310X_FLOWCTRL_AUTORTS_BIT;
856 if (termios->c_iflag & IXON)
857 flow |= MAX310X_FLOWCTRL_SWFLOW3_BIT |
858 MAX310X_FLOWCTRL_SWFLOWEN_BIT;
859 if (termios->c_iflag & IXOFF)
860 flow |= MAX310X_FLOWCTRL_SWFLOW1_BIT |
861 MAX310X_FLOWCTRL_SWFLOWEN_BIT;
862 max310x_port_write(port, MAX310X_FLOWCTRL_REG, flow);
863
864 /* Get baud rate generator configuration */
865 baud = uart_get_baud_rate(port, termios, old,
866 port->uartclk / 16 / 0xffff,
867 port->uartclk / 4);
868
869 /* Setup baudrate generator */
870 baud = max310x_set_baud(port, baud);
871
872 /* Update timeout according to new baud rate */
873 uart_update_timeout(port, termios->c_cflag, baud);
874 }
875
876 static int max310x_ioctl(struct uart_port *port, unsigned int cmd,
877 unsigned long arg)
878 {
879 struct serial_rs485 rs485;
880 unsigned int val;
881
882 switch (cmd) {
883 case TIOCSRS485:
884 if (copy_from_user(&rs485, (struct serial_rs485 *)arg,
885 sizeof(rs485)))
886 return -EFAULT;
887 if (rs485.delay_rts_before_send > 0x0f ||
888 rs485.delay_rts_after_send > 0x0f)
889 return -ERANGE;
890 val = (rs485.delay_rts_before_send << 4) |
891 rs485.delay_rts_after_send;
892 max310x_port_write(port, MAX310X_HDPIXDELAY_REG, val);
893 if (rs485.flags & SER_RS485_ENABLED) {
894 max310x_port_update(port, MAX310X_MODE1_REG,
895 MAX310X_MODE1_TRNSCVCTRL_BIT,
896 MAX310X_MODE1_TRNSCVCTRL_BIT);
897 max310x_port_update(port, MAX310X_MODE2_REG,
898 MAX310X_MODE2_ECHOSUPR_BIT,
899 MAX310X_MODE2_ECHOSUPR_BIT);
900 } else {
901 max310x_port_update(port, MAX310X_MODE1_REG,
902 MAX310X_MODE1_TRNSCVCTRL_BIT, 0);
903 max310x_port_update(port, MAX310X_MODE2_REG,
904 MAX310X_MODE2_ECHOSUPR_BIT, 0);
905 }
906 break;
907 case TIOCGRS485:
908 memset(&rs485, 0, sizeof(rs485));
909 val = max310x_port_read(port, MAX310X_MODE1_REG);
910 rs485.flags = (val & MAX310X_MODE1_TRNSCVCTRL_BIT) ?
911 SER_RS485_ENABLED : 0;
912 rs485.flags |= SER_RS485_RTS_ON_SEND;
913 val = max310x_port_read(port, MAX310X_HDPIXDELAY_REG);
914 rs485.delay_rts_before_send = val >> 4;
915 rs485.delay_rts_after_send = val & 0x0f;
916 if (copy_to_user((struct serial_rs485 *)arg, &rs485,
917 sizeof(rs485)))
918 return -EFAULT;
919 break;
920 default:
921 return -ENOIOCTLCMD;
922 }
923
924 return 0;
925 }
926
927 static int max310x_startup(struct uart_port *port)
928 {
929 struct max310x_port *s = dev_get_drvdata(port->dev);
930 unsigned int val;
931
932 s->devtype->power(port, 1);
933
934 /* Configure MODE1 register */
935 max310x_port_update(port, MAX310X_MODE1_REG,
936 MAX310X_MODE1_TRNSCVCTRL_BIT, 0);
937
938 /* Configure MODE2 register & Reset FIFOs*/
939 val = MAX310X_MODE2_RXEMPTINV_BIT | MAX310X_MODE2_FIFORST_BIT;
940 max310x_port_write(port, MAX310X_MODE2_REG, val);
941 max310x_port_update(port, MAX310X_MODE2_REG,
942 MAX310X_MODE2_FIFORST_BIT, 0);
943
944 /* Configure flow control levels */
945 /* Flow control halt level 96, resume level 48 */
946 max310x_port_write(port, MAX310X_FLOWLVL_REG,
947 MAX310X_FLOWLVL_RES(48) | MAX310X_FLOWLVL_HALT(96));
948
949 /* Clear IRQ status register */
950 max310x_port_read(port, MAX310X_IRQSTS_REG);
951
952 /* Enable RX, TX, CTS change interrupts */
953 val = MAX310X_IRQ_RXEMPTY_BIT | MAX310X_IRQ_TXEMPTY_BIT;
954 max310x_port_write(port, MAX310X_IRQEN_REG, val | MAX310X_IRQ_CTS_BIT);
955
956 return 0;
957 }
958
959 static void max310x_shutdown(struct uart_port *port)
960 {
961 struct max310x_port *s = dev_get_drvdata(port->dev);
962
963 /* Disable all interrupts */
964 max310x_port_write(port, MAX310X_IRQEN_REG, 0);
965
966 s->devtype->power(port, 0);
967 }
968
969 static const char *max310x_type(struct uart_port *port)
970 {
971 struct max310x_port *s = dev_get_drvdata(port->dev);
972
973 return (port->type == PORT_MAX310X) ? s->devtype->name : NULL;
974 }
975
976 static int max310x_request_port(struct uart_port *port)
977 {
978 /* Do nothing */
979 return 0;
980 }
981
982 static void max310x_config_port(struct uart_port *port, int flags)
983 {
984 if (flags & UART_CONFIG_TYPE)
985 port->type = PORT_MAX310X;
986 }
987
988 static int max310x_verify_port(struct uart_port *port, struct serial_struct *s)
989 {
990 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_MAX310X))
991 return -EINVAL;
992 if (s->irq != port->irq)
993 return -EINVAL;
994
995 return 0;
996 }
997
998 static void max310x_null_void(struct uart_port *port)
999 {
1000 /* Do nothing */
1001 }
1002
1003 static const struct uart_ops max310x_ops = {
1004 .tx_empty = max310x_tx_empty,
1005 .set_mctrl = max310x_set_mctrl,
1006 .get_mctrl = max310x_get_mctrl,
1007 .stop_tx = max310x_null_void,
1008 .start_tx = max310x_start_tx,
1009 .stop_rx = max310x_null_void,
1010 .enable_ms = max310x_null_void,
1011 .break_ctl = max310x_break_ctl,
1012 .startup = max310x_startup,
1013 .shutdown = max310x_shutdown,
1014 .set_termios = max310x_set_termios,
1015 .type = max310x_type,
1016 .request_port = max310x_request_port,
1017 .release_port = max310x_null_void,
1018 .config_port = max310x_config_port,
1019 .verify_port = max310x_verify_port,
1020 .ioctl = max310x_ioctl,
1021 };
1022
1023 static int __maybe_unused max310x_suspend(struct device *dev)
1024 {
1025 struct max310x_port *s = dev_get_drvdata(dev);
1026 int i;
1027
1028 for (i = 0; i < s->uart.nr; i++) {
1029 uart_suspend_port(&s->uart, &s->p[i].port);
1030 s->devtype->power(&s->p[i].port, 0);
1031 }
1032
1033 return 0;
1034 }
1035
1036 static int __maybe_unused max310x_resume(struct device *dev)
1037 {
1038 struct max310x_port *s = dev_get_drvdata(dev);
1039 int i;
1040
1041 for (i = 0; i < s->uart.nr; i++) {
1042 s->devtype->power(&s->p[i].port, 1);
1043 uart_resume_port(&s->uart, &s->p[i].port);
1044 }
1045
1046 return 0;
1047 }
1048
1049 static SIMPLE_DEV_PM_OPS(max310x_pm_ops, max310x_suspend, max310x_resume);
1050
1051 #ifdef CONFIG_GPIOLIB
1052 static int max310x_gpio_get(struct gpio_chip *chip, unsigned offset)
1053 {
1054 unsigned int val;
1055 struct max310x_port *s = container_of(chip, struct max310x_port, gpio);
1056 struct uart_port *port = &s->p[offset / 4].port;
1057
1058 val = max310x_port_read(port, MAX310X_GPIODATA_REG);
1059
1060 return !!((val >> 4) & (1 << (offset % 4)));
1061 }
1062
1063 static void max310x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1064 {
1065 struct max310x_port *s = container_of(chip, struct max310x_port, gpio);
1066 struct uart_port *port = &s->p[offset / 4].port;
1067
1068 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4),
1069 value ? 1 << (offset % 4) : 0);
1070 }
1071
1072 static int max310x_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1073 {
1074 struct max310x_port *s = container_of(chip, struct max310x_port, gpio);
1075 struct uart_port *port = &s->p[offset / 4].port;
1076
1077 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 0);
1078
1079 return 0;
1080 }
1081
1082 static int max310x_gpio_direction_output(struct gpio_chip *chip,
1083 unsigned offset, int value)
1084 {
1085 struct max310x_port *s = container_of(chip, struct max310x_port, gpio);
1086 struct uart_port *port = &s->p[offset / 4].port;
1087
1088 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4),
1089 value ? 1 << (offset % 4) : 0);
1090 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4),
1091 1 << (offset % 4));
1092
1093 return 0;
1094 }
1095 #endif
1096
1097 static int max310x_probe(struct device *dev, struct max310x_devtype *devtype,
1098 struct regmap *regmap, int irq, unsigned long flags)
1099 {
1100 int i, ret, fmin, fmax, freq, uartclk;
1101 struct clk *clk_osc, *clk_xtal;
1102 struct max310x_port *s;
1103 bool xtal = false;
1104
1105 if (IS_ERR(regmap))
1106 return PTR_ERR(regmap);
1107
1108 /* Alloc port structure */
1109 s = devm_kzalloc(dev, sizeof(*s) +
1110 sizeof(struct max310x_one) * devtype->nr, GFP_KERNEL);
1111 if (!s) {
1112 dev_err(dev, "Error allocating port structure\n");
1113 return -ENOMEM;
1114 }
1115
1116 clk_osc = devm_clk_get(dev, "osc");
1117 clk_xtal = devm_clk_get(dev, "xtal");
1118 if (!IS_ERR(clk_osc)) {
1119 s->clk = clk_osc;
1120 fmin = 500000;
1121 fmax = 35000000;
1122 } else if (!IS_ERR(clk_xtal)) {
1123 s->clk = clk_xtal;
1124 fmin = 1000000;
1125 fmax = 4000000;
1126 xtal = true;
1127 } else if (PTR_ERR(clk_osc) == -EPROBE_DEFER ||
1128 PTR_ERR(clk_xtal) == -EPROBE_DEFER) {
1129 return -EPROBE_DEFER;
1130 } else {
1131 dev_err(dev, "Cannot get clock\n");
1132 return -EINVAL;
1133 }
1134
1135 ret = clk_prepare_enable(s->clk);
1136 if (ret)
1137 return ret;
1138
1139 freq = clk_get_rate(s->clk);
1140 /* Check frequency limits */
1141 if (freq < fmin || freq > fmax) {
1142 ret = -ERANGE;
1143 goto out_clk;
1144 }
1145
1146 s->regmap = regmap;
1147 s->devtype = devtype;
1148 dev_set_drvdata(dev, s);
1149
1150 /* Check device to ensure we are talking to what we expect */
1151 ret = devtype->detect(dev);
1152 if (ret)
1153 goto out_clk;
1154
1155 for (i = 0; i < devtype->nr; i++) {
1156 unsigned int offs = i << 5;
1157
1158 /* Reset port */
1159 regmap_write(s->regmap, MAX310X_MODE2_REG + offs,
1160 MAX310X_MODE2_RST_BIT);
1161 /* Clear port reset */
1162 regmap_write(s->regmap, MAX310X_MODE2_REG + offs, 0);
1163
1164 /* Wait for port startup */
1165 do {
1166 regmap_read(s->regmap,
1167 MAX310X_BRGDIVLSB_REG + offs, &ret);
1168 } while (ret != 0x01);
1169
1170 regmap_update_bits(s->regmap, MAX310X_MODE1_REG + offs,
1171 MAX310X_MODE1_AUTOSLEEP_BIT,
1172 MAX310X_MODE1_AUTOSLEEP_BIT);
1173 }
1174
1175 uartclk = max310x_set_ref_clk(s, freq, xtal);
1176 dev_dbg(dev, "Reference clock set to %i Hz\n", uartclk);
1177
1178 /* Register UART driver */
1179 s->uart.owner = THIS_MODULE;
1180 s->uart.dev_name = "ttyMAX";
1181 s->uart.major = MAX310X_MAJOR;
1182 s->uart.minor = MAX310X_MINOR;
1183 s->uart.nr = devtype->nr;
1184 ret = uart_register_driver(&s->uart);
1185 if (ret) {
1186 dev_err(dev, "Registering UART driver failed\n");
1187 goto out_clk;
1188 }
1189
1190 #ifdef CONFIG_GPIOLIB
1191 /* Setup GPIO cotroller */
1192 s->gpio.owner = THIS_MODULE;
1193 s->gpio.dev = dev;
1194 s->gpio.label = dev_name(dev);
1195 s->gpio.direction_input = max310x_gpio_direction_input;
1196 s->gpio.get = max310x_gpio_get;
1197 s->gpio.direction_output= max310x_gpio_direction_output;
1198 s->gpio.set = max310x_gpio_set;
1199 s->gpio.base = -1;
1200 s->gpio.ngpio = devtype->nr * 4;
1201 s->gpio.can_sleep = 1;
1202 ret = gpiochip_add(&s->gpio);
1203 if (ret)
1204 goto out_uart;
1205 #endif
1206
1207 mutex_init(&s->mutex);
1208
1209 for (i = 0; i < devtype->nr; i++) {
1210 /* Initialize port data */
1211 s->p[i].port.line = i;
1212 s->p[i].port.dev = dev;
1213 s->p[i].port.irq = irq;
1214 s->p[i].port.type = PORT_MAX310X;
1215 s->p[i].port.fifosize = MAX310X_FIFO_SIZE;
1216 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY;
1217 s->p[i].port.iotype = UPIO_PORT;
1218 s->p[i].port.iobase = i * 0x20;
1219 s->p[i].port.membase = (void __iomem *)~0;
1220 s->p[i].port.uartclk = uartclk;
1221 s->p[i].port.ops = &max310x_ops;
1222 /* Disable all interrupts */
1223 max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0);
1224 /* Clear IRQ status register */
1225 max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG);
1226 /* Enable IRQ pin */
1227 max310x_port_update(&s->p[i].port, MAX310X_MODE1_REG,
1228 MAX310X_MODE1_IRQSEL_BIT,
1229 MAX310X_MODE1_IRQSEL_BIT);
1230 /* Initialize queue for start TX */
1231 INIT_WORK(&s->p[i].tx_work, max310x_wq_proc);
1232 /* Initialize queue for changing mode */
1233 INIT_WORK(&s->p[i].md_work, max310x_md_proc);
1234 /* Register port */
1235 uart_add_one_port(&s->uart, &s->p[i].port);
1236 /* Go to suspend mode */
1237 devtype->power(&s->p[i].port, 0);
1238 }
1239
1240 /* Setup interrupt */
1241 ret = devm_request_threaded_irq(dev, irq, NULL, max310x_ist,
1242 IRQF_ONESHOT | flags, dev_name(dev), s);
1243 if (!ret)
1244 return 0;
1245
1246 dev_err(dev, "Unable to reguest IRQ %i\n", irq);
1247
1248 mutex_destroy(&s->mutex);
1249
1250 #ifdef CONFIG_GPIOLIB
1251 WARN_ON(gpiochip_remove(&s->gpio));
1252
1253 out_uart:
1254 #endif
1255 uart_unregister_driver(&s->uart);
1256
1257 out_clk:
1258 clk_disable_unprepare(s->clk);
1259
1260 return ret;
1261 }
1262
1263 static int max310x_remove(struct device *dev)
1264 {
1265 struct max310x_port *s = dev_get_drvdata(dev);
1266 int i, ret = 0;
1267
1268 #ifdef CONFIG_GPIOLIB
1269 ret = gpiochip_remove(&s->gpio);
1270 if (ret)
1271 return ret;
1272 #endif
1273
1274 for (i = 0; i < s->uart.nr; i++) {
1275 cancel_work_sync(&s->p[i].tx_work);
1276 cancel_work_sync(&s->p[i].md_work);
1277 uart_remove_one_port(&s->uart, &s->p[i].port);
1278 s->devtype->power(&s->p[i].port, 0);
1279 }
1280
1281 mutex_destroy(&s->mutex);
1282 uart_unregister_driver(&s->uart);
1283 clk_disable_unprepare(s->clk);
1284
1285 return ret;
1286 }
1287
1288 static const struct of_device_id __maybe_unused max310x_dt_ids[] = {
1289 { .compatible = "maxim,max3107", .data = &max3107_devtype, },
1290 { .compatible = "maxim,max3108", .data = &max3108_devtype, },
1291 { .compatible = "maxim,max3109", .data = &max3109_devtype, },
1292 { .compatible = "maxim,max14830", .data = &max14830_devtype },
1293 { }
1294 };
1295 MODULE_DEVICE_TABLE(of, max310x_dt_ids);
1296
1297 static struct regmap_config regcfg = {
1298 .reg_bits = 8,
1299 .val_bits = 8,
1300 .write_flag_mask = 0x80,
1301 .cache_type = REGCACHE_RBTREE,
1302 .writeable_reg = max310x_reg_writeable,
1303 .volatile_reg = max310x_reg_volatile,
1304 .precious_reg = max310x_reg_precious,
1305 };
1306
1307 #ifdef CONFIG_SPI_MASTER
1308 static int max310x_spi_probe(struct spi_device *spi)
1309 {
1310 struct max310x_devtype *devtype;
1311 unsigned long flags = 0;
1312 struct regmap *regmap;
1313 int ret;
1314
1315 /* Setup SPI bus */
1316 spi->bits_per_word = 8;
1317 spi->mode = spi->mode ? : SPI_MODE_0;
1318 spi->max_speed_hz = spi->max_speed_hz ? : 26000000;
1319 ret = spi_setup(spi);
1320 if (ret)
1321 return ret;
1322
1323 if (spi->dev.of_node) {
1324 const struct of_device_id *of_id =
1325 of_match_device(max310x_dt_ids, &spi->dev);
1326
1327 devtype = (struct max310x_devtype *)of_id->data;
1328 } else {
1329 const struct spi_device_id *id_entry = spi_get_device_id(spi);
1330
1331 devtype = (struct max310x_devtype *)id_entry->driver_data;
1332 flags = IRQF_TRIGGER_FALLING;
1333 }
1334
1335 regcfg.max_register = devtype->nr * 0x20 - 1;
1336 regmap = devm_regmap_init_spi(spi, &regcfg);
1337
1338 return max310x_probe(&spi->dev, devtype, regmap, spi->irq, flags);
1339 }
1340
1341 static int max310x_spi_remove(struct spi_device *spi)
1342 {
1343 return max310x_remove(&spi->dev);
1344 }
1345
1346 static const struct spi_device_id max310x_id_table[] = {
1347 { "max3107", (kernel_ulong_t)&max3107_devtype, },
1348 { "max3108", (kernel_ulong_t)&max3108_devtype, },
1349 { "max3109", (kernel_ulong_t)&max3109_devtype, },
1350 { "max14830", (kernel_ulong_t)&max14830_devtype, },
1351 { }
1352 };
1353 MODULE_DEVICE_TABLE(spi, max310x_id_table);
1354
1355 static struct spi_driver max310x_uart_driver = {
1356 .driver = {
1357 .name = MAX310X_NAME,
1358 .owner = THIS_MODULE,
1359 .of_match_table = of_match_ptr(max310x_dt_ids),
1360 .pm = &max310x_pm_ops,
1361 },
1362 .probe = max310x_spi_probe,
1363 .remove = max310x_spi_remove,
1364 .id_table = max310x_id_table,
1365 };
1366 module_spi_driver(max310x_uart_driver);
1367 #endif
1368
1369 MODULE_LICENSE("GPL");
1370 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
1371 MODULE_DESCRIPTION("MAX310X serial driver");
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