2 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
10 * S3C USB2.0 High-speed / OtG driver
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/spinlock.h>
20 #include <linux/interrupt.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/mutex.h>
24 #include <linux/seq_file.h>
25 #include <linux/delay.h>
27 #include <linux/slab.h>
28 #include <linux/of_platform.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
32 #include <linux/usb/phy.h>
37 /* conversion functions */
38 static inline struct dwc2_hsotg_req
*our_req(struct usb_request
*req
)
40 return container_of(req
, struct dwc2_hsotg_req
, req
);
43 static inline struct dwc2_hsotg_ep
*our_ep(struct usb_ep
*ep
)
45 return container_of(ep
, struct dwc2_hsotg_ep
, ep
);
48 static inline struct dwc2_hsotg
*to_hsotg(struct usb_gadget
*gadget
)
50 return container_of(gadget
, struct dwc2_hsotg
, gadget
);
53 static inline void __orr32(void __iomem
*ptr
, u32 val
)
55 dwc2_writel(dwc2_readl(ptr
) | val
, ptr
);
58 static inline void __bic32(void __iomem
*ptr
, u32 val
)
60 dwc2_writel(dwc2_readl(ptr
) & ~val
, ptr
);
63 static inline struct dwc2_hsotg_ep
*index_to_ep(struct dwc2_hsotg
*hsotg
,
64 u32 ep_index
, u32 dir_in
)
67 return hsotg
->eps_in
[ep_index
];
69 return hsotg
->eps_out
[ep_index
];
72 /* forward declaration of functions */
73 static void dwc2_hsotg_dump(struct dwc2_hsotg
*hsotg
);
76 * using_dma - return the DMA status of the driver.
77 * @hsotg: The driver state.
79 * Return true if we're using DMA.
81 * Currently, we have the DMA support code worked into everywhere
82 * that needs it, but the AMBA DMA implementation in the hardware can
83 * only DMA from 32bit aligned addresses. This means that gadgets such
84 * as the CDC Ethernet cannot work as they often pass packets which are
87 * Unfortunately the choice to use DMA or not is global to the controller
88 * and seems to be only settable when the controller is being put through
89 * a core reset. This means we either need to fix the gadgets to take
90 * account of DMA alignment, or add bounce buffers (yuerk).
92 * g_using_dma is set depending on dts flag.
94 static inline bool using_dma(struct dwc2_hsotg
*hsotg
)
96 return hsotg
->params
.g_dma
;
100 * using_desc_dma - return the descriptor DMA status of the driver.
101 * @hsotg: The driver state.
103 * Return true if we're using descriptor DMA.
105 static inline bool using_desc_dma(struct dwc2_hsotg
*hsotg
)
107 return hsotg
->params
.g_dma_desc
;
111 * dwc2_gadget_incr_frame_num - Increments the targeted frame number.
112 * @hs_ep: The endpoint
113 * @increment: The value to increment by
115 * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT.
116 * If an overrun occurs it will wrap the value and set the frame_overrun flag.
118 static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep
*hs_ep
)
120 hs_ep
->target_frame
+= hs_ep
->interval
;
121 if (hs_ep
->target_frame
> DSTS_SOFFN_LIMIT
) {
122 hs_ep
->frame_overrun
= 1;
123 hs_ep
->target_frame
&= DSTS_SOFFN_LIMIT
;
125 hs_ep
->frame_overrun
= 0;
130 * dwc2_hsotg_en_gsint - enable one or more of the general interrupt
131 * @hsotg: The device state
132 * @ints: A bitmask of the interrupts to enable
134 static void dwc2_hsotg_en_gsint(struct dwc2_hsotg
*hsotg
, u32 ints
)
136 u32 gsintmsk
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
139 new_gsintmsk
= gsintmsk
| ints
;
141 if (new_gsintmsk
!= gsintmsk
) {
142 dev_dbg(hsotg
->dev
, "gsintmsk now 0x%08x\n", new_gsintmsk
);
143 dwc2_writel(new_gsintmsk
, hsotg
->regs
+ GINTMSK
);
148 * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt
149 * @hsotg: The device state
150 * @ints: A bitmask of the interrupts to enable
152 static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg
*hsotg
, u32 ints
)
154 u32 gsintmsk
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
157 new_gsintmsk
= gsintmsk
& ~ints
;
159 if (new_gsintmsk
!= gsintmsk
)
160 dwc2_writel(new_gsintmsk
, hsotg
->regs
+ GINTMSK
);
164 * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq
165 * @hsotg: The device state
166 * @ep: The endpoint index
167 * @dir_in: True if direction is in.
168 * @en: The enable value, true to enable
170 * Set or clear the mask for an individual endpoint's interrupt
173 static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg
*hsotg
,
174 unsigned int ep
, unsigned int dir_in
,
184 local_irq_save(flags
);
185 daint
= dwc2_readl(hsotg
->regs
+ DAINTMSK
);
190 dwc2_writel(daint
, hsotg
->regs
+ DAINTMSK
);
191 local_irq_restore(flags
);
195 * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs
196 * @hsotg: The device instance.
198 static void dwc2_hsotg_init_fifo(struct dwc2_hsotg
*hsotg
)
204 u32
*txfsz
= hsotg
->params
.g_tx_fifo_size
;
206 /* Reset fifo map if not correctly cleared during previous session */
207 WARN_ON(hsotg
->fifo_map
);
210 /* set RX/NPTX FIFO sizes */
211 dwc2_writel(hsotg
->params
.g_rx_fifo_size
, hsotg
->regs
+ GRXFSIZ
);
212 dwc2_writel((hsotg
->params
.g_rx_fifo_size
<< FIFOSIZE_STARTADDR_SHIFT
) |
213 (hsotg
->params
.g_np_tx_fifo_size
<< FIFOSIZE_DEPTH_SHIFT
),
214 hsotg
->regs
+ GNPTXFSIZ
);
217 * arange all the rest of the TX FIFOs, as some versions of this
218 * block have overlapping default addresses. This also ensures
219 * that if the settings have been changed, then they are set to
223 /* start at the end of the GNPTXFSIZ, rounded up */
224 addr
= hsotg
->params
.g_rx_fifo_size
+ hsotg
->params
.g_np_tx_fifo_size
;
227 * Configure fifos sizes from provided configuration and assign
228 * them to endpoints dynamically according to maxpacket size value of
231 for (ep
= 1; ep
< MAX_EPS_CHANNELS
; ep
++) {
235 val
|= txfsz
[ep
] << FIFOSIZE_DEPTH_SHIFT
;
236 WARN_ONCE(addr
+ txfsz
[ep
] > hsotg
->fifo_mem
,
237 "insufficient fifo memory");
240 dwc2_writel(val
, hsotg
->regs
+ DPTXFSIZN(ep
));
241 val
= dwc2_readl(hsotg
->regs
+ DPTXFSIZN(ep
));
245 * according to p428 of the design guide, we need to ensure that
246 * all fifos are flushed before continuing
249 dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH
|
250 GRSTCTL_RXFFLSH
, hsotg
->regs
+ GRSTCTL
);
252 /* wait until the fifos are both flushed */
255 val
= dwc2_readl(hsotg
->regs
+ GRSTCTL
);
257 if ((val
& (GRSTCTL_TXFFLSH
| GRSTCTL_RXFFLSH
)) == 0)
260 if (--timeout
== 0) {
262 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
270 dev_dbg(hsotg
->dev
, "FIFOs reset, timeout at %d\n", timeout
);
274 * @ep: USB endpoint to allocate request for.
275 * @flags: Allocation flags
277 * Allocate a new USB request structure appropriate for the specified endpoint
279 static struct usb_request
*dwc2_hsotg_ep_alloc_request(struct usb_ep
*ep
,
282 struct dwc2_hsotg_req
*req
;
284 req
= kzalloc(sizeof(struct dwc2_hsotg_req
), flags
);
288 INIT_LIST_HEAD(&req
->queue
);
294 * is_ep_periodic - return true if the endpoint is in periodic mode.
295 * @hs_ep: The endpoint to query.
297 * Returns true if the endpoint is in periodic mode, meaning it is being
298 * used for an Interrupt or ISO transfer.
300 static inline int is_ep_periodic(struct dwc2_hsotg_ep
*hs_ep
)
302 return hs_ep
->periodic
;
306 * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request
307 * @hsotg: The device state.
308 * @hs_ep: The endpoint for the request
309 * @hs_req: The request being processed.
311 * This is the reverse of dwc2_hsotg_map_dma(), called for the completion
312 * of a request to ensure the buffer is ready for access by the caller.
314 static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg
*hsotg
,
315 struct dwc2_hsotg_ep
*hs_ep
,
316 struct dwc2_hsotg_req
*hs_req
)
318 struct usb_request
*req
= &hs_req
->req
;
319 usb_gadget_unmap_request(&hsotg
->gadget
, req
, hs_ep
->dir_in
);
323 * dwc2_gadget_alloc_ctrl_desc_chains - allocate DMA descriptor chains
324 * for Control endpoint
325 * @hsotg: The device state.
327 * This function will allocate 4 descriptor chains for EP 0: 2 for
328 * Setup stage, per one for IN and OUT data/status transactions.
330 static int dwc2_gadget_alloc_ctrl_desc_chains(struct dwc2_hsotg
*hsotg
)
332 hsotg
->setup_desc
[0] =
333 dmam_alloc_coherent(hsotg
->dev
,
334 sizeof(struct dwc2_dma_desc
),
335 &hsotg
->setup_desc_dma
[0],
337 if (!hsotg
->setup_desc
[0])
340 hsotg
->setup_desc
[1] =
341 dmam_alloc_coherent(hsotg
->dev
,
342 sizeof(struct dwc2_dma_desc
),
343 &hsotg
->setup_desc_dma
[1],
345 if (!hsotg
->setup_desc
[1])
348 hsotg
->ctrl_in_desc
=
349 dmam_alloc_coherent(hsotg
->dev
,
350 sizeof(struct dwc2_dma_desc
),
351 &hsotg
->ctrl_in_desc_dma
,
353 if (!hsotg
->ctrl_in_desc
)
356 hsotg
->ctrl_out_desc
=
357 dmam_alloc_coherent(hsotg
->dev
,
358 sizeof(struct dwc2_dma_desc
),
359 &hsotg
->ctrl_out_desc_dma
,
361 if (!hsotg
->ctrl_out_desc
)
371 * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO
372 * @hsotg: The controller state.
373 * @hs_ep: The endpoint we're going to write for.
374 * @hs_req: The request to write data for.
376 * This is called when the TxFIFO has some space in it to hold a new
377 * transmission and we have something to give it. The actual setup of
378 * the data size is done elsewhere, so all we have to do is to actually
381 * The return value is zero if there is more space (or nothing was done)
382 * otherwise -ENOSPC is returned if the FIFO space was used up.
384 * This routine is only needed for PIO
386 static int dwc2_hsotg_write_fifo(struct dwc2_hsotg
*hsotg
,
387 struct dwc2_hsotg_ep
*hs_ep
,
388 struct dwc2_hsotg_req
*hs_req
)
390 bool periodic
= is_ep_periodic(hs_ep
);
391 u32 gnptxsts
= dwc2_readl(hsotg
->regs
+ GNPTXSTS
);
392 int buf_pos
= hs_req
->req
.actual
;
393 int to_write
= hs_ep
->size_loaded
;
399 to_write
-= (buf_pos
- hs_ep
->last_load
);
401 /* if there's nothing to write, get out early */
405 if (periodic
&& !hsotg
->dedicated_fifos
) {
406 u32 epsize
= dwc2_readl(hsotg
->regs
+ DIEPTSIZ(hs_ep
->index
));
411 * work out how much data was loaded so we can calculate
412 * how much data is left in the fifo.
415 size_left
= DXEPTSIZ_XFERSIZE_GET(epsize
);
418 * if shared fifo, we cannot write anything until the
419 * previous data has been completely sent.
421 if (hs_ep
->fifo_load
!= 0) {
422 dwc2_hsotg_en_gsint(hsotg
, GINTSTS_PTXFEMP
);
426 dev_dbg(hsotg
->dev
, "%s: left=%d, load=%d, fifo=%d, size %d\n",
428 hs_ep
->size_loaded
, hs_ep
->fifo_load
, hs_ep
->fifo_size
);
430 /* how much of the data has moved */
431 size_done
= hs_ep
->size_loaded
- size_left
;
433 /* how much data is left in the fifo */
434 can_write
= hs_ep
->fifo_load
- size_done
;
435 dev_dbg(hsotg
->dev
, "%s: => can_write1=%d\n",
436 __func__
, can_write
);
438 can_write
= hs_ep
->fifo_size
- can_write
;
439 dev_dbg(hsotg
->dev
, "%s: => can_write2=%d\n",
440 __func__
, can_write
);
442 if (can_write
<= 0) {
443 dwc2_hsotg_en_gsint(hsotg
, GINTSTS_PTXFEMP
);
446 } else if (hsotg
->dedicated_fifos
&& hs_ep
->index
!= 0) {
447 can_write
= dwc2_readl(hsotg
->regs
+
448 DTXFSTS(hs_ep
->fifo_index
));
453 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts
) == 0) {
455 "%s: no queue slots available (0x%08x)\n",
458 dwc2_hsotg_en_gsint(hsotg
, GINTSTS_NPTXFEMP
);
462 can_write
= GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts
);
463 can_write
*= 4; /* fifo size is in 32bit quantities. */
466 max_transfer
= hs_ep
->ep
.maxpacket
* hs_ep
->mc
;
468 dev_dbg(hsotg
->dev
, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
469 __func__
, gnptxsts
, can_write
, to_write
, max_transfer
);
472 * limit to 512 bytes of data, it seems at least on the non-periodic
473 * FIFO, requests of >512 cause the endpoint to get stuck with a
474 * fragment of the end of the transfer in it.
476 if (can_write
> 512 && !periodic
)
480 * limit the write to one max-packet size worth of data, but allow
481 * the transfer to return that it did not run out of fifo space
484 if (to_write
> max_transfer
) {
485 to_write
= max_transfer
;
487 /* it's needed only when we do not use dedicated fifos */
488 if (!hsotg
->dedicated_fifos
)
489 dwc2_hsotg_en_gsint(hsotg
,
490 periodic
? GINTSTS_PTXFEMP
:
494 /* see if we can write data */
496 if (to_write
> can_write
) {
497 to_write
= can_write
;
498 pkt_round
= to_write
% max_transfer
;
501 * Round the write down to an
502 * exact number of packets.
504 * Note, we do not currently check to see if we can ever
505 * write a full packet or not to the FIFO.
509 to_write
-= pkt_round
;
512 * enable correct FIFO interrupt to alert us when there
516 /* it's needed only when we do not use dedicated fifos */
517 if (!hsotg
->dedicated_fifos
)
518 dwc2_hsotg_en_gsint(hsotg
,
519 periodic
? GINTSTS_PTXFEMP
:
523 dev_dbg(hsotg
->dev
, "write %d/%d, can_write %d, done %d\n",
524 to_write
, hs_req
->req
.length
, can_write
, buf_pos
);
529 hs_req
->req
.actual
= buf_pos
+ to_write
;
530 hs_ep
->total_data
+= to_write
;
533 hs_ep
->fifo_load
+= to_write
;
535 to_write
= DIV_ROUND_UP(to_write
, 4);
536 data
= hs_req
->req
.buf
+ buf_pos
;
538 iowrite32_rep(hsotg
->regs
+ EPFIFO(hs_ep
->index
), data
, to_write
);
540 return (to_write
>= can_write
) ? -ENOSPC
: 0;
544 * get_ep_limit - get the maximum data legnth for this endpoint
545 * @hs_ep: The endpoint
547 * Return the maximum data that can be queued in one go on a given endpoint
548 * so that transfers that are too long can be split.
550 static unsigned get_ep_limit(struct dwc2_hsotg_ep
*hs_ep
)
552 int index
= hs_ep
->index
;
557 maxsize
= DXEPTSIZ_XFERSIZE_LIMIT
+ 1;
558 maxpkt
= DXEPTSIZ_PKTCNT_LIMIT
+ 1;
562 maxpkt
= DIEPTSIZ0_PKTCNT_LIMIT
+ 1;
567 /* we made the constant loading easier above by using +1 */
572 * constrain by packet count if maxpkts*pktsize is greater
573 * than the length register size.
576 if ((maxpkt
* hs_ep
->ep
.maxpacket
) < maxsize
)
577 maxsize
= maxpkt
* hs_ep
->ep
.maxpacket
;
583 * dwc2_hsotg_read_frameno - read current frame number
584 * @hsotg: The device instance
586 * Return the current frame number
588 static u32
dwc2_hsotg_read_frameno(struct dwc2_hsotg
*hsotg
)
592 dsts
= dwc2_readl(hsotg
->regs
+ DSTS
);
593 dsts
&= DSTS_SOFFN_MASK
;
594 dsts
>>= DSTS_SOFFN_SHIFT
;
600 * dwc2_gadget_get_chain_limit - get the maximum data payload value of the
601 * DMA descriptor chain prepared for specific endpoint
602 * @hs_ep: The endpoint
604 * Return the maximum data that can be queued in one go on a given endpoint
605 * depending on its descriptor chain capacity so that transfers that
606 * are too long can be split.
608 static unsigned int dwc2_gadget_get_chain_limit(struct dwc2_hsotg_ep
*hs_ep
)
610 int is_isoc
= hs_ep
->isochronous
;
611 unsigned int maxsize
;
614 maxsize
= hs_ep
->dir_in
? DEV_DMA_ISOC_TX_NBYTES_LIMIT
:
615 DEV_DMA_ISOC_RX_NBYTES_LIMIT
;
617 maxsize
= DEV_DMA_NBYTES_LIMIT
;
619 /* Above size of one descriptor was chosen, multiple it */
620 maxsize
*= MAX_DMA_DESC_NUM_GENERIC
;
626 * dwc2_gadget_get_desc_params - get DMA descriptor parameters.
627 * @hs_ep: The endpoint
628 * @mask: RX/TX bytes mask to be defined
630 * Returns maximum data payload for one descriptor after analyzing endpoint
632 * DMA descriptor transfer bytes limit depends on EP type:
634 * Isochronous - descriptor rx/tx bytes bitfield limit,
635 * Control In/Bulk/Interrupt - multiple of mps. This will allow to not
636 * have concatenations from various descriptors within one packet.
638 * Selects corresponding mask for RX/TX bytes as well.
640 static u32
dwc2_gadget_get_desc_params(struct dwc2_hsotg_ep
*hs_ep
, u32
*mask
)
642 u32 mps
= hs_ep
->ep
.maxpacket
;
643 int dir_in
= hs_ep
->dir_in
;
646 if (!hs_ep
->index
&& !dir_in
) {
648 *mask
= DEV_DMA_NBYTES_MASK
;
649 } else if (hs_ep
->isochronous
) {
651 desc_size
= DEV_DMA_ISOC_TX_NBYTES_LIMIT
;
652 *mask
= DEV_DMA_ISOC_TX_NBYTES_MASK
;
654 desc_size
= DEV_DMA_ISOC_RX_NBYTES_LIMIT
;
655 *mask
= DEV_DMA_ISOC_RX_NBYTES_MASK
;
658 desc_size
= DEV_DMA_NBYTES_LIMIT
;
659 *mask
= DEV_DMA_NBYTES_MASK
;
661 /* Round down desc_size to be mps multiple */
662 desc_size
-= desc_size
% mps
;
669 * dwc2_gadget_config_nonisoc_xfer_ddma - prepare non ISOC DMA desc chain.
670 * @hs_ep: The endpoint
671 * @dma_buff: DMA address to use
672 * @len: Length of the transfer
674 * This function will iterate over descriptor chain and fill its entries
675 * with corresponding information based on transfer data.
677 static void dwc2_gadget_config_nonisoc_xfer_ddma(struct dwc2_hsotg_ep
*hs_ep
,
681 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
682 int dir_in
= hs_ep
->dir_in
;
683 struct dwc2_dma_desc
*desc
= hs_ep
->desc_list
;
684 u32 mps
= hs_ep
->ep
.maxpacket
;
690 maxsize
= dwc2_gadget_get_desc_params(hs_ep
, &mask
);
692 hs_ep
->desc_count
= (len
/ maxsize
) +
693 ((len
% maxsize
) ? 1 : 0);
695 hs_ep
->desc_count
= 1;
697 for (i
= 0; i
< hs_ep
->desc_count
; ++i
) {
699 desc
->status
|= (DEV_DMA_BUFF_STS_HBUSY
700 << DEV_DMA_BUFF_STS_SHIFT
);
703 if (!hs_ep
->index
&& !dir_in
)
704 desc
->status
|= (DEV_DMA_L
| DEV_DMA_IOC
);
706 desc
->status
|= (maxsize
<<
707 DEV_DMA_NBYTES_SHIFT
& mask
);
708 desc
->buf
= dma_buff
+ offset
;
713 desc
->status
|= (DEV_DMA_L
| DEV_DMA_IOC
);
716 desc
->status
|= (len
% mps
) ? DEV_DMA_SHORT
:
717 ((hs_ep
->send_zlp
) ? DEV_DMA_SHORT
: 0);
719 dev_err(hsotg
->dev
, "wrong len %d\n", len
);
722 len
<< DEV_DMA_NBYTES_SHIFT
& mask
;
723 desc
->buf
= dma_buff
+ offset
;
726 desc
->status
&= ~DEV_DMA_BUFF_STS_MASK
;
727 desc
->status
|= (DEV_DMA_BUFF_STS_HREADY
728 << DEV_DMA_BUFF_STS_SHIFT
);
734 * dwc2_gadget_fill_isoc_desc - fills next isochronous descriptor in chain.
735 * @hs_ep: The isochronous endpoint.
736 * @dma_buff: usb requests dma buffer.
737 * @len: usb request transfer length.
739 * Finds out index of first free entry either in the bottom or up half of
740 * descriptor chain depend on which is under SW control and not processed
741 * by HW. Then fills that descriptor with the data of the arrived usb request,
742 * frame info, sets Last and IOC bits increments next_desc. If filled
743 * descriptor is not the first one, removes L bit from the previous descriptor
746 static int dwc2_gadget_fill_isoc_desc(struct dwc2_hsotg_ep
*hs_ep
,
747 dma_addr_t dma_buff
, unsigned int len
)
749 struct dwc2_dma_desc
*desc
;
750 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
755 maxsize
= dwc2_gadget_get_desc_params(hs_ep
, &mask
);
757 dev_err(hsotg
->dev
, "wrong len %d\n", len
);
762 * If SW has already filled half of chain, then return and wait for
763 * the other chain to be processed by HW.
765 if (hs_ep
->next_desc
== MAX_DMA_DESC_NUM_GENERIC
/ 2)
768 /* Increment frame number by interval for IN */
770 dwc2_gadget_incr_frame_num(hs_ep
);
772 index
= (MAX_DMA_DESC_NUM_GENERIC
/ 2) * hs_ep
->isoc_chain_num
+
775 /* Sanity check of calculated index */
776 if ((hs_ep
->isoc_chain_num
&& index
> MAX_DMA_DESC_NUM_GENERIC
) ||
777 (!hs_ep
->isoc_chain_num
&& index
> MAX_DMA_DESC_NUM_GENERIC
/ 2)) {
778 dev_err(hsotg
->dev
, "wrong index %d for iso chain\n", index
);
782 desc
= &hs_ep
->desc_list
[index
];
784 /* Clear L bit of previous desc if more than one entries in the chain */
785 if (hs_ep
->next_desc
)
786 hs_ep
->desc_list
[index
- 1].status
&= ~DEV_DMA_L
;
788 dev_dbg(hsotg
->dev
, "%s: Filling ep %d, dir %s isoc desc # %d\n",
789 __func__
, hs_ep
->index
, hs_ep
->dir_in
? "in" : "out", index
);
792 desc
->status
|= (DEV_DMA_BUFF_STS_HBUSY
<< DEV_DMA_BUFF_STS_SHIFT
);
794 desc
->buf
= dma_buff
;
795 desc
->status
|= (DEV_DMA_L
| DEV_DMA_IOC
|
796 ((len
<< DEV_DMA_NBYTES_SHIFT
) & mask
));
799 desc
->status
|= ((hs_ep
->mc
<< DEV_DMA_ISOC_PID_SHIFT
) &
800 DEV_DMA_ISOC_PID_MASK
) |
801 ((len
% hs_ep
->ep
.maxpacket
) ?
803 ((hs_ep
->target_frame
<<
804 DEV_DMA_ISOC_FRNUM_SHIFT
) &
805 DEV_DMA_ISOC_FRNUM_MASK
);
808 desc
->status
&= ~DEV_DMA_BUFF_STS_MASK
;
809 desc
->status
|= (DEV_DMA_BUFF_STS_HREADY
<< DEV_DMA_BUFF_STS_SHIFT
);
811 /* Update index of last configured entry in the chain */
818 * dwc2_gadget_start_isoc_ddma - start isochronous transfer in DDMA
819 * @hs_ep: The isochronous endpoint.
821 * Prepare first descriptor chain for isochronous endpoints. Afterwards
822 * write DMA address to HW and enable the endpoint.
824 * Switch between descriptor chains via isoc_chain_num to give SW opportunity
825 * to prepare second descriptor chain while first one is being processed by HW.
827 static void dwc2_gadget_start_isoc_ddma(struct dwc2_hsotg_ep
*hs_ep
)
829 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
830 struct dwc2_hsotg_req
*hs_req
, *treq
;
831 int index
= hs_ep
->index
;
837 if (list_empty(&hs_ep
->queue
)) {
838 dev_dbg(hsotg
->dev
, "%s: No requests in queue\n", __func__
);
842 list_for_each_entry_safe(hs_req
, treq
, &hs_ep
->queue
, queue
) {
843 ret
= dwc2_gadget_fill_isoc_desc(hs_ep
, hs_req
->req
.dma
,
846 dev_dbg(hsotg
->dev
, "%s: desc chain full\n", __func__
);
851 depctl
= hs_ep
->dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
852 dma_reg
= hs_ep
->dir_in
? DIEPDMA(index
) : DOEPDMA(index
);
854 /* write descriptor chain address to control register */
855 dwc2_writel(hs_ep
->desc_list_dma
, hsotg
->regs
+ dma_reg
);
857 ctrl
= dwc2_readl(hsotg
->regs
+ depctl
);
858 ctrl
|= DXEPCTL_EPENA
| DXEPCTL_CNAK
;
859 dwc2_writel(ctrl
, hsotg
->regs
+ depctl
);
861 /* Switch ISOC descriptor chain number being processed by SW*/
862 hs_ep
->isoc_chain_num
= (hs_ep
->isoc_chain_num
^ 1) & 0x1;
863 hs_ep
->next_desc
= 0;
867 * dwc2_hsotg_start_req - start a USB request from an endpoint's queue
868 * @hsotg: The controller state.
869 * @hs_ep: The endpoint to process a request for
870 * @hs_req: The request to start.
871 * @continuing: True if we are doing more for the current request.
873 * Start the given request running by setting the endpoint registers
874 * appropriately, and writing any data to the FIFOs.
876 static void dwc2_hsotg_start_req(struct dwc2_hsotg
*hsotg
,
877 struct dwc2_hsotg_ep
*hs_ep
,
878 struct dwc2_hsotg_req
*hs_req
,
881 struct usb_request
*ureq
= &hs_req
->req
;
882 int index
= hs_ep
->index
;
883 int dir_in
= hs_ep
->dir_in
;
891 unsigned int dma_reg
;
894 if (hs_ep
->req
&& !continuing
) {
895 dev_err(hsotg
->dev
, "%s: active request\n", __func__
);
898 } else if (hs_ep
->req
!= hs_req
&& continuing
) {
900 "%s: continue different req\n", __func__
);
906 dma_reg
= dir_in
? DIEPDMA(index
) : DOEPDMA(index
);
907 epctrl_reg
= dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
908 epsize_reg
= dir_in
? DIEPTSIZ(index
) : DOEPTSIZ(index
);
910 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
911 __func__
, dwc2_readl(hsotg
->regs
+ epctrl_reg
), index
,
912 hs_ep
->dir_in
? "in" : "out");
914 /* If endpoint is stalled, we will restart request later */
915 ctrl
= dwc2_readl(hsotg
->regs
+ epctrl_reg
);
917 if (index
&& ctrl
& DXEPCTL_STALL
) {
918 dev_warn(hsotg
->dev
, "%s: ep%d is stalled\n", __func__
, index
);
922 length
= ureq
->length
- ureq
->actual
;
923 dev_dbg(hsotg
->dev
, "ureq->length:%d ureq->actual:%d\n",
924 ureq
->length
, ureq
->actual
);
926 if (!using_desc_dma(hsotg
))
927 maxreq
= get_ep_limit(hs_ep
);
929 maxreq
= dwc2_gadget_get_chain_limit(hs_ep
);
931 if (length
> maxreq
) {
932 int round
= maxreq
% hs_ep
->ep
.maxpacket
;
934 dev_dbg(hsotg
->dev
, "%s: length %d, max-req %d, r %d\n",
935 __func__
, length
, maxreq
, round
);
937 /* round down to multiple of packets */
945 packets
= DIV_ROUND_UP(length
, hs_ep
->ep
.maxpacket
);
947 packets
= 1; /* send one packet if length is zero. */
949 if (hs_ep
->isochronous
&& length
> (hs_ep
->mc
* hs_ep
->ep
.maxpacket
)) {
950 dev_err(hsotg
->dev
, "req length > maxpacket*mc\n");
954 if (dir_in
&& index
!= 0)
955 if (hs_ep
->isochronous
)
956 epsize
= DXEPTSIZ_MC(packets
);
958 epsize
= DXEPTSIZ_MC(1);
963 * zero length packet should be programmed on its own and should not
964 * be counted in DIEPTSIZ.PktCnt with other packets.
966 if (dir_in
&& ureq
->zero
&& !continuing
) {
967 /* Test if zlp is actually required. */
968 if ((ureq
->length
>= hs_ep
->ep
.maxpacket
) &&
969 !(ureq
->length
% hs_ep
->ep
.maxpacket
))
973 epsize
|= DXEPTSIZ_PKTCNT(packets
);
974 epsize
|= DXEPTSIZ_XFERSIZE(length
);
976 dev_dbg(hsotg
->dev
, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
977 __func__
, packets
, length
, ureq
->length
, epsize
, epsize_reg
);
979 /* store the request as the current one we're doing */
982 if (using_desc_dma(hsotg
)) {
984 u32 mps
= hs_ep
->ep
.maxpacket
;
986 /* Adjust length: EP0 - MPS, other OUT EPs - multiple of MPS */
990 else if (length
% mps
)
991 length
+= (mps
- (length
% mps
));
995 * If more data to send, adjust DMA for EP0 out data stage.
996 * ureq->dma stays unchanged, hence increment it by already
997 * passed passed data count before starting new transaction.
999 if (!index
&& hsotg
->ep0_state
== DWC2_EP0_DATA_OUT
&&
1001 offset
= ureq
->actual
;
1003 /* Fill DDMA chain entries */
1004 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep
, ureq
->dma
+ offset
,
1007 /* write descriptor chain address to control register */
1008 dwc2_writel(hs_ep
->desc_list_dma
, hsotg
->regs
+ dma_reg
);
1010 dev_dbg(hsotg
->dev
, "%s: %08x pad => 0x%08x\n",
1011 __func__
, (u32
)hs_ep
->desc_list_dma
, dma_reg
);
1013 /* write size / packets */
1014 dwc2_writel(epsize
, hsotg
->regs
+ epsize_reg
);
1016 if (using_dma(hsotg
) && !continuing
&& (length
!= 0)) {
1018 * write DMA address to control register, buffer
1019 * already synced by dwc2_hsotg_ep_queue().
1022 dwc2_writel(ureq
->dma
, hsotg
->regs
+ dma_reg
);
1024 dev_dbg(hsotg
->dev
, "%s: %pad => 0x%08x\n",
1025 __func__
, &ureq
->dma
, dma_reg
);
1029 if (hs_ep
->isochronous
&& hs_ep
->interval
== 1) {
1030 hs_ep
->target_frame
= dwc2_hsotg_read_frameno(hsotg
);
1031 dwc2_gadget_incr_frame_num(hs_ep
);
1033 if (hs_ep
->target_frame
& 0x1)
1034 ctrl
|= DXEPCTL_SETODDFR
;
1036 ctrl
|= DXEPCTL_SETEVENFR
;
1039 ctrl
|= DXEPCTL_EPENA
; /* ensure ep enabled */
1041 dev_dbg(hsotg
->dev
, "ep0 state:%d\n", hsotg
->ep0_state
);
1043 /* For Setup request do not clear NAK */
1044 if (!(index
== 0 && hsotg
->ep0_state
== DWC2_EP0_SETUP
))
1045 ctrl
|= DXEPCTL_CNAK
; /* clear NAK set by core */
1047 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x\n", __func__
, ctrl
);
1048 dwc2_writel(ctrl
, hsotg
->regs
+ epctrl_reg
);
1051 * set these, it seems that DMA support increments past the end
1052 * of the packet buffer so we need to calculate the length from
1055 hs_ep
->size_loaded
= length
;
1056 hs_ep
->last_load
= ureq
->actual
;
1058 if (dir_in
&& !using_dma(hsotg
)) {
1059 /* set these anyway, we may need them for non-periodic in */
1060 hs_ep
->fifo_load
= 0;
1062 dwc2_hsotg_write_fifo(hsotg
, hs_ep
, hs_req
);
1066 * Note, trying to clear the NAK here causes problems with transmit
1067 * on the S3C6400 ending up with the TXFIFO becoming full.
1070 /* check ep is enabled */
1071 if (!(dwc2_readl(hsotg
->regs
+ epctrl_reg
) & DXEPCTL_EPENA
))
1073 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
1074 index
, dwc2_readl(hsotg
->regs
+ epctrl_reg
));
1076 dev_dbg(hsotg
->dev
, "%s: DXEPCTL=0x%08x\n",
1077 __func__
, dwc2_readl(hsotg
->regs
+ epctrl_reg
));
1079 /* enable ep interrupts */
1080 dwc2_hsotg_ctrl_epint(hsotg
, hs_ep
->index
, hs_ep
->dir_in
, 1);
1084 * dwc2_hsotg_map_dma - map the DMA memory being used for the request
1085 * @hsotg: The device state.
1086 * @hs_ep: The endpoint the request is on.
1087 * @req: The request being processed.
1089 * We've been asked to queue a request, so ensure that the memory buffer
1090 * is correctly setup for DMA. If we've been passed an extant DMA address
1091 * then ensure the buffer has been synced to memory. If our buffer has no
1092 * DMA memory, then we map the memory and mark our request to allow us to
1093 * cleanup on completion.
1095 static int dwc2_hsotg_map_dma(struct dwc2_hsotg
*hsotg
,
1096 struct dwc2_hsotg_ep
*hs_ep
,
1097 struct usb_request
*req
)
1101 ret
= usb_gadget_map_request(&hsotg
->gadget
, req
, hs_ep
->dir_in
);
1108 dev_err(hsotg
->dev
, "%s: failed to map buffer %p, %d bytes\n",
1109 __func__
, req
->buf
, req
->length
);
1114 static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg
*hsotg
,
1115 struct dwc2_hsotg_ep
*hs_ep
, struct dwc2_hsotg_req
*hs_req
)
1117 void *req_buf
= hs_req
->req
.buf
;
1119 /* If dma is not being used or buffer is aligned */
1120 if (!using_dma(hsotg
) || !((long)req_buf
& 3))
1123 WARN_ON(hs_req
->saved_req_buf
);
1125 dev_dbg(hsotg
->dev
, "%s: %s: buf=%p length=%d\n", __func__
,
1126 hs_ep
->ep
.name
, req_buf
, hs_req
->req
.length
);
1128 hs_req
->req
.buf
= kmalloc(hs_req
->req
.length
, GFP_ATOMIC
);
1129 if (!hs_req
->req
.buf
) {
1130 hs_req
->req
.buf
= req_buf
;
1132 "%s: unable to allocate memory for bounce buffer\n",
1137 /* Save actual buffer */
1138 hs_req
->saved_req_buf
= req_buf
;
1141 memcpy(hs_req
->req
.buf
, req_buf
, hs_req
->req
.length
);
1145 static void dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg
*hsotg
,
1146 struct dwc2_hsotg_ep
*hs_ep
, struct dwc2_hsotg_req
*hs_req
)
1148 /* If dma is not being used or buffer was aligned */
1149 if (!using_dma(hsotg
) || !hs_req
->saved_req_buf
)
1152 dev_dbg(hsotg
->dev
, "%s: %s: status=%d actual-length=%d\n", __func__
,
1153 hs_ep
->ep
.name
, hs_req
->req
.status
, hs_req
->req
.actual
);
1155 /* Copy data from bounce buffer on successful out transfer */
1156 if (!hs_ep
->dir_in
&& !hs_req
->req
.status
)
1157 memcpy(hs_req
->saved_req_buf
, hs_req
->req
.buf
,
1158 hs_req
->req
.actual
);
1160 /* Free bounce buffer */
1161 kfree(hs_req
->req
.buf
);
1163 hs_req
->req
.buf
= hs_req
->saved_req_buf
;
1164 hs_req
->saved_req_buf
= NULL
;
1168 * dwc2_gadget_target_frame_elapsed - Checks target frame
1169 * @hs_ep: The driver endpoint to check
1171 * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop
1172 * corresponding transfer.
1174 static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep
*hs_ep
)
1176 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
1177 u32 target_frame
= hs_ep
->target_frame
;
1178 u32 current_frame
= dwc2_hsotg_read_frameno(hsotg
);
1179 bool frame_overrun
= hs_ep
->frame_overrun
;
1181 if (!frame_overrun
&& current_frame
>= target_frame
)
1184 if (frame_overrun
&& current_frame
>= target_frame
&&
1185 ((current_frame
- target_frame
) < DSTS_SOFFN_LIMIT
/ 2))
1192 * dwc2_gadget_set_ep0_desc_chain - Set EP's desc chain pointers
1193 * @hsotg: The driver state
1194 * @hs_ep: the ep descriptor chain is for
1196 * Called to update EP0 structure's pointers depend on stage of
1199 static int dwc2_gadget_set_ep0_desc_chain(struct dwc2_hsotg
*hsotg
,
1200 struct dwc2_hsotg_ep
*hs_ep
)
1202 switch (hsotg
->ep0_state
) {
1203 case DWC2_EP0_SETUP
:
1204 case DWC2_EP0_STATUS_OUT
:
1205 hs_ep
->desc_list
= hsotg
->setup_desc
[0];
1206 hs_ep
->desc_list_dma
= hsotg
->setup_desc_dma
[0];
1208 case DWC2_EP0_DATA_IN
:
1209 case DWC2_EP0_STATUS_IN
:
1210 hs_ep
->desc_list
= hsotg
->ctrl_in_desc
;
1211 hs_ep
->desc_list_dma
= hsotg
->ctrl_in_desc_dma
;
1213 case DWC2_EP0_DATA_OUT
:
1214 hs_ep
->desc_list
= hsotg
->ctrl_out_desc
;
1215 hs_ep
->desc_list_dma
= hsotg
->ctrl_out_desc_dma
;
1218 dev_err(hsotg
->dev
, "invalid EP 0 state in queue %d\n",
1226 static int dwc2_hsotg_ep_queue(struct usb_ep
*ep
, struct usb_request
*req
,
1229 struct dwc2_hsotg_req
*hs_req
= our_req(req
);
1230 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
1231 struct dwc2_hsotg
*hs
= hs_ep
->parent
;
1235 dev_dbg(hs
->dev
, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
1236 ep
->name
, req
, req
->length
, req
->buf
, req
->no_interrupt
,
1237 req
->zero
, req
->short_not_ok
);
1239 /* Prevent new request submission when controller is suspended */
1240 if (hs
->lx_state
== DWC2_L2
) {
1241 dev_dbg(hs
->dev
, "%s: don't submit request while suspended\n",
1246 /* initialise status of the request */
1247 INIT_LIST_HEAD(&hs_req
->queue
);
1249 req
->status
= -EINPROGRESS
;
1251 ret
= dwc2_hsotg_handle_unaligned_buf_start(hs
, hs_ep
, hs_req
);
1255 /* if we're using DMA, sync the buffers as necessary */
1256 if (using_dma(hs
)) {
1257 ret
= dwc2_hsotg_map_dma(hs
, hs_ep
, req
);
1261 /* If using descriptor DMA configure EP0 descriptor chain pointers */
1262 if (using_desc_dma(hs
) && !hs_ep
->index
) {
1263 ret
= dwc2_gadget_set_ep0_desc_chain(hs
, hs_ep
);
1268 first
= list_empty(&hs_ep
->queue
);
1269 list_add_tail(&hs_req
->queue
, &hs_ep
->queue
);
1272 * Handle DDMA isochronous transfers separately - just add new entry
1273 * to the half of descriptor chain that is not processed by HW.
1274 * Transfer will be started once SW gets either one of NAK or
1275 * OutTknEpDis interrupts.
1277 if (using_desc_dma(hs
) && hs_ep
->isochronous
&&
1278 hs_ep
->target_frame
!= TARGET_FRAME_INITIAL
) {
1279 ret
= dwc2_gadget_fill_isoc_desc(hs_ep
, hs_req
->req
.dma
,
1280 hs_req
->req
.length
);
1282 dev_dbg(hs
->dev
, "%s: ISO desc chain full\n", __func__
);
1288 if (!hs_ep
->isochronous
) {
1289 dwc2_hsotg_start_req(hs
, hs_ep
, hs_req
, false);
1293 while (dwc2_gadget_target_frame_elapsed(hs_ep
))
1294 dwc2_gadget_incr_frame_num(hs_ep
);
1296 if (hs_ep
->target_frame
!= TARGET_FRAME_INITIAL
)
1297 dwc2_hsotg_start_req(hs
, hs_ep
, hs_req
, false);
1302 static int dwc2_hsotg_ep_queue_lock(struct usb_ep
*ep
, struct usb_request
*req
,
1305 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
1306 struct dwc2_hsotg
*hs
= hs_ep
->parent
;
1307 unsigned long flags
= 0;
1310 spin_lock_irqsave(&hs
->lock
, flags
);
1311 ret
= dwc2_hsotg_ep_queue(ep
, req
, gfp_flags
);
1312 spin_unlock_irqrestore(&hs
->lock
, flags
);
1317 static void dwc2_hsotg_ep_free_request(struct usb_ep
*ep
,
1318 struct usb_request
*req
)
1320 struct dwc2_hsotg_req
*hs_req
= our_req(req
);
1326 * dwc2_hsotg_complete_oursetup - setup completion callback
1327 * @ep: The endpoint the request was on.
1328 * @req: The request completed.
1330 * Called on completion of any requests the driver itself
1331 * submitted that need cleaning up.
1333 static void dwc2_hsotg_complete_oursetup(struct usb_ep
*ep
,
1334 struct usb_request
*req
)
1336 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
1337 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
1339 dev_dbg(hsotg
->dev
, "%s: ep %p, req %p\n", __func__
, ep
, req
);
1341 dwc2_hsotg_ep_free_request(ep
, req
);
1345 * ep_from_windex - convert control wIndex value to endpoint
1346 * @hsotg: The driver state.
1347 * @windex: The control request wIndex field (in host order).
1349 * Convert the given wIndex into a pointer to an driver endpoint
1350 * structure, or return NULL if it is not a valid endpoint.
1352 static struct dwc2_hsotg_ep
*ep_from_windex(struct dwc2_hsotg
*hsotg
,
1355 struct dwc2_hsotg_ep
*ep
;
1356 int dir
= (windex
& USB_DIR_IN
) ? 1 : 0;
1357 int idx
= windex
& 0x7F;
1359 if (windex
>= 0x100)
1362 if (idx
> hsotg
->num_of_eps
)
1365 ep
= index_to_ep(hsotg
, idx
, dir
);
1367 if (idx
&& ep
->dir_in
!= dir
)
1374 * dwc2_hsotg_set_test_mode - Enable usb Test Modes
1375 * @hsotg: The driver state.
1376 * @testmode: requested usb test mode
1377 * Enable usb Test Mode requested by the Host.
1379 int dwc2_hsotg_set_test_mode(struct dwc2_hsotg
*hsotg
, int testmode
)
1381 int dctl
= dwc2_readl(hsotg
->regs
+ DCTL
);
1383 dctl
&= ~DCTL_TSTCTL_MASK
;
1390 dctl
|= testmode
<< DCTL_TSTCTL_SHIFT
;
1395 dwc2_writel(dctl
, hsotg
->regs
+ DCTL
);
1400 * dwc2_hsotg_send_reply - send reply to control request
1401 * @hsotg: The device state
1403 * @buff: Buffer for request
1404 * @length: Length of reply.
1406 * Create a request and queue it on the given endpoint. This is useful as
1407 * an internal method of sending replies to certain control requests, etc.
1409 static int dwc2_hsotg_send_reply(struct dwc2_hsotg
*hsotg
,
1410 struct dwc2_hsotg_ep
*ep
,
1414 struct usb_request
*req
;
1417 dev_dbg(hsotg
->dev
, "%s: buff %p, len %d\n", __func__
, buff
, length
);
1419 req
= dwc2_hsotg_ep_alloc_request(&ep
->ep
, GFP_ATOMIC
);
1420 hsotg
->ep0_reply
= req
;
1422 dev_warn(hsotg
->dev
, "%s: cannot alloc req\n", __func__
);
1426 req
->buf
= hsotg
->ep0_buff
;
1427 req
->length
= length
;
1429 * zero flag is for sending zlp in DATA IN stage. It has no impact on
1433 req
->complete
= dwc2_hsotg_complete_oursetup
;
1436 memcpy(req
->buf
, buff
, length
);
1438 ret
= dwc2_hsotg_ep_queue(&ep
->ep
, req
, GFP_ATOMIC
);
1440 dev_warn(hsotg
->dev
, "%s: cannot queue req\n", __func__
);
1448 * dwc2_hsotg_process_req_status - process request GET_STATUS
1449 * @hsotg: The device state
1450 * @ctrl: USB control request
1452 static int dwc2_hsotg_process_req_status(struct dwc2_hsotg
*hsotg
,
1453 struct usb_ctrlrequest
*ctrl
)
1455 struct dwc2_hsotg_ep
*ep0
= hsotg
->eps_out
[0];
1456 struct dwc2_hsotg_ep
*ep
;
1460 dev_dbg(hsotg
->dev
, "%s: USB_REQ_GET_STATUS\n", __func__
);
1463 dev_warn(hsotg
->dev
, "%s: direction out?\n", __func__
);
1467 switch (ctrl
->bRequestType
& USB_RECIP_MASK
) {
1468 case USB_RECIP_DEVICE
:
1469 reply
= cpu_to_le16(0); /* bit 0 => self powered,
1470 * bit 1 => remote wakeup */
1473 case USB_RECIP_INTERFACE
:
1474 /* currently, the data result should be zero */
1475 reply
= cpu_to_le16(0);
1478 case USB_RECIP_ENDPOINT
:
1479 ep
= ep_from_windex(hsotg
, le16_to_cpu(ctrl
->wIndex
));
1483 reply
= cpu_to_le16(ep
->halted
? 1 : 0);
1490 if (le16_to_cpu(ctrl
->wLength
) != 2)
1493 ret
= dwc2_hsotg_send_reply(hsotg
, ep0
, &reply
, 2);
1495 dev_err(hsotg
->dev
, "%s: failed to send reply\n", __func__
);
1502 static int dwc2_hsotg_ep_sethalt(struct usb_ep
*ep
, int value
, bool now
);
1505 * get_ep_head - return the first request on the endpoint
1506 * @hs_ep: The controller endpoint to get
1508 * Get the first request on the endpoint.
1510 static struct dwc2_hsotg_req
*get_ep_head(struct dwc2_hsotg_ep
*hs_ep
)
1512 return list_first_entry_or_null(&hs_ep
->queue
, struct dwc2_hsotg_req
,
1517 * dwc2_gadget_start_next_request - Starts next request from ep queue
1518 * @hs_ep: Endpoint structure
1520 * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked
1521 * in its handler. Hence we need to unmask it here to be able to do
1522 * resynchronization.
1524 static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep
*hs_ep
)
1527 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
1528 int dir_in
= hs_ep
->dir_in
;
1529 struct dwc2_hsotg_req
*hs_req
;
1530 u32 epmsk_reg
= dir_in
? DIEPMSK
: DOEPMSK
;
1532 if (!list_empty(&hs_ep
->queue
)) {
1533 hs_req
= get_ep_head(hs_ep
);
1534 dwc2_hsotg_start_req(hsotg
, hs_ep
, hs_req
, false);
1537 if (!hs_ep
->isochronous
)
1541 dev_dbg(hsotg
->dev
, "%s: No more ISOC-IN requests\n",
1544 dev_dbg(hsotg
->dev
, "%s: No more ISOC-OUT requests\n",
1546 mask
= dwc2_readl(hsotg
->regs
+ epmsk_reg
);
1547 mask
|= DOEPMSK_OUTTKNEPDISMSK
;
1548 dwc2_writel(mask
, hsotg
->regs
+ epmsk_reg
);
1553 * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE
1554 * @hsotg: The device state
1555 * @ctrl: USB control request
1557 static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg
*hsotg
,
1558 struct usb_ctrlrequest
*ctrl
)
1560 struct dwc2_hsotg_ep
*ep0
= hsotg
->eps_out
[0];
1561 struct dwc2_hsotg_req
*hs_req
;
1562 bool set
= (ctrl
->bRequest
== USB_REQ_SET_FEATURE
);
1563 struct dwc2_hsotg_ep
*ep
;
1570 dev_dbg(hsotg
->dev
, "%s: %s_FEATURE\n",
1571 __func__
, set
? "SET" : "CLEAR");
1573 wValue
= le16_to_cpu(ctrl
->wValue
);
1574 wIndex
= le16_to_cpu(ctrl
->wIndex
);
1575 recip
= ctrl
->bRequestType
& USB_RECIP_MASK
;
1578 case USB_RECIP_DEVICE
:
1580 case USB_DEVICE_TEST_MODE
:
1581 if ((wIndex
& 0xff) != 0)
1586 hsotg
->test_mode
= wIndex
>> 8;
1587 ret
= dwc2_hsotg_send_reply(hsotg
, ep0
, NULL
, 0);
1590 "%s: failed to send reply\n", __func__
);
1599 case USB_RECIP_ENDPOINT
:
1600 ep
= ep_from_windex(hsotg
, wIndex
);
1602 dev_dbg(hsotg
->dev
, "%s: no endpoint for 0x%04x\n",
1608 case USB_ENDPOINT_HALT
:
1609 halted
= ep
->halted
;
1611 dwc2_hsotg_ep_sethalt(&ep
->ep
, set
, true);
1613 ret
= dwc2_hsotg_send_reply(hsotg
, ep0
, NULL
, 0);
1616 "%s: failed to send reply\n", __func__
);
1621 * we have to complete all requests for ep if it was
1622 * halted, and the halt was cleared by CLEAR_FEATURE
1625 if (!set
&& halted
) {
1627 * If we have request in progress,
1633 list_del_init(&hs_req
->queue
);
1634 if (hs_req
->req
.complete
) {
1635 spin_unlock(&hsotg
->lock
);
1636 usb_gadget_giveback_request(
1637 &ep
->ep
, &hs_req
->req
);
1638 spin_lock(&hsotg
->lock
);
1642 /* If we have pending request, then start it */
1644 dwc2_gadget_start_next_request(ep
);
1660 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg
*hsotg
);
1663 * dwc2_hsotg_stall_ep0 - stall ep0
1664 * @hsotg: The device state
1666 * Set stall for ep0 as response for setup request.
1668 static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg
*hsotg
)
1670 struct dwc2_hsotg_ep
*ep0
= hsotg
->eps_out
[0];
1674 dev_dbg(hsotg
->dev
, "ep0 stall (dir=%d)\n", ep0
->dir_in
);
1675 reg
= (ep0
->dir_in
) ? DIEPCTL0
: DOEPCTL0
;
1678 * DxEPCTL_Stall will be cleared by EP once it has
1679 * taken effect, so no need to clear later.
1682 ctrl
= dwc2_readl(hsotg
->regs
+ reg
);
1683 ctrl
|= DXEPCTL_STALL
;
1684 ctrl
|= DXEPCTL_CNAK
;
1685 dwc2_writel(ctrl
, hsotg
->regs
+ reg
);
1688 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1689 ctrl
, reg
, dwc2_readl(hsotg
->regs
+ reg
));
1692 * complete won't be called, so we enqueue
1693 * setup request here
1695 dwc2_hsotg_enqueue_setup(hsotg
);
1699 * dwc2_hsotg_process_control - process a control request
1700 * @hsotg: The device state
1701 * @ctrl: The control request received
1703 * The controller has received the SETUP phase of a control request, and
1704 * needs to work out what to do next (and whether to pass it on to the
1707 static void dwc2_hsotg_process_control(struct dwc2_hsotg
*hsotg
,
1708 struct usb_ctrlrequest
*ctrl
)
1710 struct dwc2_hsotg_ep
*ep0
= hsotg
->eps_out
[0];
1715 "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n",
1716 ctrl
->bRequestType
, ctrl
->bRequest
, ctrl
->wValue
,
1717 ctrl
->wIndex
, ctrl
->wLength
);
1719 if (ctrl
->wLength
== 0) {
1721 hsotg
->ep0_state
= DWC2_EP0_STATUS_IN
;
1722 } else if (ctrl
->bRequestType
& USB_DIR_IN
) {
1724 hsotg
->ep0_state
= DWC2_EP0_DATA_IN
;
1727 hsotg
->ep0_state
= DWC2_EP0_DATA_OUT
;
1730 if ((ctrl
->bRequestType
& USB_TYPE_MASK
) == USB_TYPE_STANDARD
) {
1731 switch (ctrl
->bRequest
) {
1732 case USB_REQ_SET_ADDRESS
:
1733 hsotg
->connected
= 1;
1734 dcfg
= dwc2_readl(hsotg
->regs
+ DCFG
);
1735 dcfg
&= ~DCFG_DEVADDR_MASK
;
1736 dcfg
|= (le16_to_cpu(ctrl
->wValue
) <<
1737 DCFG_DEVADDR_SHIFT
) & DCFG_DEVADDR_MASK
;
1738 dwc2_writel(dcfg
, hsotg
->regs
+ DCFG
);
1740 dev_info(hsotg
->dev
, "new address %d\n", ctrl
->wValue
);
1742 ret
= dwc2_hsotg_send_reply(hsotg
, ep0
, NULL
, 0);
1745 case USB_REQ_GET_STATUS
:
1746 ret
= dwc2_hsotg_process_req_status(hsotg
, ctrl
);
1749 case USB_REQ_CLEAR_FEATURE
:
1750 case USB_REQ_SET_FEATURE
:
1751 ret
= dwc2_hsotg_process_req_feature(hsotg
, ctrl
);
1756 /* as a fallback, try delivering it to the driver to deal with */
1758 if (ret
== 0 && hsotg
->driver
) {
1759 spin_unlock(&hsotg
->lock
);
1760 ret
= hsotg
->driver
->setup(&hsotg
->gadget
, ctrl
);
1761 spin_lock(&hsotg
->lock
);
1763 dev_dbg(hsotg
->dev
, "driver->setup() ret %d\n", ret
);
1767 * the request is either unhandlable, or is not formatted correctly
1768 * so respond with a STALL for the status stage to indicate failure.
1772 dwc2_hsotg_stall_ep0(hsotg
);
1776 * dwc2_hsotg_complete_setup - completion of a setup transfer
1777 * @ep: The endpoint the request was on.
1778 * @req: The request completed.
1780 * Called on completion of any requests the driver itself submitted for
1783 static void dwc2_hsotg_complete_setup(struct usb_ep
*ep
,
1784 struct usb_request
*req
)
1786 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
1787 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
1789 if (req
->status
< 0) {
1790 dev_dbg(hsotg
->dev
, "%s: failed %d\n", __func__
, req
->status
);
1794 spin_lock(&hsotg
->lock
);
1795 if (req
->actual
== 0)
1796 dwc2_hsotg_enqueue_setup(hsotg
);
1798 dwc2_hsotg_process_control(hsotg
, req
->buf
);
1799 spin_unlock(&hsotg
->lock
);
1803 * dwc2_hsotg_enqueue_setup - start a request for EP0 packets
1804 * @hsotg: The device state.
1806 * Enqueue a request on EP0 if necessary to received any SETUP packets
1807 * received from the host.
1809 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg
*hsotg
)
1811 struct usb_request
*req
= hsotg
->ctrl_req
;
1812 struct dwc2_hsotg_req
*hs_req
= our_req(req
);
1815 dev_dbg(hsotg
->dev
, "%s: queueing setup request\n", __func__
);
1819 req
->buf
= hsotg
->ctrl_buff
;
1820 req
->complete
= dwc2_hsotg_complete_setup
;
1822 if (!list_empty(&hs_req
->queue
)) {
1823 dev_dbg(hsotg
->dev
, "%s already queued???\n", __func__
);
1827 hsotg
->eps_out
[0]->dir_in
= 0;
1828 hsotg
->eps_out
[0]->send_zlp
= 0;
1829 hsotg
->ep0_state
= DWC2_EP0_SETUP
;
1831 ret
= dwc2_hsotg_ep_queue(&hsotg
->eps_out
[0]->ep
, req
, GFP_ATOMIC
);
1833 dev_err(hsotg
->dev
, "%s: failed queue (%d)\n", __func__
, ret
);
1835 * Don't think there's much we can do other than watch the
1841 static void dwc2_hsotg_program_zlp(struct dwc2_hsotg
*hsotg
,
1842 struct dwc2_hsotg_ep
*hs_ep
)
1845 u8 index
= hs_ep
->index
;
1846 u32 epctl_reg
= hs_ep
->dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
1847 u32 epsiz_reg
= hs_ep
->dir_in
? DIEPTSIZ(index
) : DOEPTSIZ(index
);
1850 dev_dbg(hsotg
->dev
, "Sending zero-length packet on ep%d\n",
1853 dev_dbg(hsotg
->dev
, "Receiving zero-length packet on ep%d\n",
1855 if (using_desc_dma(hsotg
)) {
1856 /* Not specific buffer needed for ep0 ZLP */
1857 dma_addr_t dma
= hs_ep
->desc_list_dma
;
1859 dwc2_gadget_set_ep0_desc_chain(hsotg
, hs_ep
);
1860 dwc2_gadget_config_nonisoc_xfer_ddma(hs_ep
, dma
, 0);
1862 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
1863 DXEPTSIZ_XFERSIZE(0), hsotg
->regs
+
1867 ctrl
= dwc2_readl(hsotg
->regs
+ epctl_reg
);
1868 ctrl
|= DXEPCTL_CNAK
; /* clear NAK set by core */
1869 ctrl
|= DXEPCTL_EPENA
; /* ensure ep enabled */
1870 ctrl
|= DXEPCTL_USBACTEP
;
1871 dwc2_writel(ctrl
, hsotg
->regs
+ epctl_reg
);
1875 * dwc2_hsotg_complete_request - complete a request given to us
1876 * @hsotg: The device state.
1877 * @hs_ep: The endpoint the request was on.
1878 * @hs_req: The request to complete.
1879 * @result: The result code (0 => Ok, otherwise errno)
1881 * The given request has finished, so call the necessary completion
1882 * if it has one and then look to see if we can start a new request
1885 * Note, expects the ep to already be locked as appropriate.
1887 static void dwc2_hsotg_complete_request(struct dwc2_hsotg
*hsotg
,
1888 struct dwc2_hsotg_ep
*hs_ep
,
1889 struct dwc2_hsotg_req
*hs_req
,
1894 dev_dbg(hsotg
->dev
, "%s: nothing to complete?\n", __func__
);
1898 dev_dbg(hsotg
->dev
, "complete: ep %p %s, req %p, %d => %p\n",
1899 hs_ep
, hs_ep
->ep
.name
, hs_req
, result
, hs_req
->req
.complete
);
1902 * only replace the status if we've not already set an error
1903 * from a previous transaction
1906 if (hs_req
->req
.status
== -EINPROGRESS
)
1907 hs_req
->req
.status
= result
;
1909 if (using_dma(hsotg
))
1910 dwc2_hsotg_unmap_dma(hsotg
, hs_ep
, hs_req
);
1912 dwc2_hsotg_handle_unaligned_buf_complete(hsotg
, hs_ep
, hs_req
);
1915 list_del_init(&hs_req
->queue
);
1918 * call the complete request with the locks off, just in case the
1919 * request tries to queue more work for this endpoint.
1922 if (hs_req
->req
.complete
) {
1923 spin_unlock(&hsotg
->lock
);
1924 usb_gadget_giveback_request(&hs_ep
->ep
, &hs_req
->req
);
1925 spin_lock(&hsotg
->lock
);
1928 /* In DDMA don't need to proceed to starting of next ISOC request */
1929 if (using_desc_dma(hsotg
) && hs_ep
->isochronous
)
1933 * Look to see if there is anything else to do. Note, the completion
1934 * of the previous request may have caused a new request to be started
1935 * so be careful when doing this.
1938 if (!hs_ep
->req
&& result
>= 0) {
1939 dwc2_gadget_start_next_request(hs_ep
);
1944 * dwc2_gadget_complete_isoc_request_ddma - complete an isoc request in DDMA
1945 * @hs_ep: The endpoint the request was on.
1947 * Get first request from the ep queue, determine descriptor on which complete
1948 * happened. SW based on isoc_chain_num discovers which half of the descriptor
1949 * chain is currently in use by HW, adjusts dma_address and calculates index
1950 * of completed descriptor based on the value of DEPDMA register. Update actual
1951 * length of request, giveback to gadget.
1953 static void dwc2_gadget_complete_isoc_request_ddma(struct dwc2_hsotg_ep
*hs_ep
)
1955 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
1956 struct dwc2_hsotg_req
*hs_req
;
1957 struct usb_request
*ureq
;
1959 dma_addr_t dma_addr
;
1965 hs_req
= get_ep_head(hs_ep
);
1967 dev_warn(hsotg
->dev
, "%s: ISOC EP queue empty\n", __func__
);
1970 ureq
= &hs_req
->req
;
1972 dma_addr
= hs_ep
->desc_list_dma
;
1975 * If lower half of descriptor chain is currently use by SW,
1976 * that means higher half is being processed by HW, so shift
1977 * DMA address to higher half of descriptor chain.
1979 if (!hs_ep
->isoc_chain_num
)
1980 dma_addr
+= sizeof(struct dwc2_dma_desc
) *
1981 (MAX_DMA_DESC_NUM_GENERIC
/ 2);
1983 dma_reg
= hs_ep
->dir_in
? DIEPDMA(hs_ep
->index
) : DOEPDMA(hs_ep
->index
);
1984 depdma
= dwc2_readl(hsotg
->regs
+ dma_reg
);
1986 index
= (depdma
- dma_addr
) / sizeof(struct dwc2_dma_desc
) - 1;
1987 desc_sts
= hs_ep
->desc_list
[index
].status
;
1989 mask
= hs_ep
->dir_in
? DEV_DMA_ISOC_TX_NBYTES_MASK
:
1990 DEV_DMA_ISOC_RX_NBYTES_MASK
;
1991 ureq
->actual
= ureq
->length
-
1992 ((desc_sts
& mask
) >> DEV_DMA_ISOC_NBYTES_SHIFT
);
1994 /* Adjust actual length for ISOC Out if length is not align of 4 */
1995 if (!hs_ep
->dir_in
&& ureq
->length
& 0x3)
1996 ureq
->actual
+= 4 - (ureq
->length
& 0x3);
1998 dwc2_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, 0);
2002 * dwc2_gadget_start_next_isoc_ddma - start next isoc request, if any.
2003 * @hs_ep: The isochronous endpoint to be re-enabled.
2005 * If ep has been disabled due to last descriptor servicing (IN endpoint) or
2006 * BNA (OUT endpoint) check the status of other half of descriptor chain that
2007 * was under SW control till HW was busy and restart the endpoint if needed.
2009 static void dwc2_gadget_start_next_isoc_ddma(struct dwc2_hsotg_ep
*hs_ep
)
2011 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
2015 u32 dma_addr
= hs_ep
->desc_list_dma
;
2016 unsigned char index
= hs_ep
->index
;
2018 dma_reg
= hs_ep
->dir_in
? DIEPDMA(index
) : DOEPDMA(index
);
2019 depctl
= hs_ep
->dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
2021 ctrl
= dwc2_readl(hsotg
->regs
+ depctl
);
2024 * EP was disabled if HW has processed last descriptor or BNA was set.
2025 * So restart ep if SW has prepared new descriptor chain in ep_queue
2026 * routine while HW was busy.
2028 if (!(ctrl
& DXEPCTL_EPENA
)) {
2029 if (!hs_ep
->next_desc
) {
2030 dev_dbg(hsotg
->dev
, "%s: No more ISOC requests\n",
2035 dma_addr
+= sizeof(struct dwc2_dma_desc
) *
2036 (MAX_DMA_DESC_NUM_GENERIC
/ 2) *
2037 hs_ep
->isoc_chain_num
;
2038 dwc2_writel(dma_addr
, hsotg
->regs
+ dma_reg
);
2040 ctrl
|= DXEPCTL_EPENA
| DXEPCTL_CNAK
;
2041 dwc2_writel(ctrl
, hsotg
->regs
+ depctl
);
2043 /* Switch ISOC descriptor chain number being processed by SW*/
2044 hs_ep
->isoc_chain_num
= (hs_ep
->isoc_chain_num
^ 1) & 0x1;
2045 hs_ep
->next_desc
= 0;
2047 dev_dbg(hsotg
->dev
, "%s: Restarted isochronous endpoint\n",
2053 * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint
2054 * @hsotg: The device state.
2055 * @ep_idx: The endpoint index for the data
2056 * @size: The size of data in the fifo, in bytes
2058 * The FIFO status shows there is data to read from the FIFO for a given
2059 * endpoint, so sort out whether we need to read the data into a request
2060 * that has been made for that endpoint.
2062 static void dwc2_hsotg_rx_data(struct dwc2_hsotg
*hsotg
, int ep_idx
, int size
)
2064 struct dwc2_hsotg_ep
*hs_ep
= hsotg
->eps_out
[ep_idx
];
2065 struct dwc2_hsotg_req
*hs_req
= hs_ep
->req
;
2066 void __iomem
*fifo
= hsotg
->regs
+ EPFIFO(ep_idx
);
2073 u32 epctl
= dwc2_readl(hsotg
->regs
+ DOEPCTL(ep_idx
));
2077 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
2078 __func__
, size
, ep_idx
, epctl
);
2080 /* dump the data from the FIFO, we've nothing we can do */
2081 for (ptr
= 0; ptr
< size
; ptr
+= 4)
2082 (void)dwc2_readl(fifo
);
2088 read_ptr
= hs_req
->req
.actual
;
2089 max_req
= hs_req
->req
.length
- read_ptr
;
2091 dev_dbg(hsotg
->dev
, "%s: read %d/%d, done %d/%d\n",
2092 __func__
, to_read
, max_req
, read_ptr
, hs_req
->req
.length
);
2094 if (to_read
> max_req
) {
2096 * more data appeared than we where willing
2097 * to deal with in this request.
2100 /* currently we don't deal this */
2104 hs_ep
->total_data
+= to_read
;
2105 hs_req
->req
.actual
+= to_read
;
2106 to_read
= DIV_ROUND_UP(to_read
, 4);
2109 * note, we might over-write the buffer end by 3 bytes depending on
2110 * alignment of the data.
2112 ioread32_rep(fifo
, hs_req
->req
.buf
+ read_ptr
, to_read
);
2116 * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint
2117 * @hsotg: The device instance
2118 * @dir_in: If IN zlp
2120 * Generate a zero-length IN packet request for terminating a SETUP
2123 * Note, since we don't write any data to the TxFIFO, then it is
2124 * currently believed that we do not need to wait for any space in
2127 static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg
*hsotg
, bool dir_in
)
2129 /* eps_out[0] is used in both directions */
2130 hsotg
->eps_out
[0]->dir_in
= dir_in
;
2131 hsotg
->ep0_state
= dir_in
? DWC2_EP0_STATUS_IN
: DWC2_EP0_STATUS_OUT
;
2133 dwc2_hsotg_program_zlp(hsotg
, hsotg
->eps_out
[0]);
2136 static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg
*hsotg
,
2141 ctrl
= dwc2_readl(hsotg
->regs
+ epctl_reg
);
2142 if (ctrl
& DXEPCTL_EOFRNUM
)
2143 ctrl
|= DXEPCTL_SETEVENFR
;
2145 ctrl
|= DXEPCTL_SETODDFR
;
2146 dwc2_writel(ctrl
, hsotg
->regs
+ epctl_reg
);
2150 * dwc2_gadget_get_xfersize_ddma - get transferred bytes amount from desc
2151 * @hs_ep - The endpoint on which transfer went
2153 * Iterate over endpoints descriptor chain and get info on bytes remained
2154 * in DMA descriptors after transfer has completed. Used for non isoc EPs.
2156 static unsigned int dwc2_gadget_get_xfersize_ddma(struct dwc2_hsotg_ep
*hs_ep
)
2158 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
2159 unsigned int bytes_rem
= 0;
2160 struct dwc2_dma_desc
*desc
= hs_ep
->desc_list
;
2167 for (i
= 0; i
< hs_ep
->desc_count
; ++i
) {
2168 status
= desc
->status
;
2169 bytes_rem
+= status
& DEV_DMA_NBYTES_MASK
;
2171 if (status
& DEV_DMA_STS_MASK
)
2172 dev_err(hsotg
->dev
, "descriptor %d closed with %x\n",
2173 i
, status
& DEV_DMA_STS_MASK
);
2180 * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
2181 * @hsotg: The device instance
2182 * @epnum: The endpoint received from
2184 * The RXFIFO has delivered an OutDone event, which means that the data
2185 * transfer for an OUT endpoint has been completed, either by a short
2186 * packet or by the finish of a transfer.
2188 static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg
*hsotg
, int epnum
)
2190 u32 epsize
= dwc2_readl(hsotg
->regs
+ DOEPTSIZ(epnum
));
2191 struct dwc2_hsotg_ep
*hs_ep
= hsotg
->eps_out
[epnum
];
2192 struct dwc2_hsotg_req
*hs_req
= hs_ep
->req
;
2193 struct usb_request
*req
= &hs_req
->req
;
2194 unsigned size_left
= DXEPTSIZ_XFERSIZE_GET(epsize
);
2198 dev_dbg(hsotg
->dev
, "%s: no request active\n", __func__
);
2202 if (epnum
== 0 && hsotg
->ep0_state
== DWC2_EP0_STATUS_OUT
) {
2203 dev_dbg(hsotg
->dev
, "zlp packet received\n");
2204 dwc2_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, 0);
2205 dwc2_hsotg_enqueue_setup(hsotg
);
2209 if (using_desc_dma(hsotg
))
2210 size_left
= dwc2_gadget_get_xfersize_ddma(hs_ep
);
2212 if (using_dma(hsotg
)) {
2216 * Calculate the size of the transfer by checking how much
2217 * is left in the endpoint size register and then working it
2218 * out from the amount we loaded for the transfer.
2220 * We need to do this as DMA pointers are always 32bit aligned
2221 * so may overshoot/undershoot the transfer.
2224 size_done
= hs_ep
->size_loaded
- size_left
;
2225 size_done
+= hs_ep
->last_load
;
2227 req
->actual
= size_done
;
2230 /* if there is more request to do, schedule new transfer */
2231 if (req
->actual
< req
->length
&& size_left
== 0) {
2232 dwc2_hsotg_start_req(hsotg
, hs_ep
, hs_req
, true);
2236 if (req
->actual
< req
->length
&& req
->short_not_ok
) {
2237 dev_dbg(hsotg
->dev
, "%s: got %d/%d (short not ok) => error\n",
2238 __func__
, req
->actual
, req
->length
);
2241 * todo - what should we return here? there's no one else
2242 * even bothering to check the status.
2246 /* DDMA IN status phase will start from StsPhseRcvd interrupt */
2247 if (!using_desc_dma(hsotg
) && epnum
== 0 &&
2248 hsotg
->ep0_state
== DWC2_EP0_DATA_OUT
) {
2249 /* Move to STATUS IN */
2250 dwc2_hsotg_ep0_zlp(hsotg
, true);
2255 * Slave mode OUT transfers do not go through XferComplete so
2256 * adjust the ISOC parity here.
2258 if (!using_dma(hsotg
)) {
2259 if (hs_ep
->isochronous
&& hs_ep
->interval
== 1)
2260 dwc2_hsotg_change_ep_iso_parity(hsotg
, DOEPCTL(epnum
));
2261 else if (hs_ep
->isochronous
&& hs_ep
->interval
> 1)
2262 dwc2_gadget_incr_frame_num(hs_ep
);
2265 dwc2_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, result
);
2269 * dwc2_hsotg_handle_rx - RX FIFO has data
2270 * @hsotg: The device instance
2272 * The IRQ handler has detected that the RX FIFO has some data in it
2273 * that requires processing, so find out what is in there and do the
2276 * The RXFIFO is a true FIFO, the packets coming out are still in packet
2277 * chunks, so if you have x packets received on an endpoint you'll get x
2278 * FIFO events delivered, each with a packet's worth of data in it.
2280 * When using DMA, we should not be processing events from the RXFIFO
2281 * as the actual data should be sent to the memory directly and we turn
2282 * on the completion interrupts to get notifications of transfer completion.
2284 static void dwc2_hsotg_handle_rx(struct dwc2_hsotg
*hsotg
)
2286 u32 grxstsr
= dwc2_readl(hsotg
->regs
+ GRXSTSP
);
2287 u32 epnum
, status
, size
;
2289 WARN_ON(using_dma(hsotg
));
2291 epnum
= grxstsr
& GRXSTS_EPNUM_MASK
;
2292 status
= grxstsr
& GRXSTS_PKTSTS_MASK
;
2294 size
= grxstsr
& GRXSTS_BYTECNT_MASK
;
2295 size
>>= GRXSTS_BYTECNT_SHIFT
;
2297 dev_dbg(hsotg
->dev
, "%s: GRXSTSP=0x%08x (%d@%d)\n",
2298 __func__
, grxstsr
, size
, epnum
);
2300 switch ((status
& GRXSTS_PKTSTS_MASK
) >> GRXSTS_PKTSTS_SHIFT
) {
2301 case GRXSTS_PKTSTS_GLOBALOUTNAK
:
2302 dev_dbg(hsotg
->dev
, "GLOBALOUTNAK\n");
2305 case GRXSTS_PKTSTS_OUTDONE
:
2306 dev_dbg(hsotg
->dev
, "OutDone (Frame=0x%08x)\n",
2307 dwc2_hsotg_read_frameno(hsotg
));
2309 if (!using_dma(hsotg
))
2310 dwc2_hsotg_handle_outdone(hsotg
, epnum
);
2313 case GRXSTS_PKTSTS_SETUPDONE
:
2315 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2316 dwc2_hsotg_read_frameno(hsotg
),
2317 dwc2_readl(hsotg
->regs
+ DOEPCTL(0)));
2319 * Call dwc2_hsotg_handle_outdone here if it was not called from
2320 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
2321 * generate GRXSTS_PKTSTS_OUTDONE for setup packet.
2323 if (hsotg
->ep0_state
== DWC2_EP0_SETUP
)
2324 dwc2_hsotg_handle_outdone(hsotg
, epnum
);
2327 case GRXSTS_PKTSTS_OUTRX
:
2328 dwc2_hsotg_rx_data(hsotg
, epnum
, size
);
2331 case GRXSTS_PKTSTS_SETUPRX
:
2333 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
2334 dwc2_hsotg_read_frameno(hsotg
),
2335 dwc2_readl(hsotg
->regs
+ DOEPCTL(0)));
2337 WARN_ON(hsotg
->ep0_state
!= DWC2_EP0_SETUP
);
2339 dwc2_hsotg_rx_data(hsotg
, epnum
, size
);
2343 dev_warn(hsotg
->dev
, "%s: unknown status %08x\n",
2346 dwc2_hsotg_dump(hsotg
);
2352 * dwc2_hsotg_ep0_mps - turn max packet size into register setting
2353 * @mps: The maximum packet size in bytes.
2355 static u32
dwc2_hsotg_ep0_mps(unsigned int mps
)
2359 return D0EPCTL_MPS_64
;
2361 return D0EPCTL_MPS_32
;
2363 return D0EPCTL_MPS_16
;
2365 return D0EPCTL_MPS_8
;
2368 /* bad max packet size, warn and return invalid result */
2374 * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field
2375 * @hsotg: The driver state.
2376 * @ep: The index number of the endpoint
2377 * @mps: The maximum packet size in bytes
2378 * @mc: The multicount value
2380 * Configure the maximum packet size for the given endpoint, updating
2381 * the hardware control registers to reflect this.
2383 static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg
*hsotg
,
2384 unsigned int ep
, unsigned int mps
,
2385 unsigned int mc
, unsigned int dir_in
)
2387 struct dwc2_hsotg_ep
*hs_ep
;
2388 void __iomem
*regs
= hsotg
->regs
;
2391 hs_ep
= index_to_ep(hsotg
, ep
, dir_in
);
2396 u32 mps_bytes
= mps
;
2398 /* EP0 is a special case */
2399 mps
= dwc2_hsotg_ep0_mps(mps_bytes
);
2402 hs_ep
->ep
.maxpacket
= mps_bytes
;
2410 hs_ep
->ep
.maxpacket
= mps
;
2414 reg
= dwc2_readl(regs
+ DIEPCTL(ep
));
2415 reg
&= ~DXEPCTL_MPS_MASK
;
2417 dwc2_writel(reg
, regs
+ DIEPCTL(ep
));
2419 reg
= dwc2_readl(regs
+ DOEPCTL(ep
));
2420 reg
&= ~DXEPCTL_MPS_MASK
;
2422 dwc2_writel(reg
, regs
+ DOEPCTL(ep
));
2428 dev_err(hsotg
->dev
, "ep%d: bad mps of %d\n", ep
, mps
);
2432 * dwc2_hsotg_txfifo_flush - flush Tx FIFO
2433 * @hsotg: The driver state
2434 * @idx: The index for the endpoint (0..15)
2436 static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg
*hsotg
, unsigned int idx
)
2441 dwc2_writel(GRSTCTL_TXFNUM(idx
) | GRSTCTL_TXFFLSH
,
2442 hsotg
->regs
+ GRSTCTL
);
2444 /* wait until the fifo is flushed */
2448 val
= dwc2_readl(hsotg
->regs
+ GRSTCTL
);
2450 if ((val
& (GRSTCTL_TXFFLSH
)) == 0)
2453 if (--timeout
== 0) {
2455 "%s: timeout flushing fifo (GRSTCTL=%08x)\n",
2465 * dwc2_hsotg_trytx - check to see if anything needs transmitting
2466 * @hsotg: The driver state
2467 * @hs_ep: The driver endpoint to check.
2469 * Check to see if there is a request that has data to send, and if so
2470 * make an attempt to write data into the FIFO.
2472 static int dwc2_hsotg_trytx(struct dwc2_hsotg
*hsotg
,
2473 struct dwc2_hsotg_ep
*hs_ep
)
2475 struct dwc2_hsotg_req
*hs_req
= hs_ep
->req
;
2477 if (!hs_ep
->dir_in
|| !hs_req
) {
2479 * if request is not enqueued, we disable interrupts
2480 * for endpoints, excepting ep0
2482 if (hs_ep
->index
!= 0)
2483 dwc2_hsotg_ctrl_epint(hsotg
, hs_ep
->index
,
2488 if (hs_req
->req
.actual
< hs_req
->req
.length
) {
2489 dev_dbg(hsotg
->dev
, "trying to write more for ep%d\n",
2491 return dwc2_hsotg_write_fifo(hsotg
, hs_ep
, hs_req
);
2498 * dwc2_hsotg_complete_in - complete IN transfer
2499 * @hsotg: The device state.
2500 * @hs_ep: The endpoint that has just completed.
2502 * An IN transfer has been completed, update the transfer's state and then
2503 * call the relevant completion routines.
2505 static void dwc2_hsotg_complete_in(struct dwc2_hsotg
*hsotg
,
2506 struct dwc2_hsotg_ep
*hs_ep
)
2508 struct dwc2_hsotg_req
*hs_req
= hs_ep
->req
;
2509 u32 epsize
= dwc2_readl(hsotg
->regs
+ DIEPTSIZ(hs_ep
->index
));
2510 int size_left
, size_done
;
2513 dev_dbg(hsotg
->dev
, "XferCompl but no req\n");
2517 /* Finish ZLP handling for IN EP0 transactions */
2518 if (hs_ep
->index
== 0 && hsotg
->ep0_state
== DWC2_EP0_STATUS_IN
) {
2519 dev_dbg(hsotg
->dev
, "zlp packet sent\n");
2522 * While send zlp for DWC2_EP0_STATUS_IN EP direction was
2523 * changed to IN. Change back to complete OUT transfer request
2527 dwc2_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, 0);
2528 if (hsotg
->test_mode
) {
2531 ret
= dwc2_hsotg_set_test_mode(hsotg
, hsotg
->test_mode
);
2533 dev_dbg(hsotg
->dev
, "Invalid Test #%d\n",
2535 dwc2_hsotg_stall_ep0(hsotg
);
2539 dwc2_hsotg_enqueue_setup(hsotg
);
2544 * Calculate the size of the transfer by checking how much is left
2545 * in the endpoint size register and then working it out from
2546 * the amount we loaded for the transfer.
2548 * We do this even for DMA, as the transfer may have incremented
2549 * past the end of the buffer (DMA transfers are always 32bit
2552 if (using_desc_dma(hsotg
)) {
2553 size_left
= dwc2_gadget_get_xfersize_ddma(hs_ep
);
2555 dev_err(hsotg
->dev
, "error parsing DDMA results %d\n",
2558 size_left
= DXEPTSIZ_XFERSIZE_GET(epsize
);
2561 size_done
= hs_ep
->size_loaded
- size_left
;
2562 size_done
+= hs_ep
->last_load
;
2564 if (hs_req
->req
.actual
!= size_done
)
2565 dev_dbg(hsotg
->dev
, "%s: adjusting size done %d => %d\n",
2566 __func__
, hs_req
->req
.actual
, size_done
);
2568 hs_req
->req
.actual
= size_done
;
2569 dev_dbg(hsotg
->dev
, "req->length:%d req->actual:%d req->zero:%d\n",
2570 hs_req
->req
.length
, hs_req
->req
.actual
, hs_req
->req
.zero
);
2572 if (!size_left
&& hs_req
->req
.actual
< hs_req
->req
.length
) {
2573 dev_dbg(hsotg
->dev
, "%s trying more for req...\n", __func__
);
2574 dwc2_hsotg_start_req(hsotg
, hs_ep
, hs_req
, true);
2578 /* Zlp for all endpoints, for ep0 only in DATA IN stage */
2579 if (hs_ep
->send_zlp
) {
2580 dwc2_hsotg_program_zlp(hsotg
, hs_ep
);
2581 hs_ep
->send_zlp
= 0;
2582 /* transfer will be completed on next complete interrupt */
2586 if (hs_ep
->index
== 0 && hsotg
->ep0_state
== DWC2_EP0_DATA_IN
) {
2587 /* Move to STATUS OUT */
2588 dwc2_hsotg_ep0_zlp(hsotg
, false);
2592 dwc2_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, 0);
2596 * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep
2597 * @hsotg: The device state.
2598 * @idx: Index of ep.
2599 * @dir_in: Endpoint direction 1-in 0-out.
2601 * Reads for endpoint with given index and direction, by masking
2602 * epint_reg with coresponding mask.
2604 static u32
dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg
*hsotg
,
2605 unsigned int idx
, int dir_in
)
2607 u32 epmsk_reg
= dir_in
? DIEPMSK
: DOEPMSK
;
2608 u32 epint_reg
= dir_in
? DIEPINT(idx
) : DOEPINT(idx
);
2613 mask
= dwc2_readl(hsotg
->regs
+ epmsk_reg
);
2614 diepempmsk
= dwc2_readl(hsotg
->regs
+ DIEPEMPMSK
);
2615 mask
|= ((diepempmsk
>> idx
) & 0x1) ? DIEPMSK_TXFIFOEMPTY
: 0;
2616 mask
|= DXEPINT_SETUP_RCVD
;
2618 ints
= dwc2_readl(hsotg
->regs
+ epint_reg
);
2624 * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD
2625 * @hs_ep: The endpoint on which interrupt is asserted.
2627 * This interrupt indicates that the endpoint has been disabled per the
2628 * application's request.
2630 * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK,
2631 * in case of ISOC completes current request.
2633 * For ISOC-OUT endpoints completes expired requests. If there is remaining
2634 * request starts it.
2636 static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep
*hs_ep
)
2638 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
2639 struct dwc2_hsotg_req
*hs_req
;
2640 unsigned char idx
= hs_ep
->index
;
2641 int dir_in
= hs_ep
->dir_in
;
2642 u32 epctl_reg
= dir_in
? DIEPCTL(idx
) : DOEPCTL(idx
);
2643 int dctl
= dwc2_readl(hsotg
->regs
+ DCTL
);
2645 dev_dbg(hsotg
->dev
, "%s: EPDisbld\n", __func__
);
2648 int epctl
= dwc2_readl(hsotg
->regs
+ epctl_reg
);
2650 dwc2_hsotg_txfifo_flush(hsotg
, hs_ep
->fifo_index
);
2652 if (hs_ep
->isochronous
) {
2653 dwc2_hsotg_complete_in(hsotg
, hs_ep
);
2657 if ((epctl
& DXEPCTL_STALL
) && (epctl
& DXEPCTL_EPTYPE_BULK
)) {
2658 int dctl
= dwc2_readl(hsotg
->regs
+ DCTL
);
2660 dctl
|= DCTL_CGNPINNAK
;
2661 dwc2_writel(dctl
, hsotg
->regs
+ DCTL
);
2666 if (dctl
& DCTL_GOUTNAKSTS
) {
2667 dctl
|= DCTL_CGOUTNAK
;
2668 dwc2_writel(dctl
, hsotg
->regs
+ DCTL
);
2671 if (!hs_ep
->isochronous
)
2674 if (list_empty(&hs_ep
->queue
)) {
2675 dev_dbg(hsotg
->dev
, "%s: complete_ep 0x%p, ep->queue empty!\n",
2681 hs_req
= get_ep_head(hs_ep
);
2683 dwc2_hsotg_complete_request(hsotg
, hs_ep
, hs_req
,
2685 dwc2_gadget_incr_frame_num(hs_ep
);
2686 } while (dwc2_gadget_target_frame_elapsed(hs_ep
));
2688 dwc2_gadget_start_next_request(hs_ep
);
2692 * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS
2693 * @hs_ep: The endpoint on which interrupt is asserted.
2695 * This is starting point for ISOC-OUT transfer, synchronization done with
2696 * first out token received from host while corresponding EP is disabled.
2698 * Device does not know initial frame in which out token will come. For this
2699 * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon
2700 * getting this interrupt SW starts calculation for next transfer frame.
2702 static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep
*ep
)
2704 struct dwc2_hsotg
*hsotg
= ep
->parent
;
2705 int dir_in
= ep
->dir_in
;
2709 if (dir_in
|| !ep
->isochronous
)
2713 * Store frame in which irq was asserted here, as
2714 * it can change while completing request below.
2716 tmp
= dwc2_hsotg_read_frameno(hsotg
);
2718 dwc2_hsotg_complete_request(hsotg
, ep
, get_ep_head(ep
), -ENODATA
);
2720 if (using_desc_dma(hsotg
)) {
2721 if (ep
->target_frame
== TARGET_FRAME_INITIAL
) {
2722 /* Start first ISO Out */
2723 ep
->target_frame
= tmp
;
2724 dwc2_gadget_start_isoc_ddma(ep
);
2729 if (ep
->interval
> 1 &&
2730 ep
->target_frame
== TARGET_FRAME_INITIAL
) {
2734 dsts
= dwc2_readl(hsotg
->regs
+ DSTS
);
2735 ep
->target_frame
= dwc2_hsotg_read_frameno(hsotg
);
2736 dwc2_gadget_incr_frame_num(ep
);
2738 ctrl
= dwc2_readl(hsotg
->regs
+ DOEPCTL(ep
->index
));
2739 if (ep
->target_frame
& 0x1)
2740 ctrl
|= DXEPCTL_SETODDFR
;
2742 ctrl
|= DXEPCTL_SETEVENFR
;
2744 dwc2_writel(ctrl
, hsotg
->regs
+ DOEPCTL(ep
->index
));
2747 dwc2_gadget_start_next_request(ep
);
2748 doepmsk
= dwc2_readl(hsotg
->regs
+ DOEPMSK
);
2749 doepmsk
&= ~DOEPMSK_OUTTKNEPDISMSK
;
2750 dwc2_writel(doepmsk
, hsotg
->regs
+ DOEPMSK
);
2754 * dwc2_gadget_handle_nak - handle NAK interrupt
2755 * @hs_ep: The endpoint on which interrupt is asserted.
2757 * This is starting point for ISOC-IN transfer, synchronization done with
2758 * first IN token received from host while corresponding EP is disabled.
2760 * Device does not know when first one token will arrive from host. On first
2761 * token arrival HW generates 2 interrupts: 'in token received while FIFO empty'
2762 * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was
2763 * sent in response to that as there was no data in FIFO. SW is basing on this
2764 * interrupt to obtain frame in which token has come and then based on the
2765 * interval calculates next frame for transfer.
2767 static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep
*hs_ep
)
2769 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
2770 int dir_in
= hs_ep
->dir_in
;
2772 if (!dir_in
|| !hs_ep
->isochronous
)
2775 if (hs_ep
->target_frame
== TARGET_FRAME_INITIAL
) {
2776 hs_ep
->target_frame
= dwc2_hsotg_read_frameno(hsotg
);
2778 if (using_desc_dma(hsotg
)) {
2779 dwc2_gadget_start_isoc_ddma(hs_ep
);
2783 if (hs_ep
->interval
> 1) {
2784 u32 ctrl
= dwc2_readl(hsotg
->regs
+
2785 DIEPCTL(hs_ep
->index
));
2786 if (hs_ep
->target_frame
& 0x1)
2787 ctrl
|= DXEPCTL_SETODDFR
;
2789 ctrl
|= DXEPCTL_SETEVENFR
;
2791 dwc2_writel(ctrl
, hsotg
->regs
+ DIEPCTL(hs_ep
->index
));
2794 dwc2_hsotg_complete_request(hsotg
, hs_ep
,
2795 get_ep_head(hs_ep
), 0);
2798 dwc2_gadget_incr_frame_num(hs_ep
);
2802 * dwc2_hsotg_epint - handle an in/out endpoint interrupt
2803 * @hsotg: The driver state
2804 * @idx: The index for the endpoint (0..15)
2805 * @dir_in: Set if this is an IN endpoint
2807 * Process and clear any interrupt pending for an individual endpoint
2809 static void dwc2_hsotg_epint(struct dwc2_hsotg
*hsotg
, unsigned int idx
,
2812 struct dwc2_hsotg_ep
*hs_ep
= index_to_ep(hsotg
, idx
, dir_in
);
2813 u32 epint_reg
= dir_in
? DIEPINT(idx
) : DOEPINT(idx
);
2814 u32 epctl_reg
= dir_in
? DIEPCTL(idx
) : DOEPCTL(idx
);
2815 u32 epsiz_reg
= dir_in
? DIEPTSIZ(idx
) : DOEPTSIZ(idx
);
2819 ints
= dwc2_gadget_read_ep_interrupts(hsotg
, idx
, dir_in
);
2820 ctrl
= dwc2_readl(hsotg
->regs
+ epctl_reg
);
2822 /* Clear endpoint interrupts */
2823 dwc2_writel(ints
, hsotg
->regs
+ epint_reg
);
2826 dev_err(hsotg
->dev
, "%s:Interrupt for unconfigured ep%d(%s)\n",
2827 __func__
, idx
, dir_in
? "in" : "out");
2831 dev_dbg(hsotg
->dev
, "%s: ep%d(%s) DxEPINT=0x%08x\n",
2832 __func__
, idx
, dir_in
? "in" : "out", ints
);
2834 /* Don't process XferCompl interrupt if it is a setup packet */
2835 if (idx
== 0 && (ints
& (DXEPINT_SETUP
| DXEPINT_SETUP_RCVD
)))
2836 ints
&= ~DXEPINT_XFERCOMPL
;
2839 * Don't process XferCompl interrupt in DDMA if EP0 is still in SETUP
2840 * stage and xfercomplete was generated without SETUP phase done
2841 * interrupt. SW should parse received setup packet only after host's
2842 * exit from setup phase of control transfer.
2844 if (using_desc_dma(hsotg
) && idx
== 0 && !hs_ep
->dir_in
&&
2845 hsotg
->ep0_state
== DWC2_EP0_SETUP
&& !(ints
& DXEPINT_SETUP
))
2846 ints
&= ~DXEPINT_XFERCOMPL
;
2848 if (ints
& DXEPINT_XFERCOMPL
) {
2850 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
2851 __func__
, dwc2_readl(hsotg
->regs
+ epctl_reg
),
2852 dwc2_readl(hsotg
->regs
+ epsiz_reg
));
2854 /* In DDMA handle isochronous requests separately */
2855 if (using_desc_dma(hsotg
) && hs_ep
->isochronous
) {
2856 dwc2_gadget_complete_isoc_request_ddma(hs_ep
);
2857 /* Try to start next isoc request */
2858 dwc2_gadget_start_next_isoc_ddma(hs_ep
);
2859 } else if (dir_in
) {
2861 * We get OutDone from the FIFO, so we only
2862 * need to look at completing IN requests here
2863 * if operating slave mode
2865 if (hs_ep
->isochronous
&& hs_ep
->interval
> 1)
2866 dwc2_gadget_incr_frame_num(hs_ep
);
2868 dwc2_hsotg_complete_in(hsotg
, hs_ep
);
2869 if (ints
& DXEPINT_NAKINTRPT
)
2870 ints
&= ~DXEPINT_NAKINTRPT
;
2872 if (idx
== 0 && !hs_ep
->req
)
2873 dwc2_hsotg_enqueue_setup(hsotg
);
2874 } else if (using_dma(hsotg
)) {
2876 * We're using DMA, we need to fire an OutDone here
2877 * as we ignore the RXFIFO.
2879 if (hs_ep
->isochronous
&& hs_ep
->interval
> 1)
2880 dwc2_gadget_incr_frame_num(hs_ep
);
2882 dwc2_hsotg_handle_outdone(hsotg
, idx
);
2886 if (ints
& DXEPINT_EPDISBLD
)
2887 dwc2_gadget_handle_ep_disabled(hs_ep
);
2889 if (ints
& DXEPINT_OUTTKNEPDIS
)
2890 dwc2_gadget_handle_out_token_ep_disabled(hs_ep
);
2892 if (ints
& DXEPINT_NAKINTRPT
)
2893 dwc2_gadget_handle_nak(hs_ep
);
2895 if (ints
& DXEPINT_AHBERR
)
2896 dev_dbg(hsotg
->dev
, "%s: AHBErr\n", __func__
);
2898 if (ints
& DXEPINT_SETUP
) { /* Setup or Timeout */
2899 dev_dbg(hsotg
->dev
, "%s: Setup/Timeout\n", __func__
);
2901 if (using_dma(hsotg
) && idx
== 0) {
2903 * this is the notification we've received a
2904 * setup packet. In non-DMA mode we'd get this
2905 * from the RXFIFO, instead we need to process
2912 dwc2_hsotg_handle_outdone(hsotg
, 0);
2916 if (ints
& DXEPINT_STSPHSERCVD
) {
2917 dev_dbg(hsotg
->dev
, "%s: StsPhseRcvd\n", __func__
);
2919 /* Move to STATUS IN for DDMA */
2920 if (using_desc_dma(hsotg
))
2921 dwc2_hsotg_ep0_zlp(hsotg
, true);
2924 if (ints
& DXEPINT_BACK2BACKSETUP
)
2925 dev_dbg(hsotg
->dev
, "%s: B2BSetup/INEPNakEff\n", __func__
);
2927 if (ints
& DXEPINT_BNAINTR
) {
2928 dev_dbg(hsotg
->dev
, "%s: BNA interrupt\n", __func__
);
2931 * Try to start next isoc request, if any.
2932 * Sometimes the endpoint remains enabled after BNA interrupt
2933 * assertion, which is not expected, hence we can enter here
2936 if (hs_ep
->isochronous
)
2937 dwc2_gadget_start_next_isoc_ddma(hs_ep
);
2940 if (dir_in
&& !hs_ep
->isochronous
) {
2941 /* not sure if this is important, but we'll clear it anyway */
2942 if (ints
& DXEPINT_INTKNTXFEMP
) {
2943 dev_dbg(hsotg
->dev
, "%s: ep%d: INTknTXFEmpMsk\n",
2947 /* this probably means something bad is happening */
2948 if (ints
& DXEPINT_INTKNEPMIS
) {
2949 dev_warn(hsotg
->dev
, "%s: ep%d: INTknEP\n",
2953 /* FIFO has space or is empty (see GAHBCFG) */
2954 if (hsotg
->dedicated_fifos
&&
2955 ints
& DXEPINT_TXFEMP
) {
2956 dev_dbg(hsotg
->dev
, "%s: ep%d: TxFIFOEmpty\n",
2958 if (!using_dma(hsotg
))
2959 dwc2_hsotg_trytx(hsotg
, hs_ep
);
2965 * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
2966 * @hsotg: The device state.
2968 * Handle updating the device settings after the enumeration phase has
2971 static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg
*hsotg
)
2973 u32 dsts
= dwc2_readl(hsotg
->regs
+ DSTS
);
2974 int ep0_mps
= 0, ep_mps
= 8;
2977 * This should signal the finish of the enumeration phase
2978 * of the USB handshaking, so we should now know what rate
2982 dev_dbg(hsotg
->dev
, "EnumDone (DSTS=0x%08x)\n", dsts
);
2985 * note, since we're limited by the size of transfer on EP0, and
2986 * it seems IN transfers must be a even number of packets we do
2987 * not advertise a 64byte MPS on EP0.
2990 /* catch both EnumSpd_FS and EnumSpd_FS48 */
2991 switch ((dsts
& DSTS_ENUMSPD_MASK
) >> DSTS_ENUMSPD_SHIFT
) {
2992 case DSTS_ENUMSPD_FS
:
2993 case DSTS_ENUMSPD_FS48
:
2994 hsotg
->gadget
.speed
= USB_SPEED_FULL
;
2995 ep0_mps
= EP0_MPS_LIMIT
;
2999 case DSTS_ENUMSPD_HS
:
3000 hsotg
->gadget
.speed
= USB_SPEED_HIGH
;
3001 ep0_mps
= EP0_MPS_LIMIT
;
3005 case DSTS_ENUMSPD_LS
:
3006 hsotg
->gadget
.speed
= USB_SPEED_LOW
;
3010 * note, we don't actually support LS in this driver at the
3011 * moment, and the documentation seems to imply that it isn't
3012 * supported by the PHYs on some of the devices.
3016 dev_info(hsotg
->dev
, "new device is %s\n",
3017 usb_speed_string(hsotg
->gadget
.speed
));
3020 * we should now know the maximum packet size for an
3021 * endpoint, so set the endpoints to a default value.
3026 /* Initialize ep0 for both in and out directions */
3027 dwc2_hsotg_set_ep_maxpacket(hsotg
, 0, ep0_mps
, 0, 1);
3028 dwc2_hsotg_set_ep_maxpacket(hsotg
, 0, ep0_mps
, 0, 0);
3029 for (i
= 1; i
< hsotg
->num_of_eps
; i
++) {
3030 if (hsotg
->eps_in
[i
])
3031 dwc2_hsotg_set_ep_maxpacket(hsotg
, i
, ep_mps
,
3033 if (hsotg
->eps_out
[i
])
3034 dwc2_hsotg_set_ep_maxpacket(hsotg
, i
, ep_mps
,
3039 /* ensure after enumeration our EP0 is active */
3041 dwc2_hsotg_enqueue_setup(hsotg
);
3043 dev_dbg(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3044 dwc2_readl(hsotg
->regs
+ DIEPCTL0
),
3045 dwc2_readl(hsotg
->regs
+ DOEPCTL0
));
3049 * kill_all_requests - remove all requests from the endpoint's queue
3050 * @hsotg: The device state.
3051 * @ep: The endpoint the requests may be on.
3052 * @result: The result code to use.
3054 * Go through the requests on the given endpoint and mark them
3055 * completed with the given result code.
3057 static void kill_all_requests(struct dwc2_hsotg
*hsotg
,
3058 struct dwc2_hsotg_ep
*ep
,
3061 struct dwc2_hsotg_req
*req
, *treq
;
3066 list_for_each_entry_safe(req
, treq
, &ep
->queue
, queue
)
3067 dwc2_hsotg_complete_request(hsotg
, ep
, req
,
3070 if (!hsotg
->dedicated_fifos
)
3072 size
= (dwc2_readl(hsotg
->regs
+ DTXFSTS(ep
->fifo_index
)) & 0xffff) * 4;
3073 if (size
< ep
->fifo_size
)
3074 dwc2_hsotg_txfifo_flush(hsotg
, ep
->fifo_index
);
3078 * dwc2_hsotg_disconnect - disconnect service
3079 * @hsotg: The device state.
3081 * The device has been disconnected. Remove all current
3082 * transactions and signal the gadget driver that this
3085 void dwc2_hsotg_disconnect(struct dwc2_hsotg
*hsotg
)
3089 if (!hsotg
->connected
)
3092 hsotg
->connected
= 0;
3093 hsotg
->test_mode
= 0;
3095 for (ep
= 0; ep
< hsotg
->num_of_eps
; ep
++) {
3096 if (hsotg
->eps_in
[ep
])
3097 kill_all_requests(hsotg
, hsotg
->eps_in
[ep
],
3099 if (hsotg
->eps_out
[ep
])
3100 kill_all_requests(hsotg
, hsotg
->eps_out
[ep
],
3104 call_gadget(hsotg
, disconnect
);
3105 hsotg
->lx_state
= DWC2_L3
;
3109 * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
3110 * @hsotg: The device state:
3111 * @periodic: True if this is a periodic FIFO interrupt
3113 static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg
*hsotg
, bool periodic
)
3115 struct dwc2_hsotg_ep
*ep
;
3118 /* look through for any more data to transmit */
3119 for (epno
= 0; epno
< hsotg
->num_of_eps
; epno
++) {
3120 ep
= index_to_ep(hsotg
, epno
, 1);
3128 if ((periodic
&& !ep
->periodic
) ||
3129 (!periodic
&& ep
->periodic
))
3132 ret
= dwc2_hsotg_trytx(hsotg
, ep
);
3138 /* IRQ flags which will trigger a retry around the IRQ loop */
3139 #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
3144 * dwc2_hsotg_core_init - issue softreset to the core
3145 * @hsotg: The device state
3147 * Issue a soft reset to the core, and await the core finishing it.
3149 void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg
*hsotg
,
3157 /* Kill any ep0 requests as controller will be reinitialized */
3158 kill_all_requests(hsotg
, hsotg
->eps_out
[0], -ECONNRESET
);
3161 if (dwc2_core_reset(hsotg
))
3165 * we must now enable ep0 ready for host detection and then
3166 * set configuration.
3169 /* keep other bits untouched (so e.g. forced modes are not lost) */
3170 usbcfg
= dwc2_readl(hsotg
->regs
+ GUSBCFG
);
3171 usbcfg
&= ~(GUSBCFG_TOUTCAL_MASK
| GUSBCFG_PHYIF16
| GUSBCFG_SRPCAP
|
3174 if (hsotg
->params
.phy_type
== DWC2_PHY_TYPE_PARAM_FS
&&
3175 (hsotg
->params
.speed
== DWC2_SPEED_PARAM_FULL
||
3176 hsotg
->params
.speed
== DWC2_SPEED_PARAM_LOW
)) {
3177 /* FS/LS Dedicated Transceiver Interface */
3178 usbcfg
|= GUSBCFG_PHYSEL
;
3180 /* set the PLL on, remove the HNP/SRP and set the PHY */
3181 val
= (hsotg
->phyif
== GUSBCFG_PHYIF8
) ? 9 : 5;
3182 usbcfg
|= hsotg
->phyif
| GUSBCFG_TOUTCAL(7) |
3183 (val
<< GUSBCFG_USBTRDTIM_SHIFT
);
3185 dwc2_writel(usbcfg
, hsotg
->regs
+ GUSBCFG
);
3187 dwc2_hsotg_init_fifo(hsotg
);
3190 __orr32(hsotg
->regs
+ DCTL
, DCTL_SFTDISCON
);
3192 dcfg
|= DCFG_EPMISCNT(1);
3194 switch (hsotg
->params
.speed
) {
3195 case DWC2_SPEED_PARAM_LOW
:
3196 dcfg
|= DCFG_DEVSPD_LS
;
3198 case DWC2_SPEED_PARAM_FULL
:
3199 if (hsotg
->params
.phy_type
== DWC2_PHY_TYPE_PARAM_FS
)
3200 dcfg
|= DCFG_DEVSPD_FS48
;
3202 dcfg
|= DCFG_DEVSPD_FS
;
3205 dcfg
|= DCFG_DEVSPD_HS
;
3208 dwc2_writel(dcfg
, hsotg
->regs
+ DCFG
);
3210 /* Clear any pending OTG interrupts */
3211 dwc2_writel(0xffffffff, hsotg
->regs
+ GOTGINT
);
3213 /* Clear any pending interrupts */
3214 dwc2_writel(0xffffffff, hsotg
->regs
+ GINTSTS
);
3215 intmsk
= GINTSTS_ERLYSUSP
| GINTSTS_SESSREQINT
|
3216 GINTSTS_GOUTNAKEFF
| GINTSTS_GINNAKEFF
|
3217 GINTSTS_USBRST
| GINTSTS_RESETDET
|
3218 GINTSTS_ENUMDONE
| GINTSTS_OTGINT
|
3219 GINTSTS_USBSUSP
| GINTSTS_WKUPINT
;
3221 if (!using_desc_dma(hsotg
))
3222 intmsk
|= GINTSTS_INCOMPL_SOIN
| GINTSTS_INCOMPL_SOOUT
;
3224 if (hsotg
->params
.external_id_pin_ctl
<= 0)
3225 intmsk
|= GINTSTS_CONIDSTSCHNG
;
3227 dwc2_writel(intmsk
, hsotg
->regs
+ GINTMSK
);
3229 if (using_dma(hsotg
)) {
3230 dwc2_writel(GAHBCFG_GLBL_INTR_EN
| GAHBCFG_DMA_EN
|
3231 (GAHBCFG_HBSTLEN_INCR4
<< GAHBCFG_HBSTLEN_SHIFT
),
3232 hsotg
->regs
+ GAHBCFG
);
3234 /* Set DDMA mode support in the core if needed */
3235 if (using_desc_dma(hsotg
))
3236 __orr32(hsotg
->regs
+ DCFG
, DCFG_DESCDMA_EN
);
3239 dwc2_writel(((hsotg
->dedicated_fifos
) ?
3240 (GAHBCFG_NP_TXF_EMP_LVL
|
3241 GAHBCFG_P_TXF_EMP_LVL
) : 0) |
3242 GAHBCFG_GLBL_INTR_EN
, hsotg
->regs
+ GAHBCFG
);
3246 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
3247 * when we have no data to transfer. Otherwise we get being flooded by
3251 dwc2_writel(((hsotg
->dedicated_fifos
&& !using_dma(hsotg
)) ?
3252 DIEPMSK_TXFIFOEMPTY
| DIEPMSK_INTKNTXFEMPMSK
: 0) |
3253 DIEPMSK_EPDISBLDMSK
| DIEPMSK_XFERCOMPLMSK
|
3254 DIEPMSK_TIMEOUTMSK
| DIEPMSK_AHBERRMSK
,
3255 hsotg
->regs
+ DIEPMSK
);
3258 * don't need XferCompl, we get that from RXFIFO in slave mode. In
3259 * DMA mode we may need this and StsPhseRcvd.
3261 dwc2_writel((using_dma(hsotg
) ? (DIEPMSK_XFERCOMPLMSK
|
3262 DOEPMSK_STSPHSERCVDMSK
) : 0) |
3263 DOEPMSK_EPDISBLDMSK
| DOEPMSK_AHBERRMSK
|
3265 hsotg
->regs
+ DOEPMSK
);
3267 /* Enable BNA interrupt for DDMA */
3268 if (using_desc_dma(hsotg
))
3269 __orr32(hsotg
->regs
+ DOEPMSK
, DOEPMSK_BNAMSK
);
3271 dwc2_writel(0, hsotg
->regs
+ DAINTMSK
);
3273 dev_dbg(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3274 dwc2_readl(hsotg
->regs
+ DIEPCTL0
),
3275 dwc2_readl(hsotg
->regs
+ DOEPCTL0
));
3277 /* enable in and out endpoint interrupts */
3278 dwc2_hsotg_en_gsint(hsotg
, GINTSTS_OEPINT
| GINTSTS_IEPINT
);
3281 * Enable the RXFIFO when in slave mode, as this is how we collect
3282 * the data. In DMA mode, we get events from the FIFO but also
3283 * things we cannot process, so do not use it.
3285 if (!using_dma(hsotg
))
3286 dwc2_hsotg_en_gsint(hsotg
, GINTSTS_RXFLVL
);
3288 /* Enable interrupts for EP0 in and out */
3289 dwc2_hsotg_ctrl_epint(hsotg
, 0, 0, 1);
3290 dwc2_hsotg_ctrl_epint(hsotg
, 0, 1, 1);
3292 if (!is_usb_reset
) {
3293 __orr32(hsotg
->regs
+ DCTL
, DCTL_PWRONPRGDONE
);
3294 udelay(10); /* see openiboot */
3295 __bic32(hsotg
->regs
+ DCTL
, DCTL_PWRONPRGDONE
);
3298 dev_dbg(hsotg
->dev
, "DCTL=0x%08x\n", dwc2_readl(hsotg
->regs
+ DCTL
));
3301 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
3302 * writing to the EPCTL register..
3305 /* set to read 1 8byte packet */
3306 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
3307 DXEPTSIZ_XFERSIZE(8), hsotg
->regs
+ DOEPTSIZ0
);
3309 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg
->eps_out
[0]->ep
.maxpacket
) |
3310 DXEPCTL_CNAK
| DXEPCTL_EPENA
|
3312 hsotg
->regs
+ DOEPCTL0
);
3314 /* enable, but don't activate EP0in */
3315 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg
->eps_out
[0]->ep
.maxpacket
) |
3316 DXEPCTL_USBACTEP
, hsotg
->regs
+ DIEPCTL0
);
3318 dwc2_hsotg_enqueue_setup(hsotg
);
3320 dev_dbg(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
3321 dwc2_readl(hsotg
->regs
+ DIEPCTL0
),
3322 dwc2_readl(hsotg
->regs
+ DOEPCTL0
));
3324 /* clear global NAKs */
3325 val
= DCTL_CGOUTNAK
| DCTL_CGNPINNAK
;
3327 val
|= DCTL_SFTDISCON
;
3328 __orr32(hsotg
->regs
+ DCTL
, val
);
3330 /* must be at-least 3ms to allow bus to see disconnect */
3333 hsotg
->lx_state
= DWC2_L0
;
3336 static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg
*hsotg
)
3338 /* set the soft-disconnect bit */
3339 __orr32(hsotg
->regs
+ DCTL
, DCTL_SFTDISCON
);
3342 void dwc2_hsotg_core_connect(struct dwc2_hsotg
*hsotg
)
3344 /* remove the soft-disconnect and let's go */
3345 __bic32(hsotg
->regs
+ DCTL
, DCTL_SFTDISCON
);
3349 * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt.
3350 * @hsotg: The device state:
3352 * This interrupt indicates one of the following conditions occurred while
3353 * transmitting an ISOC transaction.
3354 * - Corrupted IN Token for ISOC EP.
3355 * - Packet not complete in FIFO.
3357 * The following actions will be taken:
3358 * - Determine the EP
3359 * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO
3361 static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg
*hsotg
)
3363 struct dwc2_hsotg_ep
*hs_ep
;
3367 dev_dbg(hsotg
->dev
, "Incomplete isoc in interrupt received:\n");
3369 for (idx
= 1; idx
<= hsotg
->num_of_eps
; idx
++) {
3370 hs_ep
= hsotg
->eps_in
[idx
];
3371 epctrl
= dwc2_readl(hsotg
->regs
+ DIEPCTL(idx
));
3372 if ((epctrl
& DXEPCTL_EPENA
) && hs_ep
->isochronous
&&
3373 dwc2_gadget_target_frame_elapsed(hs_ep
)) {
3374 epctrl
|= DXEPCTL_SNAK
;
3375 epctrl
|= DXEPCTL_EPDIS
;
3376 dwc2_writel(epctrl
, hsotg
->regs
+ DIEPCTL(idx
));
3380 /* Clear interrupt */
3381 dwc2_writel(GINTSTS_INCOMPL_SOIN
, hsotg
->regs
+ GINTSTS
);
3385 * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt
3386 * @hsotg: The device state:
3388 * This interrupt indicates one of the following conditions occurred while
3389 * transmitting an ISOC transaction.
3390 * - Corrupted OUT Token for ISOC EP.
3391 * - Packet not complete in FIFO.
3393 * The following actions will be taken:
3394 * - Determine the EP
3395 * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed.
3397 static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg
*hsotg
)
3402 struct dwc2_hsotg_ep
*hs_ep
;
3405 dev_dbg(hsotg
->dev
, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__
);
3407 for (idx
= 1; idx
<= hsotg
->num_of_eps
; idx
++) {
3408 hs_ep
= hsotg
->eps_out
[idx
];
3409 epctrl
= dwc2_readl(hsotg
->regs
+ DOEPCTL(idx
));
3410 if ((epctrl
& DXEPCTL_EPENA
) && hs_ep
->isochronous
&&
3411 dwc2_gadget_target_frame_elapsed(hs_ep
)) {
3412 /* Unmask GOUTNAKEFF interrupt */
3413 gintmsk
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
3414 gintmsk
|= GINTSTS_GOUTNAKEFF
;
3415 dwc2_writel(gintmsk
, hsotg
->regs
+ GINTMSK
);
3417 gintsts
= dwc2_readl(hsotg
->regs
+ GINTSTS
);
3418 if (!(gintsts
& GINTSTS_GOUTNAKEFF
))
3419 __orr32(hsotg
->regs
+ DCTL
, DCTL_SGOUTNAK
);
3423 /* Clear interrupt */
3424 dwc2_writel(GINTSTS_INCOMPL_SOOUT
, hsotg
->regs
+ GINTSTS
);
3428 * dwc2_hsotg_irq - handle device interrupt
3429 * @irq: The IRQ number triggered
3430 * @pw: The pw value when registered the handler.
3432 static irqreturn_t
dwc2_hsotg_irq(int irq
, void *pw
)
3434 struct dwc2_hsotg
*hsotg
= pw
;
3435 int retry_count
= 8;
3439 if (!dwc2_is_device_mode(hsotg
))
3442 spin_lock(&hsotg
->lock
);
3444 gintsts
= dwc2_readl(hsotg
->regs
+ GINTSTS
);
3445 gintmsk
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
3447 dev_dbg(hsotg
->dev
, "%s: %08x %08x (%08x) retry %d\n",
3448 __func__
, gintsts
, gintsts
& gintmsk
, gintmsk
, retry_count
);
3452 if (gintsts
& GINTSTS_RESETDET
) {
3453 dev_dbg(hsotg
->dev
, "%s: USBRstDet\n", __func__
);
3455 dwc2_writel(GINTSTS_RESETDET
, hsotg
->regs
+ GINTSTS
);
3457 /* This event must be used only if controller is suspended */
3458 if (hsotg
->lx_state
== DWC2_L2
) {
3459 dwc2_exit_hibernation(hsotg
, true);
3460 hsotg
->lx_state
= DWC2_L0
;
3464 if (gintsts
& (GINTSTS_USBRST
| GINTSTS_RESETDET
)) {
3466 u32 usb_status
= dwc2_readl(hsotg
->regs
+ GOTGCTL
);
3467 u32 connected
= hsotg
->connected
;
3469 dev_dbg(hsotg
->dev
, "%s: USBRst\n", __func__
);
3470 dev_dbg(hsotg
->dev
, "GNPTXSTS=%08x\n",
3471 dwc2_readl(hsotg
->regs
+ GNPTXSTS
));
3473 dwc2_writel(GINTSTS_USBRST
, hsotg
->regs
+ GINTSTS
);
3475 /* Report disconnection if it is not already done. */
3476 dwc2_hsotg_disconnect(hsotg
);
3478 if (usb_status
& GOTGCTL_BSESVLD
&& connected
)
3479 dwc2_hsotg_core_init_disconnected(hsotg
, true);
3482 if (gintsts
& GINTSTS_ENUMDONE
) {
3483 dwc2_writel(GINTSTS_ENUMDONE
, hsotg
->regs
+ GINTSTS
);
3485 dwc2_hsotg_irq_enumdone(hsotg
);
3488 if (gintsts
& (GINTSTS_OEPINT
| GINTSTS_IEPINT
)) {
3489 u32 daint
= dwc2_readl(hsotg
->regs
+ DAINT
);
3490 u32 daintmsk
= dwc2_readl(hsotg
->regs
+ DAINTMSK
);
3491 u32 daint_out
, daint_in
;
3495 daint_out
= daint
>> DAINT_OUTEP_SHIFT
;
3496 daint_in
= daint
& ~(daint_out
<< DAINT_OUTEP_SHIFT
);
3498 dev_dbg(hsotg
->dev
, "%s: daint=%08x\n", __func__
, daint
);
3500 for (ep
= 0; ep
< hsotg
->num_of_eps
&& daint_out
;
3501 ep
++, daint_out
>>= 1) {
3503 dwc2_hsotg_epint(hsotg
, ep
, 0);
3506 for (ep
= 0; ep
< hsotg
->num_of_eps
&& daint_in
;
3507 ep
++, daint_in
>>= 1) {
3509 dwc2_hsotg_epint(hsotg
, ep
, 1);
3513 /* check both FIFOs */
3515 if (gintsts
& GINTSTS_NPTXFEMP
) {
3516 dev_dbg(hsotg
->dev
, "NPTxFEmp\n");
3519 * Disable the interrupt to stop it happening again
3520 * unless one of these endpoint routines decides that
3521 * it needs re-enabling
3524 dwc2_hsotg_disable_gsint(hsotg
, GINTSTS_NPTXFEMP
);
3525 dwc2_hsotg_irq_fifoempty(hsotg
, false);
3528 if (gintsts
& GINTSTS_PTXFEMP
) {
3529 dev_dbg(hsotg
->dev
, "PTxFEmp\n");
3531 /* See note in GINTSTS_NPTxFEmp */
3533 dwc2_hsotg_disable_gsint(hsotg
, GINTSTS_PTXFEMP
);
3534 dwc2_hsotg_irq_fifoempty(hsotg
, true);
3537 if (gintsts
& GINTSTS_RXFLVL
) {
3539 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
3540 * we need to retry dwc2_hsotg_handle_rx if this is still
3544 dwc2_hsotg_handle_rx(hsotg
);
3547 if (gintsts
& GINTSTS_ERLYSUSP
) {
3548 dev_dbg(hsotg
->dev
, "GINTSTS_ErlySusp\n");
3549 dwc2_writel(GINTSTS_ERLYSUSP
, hsotg
->regs
+ GINTSTS
);
3553 * these next two seem to crop-up occasionally causing the core
3554 * to shutdown the USB transfer, so try clearing them and logging
3558 if (gintsts
& GINTSTS_GOUTNAKEFF
) {
3562 struct dwc2_hsotg_ep
*hs_ep
;
3564 /* Mask this interrupt */
3565 gintmsk
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
3566 gintmsk
&= ~GINTSTS_GOUTNAKEFF
;
3567 dwc2_writel(gintmsk
, hsotg
->regs
+ GINTMSK
);
3569 dev_dbg(hsotg
->dev
, "GOUTNakEff triggered\n");
3570 for (idx
= 1; idx
<= hsotg
->num_of_eps
; idx
++) {
3571 hs_ep
= hsotg
->eps_out
[idx
];
3572 epctrl
= dwc2_readl(hsotg
->regs
+ DOEPCTL(idx
));
3574 if ((epctrl
& DXEPCTL_EPENA
) && hs_ep
->isochronous
) {
3575 epctrl
|= DXEPCTL_SNAK
;
3576 epctrl
|= DXEPCTL_EPDIS
;
3577 dwc2_writel(epctrl
, hsotg
->regs
+ DOEPCTL(idx
));
3581 /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */
3584 if (gintsts
& GINTSTS_GINNAKEFF
) {
3585 dev_info(hsotg
->dev
, "GINNakEff triggered\n");
3587 __orr32(hsotg
->regs
+ DCTL
, DCTL_CGNPINNAK
);
3589 dwc2_hsotg_dump(hsotg
);
3592 if (gintsts
& GINTSTS_INCOMPL_SOIN
)
3593 dwc2_gadget_handle_incomplete_isoc_in(hsotg
);
3595 if (gintsts
& GINTSTS_INCOMPL_SOOUT
)
3596 dwc2_gadget_handle_incomplete_isoc_out(hsotg
);
3599 * if we've had fifo events, we should try and go around the
3600 * loop again to see if there's any point in returning yet.
3603 if (gintsts
& IRQ_RETRY_MASK
&& --retry_count
> 0)
3606 spin_unlock(&hsotg
->lock
);
3611 static int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg
*hs_otg
, u32 reg
,
3612 u32 bit
, u32 timeout
)
3616 for (i
= 0; i
< timeout
; i
++) {
3617 if (dwc2_readl(hs_otg
->regs
+ reg
) & bit
)
3625 static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg
*hsotg
,
3626 struct dwc2_hsotg_ep
*hs_ep
)
3631 epctrl_reg
= hs_ep
->dir_in
? DIEPCTL(hs_ep
->index
) :
3632 DOEPCTL(hs_ep
->index
);
3633 epint_reg
= hs_ep
->dir_in
? DIEPINT(hs_ep
->index
) :
3634 DOEPINT(hs_ep
->index
);
3636 dev_dbg(hsotg
->dev
, "%s: stopping transfer on %s\n", __func__
,
3639 if (hs_ep
->dir_in
) {
3640 if (hsotg
->dedicated_fifos
|| hs_ep
->periodic
) {
3641 __orr32(hsotg
->regs
+ epctrl_reg
, DXEPCTL_SNAK
);
3642 /* Wait for Nak effect */
3643 if (dwc2_hsotg_wait_bit_set(hsotg
, epint_reg
,
3644 DXEPINT_INEPNAKEFF
, 100))
3645 dev_warn(hsotg
->dev
,
3646 "%s: timeout DIEPINT.NAKEFF\n",
3649 __orr32(hsotg
->regs
+ DCTL
, DCTL_SGNPINNAK
);
3650 /* Wait for Nak effect */
3651 if (dwc2_hsotg_wait_bit_set(hsotg
, GINTSTS
,
3652 GINTSTS_GINNAKEFF
, 100))
3653 dev_warn(hsotg
->dev
,
3654 "%s: timeout GINTSTS.GINNAKEFF\n",
3658 if (!(dwc2_readl(hsotg
->regs
+ GINTSTS
) & GINTSTS_GOUTNAKEFF
))
3659 __orr32(hsotg
->regs
+ DCTL
, DCTL_SGOUTNAK
);
3661 /* Wait for global nak to take effect */
3662 if (dwc2_hsotg_wait_bit_set(hsotg
, GINTSTS
,
3663 GINTSTS_GOUTNAKEFF
, 100))
3664 dev_warn(hsotg
->dev
, "%s: timeout GINTSTS.GOUTNAKEFF\n",
3669 __orr32(hsotg
->regs
+ epctrl_reg
, DXEPCTL_EPDIS
| DXEPCTL_SNAK
);
3671 /* Wait for ep to be disabled */
3672 if (dwc2_hsotg_wait_bit_set(hsotg
, epint_reg
, DXEPINT_EPDISBLD
, 100))
3673 dev_warn(hsotg
->dev
,
3674 "%s: timeout DOEPCTL.EPDisable\n", __func__
);
3676 /* Clear EPDISBLD interrupt */
3677 __orr32(hsotg
->regs
+ epint_reg
, DXEPINT_EPDISBLD
);
3679 if (hs_ep
->dir_in
) {
3680 unsigned short fifo_index
;
3682 if (hsotg
->dedicated_fifos
|| hs_ep
->periodic
)
3683 fifo_index
= hs_ep
->fifo_index
;
3688 dwc2_flush_tx_fifo(hsotg
, fifo_index
);
3690 /* Clear Global In NP NAK in Shared FIFO for non periodic ep */
3691 if (!hsotg
->dedicated_fifos
&& !hs_ep
->periodic
)
3692 __orr32(hsotg
->regs
+ DCTL
, DCTL_CGNPINNAK
);
3695 /* Remove global NAKs */
3696 __orr32(hsotg
->regs
+ DCTL
, DCTL_CGOUTNAK
);
3701 * dwc2_hsotg_ep_enable - enable the given endpoint
3702 * @ep: The USB endpint to configure
3703 * @desc: The USB endpoint descriptor to configure with.
3705 * This is called from the USB gadget code's usb_ep_enable().
3707 static int dwc2_hsotg_ep_enable(struct usb_ep
*ep
,
3708 const struct usb_endpoint_descriptor
*desc
)
3710 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
3711 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
3712 unsigned long flags
;
3713 unsigned int index
= hs_ep
->index
;
3719 unsigned int dir_in
;
3720 unsigned int i
, val
, size
;
3724 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
3725 __func__
, ep
->name
, desc
->bEndpointAddress
, desc
->bmAttributes
,
3726 desc
->wMaxPacketSize
, desc
->bInterval
);
3728 /* not to be called for EP0 */
3730 dev_err(hsotg
->dev
, "%s: called for EP 0\n", __func__
);
3734 dir_in
= (desc
->bEndpointAddress
& USB_ENDPOINT_DIR_MASK
) ? 1 : 0;
3735 if (dir_in
!= hs_ep
->dir_in
) {
3736 dev_err(hsotg
->dev
, "%s: direction mismatch!\n", __func__
);
3740 mps
= usb_endpoint_maxp(desc
);
3741 mc
= usb_endpoint_maxp_mult(desc
);
3743 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
3745 epctrl_reg
= dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
3746 epctrl
= dwc2_readl(hsotg
->regs
+ epctrl_reg
);
3748 dev_dbg(hsotg
->dev
, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
3749 __func__
, epctrl
, epctrl_reg
);
3751 /* Allocate DMA descriptor chain for non-ctrl endpoints */
3752 if (using_desc_dma(hsotg
)) {
3753 hs_ep
->desc_list
= dma_alloc_coherent(hsotg
->dev
,
3754 MAX_DMA_DESC_NUM_GENERIC
*
3755 sizeof(struct dwc2_dma_desc
),
3756 &hs_ep
->desc_list_dma
, GFP_KERNEL
);
3757 if (!hs_ep
->desc_list
) {
3763 spin_lock_irqsave(&hsotg
->lock
, flags
);
3765 epctrl
&= ~(DXEPCTL_EPTYPE_MASK
| DXEPCTL_MPS_MASK
);
3766 epctrl
|= DXEPCTL_MPS(mps
);
3769 * mark the endpoint as active, otherwise the core may ignore
3770 * transactions entirely for this endpoint
3772 epctrl
|= DXEPCTL_USBACTEP
;
3774 /* update the endpoint state */
3775 dwc2_hsotg_set_ep_maxpacket(hsotg
, hs_ep
->index
, mps
, mc
, dir_in
);
3777 /* default, set to non-periodic */
3778 hs_ep
->isochronous
= 0;
3779 hs_ep
->periodic
= 0;
3781 hs_ep
->interval
= desc
->bInterval
;
3783 switch (desc
->bmAttributes
& USB_ENDPOINT_XFERTYPE_MASK
) {
3784 case USB_ENDPOINT_XFER_ISOC
:
3785 epctrl
|= DXEPCTL_EPTYPE_ISO
;
3786 epctrl
|= DXEPCTL_SETEVENFR
;
3787 hs_ep
->isochronous
= 1;
3788 hs_ep
->interval
= 1 << (desc
->bInterval
- 1);
3789 hs_ep
->target_frame
= TARGET_FRAME_INITIAL
;
3790 hs_ep
->isoc_chain_num
= 0;
3791 hs_ep
->next_desc
= 0;
3793 hs_ep
->periodic
= 1;
3794 mask
= dwc2_readl(hsotg
->regs
+ DIEPMSK
);
3795 mask
|= DIEPMSK_NAKMSK
;
3796 dwc2_writel(mask
, hsotg
->regs
+ DIEPMSK
);
3798 mask
= dwc2_readl(hsotg
->regs
+ DOEPMSK
);
3799 mask
|= DOEPMSK_OUTTKNEPDISMSK
;
3800 dwc2_writel(mask
, hsotg
->regs
+ DOEPMSK
);
3804 case USB_ENDPOINT_XFER_BULK
:
3805 epctrl
|= DXEPCTL_EPTYPE_BULK
;
3808 case USB_ENDPOINT_XFER_INT
:
3810 hs_ep
->periodic
= 1;
3812 if (hsotg
->gadget
.speed
== USB_SPEED_HIGH
)
3813 hs_ep
->interval
= 1 << (desc
->bInterval
- 1);
3815 epctrl
|= DXEPCTL_EPTYPE_INTERRUPT
;
3818 case USB_ENDPOINT_XFER_CONTROL
:
3819 epctrl
|= DXEPCTL_EPTYPE_CONTROL
;
3824 * if the hardware has dedicated fifos, we must give each IN EP
3825 * a unique tx-fifo even if it is non-periodic.
3827 if (dir_in
&& hsotg
->dedicated_fifos
) {
3829 u32 fifo_size
= UINT_MAX
;
3830 size
= hs_ep
->ep
.maxpacket
*hs_ep
->mc
;
3831 for (i
= 1; i
< hsotg
->num_of_eps
; ++i
) {
3832 if (hsotg
->fifo_map
& (1<<i
))
3834 val
= dwc2_readl(hsotg
->regs
+ DPTXFSIZN(i
));
3835 val
= (val
>> FIFOSIZE_DEPTH_SHIFT
)*4;
3838 /* Search for smallest acceptable fifo */
3839 if (val
< fifo_size
) {
3846 "%s: No suitable fifo found\n", __func__
);
3850 hsotg
->fifo_map
|= 1 << fifo_index
;
3851 epctrl
|= DXEPCTL_TXFNUM(fifo_index
);
3852 hs_ep
->fifo_index
= fifo_index
;
3853 hs_ep
->fifo_size
= fifo_size
;
3856 /* for non control endpoints, set PID to D0 */
3857 if (index
&& !hs_ep
->isochronous
)
3858 epctrl
|= DXEPCTL_SETD0PID
;
3860 dev_dbg(hsotg
->dev
, "%s: write DxEPCTL=0x%08x\n",
3863 dwc2_writel(epctrl
, hsotg
->regs
+ epctrl_reg
);
3864 dev_dbg(hsotg
->dev
, "%s: read DxEPCTL=0x%08x\n",
3865 __func__
, dwc2_readl(hsotg
->regs
+ epctrl_reg
));
3867 /* enable the endpoint interrupt */
3868 dwc2_hsotg_ctrl_epint(hsotg
, index
, dir_in
, 1);
3871 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3874 if (ret
&& using_desc_dma(hsotg
) && hs_ep
->desc_list
) {
3875 dma_free_coherent(hsotg
->dev
, MAX_DMA_DESC_NUM_GENERIC
*
3876 sizeof(struct dwc2_dma_desc
),
3877 hs_ep
->desc_list
, hs_ep
->desc_list_dma
);
3878 hs_ep
->desc_list
= NULL
;
3885 * dwc2_hsotg_ep_disable - disable given endpoint
3886 * @ep: The endpoint to disable.
3888 static int dwc2_hsotg_ep_disable(struct usb_ep
*ep
)
3890 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
3891 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
3892 int dir_in
= hs_ep
->dir_in
;
3893 int index
= hs_ep
->index
;
3894 unsigned long flags
;
3898 dev_dbg(hsotg
->dev
, "%s(ep %p)\n", __func__
, ep
);
3900 if (ep
== &hsotg
->eps_out
[0]->ep
) {
3901 dev_err(hsotg
->dev
, "%s: called for ep0\n", __func__
);
3905 /* Remove DMA memory allocated for non-control Endpoints */
3906 if (using_desc_dma(hsotg
)) {
3907 dma_free_coherent(hsotg
->dev
, MAX_DMA_DESC_NUM_GENERIC
*
3908 sizeof(struct dwc2_dma_desc
),
3909 hs_ep
->desc_list
, hs_ep
->desc_list_dma
);
3910 hs_ep
->desc_list
= NULL
;
3913 epctrl_reg
= dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
3915 spin_lock_irqsave(&hsotg
->lock
, flags
);
3917 ctrl
= dwc2_readl(hsotg
->regs
+ epctrl_reg
);
3919 if (ctrl
& DXEPCTL_EPENA
)
3920 dwc2_hsotg_ep_stop_xfr(hsotg
, hs_ep
);
3922 ctrl
&= ~DXEPCTL_EPENA
;
3923 ctrl
&= ~DXEPCTL_USBACTEP
;
3924 ctrl
|= DXEPCTL_SNAK
;
3926 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x\n", __func__
, ctrl
);
3927 dwc2_writel(ctrl
, hsotg
->regs
+ epctrl_reg
);
3929 /* disable endpoint interrupts */
3930 dwc2_hsotg_ctrl_epint(hsotg
, hs_ep
->index
, hs_ep
->dir_in
, 0);
3932 /* terminate all requests with shutdown */
3933 kill_all_requests(hsotg
, hs_ep
, -ESHUTDOWN
);
3935 hsotg
->fifo_map
&= ~(1 << hs_ep
->fifo_index
);
3936 hs_ep
->fifo_index
= 0;
3937 hs_ep
->fifo_size
= 0;
3939 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3944 * on_list - check request is on the given endpoint
3945 * @ep: The endpoint to check.
3946 * @test: The request to test if it is on the endpoint.
3948 static bool on_list(struct dwc2_hsotg_ep
*ep
, struct dwc2_hsotg_req
*test
)
3950 struct dwc2_hsotg_req
*req
, *treq
;
3952 list_for_each_entry_safe(req
, treq
, &ep
->queue
, queue
) {
3961 * dwc2_hsotg_ep_dequeue - dequeue given endpoint
3962 * @ep: The endpoint to dequeue.
3963 * @req: The request to be removed from a queue.
3965 static int dwc2_hsotg_ep_dequeue(struct usb_ep
*ep
, struct usb_request
*req
)
3967 struct dwc2_hsotg_req
*hs_req
= our_req(req
);
3968 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
3969 struct dwc2_hsotg
*hs
= hs_ep
->parent
;
3970 unsigned long flags
;
3972 dev_dbg(hs
->dev
, "ep_dequeue(%p,%p)\n", ep
, req
);
3974 spin_lock_irqsave(&hs
->lock
, flags
);
3976 if (!on_list(hs_ep
, hs_req
)) {
3977 spin_unlock_irqrestore(&hs
->lock
, flags
);
3981 /* Dequeue already started request */
3982 if (req
== &hs_ep
->req
->req
)
3983 dwc2_hsotg_ep_stop_xfr(hs
, hs_ep
);
3985 dwc2_hsotg_complete_request(hs
, hs_ep
, hs_req
, -ECONNRESET
);
3986 spin_unlock_irqrestore(&hs
->lock
, flags
);
3992 * dwc2_hsotg_ep_sethalt - set halt on a given endpoint
3993 * @ep: The endpoint to set halt.
3994 * @value: Set or unset the halt.
3995 * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if
3996 * the endpoint is busy processing requests.
3998 * We need to stall the endpoint immediately if request comes from set_feature
3999 * protocol command handler.
4001 static int dwc2_hsotg_ep_sethalt(struct usb_ep
*ep
, int value
, bool now
)
4003 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
4004 struct dwc2_hsotg
*hs
= hs_ep
->parent
;
4005 int index
= hs_ep
->index
;
4010 dev_info(hs
->dev
, "%s(ep %p %s, %d)\n", __func__
, ep
, ep
->name
, value
);
4014 dwc2_hsotg_stall_ep0(hs
);
4017 "%s: can't clear halt on ep0\n", __func__
);
4021 if (hs_ep
->isochronous
) {
4022 dev_err(hs
->dev
, "%s is Isochronous Endpoint\n", ep
->name
);
4026 if (!now
&& value
&& !list_empty(&hs_ep
->queue
)) {
4027 dev_dbg(hs
->dev
, "%s request is pending, cannot halt\n",
4032 if (hs_ep
->dir_in
) {
4033 epreg
= DIEPCTL(index
);
4034 epctl
= dwc2_readl(hs
->regs
+ epreg
);
4037 epctl
|= DXEPCTL_STALL
| DXEPCTL_SNAK
;
4038 if (epctl
& DXEPCTL_EPENA
)
4039 epctl
|= DXEPCTL_EPDIS
;
4041 epctl
&= ~DXEPCTL_STALL
;
4042 xfertype
= epctl
& DXEPCTL_EPTYPE_MASK
;
4043 if (xfertype
== DXEPCTL_EPTYPE_BULK
||
4044 xfertype
== DXEPCTL_EPTYPE_INTERRUPT
)
4045 epctl
|= DXEPCTL_SETD0PID
;
4047 dwc2_writel(epctl
, hs
->regs
+ epreg
);
4050 epreg
= DOEPCTL(index
);
4051 epctl
= dwc2_readl(hs
->regs
+ epreg
);
4054 epctl
|= DXEPCTL_STALL
;
4056 epctl
&= ~DXEPCTL_STALL
;
4057 xfertype
= epctl
& DXEPCTL_EPTYPE_MASK
;
4058 if (xfertype
== DXEPCTL_EPTYPE_BULK
||
4059 xfertype
== DXEPCTL_EPTYPE_INTERRUPT
)
4060 epctl
|= DXEPCTL_SETD0PID
;
4062 dwc2_writel(epctl
, hs
->regs
+ epreg
);
4065 hs_ep
->halted
= value
;
4071 * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
4072 * @ep: The endpoint to set halt.
4073 * @value: Set or unset the halt.
4075 static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep
*ep
, int value
)
4077 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
4078 struct dwc2_hsotg
*hs
= hs_ep
->parent
;
4079 unsigned long flags
= 0;
4082 spin_lock_irqsave(&hs
->lock
, flags
);
4083 ret
= dwc2_hsotg_ep_sethalt(ep
, value
, false);
4084 spin_unlock_irqrestore(&hs
->lock
, flags
);
4089 static struct usb_ep_ops dwc2_hsotg_ep_ops
= {
4090 .enable
= dwc2_hsotg_ep_enable
,
4091 .disable
= dwc2_hsotg_ep_disable
,
4092 .alloc_request
= dwc2_hsotg_ep_alloc_request
,
4093 .free_request
= dwc2_hsotg_ep_free_request
,
4094 .queue
= dwc2_hsotg_ep_queue_lock
,
4095 .dequeue
= dwc2_hsotg_ep_dequeue
,
4096 .set_halt
= dwc2_hsotg_ep_sethalt_lock
,
4097 /* note, don't believe we have any call for the fifo routines */
4101 * dwc2_hsotg_init - initalize the usb core
4102 * @hsotg: The driver state
4104 static void dwc2_hsotg_init(struct dwc2_hsotg
*hsotg
)
4108 /* unmask subset of endpoint interrupts */
4110 dwc2_writel(DIEPMSK_TIMEOUTMSK
| DIEPMSK_AHBERRMSK
|
4111 DIEPMSK_EPDISBLDMSK
| DIEPMSK_XFERCOMPLMSK
,
4112 hsotg
->regs
+ DIEPMSK
);
4114 dwc2_writel(DOEPMSK_SETUPMSK
| DOEPMSK_AHBERRMSK
|
4115 DOEPMSK_EPDISBLDMSK
| DOEPMSK_XFERCOMPLMSK
,
4116 hsotg
->regs
+ DOEPMSK
);
4118 dwc2_writel(0, hsotg
->regs
+ DAINTMSK
);
4120 /* Be in disconnected state until gadget is registered */
4121 __orr32(hsotg
->regs
+ DCTL
, DCTL_SFTDISCON
);
4125 dev_dbg(hsotg
->dev
, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4126 dwc2_readl(hsotg
->regs
+ GRXFSIZ
),
4127 dwc2_readl(hsotg
->regs
+ GNPTXFSIZ
));
4129 dwc2_hsotg_init_fifo(hsotg
);
4131 /* keep other bits untouched (so e.g. forced modes are not lost) */
4132 usbcfg
= dwc2_readl(hsotg
->regs
+ GUSBCFG
);
4133 usbcfg
&= ~(GUSBCFG_TOUTCAL_MASK
| GUSBCFG_PHYIF16
| GUSBCFG_SRPCAP
|
4136 /* set the PLL on, remove the HNP/SRP and set the PHY */
4137 trdtim
= (hsotg
->phyif
== GUSBCFG_PHYIF8
) ? 9 : 5;
4138 usbcfg
|= hsotg
->phyif
| GUSBCFG_TOUTCAL(7) |
4139 (trdtim
<< GUSBCFG_USBTRDTIM_SHIFT
);
4140 dwc2_writel(usbcfg
, hsotg
->regs
+ GUSBCFG
);
4142 if (using_dma(hsotg
))
4143 __orr32(hsotg
->regs
+ GAHBCFG
, GAHBCFG_DMA_EN
);
4147 * dwc2_hsotg_udc_start - prepare the udc for work
4148 * @gadget: The usb gadget state
4149 * @driver: The usb gadget driver
4151 * Perform initialization to prepare udc device and driver
4154 static int dwc2_hsotg_udc_start(struct usb_gadget
*gadget
,
4155 struct usb_gadget_driver
*driver
)
4157 struct dwc2_hsotg
*hsotg
= to_hsotg(gadget
);
4158 unsigned long flags
;
4162 pr_err("%s: called with no device\n", __func__
);
4167 dev_err(hsotg
->dev
, "%s: no driver\n", __func__
);
4171 if (driver
->max_speed
< USB_SPEED_FULL
)
4172 dev_err(hsotg
->dev
, "%s: bad speed\n", __func__
);
4174 if (!driver
->setup
) {
4175 dev_err(hsotg
->dev
, "%s: missing entry points\n", __func__
);
4179 WARN_ON(hsotg
->driver
);
4181 driver
->driver
.bus
= NULL
;
4182 hsotg
->driver
= driver
;
4183 hsotg
->gadget
.dev
.of_node
= hsotg
->dev
->of_node
;
4184 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
4186 if (hsotg
->dr_mode
== USB_DR_MODE_PERIPHERAL
) {
4187 ret
= dwc2_lowlevel_hw_enable(hsotg
);
4192 if (!IS_ERR_OR_NULL(hsotg
->uphy
))
4193 otg_set_peripheral(hsotg
->uphy
->otg
, &hsotg
->gadget
);
4195 spin_lock_irqsave(&hsotg
->lock
, flags
);
4196 if (dwc2_hw_is_device(hsotg
)) {
4197 dwc2_hsotg_init(hsotg
);
4198 dwc2_hsotg_core_init_disconnected(hsotg
, false);
4202 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
4204 dev_info(hsotg
->dev
, "bound driver %s\n", driver
->driver
.name
);
4209 hsotg
->driver
= NULL
;
4214 * dwc2_hsotg_udc_stop - stop the udc
4215 * @gadget: The usb gadget state
4216 * @driver: The usb gadget driver
4218 * Stop udc hw block and stay tunned for future transmissions
4220 static int dwc2_hsotg_udc_stop(struct usb_gadget
*gadget
)
4222 struct dwc2_hsotg
*hsotg
= to_hsotg(gadget
);
4223 unsigned long flags
= 0;
4229 /* all endpoints should be shutdown */
4230 for (ep
= 1; ep
< hsotg
->num_of_eps
; ep
++) {
4231 if (hsotg
->eps_in
[ep
])
4232 dwc2_hsotg_ep_disable(&hsotg
->eps_in
[ep
]->ep
);
4233 if (hsotg
->eps_out
[ep
])
4234 dwc2_hsotg_ep_disable(&hsotg
->eps_out
[ep
]->ep
);
4237 spin_lock_irqsave(&hsotg
->lock
, flags
);
4239 hsotg
->driver
= NULL
;
4240 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
4243 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
4245 if (!IS_ERR_OR_NULL(hsotg
->uphy
))
4246 otg_set_peripheral(hsotg
->uphy
->otg
, NULL
);
4248 if (hsotg
->dr_mode
== USB_DR_MODE_PERIPHERAL
)
4249 dwc2_lowlevel_hw_disable(hsotg
);
4255 * dwc2_hsotg_gadget_getframe - read the frame number
4256 * @gadget: The usb gadget state
4258 * Read the {micro} frame number
4260 static int dwc2_hsotg_gadget_getframe(struct usb_gadget
*gadget
)
4262 return dwc2_hsotg_read_frameno(to_hsotg(gadget
));
4266 * dwc2_hsotg_pullup - connect/disconnect the USB PHY
4267 * @gadget: The usb gadget state
4268 * @is_on: Current state of the USB PHY
4270 * Connect/Disconnect the USB PHY pullup
4272 static int dwc2_hsotg_pullup(struct usb_gadget
*gadget
, int is_on
)
4274 struct dwc2_hsotg
*hsotg
= to_hsotg(gadget
);
4275 unsigned long flags
= 0;
4277 dev_dbg(hsotg
->dev
, "%s: is_on: %d op_state: %d\n", __func__
, is_on
,
4280 /* Don't modify pullup state while in host mode */
4281 if (hsotg
->op_state
!= OTG_STATE_B_PERIPHERAL
) {
4282 hsotg
->enabled
= is_on
;
4286 spin_lock_irqsave(&hsotg
->lock
, flags
);
4289 dwc2_hsotg_core_init_disconnected(hsotg
, false);
4290 dwc2_hsotg_core_connect(hsotg
);
4292 dwc2_hsotg_core_disconnect(hsotg
);
4293 dwc2_hsotg_disconnect(hsotg
);
4297 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
4298 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
4303 static int dwc2_hsotg_vbus_session(struct usb_gadget
*gadget
, int is_active
)
4305 struct dwc2_hsotg
*hsotg
= to_hsotg(gadget
);
4306 unsigned long flags
;
4308 dev_dbg(hsotg
->dev
, "%s: is_active: %d\n", __func__
, is_active
);
4309 spin_lock_irqsave(&hsotg
->lock
, flags
);
4312 * If controller is hibernated, it must exit from hibernation
4313 * before being initialized / de-initialized
4315 if (hsotg
->lx_state
== DWC2_L2
)
4316 dwc2_exit_hibernation(hsotg
, false);
4319 hsotg
->op_state
= OTG_STATE_B_PERIPHERAL
;
4321 dwc2_hsotg_core_init_disconnected(hsotg
, false);
4323 dwc2_hsotg_core_connect(hsotg
);
4325 dwc2_hsotg_core_disconnect(hsotg
);
4326 dwc2_hsotg_disconnect(hsotg
);
4329 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
4334 * dwc2_hsotg_vbus_draw - report bMaxPower field
4335 * @gadget: The usb gadget state
4336 * @mA: Amount of current
4338 * Report how much power the device may consume to the phy.
4340 static int dwc2_hsotg_vbus_draw(struct usb_gadget
*gadget
, unsigned mA
)
4342 struct dwc2_hsotg
*hsotg
= to_hsotg(gadget
);
4344 if (IS_ERR_OR_NULL(hsotg
->uphy
))
4346 return usb_phy_set_power(hsotg
->uphy
, mA
);
4349 static const struct usb_gadget_ops dwc2_hsotg_gadget_ops
= {
4350 .get_frame
= dwc2_hsotg_gadget_getframe
,
4351 .udc_start
= dwc2_hsotg_udc_start
,
4352 .udc_stop
= dwc2_hsotg_udc_stop
,
4353 .pullup
= dwc2_hsotg_pullup
,
4354 .vbus_session
= dwc2_hsotg_vbus_session
,
4355 .vbus_draw
= dwc2_hsotg_vbus_draw
,
4359 * dwc2_hsotg_initep - initialise a single endpoint
4360 * @hsotg: The device state.
4361 * @hs_ep: The endpoint to be initialised.
4362 * @epnum: The endpoint number
4364 * Initialise the given endpoint (as part of the probe and device state
4365 * creation) to give to the gadget driver. Setup the endpoint name, any
4366 * direction information and other state that may be required.
4368 static void dwc2_hsotg_initep(struct dwc2_hsotg
*hsotg
,
4369 struct dwc2_hsotg_ep
*hs_ep
,
4382 hs_ep
->dir_in
= dir_in
;
4383 hs_ep
->index
= epnum
;
4385 snprintf(hs_ep
->name
, sizeof(hs_ep
->name
), "ep%d%s", epnum
, dir
);
4387 INIT_LIST_HEAD(&hs_ep
->queue
);
4388 INIT_LIST_HEAD(&hs_ep
->ep
.ep_list
);
4390 /* add to the list of endpoints known by the gadget driver */
4392 list_add_tail(&hs_ep
->ep
.ep_list
, &hsotg
->gadget
.ep_list
);
4394 hs_ep
->parent
= hsotg
;
4395 hs_ep
->ep
.name
= hs_ep
->name
;
4397 if (hsotg
->params
.speed
== DWC2_SPEED_PARAM_LOW
)
4398 usb_ep_set_maxpacket_limit(&hs_ep
->ep
, 8);
4400 usb_ep_set_maxpacket_limit(&hs_ep
->ep
,
4401 epnum
? 1024 : EP0_MPS_LIMIT
);
4402 hs_ep
->ep
.ops
= &dwc2_hsotg_ep_ops
;
4405 hs_ep
->ep
.caps
.type_control
= true;
4407 if (hsotg
->params
.speed
!= DWC2_SPEED_PARAM_LOW
) {
4408 hs_ep
->ep
.caps
.type_iso
= true;
4409 hs_ep
->ep
.caps
.type_bulk
= true;
4411 hs_ep
->ep
.caps
.type_int
= true;
4415 hs_ep
->ep
.caps
.dir_in
= true;
4417 hs_ep
->ep
.caps
.dir_out
= true;
4420 * if we're using dma, we need to set the next-endpoint pointer
4421 * to be something valid.
4424 if (using_dma(hsotg
)) {
4425 u32 next
= DXEPCTL_NEXTEP((epnum
+ 1) % 15);
4427 dwc2_writel(next
, hsotg
->regs
+ DIEPCTL(epnum
));
4429 dwc2_writel(next
, hsotg
->regs
+ DOEPCTL(epnum
));
4434 * dwc2_hsotg_hw_cfg - read HW configuration registers
4435 * @param: The device state
4437 * Read the USB core HW configuration registers
4439 static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg
*hsotg
)
4445 /* check hardware configuration */
4447 hsotg
->num_of_eps
= hsotg
->hw_params
.num_dev_ep
;
4450 hsotg
->num_of_eps
++;
4452 hsotg
->eps_in
[0] = devm_kzalloc(hsotg
->dev
, sizeof(struct dwc2_hsotg_ep
),
4454 if (!hsotg
->eps_in
[0])
4456 /* Same dwc2_hsotg_ep is used in both directions for ep0 */
4457 hsotg
->eps_out
[0] = hsotg
->eps_in
[0];
4459 cfg
= hsotg
->hw_params
.dev_ep_dirs
;
4460 for (i
= 1, cfg
>>= 2; i
< hsotg
->num_of_eps
; i
++, cfg
>>= 2) {
4462 /* Direction in or both */
4463 if (!(ep_type
& 2)) {
4464 hsotg
->eps_in
[i
] = devm_kzalloc(hsotg
->dev
,
4465 sizeof(struct dwc2_hsotg_ep
), GFP_KERNEL
);
4466 if (!hsotg
->eps_in
[i
])
4469 /* Direction out or both */
4470 if (!(ep_type
& 1)) {
4471 hsotg
->eps_out
[i
] = devm_kzalloc(hsotg
->dev
,
4472 sizeof(struct dwc2_hsotg_ep
), GFP_KERNEL
);
4473 if (!hsotg
->eps_out
[i
])
4478 hsotg
->fifo_mem
= hsotg
->hw_params
.total_fifo_size
;
4479 hsotg
->dedicated_fifos
= hsotg
->hw_params
.en_multiple_tx_fifo
;
4481 dev_info(hsotg
->dev
, "EPs: %d, %s fifos, %d entries in SPRAM\n",
4483 hsotg
->dedicated_fifos
? "dedicated" : "shared",
4489 * dwc2_hsotg_dump - dump state of the udc
4490 * @param: The device state
4492 static void dwc2_hsotg_dump(struct dwc2_hsotg
*hsotg
)
4495 struct device
*dev
= hsotg
->dev
;
4496 void __iomem
*regs
= hsotg
->regs
;
4500 dev_info(dev
, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
4501 dwc2_readl(regs
+ DCFG
), dwc2_readl(regs
+ DCTL
),
4502 dwc2_readl(regs
+ DIEPMSK
));
4504 dev_info(dev
, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
4505 dwc2_readl(regs
+ GAHBCFG
), dwc2_readl(regs
+ GHWCFG1
));
4507 dev_info(dev
, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
4508 dwc2_readl(regs
+ GRXFSIZ
), dwc2_readl(regs
+ GNPTXFSIZ
));
4510 /* show periodic fifo settings */
4512 for (idx
= 1; idx
< hsotg
->num_of_eps
; idx
++) {
4513 val
= dwc2_readl(regs
+ DPTXFSIZN(idx
));
4514 dev_info(dev
, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx
,
4515 val
>> FIFOSIZE_DEPTH_SHIFT
,
4516 val
& FIFOSIZE_STARTADDR_MASK
);
4519 for (idx
= 0; idx
< hsotg
->num_of_eps
; idx
++) {
4521 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx
,
4522 dwc2_readl(regs
+ DIEPCTL(idx
)),
4523 dwc2_readl(regs
+ DIEPTSIZ(idx
)),
4524 dwc2_readl(regs
+ DIEPDMA(idx
)));
4526 val
= dwc2_readl(regs
+ DOEPCTL(idx
));
4528 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
4529 idx
, dwc2_readl(regs
+ DOEPCTL(idx
)),
4530 dwc2_readl(regs
+ DOEPTSIZ(idx
)),
4531 dwc2_readl(regs
+ DOEPDMA(idx
)));
4535 dev_info(dev
, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
4536 dwc2_readl(regs
+ DVBUSDIS
), dwc2_readl(regs
+ DVBUSPULSE
));
4541 * dwc2_gadget_init - init function for gadget
4542 * @dwc2: The data structure for the DWC2 driver.
4543 * @irq: The IRQ number for the controller.
4545 int dwc2_gadget_init(struct dwc2_hsotg
*hsotg
, int irq
)
4547 struct device
*dev
= hsotg
->dev
;
4551 /* Dump fifo information */
4552 dev_dbg(dev
, "NonPeriodic TXFIFO size: %d\n",
4553 hsotg
->params
.g_np_tx_fifo_size
);
4554 dev_dbg(dev
, "RXFIFO size: %d\n", hsotg
->params
.g_rx_fifo_size
);
4556 hsotg
->gadget
.max_speed
= USB_SPEED_HIGH
;
4557 hsotg
->gadget
.ops
= &dwc2_hsotg_gadget_ops
;
4558 hsotg
->gadget
.name
= dev_name(dev
);
4559 if (hsotg
->dr_mode
== USB_DR_MODE_OTG
)
4560 hsotg
->gadget
.is_otg
= 1;
4561 else if (hsotg
->dr_mode
== USB_DR_MODE_PERIPHERAL
)
4562 hsotg
->op_state
= OTG_STATE_B_PERIPHERAL
;
4564 ret
= dwc2_hsotg_hw_cfg(hsotg
);
4566 dev_err(hsotg
->dev
, "Hardware configuration failed: %d\n", ret
);
4570 hsotg
->ctrl_buff
= devm_kzalloc(hsotg
->dev
,
4571 DWC2_CTRL_BUFF_SIZE
, GFP_KERNEL
);
4572 if (!hsotg
->ctrl_buff
)
4575 hsotg
->ep0_buff
= devm_kzalloc(hsotg
->dev
,
4576 DWC2_CTRL_BUFF_SIZE
, GFP_KERNEL
);
4577 if (!hsotg
->ep0_buff
)
4580 if (using_desc_dma(hsotg
)) {
4581 ret
= dwc2_gadget_alloc_ctrl_desc_chains(hsotg
);
4586 ret
= devm_request_irq(hsotg
->dev
, irq
, dwc2_hsotg_irq
, IRQF_SHARED
,
4587 dev_name(hsotg
->dev
), hsotg
);
4589 dev_err(dev
, "cannot claim IRQ for gadget\n");
4593 /* hsotg->num_of_eps holds number of EPs other than ep0 */
4595 if (hsotg
->num_of_eps
== 0) {
4596 dev_err(dev
, "wrong number of EPs (zero)\n");
4600 /* setup endpoint information */
4602 INIT_LIST_HEAD(&hsotg
->gadget
.ep_list
);
4603 hsotg
->gadget
.ep0
= &hsotg
->eps_out
[0]->ep
;
4605 /* allocate EP0 request */
4607 hsotg
->ctrl_req
= dwc2_hsotg_ep_alloc_request(&hsotg
->eps_out
[0]->ep
,
4609 if (!hsotg
->ctrl_req
) {
4610 dev_err(dev
, "failed to allocate ctrl req\n");
4614 /* initialise the endpoints now the core has been initialised */
4615 for (epnum
= 0; epnum
< hsotg
->num_of_eps
; epnum
++) {
4616 if (hsotg
->eps_in
[epnum
])
4617 dwc2_hsotg_initep(hsotg
, hsotg
->eps_in
[epnum
],
4619 if (hsotg
->eps_out
[epnum
])
4620 dwc2_hsotg_initep(hsotg
, hsotg
->eps_out
[epnum
],
4624 ret
= usb_add_gadget_udc(dev
, &hsotg
->gadget
);
4628 dwc2_hsotg_dump(hsotg
);
4634 * dwc2_hsotg_remove - remove function for hsotg driver
4635 * @pdev: The platform information for the driver
4637 int dwc2_hsotg_remove(struct dwc2_hsotg
*hsotg
)
4639 usb_del_gadget_udc(&hsotg
->gadget
);
4644 int dwc2_hsotg_suspend(struct dwc2_hsotg
*hsotg
)
4646 unsigned long flags
;
4648 if (hsotg
->lx_state
!= DWC2_L0
)
4651 if (hsotg
->driver
) {
4654 dev_info(hsotg
->dev
, "suspending usb gadget %s\n",
4655 hsotg
->driver
->driver
.name
);
4657 spin_lock_irqsave(&hsotg
->lock
, flags
);
4659 dwc2_hsotg_core_disconnect(hsotg
);
4660 dwc2_hsotg_disconnect(hsotg
);
4661 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
4662 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
4664 for (ep
= 0; ep
< hsotg
->num_of_eps
; ep
++) {
4665 if (hsotg
->eps_in
[ep
])
4666 dwc2_hsotg_ep_disable(&hsotg
->eps_in
[ep
]->ep
);
4667 if (hsotg
->eps_out
[ep
])
4668 dwc2_hsotg_ep_disable(&hsotg
->eps_out
[ep
]->ep
);
4675 int dwc2_hsotg_resume(struct dwc2_hsotg
*hsotg
)
4677 unsigned long flags
;
4679 if (hsotg
->lx_state
== DWC2_L2
)
4682 if (hsotg
->driver
) {
4683 dev_info(hsotg
->dev
, "resuming usb gadget %s\n",
4684 hsotg
->driver
->driver
.name
);
4686 spin_lock_irqsave(&hsotg
->lock
, flags
);
4687 dwc2_hsotg_core_init_disconnected(hsotg
, false);
4689 dwc2_hsotg_core_connect(hsotg
);
4690 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
4697 * dwc2_backup_device_registers() - Backup controller device registers.
4698 * When suspending usb bus, registers needs to be backuped
4699 * if controller power is disabled once suspended.
4701 * @hsotg: Programming view of the DWC_otg controller
4703 int dwc2_backup_device_registers(struct dwc2_hsotg
*hsotg
)
4705 struct dwc2_dregs_backup
*dr
;
4708 dev_dbg(hsotg
->dev
, "%s\n", __func__
);
4710 /* Backup dev regs */
4711 dr
= &hsotg
->dr_backup
;
4713 dr
->dcfg
= dwc2_readl(hsotg
->regs
+ DCFG
);
4714 dr
->dctl
= dwc2_readl(hsotg
->regs
+ DCTL
);
4715 dr
->daintmsk
= dwc2_readl(hsotg
->regs
+ DAINTMSK
);
4716 dr
->diepmsk
= dwc2_readl(hsotg
->regs
+ DIEPMSK
);
4717 dr
->doepmsk
= dwc2_readl(hsotg
->regs
+ DOEPMSK
);
4719 for (i
= 0; i
< hsotg
->num_of_eps
; i
++) {
4721 dr
->diepctl
[i
] = dwc2_readl(hsotg
->regs
+ DIEPCTL(i
));
4723 /* Ensure DATA PID is correctly configured */
4724 if (dr
->diepctl
[i
] & DXEPCTL_DPID
)
4725 dr
->diepctl
[i
] |= DXEPCTL_SETD1PID
;
4727 dr
->diepctl
[i
] |= DXEPCTL_SETD0PID
;
4729 dr
->dieptsiz
[i
] = dwc2_readl(hsotg
->regs
+ DIEPTSIZ(i
));
4730 dr
->diepdma
[i
] = dwc2_readl(hsotg
->regs
+ DIEPDMA(i
));
4732 /* Backup OUT EPs */
4733 dr
->doepctl
[i
] = dwc2_readl(hsotg
->regs
+ DOEPCTL(i
));
4735 /* Ensure DATA PID is correctly configured */
4736 if (dr
->doepctl
[i
] & DXEPCTL_DPID
)
4737 dr
->doepctl
[i
] |= DXEPCTL_SETD1PID
;
4739 dr
->doepctl
[i
] |= DXEPCTL_SETD0PID
;
4741 dr
->doeptsiz
[i
] = dwc2_readl(hsotg
->regs
+ DOEPTSIZ(i
));
4742 dr
->doepdma
[i
] = dwc2_readl(hsotg
->regs
+ DOEPDMA(i
));
4749 * dwc2_restore_device_registers() - Restore controller device registers.
4750 * When resuming usb bus, device registers needs to be restored
4751 * if controller power were disabled.
4753 * @hsotg: Programming view of the DWC_otg controller
4755 int dwc2_restore_device_registers(struct dwc2_hsotg
*hsotg
)
4757 struct dwc2_dregs_backup
*dr
;
4761 dev_dbg(hsotg
->dev
, "%s\n", __func__
);
4763 /* Restore dev regs */
4764 dr
= &hsotg
->dr_backup
;
4766 dev_err(hsotg
->dev
, "%s: no device registers to restore\n",
4772 dwc2_writel(dr
->dcfg
, hsotg
->regs
+ DCFG
);
4773 dwc2_writel(dr
->dctl
, hsotg
->regs
+ DCTL
);
4774 dwc2_writel(dr
->daintmsk
, hsotg
->regs
+ DAINTMSK
);
4775 dwc2_writel(dr
->diepmsk
, hsotg
->regs
+ DIEPMSK
);
4776 dwc2_writel(dr
->doepmsk
, hsotg
->regs
+ DOEPMSK
);
4778 for (i
= 0; i
< hsotg
->num_of_eps
; i
++) {
4779 /* Restore IN EPs */
4780 dwc2_writel(dr
->diepctl
[i
], hsotg
->regs
+ DIEPCTL(i
));
4781 dwc2_writel(dr
->dieptsiz
[i
], hsotg
->regs
+ DIEPTSIZ(i
));
4782 dwc2_writel(dr
->diepdma
[i
], hsotg
->regs
+ DIEPDMA(i
));
4784 /* Restore OUT EPs */
4785 dwc2_writel(dr
->doepctl
[i
], hsotg
->regs
+ DOEPCTL(i
));
4786 dwc2_writel(dr
->doeptsiz
[i
], hsotg
->regs
+ DOEPTSIZ(i
));
4787 dwc2_writel(dr
->doepdma
[i
], hsotg
->regs
+ DOEPDMA(i
));
4790 /* Set the Power-On Programming done bit */
4791 dctl
= dwc2_readl(hsotg
->regs
+ DCTL
);
4792 dctl
|= DCTL_PWRONPRGDONE
;
4793 dwc2_writel(dctl
, hsotg
->regs
+ DCTL
);