2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/slab.h>
21 #include <linux/spinlock.h>
22 #include <linux/platform_device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/interrupt.h>
26 #include <linux/list.h>
27 #include <linux/dma-mapping.h>
29 #include <linux/usb/ch9.h>
30 #include <linux/usb/gadget.h>
31 #include <linux/usb/composite.h>
38 static void __dwc3_ep0_do_control_status(struct dwc3
*dwc
, struct dwc3_ep
*dep
);
39 static void __dwc3_ep0_do_control_data(struct dwc3
*dwc
,
40 struct dwc3_ep
*dep
, struct dwc3_request
*req
);
42 static void dwc3_ep0_prepare_one_trb(struct dwc3_ep
*dep
,
43 dma_addr_t buf_dma
, u32 len
, u32 type
, bool chain
)
49 trb
= &dwc
->ep0_trb
[dep
->trb_enqueue
];
54 trb
->bpl
= lower_32_bits(buf_dma
);
55 trb
->bph
= upper_32_bits(buf_dma
);
59 trb
->ctrl
|= (DWC3_TRB_CTRL_HWO
60 | DWC3_TRB_CTRL_ISP_IMI
);
63 trb
->ctrl
|= DWC3_TRB_CTRL_CHN
;
65 trb
->ctrl
|= (DWC3_TRB_CTRL_IOC
68 trace_dwc3_prepare_trb(dep
, trb
);
71 static int dwc3_ep0_start_trans(struct dwc3_ep
*dep
)
73 struct dwc3_gadget_ep_cmd_params params
;
77 if (dep
->flags
& DWC3_EP_BUSY
)
82 memset(¶ms
, 0, sizeof(params
));
83 params
.param0
= upper_32_bits(dwc
->ep0_trb_addr
);
84 params
.param1
= lower_32_bits(dwc
->ep0_trb_addr
);
86 ret
= dwc3_send_gadget_ep_cmd(dep
, DWC3_DEPCMD_STARTTRANSFER
, ¶ms
);
90 dep
->flags
|= DWC3_EP_BUSY
;
91 dep
->resource_index
= dwc3_gadget_ep_get_transfer_index(dep
);
92 dwc
->ep0_next_event
= DWC3_EP0_COMPLETE
;
97 static int __dwc3_gadget_ep0_queue(struct dwc3_ep
*dep
,
98 struct dwc3_request
*req
)
100 struct dwc3
*dwc
= dep
->dwc
;
102 req
->request
.actual
= 0;
103 req
->request
.status
= -EINPROGRESS
;
104 req
->epnum
= dep
->number
;
106 list_add_tail(&req
->list
, &dep
->pending_list
);
109 * Gadget driver might not be quick enough to queue a request
110 * before we get a Transfer Not Ready event on this endpoint.
112 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
113 * flag is set, it's telling us that as soon as Gadget queues the
114 * required request, we should kick the transfer here because the
115 * IRQ we were waiting for is long gone.
117 if (dep
->flags
& DWC3_EP_PENDING_REQUEST
) {
120 direction
= !!(dep
->flags
& DWC3_EP0_DIR_IN
);
122 if (dwc
->ep0state
!= EP0_DATA_PHASE
) {
123 dev_WARN(dwc
->dev
, "Unexpected pending request\n");
127 __dwc3_ep0_do_control_data(dwc
, dwc
->eps
[direction
], req
);
129 dep
->flags
&= ~(DWC3_EP_PENDING_REQUEST
|
136 * In case gadget driver asked us to delay the STATUS phase,
139 if (dwc
->delayed_status
) {
142 direction
= !dwc
->ep0_expect_in
;
143 dwc
->delayed_status
= false;
144 usb_gadget_set_state(&dwc
->gadget
, USB_STATE_CONFIGURED
);
146 if (dwc
->ep0state
== EP0_STATUS_PHASE
)
147 __dwc3_ep0_do_control_status(dwc
, dwc
->eps
[direction
]);
153 * Unfortunately we have uncovered a limitation wrt the Data Phase.
155 * Section 9.4 says we can wait for the XferNotReady(DATA) event to
156 * come before issueing Start Transfer command, but if we do, we will
157 * miss situations where the host starts another SETUP phase instead of
158 * the DATA phase. Such cases happen at least on TD.7.6 of the Link
159 * Layer Compliance Suite.
161 * The problem surfaces due to the fact that in case of back-to-back
162 * SETUP packets there will be no XferNotReady(DATA) generated and we
163 * will be stuck waiting for XferNotReady(DATA) forever.
165 * By looking at tables 9-13 and 9-14 of the Databook, we can see that
166 * it tells us to start Data Phase right away. It also mentions that if
167 * we receive a SETUP phase instead of the DATA phase, core will issue
168 * XferComplete for the DATA phase, before actually initiating it in
169 * the wire, with the TRB's status set to "SETUP_PENDING". Such status
170 * can only be used to print some debugging logs, as the core expects
171 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
172 * just so it completes right away, without transferring anything and,
173 * only then, we can go back to the SETUP phase.
175 * Because of this scenario, SNPS decided to change the programming
176 * model of control transfers and support on-demand transfers only for
177 * the STATUS phase. To fix the issue we have now, we will always wait
178 * for gadget driver to queue the DATA phase's struct usb_request, then
179 * start it right away.
181 * If we're actually in a 2-stage transfer, we will wait for
182 * XferNotReady(STATUS).
184 if (dwc
->three_stage_setup
) {
187 direction
= dwc
->ep0_expect_in
;
188 dwc
->ep0state
= EP0_DATA_PHASE
;
190 __dwc3_ep0_do_control_data(dwc
, dwc
->eps
[direction
], req
);
192 dep
->flags
&= ~DWC3_EP0_DIR_IN
;
198 int dwc3_gadget_ep0_queue(struct usb_ep
*ep
, struct usb_request
*request
,
201 struct dwc3_request
*req
= to_dwc3_request(request
);
202 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
203 struct dwc3
*dwc
= dep
->dwc
;
209 spin_lock_irqsave(&dwc
->lock
, flags
);
210 if (!dep
->endpoint
.desc
) {
211 dev_err(dwc
->dev
, "%s: can't queue to disabled endpoint\n",
217 /* we share one TRB for ep0/1 */
218 if (!list_empty(&dep
->pending_list
)) {
223 ret
= __dwc3_gadget_ep0_queue(dep
, req
);
226 spin_unlock_irqrestore(&dwc
->lock
, flags
);
231 static void dwc3_ep0_stall_and_restart(struct dwc3
*dwc
)
235 /* reinitialize physical ep1 */
237 dep
->flags
= DWC3_EP_ENABLED
;
239 /* stall is always issued on EP0 */
241 __dwc3_gadget_ep_set_halt(dep
, 1, false);
242 dep
->flags
= DWC3_EP_ENABLED
;
243 dwc
->delayed_status
= false;
245 if (!list_empty(&dep
->pending_list
)) {
246 struct dwc3_request
*req
;
248 req
= next_request(&dep
->pending_list
);
249 dwc3_gadget_giveback(dep
, req
, -ECONNRESET
);
252 dwc
->ep0state
= EP0_SETUP_PHASE
;
253 dwc3_ep0_out_start(dwc
);
256 int __dwc3_gadget_ep0_set_halt(struct usb_ep
*ep
, int value
)
258 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
259 struct dwc3
*dwc
= dep
->dwc
;
261 dwc3_ep0_stall_and_restart(dwc
);
266 int dwc3_gadget_ep0_set_halt(struct usb_ep
*ep
, int value
)
268 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
269 struct dwc3
*dwc
= dep
->dwc
;
273 spin_lock_irqsave(&dwc
->lock
, flags
);
274 ret
= __dwc3_gadget_ep0_set_halt(ep
, value
);
275 spin_unlock_irqrestore(&dwc
->lock
, flags
);
280 void dwc3_ep0_out_start(struct dwc3
*dwc
)
285 complete(&dwc
->ep0_in_setup
);
288 dwc3_ep0_prepare_one_trb(dep
, dwc
->ep0_trb_addr
, 8,
289 DWC3_TRBCTL_CONTROL_SETUP
, false);
290 ret
= dwc3_ep0_start_trans(dep
);
294 static struct dwc3_ep
*dwc3_wIndex_to_dep(struct dwc3
*dwc
, __le16 wIndex_le
)
297 u32 windex
= le16_to_cpu(wIndex_le
);
300 epnum
= (windex
& USB_ENDPOINT_NUMBER_MASK
) << 1;
301 if ((windex
& USB_ENDPOINT_DIR_MASK
) == USB_DIR_IN
)
304 dep
= dwc
->eps
[epnum
];
305 if (dep
->flags
& DWC3_EP_ENABLED
)
311 static void dwc3_ep0_status_cmpl(struct usb_ep
*ep
, struct usb_request
*req
)
317 static int dwc3_ep0_handle_status(struct dwc3
*dwc
,
318 struct usb_ctrlrequest
*ctrl
)
324 __le16
*response_pkt
;
326 recip
= ctrl
->bRequestType
& USB_RECIP_MASK
;
328 case USB_RECIP_DEVICE
:
330 * LTM will be set once we know how to set this in HW.
332 usb_status
|= dwc
->gadget
.is_selfpowered
;
334 if ((dwc
->speed
== DWC3_DSTS_SUPERSPEED
) ||
335 (dwc
->speed
== DWC3_DSTS_SUPERSPEED_PLUS
)) {
336 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
337 if (reg
& DWC3_DCTL_INITU1ENA
)
338 usb_status
|= 1 << USB_DEV_STAT_U1_ENABLED
;
339 if (reg
& DWC3_DCTL_INITU2ENA
)
340 usb_status
|= 1 << USB_DEV_STAT_U2_ENABLED
;
345 case USB_RECIP_INTERFACE
:
347 * Function Remote Wake Capable D0
348 * Function Remote Wakeup D1
352 case USB_RECIP_ENDPOINT
:
353 dep
= dwc3_wIndex_to_dep(dwc
, ctrl
->wIndex
);
357 if (dep
->flags
& DWC3_EP_STALL
)
358 usb_status
= 1 << USB_ENDPOINT_HALT
;
364 response_pkt
= (__le16
*) dwc
->setup_buf
;
365 *response_pkt
= cpu_to_le16(usb_status
);
368 dwc
->ep0_usb_req
.dep
= dep
;
369 dwc
->ep0_usb_req
.request
.length
= sizeof(*response_pkt
);
370 dwc
->ep0_usb_req
.request
.buf
= dwc
->setup_buf
;
371 dwc
->ep0_usb_req
.request
.complete
= dwc3_ep0_status_cmpl
;
373 return __dwc3_gadget_ep0_queue(dep
, &dwc
->ep0_usb_req
);
376 static int dwc3_ep0_handle_u1(struct dwc3
*dwc
, enum usb_device_state state
,
381 if (state
!= USB_STATE_CONFIGURED
)
383 if ((dwc
->speed
!= DWC3_DSTS_SUPERSPEED
) &&
384 (dwc
->speed
!= DWC3_DSTS_SUPERSPEED_PLUS
))
387 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
389 reg
|= DWC3_DCTL_INITU1ENA
;
391 reg
&= ~DWC3_DCTL_INITU1ENA
;
392 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
397 static int dwc3_ep0_handle_u2(struct dwc3
*dwc
, enum usb_device_state state
,
403 if (state
!= USB_STATE_CONFIGURED
)
405 if ((dwc
->speed
!= DWC3_DSTS_SUPERSPEED
) &&
406 (dwc
->speed
!= DWC3_DSTS_SUPERSPEED_PLUS
))
409 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
411 reg
|= DWC3_DCTL_INITU2ENA
;
413 reg
&= ~DWC3_DCTL_INITU2ENA
;
414 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
419 static int dwc3_ep0_handle_test(struct dwc3
*dwc
, enum usb_device_state state
,
422 if ((wIndex
& 0xff) != 0)
427 switch (wIndex
>> 8) {
433 dwc
->test_mode_nr
= wIndex
>> 8;
434 dwc
->test_mode
= true;
443 static int dwc3_ep0_handle_device(struct dwc3
*dwc
,
444 struct usb_ctrlrequest
*ctrl
, int set
)
446 enum usb_device_state state
;
451 wValue
= le16_to_cpu(ctrl
->wValue
);
452 wIndex
= le16_to_cpu(ctrl
->wIndex
);
453 state
= dwc
->gadget
.state
;
456 case USB_DEVICE_REMOTE_WAKEUP
:
459 * 9.4.1 says only only for SS, in AddressState only for
460 * default control pipe
462 case USB_DEVICE_U1_ENABLE
:
463 ret
= dwc3_ep0_handle_u1(dwc
, state
, set
);
465 case USB_DEVICE_U2_ENABLE
:
466 ret
= dwc3_ep0_handle_u2(dwc
, state
, set
);
468 case USB_DEVICE_LTM_ENABLE
:
471 case USB_DEVICE_TEST_MODE
:
472 ret
= dwc3_ep0_handle_test(dwc
, state
, wIndex
, set
);
481 static int dwc3_ep0_handle_intf(struct dwc3
*dwc
,
482 struct usb_ctrlrequest
*ctrl
, int set
)
484 enum usb_device_state state
;
489 wValue
= le16_to_cpu(ctrl
->wValue
);
490 wIndex
= le16_to_cpu(ctrl
->wIndex
);
491 state
= dwc
->gadget
.state
;
494 case USB_INTRF_FUNC_SUSPEND
:
496 * REVISIT: Ideally we would enable some low power mode here,
497 * however it's unclear what we should be doing here.
499 * For now, we're not doing anything, just making sure we return
500 * 0 so USB Command Verifier tests pass without any errors.
510 static int dwc3_ep0_handle_endpoint(struct dwc3
*dwc
,
511 struct usb_ctrlrequest
*ctrl
, int set
)
514 enum usb_device_state state
;
519 wValue
= le16_to_cpu(ctrl
->wValue
);
520 wIndex
= le16_to_cpu(ctrl
->wIndex
);
521 state
= dwc
->gadget
.state
;
524 case USB_ENDPOINT_HALT
:
525 dep
= dwc3_wIndex_to_dep(dwc
, ctrl
->wIndex
);
529 if (set
== 0 && (dep
->flags
& DWC3_EP_WEDGE
))
532 ret
= __dwc3_gadget_ep_set_halt(dep
, set
, true);
543 static int dwc3_ep0_handle_feature(struct dwc3
*dwc
,
544 struct usb_ctrlrequest
*ctrl
, int set
)
548 enum usb_device_state state
;
550 recip
= ctrl
->bRequestType
& USB_RECIP_MASK
;
551 state
= dwc
->gadget
.state
;
554 case USB_RECIP_DEVICE
:
555 ret
= dwc3_ep0_handle_device(dwc
, ctrl
, set
);
557 case USB_RECIP_INTERFACE
:
558 ret
= dwc3_ep0_handle_intf(dwc
, ctrl
, set
);
560 case USB_RECIP_ENDPOINT
:
561 ret
= dwc3_ep0_handle_endpoint(dwc
, ctrl
, set
);
570 static int dwc3_ep0_set_address(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
572 enum usb_device_state state
= dwc
->gadget
.state
;
576 addr
= le16_to_cpu(ctrl
->wValue
);
578 dev_err(dwc
->dev
, "invalid device address %d\n", addr
);
582 if (state
== USB_STATE_CONFIGURED
) {
583 dev_err(dwc
->dev
, "can't SetAddress() from Configured State\n");
587 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
588 reg
&= ~(DWC3_DCFG_DEVADDR_MASK
);
589 reg
|= DWC3_DCFG_DEVADDR(addr
);
590 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
593 usb_gadget_set_state(&dwc
->gadget
, USB_STATE_ADDRESS
);
595 usb_gadget_set_state(&dwc
->gadget
, USB_STATE_DEFAULT
);
600 static int dwc3_ep0_delegate_req(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
604 spin_unlock(&dwc
->lock
);
605 ret
= dwc
->gadget_driver
->setup(&dwc
->gadget
, ctrl
);
606 spin_lock(&dwc
->lock
);
610 static int dwc3_ep0_set_config(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
612 enum usb_device_state state
= dwc
->gadget
.state
;
617 cfg
= le16_to_cpu(ctrl
->wValue
);
620 case USB_STATE_DEFAULT
:
623 case USB_STATE_ADDRESS
:
624 ret
= dwc3_ep0_delegate_req(dwc
, ctrl
);
625 /* if the cfg matches and the cfg is non zero */
626 if (cfg
&& (!ret
|| (ret
== USB_GADGET_DELAYED_STATUS
))) {
629 * only change state if set_config has already
630 * been processed. If gadget driver returns
631 * USB_GADGET_DELAYED_STATUS, we will wait
632 * to change the state on the next usb_ep_queue()
635 usb_gadget_set_state(&dwc
->gadget
,
636 USB_STATE_CONFIGURED
);
639 * Enable transition to U1/U2 state when
640 * nothing is pending from application.
642 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
643 reg
|= (DWC3_DCTL_ACCEPTU1ENA
| DWC3_DCTL_ACCEPTU2ENA
);
644 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
648 case USB_STATE_CONFIGURED
:
649 ret
= dwc3_ep0_delegate_req(dwc
, ctrl
);
651 usb_gadget_set_state(&dwc
->gadget
,
660 static void dwc3_ep0_set_sel_cmpl(struct usb_ep
*ep
, struct usb_request
*req
)
662 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
663 struct dwc3
*dwc
= dep
->dwc
;
677 memcpy(&timing
, req
->buf
, sizeof(timing
));
679 dwc
->u1sel
= timing
.u1sel
;
680 dwc
->u1pel
= timing
.u1pel
;
681 dwc
->u2sel
= le16_to_cpu(timing
.u2sel
);
682 dwc
->u2pel
= le16_to_cpu(timing
.u2pel
);
684 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
685 if (reg
& DWC3_DCTL_INITU2ENA
)
687 if (reg
& DWC3_DCTL_INITU1ENA
)
691 * According to Synopsys Databook, if parameter is
692 * greater than 125, a value of zero should be
693 * programmed in the register.
698 /* now that we have the time, issue DGCMD Set Sel */
699 ret
= dwc3_send_gadget_generic_command(dwc
,
700 DWC3_DGCMD_SET_PERIODIC_PAR
, param
);
704 static int dwc3_ep0_set_sel(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
707 enum usb_device_state state
= dwc
->gadget
.state
;
711 if (state
== USB_STATE_DEFAULT
)
714 wValue
= le16_to_cpu(ctrl
->wValue
);
715 wLength
= le16_to_cpu(ctrl
->wLength
);
718 dev_err(dwc
->dev
, "Set SEL should be 6 bytes, got %d\n",
724 * To handle Set SEL we need to receive 6 bytes from Host. So let's
725 * queue a usb_request for 6 bytes.
727 * Remember, though, this controller can't handle non-wMaxPacketSize
728 * aligned transfers on the OUT direction, so we queue a request for
729 * wMaxPacketSize instead.
732 dwc
->ep0_usb_req
.dep
= dep
;
733 dwc
->ep0_usb_req
.request
.length
= dep
->endpoint
.maxpacket
;
734 dwc
->ep0_usb_req
.request
.buf
= dwc
->setup_buf
;
735 dwc
->ep0_usb_req
.request
.complete
= dwc3_ep0_set_sel_cmpl
;
737 return __dwc3_gadget_ep0_queue(dep
, &dwc
->ep0_usb_req
);
740 static int dwc3_ep0_set_isoch_delay(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
746 wValue
= le16_to_cpu(ctrl
->wValue
);
747 wLength
= le16_to_cpu(ctrl
->wLength
);
748 wIndex
= le16_to_cpu(ctrl
->wIndex
);
750 if (wIndex
|| wLength
)
754 * REVISIT It's unclear from Databook what to do with this
755 * value. For now, just cache it.
757 dwc
->isoch_delay
= wValue
;
762 static int dwc3_ep0_std_request(struct dwc3
*dwc
, struct usb_ctrlrequest
*ctrl
)
766 switch (ctrl
->bRequest
) {
767 case USB_REQ_GET_STATUS
:
768 ret
= dwc3_ep0_handle_status(dwc
, ctrl
);
770 case USB_REQ_CLEAR_FEATURE
:
771 ret
= dwc3_ep0_handle_feature(dwc
, ctrl
, 0);
773 case USB_REQ_SET_FEATURE
:
774 ret
= dwc3_ep0_handle_feature(dwc
, ctrl
, 1);
776 case USB_REQ_SET_ADDRESS
:
777 ret
= dwc3_ep0_set_address(dwc
, ctrl
);
779 case USB_REQ_SET_CONFIGURATION
:
780 ret
= dwc3_ep0_set_config(dwc
, ctrl
);
782 case USB_REQ_SET_SEL
:
783 ret
= dwc3_ep0_set_sel(dwc
, ctrl
);
785 case USB_REQ_SET_ISOCH_DELAY
:
786 ret
= dwc3_ep0_set_isoch_delay(dwc
, ctrl
);
789 ret
= dwc3_ep0_delegate_req(dwc
, ctrl
);
796 static void dwc3_ep0_inspect_setup(struct dwc3
*dwc
,
797 const struct dwc3_event_depevt
*event
)
799 struct usb_ctrlrequest
*ctrl
= (void *) dwc
->ep0_trb
;
803 if (!dwc
->gadget_driver
)
806 trace_dwc3_ctrl_req(ctrl
);
808 len
= le16_to_cpu(ctrl
->wLength
);
810 dwc
->three_stage_setup
= false;
811 dwc
->ep0_expect_in
= false;
812 dwc
->ep0_next_event
= DWC3_EP0_NRDY_STATUS
;
814 dwc
->three_stage_setup
= true;
815 dwc
->ep0_expect_in
= !!(ctrl
->bRequestType
& USB_DIR_IN
);
816 dwc
->ep0_next_event
= DWC3_EP0_NRDY_DATA
;
819 if ((ctrl
->bRequestType
& USB_TYPE_MASK
) == USB_TYPE_STANDARD
)
820 ret
= dwc3_ep0_std_request(dwc
, ctrl
);
822 ret
= dwc3_ep0_delegate_req(dwc
, ctrl
);
824 if (ret
== USB_GADGET_DELAYED_STATUS
)
825 dwc
->delayed_status
= true;
829 dwc3_ep0_stall_and_restart(dwc
);
832 static void dwc3_ep0_complete_data(struct dwc3
*dwc
,
833 const struct dwc3_event_depevt
*event
)
835 struct dwc3_request
*r
= NULL
;
836 struct usb_request
*ur
;
837 struct dwc3_trb
*trb
;
840 unsigned remaining_ur_length
;
847 epnum
= event
->endpoint_number
;
850 dwc
->ep0_next_event
= DWC3_EP0_NRDY_STATUS
;
852 trace_dwc3_complete_trb(ep0
, trb
);
854 r
= next_request(&ep0
->pending_list
);
858 status
= DWC3_TRB_SIZE_TRBSTS(trb
->size
);
859 if (status
== DWC3_TRBSTS_SETUP_PENDING
) {
860 dwc
->setup_packet_pending
= true;
862 dwc3_gadget_giveback(ep0
, r
, -ECONNRESET
);
869 remaining_ur_length
= ur
->length
;
871 length
= trb
->size
& DWC3_TRB_SIZE_MASK
;
872 maxp
= ep0
->endpoint
.maxpacket
;
873 transferred
= ur
->length
- length
;
874 ur
->actual
+= transferred
;
876 if ((IS_ALIGNED(ur
->length
, ep0
->endpoint
.maxpacket
) &&
877 ur
->length
&& ur
->zero
) || dwc
->ep0_bounced
) {
879 trb
->ctrl
&= ~DWC3_TRB_CTRL_HWO
;
880 trace_dwc3_complete_trb(ep0
, trb
);
881 ep0
->trb_enqueue
= 0;
882 dwc
->ep0_bounced
= false;
885 if ((epnum
& 1) && ur
->actual
< ur
->length
)
886 dwc3_ep0_stall_and_restart(dwc
);
888 dwc3_gadget_giveback(ep0
, r
, 0);
891 static void dwc3_ep0_complete_status(struct dwc3
*dwc
,
892 const struct dwc3_event_depevt
*event
)
894 struct dwc3_request
*r
;
896 struct dwc3_trb
*trb
;
902 trace_dwc3_complete_trb(dep
, trb
);
904 if (!list_empty(&dep
->pending_list
)) {
905 r
= next_request(&dep
->pending_list
);
907 dwc3_gadget_giveback(dep
, r
, 0);
910 if (dwc
->test_mode
) {
913 ret
= dwc3_gadget_set_test_mode(dwc
, dwc
->test_mode_nr
);
915 dev_err(dwc
->dev
, "invalid test #%d\n",
917 dwc3_ep0_stall_and_restart(dwc
);
922 status
= DWC3_TRB_SIZE_TRBSTS(trb
->size
);
923 if (status
== DWC3_TRBSTS_SETUP_PENDING
)
924 dwc
->setup_packet_pending
= true;
926 dwc
->ep0state
= EP0_SETUP_PHASE
;
927 dwc3_ep0_out_start(dwc
);
930 static void dwc3_ep0_xfer_complete(struct dwc3
*dwc
,
931 const struct dwc3_event_depevt
*event
)
933 struct dwc3_ep
*dep
= dwc
->eps
[event
->endpoint_number
];
935 dep
->flags
&= ~DWC3_EP_BUSY
;
936 dep
->resource_index
= 0;
937 dwc
->setup_packet_pending
= false;
939 switch (dwc
->ep0state
) {
940 case EP0_SETUP_PHASE
:
941 dwc3_ep0_inspect_setup(dwc
, event
);
945 dwc3_ep0_complete_data(dwc
, event
);
948 case EP0_STATUS_PHASE
:
949 dwc3_ep0_complete_status(dwc
, event
);
952 WARN(true, "UNKNOWN ep0state %d\n", dwc
->ep0state
);
956 static void __dwc3_ep0_do_control_data(struct dwc3
*dwc
,
957 struct dwc3_ep
*dep
, struct dwc3_request
*req
)
961 req
->direction
= !!dep
->number
;
963 if (req
->request
.length
== 0) {
964 dwc3_ep0_prepare_one_trb(dep
, dwc
->ep0_trb_addr
, 0,
965 DWC3_TRBCTL_CONTROL_DATA
, false);
966 ret
= dwc3_ep0_start_trans(dep
);
967 } else if (!IS_ALIGNED(req
->request
.length
, dep
->endpoint
.maxpacket
)
968 && (dep
->number
== 0)) {
972 ret
= usb_gadget_map_request_by_dev(dwc
->sysdev
,
973 &req
->request
, dep
->number
);
977 maxpacket
= dep
->endpoint
.maxpacket
;
978 rem
= req
->request
.length
% maxpacket
;
979 dwc
->ep0_bounced
= true;
981 /* prepare normal TRB */
982 dwc3_ep0_prepare_one_trb(dep
, req
->request
.dma
,
984 DWC3_TRBCTL_CONTROL_DATA
,
987 /* Now prepare one extra TRB to align transfer size */
988 dwc3_ep0_prepare_one_trb(dep
, dwc
->bounce_addr
,
990 DWC3_TRBCTL_CONTROL_DATA
,
992 ret
= dwc3_ep0_start_trans(dep
);
993 } else if (IS_ALIGNED(req
->request
.length
, dep
->endpoint
.maxpacket
) &&
994 req
->request
.length
&& req
->request
.zero
) {
998 ret
= usb_gadget_map_request_by_dev(dwc
->sysdev
,
999 &req
->request
, dep
->number
);
1003 maxpacket
= dep
->endpoint
.maxpacket
;
1004 rem
= req
->request
.length
% maxpacket
;
1006 /* prepare normal TRB */
1007 dwc3_ep0_prepare_one_trb(dep
, req
->request
.dma
,
1008 req
->request
.length
,
1009 DWC3_TRBCTL_CONTROL_DATA
,
1012 /* Now prepare one extra TRB to align transfer size */
1013 dwc3_ep0_prepare_one_trb(dep
, dwc
->bounce_addr
,
1014 0, DWC3_TRBCTL_CONTROL_DATA
,
1016 ret
= dwc3_ep0_start_trans(dep
);
1018 ret
= usb_gadget_map_request_by_dev(dwc
->sysdev
,
1019 &req
->request
, dep
->number
);
1023 dwc3_ep0_prepare_one_trb(dep
, req
->request
.dma
,
1024 req
->request
.length
, DWC3_TRBCTL_CONTROL_DATA
,
1026 ret
= dwc3_ep0_start_trans(dep
);
1032 static int dwc3_ep0_start_control_status(struct dwc3_ep
*dep
)
1034 struct dwc3
*dwc
= dep
->dwc
;
1037 type
= dwc
->three_stage_setup
? DWC3_TRBCTL_CONTROL_STATUS3
1038 : DWC3_TRBCTL_CONTROL_STATUS2
;
1040 dwc3_ep0_prepare_one_trb(dep
, dwc
->ep0_trb_addr
, 0, type
, false);
1041 return dwc3_ep0_start_trans(dep
);
1044 static void __dwc3_ep0_do_control_status(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
1046 WARN_ON(dwc3_ep0_start_control_status(dep
));
1049 static void dwc3_ep0_do_control_status(struct dwc3
*dwc
,
1050 const struct dwc3_event_depevt
*event
)
1052 struct dwc3_ep
*dep
= dwc
->eps
[event
->endpoint_number
];
1054 __dwc3_ep0_do_control_status(dwc
, dep
);
1057 static void dwc3_ep0_end_control_data(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
1059 struct dwc3_gadget_ep_cmd_params params
;
1063 if (!dep
->resource_index
)
1066 cmd
= DWC3_DEPCMD_ENDTRANSFER
;
1067 cmd
|= DWC3_DEPCMD_CMDIOC
;
1068 cmd
|= DWC3_DEPCMD_PARAM(dep
->resource_index
);
1069 memset(¶ms
, 0, sizeof(params
));
1070 ret
= dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
1072 dep
->resource_index
= 0;
1075 static void dwc3_ep0_xfernotready(struct dwc3
*dwc
,
1076 const struct dwc3_event_depevt
*event
)
1078 switch (event
->status
) {
1079 case DEPEVT_STATUS_CONTROL_DATA
:
1081 * We already have a DATA transfer in the controller's cache,
1082 * if we receive a XferNotReady(DATA) we will ignore it, unless
1083 * it's for the wrong direction.
1085 * In that case, we must issue END_TRANSFER command to the Data
1086 * Phase we already have started and issue SetStall on the
1089 if (dwc
->ep0_expect_in
!= event
->endpoint_number
) {
1090 struct dwc3_ep
*dep
= dwc
->eps
[dwc
->ep0_expect_in
];
1092 dev_err(dwc
->dev
, "unexpected direction for Data Phase\n");
1093 dwc3_ep0_end_control_data(dwc
, dep
);
1094 dwc3_ep0_stall_and_restart(dwc
);
1100 case DEPEVT_STATUS_CONTROL_STATUS
:
1101 if (dwc
->ep0_next_event
!= DWC3_EP0_NRDY_STATUS
)
1104 dwc
->ep0state
= EP0_STATUS_PHASE
;
1106 if (dwc
->delayed_status
) {
1107 struct dwc3_ep
*dep
= dwc
->eps
[0];
1109 WARN_ON_ONCE(event
->endpoint_number
!= 1);
1111 * We should handle the delay STATUS phase here if the
1112 * request for handling delay STATUS has been queued
1115 if (!list_empty(&dep
->pending_list
)) {
1116 dwc
->delayed_status
= false;
1117 usb_gadget_set_state(&dwc
->gadget
,
1118 USB_STATE_CONFIGURED
);
1119 dwc3_ep0_do_control_status(dwc
, event
);
1125 dwc3_ep0_do_control_status(dwc
, event
);
1129 void dwc3_ep0_interrupt(struct dwc3
*dwc
,
1130 const struct dwc3_event_depevt
*event
)
1132 switch (event
->endpoint_event
) {
1133 case DWC3_DEPEVT_XFERCOMPLETE
:
1134 dwc3_ep0_xfer_complete(dwc
, event
);
1137 case DWC3_DEPEVT_XFERNOTREADY
:
1138 dwc3_ep0_xfernotready(dwc
, event
);
1141 case DWC3_DEPEVT_XFERINPROGRESS
:
1142 case DWC3_DEPEVT_RXTXFIFOEVT
:
1143 case DWC3_DEPEVT_STREAMEVT
:
1144 case DWC3_DEPEVT_EPCMDCMPLT
: