2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/spinlock.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/interrupt.h>
27 #include <linux/list.h>
28 #include <linux/dma-mapping.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
39 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
40 * @dwc: pointer to our context structure
41 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
43 * Caller should take care of locking. This function will
44 * return 0 on success or -EINVAL if wrong Test Selector
47 int dwc3_gadget_set_test_mode(struct dwc3
*dwc
, int mode
)
51 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
52 reg
&= ~DWC3_DCTL_TSTCTRL_MASK
;
66 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
72 * dwc3_gadget_get_link_state - Gets current state of USB Link
73 * @dwc: pointer to our context structure
75 * Caller should take care of locking. This function will
76 * return the link state on success (>= 0) or -ETIMEDOUT.
78 int dwc3_gadget_get_link_state(struct dwc3
*dwc
)
82 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
84 return DWC3_DSTS_USBLNKST(reg
);
88 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
89 * @dwc: pointer to our context structure
90 * @state: the state to put link into
92 * Caller should take care of locking. This function will
93 * return 0 on success or -ETIMEDOUT.
95 int dwc3_gadget_set_link_state(struct dwc3
*dwc
, enum dwc3_link_state state
)
101 * Wait until device controller is ready. Only applies to 1.94a and
104 if (dwc
->revision
>= DWC3_REVISION_194A
) {
106 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
107 if (reg
& DWC3_DSTS_DCNRD
)
117 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
118 reg
&= ~DWC3_DCTL_ULSTCHNGREQ_MASK
;
120 /* set requested state */
121 reg
|= DWC3_DCTL_ULSTCHNGREQ(state
);
122 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
125 * The following code is racy when called from dwc3_gadget_wakeup,
126 * and is not needed, at least on newer versions
128 if (dwc
->revision
>= DWC3_REVISION_194A
)
131 /* wait for a change in DSTS */
134 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
136 if (DWC3_DSTS_USBLNKST(reg
) == state
)
146 * dwc3_ep_inc_trb() - Increment a TRB index.
147 * @index - Pointer to the TRB index to increment.
149 * The index should never point to the link TRB. After incrementing,
150 * if it is point to the link TRB, wrap around to the beginning. The
151 * link TRB is always at the last TRB entry.
153 static void dwc3_ep_inc_trb(u8
*index
)
156 if (*index
== (DWC3_TRB_NUM
- 1))
160 static void dwc3_ep_inc_enq(struct dwc3_ep
*dep
)
162 dwc3_ep_inc_trb(&dep
->trb_enqueue
);
165 static void dwc3_ep_inc_deq(struct dwc3_ep
*dep
)
167 dwc3_ep_inc_trb(&dep
->trb_dequeue
);
170 void dwc3_gadget_giveback(struct dwc3_ep
*dep
, struct dwc3_request
*req
,
173 struct dwc3
*dwc
= dep
->dwc
;
174 unsigned int unmap_after_complete
= false;
176 req
->started
= false;
177 list_del(&req
->list
);
181 if (req
->request
.status
== -EINPROGRESS
)
182 req
->request
.status
= status
;
185 * NOTICE we don't want to unmap before calling ->complete() if we're
186 * dealing with a bounced ep0 request. If we unmap it here, we would end
187 * up overwritting the contents of req->buf and this could confuse the
190 if (dwc
->ep0_bounced
&& dep
->number
<= 1) {
191 dwc
->ep0_bounced
= false;
192 unmap_after_complete
= true;
194 usb_gadget_unmap_request_by_dev(dwc
->sysdev
,
195 &req
->request
, req
->direction
);
198 trace_dwc3_gadget_giveback(req
);
200 spin_unlock(&dwc
->lock
);
201 usb_gadget_giveback_request(&dep
->endpoint
, &req
->request
);
202 spin_lock(&dwc
->lock
);
204 if (unmap_after_complete
)
205 usb_gadget_unmap_request_by_dev(dwc
->sysdev
,
206 &req
->request
, req
->direction
);
209 pm_runtime_put(dwc
->dev
);
212 int dwc3_send_gadget_generic_command(struct dwc3
*dwc
, unsigned cmd
, u32 param
)
219 dwc3_writel(dwc
->regs
, DWC3_DGCMDPAR
, param
);
220 dwc3_writel(dwc
->regs
, DWC3_DGCMD
, cmd
| DWC3_DGCMD_CMDACT
);
223 reg
= dwc3_readl(dwc
->regs
, DWC3_DGCMD
);
224 if (!(reg
& DWC3_DGCMD_CMDACT
)) {
225 status
= DWC3_DGCMD_STATUS(reg
);
237 trace_dwc3_gadget_generic_cmd(cmd
, param
, status
);
242 static int __dwc3_gadget_wakeup(struct dwc3
*dwc
);
244 int dwc3_send_gadget_ep_cmd(struct dwc3_ep
*dep
, unsigned cmd
,
245 struct dwc3_gadget_ep_cmd_params
*params
)
247 const struct usb_endpoint_descriptor
*desc
= dep
->endpoint
.desc
;
248 struct dwc3
*dwc
= dep
->dwc
;
257 * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
258 * we're issuing an endpoint command, we must check if
259 * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
261 * We will also set SUSPHY bit to what it was before returning as stated
262 * by the same section on Synopsys databook.
264 if (dwc
->gadget
.speed
<= USB_SPEED_HIGH
) {
265 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB2PHYCFG(0));
266 if (unlikely(reg
& DWC3_GUSB2PHYCFG_SUSPHY
)) {
268 reg
&= ~DWC3_GUSB2PHYCFG_SUSPHY
;
269 dwc3_writel(dwc
->regs
, DWC3_GUSB2PHYCFG(0), reg
);
273 if (DWC3_DEPCMD_CMD(cmd
) == DWC3_DEPCMD_STARTTRANSFER
) {
276 needs_wakeup
= (dwc
->link_state
== DWC3_LINK_STATE_U1
||
277 dwc
->link_state
== DWC3_LINK_STATE_U2
||
278 dwc
->link_state
== DWC3_LINK_STATE_U3
);
280 if (unlikely(needs_wakeup
)) {
281 ret
= __dwc3_gadget_wakeup(dwc
);
282 dev_WARN_ONCE(dwc
->dev
, ret
, "wakeup failed --> %d\n",
287 dwc3_writel(dep
->regs
, DWC3_DEPCMDPAR0
, params
->param0
);
288 dwc3_writel(dep
->regs
, DWC3_DEPCMDPAR1
, params
->param1
);
289 dwc3_writel(dep
->regs
, DWC3_DEPCMDPAR2
, params
->param2
);
292 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
293 * not relying on XferNotReady, we can make use of a special "No
294 * Response Update Transfer" command where we should clear both CmdAct
297 * With this, we don't need to wait for command completion and can
298 * straight away issue further commands to the endpoint.
300 * NOTICE: We're making an assumption that control endpoints will never
301 * make use of Update Transfer command. This is a safe assumption
302 * because we can never have more than one request at a time with
303 * Control Endpoints. If anybody changes that assumption, this chunk
304 * needs to be updated accordingly.
306 if (DWC3_DEPCMD_CMD(cmd
) == DWC3_DEPCMD_UPDATETRANSFER
&&
307 !usb_endpoint_xfer_isoc(desc
))
308 cmd
&= ~(DWC3_DEPCMD_CMDIOC
| DWC3_DEPCMD_CMDACT
);
310 cmd
|= DWC3_DEPCMD_CMDACT
;
312 dwc3_writel(dep
->regs
, DWC3_DEPCMD
, cmd
);
314 reg
= dwc3_readl(dep
->regs
, DWC3_DEPCMD
);
315 if (!(reg
& DWC3_DEPCMD_CMDACT
)) {
316 cmd_status
= DWC3_DEPCMD_STATUS(reg
);
318 switch (cmd_status
) {
322 case DEPEVT_TRANSFER_NO_RESOURCE
:
325 case DEPEVT_TRANSFER_BUS_EXPIRY
:
327 * SW issues START TRANSFER command to
328 * isochronous ep with future frame interval. If
329 * future interval time has already passed when
330 * core receives the command, it will respond
331 * with an error status of 'Bus Expiry'.
333 * Instead of always returning -EINVAL, let's
334 * give a hint to the gadget driver that this is
335 * the case by returning -EAGAIN.
340 dev_WARN(dwc
->dev
, "UNKNOWN cmd status\n");
349 cmd_status
= -ETIMEDOUT
;
352 trace_dwc3_gadget_ep_cmd(dep
, cmd
, params
, cmd_status
);
355 switch (DWC3_DEPCMD_CMD(cmd
)) {
356 case DWC3_DEPCMD_STARTTRANSFER
:
357 dep
->flags
|= DWC3_EP_TRANSFER_STARTED
;
359 case DWC3_DEPCMD_ENDTRANSFER
:
360 dep
->flags
&= ~DWC3_EP_TRANSFER_STARTED
;
368 if (unlikely(susphy
)) {
369 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB2PHYCFG(0));
370 reg
|= DWC3_GUSB2PHYCFG_SUSPHY
;
371 dwc3_writel(dwc
->regs
, DWC3_GUSB2PHYCFG(0), reg
);
377 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep
*dep
)
379 struct dwc3
*dwc
= dep
->dwc
;
380 struct dwc3_gadget_ep_cmd_params params
;
381 u32 cmd
= DWC3_DEPCMD_CLEARSTALL
;
384 * As of core revision 2.60a the recommended programming model
385 * is to set the ClearPendIN bit when issuing a Clear Stall EP
386 * command for IN endpoints. This is to prevent an issue where
387 * some (non-compliant) hosts may not send ACK TPs for pending
388 * IN transfers due to a mishandled error condition. Synopsys
391 if (dep
->direction
&& (dwc
->revision
>= DWC3_REVISION_260A
) &&
392 (dwc
->gadget
.speed
>= USB_SPEED_SUPER
))
393 cmd
|= DWC3_DEPCMD_CLEARPENDIN
;
395 memset(¶ms
, 0, sizeof(params
));
397 return dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
400 static dma_addr_t
dwc3_trb_dma_offset(struct dwc3_ep
*dep
,
401 struct dwc3_trb
*trb
)
403 u32 offset
= (char *) trb
- (char *) dep
->trb_pool
;
405 return dep
->trb_pool_dma
+ offset
;
408 static int dwc3_alloc_trb_pool(struct dwc3_ep
*dep
)
410 struct dwc3
*dwc
= dep
->dwc
;
415 dep
->trb_pool
= dma_alloc_coherent(dwc
->sysdev
,
416 sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
,
417 &dep
->trb_pool_dma
, GFP_KERNEL
);
418 if (!dep
->trb_pool
) {
419 dev_err(dep
->dwc
->dev
, "failed to allocate trb pool for %s\n",
427 static void dwc3_free_trb_pool(struct dwc3_ep
*dep
)
429 struct dwc3
*dwc
= dep
->dwc
;
431 dma_free_coherent(dwc
->sysdev
, sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
,
432 dep
->trb_pool
, dep
->trb_pool_dma
);
434 dep
->trb_pool
= NULL
;
435 dep
->trb_pool_dma
= 0;
438 static int dwc3_gadget_set_xfer_resource(struct dwc3
*dwc
, struct dwc3_ep
*dep
);
441 * dwc3_gadget_start_config - Configure EP resources
442 * @dwc: pointer to our controller context structure
443 * @dep: endpoint that is being enabled
445 * The assignment of transfer resources cannot perfectly follow the
446 * data book due to the fact that the controller driver does not have
447 * all knowledge of the configuration in advance. It is given this
448 * information piecemeal by the composite gadget framework after every
449 * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
450 * programming model in this scenario can cause errors. For two
453 * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
454 * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
455 * multiple interfaces.
457 * 2) The databook does not mention doing more DEPXFERCFG for new
458 * endpoint on alt setting (8.1.6).
460 * The following simplified method is used instead:
462 * All hardware endpoints can be assigned a transfer resource and this
463 * setting will stay persistent until either a core reset or
464 * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
465 * do DEPXFERCFG for every hardware endpoint as well. We are
466 * guaranteed that there are as many transfer resources as endpoints.
468 * This function is called for each endpoint when it is being enabled
469 * but is triggered only when called for EP0-out, which always happens
470 * first, and which should only happen in one of the above conditions.
472 static int dwc3_gadget_start_config(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
474 struct dwc3_gadget_ep_cmd_params params
;
482 memset(¶ms
, 0x00, sizeof(params
));
483 cmd
= DWC3_DEPCMD_DEPSTARTCFG
;
485 ret
= dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
489 for (i
= 0; i
< DWC3_ENDPOINTS_NUM
; i
++) {
490 struct dwc3_ep
*dep
= dwc
->eps
[i
];
495 ret
= dwc3_gadget_set_xfer_resource(dwc
, dep
);
503 static int dwc3_gadget_set_ep_config(struct dwc3
*dwc
, struct dwc3_ep
*dep
,
504 bool modify
, bool restore
)
506 const struct usb_ss_ep_comp_descriptor
*comp_desc
;
507 const struct usb_endpoint_descriptor
*desc
;
508 struct dwc3_gadget_ep_cmd_params params
;
510 if (dev_WARN_ONCE(dwc
->dev
, modify
&& restore
,
511 "Can't modify and restore\n"))
514 comp_desc
= dep
->endpoint
.comp_desc
;
515 desc
= dep
->endpoint
.desc
;
517 memset(¶ms
, 0x00, sizeof(params
));
519 params
.param0
= DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc
))
520 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc
));
522 /* Burst size is only needed in SuperSpeed mode */
523 if (dwc
->gadget
.speed
>= USB_SPEED_SUPER
) {
524 u32 burst
= dep
->endpoint
.maxburst
;
525 params
.param0
|= DWC3_DEPCFG_BURST_SIZE(burst
- 1);
529 params
.param0
|= DWC3_DEPCFG_ACTION_MODIFY
;
530 } else if (restore
) {
531 params
.param0
|= DWC3_DEPCFG_ACTION_RESTORE
;
532 params
.param2
|= dep
->saved_state
;
534 params
.param0
|= DWC3_DEPCFG_ACTION_INIT
;
537 if (usb_endpoint_xfer_control(desc
))
538 params
.param1
= DWC3_DEPCFG_XFER_COMPLETE_EN
;
540 if (dep
->number
<= 1 || usb_endpoint_xfer_isoc(desc
))
541 params
.param1
|= DWC3_DEPCFG_XFER_NOT_READY_EN
;
543 if (usb_ss_max_streams(comp_desc
) && usb_endpoint_xfer_bulk(desc
)) {
544 params
.param1
|= DWC3_DEPCFG_STREAM_CAPABLE
545 | DWC3_DEPCFG_STREAM_EVENT_EN
;
546 dep
->stream_capable
= true;
549 if (!usb_endpoint_xfer_control(desc
))
550 params
.param1
|= DWC3_DEPCFG_XFER_IN_PROGRESS_EN
;
553 * We are doing 1:1 mapping for endpoints, meaning
554 * Physical Endpoints 2 maps to Logical Endpoint 2 and
555 * so on. We consider the direction bit as part of the physical
556 * endpoint number. So USB endpoint 0x81 is 0x03.
558 params
.param1
|= DWC3_DEPCFG_EP_NUMBER(dep
->number
);
561 * We must use the lower 16 TX FIFOs even though
565 params
.param0
|= DWC3_DEPCFG_FIFO_NUMBER(dep
->number
>> 1);
567 if (desc
->bInterval
) {
568 params
.param1
|= DWC3_DEPCFG_BINTERVAL_M1(desc
->bInterval
- 1);
569 dep
->interval
= 1 << (desc
->bInterval
- 1);
572 return dwc3_send_gadget_ep_cmd(dep
, DWC3_DEPCMD_SETEPCONFIG
, ¶ms
);
575 static int dwc3_gadget_set_xfer_resource(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
577 struct dwc3_gadget_ep_cmd_params params
;
579 memset(¶ms
, 0x00, sizeof(params
));
581 params
.param0
= DWC3_DEPXFERCFG_NUM_XFER_RES(1);
583 return dwc3_send_gadget_ep_cmd(dep
, DWC3_DEPCMD_SETTRANSFRESOURCE
,
588 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
589 * @dep: endpoint to be initialized
590 * @desc: USB Endpoint Descriptor
592 * Caller should take care of locking
594 static int __dwc3_gadget_ep_enable(struct dwc3_ep
*dep
,
595 bool modify
, bool restore
)
597 const struct usb_endpoint_descriptor
*desc
= dep
->endpoint
.desc
;
598 struct dwc3
*dwc
= dep
->dwc
;
603 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
604 ret
= dwc3_gadget_start_config(dwc
, dep
);
609 ret
= dwc3_gadget_set_ep_config(dwc
, dep
, modify
, restore
);
613 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
614 struct dwc3_trb
*trb_st_hw
;
615 struct dwc3_trb
*trb_link
;
617 dep
->type
= usb_endpoint_type(desc
);
618 dep
->flags
|= DWC3_EP_ENABLED
;
619 dep
->flags
&= ~DWC3_EP_END_TRANSFER_PENDING
;
621 reg
= dwc3_readl(dwc
->regs
, DWC3_DALEPENA
);
622 reg
|= DWC3_DALEPENA_EP(dep
->number
);
623 dwc3_writel(dwc
->regs
, DWC3_DALEPENA
, reg
);
625 init_waitqueue_head(&dep
->wait_end_transfer
);
627 if (usb_endpoint_xfer_control(desc
))
630 /* Initialize the TRB ring */
631 dep
->trb_dequeue
= 0;
632 dep
->trb_enqueue
= 0;
633 memset(dep
->trb_pool
, 0,
634 sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
);
636 /* Link TRB. The HWO bit is never reset */
637 trb_st_hw
= &dep
->trb_pool
[0];
639 trb_link
= &dep
->trb_pool
[DWC3_TRB_NUM
- 1];
640 trb_link
->bpl
= lower_32_bits(dwc3_trb_dma_offset(dep
, trb_st_hw
));
641 trb_link
->bph
= upper_32_bits(dwc3_trb_dma_offset(dep
, trb_st_hw
));
642 trb_link
->ctrl
|= DWC3_TRBCTL_LINK_TRB
;
643 trb_link
->ctrl
|= DWC3_TRB_CTRL_HWO
;
647 * Issue StartTransfer here with no-op TRB so we can always rely on No
648 * Response Update Transfer command.
650 if (usb_endpoint_xfer_bulk(desc
)) {
651 struct dwc3_gadget_ep_cmd_params params
;
652 struct dwc3_trb
*trb
;
656 memset(¶ms
, 0, sizeof(params
));
657 trb
= &dep
->trb_pool
[0];
658 trb_dma
= dwc3_trb_dma_offset(dep
, trb
);
660 params
.param0
= upper_32_bits(trb_dma
);
661 params
.param1
= lower_32_bits(trb_dma
);
663 cmd
= DWC3_DEPCMD_STARTTRANSFER
;
665 ret
= dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
669 dep
->flags
|= DWC3_EP_BUSY
;
671 dep
->resource_index
= dwc3_gadget_ep_get_transfer_index(dep
);
672 WARN_ON_ONCE(!dep
->resource_index
);
677 trace_dwc3_gadget_ep_enable(dep
);
682 static void dwc3_stop_active_transfer(struct dwc3
*dwc
, u32 epnum
, bool force
);
683 static void dwc3_remove_requests(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
685 struct dwc3_request
*req
;
687 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
689 /* - giveback all requests to gadget driver */
690 while (!list_empty(&dep
->started_list
)) {
691 req
= next_request(&dep
->started_list
);
693 dwc3_gadget_giveback(dep
, req
, -ESHUTDOWN
);
696 while (!list_empty(&dep
->pending_list
)) {
697 req
= next_request(&dep
->pending_list
);
699 dwc3_gadget_giveback(dep
, req
, -ESHUTDOWN
);
704 * __dwc3_gadget_ep_disable - Disables a HW endpoint
705 * @dep: the endpoint to disable
707 * This function also removes requests which are currently processed ny the
708 * hardware and those which are not yet scheduled.
709 * Caller should take care of locking.
711 static int __dwc3_gadget_ep_disable(struct dwc3_ep
*dep
)
713 struct dwc3
*dwc
= dep
->dwc
;
716 trace_dwc3_gadget_ep_disable(dep
);
718 dwc3_remove_requests(dwc
, dep
);
720 /* make sure HW endpoint isn't stalled */
721 if (dep
->flags
& DWC3_EP_STALL
)
722 __dwc3_gadget_ep_set_halt(dep
, 0, false);
724 reg
= dwc3_readl(dwc
->regs
, DWC3_DALEPENA
);
725 reg
&= ~DWC3_DALEPENA_EP(dep
->number
);
726 dwc3_writel(dwc
->regs
, DWC3_DALEPENA
, reg
);
728 dep
->stream_capable
= false;
730 dep
->flags
&= DWC3_EP_END_TRANSFER_PENDING
;
732 /* Clear out the ep descriptors for non-ep0 */
733 if (dep
->number
> 1) {
734 dep
->endpoint
.comp_desc
= NULL
;
735 dep
->endpoint
.desc
= NULL
;
741 /* -------------------------------------------------------------------------- */
743 static int dwc3_gadget_ep0_enable(struct usb_ep
*ep
,
744 const struct usb_endpoint_descriptor
*desc
)
749 static int dwc3_gadget_ep0_disable(struct usb_ep
*ep
)
754 /* -------------------------------------------------------------------------- */
756 static int dwc3_gadget_ep_enable(struct usb_ep
*ep
,
757 const struct usb_endpoint_descriptor
*desc
)
764 if (!ep
|| !desc
|| desc
->bDescriptorType
!= USB_DT_ENDPOINT
) {
765 pr_debug("dwc3: invalid parameters\n");
769 if (!desc
->wMaxPacketSize
) {
770 pr_debug("dwc3: missing wMaxPacketSize\n");
774 dep
= to_dwc3_ep(ep
);
777 if (dev_WARN_ONCE(dwc
->dev
, dep
->flags
& DWC3_EP_ENABLED
,
778 "%s is already enabled\n",
782 spin_lock_irqsave(&dwc
->lock
, flags
);
783 ret
= __dwc3_gadget_ep_enable(dep
, false, false);
784 spin_unlock_irqrestore(&dwc
->lock
, flags
);
789 static int dwc3_gadget_ep_disable(struct usb_ep
*ep
)
797 pr_debug("dwc3: invalid parameters\n");
801 dep
= to_dwc3_ep(ep
);
804 if (dev_WARN_ONCE(dwc
->dev
, !(dep
->flags
& DWC3_EP_ENABLED
),
805 "%s is already disabled\n",
809 spin_lock_irqsave(&dwc
->lock
, flags
);
810 ret
= __dwc3_gadget_ep_disable(dep
);
811 spin_unlock_irqrestore(&dwc
->lock
, flags
);
816 static struct usb_request
*dwc3_gadget_ep_alloc_request(struct usb_ep
*ep
,
819 struct dwc3_request
*req
;
820 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
822 req
= kzalloc(sizeof(*req
), gfp_flags
);
826 req
->epnum
= dep
->number
;
829 dep
->allocated_requests
++;
831 trace_dwc3_alloc_request(req
);
833 return &req
->request
;
836 static void dwc3_gadget_ep_free_request(struct usb_ep
*ep
,
837 struct usb_request
*request
)
839 struct dwc3_request
*req
= to_dwc3_request(request
);
840 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
842 dep
->allocated_requests
--;
843 trace_dwc3_free_request(req
);
847 static u32
dwc3_calc_trbs_left(struct dwc3_ep
*dep
);
850 * dwc3_prepare_one_trb - setup one TRB from one request
851 * @dep: endpoint for which this request is prepared
852 * @req: dwc3_request pointer
854 static void dwc3_prepare_one_trb(struct dwc3_ep
*dep
,
855 struct dwc3_request
*req
, dma_addr_t dma
,
856 unsigned length
, unsigned chain
, unsigned node
)
858 struct dwc3_trb
*trb
;
859 struct dwc3
*dwc
= dep
->dwc
;
860 struct usb_gadget
*gadget
= &dwc
->gadget
;
861 enum usb_device_speed speed
= gadget
->speed
;
863 trb
= &dep
->trb_pool
[dep
->trb_enqueue
];
866 dwc3_gadget_move_started_request(req
);
868 req
->trb_dma
= dwc3_trb_dma_offset(dep
, trb
);
869 dep
->queued_requests
++;
872 dwc3_ep_inc_enq(dep
);
874 trb
->size
= DWC3_TRB_SIZE_LENGTH(length
);
875 trb
->bpl
= lower_32_bits(dma
);
876 trb
->bph
= upper_32_bits(dma
);
878 switch (usb_endpoint_type(dep
->endpoint
.desc
)) {
879 case USB_ENDPOINT_XFER_CONTROL
:
880 trb
->ctrl
= DWC3_TRBCTL_CONTROL_SETUP
;
883 case USB_ENDPOINT_XFER_ISOC
:
885 trb
->ctrl
= DWC3_TRBCTL_ISOCHRONOUS_FIRST
;
887 if (speed
== USB_SPEED_HIGH
) {
888 struct usb_ep
*ep
= &dep
->endpoint
;
889 trb
->size
|= DWC3_TRB_SIZE_PCM1(ep
->mult
- 1);
892 trb
->ctrl
= DWC3_TRBCTL_ISOCHRONOUS
;
895 /* always enable Interrupt on Missed ISOC */
896 trb
->ctrl
|= DWC3_TRB_CTRL_ISP_IMI
;
899 case USB_ENDPOINT_XFER_BULK
:
900 case USB_ENDPOINT_XFER_INT
:
901 trb
->ctrl
= DWC3_TRBCTL_NORMAL
;
905 * This is only possible with faulty memory because we
906 * checked it already :)
908 dev_WARN(dwc
->dev
, "Unknown endpoint type %d\n",
909 usb_endpoint_type(dep
->endpoint
.desc
));
912 /* always enable Continue on Short Packet */
913 if (usb_endpoint_dir_out(dep
->endpoint
.desc
)) {
914 trb
->ctrl
|= DWC3_TRB_CTRL_CSP
;
916 if (req
->request
.short_not_ok
)
917 trb
->ctrl
|= DWC3_TRB_CTRL_ISP_IMI
;
920 if ((!req
->request
.no_interrupt
&& !chain
) ||
921 (dwc3_calc_trbs_left(dep
) == 0))
922 trb
->ctrl
|= DWC3_TRB_CTRL_IOC
;
925 trb
->ctrl
|= DWC3_TRB_CTRL_CHN
;
927 if (usb_endpoint_xfer_bulk(dep
->endpoint
.desc
) && dep
->stream_capable
)
928 trb
->ctrl
|= DWC3_TRB_CTRL_SID_SOFN(req
->request
.stream_id
);
930 trb
->ctrl
|= DWC3_TRB_CTRL_HWO
;
932 trace_dwc3_prepare_trb(dep
, trb
);
936 * dwc3_ep_prev_trb() - Returns the previous TRB in the ring
937 * @dep: The endpoint with the TRB ring
938 * @index: The index of the current TRB in the ring
940 * Returns the TRB prior to the one pointed to by the index. If the
941 * index is 0, we will wrap backwards, skip the link TRB, and return
942 * the one just before that.
944 static struct dwc3_trb
*dwc3_ep_prev_trb(struct dwc3_ep
*dep
, u8 index
)
949 tmp
= DWC3_TRB_NUM
- 1;
951 return &dep
->trb_pool
[tmp
- 1];
954 static u32
dwc3_calc_trbs_left(struct dwc3_ep
*dep
)
956 struct dwc3_trb
*tmp
;
957 struct dwc3
*dwc
= dep
->dwc
;
961 * If enqueue & dequeue are equal than it is either full or empty.
963 * One way to know for sure is if the TRB right before us has HWO bit
964 * set or not. If it has, then we're definitely full and can't fit any
965 * more transfers in our ring.
967 if (dep
->trb_enqueue
== dep
->trb_dequeue
) {
968 tmp
= dwc3_ep_prev_trb(dep
, dep
->trb_enqueue
);
969 if (dev_WARN_ONCE(dwc
->dev
, tmp
->ctrl
& DWC3_TRB_CTRL_HWO
,
970 "%s No TRBS left\n", dep
->name
))
973 return DWC3_TRB_NUM
- 1;
976 trbs_left
= dep
->trb_dequeue
- dep
->trb_enqueue
;
977 trbs_left
&= (DWC3_TRB_NUM
- 1);
979 if (dep
->trb_dequeue
< dep
->trb_enqueue
)
985 static void dwc3_prepare_one_trb_sg(struct dwc3_ep
*dep
,
986 struct dwc3_request
*req
)
988 struct scatterlist
*sg
= req
->sg
;
989 struct scatterlist
*s
;
994 for_each_sg(sg
, s
, req
->num_pending_sgs
, i
) {
995 unsigned chain
= true;
997 length
= sg_dma_len(s
);
998 dma
= sg_dma_address(s
);
1003 dwc3_prepare_one_trb(dep
, req
, dma
, length
,
1006 if (!dwc3_calc_trbs_left(dep
))
1011 static void dwc3_prepare_one_trb_linear(struct dwc3_ep
*dep
,
1012 struct dwc3_request
*req
)
1014 unsigned int length
;
1017 dma
= req
->request
.dma
;
1018 length
= req
->request
.length
;
1020 dwc3_prepare_one_trb(dep
, req
, dma
, length
,
1025 * dwc3_prepare_trbs - setup TRBs from requests
1026 * @dep: endpoint for which requests are being prepared
1028 * The function goes through the requests list and sets up TRBs for the
1029 * transfers. The function returns once there are no more TRBs available or
1030 * it runs out of requests.
1032 static void dwc3_prepare_trbs(struct dwc3_ep
*dep
)
1034 struct dwc3_request
*req
, *n
;
1036 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM
);
1038 if (!dwc3_calc_trbs_left(dep
))
1042 * We can get in a situation where there's a request in the started list
1043 * but there weren't enough TRBs to fully kick it in the first time
1044 * around, so it has been waiting for more TRBs to be freed up.
1046 * In that case, we should check if we have a request with pending_sgs
1047 * in the started list and prepare TRBs for that request first,
1048 * otherwise we will prepare TRBs completely out of order and that will
1051 list_for_each_entry(req
, &dep
->started_list
, list
) {
1052 if (req
->num_pending_sgs
> 0)
1053 dwc3_prepare_one_trb_sg(dep
, req
);
1055 if (!dwc3_calc_trbs_left(dep
))
1059 list_for_each_entry_safe(req
, n
, &dep
->pending_list
, list
) {
1060 if (req
->num_pending_sgs
> 0)
1061 dwc3_prepare_one_trb_sg(dep
, req
);
1063 dwc3_prepare_one_trb_linear(dep
, req
);
1065 if (!dwc3_calc_trbs_left(dep
))
1070 static int __dwc3_gadget_kick_transfer(struct dwc3_ep
*dep
, u16 cmd_param
)
1072 struct dwc3_gadget_ep_cmd_params params
;
1073 struct dwc3_request
*req
;
1078 starting
= !(dep
->flags
& DWC3_EP_BUSY
);
1080 dwc3_prepare_trbs(dep
);
1081 req
= next_request(&dep
->started_list
);
1083 dep
->flags
|= DWC3_EP_PENDING_REQUEST
;
1087 memset(¶ms
, 0, sizeof(params
));
1090 params
.param0
= upper_32_bits(req
->trb_dma
);
1091 params
.param1
= lower_32_bits(req
->trb_dma
);
1092 cmd
= DWC3_DEPCMD_STARTTRANSFER
|
1093 DWC3_DEPCMD_PARAM(cmd_param
);
1095 cmd
= DWC3_DEPCMD_UPDATETRANSFER
|
1096 DWC3_DEPCMD_PARAM(dep
->resource_index
);
1099 ret
= dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
1102 * FIXME we need to iterate over the list of requests
1103 * here and stop, unmap, free and del each of the linked
1104 * requests instead of what we do now.
1107 memset(req
->trb
, 0, sizeof(struct dwc3_trb
));
1108 dep
->queued_requests
--;
1109 dwc3_gadget_giveback(dep
, req
, ret
);
1113 dep
->flags
|= DWC3_EP_BUSY
;
1116 dep
->resource_index
= dwc3_gadget_ep_get_transfer_index(dep
);
1117 WARN_ON_ONCE(!dep
->resource_index
);
1123 static int __dwc3_gadget_get_frame(struct dwc3
*dwc
)
1127 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1128 return DWC3_DSTS_SOFFN(reg
);
1131 static void __dwc3_gadget_start_isoc(struct dwc3
*dwc
,
1132 struct dwc3_ep
*dep
, u32 cur_uf
)
1136 if (list_empty(&dep
->pending_list
)) {
1137 dev_info(dwc
->dev
, "%s: ran out of requests\n",
1139 dep
->flags
|= DWC3_EP_PENDING_REQUEST
;
1143 /* 4 micro frames in the future */
1144 uf
= cur_uf
+ dep
->interval
* 4;
1146 __dwc3_gadget_kick_transfer(dep
, uf
);
1149 static void dwc3_gadget_start_isoc(struct dwc3
*dwc
,
1150 struct dwc3_ep
*dep
, const struct dwc3_event_depevt
*event
)
1154 mask
= ~(dep
->interval
- 1);
1155 cur_uf
= event
->parameters
& mask
;
1157 __dwc3_gadget_start_isoc(dwc
, dep
, cur_uf
);
1160 static int __dwc3_gadget_ep_queue(struct dwc3_ep
*dep
, struct dwc3_request
*req
)
1162 struct dwc3
*dwc
= dep
->dwc
;
1165 if (!dep
->endpoint
.desc
) {
1166 dev_err(dwc
->dev
, "%s: can't queue to disabled endpoint\n",
1171 if (WARN(req
->dep
!= dep
, "request %p belongs to '%s'\n",
1172 &req
->request
, req
->dep
->name
)) {
1173 dev_err(dwc
->dev
, "%s: request %p belongs to '%s'\n",
1174 dep
->name
, &req
->request
, req
->dep
->name
);
1178 pm_runtime_get(dwc
->dev
);
1180 req
->request
.actual
= 0;
1181 req
->request
.status
= -EINPROGRESS
;
1182 req
->direction
= dep
->direction
;
1183 req
->epnum
= dep
->number
;
1185 trace_dwc3_ep_queue(req
);
1187 ret
= usb_gadget_map_request_by_dev(dwc
->sysdev
, &req
->request
,
1192 req
->sg
= req
->request
.sg
;
1193 req
->num_pending_sgs
= req
->request
.num_mapped_sgs
;
1195 list_add_tail(&req
->list
, &dep
->pending_list
);
1198 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1199 * wait for a XferNotReady event so we will know what's the current
1200 * (micro-)frame number.
1202 * Without this trick, we are very, very likely gonna get Bus Expiry
1203 * errors which will force us issue EndTransfer command.
1205 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1206 if ((dep
->flags
& DWC3_EP_PENDING_REQUEST
)) {
1207 if (dep
->flags
& DWC3_EP_TRANSFER_STARTED
) {
1208 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
1209 dep
->flags
= DWC3_EP_ENABLED
;
1213 cur_uf
= __dwc3_gadget_get_frame(dwc
);
1214 __dwc3_gadget_start_isoc(dwc
, dep
, cur_uf
);
1215 dep
->flags
&= ~DWC3_EP_PENDING_REQUEST
;
1221 if (!dwc3_calc_trbs_left(dep
))
1224 ret
= __dwc3_gadget_kick_transfer(dep
, 0);
1231 static void __dwc3_gadget_ep_zlp_complete(struct usb_ep
*ep
,
1232 struct usb_request
*request
)
1234 dwc3_gadget_ep_free_request(ep
, request
);
1237 static int __dwc3_gadget_ep_queue_zlp(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
1239 struct dwc3_request
*req
;
1240 struct usb_request
*request
;
1241 struct usb_ep
*ep
= &dep
->endpoint
;
1243 request
= dwc3_gadget_ep_alloc_request(ep
, GFP_ATOMIC
);
1247 request
->length
= 0;
1248 request
->buf
= dwc
->zlp_buf
;
1249 request
->complete
= __dwc3_gadget_ep_zlp_complete
;
1251 req
= to_dwc3_request(request
);
1253 return __dwc3_gadget_ep_queue(dep
, req
);
1256 static int dwc3_gadget_ep_queue(struct usb_ep
*ep
, struct usb_request
*request
,
1259 struct dwc3_request
*req
= to_dwc3_request(request
);
1260 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1261 struct dwc3
*dwc
= dep
->dwc
;
1263 unsigned long flags
;
1267 spin_lock_irqsave(&dwc
->lock
, flags
);
1268 ret
= __dwc3_gadget_ep_queue(dep
, req
);
1271 * Okay, here's the thing, if gadget driver has requested for a ZLP by
1272 * setting request->zero, instead of doing magic, we will just queue an
1273 * extra usb_request ourselves so that it gets handled the same way as
1274 * any other request.
1276 if (ret
== 0 && request
->zero
&& request
->length
&&
1277 (request
->length
% ep
->maxpacket
== 0))
1278 ret
= __dwc3_gadget_ep_queue_zlp(dwc
, dep
);
1280 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1285 static int dwc3_gadget_ep_dequeue(struct usb_ep
*ep
,
1286 struct usb_request
*request
)
1288 struct dwc3_request
*req
= to_dwc3_request(request
);
1289 struct dwc3_request
*r
= NULL
;
1291 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1292 struct dwc3
*dwc
= dep
->dwc
;
1294 unsigned long flags
;
1297 trace_dwc3_ep_dequeue(req
);
1299 spin_lock_irqsave(&dwc
->lock
, flags
);
1301 list_for_each_entry(r
, &dep
->pending_list
, list
) {
1307 list_for_each_entry(r
, &dep
->started_list
, list
) {
1312 /* wait until it is processed */
1313 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
1316 dev_err(dwc
->dev
, "request %p was not queued to %s\n",
1323 /* giveback the request */
1324 dwc3_gadget_giveback(dep
, req
, -ECONNRESET
);
1327 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1332 int __dwc3_gadget_ep_set_halt(struct dwc3_ep
*dep
, int value
, int protocol
)
1334 struct dwc3_gadget_ep_cmd_params params
;
1335 struct dwc3
*dwc
= dep
->dwc
;
1338 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1339 dev_err(dwc
->dev
, "%s is of Isochronous type\n", dep
->name
);
1343 memset(¶ms
, 0x00, sizeof(params
));
1346 struct dwc3_trb
*trb
;
1348 unsigned transfer_in_flight
;
1351 if (dep
->flags
& DWC3_EP_STALL
)
1354 if (dep
->number
> 1)
1355 trb
= dwc3_ep_prev_trb(dep
, dep
->trb_enqueue
);
1357 trb
= &dwc
->ep0_trb
[dep
->trb_enqueue
];
1359 transfer_in_flight
= trb
->ctrl
& DWC3_TRB_CTRL_HWO
;
1360 started
= !list_empty(&dep
->started_list
);
1362 if (!protocol
&& ((dep
->direction
&& transfer_in_flight
) ||
1363 (!dep
->direction
&& started
))) {
1367 ret
= dwc3_send_gadget_ep_cmd(dep
, DWC3_DEPCMD_SETSTALL
,
1370 dev_err(dwc
->dev
, "failed to set STALL on %s\n",
1373 dep
->flags
|= DWC3_EP_STALL
;
1375 if (!(dep
->flags
& DWC3_EP_STALL
))
1378 ret
= dwc3_send_clear_stall_ep_cmd(dep
);
1380 dev_err(dwc
->dev
, "failed to clear STALL on %s\n",
1383 dep
->flags
&= ~(DWC3_EP_STALL
| DWC3_EP_WEDGE
);
1389 static int dwc3_gadget_ep_set_halt(struct usb_ep
*ep
, int value
)
1391 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1392 struct dwc3
*dwc
= dep
->dwc
;
1394 unsigned long flags
;
1398 spin_lock_irqsave(&dwc
->lock
, flags
);
1399 ret
= __dwc3_gadget_ep_set_halt(dep
, value
, false);
1400 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1405 static int dwc3_gadget_ep_set_wedge(struct usb_ep
*ep
)
1407 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1408 struct dwc3
*dwc
= dep
->dwc
;
1409 unsigned long flags
;
1412 spin_lock_irqsave(&dwc
->lock
, flags
);
1413 dep
->flags
|= DWC3_EP_WEDGE
;
1415 if (dep
->number
== 0 || dep
->number
== 1)
1416 ret
= __dwc3_gadget_ep0_set_halt(ep
, 1);
1418 ret
= __dwc3_gadget_ep_set_halt(dep
, 1, false);
1419 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1424 /* -------------------------------------------------------------------------- */
1426 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc
= {
1427 .bLength
= USB_DT_ENDPOINT_SIZE
,
1428 .bDescriptorType
= USB_DT_ENDPOINT
,
1429 .bmAttributes
= USB_ENDPOINT_XFER_CONTROL
,
1432 static const struct usb_ep_ops dwc3_gadget_ep0_ops
= {
1433 .enable
= dwc3_gadget_ep0_enable
,
1434 .disable
= dwc3_gadget_ep0_disable
,
1435 .alloc_request
= dwc3_gadget_ep_alloc_request
,
1436 .free_request
= dwc3_gadget_ep_free_request
,
1437 .queue
= dwc3_gadget_ep0_queue
,
1438 .dequeue
= dwc3_gadget_ep_dequeue
,
1439 .set_halt
= dwc3_gadget_ep0_set_halt
,
1440 .set_wedge
= dwc3_gadget_ep_set_wedge
,
1443 static const struct usb_ep_ops dwc3_gadget_ep_ops
= {
1444 .enable
= dwc3_gadget_ep_enable
,
1445 .disable
= dwc3_gadget_ep_disable
,
1446 .alloc_request
= dwc3_gadget_ep_alloc_request
,
1447 .free_request
= dwc3_gadget_ep_free_request
,
1448 .queue
= dwc3_gadget_ep_queue
,
1449 .dequeue
= dwc3_gadget_ep_dequeue
,
1450 .set_halt
= dwc3_gadget_ep_set_halt
,
1451 .set_wedge
= dwc3_gadget_ep_set_wedge
,
1454 /* -------------------------------------------------------------------------- */
1456 static int dwc3_gadget_get_frame(struct usb_gadget
*g
)
1458 struct dwc3
*dwc
= gadget_to_dwc(g
);
1460 return __dwc3_gadget_get_frame(dwc
);
1463 static int __dwc3_gadget_wakeup(struct dwc3
*dwc
)
1474 * According to the Databook Remote wakeup request should
1475 * be issued only when the device is in early suspend state.
1477 * We can check that via USB Link State bits in DSTS register.
1479 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1481 speed
= reg
& DWC3_DSTS_CONNECTSPD
;
1482 if ((speed
== DWC3_DSTS_SUPERSPEED
) ||
1483 (speed
== DWC3_DSTS_SUPERSPEED_PLUS
))
1486 link_state
= DWC3_DSTS_USBLNKST(reg
);
1488 switch (link_state
) {
1489 case DWC3_LINK_STATE_RX_DET
: /* in HS, means Early Suspend */
1490 case DWC3_LINK_STATE_U3
: /* in HS, means SUSPEND */
1496 ret
= dwc3_gadget_set_link_state(dwc
, DWC3_LINK_STATE_RECOV
);
1498 dev_err(dwc
->dev
, "failed to put link in Recovery\n");
1502 /* Recent versions do this automatically */
1503 if (dwc
->revision
< DWC3_REVISION_194A
) {
1504 /* write zeroes to Link Change Request */
1505 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1506 reg
&= ~DWC3_DCTL_ULSTCHNGREQ_MASK
;
1507 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1510 /* poll until Link State changes to ON */
1514 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1516 /* in HS, means ON */
1517 if (DWC3_DSTS_USBLNKST(reg
) == DWC3_LINK_STATE_U0
)
1521 if (DWC3_DSTS_USBLNKST(reg
) != DWC3_LINK_STATE_U0
) {
1522 dev_err(dwc
->dev
, "failed to send remote wakeup\n");
1529 static int dwc3_gadget_wakeup(struct usb_gadget
*g
)
1531 struct dwc3
*dwc
= gadget_to_dwc(g
);
1532 unsigned long flags
;
1535 spin_lock_irqsave(&dwc
->lock
, flags
);
1536 ret
= __dwc3_gadget_wakeup(dwc
);
1537 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1542 static int dwc3_gadget_set_selfpowered(struct usb_gadget
*g
,
1545 struct dwc3
*dwc
= gadget_to_dwc(g
);
1546 unsigned long flags
;
1548 spin_lock_irqsave(&dwc
->lock
, flags
);
1549 g
->is_selfpowered
= !!is_selfpowered
;
1550 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1555 static int dwc3_gadget_run_stop(struct dwc3
*dwc
, int is_on
, int suspend
)
1560 if (pm_runtime_suspended(dwc
->dev
))
1563 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1565 if (dwc
->revision
<= DWC3_REVISION_187A
) {
1566 reg
&= ~DWC3_DCTL_TRGTULST_MASK
;
1567 reg
|= DWC3_DCTL_TRGTULST_RX_DET
;
1570 if (dwc
->revision
>= DWC3_REVISION_194A
)
1571 reg
&= ~DWC3_DCTL_KEEP_CONNECT
;
1572 reg
|= DWC3_DCTL_RUN_STOP
;
1574 if (dwc
->has_hibernation
)
1575 reg
|= DWC3_DCTL_KEEP_CONNECT
;
1577 dwc
->pullups_connected
= true;
1579 reg
&= ~DWC3_DCTL_RUN_STOP
;
1581 if (dwc
->has_hibernation
&& !suspend
)
1582 reg
&= ~DWC3_DCTL_KEEP_CONNECT
;
1584 dwc
->pullups_connected
= false;
1587 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1590 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1591 reg
&= DWC3_DSTS_DEVCTRLHLT
;
1592 } while (--timeout
&& !(!is_on
^ !reg
));
1600 static int dwc3_gadget_pullup(struct usb_gadget
*g
, int is_on
)
1602 struct dwc3
*dwc
= gadget_to_dwc(g
);
1603 unsigned long flags
;
1609 * Per databook, when we want to stop the gadget, if a control transfer
1610 * is still in process, complete it and get the core into setup phase.
1612 if (!is_on
&& dwc
->ep0state
!= EP0_SETUP_PHASE
) {
1613 reinit_completion(&dwc
->ep0_in_setup
);
1615 ret
= wait_for_completion_timeout(&dwc
->ep0_in_setup
,
1616 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT
));
1618 dev_err(dwc
->dev
, "timed out waiting for SETUP phase\n");
1623 spin_lock_irqsave(&dwc
->lock
, flags
);
1624 ret
= dwc3_gadget_run_stop(dwc
, is_on
, false);
1625 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1630 static void dwc3_gadget_enable_irq(struct dwc3
*dwc
)
1634 /* Enable all but Start and End of Frame IRQs */
1635 reg
= (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN
|
1636 DWC3_DEVTEN_EVNTOVERFLOWEN
|
1637 DWC3_DEVTEN_CMDCMPLTEN
|
1638 DWC3_DEVTEN_ERRTICERREN
|
1639 DWC3_DEVTEN_WKUPEVTEN
|
1640 DWC3_DEVTEN_CONNECTDONEEN
|
1641 DWC3_DEVTEN_USBRSTEN
|
1642 DWC3_DEVTEN_DISCONNEVTEN
);
1644 if (dwc
->revision
< DWC3_REVISION_250A
)
1645 reg
|= DWC3_DEVTEN_ULSTCNGEN
;
1647 dwc3_writel(dwc
->regs
, DWC3_DEVTEN
, reg
);
1650 static void dwc3_gadget_disable_irq(struct dwc3
*dwc
)
1652 /* mask all interrupts */
1653 dwc3_writel(dwc
->regs
, DWC3_DEVTEN
, 0x00);
1656 static irqreturn_t
dwc3_interrupt(int irq
, void *_dwc
);
1657 static irqreturn_t
dwc3_thread_interrupt(int irq
, void *_dwc
);
1660 * dwc3_gadget_setup_nump - Calculate and initialize NUMP field of DCFG
1661 * dwc: pointer to our context structure
1663 * The following looks like complex but it's actually very simple. In order to
1664 * calculate the number of packets we can burst at once on OUT transfers, we're
1665 * gonna use RxFIFO size.
1667 * To calculate RxFIFO size we need two numbers:
1668 * MDWIDTH = size, in bits, of the internal memory bus
1669 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1671 * Given these two numbers, the formula is simple:
1673 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1675 * 24 bytes is for 3x SETUP packets
1676 * 16 bytes is a clock domain crossing tolerance
1678 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1680 static void dwc3_gadget_setup_nump(struct dwc3
*dwc
)
1687 ram2_depth
= DWC3_GHWPARAMS7_RAM2_DEPTH(dwc
->hwparams
.hwparams7
);
1688 mdwidth
= DWC3_GHWPARAMS0_MDWIDTH(dwc
->hwparams
.hwparams0
);
1690 nump
= ((ram2_depth
* mdwidth
/ 8) - 24 - 16) / 1024;
1691 nump
= min_t(u32
, nump
, 16);
1694 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
1695 reg
&= ~DWC3_DCFG_NUMP_MASK
;
1696 reg
|= nump
<< DWC3_DCFG_NUMP_SHIFT
;
1697 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
1700 static int __dwc3_gadget_start(struct dwc3
*dwc
)
1702 struct dwc3_ep
*dep
;
1707 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
1708 * the core supports IMOD, disable it.
1710 if (dwc
->imod_interval
) {
1711 dwc3_writel(dwc
->regs
, DWC3_DEV_IMOD(0), dwc
->imod_interval
);
1712 dwc3_writel(dwc
->regs
, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB
);
1713 } else if (dwc3_has_imod(dwc
)) {
1714 dwc3_writel(dwc
->regs
, DWC3_DEV_IMOD(0), 0);
1717 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
1718 reg
&= ~(DWC3_DCFG_SPEED_MASK
);
1721 * WORKAROUND: DWC3 revision < 2.20a have an issue
1722 * which would cause metastability state on Run/Stop
1723 * bit if we try to force the IP to USB2-only mode.
1725 * Because of that, we cannot configure the IP to any
1726 * speed other than the SuperSpeed
1730 * STAR#9000525659: Clock Domain Crossing on DCTL in
1733 if (dwc
->revision
< DWC3_REVISION_220A
) {
1734 reg
|= DWC3_DCFG_SUPERSPEED
;
1736 switch (dwc
->maximum_speed
) {
1738 reg
|= DWC3_DCFG_LOWSPEED
;
1740 case USB_SPEED_FULL
:
1741 reg
|= DWC3_DCFG_FULLSPEED
;
1743 case USB_SPEED_HIGH
:
1744 reg
|= DWC3_DCFG_HIGHSPEED
;
1746 case USB_SPEED_SUPER_PLUS
:
1747 reg
|= DWC3_DCFG_SUPERSPEED_PLUS
;
1750 dev_err(dwc
->dev
, "invalid dwc->maximum_speed (%d)\n",
1751 dwc
->maximum_speed
);
1753 case USB_SPEED_SUPER
:
1754 reg
|= DWC3_DCFG_SUPERSPEED
;
1758 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
1761 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1762 * field instead of letting dwc3 itself calculate that automatically.
1764 * This way, we maximize the chances that we'll be able to get several
1765 * bursts of data without going through any sort of endpoint throttling.
1767 reg
= dwc3_readl(dwc
->regs
, DWC3_GRXTHRCFG
);
1768 reg
&= ~DWC3_GRXTHRCFG_PKTCNTSEL
;
1769 dwc3_writel(dwc
->regs
, DWC3_GRXTHRCFG
, reg
);
1771 dwc3_gadget_setup_nump(dwc
);
1773 /* Start with SuperSpeed Default */
1774 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
1777 ret
= __dwc3_gadget_ep_enable(dep
, false, false);
1779 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
1784 ret
= __dwc3_gadget_ep_enable(dep
, false, false);
1786 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
1790 /* begin to receive SETUP packets */
1791 dwc
->ep0state
= EP0_SETUP_PHASE
;
1792 dwc3_ep0_out_start(dwc
);
1794 dwc3_gadget_enable_irq(dwc
);
1799 __dwc3_gadget_ep_disable(dwc
->eps
[0]);
1805 static int dwc3_gadget_start(struct usb_gadget
*g
,
1806 struct usb_gadget_driver
*driver
)
1808 struct dwc3
*dwc
= gadget_to_dwc(g
);
1809 unsigned long flags
;
1813 irq
= dwc
->irq_gadget
;
1814 ret
= request_threaded_irq(irq
, dwc3_interrupt
, dwc3_thread_interrupt
,
1815 IRQF_SHARED
, "dwc3", dwc
->ev_buf
);
1817 dev_err(dwc
->dev
, "failed to request irq #%d --> %d\n",
1822 spin_lock_irqsave(&dwc
->lock
, flags
);
1823 if (dwc
->gadget_driver
) {
1824 dev_err(dwc
->dev
, "%s is already bound to %s\n",
1826 dwc
->gadget_driver
->driver
.name
);
1831 dwc
->gadget_driver
= driver
;
1833 if (pm_runtime_active(dwc
->dev
))
1834 __dwc3_gadget_start(dwc
);
1836 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1841 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1848 static void __dwc3_gadget_stop(struct dwc3
*dwc
)
1850 dwc3_gadget_disable_irq(dwc
);
1851 __dwc3_gadget_ep_disable(dwc
->eps
[0]);
1852 __dwc3_gadget_ep_disable(dwc
->eps
[1]);
1855 static int dwc3_gadget_stop(struct usb_gadget
*g
)
1857 struct dwc3
*dwc
= gadget_to_dwc(g
);
1858 unsigned long flags
;
1861 spin_lock_irqsave(&dwc
->lock
, flags
);
1863 if (pm_runtime_suspended(dwc
->dev
))
1866 __dwc3_gadget_stop(dwc
);
1868 for (epnum
= 2; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
1869 struct dwc3_ep
*dep
= dwc
->eps
[epnum
];
1874 if (!(dep
->flags
& DWC3_EP_END_TRANSFER_PENDING
))
1877 wait_event_lock_irq(dep
->wait_end_transfer
,
1878 !(dep
->flags
& DWC3_EP_END_TRANSFER_PENDING
),
1883 dwc
->gadget_driver
= NULL
;
1884 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1886 free_irq(dwc
->irq_gadget
, dwc
->ev_buf
);
1891 static const struct usb_gadget_ops dwc3_gadget_ops
= {
1892 .get_frame
= dwc3_gadget_get_frame
,
1893 .wakeup
= dwc3_gadget_wakeup
,
1894 .set_selfpowered
= dwc3_gadget_set_selfpowered
,
1895 .pullup
= dwc3_gadget_pullup
,
1896 .udc_start
= dwc3_gadget_start
,
1897 .udc_stop
= dwc3_gadget_stop
,
1900 /* -------------------------------------------------------------------------- */
1902 static int dwc3_gadget_init_hw_endpoints(struct dwc3
*dwc
,
1903 u8 num
, u32 direction
)
1905 struct dwc3_ep
*dep
;
1908 for (i
= 0; i
< num
; i
++) {
1909 u8 epnum
= (i
<< 1) | (direction
? 1 : 0);
1911 dep
= kzalloc(sizeof(*dep
), GFP_KERNEL
);
1916 dep
->number
= epnum
;
1917 dep
->direction
= !!direction
;
1918 dep
->regs
= dwc
->regs
+ DWC3_DEP_BASE(epnum
);
1919 dwc
->eps
[epnum
] = dep
;
1921 snprintf(dep
->name
, sizeof(dep
->name
), "ep%d%s", epnum
>> 1,
1922 (epnum
& 1) ? "in" : "out");
1924 dep
->endpoint
.name
= dep
->name
;
1926 if (!(dep
->number
> 1)) {
1927 dep
->endpoint
.desc
= &dwc3_gadget_ep0_desc
;
1928 dep
->endpoint
.comp_desc
= NULL
;
1931 spin_lock_init(&dep
->lock
);
1933 if (epnum
== 0 || epnum
== 1) {
1934 usb_ep_set_maxpacket_limit(&dep
->endpoint
, 512);
1935 dep
->endpoint
.maxburst
= 1;
1936 dep
->endpoint
.ops
= &dwc3_gadget_ep0_ops
;
1938 dwc
->gadget
.ep0
= &dep
->endpoint
;
1942 usb_ep_set_maxpacket_limit(&dep
->endpoint
, 1024);
1943 dep
->endpoint
.max_streams
= 15;
1944 dep
->endpoint
.ops
= &dwc3_gadget_ep_ops
;
1945 list_add_tail(&dep
->endpoint
.ep_list
,
1946 &dwc
->gadget
.ep_list
);
1948 ret
= dwc3_alloc_trb_pool(dep
);
1953 if (epnum
== 0 || epnum
== 1) {
1954 dep
->endpoint
.caps
.type_control
= true;
1956 dep
->endpoint
.caps
.type_iso
= true;
1957 dep
->endpoint
.caps
.type_bulk
= true;
1958 dep
->endpoint
.caps
.type_int
= true;
1961 dep
->endpoint
.caps
.dir_in
= !!direction
;
1962 dep
->endpoint
.caps
.dir_out
= !direction
;
1964 INIT_LIST_HEAD(&dep
->pending_list
);
1965 INIT_LIST_HEAD(&dep
->started_list
);
1971 static int dwc3_gadget_init_endpoints(struct dwc3
*dwc
)
1975 INIT_LIST_HEAD(&dwc
->gadget
.ep_list
);
1977 ret
= dwc3_gadget_init_hw_endpoints(dwc
, dwc
->num_out_eps
, 0);
1979 dev_err(dwc
->dev
, "failed to initialize OUT endpoints\n");
1983 ret
= dwc3_gadget_init_hw_endpoints(dwc
, dwc
->num_in_eps
, 1);
1985 dev_err(dwc
->dev
, "failed to initialize IN endpoints\n");
1992 static void dwc3_gadget_free_endpoints(struct dwc3
*dwc
)
1994 struct dwc3_ep
*dep
;
1997 for (epnum
= 0; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
1998 dep
= dwc
->eps
[epnum
];
2002 * Physical endpoints 0 and 1 are special; they form the
2003 * bi-directional USB endpoint 0.
2005 * For those two physical endpoints, we don't allocate a TRB
2006 * pool nor do we add them the endpoints list. Due to that, we
2007 * shouldn't do these two operations otherwise we would end up
2008 * with all sorts of bugs when removing dwc3.ko.
2010 if (epnum
!= 0 && epnum
!= 1) {
2011 dwc3_free_trb_pool(dep
);
2012 list_del(&dep
->endpoint
.ep_list
);
2019 /* -------------------------------------------------------------------------- */
2021 static int __dwc3_cleanup_done_trbs(struct dwc3
*dwc
, struct dwc3_ep
*dep
,
2022 struct dwc3_request
*req
, struct dwc3_trb
*trb
,
2023 const struct dwc3_event_depevt
*event
, int status
,
2027 unsigned int s_pkt
= 0;
2028 unsigned int trb_status
;
2030 dwc3_ep_inc_deq(dep
);
2032 if (req
->trb
== trb
)
2033 dep
->queued_requests
--;
2035 trace_dwc3_complete_trb(dep
, trb
);
2038 * If we're in the middle of series of chained TRBs and we
2039 * receive a short transfer along the way, DWC3 will skip
2040 * through all TRBs including the last TRB in the chain (the
2041 * where CHN bit is zero. DWC3 will also avoid clearing HWO
2042 * bit and SW has to do it manually.
2044 * We're going to do that here to avoid problems of HW trying
2045 * to use bogus TRBs for transfers.
2047 if (chain
&& (trb
->ctrl
& DWC3_TRB_CTRL_HWO
))
2048 trb
->ctrl
&= ~DWC3_TRB_CTRL_HWO
;
2050 if ((trb
->ctrl
& DWC3_TRB_CTRL_HWO
) && status
!= -ESHUTDOWN
)
2053 count
= trb
->size
& DWC3_TRB_SIZE_MASK
;
2054 req
->remaining
+= count
;
2056 if (dep
->direction
) {
2058 trb_status
= DWC3_TRB_SIZE_TRBSTS(trb
->size
);
2059 if (trb_status
== DWC3_TRBSTS_MISSED_ISOC
) {
2061 * If missed isoc occurred and there is
2062 * no request queued then issue END
2063 * TRANSFER, so that core generates
2064 * next xfernotready and we will issue
2065 * a fresh START TRANSFER.
2066 * If there are still queued request
2067 * then wait, do not issue either END
2068 * or UPDATE TRANSFER, just attach next
2069 * request in pending_list during
2070 * giveback.If any future queued request
2071 * is successfully transferred then we
2072 * will issue UPDATE TRANSFER for all
2073 * request in the pending_list.
2075 dep
->flags
|= DWC3_EP_MISSED_ISOC
;
2077 dev_err(dwc
->dev
, "incomplete IN transfer %s\n",
2079 status
= -ECONNRESET
;
2082 dep
->flags
&= ~DWC3_EP_MISSED_ISOC
;
2085 if (count
&& (event
->status
& DEPEVT_STATUS_SHORT
))
2089 if (s_pkt
&& !chain
)
2092 if ((event
->status
& DEPEVT_STATUS_IOC
) &&
2093 (trb
->ctrl
& DWC3_TRB_CTRL_IOC
))
2099 static int dwc3_cleanup_done_reqs(struct dwc3
*dwc
, struct dwc3_ep
*dep
,
2100 const struct dwc3_event_depevt
*event
, int status
)
2102 struct dwc3_request
*req
, *n
;
2103 struct dwc3_trb
*trb
;
2107 list_for_each_entry_safe(req
, n
, &dep
->started_list
, list
) {
2111 length
= req
->request
.length
;
2112 chain
= req
->num_pending_sgs
> 0;
2114 struct scatterlist
*sg
= req
->sg
;
2115 struct scatterlist
*s
;
2116 unsigned int pending
= req
->num_pending_sgs
;
2119 for_each_sg(sg
, s
, pending
, i
) {
2120 trb
= &dep
->trb_pool
[dep
->trb_dequeue
];
2122 if (trb
->ctrl
& DWC3_TRB_CTRL_HWO
)
2125 req
->sg
= sg_next(s
);
2126 req
->num_pending_sgs
--;
2128 ret
= __dwc3_cleanup_done_trbs(dwc
, dep
, req
, trb
,
2129 event
, status
, chain
);
2134 trb
= &dep
->trb_pool
[dep
->trb_dequeue
];
2135 ret
= __dwc3_cleanup_done_trbs(dwc
, dep
, req
, trb
,
2136 event
, status
, chain
);
2139 req
->request
.actual
= length
- req
->remaining
;
2141 if ((req
->request
.actual
< length
) && req
->num_pending_sgs
)
2142 return __dwc3_gadget_kick_transfer(dep
, 0);
2144 dwc3_gadget_giveback(dep
, req
, status
);
2147 if ((event
->status
& DEPEVT_STATUS_IOC
) &&
2148 (trb
->ctrl
& DWC3_TRB_CTRL_IOC
))
2155 * Our endpoint might get disabled by another thread during
2156 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2157 * early on so DWC3_EP_BUSY flag gets cleared
2159 if (!dep
->endpoint
.desc
)
2162 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
) &&
2163 list_empty(&dep
->started_list
)) {
2164 if (list_empty(&dep
->pending_list
)) {
2166 * If there is no entry in request list then do
2167 * not issue END TRANSFER now. Just set PENDING
2168 * flag, so that END TRANSFER is issued when an
2169 * entry is added into request list.
2171 dep
->flags
= DWC3_EP_PENDING_REQUEST
;
2173 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
2174 dep
->flags
= DWC3_EP_ENABLED
;
2179 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
) && ioc
)
2185 static void dwc3_endpoint_transfer_complete(struct dwc3
*dwc
,
2186 struct dwc3_ep
*dep
, const struct dwc3_event_depevt
*event
)
2188 unsigned status
= 0;
2190 u32 is_xfer_complete
;
2192 is_xfer_complete
= (event
->endpoint_event
== DWC3_DEPEVT_XFERCOMPLETE
);
2194 if (event
->status
& DEPEVT_STATUS_BUSERR
)
2195 status
= -ECONNRESET
;
2197 clean_busy
= dwc3_cleanup_done_reqs(dwc
, dep
, event
, status
);
2198 if (clean_busy
&& (!dep
->endpoint
.desc
|| is_xfer_complete
||
2199 usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)))
2200 dep
->flags
&= ~DWC3_EP_BUSY
;
2203 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2204 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2206 if (dwc
->revision
< DWC3_REVISION_183A
) {
2210 for (i
= 0; i
< DWC3_ENDPOINTS_NUM
; i
++) {
2213 if (!(dep
->flags
& DWC3_EP_ENABLED
))
2216 if (!list_empty(&dep
->started_list
))
2220 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2222 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2228 * Our endpoint might get disabled by another thread during
2229 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2230 * early on so DWC3_EP_BUSY flag gets cleared
2232 if (!dep
->endpoint
.desc
)
2235 if (!usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
2238 ret
= __dwc3_gadget_kick_transfer(dep
, 0);
2239 if (!ret
|| ret
== -EBUSY
)
2244 static void dwc3_endpoint_interrupt(struct dwc3
*dwc
,
2245 const struct dwc3_event_depevt
*event
)
2247 struct dwc3_ep
*dep
;
2248 u8 epnum
= event
->endpoint_number
;
2251 dep
= dwc
->eps
[epnum
];
2253 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
2254 if (!(dep
->flags
& DWC3_EP_END_TRANSFER_PENDING
))
2257 /* Handle only EPCMDCMPLT when EP disabled */
2258 if (event
->endpoint_event
!= DWC3_DEPEVT_EPCMDCMPLT
)
2262 if (epnum
== 0 || epnum
== 1) {
2263 dwc3_ep0_interrupt(dwc
, event
);
2267 switch (event
->endpoint_event
) {
2268 case DWC3_DEPEVT_XFERCOMPLETE
:
2269 dep
->resource_index
= 0;
2271 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
2272 dev_err(dwc
->dev
, "XferComplete for Isochronous endpoint\n");
2276 dwc3_endpoint_transfer_complete(dwc
, dep
, event
);
2278 case DWC3_DEPEVT_XFERINPROGRESS
:
2279 dwc3_endpoint_transfer_complete(dwc
, dep
, event
);
2281 case DWC3_DEPEVT_XFERNOTREADY
:
2282 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
2283 dwc3_gadget_start_isoc(dwc
, dep
, event
);
2287 ret
= __dwc3_gadget_kick_transfer(dep
, 0);
2288 if (!ret
|| ret
== -EBUSY
)
2293 case DWC3_DEPEVT_STREAMEVT
:
2294 if (!usb_endpoint_xfer_bulk(dep
->endpoint
.desc
)) {
2295 dev_err(dwc
->dev
, "Stream event for non-Bulk %s\n",
2300 case DWC3_DEPEVT_EPCMDCMPLT
:
2301 cmd
= DEPEVT_PARAMETER_CMD(event
->parameters
);
2303 if (cmd
== DWC3_DEPCMD_ENDTRANSFER
) {
2304 dep
->flags
&= ~DWC3_EP_END_TRANSFER_PENDING
;
2305 wake_up(&dep
->wait_end_transfer
);
2308 case DWC3_DEPEVT_RXTXFIFOEVT
:
2313 static void dwc3_disconnect_gadget(struct dwc3
*dwc
)
2315 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->disconnect
) {
2316 spin_unlock(&dwc
->lock
);
2317 dwc
->gadget_driver
->disconnect(&dwc
->gadget
);
2318 spin_lock(&dwc
->lock
);
2322 static void dwc3_suspend_gadget(struct dwc3
*dwc
)
2324 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->suspend
) {
2325 spin_unlock(&dwc
->lock
);
2326 dwc
->gadget_driver
->suspend(&dwc
->gadget
);
2327 spin_lock(&dwc
->lock
);
2331 static void dwc3_resume_gadget(struct dwc3
*dwc
)
2333 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->resume
) {
2334 spin_unlock(&dwc
->lock
);
2335 dwc
->gadget_driver
->resume(&dwc
->gadget
);
2336 spin_lock(&dwc
->lock
);
2340 static void dwc3_reset_gadget(struct dwc3
*dwc
)
2342 if (!dwc
->gadget_driver
)
2345 if (dwc
->gadget
.speed
!= USB_SPEED_UNKNOWN
) {
2346 spin_unlock(&dwc
->lock
);
2347 usb_gadget_udc_reset(&dwc
->gadget
, dwc
->gadget_driver
);
2348 spin_lock(&dwc
->lock
);
2352 static void dwc3_stop_active_transfer(struct dwc3
*dwc
, u32 epnum
, bool force
)
2354 struct dwc3_ep
*dep
;
2355 struct dwc3_gadget_ep_cmd_params params
;
2359 dep
= dwc
->eps
[epnum
];
2361 if ((dep
->flags
& DWC3_EP_END_TRANSFER_PENDING
) ||
2362 !dep
->resource_index
)
2366 * NOTICE: We are violating what the Databook says about the
2367 * EndTransfer command. Ideally we would _always_ wait for the
2368 * EndTransfer Command Completion IRQ, but that's causing too
2369 * much trouble synchronizing between us and gadget driver.
2371 * We have discussed this with the IP Provider and it was
2372 * suggested to giveback all requests here, but give HW some
2373 * extra time to synchronize with the interconnect. We're using
2374 * an arbitrary 100us delay for that.
2376 * Note also that a similar handling was tested by Synopsys
2377 * (thanks a lot Paul) and nothing bad has come out of it.
2378 * In short, what we're doing is:
2380 * - Issue EndTransfer WITH CMDIOC bit set
2383 * As of IP version 3.10a of the DWC_usb3 IP, the controller
2384 * supports a mode to work around the above limitation. The
2385 * software can poll the CMDACT bit in the DEPCMD register
2386 * after issuing a EndTransfer command. This mode is enabled
2387 * by writing GUCTL2[14]. This polling is already done in the
2388 * dwc3_send_gadget_ep_cmd() function so if the mode is
2389 * enabled, the EndTransfer command will have completed upon
2390 * returning from this function and we don't need to delay for
2393 * This mode is NOT available on the DWC_usb31 IP.
2396 cmd
= DWC3_DEPCMD_ENDTRANSFER
;
2397 cmd
|= force
? DWC3_DEPCMD_HIPRI_FORCERM
: 0;
2398 cmd
|= DWC3_DEPCMD_CMDIOC
;
2399 cmd
|= DWC3_DEPCMD_PARAM(dep
->resource_index
);
2400 memset(¶ms
, 0, sizeof(params
));
2401 ret
= dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
2403 dep
->resource_index
= 0;
2404 dep
->flags
&= ~DWC3_EP_BUSY
;
2406 if (dwc3_is_usb31(dwc
) || dwc
->revision
< DWC3_REVISION_310A
) {
2407 dep
->flags
|= DWC3_EP_END_TRANSFER_PENDING
;
2412 static void dwc3_clear_stall_all_ep(struct dwc3
*dwc
)
2416 for (epnum
= 1; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
2417 struct dwc3_ep
*dep
;
2420 dep
= dwc
->eps
[epnum
];
2424 if (!(dep
->flags
& DWC3_EP_STALL
))
2427 dep
->flags
&= ~DWC3_EP_STALL
;
2429 ret
= dwc3_send_clear_stall_ep_cmd(dep
);
2434 static void dwc3_gadget_disconnect_interrupt(struct dwc3
*dwc
)
2438 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2439 reg
&= ~DWC3_DCTL_INITU1ENA
;
2440 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2442 reg
&= ~DWC3_DCTL_INITU2ENA
;
2443 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2445 dwc3_disconnect_gadget(dwc
);
2447 dwc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2448 dwc
->setup_packet_pending
= false;
2449 usb_gadget_set_state(&dwc
->gadget
, USB_STATE_NOTATTACHED
);
2451 dwc
->connected
= false;
2454 static void dwc3_gadget_reset_interrupt(struct dwc3
*dwc
)
2458 dwc
->connected
= true;
2461 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2462 * would cause a missing Disconnect Event if there's a
2463 * pending Setup Packet in the FIFO.
2465 * There's no suggested workaround on the official Bug
2466 * report, which states that "unless the driver/application
2467 * is doing any special handling of a disconnect event,
2468 * there is no functional issue".
2470 * Unfortunately, it turns out that we _do_ some special
2471 * handling of a disconnect event, namely complete all
2472 * pending transfers, notify gadget driver of the
2473 * disconnection, and so on.
2475 * Our suggested workaround is to follow the Disconnect
2476 * Event steps here, instead, based on a setup_packet_pending
2477 * flag. Such flag gets set whenever we have a SETUP_PENDING
2478 * status for EP0 TRBs and gets cleared on XferComplete for the
2483 * STAR#9000466709: RTL: Device : Disconnect event not
2484 * generated if setup packet pending in FIFO
2486 if (dwc
->revision
< DWC3_REVISION_188A
) {
2487 if (dwc
->setup_packet_pending
)
2488 dwc3_gadget_disconnect_interrupt(dwc
);
2491 dwc3_reset_gadget(dwc
);
2493 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2494 reg
&= ~DWC3_DCTL_TSTCTRL_MASK
;
2495 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2496 dwc
->test_mode
= false;
2497 dwc3_clear_stall_all_ep(dwc
);
2499 /* Reset device address to zero */
2500 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
2501 reg
&= ~(DWC3_DCFG_DEVADDR_MASK
);
2502 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
2505 static void dwc3_gadget_conndone_interrupt(struct dwc3
*dwc
)
2507 struct dwc3_ep
*dep
;
2512 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
2513 speed
= reg
& DWC3_DSTS_CONNECTSPD
;
2517 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2518 * each time on Connect Done.
2520 * Currently we always use the reset value. If any platform
2521 * wants to set this to a different value, we need to add a
2522 * setting and update GCTL.RAMCLKSEL here.
2526 case DWC3_DSTS_SUPERSPEED_PLUS
:
2527 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
2528 dwc
->gadget
.ep0
->maxpacket
= 512;
2529 dwc
->gadget
.speed
= USB_SPEED_SUPER_PLUS
;
2531 case DWC3_DSTS_SUPERSPEED
:
2533 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2534 * would cause a missing USB3 Reset event.
2536 * In such situations, we should force a USB3 Reset
2537 * event by calling our dwc3_gadget_reset_interrupt()
2542 * STAR#9000483510: RTL: SS : USB3 reset event may
2543 * not be generated always when the link enters poll
2545 if (dwc
->revision
< DWC3_REVISION_190A
)
2546 dwc3_gadget_reset_interrupt(dwc
);
2548 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
2549 dwc
->gadget
.ep0
->maxpacket
= 512;
2550 dwc
->gadget
.speed
= USB_SPEED_SUPER
;
2552 case DWC3_DSTS_HIGHSPEED
:
2553 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(64);
2554 dwc
->gadget
.ep0
->maxpacket
= 64;
2555 dwc
->gadget
.speed
= USB_SPEED_HIGH
;
2557 case DWC3_DSTS_FULLSPEED
:
2558 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(64);
2559 dwc
->gadget
.ep0
->maxpacket
= 64;
2560 dwc
->gadget
.speed
= USB_SPEED_FULL
;
2562 case DWC3_DSTS_LOWSPEED
:
2563 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(8);
2564 dwc
->gadget
.ep0
->maxpacket
= 8;
2565 dwc
->gadget
.speed
= USB_SPEED_LOW
;
2569 /* Enable USB2 LPM Capability */
2571 if ((dwc
->revision
> DWC3_REVISION_194A
) &&
2572 (speed
!= DWC3_DSTS_SUPERSPEED
) &&
2573 (speed
!= DWC3_DSTS_SUPERSPEED_PLUS
)) {
2574 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
2575 reg
|= DWC3_DCFG_LPM_CAP
;
2576 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
2578 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2579 reg
&= ~(DWC3_DCTL_HIRD_THRES_MASK
| DWC3_DCTL_L1_HIBER_EN
);
2581 reg
|= DWC3_DCTL_HIRD_THRES(dwc
->hird_threshold
);
2584 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2585 * DCFG.LPMCap is set, core responses with an ACK and the
2586 * BESL value in the LPM token is less than or equal to LPM
2589 WARN_ONCE(dwc
->revision
< DWC3_REVISION_240A
2590 && dwc
->has_lpm_erratum
,
2591 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
2593 if (dwc
->has_lpm_erratum
&& dwc
->revision
>= DWC3_REVISION_240A
)
2594 reg
|= DWC3_DCTL_LPM_ERRATA(dwc
->lpm_nyet_threshold
);
2596 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2598 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2599 reg
&= ~DWC3_DCTL_HIRD_THRES_MASK
;
2600 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2604 ret
= __dwc3_gadget_ep_enable(dep
, true, false);
2606 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
2611 ret
= __dwc3_gadget_ep_enable(dep
, true, false);
2613 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
2618 * Configure PHY via GUSB3PIPECTLn if required.
2620 * Update GTXFIFOSIZn
2622 * In both cases reset values should be sufficient.
2626 static void dwc3_gadget_wakeup_interrupt(struct dwc3
*dwc
)
2629 * TODO take core out of low power mode when that's
2633 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->resume
) {
2634 spin_unlock(&dwc
->lock
);
2635 dwc
->gadget_driver
->resume(&dwc
->gadget
);
2636 spin_lock(&dwc
->lock
);
2640 static void dwc3_gadget_linksts_change_interrupt(struct dwc3
*dwc
,
2641 unsigned int evtinfo
)
2643 enum dwc3_link_state next
= evtinfo
& DWC3_LINK_STATE_MASK
;
2644 unsigned int pwropt
;
2647 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2648 * Hibernation mode enabled which would show up when device detects
2649 * host-initiated U3 exit.
2651 * In that case, device will generate a Link State Change Interrupt
2652 * from U3 to RESUME which is only necessary if Hibernation is
2655 * There are no functional changes due to such spurious event and we
2656 * just need to ignore it.
2660 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2663 pwropt
= DWC3_GHWPARAMS1_EN_PWROPT(dwc
->hwparams
.hwparams1
);
2664 if ((dwc
->revision
< DWC3_REVISION_250A
) &&
2665 (pwropt
!= DWC3_GHWPARAMS1_EN_PWROPT_HIB
)) {
2666 if ((dwc
->link_state
== DWC3_LINK_STATE_U3
) &&
2667 (next
== DWC3_LINK_STATE_RESUME
)) {
2673 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2674 * on the link partner, the USB session might do multiple entry/exit
2675 * of low power states before a transfer takes place.
2677 * Due to this problem, we might experience lower throughput. The
2678 * suggested workaround is to disable DCTL[12:9] bits if we're
2679 * transitioning from U1/U2 to U0 and enable those bits again
2680 * after a transfer completes and there are no pending transfers
2681 * on any of the enabled endpoints.
2683 * This is the first half of that workaround.
2687 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2688 * core send LGO_Ux entering U0
2690 if (dwc
->revision
< DWC3_REVISION_183A
) {
2691 if (next
== DWC3_LINK_STATE_U0
) {
2695 switch (dwc
->link_state
) {
2696 case DWC3_LINK_STATE_U1
:
2697 case DWC3_LINK_STATE_U2
:
2698 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2699 u1u2
= reg
& (DWC3_DCTL_INITU2ENA
2700 | DWC3_DCTL_ACCEPTU2ENA
2701 | DWC3_DCTL_INITU1ENA
2702 | DWC3_DCTL_ACCEPTU1ENA
);
2705 dwc
->u1u2
= reg
& u1u2
;
2709 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2719 case DWC3_LINK_STATE_U1
:
2720 if (dwc
->speed
== USB_SPEED_SUPER
)
2721 dwc3_suspend_gadget(dwc
);
2723 case DWC3_LINK_STATE_U2
:
2724 case DWC3_LINK_STATE_U3
:
2725 dwc3_suspend_gadget(dwc
);
2727 case DWC3_LINK_STATE_RESUME
:
2728 dwc3_resume_gadget(dwc
);
2735 dwc
->link_state
= next
;
2738 static void dwc3_gadget_suspend_interrupt(struct dwc3
*dwc
,
2739 unsigned int evtinfo
)
2741 enum dwc3_link_state next
= evtinfo
& DWC3_LINK_STATE_MASK
;
2743 if (dwc
->link_state
!= next
&& next
== DWC3_LINK_STATE_U3
)
2744 dwc3_suspend_gadget(dwc
);
2746 dwc
->link_state
= next
;
2749 static void dwc3_gadget_hibernation_interrupt(struct dwc3
*dwc
,
2750 unsigned int evtinfo
)
2752 unsigned int is_ss
= evtinfo
& BIT(4);
2755 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2756 * have a known issue which can cause USB CV TD.9.23 to fail
2759 * Because of this issue, core could generate bogus hibernation
2760 * events which SW needs to ignore.
2764 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2765 * Device Fallback from SuperSpeed
2767 if (is_ss
^ (dwc
->speed
== USB_SPEED_SUPER
))
2770 /* enter hibernation here */
2773 static void dwc3_gadget_interrupt(struct dwc3
*dwc
,
2774 const struct dwc3_event_devt
*event
)
2776 switch (event
->type
) {
2777 case DWC3_DEVICE_EVENT_DISCONNECT
:
2778 dwc3_gadget_disconnect_interrupt(dwc
);
2780 case DWC3_DEVICE_EVENT_RESET
:
2781 dwc3_gadget_reset_interrupt(dwc
);
2783 case DWC3_DEVICE_EVENT_CONNECT_DONE
:
2784 dwc3_gadget_conndone_interrupt(dwc
);
2786 case DWC3_DEVICE_EVENT_WAKEUP
:
2787 dwc3_gadget_wakeup_interrupt(dwc
);
2789 case DWC3_DEVICE_EVENT_HIBER_REQ
:
2790 if (dev_WARN_ONCE(dwc
->dev
, !dwc
->has_hibernation
,
2791 "unexpected hibernation event\n"))
2794 dwc3_gadget_hibernation_interrupt(dwc
, event
->event_info
);
2796 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE
:
2797 dwc3_gadget_linksts_change_interrupt(dwc
, event
->event_info
);
2799 case DWC3_DEVICE_EVENT_EOPF
:
2800 /* It changed to be suspend event for version 2.30a and above */
2801 if (dwc
->revision
>= DWC3_REVISION_230A
) {
2803 * Ignore suspend event until the gadget enters into
2804 * USB_STATE_CONFIGURED state.
2806 if (dwc
->gadget
.state
>= USB_STATE_CONFIGURED
)
2807 dwc3_gadget_suspend_interrupt(dwc
,
2811 case DWC3_DEVICE_EVENT_SOF
:
2812 case DWC3_DEVICE_EVENT_ERRATIC_ERROR
:
2813 case DWC3_DEVICE_EVENT_CMD_CMPL
:
2814 case DWC3_DEVICE_EVENT_OVERFLOW
:
2817 dev_WARN(dwc
->dev
, "UNKNOWN IRQ %d\n", event
->type
);
2821 static void dwc3_process_event_entry(struct dwc3
*dwc
,
2822 const union dwc3_event
*event
)
2824 trace_dwc3_event(event
->raw
, dwc
);
2826 /* Endpoint IRQ, handle it and return early */
2827 if (event
->type
.is_devspec
== 0) {
2829 return dwc3_endpoint_interrupt(dwc
, &event
->depevt
);
2832 switch (event
->type
.type
) {
2833 case DWC3_EVENT_TYPE_DEV
:
2834 dwc3_gadget_interrupt(dwc
, &event
->devt
);
2836 /* REVISIT what to do with Carkit and I2C events ? */
2838 dev_err(dwc
->dev
, "UNKNOWN IRQ type %d\n", event
->raw
);
2842 static irqreturn_t
dwc3_process_event_buf(struct dwc3_event_buffer
*evt
)
2844 struct dwc3
*dwc
= evt
->dwc
;
2845 irqreturn_t ret
= IRQ_NONE
;
2851 if (!(evt
->flags
& DWC3_EVENT_PENDING
))
2855 union dwc3_event event
;
2857 event
.raw
= *(u32
*) (evt
->cache
+ evt
->lpos
);
2859 dwc3_process_event_entry(dwc
, &event
);
2862 * FIXME we wrap around correctly to the next entry as
2863 * almost all entries are 4 bytes in size. There is one
2864 * entry which has 12 bytes which is a regular entry
2865 * followed by 8 bytes data. ATM I don't know how
2866 * things are organized if we get next to the a
2867 * boundary so I worry about that once we try to handle
2870 evt
->lpos
= (evt
->lpos
+ 4) % evt
->length
;
2875 evt
->flags
&= ~DWC3_EVENT_PENDING
;
2878 /* Unmask interrupt */
2879 reg
= dwc3_readl(dwc
->regs
, DWC3_GEVNTSIZ(0));
2880 reg
&= ~DWC3_GEVNTSIZ_INTMASK
;
2881 dwc3_writel(dwc
->regs
, DWC3_GEVNTSIZ(0), reg
);
2883 if (dwc
->imod_interval
) {
2884 dwc3_writel(dwc
->regs
, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB
);
2885 dwc3_writel(dwc
->regs
, DWC3_DEV_IMOD(0), dwc
->imod_interval
);
2891 static irqreturn_t
dwc3_thread_interrupt(int irq
, void *_evt
)
2893 struct dwc3_event_buffer
*evt
= _evt
;
2894 struct dwc3
*dwc
= evt
->dwc
;
2895 unsigned long flags
;
2896 irqreturn_t ret
= IRQ_NONE
;
2898 spin_lock_irqsave(&dwc
->lock
, flags
);
2899 ret
= dwc3_process_event_buf(evt
);
2900 spin_unlock_irqrestore(&dwc
->lock
, flags
);
2905 static irqreturn_t
dwc3_check_event_buf(struct dwc3_event_buffer
*evt
)
2907 struct dwc3
*dwc
= evt
->dwc
;
2912 if (pm_runtime_suspended(dwc
->dev
)) {
2913 pm_runtime_get(dwc
->dev
);
2914 disable_irq_nosync(dwc
->irq_gadget
);
2915 dwc
->pending_events
= true;
2919 count
= dwc3_readl(dwc
->regs
, DWC3_GEVNTCOUNT(0));
2920 count
&= DWC3_GEVNTCOUNT_MASK
;
2925 evt
->flags
|= DWC3_EVENT_PENDING
;
2927 /* Mask interrupt */
2928 reg
= dwc3_readl(dwc
->regs
, DWC3_GEVNTSIZ(0));
2929 reg
|= DWC3_GEVNTSIZ_INTMASK
;
2930 dwc3_writel(dwc
->regs
, DWC3_GEVNTSIZ(0), reg
);
2932 amount
= min(count
, evt
->length
- evt
->lpos
);
2933 memcpy(evt
->cache
+ evt
->lpos
, evt
->buf
+ evt
->lpos
, amount
);
2936 memcpy(evt
->cache
, evt
->buf
, count
- amount
);
2938 dwc3_writel(dwc
->regs
, DWC3_GEVNTCOUNT(0), count
);
2940 return IRQ_WAKE_THREAD
;
2943 static irqreturn_t
dwc3_interrupt(int irq
, void *_evt
)
2945 struct dwc3_event_buffer
*evt
= _evt
;
2947 return dwc3_check_event_buf(evt
);
2950 static int dwc3_gadget_get_irq(struct dwc3
*dwc
)
2952 struct platform_device
*dwc3_pdev
= to_platform_device(dwc
->dev
);
2955 irq
= platform_get_irq_byname(dwc3_pdev
, "peripheral");
2959 if (irq
== -EPROBE_DEFER
)
2962 irq
= platform_get_irq_byname(dwc3_pdev
, "dwc_usb3");
2966 if (irq
== -EPROBE_DEFER
)
2969 irq
= platform_get_irq(dwc3_pdev
, 0);
2973 if (irq
!= -EPROBE_DEFER
)
2974 dev_err(dwc
->dev
, "missing peripheral IRQ\n");
2984 * dwc3_gadget_init - Initializes gadget related registers
2985 * @dwc: pointer to our controller context structure
2987 * Returns 0 on success otherwise negative errno.
2989 int dwc3_gadget_init(struct dwc3
*dwc
)
2994 irq
= dwc3_gadget_get_irq(dwc
);
3000 dwc
->irq_gadget
= irq
;
3002 dwc
->ctrl_req
= dma_alloc_coherent(dwc
->sysdev
, sizeof(*dwc
->ctrl_req
),
3003 &dwc
->ctrl_req_addr
, GFP_KERNEL
);
3004 if (!dwc
->ctrl_req
) {
3005 dev_err(dwc
->dev
, "failed to allocate ctrl request\n");
3010 dwc
->ep0_trb
= dma_alloc_coherent(dwc
->sysdev
,
3011 sizeof(*dwc
->ep0_trb
) * 2,
3012 &dwc
->ep0_trb_addr
, GFP_KERNEL
);
3013 if (!dwc
->ep0_trb
) {
3014 dev_err(dwc
->dev
, "failed to allocate ep0 trb\n");
3019 dwc
->setup_buf
= kzalloc(DWC3_EP0_BOUNCE_SIZE
, GFP_KERNEL
);
3020 if (!dwc
->setup_buf
) {
3025 dwc
->ep0_bounce
= dma_alloc_coherent(dwc
->sysdev
,
3026 DWC3_EP0_BOUNCE_SIZE
, &dwc
->ep0_bounce_addr
,
3028 if (!dwc
->ep0_bounce
) {
3029 dev_err(dwc
->dev
, "failed to allocate ep0 bounce buffer\n");
3034 dwc
->zlp_buf
= kzalloc(DWC3_ZLP_BUF_SIZE
, GFP_KERNEL
);
3035 if (!dwc
->zlp_buf
) {
3040 init_completion(&dwc
->ep0_in_setup
);
3042 dwc
->gadget
.ops
= &dwc3_gadget_ops
;
3043 dwc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
3044 dwc
->gadget
.sg_supported
= true;
3045 dwc
->gadget
.name
= "dwc3-gadget";
3046 dwc
->gadget
.is_otg
= dwc
->dr_mode
== USB_DR_MODE_OTG
;
3049 * FIXME We might be setting max_speed to <SUPER, however versions
3050 * <2.20a of dwc3 have an issue with metastability (documented
3051 * elsewhere in this driver) which tells us we can't set max speed to
3052 * anything lower than SUPER.
3054 * Because gadget.max_speed is only used by composite.c and function
3055 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3056 * to happen so we avoid sending SuperSpeed Capability descriptor
3057 * together with our BOS descriptor as that could confuse host into
3058 * thinking we can handle super speed.
3060 * Note that, in fact, we won't even support GetBOS requests when speed
3061 * is less than super speed because we don't have means, yet, to tell
3062 * composite.c that we are USB 2.0 + LPM ECN.
3064 if (dwc
->revision
< DWC3_REVISION_220A
)
3065 dev_info(dwc
->dev
, "changing max_speed on rev %08x\n",
3068 dwc
->gadget
.max_speed
= dwc
->maximum_speed
;
3071 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
3074 dwc
->gadget
.quirk_ep_out_aligned_size
= true;
3077 * REVISIT: Here we should clear all pending IRQs to be
3078 * sure we're starting from a well known location.
3081 ret
= dwc3_gadget_init_endpoints(dwc
);
3085 ret
= usb_add_gadget_udc(dwc
->dev
, &dwc
->gadget
);
3087 dev_err(dwc
->dev
, "failed to register udc\n");
3094 kfree(dwc
->zlp_buf
);
3097 dwc3_gadget_free_endpoints(dwc
);
3098 dma_free_coherent(dwc
->sysdev
, DWC3_EP0_BOUNCE_SIZE
,
3099 dwc
->ep0_bounce
, dwc
->ep0_bounce_addr
);
3102 kfree(dwc
->setup_buf
);
3105 dma_free_coherent(dwc
->sysdev
, sizeof(*dwc
->ep0_trb
) * 2,
3106 dwc
->ep0_trb
, dwc
->ep0_trb_addr
);
3109 dma_free_coherent(dwc
->sysdev
, sizeof(*dwc
->ctrl_req
),
3110 dwc
->ctrl_req
, dwc
->ctrl_req_addr
);
3116 /* -------------------------------------------------------------------------- */
3118 void dwc3_gadget_exit(struct dwc3
*dwc
)
3120 usb_del_gadget_udc(&dwc
->gadget
);
3122 dwc3_gadget_free_endpoints(dwc
);
3124 dma_free_coherent(dwc
->sysdev
, DWC3_EP0_BOUNCE_SIZE
,
3125 dwc
->ep0_bounce
, dwc
->ep0_bounce_addr
);
3127 kfree(dwc
->setup_buf
);
3128 kfree(dwc
->zlp_buf
);
3130 dma_free_coherent(dwc
->sysdev
, sizeof(*dwc
->ep0_trb
) * 2,
3131 dwc
->ep0_trb
, dwc
->ep0_trb_addr
);
3133 dma_free_coherent(dwc
->sysdev
, sizeof(*dwc
->ctrl_req
),
3134 dwc
->ctrl_req
, dwc
->ctrl_req_addr
);
3137 int dwc3_gadget_suspend(struct dwc3
*dwc
)
3141 if (!dwc
->gadget_driver
)
3144 ret
= dwc3_gadget_run_stop(dwc
, false, false);
3148 dwc3_disconnect_gadget(dwc
);
3149 __dwc3_gadget_stop(dwc
);
3154 int dwc3_gadget_resume(struct dwc3
*dwc
)
3158 if (!dwc
->gadget_driver
)
3161 ret
= __dwc3_gadget_start(dwc
);
3165 ret
= dwc3_gadget_run_stop(dwc
, true, false);
3172 __dwc3_gadget_stop(dwc
);
3178 void dwc3_gadget_process_pending_events(struct dwc3
*dwc
)
3180 if (dwc
->pending_events
) {
3181 dwc3_interrupt(dwc
->irq_gadget
, dwc
->ev_buf
);
3182 dwc
->pending_events
= false;
3183 enable_irq(dwc
->irq_gadget
);