2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/spinlock.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/interrupt.h>
27 #include <linux/list.h>
28 #include <linux/dma-mapping.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
39 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
40 * @dwc: pointer to our context structure
41 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
43 * Caller should take care of locking. This function will
44 * return 0 on success or -EINVAL if wrong Test Selector
47 int dwc3_gadget_set_test_mode(struct dwc3
*dwc
, int mode
)
51 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
52 reg
&= ~DWC3_DCTL_TSTCTRL_MASK
;
66 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
72 * dwc3_gadget_get_link_state - Gets current state of USB Link
73 * @dwc: pointer to our context structure
75 * Caller should take care of locking. This function will
76 * return the link state on success (>= 0) or -ETIMEDOUT.
78 int dwc3_gadget_get_link_state(struct dwc3
*dwc
)
82 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
84 return DWC3_DSTS_USBLNKST(reg
);
88 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
89 * @dwc: pointer to our context structure
90 * @state: the state to put link into
92 * Caller should take care of locking. This function will
93 * return 0 on success or -ETIMEDOUT.
95 int dwc3_gadget_set_link_state(struct dwc3
*dwc
, enum dwc3_link_state state
)
101 * Wait until device controller is ready. Only applies to 1.94a and
104 if (dwc
->revision
>= DWC3_REVISION_194A
) {
106 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
107 if (reg
& DWC3_DSTS_DCNRD
)
117 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
118 reg
&= ~DWC3_DCTL_ULSTCHNGREQ_MASK
;
120 /* set requested state */
121 reg
|= DWC3_DCTL_ULSTCHNGREQ(state
);
122 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
125 * The following code is racy when called from dwc3_gadget_wakeup,
126 * and is not needed, at least on newer versions
128 if (dwc
->revision
>= DWC3_REVISION_194A
)
131 /* wait for a change in DSTS */
134 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
136 if (DWC3_DSTS_USBLNKST(reg
) == state
)
146 * dwc3_ep_inc_trb() - Increment a TRB index.
147 * @index - Pointer to the TRB index to increment.
149 * The index should never point to the link TRB. After incrementing,
150 * if it is point to the link TRB, wrap around to the beginning. The
151 * link TRB is always at the last TRB entry.
153 static void dwc3_ep_inc_trb(u8
*index
)
156 if (*index
== (DWC3_TRB_NUM
- 1))
160 static void dwc3_ep_inc_enq(struct dwc3_ep
*dep
)
162 dwc3_ep_inc_trb(&dep
->trb_enqueue
);
165 static void dwc3_ep_inc_deq(struct dwc3_ep
*dep
)
167 dwc3_ep_inc_trb(&dep
->trb_dequeue
);
170 void dwc3_gadget_giveback(struct dwc3_ep
*dep
, struct dwc3_request
*req
,
173 struct dwc3
*dwc
= dep
->dwc
;
175 req
->started
= false;
176 list_del(&req
->list
);
180 if (req
->request
.status
== -EINPROGRESS
)
181 req
->request
.status
= status
;
183 if (dwc
->ep0_bounced
&& dep
->number
== 0)
184 dwc
->ep0_bounced
= false;
186 usb_gadget_unmap_request(&dwc
->gadget
, &req
->request
,
189 trace_dwc3_gadget_giveback(req
);
191 spin_unlock(&dwc
->lock
);
192 usb_gadget_giveback_request(&dep
->endpoint
, &req
->request
);
193 spin_lock(&dwc
->lock
);
196 pm_runtime_put(dwc
->dev
);
199 int dwc3_send_gadget_generic_command(struct dwc3
*dwc
, unsigned cmd
, u32 param
)
206 dwc3_writel(dwc
->regs
, DWC3_DGCMDPAR
, param
);
207 dwc3_writel(dwc
->regs
, DWC3_DGCMD
, cmd
| DWC3_DGCMD_CMDACT
);
210 reg
= dwc3_readl(dwc
->regs
, DWC3_DGCMD
);
211 if (!(reg
& DWC3_DGCMD_CMDACT
)) {
212 status
= DWC3_DGCMD_STATUS(reg
);
224 trace_dwc3_gadget_generic_cmd(cmd
, param
, status
);
229 static int __dwc3_gadget_wakeup(struct dwc3
*dwc
);
231 int dwc3_send_gadget_ep_cmd(struct dwc3_ep
*dep
, unsigned cmd
,
232 struct dwc3_gadget_ep_cmd_params
*params
)
234 const struct usb_endpoint_descriptor
*desc
= dep
->endpoint
.desc
;
235 struct dwc3
*dwc
= dep
->dwc
;
244 * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
245 * we're issuing an endpoint command, we must check if
246 * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
248 * We will also set SUSPHY bit to what it was before returning as stated
249 * by the same section on Synopsys databook.
251 if (dwc
->gadget
.speed
<= USB_SPEED_HIGH
) {
252 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB2PHYCFG(0));
253 if (unlikely(reg
& DWC3_GUSB2PHYCFG_SUSPHY
)) {
255 reg
&= ~DWC3_GUSB2PHYCFG_SUSPHY
;
256 dwc3_writel(dwc
->regs
, DWC3_GUSB2PHYCFG(0), reg
);
260 if (DWC3_DEPCMD_CMD(cmd
) == DWC3_DEPCMD_STARTTRANSFER
) {
263 needs_wakeup
= (dwc
->link_state
== DWC3_LINK_STATE_U1
||
264 dwc
->link_state
== DWC3_LINK_STATE_U2
||
265 dwc
->link_state
== DWC3_LINK_STATE_U3
);
267 if (unlikely(needs_wakeup
)) {
268 ret
= __dwc3_gadget_wakeup(dwc
);
269 dev_WARN_ONCE(dwc
->dev
, ret
, "wakeup failed --> %d\n",
274 dwc3_writel(dep
->regs
, DWC3_DEPCMDPAR0
, params
->param0
);
275 dwc3_writel(dep
->regs
, DWC3_DEPCMDPAR1
, params
->param1
);
276 dwc3_writel(dep
->regs
, DWC3_DEPCMDPAR2
, params
->param2
);
279 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
280 * not relying on XferNotReady, we can make use of a special "No
281 * Response Update Transfer" command where we should clear both CmdAct
284 * With this, we don't need to wait for command completion and can
285 * straight away issue further commands to the endpoint.
287 * NOTICE: We're making an assumption that control endpoints will never
288 * make use of Update Transfer command. This is a safe assumption
289 * because we can never have more than one request at a time with
290 * Control Endpoints. If anybody changes that assumption, this chunk
291 * needs to be updated accordingly.
293 if (DWC3_DEPCMD_CMD(cmd
) == DWC3_DEPCMD_UPDATETRANSFER
&&
294 !usb_endpoint_xfer_isoc(desc
))
295 cmd
&= ~(DWC3_DEPCMD_CMDIOC
| DWC3_DEPCMD_CMDACT
);
297 cmd
|= DWC3_DEPCMD_CMDACT
;
299 dwc3_writel(dep
->regs
, DWC3_DEPCMD
, cmd
);
301 reg
= dwc3_readl(dep
->regs
, DWC3_DEPCMD
);
302 if (!(reg
& DWC3_DEPCMD_CMDACT
)) {
303 cmd_status
= DWC3_DEPCMD_STATUS(reg
);
305 switch (cmd_status
) {
309 case DEPEVT_TRANSFER_NO_RESOURCE
:
312 case DEPEVT_TRANSFER_BUS_EXPIRY
:
314 * SW issues START TRANSFER command to
315 * isochronous ep with future frame interval. If
316 * future interval time has already passed when
317 * core receives the command, it will respond
318 * with an error status of 'Bus Expiry'.
320 * Instead of always returning -EINVAL, let's
321 * give a hint to the gadget driver that this is
322 * the case by returning -EAGAIN.
327 dev_WARN(dwc
->dev
, "UNKNOWN cmd status\n");
336 cmd_status
= -ETIMEDOUT
;
339 trace_dwc3_gadget_ep_cmd(dep
, cmd
, params
, cmd_status
);
342 switch (DWC3_DEPCMD_CMD(cmd
)) {
343 case DWC3_DEPCMD_STARTTRANSFER
:
344 dep
->flags
|= DWC3_EP_TRANSFER_STARTED
;
346 case DWC3_DEPCMD_ENDTRANSFER
:
347 dep
->flags
&= ~DWC3_EP_TRANSFER_STARTED
;
355 if (unlikely(susphy
)) {
356 reg
= dwc3_readl(dwc
->regs
, DWC3_GUSB2PHYCFG(0));
357 reg
|= DWC3_GUSB2PHYCFG_SUSPHY
;
358 dwc3_writel(dwc
->regs
, DWC3_GUSB2PHYCFG(0), reg
);
364 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep
*dep
)
366 struct dwc3
*dwc
= dep
->dwc
;
367 struct dwc3_gadget_ep_cmd_params params
;
368 u32 cmd
= DWC3_DEPCMD_CLEARSTALL
;
371 * As of core revision 2.60a the recommended programming model
372 * is to set the ClearPendIN bit when issuing a Clear Stall EP
373 * command for IN endpoints. This is to prevent an issue where
374 * some (non-compliant) hosts may not send ACK TPs for pending
375 * IN transfers due to a mishandled error condition. Synopsys
378 if (dep
->direction
&& (dwc
->revision
>= DWC3_REVISION_260A
) &&
379 (dwc
->gadget
.speed
>= USB_SPEED_SUPER
))
380 cmd
|= DWC3_DEPCMD_CLEARPENDIN
;
382 memset(¶ms
, 0, sizeof(params
));
384 return dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
387 static dma_addr_t
dwc3_trb_dma_offset(struct dwc3_ep
*dep
,
388 struct dwc3_trb
*trb
)
390 u32 offset
= (char *) trb
- (char *) dep
->trb_pool
;
392 return dep
->trb_pool_dma
+ offset
;
395 static int dwc3_alloc_trb_pool(struct dwc3_ep
*dep
)
397 struct dwc3
*dwc
= dep
->dwc
;
402 dep
->trb_pool
= dma_alloc_coherent(dwc
->dev
,
403 sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
,
404 &dep
->trb_pool_dma
, GFP_KERNEL
);
405 if (!dep
->trb_pool
) {
406 dev_err(dep
->dwc
->dev
, "failed to allocate trb pool for %s\n",
414 static void dwc3_free_trb_pool(struct dwc3_ep
*dep
)
416 struct dwc3
*dwc
= dep
->dwc
;
418 dma_free_coherent(dwc
->dev
, sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
,
419 dep
->trb_pool
, dep
->trb_pool_dma
);
421 dep
->trb_pool
= NULL
;
422 dep
->trb_pool_dma
= 0;
425 static int dwc3_gadget_set_xfer_resource(struct dwc3
*dwc
, struct dwc3_ep
*dep
);
428 * dwc3_gadget_start_config - Configure EP resources
429 * @dwc: pointer to our controller context structure
430 * @dep: endpoint that is being enabled
432 * The assignment of transfer resources cannot perfectly follow the
433 * data book due to the fact that the controller driver does not have
434 * all knowledge of the configuration in advance. It is given this
435 * information piecemeal by the composite gadget framework after every
436 * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
437 * programming model in this scenario can cause errors. For two
440 * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
441 * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
442 * multiple interfaces.
444 * 2) The databook does not mention doing more DEPXFERCFG for new
445 * endpoint on alt setting (8.1.6).
447 * The following simplified method is used instead:
449 * All hardware endpoints can be assigned a transfer resource and this
450 * setting will stay persistent until either a core reset or
451 * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
452 * do DEPXFERCFG for every hardware endpoint as well. We are
453 * guaranteed that there are as many transfer resources as endpoints.
455 * This function is called for each endpoint when it is being enabled
456 * but is triggered only when called for EP0-out, which always happens
457 * first, and which should only happen in one of the above conditions.
459 static int dwc3_gadget_start_config(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
461 struct dwc3_gadget_ep_cmd_params params
;
469 memset(¶ms
, 0x00, sizeof(params
));
470 cmd
= DWC3_DEPCMD_DEPSTARTCFG
;
472 ret
= dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
476 for (i
= 0; i
< DWC3_ENDPOINTS_NUM
; i
++) {
477 struct dwc3_ep
*dep
= dwc
->eps
[i
];
482 ret
= dwc3_gadget_set_xfer_resource(dwc
, dep
);
490 static int dwc3_gadget_set_ep_config(struct dwc3
*dwc
, struct dwc3_ep
*dep
,
491 const struct usb_endpoint_descriptor
*desc
,
492 const struct usb_ss_ep_comp_descriptor
*comp_desc
,
493 bool modify
, bool restore
)
495 struct dwc3_gadget_ep_cmd_params params
;
497 if (dev_WARN_ONCE(dwc
->dev
, modify
&& restore
,
498 "Can't modify and restore\n"))
501 memset(¶ms
, 0x00, sizeof(params
));
503 params
.param0
= DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc
))
504 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc
));
506 /* Burst size is only needed in SuperSpeed mode */
507 if (dwc
->gadget
.speed
>= USB_SPEED_SUPER
) {
508 u32 burst
= dep
->endpoint
.maxburst
;
509 params
.param0
|= DWC3_DEPCFG_BURST_SIZE(burst
- 1);
513 params
.param0
|= DWC3_DEPCFG_ACTION_MODIFY
;
514 } else if (restore
) {
515 params
.param0
|= DWC3_DEPCFG_ACTION_RESTORE
;
516 params
.param2
|= dep
->saved_state
;
518 params
.param0
|= DWC3_DEPCFG_ACTION_INIT
;
521 if (usb_endpoint_xfer_control(desc
))
522 params
.param1
= DWC3_DEPCFG_XFER_COMPLETE_EN
;
524 if (dep
->number
<= 1 || usb_endpoint_xfer_isoc(desc
))
525 params
.param1
|= DWC3_DEPCFG_XFER_NOT_READY_EN
;
527 if (usb_ss_max_streams(comp_desc
) && usb_endpoint_xfer_bulk(desc
)) {
528 params
.param1
|= DWC3_DEPCFG_STREAM_CAPABLE
529 | DWC3_DEPCFG_STREAM_EVENT_EN
;
530 dep
->stream_capable
= true;
533 if (!usb_endpoint_xfer_control(desc
))
534 params
.param1
|= DWC3_DEPCFG_XFER_IN_PROGRESS_EN
;
537 * We are doing 1:1 mapping for endpoints, meaning
538 * Physical Endpoints 2 maps to Logical Endpoint 2 and
539 * so on. We consider the direction bit as part of the physical
540 * endpoint number. So USB endpoint 0x81 is 0x03.
542 params
.param1
|= DWC3_DEPCFG_EP_NUMBER(dep
->number
);
545 * We must use the lower 16 TX FIFOs even though
549 params
.param0
|= DWC3_DEPCFG_FIFO_NUMBER(dep
->number
>> 1);
551 if (desc
->bInterval
) {
552 params
.param1
|= DWC3_DEPCFG_BINTERVAL_M1(desc
->bInterval
- 1);
553 dep
->interval
= 1 << (desc
->bInterval
- 1);
556 return dwc3_send_gadget_ep_cmd(dep
, DWC3_DEPCMD_SETEPCONFIG
, ¶ms
);
559 static int dwc3_gadget_set_xfer_resource(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
561 struct dwc3_gadget_ep_cmd_params params
;
563 memset(¶ms
, 0x00, sizeof(params
));
565 params
.param0
= DWC3_DEPXFERCFG_NUM_XFER_RES(1);
567 return dwc3_send_gadget_ep_cmd(dep
, DWC3_DEPCMD_SETTRANSFRESOURCE
,
572 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
573 * @dep: endpoint to be initialized
574 * @desc: USB Endpoint Descriptor
576 * Caller should take care of locking
578 static int __dwc3_gadget_ep_enable(struct dwc3_ep
*dep
,
579 const struct usb_endpoint_descriptor
*desc
,
580 const struct usb_ss_ep_comp_descriptor
*comp_desc
,
581 bool modify
, bool restore
)
583 struct dwc3
*dwc
= dep
->dwc
;
587 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
588 ret
= dwc3_gadget_start_config(dwc
, dep
);
593 ret
= dwc3_gadget_set_ep_config(dwc
, dep
, desc
, comp_desc
, modify
,
598 if (!(dep
->flags
& DWC3_EP_ENABLED
)) {
599 struct dwc3_trb
*trb_st_hw
;
600 struct dwc3_trb
*trb_link
;
602 dep
->endpoint
.desc
= desc
;
603 dep
->comp_desc
= comp_desc
;
604 dep
->type
= usb_endpoint_type(desc
);
605 dep
->flags
|= DWC3_EP_ENABLED
;
606 dep
->flags
&= ~DWC3_EP_END_TRANSFER_PENDING
;
608 reg
= dwc3_readl(dwc
->regs
, DWC3_DALEPENA
);
609 reg
|= DWC3_DALEPENA_EP(dep
->number
);
610 dwc3_writel(dwc
->regs
, DWC3_DALEPENA
, reg
);
612 init_waitqueue_head(&dep
->wait_end_transfer
);
614 if (usb_endpoint_xfer_control(desc
))
617 /* Initialize the TRB ring */
618 dep
->trb_dequeue
= 0;
619 dep
->trb_enqueue
= 0;
620 memset(dep
->trb_pool
, 0,
621 sizeof(struct dwc3_trb
) * DWC3_TRB_NUM
);
623 /* Link TRB. The HWO bit is never reset */
624 trb_st_hw
= &dep
->trb_pool
[0];
626 trb_link
= &dep
->trb_pool
[DWC3_TRB_NUM
- 1];
627 trb_link
->bpl
= lower_32_bits(dwc3_trb_dma_offset(dep
, trb_st_hw
));
628 trb_link
->bph
= upper_32_bits(dwc3_trb_dma_offset(dep
, trb_st_hw
));
629 trb_link
->ctrl
|= DWC3_TRBCTL_LINK_TRB
;
630 trb_link
->ctrl
|= DWC3_TRB_CTRL_HWO
;
634 * Issue StartTransfer here with no-op TRB so we can always rely on No
635 * Response Update Transfer command.
637 if (usb_endpoint_xfer_bulk(desc
)) {
638 struct dwc3_gadget_ep_cmd_params params
;
639 struct dwc3_trb
*trb
;
643 memset(¶ms
, 0, sizeof(params
));
644 trb
= &dep
->trb_pool
[0];
645 trb_dma
= dwc3_trb_dma_offset(dep
, trb
);
647 params
.param0
= upper_32_bits(trb_dma
);
648 params
.param1
= lower_32_bits(trb_dma
);
650 cmd
= DWC3_DEPCMD_STARTTRANSFER
;
652 ret
= dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
656 dep
->flags
|= DWC3_EP_BUSY
;
658 dep
->resource_index
= dwc3_gadget_ep_get_transfer_index(dep
);
659 WARN_ON_ONCE(!dep
->resource_index
);
664 trace_dwc3_gadget_ep_enable(dep
);
669 static void dwc3_stop_active_transfer(struct dwc3
*dwc
, u32 epnum
, bool force
);
670 static void dwc3_remove_requests(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
672 struct dwc3_request
*req
;
674 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
676 /* - giveback all requests to gadget driver */
677 while (!list_empty(&dep
->started_list
)) {
678 req
= next_request(&dep
->started_list
);
680 dwc3_gadget_giveback(dep
, req
, -ESHUTDOWN
);
683 while (!list_empty(&dep
->pending_list
)) {
684 req
= next_request(&dep
->pending_list
);
686 dwc3_gadget_giveback(dep
, req
, -ESHUTDOWN
);
691 * __dwc3_gadget_ep_disable - Disables a HW endpoint
692 * @dep: the endpoint to disable
694 * This function also removes requests which are currently processed ny the
695 * hardware and those which are not yet scheduled.
696 * Caller should take care of locking.
698 static int __dwc3_gadget_ep_disable(struct dwc3_ep
*dep
)
700 struct dwc3
*dwc
= dep
->dwc
;
703 trace_dwc3_gadget_ep_disable(dep
);
705 dwc3_remove_requests(dwc
, dep
);
707 /* make sure HW endpoint isn't stalled */
708 if (dep
->flags
& DWC3_EP_STALL
)
709 __dwc3_gadget_ep_set_halt(dep
, 0, false);
711 reg
= dwc3_readl(dwc
->regs
, DWC3_DALEPENA
);
712 reg
&= ~DWC3_DALEPENA_EP(dep
->number
);
713 dwc3_writel(dwc
->regs
, DWC3_DALEPENA
, reg
);
715 dep
->stream_capable
= false;
716 dep
->endpoint
.desc
= NULL
;
717 dep
->comp_desc
= NULL
;
719 dep
->flags
&= DWC3_EP_END_TRANSFER_PENDING
;
724 /* -------------------------------------------------------------------------- */
726 static int dwc3_gadget_ep0_enable(struct usb_ep
*ep
,
727 const struct usb_endpoint_descriptor
*desc
)
732 static int dwc3_gadget_ep0_disable(struct usb_ep
*ep
)
737 /* -------------------------------------------------------------------------- */
739 static int dwc3_gadget_ep_enable(struct usb_ep
*ep
,
740 const struct usb_endpoint_descriptor
*desc
)
747 if (!ep
|| !desc
|| desc
->bDescriptorType
!= USB_DT_ENDPOINT
) {
748 pr_debug("dwc3: invalid parameters\n");
752 if (!desc
->wMaxPacketSize
) {
753 pr_debug("dwc3: missing wMaxPacketSize\n");
757 dep
= to_dwc3_ep(ep
);
760 if (dev_WARN_ONCE(dwc
->dev
, dep
->flags
& DWC3_EP_ENABLED
,
761 "%s is already enabled\n",
765 spin_lock_irqsave(&dwc
->lock
, flags
);
766 ret
= __dwc3_gadget_ep_enable(dep
, desc
, ep
->comp_desc
, false, false);
767 spin_unlock_irqrestore(&dwc
->lock
, flags
);
772 static int dwc3_gadget_ep_disable(struct usb_ep
*ep
)
780 pr_debug("dwc3: invalid parameters\n");
784 dep
= to_dwc3_ep(ep
);
787 if (dev_WARN_ONCE(dwc
->dev
, !(dep
->flags
& DWC3_EP_ENABLED
),
788 "%s is already disabled\n",
792 spin_lock_irqsave(&dwc
->lock
, flags
);
793 ret
= __dwc3_gadget_ep_disable(dep
);
794 spin_unlock_irqrestore(&dwc
->lock
, flags
);
799 static struct usb_request
*dwc3_gadget_ep_alloc_request(struct usb_ep
*ep
,
802 struct dwc3_request
*req
;
803 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
805 req
= kzalloc(sizeof(*req
), gfp_flags
);
809 req
->epnum
= dep
->number
;
812 dep
->allocated_requests
++;
814 trace_dwc3_alloc_request(req
);
816 return &req
->request
;
819 static void dwc3_gadget_ep_free_request(struct usb_ep
*ep
,
820 struct usb_request
*request
)
822 struct dwc3_request
*req
= to_dwc3_request(request
);
823 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
825 dep
->allocated_requests
--;
826 trace_dwc3_free_request(req
);
830 static u32
dwc3_calc_trbs_left(struct dwc3_ep
*dep
);
833 * dwc3_prepare_one_trb - setup one TRB from one request
834 * @dep: endpoint for which this request is prepared
835 * @req: dwc3_request pointer
837 static void dwc3_prepare_one_trb(struct dwc3_ep
*dep
,
838 struct dwc3_request
*req
, dma_addr_t dma
,
839 unsigned length
, unsigned chain
, unsigned node
)
841 struct dwc3_trb
*trb
;
842 struct dwc3
*dwc
= dep
->dwc
;
843 struct usb_gadget
*gadget
= &dwc
->gadget
;
844 enum usb_device_speed speed
= gadget
->speed
;
846 trb
= &dep
->trb_pool
[dep
->trb_enqueue
];
849 dwc3_gadget_move_started_request(req
);
851 req
->trb_dma
= dwc3_trb_dma_offset(dep
, trb
);
852 dep
->queued_requests
++;
855 dwc3_ep_inc_enq(dep
);
857 trb
->size
= DWC3_TRB_SIZE_LENGTH(length
);
858 trb
->bpl
= lower_32_bits(dma
);
859 trb
->bph
= upper_32_bits(dma
);
861 switch (usb_endpoint_type(dep
->endpoint
.desc
)) {
862 case USB_ENDPOINT_XFER_CONTROL
:
863 trb
->ctrl
= DWC3_TRBCTL_CONTROL_SETUP
;
866 case USB_ENDPOINT_XFER_ISOC
:
868 trb
->ctrl
= DWC3_TRBCTL_ISOCHRONOUS_FIRST
;
870 if (speed
== USB_SPEED_HIGH
) {
871 struct usb_ep
*ep
= &dep
->endpoint
;
872 trb
->size
|= DWC3_TRB_SIZE_PCM1(ep
->mult
- 1);
875 trb
->ctrl
= DWC3_TRBCTL_ISOCHRONOUS
;
878 /* always enable Interrupt on Missed ISOC */
879 trb
->ctrl
|= DWC3_TRB_CTRL_ISP_IMI
;
882 case USB_ENDPOINT_XFER_BULK
:
883 case USB_ENDPOINT_XFER_INT
:
884 trb
->ctrl
= DWC3_TRBCTL_NORMAL
;
888 * This is only possible with faulty memory because we
889 * checked it already :)
891 dev_WARN(dwc
->dev
, "Unknown endpoint type %d\n",
892 usb_endpoint_type(dep
->endpoint
.desc
));
895 /* always enable Continue on Short Packet */
896 if (usb_endpoint_dir_out(dep
->endpoint
.desc
)) {
897 trb
->ctrl
|= DWC3_TRB_CTRL_CSP
;
899 if (req
->request
.short_not_ok
)
900 trb
->ctrl
|= DWC3_TRB_CTRL_ISP_IMI
;
903 if ((!req
->request
.no_interrupt
&& !chain
) ||
904 (dwc3_calc_trbs_left(dep
) == 0))
905 trb
->ctrl
|= DWC3_TRB_CTRL_IOC
;
908 trb
->ctrl
|= DWC3_TRB_CTRL_CHN
;
910 if (usb_endpoint_xfer_bulk(dep
->endpoint
.desc
) && dep
->stream_capable
)
911 trb
->ctrl
|= DWC3_TRB_CTRL_SID_SOFN(req
->request
.stream_id
);
913 trb
->ctrl
|= DWC3_TRB_CTRL_HWO
;
915 trace_dwc3_prepare_trb(dep
, trb
);
919 * dwc3_ep_prev_trb() - Returns the previous TRB in the ring
920 * @dep: The endpoint with the TRB ring
921 * @index: The index of the current TRB in the ring
923 * Returns the TRB prior to the one pointed to by the index. If the
924 * index is 0, we will wrap backwards, skip the link TRB, and return
925 * the one just before that.
927 static struct dwc3_trb
*dwc3_ep_prev_trb(struct dwc3_ep
*dep
, u8 index
)
932 tmp
= DWC3_TRB_NUM
- 1;
934 return &dep
->trb_pool
[tmp
- 1];
937 static u32
dwc3_calc_trbs_left(struct dwc3_ep
*dep
)
939 struct dwc3_trb
*tmp
;
940 struct dwc3
*dwc
= dep
->dwc
;
944 * If enqueue & dequeue are equal than it is either full or empty.
946 * One way to know for sure is if the TRB right before us has HWO bit
947 * set or not. If it has, then we're definitely full and can't fit any
948 * more transfers in our ring.
950 if (dep
->trb_enqueue
== dep
->trb_dequeue
) {
951 tmp
= dwc3_ep_prev_trb(dep
, dep
->trb_enqueue
);
952 if (dev_WARN_ONCE(dwc
->dev
, tmp
->ctrl
& DWC3_TRB_CTRL_HWO
,
953 "%s No TRBS left\n", dep
->name
))
956 return DWC3_TRB_NUM
- 1;
959 trbs_left
= dep
->trb_dequeue
- dep
->trb_enqueue
;
960 trbs_left
&= (DWC3_TRB_NUM
- 1);
962 if (dep
->trb_dequeue
< dep
->trb_enqueue
)
968 static void dwc3_prepare_one_trb_sg(struct dwc3_ep
*dep
,
969 struct dwc3_request
*req
)
971 struct scatterlist
*sg
= req
->sg
;
972 struct scatterlist
*s
;
977 for_each_sg(sg
, s
, req
->num_pending_sgs
, i
) {
978 unsigned chain
= true;
980 length
= sg_dma_len(s
);
981 dma
= sg_dma_address(s
);
986 dwc3_prepare_one_trb(dep
, req
, dma
, length
,
989 if (!dwc3_calc_trbs_left(dep
))
994 static void dwc3_prepare_one_trb_linear(struct dwc3_ep
*dep
,
995 struct dwc3_request
*req
)
1000 dma
= req
->request
.dma
;
1001 length
= req
->request
.length
;
1003 dwc3_prepare_one_trb(dep
, req
, dma
, length
,
1008 * dwc3_prepare_trbs - setup TRBs from requests
1009 * @dep: endpoint for which requests are being prepared
1011 * The function goes through the requests list and sets up TRBs for the
1012 * transfers. The function returns once there are no more TRBs available or
1013 * it runs out of requests.
1015 static void dwc3_prepare_trbs(struct dwc3_ep
*dep
)
1017 struct dwc3_request
*req
, *n
;
1019 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM
);
1021 if (!dwc3_calc_trbs_left(dep
))
1025 * We can get in a situation where there's a request in the started list
1026 * but there weren't enough TRBs to fully kick it in the first time
1027 * around, so it has been waiting for more TRBs to be freed up.
1029 * In that case, we should check if we have a request with pending_sgs
1030 * in the started list and prepare TRBs for that request first,
1031 * otherwise we will prepare TRBs completely out of order and that will
1034 list_for_each_entry(req
, &dep
->started_list
, list
) {
1035 if (req
->num_pending_sgs
> 0)
1036 dwc3_prepare_one_trb_sg(dep
, req
);
1038 if (!dwc3_calc_trbs_left(dep
))
1042 list_for_each_entry_safe(req
, n
, &dep
->pending_list
, list
) {
1043 if (req
->num_pending_sgs
> 0)
1044 dwc3_prepare_one_trb_sg(dep
, req
);
1046 dwc3_prepare_one_trb_linear(dep
, req
);
1048 if (!dwc3_calc_trbs_left(dep
))
1053 static int __dwc3_gadget_kick_transfer(struct dwc3_ep
*dep
, u16 cmd_param
)
1055 struct dwc3_gadget_ep_cmd_params params
;
1056 struct dwc3_request
*req
;
1061 starting
= !(dep
->flags
& DWC3_EP_BUSY
);
1063 dwc3_prepare_trbs(dep
);
1064 req
= next_request(&dep
->started_list
);
1066 dep
->flags
|= DWC3_EP_PENDING_REQUEST
;
1070 memset(¶ms
, 0, sizeof(params
));
1073 params
.param0
= upper_32_bits(req
->trb_dma
);
1074 params
.param1
= lower_32_bits(req
->trb_dma
);
1075 cmd
= DWC3_DEPCMD_STARTTRANSFER
|
1076 DWC3_DEPCMD_PARAM(cmd_param
);
1078 cmd
= DWC3_DEPCMD_UPDATETRANSFER
|
1079 DWC3_DEPCMD_PARAM(dep
->resource_index
);
1082 ret
= dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
1085 * FIXME we need to iterate over the list of requests
1086 * here and stop, unmap, free and del each of the linked
1087 * requests instead of what we do now.
1090 memset(req
->trb
, 0, sizeof(struct dwc3_trb
));
1091 dep
->queued_requests
--;
1092 dwc3_gadget_giveback(dep
, req
, ret
);
1096 dep
->flags
|= DWC3_EP_BUSY
;
1099 dep
->resource_index
= dwc3_gadget_ep_get_transfer_index(dep
);
1100 WARN_ON_ONCE(!dep
->resource_index
);
1106 static int __dwc3_gadget_get_frame(struct dwc3
*dwc
)
1110 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1111 return DWC3_DSTS_SOFFN(reg
);
1114 static void __dwc3_gadget_start_isoc(struct dwc3
*dwc
,
1115 struct dwc3_ep
*dep
, u32 cur_uf
)
1119 if (list_empty(&dep
->pending_list
)) {
1120 dev_info(dwc
->dev
, "%s: ran out of requests\n",
1122 dep
->flags
|= DWC3_EP_PENDING_REQUEST
;
1126 /* 4 micro frames in the future */
1127 uf
= cur_uf
+ dep
->interval
* 4;
1129 __dwc3_gadget_kick_transfer(dep
, uf
);
1132 static void dwc3_gadget_start_isoc(struct dwc3
*dwc
,
1133 struct dwc3_ep
*dep
, const struct dwc3_event_depevt
*event
)
1137 mask
= ~(dep
->interval
- 1);
1138 cur_uf
= event
->parameters
& mask
;
1140 __dwc3_gadget_start_isoc(dwc
, dep
, cur_uf
);
1143 static int __dwc3_gadget_ep_queue(struct dwc3_ep
*dep
, struct dwc3_request
*req
)
1145 struct dwc3
*dwc
= dep
->dwc
;
1148 if (!dep
->endpoint
.desc
) {
1149 dev_err(dwc
->dev
, "%s: can't queue to disabled endpoint\n",
1154 if (WARN(req
->dep
!= dep
, "request %p belongs to '%s'\n",
1155 &req
->request
, req
->dep
->name
)) {
1156 dev_err(dwc
->dev
, "%s: request %p belongs to '%s'\n",
1157 dep
->name
, &req
->request
, req
->dep
->name
);
1161 pm_runtime_get(dwc
->dev
);
1163 req
->request
.actual
= 0;
1164 req
->request
.status
= -EINPROGRESS
;
1165 req
->direction
= dep
->direction
;
1166 req
->epnum
= dep
->number
;
1168 trace_dwc3_ep_queue(req
);
1170 ret
= usb_gadget_map_request(&dwc
->gadget
, &req
->request
,
1175 req
->sg
= req
->request
.sg
;
1176 req
->num_pending_sgs
= req
->request
.num_mapped_sgs
;
1178 list_add_tail(&req
->list
, &dep
->pending_list
);
1181 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1182 * wait for a XferNotReady event so we will know what's the current
1183 * (micro-)frame number.
1185 * Without this trick, we are very, very likely gonna get Bus Expiry
1186 * errors which will force us issue EndTransfer command.
1188 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1189 if ((dep
->flags
& DWC3_EP_PENDING_REQUEST
)) {
1190 if (dep
->flags
& DWC3_EP_TRANSFER_STARTED
) {
1191 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
1192 dep
->flags
= DWC3_EP_ENABLED
;
1196 cur_uf
= __dwc3_gadget_get_frame(dwc
);
1197 __dwc3_gadget_start_isoc(dwc
, dep
, cur_uf
);
1198 dep
->flags
&= ~DWC3_EP_PENDING_REQUEST
;
1204 if (!dwc3_calc_trbs_left(dep
))
1207 ret
= __dwc3_gadget_kick_transfer(dep
, 0);
1214 static void __dwc3_gadget_ep_zlp_complete(struct usb_ep
*ep
,
1215 struct usb_request
*request
)
1217 dwc3_gadget_ep_free_request(ep
, request
);
1220 static int __dwc3_gadget_ep_queue_zlp(struct dwc3
*dwc
, struct dwc3_ep
*dep
)
1222 struct dwc3_request
*req
;
1223 struct usb_request
*request
;
1224 struct usb_ep
*ep
= &dep
->endpoint
;
1226 request
= dwc3_gadget_ep_alloc_request(ep
, GFP_ATOMIC
);
1230 request
->length
= 0;
1231 request
->buf
= dwc
->zlp_buf
;
1232 request
->complete
= __dwc3_gadget_ep_zlp_complete
;
1234 req
= to_dwc3_request(request
);
1236 return __dwc3_gadget_ep_queue(dep
, req
);
1239 static int dwc3_gadget_ep_queue(struct usb_ep
*ep
, struct usb_request
*request
,
1242 struct dwc3_request
*req
= to_dwc3_request(request
);
1243 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1244 struct dwc3
*dwc
= dep
->dwc
;
1246 unsigned long flags
;
1250 spin_lock_irqsave(&dwc
->lock
, flags
);
1251 ret
= __dwc3_gadget_ep_queue(dep
, req
);
1254 * Okay, here's the thing, if gadget driver has requested for a ZLP by
1255 * setting request->zero, instead of doing magic, we will just queue an
1256 * extra usb_request ourselves so that it gets handled the same way as
1257 * any other request.
1259 if (ret
== 0 && request
->zero
&& request
->length
&&
1260 (request
->length
% ep
->maxpacket
== 0))
1261 ret
= __dwc3_gadget_ep_queue_zlp(dwc
, dep
);
1263 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1268 static int dwc3_gadget_ep_dequeue(struct usb_ep
*ep
,
1269 struct usb_request
*request
)
1271 struct dwc3_request
*req
= to_dwc3_request(request
);
1272 struct dwc3_request
*r
= NULL
;
1274 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1275 struct dwc3
*dwc
= dep
->dwc
;
1277 unsigned long flags
;
1280 trace_dwc3_ep_dequeue(req
);
1282 spin_lock_irqsave(&dwc
->lock
, flags
);
1284 list_for_each_entry(r
, &dep
->pending_list
, list
) {
1290 list_for_each_entry(r
, &dep
->started_list
, list
) {
1295 /* wait until it is processed */
1296 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
1299 dev_err(dwc
->dev
, "request %p was not queued to %s\n",
1306 /* giveback the request */
1307 dwc3_gadget_giveback(dep
, req
, -ECONNRESET
);
1310 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1315 int __dwc3_gadget_ep_set_halt(struct dwc3_ep
*dep
, int value
, int protocol
)
1317 struct dwc3_gadget_ep_cmd_params params
;
1318 struct dwc3
*dwc
= dep
->dwc
;
1321 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
1322 dev_err(dwc
->dev
, "%s is of Isochronous type\n", dep
->name
);
1326 memset(¶ms
, 0x00, sizeof(params
));
1329 struct dwc3_trb
*trb
;
1331 unsigned transfer_in_flight
;
1334 if (dep
->number
> 1)
1335 trb
= dwc3_ep_prev_trb(dep
, dep
->trb_enqueue
);
1337 trb
= &dwc
->ep0_trb
[dep
->trb_enqueue
];
1339 transfer_in_flight
= trb
->ctrl
& DWC3_TRB_CTRL_HWO
;
1340 started
= !list_empty(&dep
->started_list
);
1342 if (!protocol
&& ((dep
->direction
&& transfer_in_flight
) ||
1343 (!dep
->direction
&& started
))) {
1347 ret
= dwc3_send_gadget_ep_cmd(dep
, DWC3_DEPCMD_SETSTALL
,
1350 dev_err(dwc
->dev
, "failed to set STALL on %s\n",
1353 dep
->flags
|= DWC3_EP_STALL
;
1356 ret
= dwc3_send_clear_stall_ep_cmd(dep
);
1358 dev_err(dwc
->dev
, "failed to clear STALL on %s\n",
1361 dep
->flags
&= ~(DWC3_EP_STALL
| DWC3_EP_WEDGE
);
1367 static int dwc3_gadget_ep_set_halt(struct usb_ep
*ep
, int value
)
1369 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1370 struct dwc3
*dwc
= dep
->dwc
;
1372 unsigned long flags
;
1376 spin_lock_irqsave(&dwc
->lock
, flags
);
1377 ret
= __dwc3_gadget_ep_set_halt(dep
, value
, false);
1378 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1383 static int dwc3_gadget_ep_set_wedge(struct usb_ep
*ep
)
1385 struct dwc3_ep
*dep
= to_dwc3_ep(ep
);
1386 struct dwc3
*dwc
= dep
->dwc
;
1387 unsigned long flags
;
1390 spin_lock_irqsave(&dwc
->lock
, flags
);
1391 dep
->flags
|= DWC3_EP_WEDGE
;
1393 if (dep
->number
== 0 || dep
->number
== 1)
1394 ret
= __dwc3_gadget_ep0_set_halt(ep
, 1);
1396 ret
= __dwc3_gadget_ep_set_halt(dep
, 1, false);
1397 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1402 /* -------------------------------------------------------------------------- */
1404 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc
= {
1405 .bLength
= USB_DT_ENDPOINT_SIZE
,
1406 .bDescriptorType
= USB_DT_ENDPOINT
,
1407 .bmAttributes
= USB_ENDPOINT_XFER_CONTROL
,
1410 static const struct usb_ep_ops dwc3_gadget_ep0_ops
= {
1411 .enable
= dwc3_gadget_ep0_enable
,
1412 .disable
= dwc3_gadget_ep0_disable
,
1413 .alloc_request
= dwc3_gadget_ep_alloc_request
,
1414 .free_request
= dwc3_gadget_ep_free_request
,
1415 .queue
= dwc3_gadget_ep0_queue
,
1416 .dequeue
= dwc3_gadget_ep_dequeue
,
1417 .set_halt
= dwc3_gadget_ep0_set_halt
,
1418 .set_wedge
= dwc3_gadget_ep_set_wedge
,
1421 static const struct usb_ep_ops dwc3_gadget_ep_ops
= {
1422 .enable
= dwc3_gadget_ep_enable
,
1423 .disable
= dwc3_gadget_ep_disable
,
1424 .alloc_request
= dwc3_gadget_ep_alloc_request
,
1425 .free_request
= dwc3_gadget_ep_free_request
,
1426 .queue
= dwc3_gadget_ep_queue
,
1427 .dequeue
= dwc3_gadget_ep_dequeue
,
1428 .set_halt
= dwc3_gadget_ep_set_halt
,
1429 .set_wedge
= dwc3_gadget_ep_set_wedge
,
1432 /* -------------------------------------------------------------------------- */
1434 static int dwc3_gadget_get_frame(struct usb_gadget
*g
)
1436 struct dwc3
*dwc
= gadget_to_dwc(g
);
1438 return __dwc3_gadget_get_frame(dwc
);
1441 static int __dwc3_gadget_wakeup(struct dwc3
*dwc
)
1452 * According to the Databook Remote wakeup request should
1453 * be issued only when the device is in early suspend state.
1455 * We can check that via USB Link State bits in DSTS register.
1457 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1459 speed
= reg
& DWC3_DSTS_CONNECTSPD
;
1460 if ((speed
== DWC3_DSTS_SUPERSPEED
) ||
1461 (speed
== DWC3_DSTS_SUPERSPEED_PLUS
))
1464 link_state
= DWC3_DSTS_USBLNKST(reg
);
1466 switch (link_state
) {
1467 case DWC3_LINK_STATE_RX_DET
: /* in HS, means Early Suspend */
1468 case DWC3_LINK_STATE_U3
: /* in HS, means SUSPEND */
1474 ret
= dwc3_gadget_set_link_state(dwc
, DWC3_LINK_STATE_RECOV
);
1476 dev_err(dwc
->dev
, "failed to put link in Recovery\n");
1480 /* Recent versions do this automatically */
1481 if (dwc
->revision
< DWC3_REVISION_194A
) {
1482 /* write zeroes to Link Change Request */
1483 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1484 reg
&= ~DWC3_DCTL_ULSTCHNGREQ_MASK
;
1485 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1488 /* poll until Link State changes to ON */
1492 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1494 /* in HS, means ON */
1495 if (DWC3_DSTS_USBLNKST(reg
) == DWC3_LINK_STATE_U0
)
1499 if (DWC3_DSTS_USBLNKST(reg
) != DWC3_LINK_STATE_U0
) {
1500 dev_err(dwc
->dev
, "failed to send remote wakeup\n");
1507 static int dwc3_gadget_wakeup(struct usb_gadget
*g
)
1509 struct dwc3
*dwc
= gadget_to_dwc(g
);
1510 unsigned long flags
;
1513 spin_lock_irqsave(&dwc
->lock
, flags
);
1514 ret
= __dwc3_gadget_wakeup(dwc
);
1515 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1520 static int dwc3_gadget_set_selfpowered(struct usb_gadget
*g
,
1523 struct dwc3
*dwc
= gadget_to_dwc(g
);
1524 unsigned long flags
;
1526 spin_lock_irqsave(&dwc
->lock
, flags
);
1527 g
->is_selfpowered
= !!is_selfpowered
;
1528 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1533 static int dwc3_gadget_run_stop(struct dwc3
*dwc
, int is_on
, int suspend
)
1538 if (pm_runtime_suspended(dwc
->dev
))
1541 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
1543 if (dwc
->revision
<= DWC3_REVISION_187A
) {
1544 reg
&= ~DWC3_DCTL_TRGTULST_MASK
;
1545 reg
|= DWC3_DCTL_TRGTULST_RX_DET
;
1548 if (dwc
->revision
>= DWC3_REVISION_194A
)
1549 reg
&= ~DWC3_DCTL_KEEP_CONNECT
;
1550 reg
|= DWC3_DCTL_RUN_STOP
;
1552 if (dwc
->has_hibernation
)
1553 reg
|= DWC3_DCTL_KEEP_CONNECT
;
1555 dwc
->pullups_connected
= true;
1557 reg
&= ~DWC3_DCTL_RUN_STOP
;
1559 if (dwc
->has_hibernation
&& !suspend
)
1560 reg
&= ~DWC3_DCTL_KEEP_CONNECT
;
1562 dwc
->pullups_connected
= false;
1565 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
1568 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
1569 reg
&= DWC3_DSTS_DEVCTRLHLT
;
1570 } while (--timeout
&& !(!is_on
^ !reg
));
1578 static int dwc3_gadget_pullup(struct usb_gadget
*g
, int is_on
)
1580 struct dwc3
*dwc
= gadget_to_dwc(g
);
1581 unsigned long flags
;
1587 * Per databook, when we want to stop the gadget, if a control transfer
1588 * is still in process, complete it and get the core into setup phase.
1590 if (!is_on
&& dwc
->ep0state
!= EP0_SETUP_PHASE
) {
1591 reinit_completion(&dwc
->ep0_in_setup
);
1593 ret
= wait_for_completion_timeout(&dwc
->ep0_in_setup
,
1594 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT
));
1596 dev_err(dwc
->dev
, "timed out waiting for SETUP phase\n");
1601 spin_lock_irqsave(&dwc
->lock
, flags
);
1602 ret
= dwc3_gadget_run_stop(dwc
, is_on
, false);
1603 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1608 static void dwc3_gadget_enable_irq(struct dwc3
*dwc
)
1612 /* Enable all but Start and End of Frame IRQs */
1613 reg
= (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN
|
1614 DWC3_DEVTEN_EVNTOVERFLOWEN
|
1615 DWC3_DEVTEN_CMDCMPLTEN
|
1616 DWC3_DEVTEN_ERRTICERREN
|
1617 DWC3_DEVTEN_WKUPEVTEN
|
1618 DWC3_DEVTEN_CONNECTDONEEN
|
1619 DWC3_DEVTEN_USBRSTEN
|
1620 DWC3_DEVTEN_DISCONNEVTEN
);
1622 if (dwc
->revision
< DWC3_REVISION_250A
)
1623 reg
|= DWC3_DEVTEN_ULSTCNGEN
;
1625 dwc3_writel(dwc
->regs
, DWC3_DEVTEN
, reg
);
1628 static void dwc3_gadget_disable_irq(struct dwc3
*dwc
)
1630 /* mask all interrupts */
1631 dwc3_writel(dwc
->regs
, DWC3_DEVTEN
, 0x00);
1634 static irqreturn_t
dwc3_interrupt(int irq
, void *_dwc
);
1635 static irqreturn_t
dwc3_thread_interrupt(int irq
, void *_dwc
);
1638 * dwc3_gadget_setup_nump - Calculate and initialize NUMP field of DCFG
1639 * dwc: pointer to our context structure
1641 * The following looks like complex but it's actually very simple. In order to
1642 * calculate the number of packets we can burst at once on OUT transfers, we're
1643 * gonna use RxFIFO size.
1645 * To calculate RxFIFO size we need two numbers:
1646 * MDWIDTH = size, in bits, of the internal memory bus
1647 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1649 * Given these two numbers, the formula is simple:
1651 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1653 * 24 bytes is for 3x SETUP packets
1654 * 16 bytes is a clock domain crossing tolerance
1656 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1658 static void dwc3_gadget_setup_nump(struct dwc3
*dwc
)
1665 ram2_depth
= DWC3_GHWPARAMS7_RAM2_DEPTH(dwc
->hwparams
.hwparams7
);
1666 mdwidth
= DWC3_GHWPARAMS0_MDWIDTH(dwc
->hwparams
.hwparams0
);
1668 nump
= ((ram2_depth
* mdwidth
/ 8) - 24 - 16) / 1024;
1669 nump
= min_t(u32
, nump
, 16);
1672 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
1673 reg
&= ~DWC3_DCFG_NUMP_MASK
;
1674 reg
|= nump
<< DWC3_DCFG_NUMP_SHIFT
;
1675 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
1678 static int __dwc3_gadget_start(struct dwc3
*dwc
)
1680 struct dwc3_ep
*dep
;
1684 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
1685 reg
&= ~(DWC3_DCFG_SPEED_MASK
);
1688 * WORKAROUND: DWC3 revision < 2.20a have an issue
1689 * which would cause metastability state on Run/Stop
1690 * bit if we try to force the IP to USB2-only mode.
1692 * Because of that, we cannot configure the IP to any
1693 * speed other than the SuperSpeed
1697 * STAR#9000525659: Clock Domain Crossing on DCTL in
1700 if (dwc
->revision
< DWC3_REVISION_220A
) {
1701 reg
|= DWC3_DCFG_SUPERSPEED
;
1703 switch (dwc
->maximum_speed
) {
1705 reg
|= DWC3_DCFG_LOWSPEED
;
1707 case USB_SPEED_FULL
:
1708 reg
|= DWC3_DCFG_FULLSPEED1
;
1710 case USB_SPEED_HIGH
:
1711 reg
|= DWC3_DCFG_HIGHSPEED
;
1713 case USB_SPEED_SUPER_PLUS
:
1714 reg
|= DWC3_DCFG_SUPERSPEED_PLUS
;
1717 dev_err(dwc
->dev
, "invalid dwc->maximum_speed (%d)\n",
1718 dwc
->maximum_speed
);
1720 case USB_SPEED_SUPER
:
1721 reg
|= DWC3_DCFG_SUPERSPEED
;
1725 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
1728 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1729 * field instead of letting dwc3 itself calculate that automatically.
1731 * This way, we maximize the chances that we'll be able to get several
1732 * bursts of data without going through any sort of endpoint throttling.
1734 reg
= dwc3_readl(dwc
->regs
, DWC3_GRXTHRCFG
);
1735 reg
&= ~DWC3_GRXTHRCFG_PKTCNTSEL
;
1736 dwc3_writel(dwc
->regs
, DWC3_GRXTHRCFG
, reg
);
1738 dwc3_gadget_setup_nump(dwc
);
1740 /* Start with SuperSpeed Default */
1741 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
1744 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, false,
1747 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
1752 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, false,
1755 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
1759 /* begin to receive SETUP packets */
1760 dwc
->ep0state
= EP0_SETUP_PHASE
;
1761 dwc3_ep0_out_start(dwc
);
1763 dwc3_gadget_enable_irq(dwc
);
1768 __dwc3_gadget_ep_disable(dwc
->eps
[0]);
1774 static int dwc3_gadget_start(struct usb_gadget
*g
,
1775 struct usb_gadget_driver
*driver
)
1777 struct dwc3
*dwc
= gadget_to_dwc(g
);
1778 unsigned long flags
;
1782 irq
= dwc
->irq_gadget
;
1783 ret
= request_threaded_irq(irq
, dwc3_interrupt
, dwc3_thread_interrupt
,
1784 IRQF_SHARED
, "dwc3", dwc
->ev_buf
);
1786 dev_err(dwc
->dev
, "failed to request irq #%d --> %d\n",
1791 spin_lock_irqsave(&dwc
->lock
, flags
);
1792 if (dwc
->gadget_driver
) {
1793 dev_err(dwc
->dev
, "%s is already bound to %s\n",
1795 dwc
->gadget_driver
->driver
.name
);
1800 dwc
->gadget_driver
= driver
;
1802 if (pm_runtime_active(dwc
->dev
))
1803 __dwc3_gadget_start(dwc
);
1805 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1810 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1817 static void __dwc3_gadget_stop(struct dwc3
*dwc
)
1819 dwc3_gadget_disable_irq(dwc
);
1820 __dwc3_gadget_ep_disable(dwc
->eps
[0]);
1821 __dwc3_gadget_ep_disable(dwc
->eps
[1]);
1824 static int dwc3_gadget_stop(struct usb_gadget
*g
)
1826 struct dwc3
*dwc
= gadget_to_dwc(g
);
1827 unsigned long flags
;
1830 spin_lock_irqsave(&dwc
->lock
, flags
);
1832 if (pm_runtime_suspended(dwc
->dev
))
1835 __dwc3_gadget_stop(dwc
);
1837 for (epnum
= 2; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
1838 struct dwc3_ep
*dep
= dwc
->eps
[epnum
];
1843 if (!(dep
->flags
& DWC3_EP_END_TRANSFER_PENDING
))
1846 wait_event_lock_irq(dep
->wait_end_transfer
,
1847 !(dep
->flags
& DWC3_EP_END_TRANSFER_PENDING
),
1852 dwc
->gadget_driver
= NULL
;
1853 spin_unlock_irqrestore(&dwc
->lock
, flags
);
1855 free_irq(dwc
->irq_gadget
, dwc
->ev_buf
);
1860 static const struct usb_gadget_ops dwc3_gadget_ops
= {
1861 .get_frame
= dwc3_gadget_get_frame
,
1862 .wakeup
= dwc3_gadget_wakeup
,
1863 .set_selfpowered
= dwc3_gadget_set_selfpowered
,
1864 .pullup
= dwc3_gadget_pullup
,
1865 .udc_start
= dwc3_gadget_start
,
1866 .udc_stop
= dwc3_gadget_stop
,
1869 /* -------------------------------------------------------------------------- */
1871 static int dwc3_gadget_init_hw_endpoints(struct dwc3
*dwc
,
1872 u8 num
, u32 direction
)
1874 struct dwc3_ep
*dep
;
1877 for (i
= 0; i
< num
; i
++) {
1878 u8 epnum
= (i
<< 1) | (direction
? 1 : 0);
1880 dep
= kzalloc(sizeof(*dep
), GFP_KERNEL
);
1885 dep
->number
= epnum
;
1886 dep
->direction
= !!direction
;
1887 dep
->regs
= dwc
->regs
+ DWC3_DEP_BASE(epnum
);
1888 dwc
->eps
[epnum
] = dep
;
1890 snprintf(dep
->name
, sizeof(dep
->name
), "ep%d%s", epnum
>> 1,
1891 (epnum
& 1) ? "in" : "out");
1893 dep
->endpoint
.name
= dep
->name
;
1894 spin_lock_init(&dep
->lock
);
1896 if (epnum
== 0 || epnum
== 1) {
1897 usb_ep_set_maxpacket_limit(&dep
->endpoint
, 512);
1898 dep
->endpoint
.maxburst
= 1;
1899 dep
->endpoint
.ops
= &dwc3_gadget_ep0_ops
;
1901 dwc
->gadget
.ep0
= &dep
->endpoint
;
1905 usb_ep_set_maxpacket_limit(&dep
->endpoint
, 1024);
1906 dep
->endpoint
.max_streams
= 15;
1907 dep
->endpoint
.ops
= &dwc3_gadget_ep_ops
;
1908 list_add_tail(&dep
->endpoint
.ep_list
,
1909 &dwc
->gadget
.ep_list
);
1911 ret
= dwc3_alloc_trb_pool(dep
);
1916 if (epnum
== 0 || epnum
== 1) {
1917 dep
->endpoint
.caps
.type_control
= true;
1919 dep
->endpoint
.caps
.type_iso
= true;
1920 dep
->endpoint
.caps
.type_bulk
= true;
1921 dep
->endpoint
.caps
.type_int
= true;
1924 dep
->endpoint
.caps
.dir_in
= !!direction
;
1925 dep
->endpoint
.caps
.dir_out
= !direction
;
1927 INIT_LIST_HEAD(&dep
->pending_list
);
1928 INIT_LIST_HEAD(&dep
->started_list
);
1934 static int dwc3_gadget_init_endpoints(struct dwc3
*dwc
)
1938 INIT_LIST_HEAD(&dwc
->gadget
.ep_list
);
1940 ret
= dwc3_gadget_init_hw_endpoints(dwc
, dwc
->num_out_eps
, 0);
1942 dev_err(dwc
->dev
, "failed to initialize OUT endpoints\n");
1946 ret
= dwc3_gadget_init_hw_endpoints(dwc
, dwc
->num_in_eps
, 1);
1948 dev_err(dwc
->dev
, "failed to initialize IN endpoints\n");
1955 static void dwc3_gadget_free_endpoints(struct dwc3
*dwc
)
1957 struct dwc3_ep
*dep
;
1960 for (epnum
= 0; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
1961 dep
= dwc
->eps
[epnum
];
1965 * Physical endpoints 0 and 1 are special; they form the
1966 * bi-directional USB endpoint 0.
1968 * For those two physical endpoints, we don't allocate a TRB
1969 * pool nor do we add them the endpoints list. Due to that, we
1970 * shouldn't do these two operations otherwise we would end up
1971 * with all sorts of bugs when removing dwc3.ko.
1973 if (epnum
!= 0 && epnum
!= 1) {
1974 dwc3_free_trb_pool(dep
);
1975 list_del(&dep
->endpoint
.ep_list
);
1982 /* -------------------------------------------------------------------------- */
1984 static int __dwc3_cleanup_done_trbs(struct dwc3
*dwc
, struct dwc3_ep
*dep
,
1985 struct dwc3_request
*req
, struct dwc3_trb
*trb
,
1986 const struct dwc3_event_depevt
*event
, int status
,
1990 unsigned int s_pkt
= 0;
1991 unsigned int trb_status
;
1993 dwc3_ep_inc_deq(dep
);
1995 if (req
->trb
== trb
)
1996 dep
->queued_requests
--;
1998 trace_dwc3_complete_trb(dep
, trb
);
2001 * If we're in the middle of series of chained TRBs and we
2002 * receive a short transfer along the way, DWC3 will skip
2003 * through all TRBs including the last TRB in the chain (the
2004 * where CHN bit is zero. DWC3 will also avoid clearing HWO
2005 * bit and SW has to do it manually.
2007 * We're going to do that here to avoid problems of HW trying
2008 * to use bogus TRBs for transfers.
2010 if (chain
&& (trb
->ctrl
& DWC3_TRB_CTRL_HWO
))
2011 trb
->ctrl
&= ~DWC3_TRB_CTRL_HWO
;
2013 if ((trb
->ctrl
& DWC3_TRB_CTRL_HWO
) && status
!= -ESHUTDOWN
)
2016 count
= trb
->size
& DWC3_TRB_SIZE_MASK
;
2017 req
->remaining
+= count
;
2019 if (dep
->direction
) {
2021 trb_status
= DWC3_TRB_SIZE_TRBSTS(trb
->size
);
2022 if (trb_status
== DWC3_TRBSTS_MISSED_ISOC
) {
2024 * If missed isoc occurred and there is
2025 * no request queued then issue END
2026 * TRANSFER, so that core generates
2027 * next xfernotready and we will issue
2028 * a fresh START TRANSFER.
2029 * If there are still queued request
2030 * then wait, do not issue either END
2031 * or UPDATE TRANSFER, just attach next
2032 * request in pending_list during
2033 * giveback.If any future queued request
2034 * is successfully transferred then we
2035 * will issue UPDATE TRANSFER for all
2036 * request in the pending_list.
2038 dep
->flags
|= DWC3_EP_MISSED_ISOC
;
2040 dev_err(dwc
->dev
, "incomplete IN transfer %s\n",
2042 status
= -ECONNRESET
;
2045 dep
->flags
&= ~DWC3_EP_MISSED_ISOC
;
2048 if (count
&& (event
->status
& DEPEVT_STATUS_SHORT
))
2052 if (s_pkt
&& !chain
)
2055 if ((event
->status
& DEPEVT_STATUS_IOC
) &&
2056 (trb
->ctrl
& DWC3_TRB_CTRL_IOC
))
2062 static int dwc3_cleanup_done_reqs(struct dwc3
*dwc
, struct dwc3_ep
*dep
,
2063 const struct dwc3_event_depevt
*event
, int status
)
2065 struct dwc3_request
*req
, *n
;
2066 struct dwc3_trb
*trb
;
2070 list_for_each_entry_safe(req
, n
, &dep
->started_list
, list
) {
2074 length
= req
->request
.length
;
2075 chain
= req
->num_pending_sgs
> 0;
2077 struct scatterlist
*sg
= req
->sg
;
2078 struct scatterlist
*s
;
2079 unsigned int pending
= req
->num_pending_sgs
;
2082 for_each_sg(sg
, s
, pending
, i
) {
2083 trb
= &dep
->trb_pool
[dep
->trb_dequeue
];
2085 if (trb
->ctrl
& DWC3_TRB_CTRL_HWO
)
2088 req
->sg
= sg_next(s
);
2089 req
->num_pending_sgs
--;
2091 ret
= __dwc3_cleanup_done_trbs(dwc
, dep
, req
, trb
,
2092 event
, status
, chain
);
2097 trb
= &dep
->trb_pool
[dep
->trb_dequeue
];
2098 ret
= __dwc3_cleanup_done_trbs(dwc
, dep
, req
, trb
,
2099 event
, status
, chain
);
2102 req
->request
.actual
= length
- req
->remaining
;
2104 if ((req
->request
.actual
< length
) && req
->num_pending_sgs
)
2105 return __dwc3_gadget_kick_transfer(dep
, 0);
2107 dwc3_gadget_giveback(dep
, req
, status
);
2110 if ((event
->status
& DEPEVT_STATUS_IOC
) &&
2111 (trb
->ctrl
& DWC3_TRB_CTRL_IOC
))
2118 * Our endpoint might get disabled by another thread during
2119 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2120 * early on so DWC3_EP_BUSY flag gets cleared
2122 if (!dep
->endpoint
.desc
)
2125 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
) &&
2126 list_empty(&dep
->started_list
)) {
2127 if (list_empty(&dep
->pending_list
)) {
2129 * If there is no entry in request list then do
2130 * not issue END TRANSFER now. Just set PENDING
2131 * flag, so that END TRANSFER is issued when an
2132 * entry is added into request list.
2134 dep
->flags
= DWC3_EP_PENDING_REQUEST
;
2136 dwc3_stop_active_transfer(dwc
, dep
->number
, true);
2137 dep
->flags
= DWC3_EP_ENABLED
;
2142 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
) && ioc
)
2148 static void dwc3_endpoint_transfer_complete(struct dwc3
*dwc
,
2149 struct dwc3_ep
*dep
, const struct dwc3_event_depevt
*event
)
2151 unsigned status
= 0;
2153 u32 is_xfer_complete
;
2155 is_xfer_complete
= (event
->endpoint_event
== DWC3_DEPEVT_XFERCOMPLETE
);
2157 if (event
->status
& DEPEVT_STATUS_BUSERR
)
2158 status
= -ECONNRESET
;
2160 clean_busy
= dwc3_cleanup_done_reqs(dwc
, dep
, event
, status
);
2161 if (clean_busy
&& (!dep
->endpoint
.desc
|| is_xfer_complete
||
2162 usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)))
2163 dep
->flags
&= ~DWC3_EP_BUSY
;
2166 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2167 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2169 if (dwc
->revision
< DWC3_REVISION_183A
) {
2173 for (i
= 0; i
< DWC3_ENDPOINTS_NUM
; i
++) {
2176 if (!(dep
->flags
& DWC3_EP_ENABLED
))
2179 if (!list_empty(&dep
->started_list
))
2183 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2185 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2191 * Our endpoint might get disabled by another thread during
2192 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2193 * early on so DWC3_EP_BUSY flag gets cleared
2195 if (!dep
->endpoint
.desc
)
2198 if (!usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
2201 ret
= __dwc3_gadget_kick_transfer(dep
, 0);
2202 if (!ret
|| ret
== -EBUSY
)
2207 static void dwc3_endpoint_interrupt(struct dwc3
*dwc
,
2208 const struct dwc3_event_depevt
*event
)
2210 struct dwc3_ep
*dep
;
2211 u8 epnum
= event
->endpoint_number
;
2214 dep
= dwc
->eps
[epnum
];
2216 if (!(dep
->flags
& DWC3_EP_ENABLED
) &&
2217 !(dep
->flags
& DWC3_EP_END_TRANSFER_PENDING
))
2220 if (epnum
== 0 || epnum
== 1) {
2221 dwc3_ep0_interrupt(dwc
, event
);
2225 switch (event
->endpoint_event
) {
2226 case DWC3_DEPEVT_XFERCOMPLETE
:
2227 dep
->resource_index
= 0;
2229 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
2230 dev_err(dwc
->dev
, "XferComplete for Isochronous endpoint\n");
2234 dwc3_endpoint_transfer_complete(dwc
, dep
, event
);
2236 case DWC3_DEPEVT_XFERINPROGRESS
:
2237 dwc3_endpoint_transfer_complete(dwc
, dep
, event
);
2239 case DWC3_DEPEVT_XFERNOTREADY
:
2240 if (usb_endpoint_xfer_isoc(dep
->endpoint
.desc
)) {
2241 dwc3_gadget_start_isoc(dwc
, dep
, event
);
2245 ret
= __dwc3_gadget_kick_transfer(dep
, 0);
2246 if (!ret
|| ret
== -EBUSY
)
2251 case DWC3_DEPEVT_STREAMEVT
:
2252 if (!usb_endpoint_xfer_bulk(dep
->endpoint
.desc
)) {
2253 dev_err(dwc
->dev
, "Stream event for non-Bulk %s\n",
2258 case DWC3_DEPEVT_EPCMDCMPLT
:
2259 cmd
= DEPEVT_PARAMETER_CMD(event
->parameters
);
2261 if (cmd
== DWC3_DEPCMD_ENDTRANSFER
) {
2262 dep
->flags
&= ~DWC3_EP_END_TRANSFER_PENDING
;
2263 wake_up(&dep
->wait_end_transfer
);
2266 case DWC3_DEPEVT_RXTXFIFOEVT
:
2271 static void dwc3_disconnect_gadget(struct dwc3
*dwc
)
2273 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->disconnect
) {
2274 spin_unlock(&dwc
->lock
);
2275 dwc
->gadget_driver
->disconnect(&dwc
->gadget
);
2276 spin_lock(&dwc
->lock
);
2280 static void dwc3_suspend_gadget(struct dwc3
*dwc
)
2282 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->suspend
) {
2283 spin_unlock(&dwc
->lock
);
2284 dwc
->gadget_driver
->suspend(&dwc
->gadget
);
2285 spin_lock(&dwc
->lock
);
2289 static void dwc3_resume_gadget(struct dwc3
*dwc
)
2291 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->resume
) {
2292 spin_unlock(&dwc
->lock
);
2293 dwc
->gadget_driver
->resume(&dwc
->gadget
);
2294 spin_lock(&dwc
->lock
);
2298 static void dwc3_reset_gadget(struct dwc3
*dwc
)
2300 if (!dwc
->gadget_driver
)
2303 if (dwc
->gadget
.speed
!= USB_SPEED_UNKNOWN
) {
2304 spin_unlock(&dwc
->lock
);
2305 usb_gadget_udc_reset(&dwc
->gadget
, dwc
->gadget_driver
);
2306 spin_lock(&dwc
->lock
);
2310 static void dwc3_stop_active_transfer(struct dwc3
*dwc
, u32 epnum
, bool force
)
2312 struct dwc3_ep
*dep
;
2313 struct dwc3_gadget_ep_cmd_params params
;
2317 dep
= dwc
->eps
[epnum
];
2319 if ((dep
->flags
& DWC3_EP_END_TRANSFER_PENDING
) ||
2320 !dep
->resource_index
)
2324 * NOTICE: We are violating what the Databook says about the
2325 * EndTransfer command. Ideally we would _always_ wait for the
2326 * EndTransfer Command Completion IRQ, but that's causing too
2327 * much trouble synchronizing between us and gadget driver.
2329 * We have discussed this with the IP Provider and it was
2330 * suggested to giveback all requests here, but give HW some
2331 * extra time to synchronize with the interconnect. We're using
2332 * an arbitrary 100us delay for that.
2334 * Note also that a similar handling was tested by Synopsys
2335 * (thanks a lot Paul) and nothing bad has come out of it.
2336 * In short, what we're doing is:
2338 * - Issue EndTransfer WITH CMDIOC bit set
2341 * As of IP version 3.10a of the DWC_usb3 IP, the controller
2342 * supports a mode to work around the above limitation. The
2343 * software can poll the CMDACT bit in the DEPCMD register
2344 * after issuing a EndTransfer command. This mode is enabled
2345 * by writing GUCTL2[14]. This polling is already done in the
2346 * dwc3_send_gadget_ep_cmd() function so if the mode is
2347 * enabled, the EndTransfer command will have completed upon
2348 * returning from this function and we don't need to delay for
2351 * This mode is NOT available on the DWC_usb31 IP.
2354 cmd
= DWC3_DEPCMD_ENDTRANSFER
;
2355 cmd
|= force
? DWC3_DEPCMD_HIPRI_FORCERM
: 0;
2356 cmd
|= DWC3_DEPCMD_CMDIOC
;
2357 cmd
|= DWC3_DEPCMD_PARAM(dep
->resource_index
);
2358 memset(¶ms
, 0, sizeof(params
));
2359 ret
= dwc3_send_gadget_ep_cmd(dep
, cmd
, ¶ms
);
2361 dep
->resource_index
= 0;
2362 dep
->flags
&= ~DWC3_EP_BUSY
;
2364 if (dwc3_is_usb31(dwc
) || dwc
->revision
< DWC3_REVISION_310A
) {
2365 dep
->flags
|= DWC3_EP_END_TRANSFER_PENDING
;
2370 static void dwc3_clear_stall_all_ep(struct dwc3
*dwc
)
2374 for (epnum
= 1; epnum
< DWC3_ENDPOINTS_NUM
; epnum
++) {
2375 struct dwc3_ep
*dep
;
2378 dep
= dwc
->eps
[epnum
];
2382 if (!(dep
->flags
& DWC3_EP_STALL
))
2385 dep
->flags
&= ~DWC3_EP_STALL
;
2387 ret
= dwc3_send_clear_stall_ep_cmd(dep
);
2392 static void dwc3_gadget_disconnect_interrupt(struct dwc3
*dwc
)
2396 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2397 reg
&= ~DWC3_DCTL_INITU1ENA
;
2398 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2400 reg
&= ~DWC3_DCTL_INITU2ENA
;
2401 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2403 dwc3_disconnect_gadget(dwc
);
2405 dwc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2406 dwc
->setup_packet_pending
= false;
2407 usb_gadget_set_state(&dwc
->gadget
, USB_STATE_NOTATTACHED
);
2409 dwc
->connected
= false;
2412 static void dwc3_gadget_reset_interrupt(struct dwc3
*dwc
)
2416 dwc
->connected
= true;
2419 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2420 * would cause a missing Disconnect Event if there's a
2421 * pending Setup Packet in the FIFO.
2423 * There's no suggested workaround on the official Bug
2424 * report, which states that "unless the driver/application
2425 * is doing any special handling of a disconnect event,
2426 * there is no functional issue".
2428 * Unfortunately, it turns out that we _do_ some special
2429 * handling of a disconnect event, namely complete all
2430 * pending transfers, notify gadget driver of the
2431 * disconnection, and so on.
2433 * Our suggested workaround is to follow the Disconnect
2434 * Event steps here, instead, based on a setup_packet_pending
2435 * flag. Such flag gets set whenever we have a SETUP_PENDING
2436 * status for EP0 TRBs and gets cleared on XferComplete for the
2441 * STAR#9000466709: RTL: Device : Disconnect event not
2442 * generated if setup packet pending in FIFO
2444 if (dwc
->revision
< DWC3_REVISION_188A
) {
2445 if (dwc
->setup_packet_pending
)
2446 dwc3_gadget_disconnect_interrupt(dwc
);
2449 dwc3_reset_gadget(dwc
);
2451 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2452 reg
&= ~DWC3_DCTL_TSTCTRL_MASK
;
2453 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2454 dwc
->test_mode
= false;
2455 dwc3_clear_stall_all_ep(dwc
);
2457 /* Reset device address to zero */
2458 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
2459 reg
&= ~(DWC3_DCFG_DEVADDR_MASK
);
2460 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
2463 static void dwc3_update_ram_clk_sel(struct dwc3
*dwc
, u32 speed
)
2466 u32 usb30_clock
= DWC3_GCTL_CLK_BUS
;
2469 * We change the clock only at SS but I dunno why I would want to do
2470 * this. Maybe it becomes part of the power saving plan.
2473 if ((speed
!= DWC3_DSTS_SUPERSPEED
) &&
2474 (speed
!= DWC3_DSTS_SUPERSPEED_PLUS
))
2478 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2479 * each time on Connect Done.
2484 reg
= dwc3_readl(dwc
->regs
, DWC3_GCTL
);
2485 reg
|= DWC3_GCTL_RAMCLKSEL(usb30_clock
);
2486 dwc3_writel(dwc
->regs
, DWC3_GCTL
, reg
);
2489 static void dwc3_gadget_conndone_interrupt(struct dwc3
*dwc
)
2491 struct dwc3_ep
*dep
;
2496 reg
= dwc3_readl(dwc
->regs
, DWC3_DSTS
);
2497 speed
= reg
& DWC3_DSTS_CONNECTSPD
;
2500 dwc3_update_ram_clk_sel(dwc
, speed
);
2503 case DWC3_DSTS_SUPERSPEED_PLUS
:
2504 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
2505 dwc
->gadget
.ep0
->maxpacket
= 512;
2506 dwc
->gadget
.speed
= USB_SPEED_SUPER_PLUS
;
2508 case DWC3_DSTS_SUPERSPEED
:
2510 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2511 * would cause a missing USB3 Reset event.
2513 * In such situations, we should force a USB3 Reset
2514 * event by calling our dwc3_gadget_reset_interrupt()
2519 * STAR#9000483510: RTL: SS : USB3 reset event may
2520 * not be generated always when the link enters poll
2522 if (dwc
->revision
< DWC3_REVISION_190A
)
2523 dwc3_gadget_reset_interrupt(dwc
);
2525 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(512);
2526 dwc
->gadget
.ep0
->maxpacket
= 512;
2527 dwc
->gadget
.speed
= USB_SPEED_SUPER
;
2529 case DWC3_DSTS_HIGHSPEED
:
2530 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(64);
2531 dwc
->gadget
.ep0
->maxpacket
= 64;
2532 dwc
->gadget
.speed
= USB_SPEED_HIGH
;
2534 case DWC3_DSTS_FULLSPEED2
:
2535 case DWC3_DSTS_FULLSPEED1
:
2536 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(64);
2537 dwc
->gadget
.ep0
->maxpacket
= 64;
2538 dwc
->gadget
.speed
= USB_SPEED_FULL
;
2540 case DWC3_DSTS_LOWSPEED
:
2541 dwc3_gadget_ep0_desc
.wMaxPacketSize
= cpu_to_le16(8);
2542 dwc
->gadget
.ep0
->maxpacket
= 8;
2543 dwc
->gadget
.speed
= USB_SPEED_LOW
;
2547 /* Enable USB2 LPM Capability */
2549 if ((dwc
->revision
> DWC3_REVISION_194A
) &&
2550 (speed
!= DWC3_DSTS_SUPERSPEED
) &&
2551 (speed
!= DWC3_DSTS_SUPERSPEED_PLUS
)) {
2552 reg
= dwc3_readl(dwc
->regs
, DWC3_DCFG
);
2553 reg
|= DWC3_DCFG_LPM_CAP
;
2554 dwc3_writel(dwc
->regs
, DWC3_DCFG
, reg
);
2556 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2557 reg
&= ~(DWC3_DCTL_HIRD_THRES_MASK
| DWC3_DCTL_L1_HIBER_EN
);
2559 reg
|= DWC3_DCTL_HIRD_THRES(dwc
->hird_threshold
);
2562 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2563 * DCFG.LPMCap is set, core responses with an ACK and the
2564 * BESL value in the LPM token is less than or equal to LPM
2567 WARN_ONCE(dwc
->revision
< DWC3_REVISION_240A
2568 && dwc
->has_lpm_erratum
,
2569 "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2571 if (dwc
->has_lpm_erratum
&& dwc
->revision
>= DWC3_REVISION_240A
)
2572 reg
|= DWC3_DCTL_LPM_ERRATA(dwc
->lpm_nyet_threshold
);
2574 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2576 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2577 reg
&= ~DWC3_DCTL_HIRD_THRES_MASK
;
2578 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2582 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, true,
2585 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
2590 ret
= __dwc3_gadget_ep_enable(dep
, &dwc3_gadget_ep0_desc
, NULL
, true,
2593 dev_err(dwc
->dev
, "failed to enable %s\n", dep
->name
);
2598 * Configure PHY via GUSB3PIPECTLn if required.
2600 * Update GTXFIFOSIZn
2602 * In both cases reset values should be sufficient.
2606 static void dwc3_gadget_wakeup_interrupt(struct dwc3
*dwc
)
2609 * TODO take core out of low power mode when that's
2613 if (dwc
->gadget_driver
&& dwc
->gadget_driver
->resume
) {
2614 spin_unlock(&dwc
->lock
);
2615 dwc
->gadget_driver
->resume(&dwc
->gadget
);
2616 spin_lock(&dwc
->lock
);
2620 static void dwc3_gadget_linksts_change_interrupt(struct dwc3
*dwc
,
2621 unsigned int evtinfo
)
2623 enum dwc3_link_state next
= evtinfo
& DWC3_LINK_STATE_MASK
;
2624 unsigned int pwropt
;
2627 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2628 * Hibernation mode enabled which would show up when device detects
2629 * host-initiated U3 exit.
2631 * In that case, device will generate a Link State Change Interrupt
2632 * from U3 to RESUME which is only necessary if Hibernation is
2635 * There are no functional changes due to such spurious event and we
2636 * just need to ignore it.
2640 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2643 pwropt
= DWC3_GHWPARAMS1_EN_PWROPT(dwc
->hwparams
.hwparams1
);
2644 if ((dwc
->revision
< DWC3_REVISION_250A
) &&
2645 (pwropt
!= DWC3_GHWPARAMS1_EN_PWROPT_HIB
)) {
2646 if ((dwc
->link_state
== DWC3_LINK_STATE_U3
) &&
2647 (next
== DWC3_LINK_STATE_RESUME
)) {
2653 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2654 * on the link partner, the USB session might do multiple entry/exit
2655 * of low power states before a transfer takes place.
2657 * Due to this problem, we might experience lower throughput. The
2658 * suggested workaround is to disable DCTL[12:9] bits if we're
2659 * transitioning from U1/U2 to U0 and enable those bits again
2660 * after a transfer completes and there are no pending transfers
2661 * on any of the enabled endpoints.
2663 * This is the first half of that workaround.
2667 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2668 * core send LGO_Ux entering U0
2670 if (dwc
->revision
< DWC3_REVISION_183A
) {
2671 if (next
== DWC3_LINK_STATE_U0
) {
2675 switch (dwc
->link_state
) {
2676 case DWC3_LINK_STATE_U1
:
2677 case DWC3_LINK_STATE_U2
:
2678 reg
= dwc3_readl(dwc
->regs
, DWC3_DCTL
);
2679 u1u2
= reg
& (DWC3_DCTL_INITU2ENA
2680 | DWC3_DCTL_ACCEPTU2ENA
2681 | DWC3_DCTL_INITU1ENA
2682 | DWC3_DCTL_ACCEPTU1ENA
);
2685 dwc
->u1u2
= reg
& u1u2
;
2689 dwc3_writel(dwc
->regs
, DWC3_DCTL
, reg
);
2699 case DWC3_LINK_STATE_U1
:
2700 if (dwc
->speed
== USB_SPEED_SUPER
)
2701 dwc3_suspend_gadget(dwc
);
2703 case DWC3_LINK_STATE_U2
:
2704 case DWC3_LINK_STATE_U3
:
2705 dwc3_suspend_gadget(dwc
);
2707 case DWC3_LINK_STATE_RESUME
:
2708 dwc3_resume_gadget(dwc
);
2715 dwc
->link_state
= next
;
2718 static void dwc3_gadget_suspend_interrupt(struct dwc3
*dwc
,
2719 unsigned int evtinfo
)
2721 enum dwc3_link_state next
= evtinfo
& DWC3_LINK_STATE_MASK
;
2723 if (dwc
->link_state
!= next
&& next
== DWC3_LINK_STATE_U3
)
2724 dwc3_suspend_gadget(dwc
);
2726 dwc
->link_state
= next
;
2729 static void dwc3_gadget_hibernation_interrupt(struct dwc3
*dwc
,
2730 unsigned int evtinfo
)
2732 unsigned int is_ss
= evtinfo
& BIT(4);
2735 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2736 * have a known issue which can cause USB CV TD.9.23 to fail
2739 * Because of this issue, core could generate bogus hibernation
2740 * events which SW needs to ignore.
2744 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2745 * Device Fallback from SuperSpeed
2747 if (is_ss
^ (dwc
->speed
== USB_SPEED_SUPER
))
2750 /* enter hibernation here */
2753 static void dwc3_gadget_interrupt(struct dwc3
*dwc
,
2754 const struct dwc3_event_devt
*event
)
2756 switch (event
->type
) {
2757 case DWC3_DEVICE_EVENT_DISCONNECT
:
2758 dwc3_gadget_disconnect_interrupt(dwc
);
2760 case DWC3_DEVICE_EVENT_RESET
:
2761 dwc3_gadget_reset_interrupt(dwc
);
2763 case DWC3_DEVICE_EVENT_CONNECT_DONE
:
2764 dwc3_gadget_conndone_interrupt(dwc
);
2766 case DWC3_DEVICE_EVENT_WAKEUP
:
2767 dwc3_gadget_wakeup_interrupt(dwc
);
2769 case DWC3_DEVICE_EVENT_HIBER_REQ
:
2770 if (dev_WARN_ONCE(dwc
->dev
, !dwc
->has_hibernation
,
2771 "unexpected hibernation event\n"))
2774 dwc3_gadget_hibernation_interrupt(dwc
, event
->event_info
);
2776 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE
:
2777 dwc3_gadget_linksts_change_interrupt(dwc
, event
->event_info
);
2779 case DWC3_DEVICE_EVENT_EOPF
:
2780 /* It changed to be suspend event for version 2.30a and above */
2781 if (dwc
->revision
>= DWC3_REVISION_230A
) {
2783 * Ignore suspend event until the gadget enters into
2784 * USB_STATE_CONFIGURED state.
2786 if (dwc
->gadget
.state
>= USB_STATE_CONFIGURED
)
2787 dwc3_gadget_suspend_interrupt(dwc
,
2791 case DWC3_DEVICE_EVENT_SOF
:
2792 case DWC3_DEVICE_EVENT_ERRATIC_ERROR
:
2793 case DWC3_DEVICE_EVENT_CMD_CMPL
:
2794 case DWC3_DEVICE_EVENT_OVERFLOW
:
2797 dev_WARN(dwc
->dev
, "UNKNOWN IRQ %d\n", event
->type
);
2801 static void dwc3_process_event_entry(struct dwc3
*dwc
,
2802 const union dwc3_event
*event
)
2804 trace_dwc3_event(event
->raw
, dwc
);
2806 /* Endpoint IRQ, handle it and return early */
2807 if (event
->type
.is_devspec
== 0) {
2809 return dwc3_endpoint_interrupt(dwc
, &event
->depevt
);
2812 switch (event
->type
.type
) {
2813 case DWC3_EVENT_TYPE_DEV
:
2814 dwc3_gadget_interrupt(dwc
, &event
->devt
);
2816 /* REVISIT what to do with Carkit and I2C events ? */
2818 dev_err(dwc
->dev
, "UNKNOWN IRQ type %d\n", event
->raw
);
2822 static irqreturn_t
dwc3_process_event_buf(struct dwc3_event_buffer
*evt
)
2824 struct dwc3
*dwc
= evt
->dwc
;
2825 irqreturn_t ret
= IRQ_NONE
;
2831 if (!(evt
->flags
& DWC3_EVENT_PENDING
))
2835 union dwc3_event event
;
2837 event
.raw
= *(u32
*) (evt
->buf
+ evt
->lpos
);
2839 dwc3_process_event_entry(dwc
, &event
);
2842 * FIXME we wrap around correctly to the next entry as
2843 * almost all entries are 4 bytes in size. There is one
2844 * entry which has 12 bytes which is a regular entry
2845 * followed by 8 bytes data. ATM I don't know how
2846 * things are organized if we get next to the a
2847 * boundary so I worry about that once we try to handle
2850 evt
->lpos
= (evt
->lpos
+ 4) % DWC3_EVENT_BUFFERS_SIZE
;
2853 dwc3_writel(dwc
->regs
, DWC3_GEVNTCOUNT(0), 4);
2857 evt
->flags
&= ~DWC3_EVENT_PENDING
;
2860 /* Unmask interrupt */
2861 reg
= dwc3_readl(dwc
->regs
, DWC3_GEVNTSIZ(0));
2862 reg
&= ~DWC3_GEVNTSIZ_INTMASK
;
2863 dwc3_writel(dwc
->regs
, DWC3_GEVNTSIZ(0), reg
);
2868 static irqreturn_t
dwc3_thread_interrupt(int irq
, void *_evt
)
2870 struct dwc3_event_buffer
*evt
= _evt
;
2871 struct dwc3
*dwc
= evt
->dwc
;
2872 unsigned long flags
;
2873 irqreturn_t ret
= IRQ_NONE
;
2875 spin_lock_irqsave(&dwc
->lock
, flags
);
2876 ret
= dwc3_process_event_buf(evt
);
2877 spin_unlock_irqrestore(&dwc
->lock
, flags
);
2882 static irqreturn_t
dwc3_check_event_buf(struct dwc3_event_buffer
*evt
)
2884 struct dwc3
*dwc
= evt
->dwc
;
2888 if (pm_runtime_suspended(dwc
->dev
)) {
2889 pm_runtime_get(dwc
->dev
);
2890 disable_irq_nosync(dwc
->irq_gadget
);
2891 dwc
->pending_events
= true;
2895 count
= dwc3_readl(dwc
->regs
, DWC3_GEVNTCOUNT(0));
2896 count
&= DWC3_GEVNTCOUNT_MASK
;
2901 evt
->flags
|= DWC3_EVENT_PENDING
;
2903 /* Mask interrupt */
2904 reg
= dwc3_readl(dwc
->regs
, DWC3_GEVNTSIZ(0));
2905 reg
|= DWC3_GEVNTSIZ_INTMASK
;
2906 dwc3_writel(dwc
->regs
, DWC3_GEVNTSIZ(0), reg
);
2908 return IRQ_WAKE_THREAD
;
2911 static irqreturn_t
dwc3_interrupt(int irq
, void *_evt
)
2913 struct dwc3_event_buffer
*evt
= _evt
;
2915 return dwc3_check_event_buf(evt
);
2918 static int dwc3_gadget_get_irq(struct dwc3
*dwc
)
2920 struct platform_device
*dwc3_pdev
= to_platform_device(dwc
->dev
);
2923 irq
= platform_get_irq_byname(dwc3_pdev
, "peripheral");
2927 if (irq
== -EPROBE_DEFER
)
2930 irq
= platform_get_irq_byname(dwc3_pdev
, "dwc_usb3");
2934 if (irq
== -EPROBE_DEFER
)
2937 irq
= platform_get_irq(dwc3_pdev
, 0);
2941 if (irq
!= -EPROBE_DEFER
)
2942 dev_err(dwc
->dev
, "missing peripheral IRQ\n");
2952 * dwc3_gadget_init - Initializes gadget related registers
2953 * @dwc: pointer to our controller context structure
2955 * Returns 0 on success otherwise negative errno.
2957 int dwc3_gadget_init(struct dwc3
*dwc
)
2962 irq
= dwc3_gadget_get_irq(dwc
);
2968 dwc
->irq_gadget
= irq
;
2970 dwc
->ctrl_req
= dma_alloc_coherent(dwc
->dev
, sizeof(*dwc
->ctrl_req
),
2971 &dwc
->ctrl_req_addr
, GFP_KERNEL
);
2972 if (!dwc
->ctrl_req
) {
2973 dev_err(dwc
->dev
, "failed to allocate ctrl request\n");
2978 dwc
->ep0_trb
= dma_alloc_coherent(dwc
->dev
, sizeof(*dwc
->ep0_trb
) * 2,
2979 &dwc
->ep0_trb_addr
, GFP_KERNEL
);
2980 if (!dwc
->ep0_trb
) {
2981 dev_err(dwc
->dev
, "failed to allocate ep0 trb\n");
2986 dwc
->setup_buf
= kzalloc(DWC3_EP0_BOUNCE_SIZE
, GFP_KERNEL
);
2987 if (!dwc
->setup_buf
) {
2992 dwc
->ep0_bounce
= dma_alloc_coherent(dwc
->dev
,
2993 DWC3_EP0_BOUNCE_SIZE
, &dwc
->ep0_bounce_addr
,
2995 if (!dwc
->ep0_bounce
) {
2996 dev_err(dwc
->dev
, "failed to allocate ep0 bounce buffer\n");
3001 dwc
->zlp_buf
= kzalloc(DWC3_ZLP_BUF_SIZE
, GFP_KERNEL
);
3002 if (!dwc
->zlp_buf
) {
3007 init_completion(&dwc
->ep0_in_setup
);
3009 dwc
->gadget
.ops
= &dwc3_gadget_ops
;
3010 dwc
->gadget
.speed
= USB_SPEED_UNKNOWN
;
3011 dwc
->gadget
.sg_supported
= true;
3012 dwc
->gadget
.name
= "dwc3-gadget";
3013 dwc
->gadget
.is_otg
= dwc
->dr_mode
== USB_DR_MODE_OTG
;
3016 * FIXME We might be setting max_speed to <SUPER, however versions
3017 * <2.20a of dwc3 have an issue with metastability (documented
3018 * elsewhere in this driver) which tells us we can't set max speed to
3019 * anything lower than SUPER.
3021 * Because gadget.max_speed is only used by composite.c and function
3022 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3023 * to happen so we avoid sending SuperSpeed Capability descriptor
3024 * together with our BOS descriptor as that could confuse host into
3025 * thinking we can handle super speed.
3027 * Note that, in fact, we won't even support GetBOS requests when speed
3028 * is less than super speed because we don't have means, yet, to tell
3029 * composite.c that we are USB 2.0 + LPM ECN.
3031 if (dwc
->revision
< DWC3_REVISION_220A
)
3032 dev_info(dwc
->dev
, "changing max_speed on rev %08x\n",
3035 dwc
->gadget
.max_speed
= dwc
->maximum_speed
;
3038 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
3041 dwc
->gadget
.quirk_ep_out_aligned_size
= true;
3044 * REVISIT: Here we should clear all pending IRQs to be
3045 * sure we're starting from a well known location.
3048 ret
= dwc3_gadget_init_endpoints(dwc
);
3052 ret
= usb_add_gadget_udc(dwc
->dev
, &dwc
->gadget
);
3054 dev_err(dwc
->dev
, "failed to register udc\n");
3061 kfree(dwc
->zlp_buf
);
3064 dwc3_gadget_free_endpoints(dwc
);
3065 dma_free_coherent(dwc
->dev
, DWC3_EP0_BOUNCE_SIZE
,
3066 dwc
->ep0_bounce
, dwc
->ep0_bounce_addr
);
3069 kfree(dwc
->setup_buf
);
3072 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ep0_trb
) * 2,
3073 dwc
->ep0_trb
, dwc
->ep0_trb_addr
);
3076 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ctrl_req
),
3077 dwc
->ctrl_req
, dwc
->ctrl_req_addr
);
3083 /* -------------------------------------------------------------------------- */
3085 void dwc3_gadget_exit(struct dwc3
*dwc
)
3087 usb_del_gadget_udc(&dwc
->gadget
);
3089 dwc3_gadget_free_endpoints(dwc
);
3091 dma_free_coherent(dwc
->dev
, DWC3_EP0_BOUNCE_SIZE
,
3092 dwc
->ep0_bounce
, dwc
->ep0_bounce_addr
);
3094 kfree(dwc
->setup_buf
);
3095 kfree(dwc
->zlp_buf
);
3097 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ep0_trb
) * 2,
3098 dwc
->ep0_trb
, dwc
->ep0_trb_addr
);
3100 dma_free_coherent(dwc
->dev
, sizeof(*dwc
->ctrl_req
),
3101 dwc
->ctrl_req
, dwc
->ctrl_req_addr
);
3104 int dwc3_gadget_suspend(struct dwc3
*dwc
)
3108 if (!dwc
->gadget_driver
)
3111 ret
= dwc3_gadget_run_stop(dwc
, false, false);
3115 dwc3_disconnect_gadget(dwc
);
3116 __dwc3_gadget_stop(dwc
);
3121 int dwc3_gadget_resume(struct dwc3
*dwc
)
3125 if (!dwc
->gadget_driver
)
3128 ret
= __dwc3_gadget_start(dwc
);
3132 ret
= dwc3_gadget_run_stop(dwc
, true, false);
3139 __dwc3_gadget_stop(dwc
);
3145 void dwc3_gadget_process_pending_events(struct dwc3
*dwc
)
3147 if (dwc
->pending_events
) {
3148 dwc3_interrupt(dwc
->irq_gadget
, dwc
->ev_buf
);
3149 dwc
->pending_events
= false;
3150 enable_irq(dwc
->irq_gadget
);