2 * linux/drivers/usb/gadget/pxa2xx_udc.c
3 * Intel PXA25x and IXP4xx on-chip full speed USB device controllers
5 * Copyright (C) 2002 Intrinsyc, Inc. (Frank Becker)
6 * Copyright (C) 2003 Robert Schwebel, Pengutronix
7 * Copyright (C) 2003 Benedikt Spranger, Pengutronix
8 * Copyright (C) 2003 David Brownell
9 * Copyright (C) 2003 Joshua Wise
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 // #define VERBOSE DBG_VERBOSE
30 #include <linux/config.h>
31 #include <linux/module.h>
32 #include <linux/kernel.h>
33 #include <linux/ioport.h>
34 #include <linux/types.h>
35 #include <linux/errno.h>
36 #include <linux/delay.h>
37 #include <linux/sched.h>
38 #include <linux/slab.h>
39 #include <linux/init.h>
40 #include <linux/timer.h>
41 #include <linux/list.h>
42 #include <linux/interrupt.h>
43 #include <linux/proc_fs.h>
45 #include <linux/platform_device.h>
46 #include <linux/dma-mapping.h>
48 #include <asm/byteorder.h>
52 #include <asm/system.h>
53 #include <asm/mach-types.h>
54 #include <asm/unaligned.h>
55 #include <asm/hardware.h>
56 #include <asm/arch/pxa-regs.h>
58 #include <linux/usb_ch9.h>
59 #include <linux/usb_gadget.h>
61 #include <asm/arch/udc.h>
65 * This driver handles the USB Device Controller (UDC) in Intel's PXA 25x
66 * series processors. The UDC for the IXP 4xx series is very similar.
67 * There are fifteen endpoints, in addition to ep0.
69 * Such controller drivers work with a gadget driver. The gadget driver
70 * returns descriptors, implements configuration and data protocols used
71 * by the host to interact with this device, and allocates endpoints to
72 * the different protocol interfaces. The controller driver virtualizes
73 * usb hardware so that the gadget drivers will be more portable.
75 * This UDC hardware wants to implement a bit too much USB protocol, so
76 * it constrains the sorts of USB configuration change events that work.
77 * The errata for these chips are misleading; some "fixed" bugs from
78 * pxa250 a0/a1 b0/b1/b2 sure act like they're still there.
81 #define DRIVER_VERSION "4-May-2005"
82 #define DRIVER_DESC "PXA 25x USB Device Controller driver"
85 static const char driver_name
[] = "pxa2xx_udc";
87 static const char ep0name
[] = "ep0";
91 // #define USE_OUT_DMA
92 // #define DISABLE_TEST_MODE
94 #ifdef CONFIG_ARCH_IXP4XX
97 /* cpu-specific register addresses are compiled in to this code */
98 #ifdef CONFIG_ARCH_PXA
99 #error "Can't configure both IXP and PXA"
104 #include "pxa2xx_udc.h"
108 static int use_dma
= 1;
109 module_param(use_dma
, bool, 0);
110 MODULE_PARM_DESC (use_dma
, "true to use dma");
112 static void dma_nodesc_handler (int dmach
, void *_ep
, struct pt_regs
*r
);
113 static void kick_dma(struct pxa2xx_ep
*ep
, struct pxa2xx_request
*req
);
116 #define DMASTR " (dma support)"
118 #define DMASTR " (dma in)"
122 #define DMASTR " (pio only)"
126 #ifdef CONFIG_USB_PXA2XX_SMALL
127 #define SIZE_STR " (small)"
132 #ifdef DISABLE_TEST_MODE
133 /* (mode == 0) == no undocumented chip tweaks
134 * (mode & 1) == double buffer bulk IN
135 * (mode & 2) == double buffer bulk OUT
136 * ... so mode = 3 (or 7, 15, etc) does it for both
138 static ushort fifo_mode
= 0;
139 module_param(fifo_mode
, ushort
, 0);
140 MODULE_PARM_DESC (fifo_mode
, "pxa2xx udc fifo mode");
143 /* ---------------------------------------------------------------------------
144 * endpoint related parts of the api to the usb controller hardware,
145 * used by gadget driver; and the inner talker-to-hardware core.
146 * ---------------------------------------------------------------------------
149 static void pxa2xx_ep_fifo_flush (struct usb_ep
*ep
);
150 static void nuke (struct pxa2xx_ep
*, int status
);
152 static void pio_irq_enable(int bEndpointAddress
)
154 bEndpointAddress
&= 0xf;
155 if (bEndpointAddress
< 8)
156 UICR0
&= ~(1 << bEndpointAddress
);
158 bEndpointAddress
-= 8;
159 UICR1
&= ~(1 << bEndpointAddress
);
163 static void pio_irq_disable(int bEndpointAddress
)
165 bEndpointAddress
&= 0xf;
166 if (bEndpointAddress
< 8)
167 UICR0
|= 1 << bEndpointAddress
;
169 bEndpointAddress
-= 8;
170 UICR1
|= 1 << bEndpointAddress
;
174 /* The UDCCR reg contains mask and interrupt status bits,
175 * so using '|=' isn't safe as it may ack an interrupt.
177 #define UDCCR_MASK_BITS (UDCCR_REM | UDCCR_SRM | UDCCR_UDE)
179 static inline void udc_set_mask_UDCCR(int mask
)
181 UDCCR
= (UDCCR
& UDCCR_MASK_BITS
) | (mask
& UDCCR_MASK_BITS
);
184 static inline void udc_clear_mask_UDCCR(int mask
)
186 UDCCR
= (UDCCR
& UDCCR_MASK_BITS
) & ~(mask
& UDCCR_MASK_BITS
);
189 static inline void udc_ack_int_UDCCR(int mask
)
191 /* udccr contains the bits we dont want to change */
192 __u32 udccr
= UDCCR
& UDCCR_MASK_BITS
;
194 UDCCR
= udccr
| (mask
& ~UDCCR_MASK_BITS
);
198 * endpoint enable/disable
200 * we need to verify the descriptors used to enable endpoints. since pxa2xx
201 * endpoint configurations are fixed, and are pretty much always enabled,
202 * there's not a lot to manage here.
204 * because pxa2xx can't selectively initialize bulk (or interrupt) endpoints,
205 * (resetting endpoint halt and toggle), SET_INTERFACE is unusable except
206 * for a single interface (with only the default altsetting) and for gadget
207 * drivers that don't halt endpoints (not reset by set_interface). that also
208 * means that if you use ISO, you must violate the USB spec rule that all
209 * iso endpoints must be in non-default altsettings.
211 static int pxa2xx_ep_enable (struct usb_ep
*_ep
,
212 const struct usb_endpoint_descriptor
*desc
)
214 struct pxa2xx_ep
*ep
;
215 struct pxa2xx_udc
*dev
;
217 ep
= container_of (_ep
, struct pxa2xx_ep
, ep
);
218 if (!_ep
|| !desc
|| ep
->desc
|| _ep
->name
== ep0name
219 || desc
->bDescriptorType
!= USB_DT_ENDPOINT
220 || ep
->bEndpointAddress
!= desc
->bEndpointAddress
221 || ep
->fifo_size
< le16_to_cpu
222 (desc
->wMaxPacketSize
)) {
223 DMSG("%s, bad ep or descriptor\n", __FUNCTION__
);
227 /* xfer types must match, except that interrupt ~= bulk */
228 if (ep
->bmAttributes
!= desc
->bmAttributes
229 && ep
->bmAttributes
!= USB_ENDPOINT_XFER_BULK
230 && desc
->bmAttributes
!= USB_ENDPOINT_XFER_INT
) {
231 DMSG("%s, %s type mismatch\n", __FUNCTION__
, _ep
->name
);
235 /* hardware _could_ do smaller, but driver doesn't */
236 if ((desc
->bmAttributes
== USB_ENDPOINT_XFER_BULK
237 && le16_to_cpu (desc
->wMaxPacketSize
)
239 || !desc
->wMaxPacketSize
) {
240 DMSG("%s, bad %s maxpacket\n", __FUNCTION__
, _ep
->name
);
245 if (!dev
->driver
|| dev
->gadget
.speed
== USB_SPEED_UNKNOWN
) {
246 DMSG("%s, bogus device state\n", __FUNCTION__
);
253 ep
->pio_irqs
= ep
->dma_irqs
= 0;
254 ep
->ep
.maxpacket
= le16_to_cpu (desc
->wMaxPacketSize
);
256 /* flush fifo (mostly for OUT buffers) */
257 pxa2xx_ep_fifo_flush (_ep
);
259 /* ... reset halt state too, if we could ... */
262 /* for (some) bulk and ISO endpoints, try to get a DMA channel and
263 * bind it to the endpoint. otherwise use PIO.
265 switch (ep
->bmAttributes
) {
266 case USB_ENDPOINT_XFER_ISOC
:
267 if (le16_to_cpu(desc
->wMaxPacketSize
) % 32)
270 case USB_ENDPOINT_XFER_BULK
:
271 if (!use_dma
|| !ep
->reg_drcmr
)
273 ep
->dma
= pxa_request_dma ((char *)_ep
->name
,
274 (le16_to_cpu (desc
->wMaxPacketSize
) > 64)
275 ? DMA_PRIO_MEDIUM
/* some iso */
277 dma_nodesc_handler
, ep
);
279 *ep
->reg_drcmr
= DRCMR_MAPVLD
| ep
->dma
;
280 DMSG("%s using dma%d\n", _ep
->name
, ep
->dma
);
285 DBG(DBG_VERBOSE
, "enabled %s\n", _ep
->name
);
289 static int pxa2xx_ep_disable (struct usb_ep
*_ep
)
291 struct pxa2xx_ep
*ep
;
294 ep
= container_of (_ep
, struct pxa2xx_ep
, ep
);
295 if (!_ep
|| !ep
->desc
) {
296 DMSG("%s, %s not enabled\n", __FUNCTION__
,
297 _ep
? ep
->ep
.name
: NULL
);
300 local_irq_save(flags
);
302 nuke (ep
, -ESHUTDOWN
);
307 pxa_free_dma (ep
->dma
);
312 /* flush fifo (mostly for IN buffers) */
313 pxa2xx_ep_fifo_flush (_ep
);
318 local_irq_restore(flags
);
319 DBG(DBG_VERBOSE
, "%s disabled\n", _ep
->name
);
323 /*-------------------------------------------------------------------------*/
325 /* for the pxa2xx, these can just wrap kmalloc/kfree. gadget drivers
326 * must still pass correctly initialized endpoints, since other controller
327 * drivers may care about how it's currently set up (dma issues etc).
331 * pxa2xx_ep_alloc_request - allocate a request data structure
333 static struct usb_request
*
334 pxa2xx_ep_alloc_request (struct usb_ep
*_ep
, gfp_t gfp_flags
)
336 struct pxa2xx_request
*req
;
338 req
= kmalloc (sizeof *req
, gfp_flags
);
342 memset (req
, 0, sizeof *req
);
343 INIT_LIST_HEAD (&req
->queue
);
349 * pxa2xx_ep_free_request - deallocate a request data structure
352 pxa2xx_ep_free_request (struct usb_ep
*_ep
, struct usb_request
*_req
)
354 struct pxa2xx_request
*req
;
356 req
= container_of (_req
, struct pxa2xx_request
, req
);
357 WARN_ON (!list_empty (&req
->queue
));
362 /* PXA cache needs flushing with DMA I/O (it's dma-incoherent), but there's
363 * no device-affinity and the heap works perfectly well for i/o buffers.
364 * It wastes much less memory than dma_alloc_coherent() would, and even
365 * prevents cacheline (32 bytes wide) sharing problems.
368 pxa2xx_ep_alloc_buffer(struct usb_ep
*_ep
, unsigned bytes
,
369 dma_addr_t
*dma
, gfp_t gfp_flags
)
373 retval
= kmalloc (bytes
, gfp_flags
& ~(__GFP_DMA
|__GFP_HIGHMEM
));
376 *dma
= virt_to_bus (retval
);
378 *dma
= (dma_addr_t
)~0;
384 pxa2xx_ep_free_buffer(struct usb_ep
*_ep
, void *buf
, dma_addr_t dma
,
390 /*-------------------------------------------------------------------------*/
393 * done - retire a request; caller blocked irqs
395 static void done(struct pxa2xx_ep
*ep
, struct pxa2xx_request
*req
, int status
)
397 unsigned stopped
= ep
->stopped
;
399 list_del_init(&req
->queue
);
401 if (likely (req
->req
.status
== -EINPROGRESS
))
402 req
->req
.status
= status
;
404 status
= req
->req
.status
;
406 if (status
&& status
!= -ESHUTDOWN
)
407 DBG(DBG_VERBOSE
, "complete %s req %p stat %d len %u/%u\n",
408 ep
->ep
.name
, &req
->req
, status
,
409 req
->req
.actual
, req
->req
.length
);
411 /* don't modify queue heads during completion callback */
413 req
->req
.complete(&ep
->ep
, &req
->req
);
414 ep
->stopped
= stopped
;
418 static inline void ep0_idle (struct pxa2xx_udc
*dev
)
420 dev
->ep0state
= EP0_IDLE
;
424 write_packet(volatile u32
*uddr
, struct pxa2xx_request
*req
, unsigned max
)
427 unsigned length
, count
;
429 buf
= req
->req
.buf
+ req
->req
.actual
;
432 /* how big will this packet be? */
433 length
= min(req
->req
.length
- req
->req
.actual
, max
);
434 req
->req
.actual
+= length
;
437 while (likely(count
--))
444 * write to an IN endpoint fifo, as many packets as possible.
445 * irqs will use this to write the rest later.
446 * caller guarantees at least one packet buffer is ready (or a zlp).
449 write_fifo (struct pxa2xx_ep
*ep
, struct pxa2xx_request
*req
)
453 max
= le16_to_cpu(ep
->desc
->wMaxPacketSize
);
456 int is_last
, is_short
;
458 count
= write_packet(ep
->reg_uddr
, req
, max
);
460 /* last packet is usually short (or a zlp) */
461 if (unlikely (count
!= max
))
462 is_last
= is_short
= 1;
464 if (likely(req
->req
.length
!= req
->req
.actual
)
469 /* interrupt/iso maxpacket may not fill the fifo */
470 is_short
= unlikely (max
< ep
->fifo_size
);
473 DBG(DBG_VERY_NOISY
, "wrote %s %d bytes%s%s %d left %p\n",
475 is_last
? "/L" : "", is_short
? "/S" : "",
476 req
->req
.length
- req
->req
.actual
, req
);
478 /* let loose that packet. maybe try writing another one,
479 * double buffering might work. TSP, TPC, and TFS
480 * bit values are the same for all normal IN endpoints.
482 *ep
->reg_udccs
= UDCCS_BI_TPC
;
484 *ep
->reg_udccs
= UDCCS_BI_TSP
;
486 /* requests complete when all IN data is in the FIFO */
489 if (list_empty(&ep
->queue
) || unlikely(ep
->dma
>= 0)) {
490 pio_irq_disable (ep
->bEndpointAddress
);
492 /* unaligned data and zlps couldn't use dma */
493 if (unlikely(!list_empty(&ep
->queue
))) {
494 req
= list_entry(ep
->queue
.next
,
495 struct pxa2xx_request
, queue
);
504 // TODO experiment: how robust can fifo mode tweaking be?
505 // double buffering is off in the default fifo mode, which
506 // prevents TFS from being set here.
508 } while (*ep
->reg_udccs
& UDCCS_BI_TFS
);
512 /* caller asserts req->pending (ep0 irq status nyet cleared); starts
513 * ep0 data stage. these chips want very simple state transitions.
516 void ep0start(struct pxa2xx_udc
*dev
, u32 flags
, const char *tag
)
518 UDCCS0
= flags
|UDCCS0_SA
|UDCCS0_OPR
;
520 dev
->req_pending
= 0;
521 DBG(DBG_VERY_NOISY
, "%s %s, %02x/%02x\n",
522 __FUNCTION__
, tag
, UDCCS0
, flags
);
526 write_ep0_fifo (struct pxa2xx_ep
*ep
, struct pxa2xx_request
*req
)
531 count
= write_packet(&UDDR0
, req
, EP0_FIFO_SIZE
);
532 ep
->dev
->stats
.write
.bytes
+= count
;
534 /* last packet "must be" short (or a zlp) */
535 is_short
= (count
!= EP0_FIFO_SIZE
);
537 DBG(DBG_VERY_NOISY
, "ep0in %d bytes %d left %p\n", count
,
538 req
->req
.length
- req
->req
.actual
, req
);
540 if (unlikely (is_short
)) {
541 if (ep
->dev
->req_pending
)
542 ep0start(ep
->dev
, UDCCS0_IPR
, "short IN");
546 count
= req
->req
.length
;
550 /* This seems to get rid of lost status irqs in some cases:
551 * host responds quickly, or next request involves config
552 * change automagic, or should have been hidden, or ...
554 * FIXME get rid of all udelays possible...
556 if (count
>= EP0_FIFO_SIZE
) {
559 if ((UDCCS0
& UDCCS0_OPR
) != 0) {
560 /* clear OPR, generate ack */
569 } else if (ep
->dev
->req_pending
)
570 ep0start(ep
->dev
, 0, "IN");
576 * read_fifo - unload packet(s) from the fifo we use for usb OUT
577 * transfers and put them into the request. caller should have made
578 * sure there's at least one packet ready.
580 * returns true if the request completed because of short packet or the
581 * request buffer having filled (and maybe overran till end-of-packet).
584 read_fifo (struct pxa2xx_ep
*ep
, struct pxa2xx_request
*req
)
589 unsigned bufferspace
, count
, is_short
;
591 /* make sure there's a packet in the FIFO.
592 * UDCCS_{BO,IO}_RPC are all the same bit value.
593 * UDCCS_{BO,IO}_RNE are all the same bit value.
595 udccs
= *ep
->reg_udccs
;
596 if (unlikely ((udccs
& UDCCS_BO_RPC
) == 0))
598 buf
= req
->req
.buf
+ req
->req
.actual
;
600 bufferspace
= req
->req
.length
- req
->req
.actual
;
602 /* read all bytes from this packet */
603 if (likely (udccs
& UDCCS_BO_RNE
)) {
604 count
= 1 + (0x0ff & *ep
->reg_ubcr
);
605 req
->req
.actual
+= min (count
, bufferspace
);
608 is_short
= (count
< ep
->ep
.maxpacket
);
609 DBG(DBG_VERY_NOISY
, "read %s %02x, %d bytes%s req %p %d/%d\n",
610 ep
->ep
.name
, udccs
, count
,
611 is_short
? "/S" : "",
612 req
, req
->req
.actual
, req
->req
.length
);
613 while (likely (count
-- != 0)) {
614 u8 byte
= (u8
) *ep
->reg_uddr
;
616 if (unlikely (bufferspace
== 0)) {
617 /* this happens when the driver's buffer
618 * is smaller than what the host sent.
619 * discard the extra data.
621 if (req
->req
.status
!= -EOVERFLOW
)
622 DMSG("%s overflow %d\n",
624 req
->req
.status
= -EOVERFLOW
;
630 *ep
->reg_udccs
= UDCCS_BO_RPC
;
631 /* RPC/RSP/RNE could now reflect the other packet buffer */
633 /* iso is one request per packet */
634 if (ep
->bmAttributes
== USB_ENDPOINT_XFER_ISOC
) {
635 if (udccs
& UDCCS_IO_ROF
)
636 req
->req
.status
= -EHOSTUNREACH
;
637 /* more like "is_done" */
642 if (is_short
|| req
->req
.actual
== req
->req
.length
) {
644 if (list_empty(&ep
->queue
))
645 pio_irq_disable (ep
->bEndpointAddress
);
649 /* finished that packet. the next one may be waiting... */
655 * special ep0 version of the above. no UBCR0 or double buffering; status
656 * handshaking is magic. most device protocols don't need control-OUT.
657 * CDC vendor commands (and RNDIS), mass storage CB/CBI, and some other
658 * protocols do use them.
661 read_ep0_fifo (struct pxa2xx_ep
*ep
, struct pxa2xx_request
*req
)
664 unsigned bufferspace
;
666 buf
= req
->req
.buf
+ req
->req
.actual
;
667 bufferspace
= req
->req
.length
- req
->req
.actual
;
669 while (UDCCS0
& UDCCS0_RNE
) {
672 if (unlikely (bufferspace
== 0)) {
673 /* this happens when the driver's buffer
674 * is smaller than what the host sent.
675 * discard the extra data.
677 if (req
->req
.status
!= -EOVERFLOW
)
678 DMSG("%s overflow\n", ep
->ep
.name
);
679 req
->req
.status
= -EOVERFLOW
;
687 UDCCS0
= UDCCS0_OPR
| UDCCS0_IPR
;
690 if (req
->req
.actual
>= req
->req
.length
)
693 /* finished that packet. the next one may be waiting... */
699 #define MAX_IN_DMA ((DCMD_LENGTH + 1) - BULK_FIFO_SIZE)
702 start_dma_nodesc(struct pxa2xx_ep
*ep
, struct pxa2xx_request
*req
, int is_in
)
704 u32 dcmd
= req
->req
.length
;
705 u32 buf
= req
->req
.dma
;
706 u32 fifo
= io_v2p ((u32
)ep
->reg_uddr
);
708 /* caller guarantees there's a packet or more remaining
709 * - IN may end with a short packet (TSP set separately),
710 * - OUT is always full length
712 buf
+= req
->req
.actual
;
713 dcmd
-= req
->req
.actual
;
716 /* no-descriptor mode can be simple for bulk-in, iso-in, iso-out */
717 DCSR(ep
->dma
) = DCSR_NODESC
;
719 DSADR(ep
->dma
) = buf
;
720 DTADR(ep
->dma
) = fifo
;
721 if (dcmd
> MAX_IN_DMA
)
724 ep
->dma_fixup
= (dcmd
% ep
->ep
.maxpacket
) != 0;
725 dcmd
|= DCMD_BURST32
| DCMD_WIDTH1
726 | DCMD_FLOWTRG
| DCMD_INCSRCADDR
;
729 DSADR(ep
->dma
) = fifo
;
730 DTADR(ep
->dma
) = buf
;
731 if (ep
->bmAttributes
!= USB_ENDPOINT_XFER_ISOC
)
732 dcmd
= ep
->ep
.maxpacket
;
733 dcmd
|= DCMD_BURST32
| DCMD_WIDTH1
734 | DCMD_FLOWSRC
| DCMD_INCTRGADDR
;
737 DCMD(ep
->dma
) = dcmd
;
738 DCSR(ep
->dma
) = DCSR_RUN
| DCSR_NODESC
740 ? DCSR_STOPIRQEN
/* use dma_nodesc_handler() */
741 : 0); /* use handle_ep() */
744 static void kick_dma(struct pxa2xx_ep
*ep
, struct pxa2xx_request
*req
)
746 int is_in
= ep
->bEndpointAddress
& USB_DIR_IN
;
749 /* unaligned tx buffers and zlps only work with PIO */
750 if ((req
->req
.dma
& 0x0f) != 0
751 || unlikely((req
->req
.length
- req
->req
.actual
)
753 pio_irq_enable(ep
->bEndpointAddress
);
754 if ((*ep
->reg_udccs
& UDCCS_BI_TFS
) != 0)
755 (void) write_fifo(ep
, req
);
757 start_dma_nodesc(ep
, req
, USB_DIR_IN
);
760 if ((req
->req
.length
- req
->req
.actual
) < ep
->ep
.maxpacket
) {
761 DMSG("%s short dma read...\n", ep
->ep
.name
);
762 /* we're always set up for pio out */
765 *ep
->reg_udccs
= UDCCS_BO_DME
766 | (*ep
->reg_udccs
& UDCCS_BO_FST
);
767 start_dma_nodesc(ep
, req
, USB_DIR_OUT
);
772 static void cancel_dma(struct pxa2xx_ep
*ep
)
774 struct pxa2xx_request
*req
;
777 if (DCSR(ep
->dma
) == 0 || list_empty(&ep
->queue
))
781 while ((DCSR(ep
->dma
) & DCSR_STOPSTATE
) == 0)
784 req
= list_entry(ep
->queue
.next
, struct pxa2xx_request
, queue
);
785 tmp
= DCMD(ep
->dma
) & DCMD_LENGTH
;
786 req
->req
.actual
= req
->req
.length
- (tmp
& DCMD_LENGTH
);
788 /* the last tx packet may be incomplete, so flush the fifo.
789 * FIXME correct req.actual if we can
791 if (ep
->bEndpointAddress
& USB_DIR_IN
)
792 *ep
->reg_udccs
= UDCCS_BI_FTF
;
795 /* dma channel stopped ... normal tx end (IN), or on error (IN/OUT) */
796 static void dma_nodesc_handler(int dmach
, void *_ep
, struct pt_regs
*r
)
798 struct pxa2xx_ep
*ep
= _ep
;
799 struct pxa2xx_request
*req
;
804 req
= list_entry(ep
->queue
.next
, struct pxa2xx_request
, queue
);
807 ep
->dev
->stats
.irqs
++;
808 HEX_DISPLAY(ep
->dev
->stats
.irqs
);
813 if ((tmp
& DCSR_STOPSTATE
) == 0
814 || (DDADR(ep
->dma
) & DDADR_STOP
) != 0) {
815 DBG(DBG_VERBOSE
, "%s, dcsr %08x ddadr %08x\n",
816 ep
->ep
.name
, DCSR(ep
->dma
), DDADR(ep
->dma
));
819 DCSR(ep
->dma
) = 0; /* clear DCSR_STOPSTATE */
821 /* update transfer status */
822 completed
= tmp
& DCSR_BUSERR
;
823 if (ep
->bEndpointAddress
& USB_DIR_IN
)
824 tmp
= DSADR(ep
->dma
);
826 tmp
= DTADR(ep
->dma
);
827 req
->req
.actual
= tmp
- req
->req
.dma
;
829 /* FIXME seems we sometimes see partial transfers... */
831 if (unlikely(completed
!= 0))
832 req
->req
.status
= -EIO
;
833 else if (req
->req
.actual
) {
834 /* these registers have zeroes in low bits; they miscount
835 * some (end-of-transfer) short packets: tx 14 as tx 12
838 req
->req
.actual
= min(req
->req
.actual
+ 3,
841 tmp
= (req
->req
.length
- req
->req
.actual
);
842 completed
= (tmp
== 0);
843 if (completed
&& (ep
->bEndpointAddress
& USB_DIR_IN
)) {
845 /* maybe validate final short packet ... */
846 if ((req
->req
.actual
% ep
->ep
.maxpacket
) != 0)
847 *ep
->reg_udccs
= UDCCS_BI_TSP
/*|UDCCS_BI_TPC*/;
849 /* ... or zlp, using pio fallback */
850 else if (ep
->bmAttributes
== USB_ENDPOINT_XFER_BULK
852 DMSG("%s zlp terminate ...\n", ep
->ep
.name
);
858 if (likely(completed
)) {
861 /* maybe re-activate after completion */
862 if (ep
->stopped
|| list_empty(&ep
->queue
))
864 req
= list_entry(ep
->queue
.next
, struct pxa2xx_request
, queue
);
873 /*-------------------------------------------------------------------------*/
876 pxa2xx_ep_queue(struct usb_ep
*_ep
, struct usb_request
*_req
, gfp_t gfp_flags
)
878 struct pxa2xx_request
*req
;
879 struct pxa2xx_ep
*ep
;
880 struct pxa2xx_udc
*dev
;
883 req
= container_of(_req
, struct pxa2xx_request
, req
);
884 if (unlikely (!_req
|| !_req
->complete
|| !_req
->buf
885 || !list_empty(&req
->queue
))) {
886 DMSG("%s, bad params\n", __FUNCTION__
);
890 ep
= container_of(_ep
, struct pxa2xx_ep
, ep
);
891 if (unlikely (!_ep
|| (!ep
->desc
&& ep
->ep
.name
!= ep0name
))) {
892 DMSG("%s, bad ep\n", __FUNCTION__
);
897 if (unlikely (!dev
->driver
898 || dev
->gadget
.speed
== USB_SPEED_UNKNOWN
)) {
899 DMSG("%s, bogus device state\n", __FUNCTION__
);
903 /* iso is always one packet per request, that's the only way
904 * we can report per-packet status. that also helps with dma.
906 if (unlikely (ep
->bmAttributes
== USB_ENDPOINT_XFER_ISOC
907 && req
->req
.length
> le16_to_cpu
908 (ep
->desc
->wMaxPacketSize
)))
912 // FIXME caller may already have done the dma mapping
914 _req
->dma
= dma_map_single(dev
->dev
,
915 _req
->buf
, _req
->length
,
916 ((ep
->bEndpointAddress
& USB_DIR_IN
) != 0)
922 DBG(DBG_NOISY
, "%s queue req %p, len %d buf %p\n",
923 _ep
->name
, _req
, _req
->length
, _req
->buf
);
925 local_irq_save(flags
);
927 _req
->status
= -EINPROGRESS
;
930 /* kickstart this i/o queue? */
931 if (list_empty(&ep
->queue
) && !ep
->stopped
) {
932 if (ep
->desc
== 0 /* ep0 */) {
933 unsigned length
= _req
->length
;
935 switch (dev
->ep0state
) {
936 case EP0_IN_DATA_PHASE
:
937 dev
->stats
.write
.ops
++;
938 if (write_ep0_fifo(ep
, req
))
942 case EP0_OUT_DATA_PHASE
:
943 dev
->stats
.read
.ops
++;
945 if (dev
->req_config
) {
946 DBG(DBG_VERBOSE
, "ep0 config ack%s\n",
947 dev
->has_cfr
? "" : " raced");
949 UDCCFR
= UDCCFR_AREN
|UDCCFR_ACM
952 dev
->ep0state
= EP0_END_XFER
;
953 local_irq_restore (flags
);
956 if (dev
->req_pending
)
957 ep0start(dev
, UDCCS0_IPR
, "OUT");
958 if (length
== 0 || ((UDCCS0
& UDCCS0_RNE
) != 0
959 && read_ep0_fifo(ep
, req
))) {
967 DMSG("ep0 i/o, odd state %d\n", dev
->ep0state
);
968 local_irq_restore (flags
);
972 /* either start dma or prime pio pump */
973 } else if (ep
->dma
>= 0) {
976 /* can the FIFO can satisfy the request immediately? */
977 } else if ((ep
->bEndpointAddress
& USB_DIR_IN
) != 0) {
978 if ((*ep
->reg_udccs
& UDCCS_BI_TFS
) != 0
979 && write_fifo(ep
, req
))
981 } else if ((*ep
->reg_udccs
& UDCCS_BO_RFS
) != 0
982 && read_fifo(ep
, req
)) {
986 if (likely (req
&& ep
->desc
) && ep
->dma
< 0)
987 pio_irq_enable(ep
->bEndpointAddress
);
990 /* pio or dma irq handler advances the queue. */
991 if (likely (req
!= 0))
992 list_add_tail(&req
->queue
, &ep
->queue
);
993 local_irq_restore(flags
);
1000 * nuke - dequeue ALL requests
1002 static void nuke(struct pxa2xx_ep
*ep
, int status
)
1004 struct pxa2xx_request
*req
;
1006 /* called with irqs blocked */
1008 if (ep
->dma
>= 0 && !ep
->stopped
)
1011 while (!list_empty(&ep
->queue
)) {
1012 req
= list_entry(ep
->queue
.next
,
1013 struct pxa2xx_request
,
1015 done(ep
, req
, status
);
1018 pio_irq_disable (ep
->bEndpointAddress
);
1022 /* dequeue JUST ONE request */
1023 static int pxa2xx_ep_dequeue(struct usb_ep
*_ep
, struct usb_request
*_req
)
1025 struct pxa2xx_ep
*ep
;
1026 struct pxa2xx_request
*req
;
1027 unsigned long flags
;
1029 ep
= container_of(_ep
, struct pxa2xx_ep
, ep
);
1030 if (!_ep
|| ep
->ep
.name
== ep0name
)
1033 local_irq_save(flags
);
1035 /* make sure it's actually queued on this endpoint */
1036 list_for_each_entry (req
, &ep
->queue
, queue
) {
1037 if (&req
->req
== _req
)
1040 if (&req
->req
!= _req
) {
1041 local_irq_restore(flags
);
1046 if (ep
->dma
>= 0 && ep
->queue
.next
== &req
->queue
&& !ep
->stopped
) {
1048 done(ep
, req
, -ECONNRESET
);
1050 if (!list_empty(&ep
->queue
)) {
1051 req
= list_entry(ep
->queue
.next
,
1052 struct pxa2xx_request
, queue
);
1057 done(ep
, req
, -ECONNRESET
);
1059 local_irq_restore(flags
);
1063 /*-------------------------------------------------------------------------*/
1065 static int pxa2xx_ep_set_halt(struct usb_ep
*_ep
, int value
)
1067 struct pxa2xx_ep
*ep
;
1068 unsigned long flags
;
1070 ep
= container_of(_ep
, struct pxa2xx_ep
, ep
);
1072 || (!ep
->desc
&& ep
->ep
.name
!= ep0name
))
1073 || ep
->bmAttributes
== USB_ENDPOINT_XFER_ISOC
) {
1074 DMSG("%s, bad ep\n", __FUNCTION__
);
1078 /* this path (reset toggle+halt) is needed to implement
1079 * SET_INTERFACE on normal hardware. but it can't be
1080 * done from software on the PXA UDC, and the hardware
1081 * forgets to do it as part of SET_INTERFACE automagic.
1083 DMSG("only host can clear %s halt\n", _ep
->name
);
1087 local_irq_save(flags
);
1089 if ((ep
->bEndpointAddress
& USB_DIR_IN
) != 0
1090 && ((*ep
->reg_udccs
& UDCCS_BI_TFS
) == 0
1091 || !list_empty(&ep
->queue
))) {
1092 local_irq_restore(flags
);
1096 /* FST bit is the same for control, bulk in, bulk out, interrupt in */
1097 *ep
->reg_udccs
= UDCCS_BI_FST
|UDCCS_BI_FTF
;
1099 /* ep0 needs special care */
1101 start_watchdog(ep
->dev
);
1102 ep
->dev
->req_pending
= 0;
1103 ep
->dev
->ep0state
= EP0_STALL
;
1105 /* and bulk/intr endpoints like dropping stalls too */
1108 for (i
= 0; i
< 1000; i
+= 20) {
1109 if (*ep
->reg_udccs
& UDCCS_BI_SST
)
1114 local_irq_restore(flags
);
1116 DBG(DBG_VERBOSE
, "%s halt\n", _ep
->name
);
1120 static int pxa2xx_ep_fifo_status(struct usb_ep
*_ep
)
1122 struct pxa2xx_ep
*ep
;
1124 ep
= container_of(_ep
, struct pxa2xx_ep
, ep
);
1126 DMSG("%s, bad ep\n", __FUNCTION__
);
1129 /* pxa can't report unclaimed bytes from IN fifos */
1130 if ((ep
->bEndpointAddress
& USB_DIR_IN
) != 0)
1132 if (ep
->dev
->gadget
.speed
== USB_SPEED_UNKNOWN
1133 || (*ep
->reg_udccs
& UDCCS_BO_RFS
) == 0)
1136 return (*ep
->reg_ubcr
& 0xfff) + 1;
1139 static void pxa2xx_ep_fifo_flush(struct usb_ep
*_ep
)
1141 struct pxa2xx_ep
*ep
;
1143 ep
= container_of(_ep
, struct pxa2xx_ep
, ep
);
1144 if (!_ep
|| ep
->ep
.name
== ep0name
|| !list_empty(&ep
->queue
)) {
1145 DMSG("%s, bad ep\n", __FUNCTION__
);
1149 /* toggle and halt bits stay unchanged */
1151 /* for OUT, just read and discard the FIFO contents. */
1152 if ((ep
->bEndpointAddress
& USB_DIR_IN
) == 0) {
1153 while (((*ep
->reg_udccs
) & UDCCS_BO_RNE
) != 0)
1154 (void) *ep
->reg_uddr
;
1158 /* most IN status is the same, but ISO can't stall */
1159 *ep
->reg_udccs
= UDCCS_BI_TPC
|UDCCS_BI_FTF
|UDCCS_BI_TUR
1160 | (ep
->bmAttributes
== USB_ENDPOINT_XFER_ISOC
)
1165 static struct usb_ep_ops pxa2xx_ep_ops
= {
1166 .enable
= pxa2xx_ep_enable
,
1167 .disable
= pxa2xx_ep_disable
,
1169 .alloc_request
= pxa2xx_ep_alloc_request
,
1170 .free_request
= pxa2xx_ep_free_request
,
1172 .alloc_buffer
= pxa2xx_ep_alloc_buffer
,
1173 .free_buffer
= pxa2xx_ep_free_buffer
,
1175 .queue
= pxa2xx_ep_queue
,
1176 .dequeue
= pxa2xx_ep_dequeue
,
1178 .set_halt
= pxa2xx_ep_set_halt
,
1179 .fifo_status
= pxa2xx_ep_fifo_status
,
1180 .fifo_flush
= pxa2xx_ep_fifo_flush
,
1184 /* ---------------------------------------------------------------------------
1185 * device-scoped parts of the api to the usb controller hardware
1186 * ---------------------------------------------------------------------------
1189 static int pxa2xx_udc_get_frame(struct usb_gadget
*_gadget
)
1191 return ((UFNRH
& 0x07) << 8) | (UFNRL
& 0xff);
1194 static int pxa2xx_udc_wakeup(struct usb_gadget
*_gadget
)
1196 /* host may not have enabled remote wakeup */
1197 if ((UDCCS0
& UDCCS0_DRWF
) == 0)
1198 return -EHOSTUNREACH
;
1199 udc_set_mask_UDCCR(UDCCR_RSM
);
1203 static void stop_activity(struct pxa2xx_udc
*, struct usb_gadget_driver
*);
1204 static void udc_enable (struct pxa2xx_udc
*);
1205 static void udc_disable(struct pxa2xx_udc
*);
1207 /* We disable the UDC -- and its 48 MHz clock -- whenever it's not
1210 static int pullup(struct pxa2xx_udc
*udc
, int is_active
)
1212 is_active
= is_active
&& udc
->vbus
&& udc
->pullup
;
1213 DMSG("%s\n", is_active
? "active" : "inactive");
1217 if (udc
->gadget
.speed
!= USB_SPEED_UNKNOWN
) {
1218 DMSG("disconnect %s\n", udc
->driver
1219 ? udc
->driver
->driver
.name
1221 stop_activity(udc
, udc
->driver
);
1228 /* VBUS reporting logically comes from a transceiver */
1229 static int pxa2xx_udc_vbus_session(struct usb_gadget
*_gadget
, int is_active
)
1231 struct pxa2xx_udc
*udc
;
1233 udc
= container_of(_gadget
, struct pxa2xx_udc
, gadget
);
1234 udc
->vbus
= is_active
= (is_active
!= 0);
1235 DMSG("vbus %s\n", is_active
? "supplied" : "inactive");
1236 pullup(udc
, is_active
);
1240 /* drivers may have software control over D+ pullup */
1241 static int pxa2xx_udc_pullup(struct usb_gadget
*_gadget
, int is_active
)
1243 struct pxa2xx_udc
*udc
;
1245 udc
= container_of(_gadget
, struct pxa2xx_udc
, gadget
);
1247 /* not all boards support pullup control */
1248 if (!udc
->mach
->udc_command
)
1251 is_active
= (is_active
!= 0);
1252 udc
->pullup
= is_active
;
1253 pullup(udc
, is_active
);
1257 static const struct usb_gadget_ops pxa2xx_udc_ops
= {
1258 .get_frame
= pxa2xx_udc_get_frame
,
1259 .wakeup
= pxa2xx_udc_wakeup
,
1260 .vbus_session
= pxa2xx_udc_vbus_session
,
1261 .pullup
= pxa2xx_udc_pullup
,
1263 // .vbus_draw ... boards may consume current from VBUS, up to
1264 // 100-500mA based on config. the 500uA suspend ceiling means
1265 // that exclusively vbus-powered PXA designs violate USB specs.
1268 /*-------------------------------------------------------------------------*/
1270 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
1272 static const char proc_node_name
[] = "driver/udc";
1275 udc_proc_read(char *page
, char **start
, off_t off
, int count
,
1276 int *eof
, void *_dev
)
1279 struct pxa2xx_udc
*dev
= _dev
;
1281 unsigned size
= count
;
1282 unsigned long flags
;
1289 local_irq_save(flags
);
1291 /* basic device status */
1292 t
= scnprintf(next
, size
, DRIVER_DESC
"\n"
1293 "%s version: %s\nGadget driver: %s\nHost %s\n\n",
1294 driver_name
, DRIVER_VERSION SIZE_STR DMASTR
,
1295 dev
->driver
? dev
->driver
->driver
.name
: "(none)",
1296 is_vbus_present() ? "full speed" : "disconnected");
1300 /* registers for device and ep0 */
1301 t
= scnprintf(next
, size
,
1302 "uicr %02X.%02X, usir %02X.%02x, ufnr %02X.%02X\n",
1303 UICR1
, UICR0
, USIR1
, USIR0
, UFNRH
, UFNRL
);
1308 t
= scnprintf(next
, size
,
1309 "udccr %02X =%s%s%s%s%s%s%s%s\n", tmp
,
1310 (tmp
& UDCCR_REM
) ? " rem" : "",
1311 (tmp
& UDCCR_RSTIR
) ? " rstir" : "",
1312 (tmp
& UDCCR_SRM
) ? " srm" : "",
1313 (tmp
& UDCCR_SUSIR
) ? " susir" : "",
1314 (tmp
& UDCCR_RESIR
) ? " resir" : "",
1315 (tmp
& UDCCR_RSM
) ? " rsm" : "",
1316 (tmp
& UDCCR_UDA
) ? " uda" : "",
1317 (tmp
& UDCCR_UDE
) ? " ude" : "");
1322 t
= scnprintf(next
, size
,
1323 "udccs0 %02X =%s%s%s%s%s%s%s%s\n", tmp
,
1324 (tmp
& UDCCS0_SA
) ? " sa" : "",
1325 (tmp
& UDCCS0_RNE
) ? " rne" : "",
1326 (tmp
& UDCCS0_FST
) ? " fst" : "",
1327 (tmp
& UDCCS0_SST
) ? " sst" : "",
1328 (tmp
& UDCCS0_DRWF
) ? " dwrf" : "",
1329 (tmp
& UDCCS0_FTF
) ? " ftf" : "",
1330 (tmp
& UDCCS0_IPR
) ? " ipr" : "",
1331 (tmp
& UDCCS0_OPR
) ? " opr" : "");
1337 t
= scnprintf(next
, size
,
1338 "udccfr %02X =%s%s\n", tmp
,
1339 (tmp
& UDCCFR_AREN
) ? " aren" : "",
1340 (tmp
& UDCCFR_ACM
) ? " acm" : "");
1345 if (!is_vbus_present() || !dev
->driver
)
1348 t
= scnprintf(next
, size
, "ep0 IN %lu/%lu, OUT %lu/%lu\nirqs %lu\n\n",
1349 dev
->stats
.write
.bytes
, dev
->stats
.write
.ops
,
1350 dev
->stats
.read
.bytes
, dev
->stats
.read
.ops
,
1355 /* dump endpoint queues */
1356 for (i
= 0; i
< PXA_UDC_NUM_ENDPOINTS
; i
++) {
1357 struct pxa2xx_ep
*ep
= &dev
->ep
[i
];
1358 struct pxa2xx_request
*req
;
1362 const struct usb_endpoint_descriptor
*d
;
1367 tmp
= *dev
->ep
[i
].reg_udccs
;
1368 t
= scnprintf(next
, size
,
1369 "%s max %d %s udccs %02x irqs %lu/%lu\n",
1370 ep
->ep
.name
, le16_to_cpu (d
->wMaxPacketSize
),
1371 (ep
->dma
>= 0) ? "dma" : "pio", tmp
,
1372 ep
->pio_irqs
, ep
->dma_irqs
);
1373 /* TODO translate all five groups of udccs bits! */
1375 } else /* ep0 should only have one transfer queued */
1376 t
= scnprintf(next
, size
, "ep0 max 16 pio irqs %lu\n",
1378 if (t
<= 0 || t
> size
)
1383 if (list_empty(&ep
->queue
)) {
1384 t
= scnprintf(next
, size
, "\t(nothing queued)\n");
1385 if (t
<= 0 || t
> size
)
1391 list_for_each_entry(req
, &ep
->queue
, queue
) {
1393 if (ep
->dma
>= 0 && req
->queue
.prev
== &ep
->queue
)
1394 t
= scnprintf(next
, size
,
1395 "\treq %p len %d/%d "
1396 "buf %p (dma%d dcmd %08x)\n",
1397 &req
->req
, req
->req
.actual
,
1398 req
->req
.length
, req
->req
.buf
,
1399 ep
->dma
, DCMD(ep
->dma
)
1400 // low 13 bits == bytes-to-go
1404 t
= scnprintf(next
, size
,
1405 "\treq %p len %d/%d buf %p\n",
1406 &req
->req
, req
->req
.actual
,
1407 req
->req
.length
, req
->req
.buf
);
1408 if (t
<= 0 || t
> size
)
1416 local_irq_restore(flags
);
1418 return count
- size
;
1421 #define create_proc_files() \
1422 create_proc_read_entry(proc_node_name, 0, NULL, udc_proc_read, dev)
1423 #define remove_proc_files() \
1424 remove_proc_entry(proc_node_name, NULL)
1426 #else /* !CONFIG_USB_GADGET_DEBUG_FILES */
1428 #define create_proc_files() do {} while (0)
1429 #define remove_proc_files() do {} while (0)
1431 #endif /* CONFIG_USB_GADGET_DEBUG_FILES */
1433 /* "function" sysfs attribute */
1435 show_function (struct device
*_dev
, struct device_attribute
*attr
, char *buf
)
1437 struct pxa2xx_udc
*dev
= dev_get_drvdata (_dev
);
1440 || !dev
->driver
->function
1441 || strlen (dev
->driver
->function
) > PAGE_SIZE
)
1443 return scnprintf (buf
, PAGE_SIZE
, "%s\n", dev
->driver
->function
);
1445 static DEVICE_ATTR (function
, S_IRUGO
, show_function
, NULL
);
1447 /*-------------------------------------------------------------------------*/
1450 * udc_disable - disable USB device controller
1452 static void udc_disable(struct pxa2xx_udc
*dev
)
1454 /* block all irqs */
1455 udc_set_mask_UDCCR(UDCCR_SRM
|UDCCR_REM
);
1456 UICR0
= UICR1
= 0xff;
1459 /* if hardware supports it, disconnect from usb */
1462 udc_clear_mask_UDCCR(UDCCR_UDE
);
1464 #ifdef CONFIG_ARCH_PXA
1465 /* Disable clock for USB device */
1466 pxa_set_cken(CKEN11_USB
, 0);
1470 dev
->gadget
.speed
= USB_SPEED_UNKNOWN
;
1476 * udc_reinit - initialize software state
1478 static void udc_reinit(struct pxa2xx_udc
*dev
)
1482 /* device/ep0 records init */
1483 INIT_LIST_HEAD (&dev
->gadget
.ep_list
);
1484 INIT_LIST_HEAD (&dev
->gadget
.ep0
->ep_list
);
1485 dev
->ep0state
= EP0_IDLE
;
1487 /* basic endpoint records init */
1488 for (i
= 0; i
< PXA_UDC_NUM_ENDPOINTS
; i
++) {
1489 struct pxa2xx_ep
*ep
= &dev
->ep
[i
];
1492 list_add_tail (&ep
->ep
.ep_list
, &dev
->gadget
.ep_list
);
1496 INIT_LIST_HEAD (&ep
->queue
);
1497 ep
->pio_irqs
= ep
->dma_irqs
= 0;
1500 /* the rest was statically initialized, and is read-only */
1503 /* until it's enabled, this UDC should be completely invisible
1506 static void udc_enable (struct pxa2xx_udc
*dev
)
1508 udc_clear_mask_UDCCR(UDCCR_UDE
);
1510 #ifdef CONFIG_ARCH_PXA
1511 /* Enable clock for USB device */
1512 pxa_set_cken(CKEN11_USB
, 1);
1516 /* try to clear these bits before we enable the udc */
1517 udc_ack_int_UDCCR(UDCCR_SUSIR
|/*UDCCR_RSTIR|*/UDCCR_RESIR
);
1520 dev
->gadget
.speed
= USB_SPEED_UNKNOWN
;
1521 dev
->stats
.irqs
= 0;
1524 * sequence taken from chapter 12.5.10, PXA250 AppProcDevManual:
1526 * - if RESET is already in progress, ack interrupt
1527 * - unmask reset interrupt
1529 udc_set_mask_UDCCR(UDCCR_UDE
);
1530 if (!(UDCCR
& UDCCR_UDA
))
1531 udc_ack_int_UDCCR(UDCCR_RSTIR
);
1533 if (dev
->has_cfr
/* UDC_RES2 is defined */) {
1534 /* pxa255 (a0+) can avoid a set_config race that could
1535 * prevent gadget drivers from configuring correctly
1537 UDCCFR
= UDCCFR_ACM
| UDCCFR_MB1
;
1539 /* "USB test mode" for pxa250 errata 40-42 (stepping a0, a1)
1540 * which could result in missing packets and interrupts.
1541 * supposedly one bit per endpoint, controlling whether it
1542 * double buffers or not; ACM/AREN bits fit into the holes.
1543 * zero bits (like USIR0_IRx) disable double buffering.
1549 #ifdef DISABLE_TEST_MODE
1550 /* "test mode" seems to have become the default in later chip
1551 * revs, preventing double buffering (and invalidating docs).
1552 * this EXPERIMENT enables it for bulk endpoints by tweaking
1553 * undefined/reserved register bits (that other drivers clear).
1554 * Belcarra code comments noted this usage.
1556 if (fifo_mode
& 1) { /* IN endpoints */
1557 UDC_RES1
|= USIR0_IR1
|USIR0_IR6
;
1558 UDC_RES2
|= USIR1_IR11
;
1560 if (fifo_mode
& 2) { /* OUT endpoints */
1561 UDC_RES1
|= USIR0_IR2
|USIR0_IR7
;
1562 UDC_RES2
|= USIR1_IR12
;
1566 /* enable suspend/resume and reset irqs */
1567 udc_clear_mask_UDCCR(UDCCR_SRM
| UDCCR_REM
);
1569 /* enable ep0 irqs */
1570 UICR0
&= ~UICR0_IM0
;
1572 /* if hardware supports it, pullup D+ and wait for reset */
1577 /* when a driver is successfully registered, it will receive
1578 * control requests including set_configuration(), which enables
1579 * non-control requests. then usb traffic follows until a
1580 * disconnect is reported. then a host may connect again, or
1581 * the driver might get unbound.
1583 int usb_gadget_register_driver(struct usb_gadget_driver
*driver
)
1585 struct pxa2xx_udc
*dev
= the_controller
;
1589 || driver
->speed
!= USB_SPEED_FULL
1592 || !driver
->disconnect
1600 /* first hook up the driver ... */
1601 dev
->driver
= driver
;
1602 dev
->gadget
.dev
.driver
= &driver
->driver
;
1605 device_add (&dev
->gadget
.dev
);
1606 retval
= driver
->bind(&dev
->gadget
);
1608 DMSG("bind to driver %s --> error %d\n",
1609 driver
->driver
.name
, retval
);
1610 device_del (&dev
->gadget
.dev
);
1613 dev
->gadget
.dev
.driver
= NULL
;
1616 device_create_file(dev
->dev
, &dev_attr_function
);
1618 /* ... then enable host detection and ep0; and we're ready
1619 * for set_configuration as well as eventual disconnect.
1621 DMSG("registered gadget driver '%s'\n", driver
->driver
.name
);
1626 EXPORT_SYMBOL(usb_gadget_register_driver
);
1629 stop_activity(struct pxa2xx_udc
*dev
, struct usb_gadget_driver
*driver
)
1633 /* don't disconnect drivers more than once */
1634 if (dev
->gadget
.speed
== USB_SPEED_UNKNOWN
)
1636 dev
->gadget
.speed
= USB_SPEED_UNKNOWN
;
1638 /* prevent new request submissions, kill any outstanding requests */
1639 for (i
= 0; i
< PXA_UDC_NUM_ENDPOINTS
; i
++) {
1640 struct pxa2xx_ep
*ep
= &dev
->ep
[i
];
1643 nuke(ep
, -ESHUTDOWN
);
1645 del_timer_sync(&dev
->timer
);
1647 /* report disconnect; the driver is already quiesced */
1650 driver
->disconnect(&dev
->gadget
);
1652 /* re-init driver-visible data structures */
1656 int usb_gadget_unregister_driver(struct usb_gadget_driver
*driver
)
1658 struct pxa2xx_udc
*dev
= the_controller
;
1662 if (!driver
|| driver
!= dev
->driver
)
1665 local_irq_disable();
1667 stop_activity(dev
, driver
);
1670 driver
->unbind(&dev
->gadget
);
1673 device_del (&dev
->gadget
.dev
);
1674 device_remove_file(dev
->dev
, &dev_attr_function
);
1676 DMSG("unregistered gadget driver '%s'\n", driver
->driver
.name
);
1680 EXPORT_SYMBOL(usb_gadget_unregister_driver
);
1683 /*-------------------------------------------------------------------------*/
1685 #ifdef CONFIG_ARCH_LUBBOCK
1687 /* Lubbock has separate connect and disconnect irqs. More typical designs
1688 * use one GPIO as the VBUS IRQ, and another to control the D+ pullup.
1692 lubbock_vbus_irq(int irq
, void *_dev
, struct pt_regs
*r
)
1694 struct pxa2xx_udc
*dev
= _dev
;
1698 HEX_DISPLAY(dev
->stats
.irqs
);
1700 case LUBBOCK_USB_IRQ
:
1703 disable_irq(LUBBOCK_USB_IRQ
);
1704 enable_irq(LUBBOCK_USB_DISC_IRQ
);
1706 case LUBBOCK_USB_DISC_IRQ
:
1709 disable_irq(LUBBOCK_USB_DISC_IRQ
);
1710 enable_irq(LUBBOCK_USB_IRQ
);
1716 pxa2xx_udc_vbus_session(&dev
->gadget
, vbus
);
1723 /*-------------------------------------------------------------------------*/
1725 static inline void clear_ep_state (struct pxa2xx_udc
*dev
)
1729 /* hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint
1730 * fifos, and pending transactions mustn't be continued in any case.
1732 for (i
= 1; i
< PXA_UDC_NUM_ENDPOINTS
; i
++)
1733 nuke(&dev
->ep
[i
], -ECONNABORTED
);
1736 static void udc_watchdog(unsigned long _dev
)
1738 struct pxa2xx_udc
*dev
= (void *)_dev
;
1740 local_irq_disable();
1741 if (dev
->ep0state
== EP0_STALL
1742 && (UDCCS0
& UDCCS0_FST
) == 0
1743 && (UDCCS0
& UDCCS0_SST
) == 0) {
1744 UDCCS0
= UDCCS0_FST
|UDCCS0_FTF
;
1745 DBG(DBG_VERBOSE
, "ep0 re-stall\n");
1746 start_watchdog(dev
);
1751 static void handle_ep0 (struct pxa2xx_udc
*dev
)
1753 u32 udccs0
= UDCCS0
;
1754 struct pxa2xx_ep
*ep
= &dev
->ep
[0];
1755 struct pxa2xx_request
*req
;
1757 struct usb_ctrlrequest r
;
1762 if (list_empty(&ep
->queue
))
1765 req
= list_entry(ep
->queue
.next
, struct pxa2xx_request
, queue
);
1767 /* clear stall status */
1768 if (udccs0
& UDCCS0_SST
) {
1770 UDCCS0
= UDCCS0_SST
;
1771 del_timer(&dev
->timer
);
1775 /* previous request unfinished? non-error iff back-to-back ... */
1776 if ((udccs0
& UDCCS0_SA
) != 0 && dev
->ep0state
!= EP0_IDLE
) {
1778 del_timer(&dev
->timer
);
1782 switch (dev
->ep0state
) {
1784 /* late-breaking status? */
1787 /* start control request? */
1788 if (likely((udccs0
& (UDCCS0_OPR
|UDCCS0_SA
|UDCCS0_RNE
))
1789 == (UDCCS0_OPR
|UDCCS0_SA
|UDCCS0_RNE
))) {
1794 /* read SETUP packet */
1795 for (i
= 0; i
< 8; i
++) {
1796 if (unlikely(!(UDCCS0
& UDCCS0_RNE
))) {
1798 DMSG("SETUP %d!\n", i
);
1801 u
.raw
[i
] = (u8
) UDDR0
;
1803 if (unlikely((UDCCS0
& UDCCS0_RNE
) != 0))
1807 DBG(DBG_VERBOSE
, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1808 u
.r
.bRequestType
, u
.r
.bRequest
,
1809 le16_to_cpu(u
.r
.wValue
),
1810 le16_to_cpu(u
.r
.wIndex
),
1811 le16_to_cpu(u
.r
.wLength
));
1813 /* cope with automagic for some standard requests. */
1814 dev
->req_std
= (u
.r
.bRequestType
& USB_TYPE_MASK
)
1815 == USB_TYPE_STANDARD
;
1816 dev
->req_config
= 0;
1817 dev
->req_pending
= 1;
1818 switch (u
.r
.bRequest
) {
1819 /* hardware restricts gadget drivers here! */
1820 case USB_REQ_SET_CONFIGURATION
:
1821 if (u
.r
.bRequestType
== USB_RECIP_DEVICE
) {
1822 /* reflect hardware's automagic
1823 * up to the gadget driver.
1826 dev
->req_config
= 1;
1827 clear_ep_state(dev
);
1828 /* if !has_cfr, there's no synch
1829 * else use AREN (later) not SA|OPR
1830 * USIR0_IR0 acts edge sensitive
1834 /* ... and here, even more ... */
1835 case USB_REQ_SET_INTERFACE
:
1836 if (u
.r
.bRequestType
== USB_RECIP_INTERFACE
) {
1837 /* udc hardware is broken by design:
1838 * - altsetting may only be zero;
1839 * - hw resets all interfaces' eps;
1840 * - ep reset doesn't include halt(?).
1842 DMSG("broken set_interface (%d/%d)\n",
1843 le16_to_cpu(u
.r
.wIndex
),
1844 le16_to_cpu(u
.r
.wValue
));
1848 /* hardware was supposed to hide this */
1849 case USB_REQ_SET_ADDRESS
:
1850 if (u
.r
.bRequestType
== USB_RECIP_DEVICE
) {
1851 ep0start(dev
, 0, "address");
1857 if (u
.r
.bRequestType
& USB_DIR_IN
)
1858 dev
->ep0state
= EP0_IN_DATA_PHASE
;
1860 dev
->ep0state
= EP0_OUT_DATA_PHASE
;
1862 i
= dev
->driver
->setup(&dev
->gadget
, &u
.r
);
1864 /* hardware automagic preventing STALL... */
1865 if (dev
->req_config
) {
1866 /* hardware sometimes neglects to tell
1867 * tell us about config change events,
1868 * so later ones may fail...
1870 WARN("config change %02x fail %d?\n",
1873 /* TODO experiment: if has_cfr,
1874 * hardware didn't ACK; maybe we
1875 * could actually STALL!
1878 DBG(DBG_VERBOSE
, "protocol STALL, "
1879 "%02x err %d\n", UDCCS0
, i
);
1881 /* the watchdog timer helps deal with cases
1882 * where udc seems to clear FST wrongly, and
1883 * then NAKs instead of STALLing.
1885 ep0start(dev
, UDCCS0_FST
|UDCCS0_FTF
, "stall");
1886 start_watchdog(dev
);
1887 dev
->ep0state
= EP0_STALL
;
1889 /* deferred i/o == no response yet */
1890 } else if (dev
->req_pending
) {
1891 if (likely(dev
->ep0state
== EP0_IN_DATA_PHASE
1892 || dev
->req_std
|| u
.r
.wLength
))
1893 ep0start(dev
, 0, "defer");
1895 ep0start(dev
, UDCCS0_IPR
, "defer/IPR");
1898 /* expect at least one data or status stage irq */
1901 } else if (likely((udccs0
& (UDCCS0_OPR
|UDCCS0_SA
))
1902 == (UDCCS0_OPR
|UDCCS0_SA
))) {
1905 /* pxa210/250 erratum 131 for B0/B1 says RNE lies.
1906 * still observed on a pxa255 a0.
1908 DBG(DBG_VERBOSE
, "e131\n");
1911 /* read SETUP data, but don't trust it too much */
1912 for (i
= 0; i
< 8; i
++)
1913 u
.raw
[i
] = (u8
) UDDR0
;
1914 if ((u
.r
.bRequestType
& USB_RECIP_MASK
)
1917 if (u
.word
[0] == 0 && u
.word
[1] == 0)
1921 /* some random early IRQ:
1924 * - OPR got set, without SA (likely status stage)
1926 UDCCS0
= udccs0
& (UDCCS0_SA
|UDCCS0_OPR
);
1929 case EP0_IN_DATA_PHASE
: /* GET_DESCRIPTOR etc */
1930 if (udccs0
& UDCCS0_OPR
) {
1931 UDCCS0
= UDCCS0_OPR
|UDCCS0_FTF
;
1932 DBG(DBG_VERBOSE
, "ep0in premature status\n");
1936 } else /* irq was IPR clearing */ {
1938 /* this IN packet might finish the request */
1939 (void) write_ep0_fifo(ep
, req
);
1940 } /* else IN token before response was written */
1943 case EP0_OUT_DATA_PHASE
: /* SET_DESCRIPTOR etc */
1944 if (udccs0
& UDCCS0_OPR
) {
1946 /* this OUT packet might finish the request */
1947 if (read_ep0_fifo(ep
, req
))
1949 /* else more OUT packets expected */
1950 } /* else OUT token before read was issued */
1951 } else /* irq was IPR clearing */ {
1952 DBG(DBG_VERBOSE
, "ep0out premature status\n");
1961 /* ack control-IN status (maybe in-zlp was skipped)
1962 * also appears after some config change events.
1964 if (udccs0
& UDCCS0_OPR
)
1965 UDCCS0
= UDCCS0_OPR
;
1969 UDCCS0
= UDCCS0_FST
;
1975 static void handle_ep(struct pxa2xx_ep
*ep
)
1977 struct pxa2xx_request
*req
;
1978 int is_in
= ep
->bEndpointAddress
& USB_DIR_IN
;
1984 if (likely (!list_empty(&ep
->queue
)))
1985 req
= list_entry(ep
->queue
.next
,
1986 struct pxa2xx_request
, queue
);
1990 // TODO check FST handling
1992 udccs
= *ep
->reg_udccs
;
1993 if (unlikely(is_in
)) { /* irq from TPC, SST, or (ISO) TUR */
1995 if (likely(ep
->bmAttributes
== USB_ENDPOINT_XFER_BULK
))
1996 tmp
|= UDCCS_BI_SST
;
1999 *ep
->reg_udccs
= tmp
;
2000 if (req
&& likely ((udccs
& UDCCS_BI_TFS
) != 0))
2001 completed
= write_fifo(ep
, req
);
2003 } else { /* irq from RPC (or for ISO, ROF) */
2004 if (likely(ep
->bmAttributes
== USB_ENDPOINT_XFER_BULK
))
2005 tmp
= UDCCS_BO_SST
| UDCCS_BO_DME
;
2007 tmp
= UDCCS_IO_ROF
| UDCCS_IO_DME
;
2010 *ep
->reg_udccs
= tmp
;
2012 /* fifos can hold packets, ready for reading... */
2015 // TODO didn't yet debug out-dma. this approach assumes
2016 // the worst about short packets and RPC; it might be better.
2018 if (likely(ep
->dma
>= 0)) {
2019 if (!(udccs
& UDCCS_BO_RSP
)) {
2020 *ep
->reg_udccs
= UDCCS_BO_RPC
;
2026 completed
= read_fifo(ep
, req
);
2028 pio_irq_disable (ep
->bEndpointAddress
);
2031 } while (completed
);
2035 * pxa2xx_udc_irq - interrupt handler
2037 * avoid delays in ep0 processing. the control handshaking isn't always
2038 * under software control (pxa250c0 and the pxa255 are better), and delays
2039 * could cause usb protocol errors.
2042 pxa2xx_udc_irq(int irq
, void *_dev
, struct pt_regs
*r
)
2044 struct pxa2xx_udc
*dev
= _dev
;
2048 HEX_DISPLAY(dev
->stats
.irqs
);
2054 /* SUSpend Interrupt Request */
2055 if (unlikely(udccr
& UDCCR_SUSIR
)) {
2056 udc_ack_int_UDCCR(UDCCR_SUSIR
);
2058 DBG(DBG_VERBOSE
, "USB suspend%s\n", is_vbus_present()
2059 ? "" : "+disconnect");
2061 if (!is_vbus_present())
2062 stop_activity(dev
, dev
->driver
);
2063 else if (dev
->gadget
.speed
!= USB_SPEED_UNKNOWN
2065 && dev
->driver
->suspend
)
2066 dev
->driver
->suspend(&dev
->gadget
);
2070 /* RESume Interrupt Request */
2071 if (unlikely(udccr
& UDCCR_RESIR
)) {
2072 udc_ack_int_UDCCR(UDCCR_RESIR
);
2074 DBG(DBG_VERBOSE
, "USB resume\n");
2076 if (dev
->gadget
.speed
!= USB_SPEED_UNKNOWN
2078 && dev
->driver
->resume
2079 && is_vbus_present())
2080 dev
->driver
->resume(&dev
->gadget
);
2083 /* ReSeT Interrupt Request - USB reset */
2084 if (unlikely(udccr
& UDCCR_RSTIR
)) {
2085 udc_ack_int_UDCCR(UDCCR_RSTIR
);
2088 if ((UDCCR
& UDCCR_UDA
) == 0) {
2089 DBG(DBG_VERBOSE
, "USB reset start\n");
2091 /* reset driver and endpoints,
2092 * in case that's not yet done
2094 stop_activity (dev
, dev
->driver
);
2097 DBG(DBG_VERBOSE
, "USB reset end\n");
2098 dev
->gadget
.speed
= USB_SPEED_FULL
;
2100 memset(&dev
->stats
, 0, sizeof dev
->stats
);
2101 /* driver and endpoints are still reset */
2105 u32 usir0
= USIR0
& ~UICR0
;
2106 u32 usir1
= USIR1
& ~UICR1
;
2109 if (unlikely (!usir0
&& !usir1
))
2112 DBG(DBG_VERY_NOISY
, "irq %02x.%02x\n", usir1
, usir0
);
2114 /* control traffic */
2115 if (usir0
& USIR0_IR0
) {
2116 dev
->ep
[0].pio_irqs
++;
2121 /* endpoint data transfers */
2122 for (i
= 0; i
< 8; i
++) {
2125 if (i
&& (usir0
& tmp
)) {
2126 handle_ep(&dev
->ep
[i
]);
2131 handle_ep(&dev
->ep
[i
+8]);
2138 /* we could also ask for 1 msec SOF (SIR) interrupts */
2144 /*-------------------------------------------------------------------------*/
2146 static void nop_release (struct device
*dev
)
2148 DMSG("%s %s\n", __FUNCTION__
, dev
->bus_id
);
2151 /* this uses load-time allocation and initialization (instead of
2152 * doing it at run-time) to save code, eliminate fault paths, and
2153 * be more obviously correct.
2155 static struct pxa2xx_udc memory
= {
2157 .ops
= &pxa2xx_udc_ops
,
2158 .ep0
= &memory
.ep
[0].ep
,
2159 .name
= driver_name
,
2162 .release
= nop_release
,
2166 /* control endpoint */
2170 .ops
= &pxa2xx_ep_ops
,
2171 .maxpacket
= EP0_FIFO_SIZE
,
2174 .reg_udccs
= &UDCCS0
,
2178 /* first group of endpoints */
2181 .name
= "ep1in-bulk",
2182 .ops
= &pxa2xx_ep_ops
,
2183 .maxpacket
= BULK_FIFO_SIZE
,
2186 .fifo_size
= BULK_FIFO_SIZE
,
2187 .bEndpointAddress
= USB_DIR_IN
| 1,
2188 .bmAttributes
= USB_ENDPOINT_XFER_BULK
,
2189 .reg_udccs
= &UDCCS1
,
2195 .name
= "ep2out-bulk",
2196 .ops
= &pxa2xx_ep_ops
,
2197 .maxpacket
= BULK_FIFO_SIZE
,
2200 .fifo_size
= BULK_FIFO_SIZE
,
2201 .bEndpointAddress
= 2,
2202 .bmAttributes
= USB_ENDPOINT_XFER_BULK
,
2203 .reg_udccs
= &UDCCS2
,
2208 #ifndef CONFIG_USB_PXA2XX_SMALL
2211 .name
= "ep3in-iso",
2212 .ops
= &pxa2xx_ep_ops
,
2213 .maxpacket
= ISO_FIFO_SIZE
,
2216 .fifo_size
= ISO_FIFO_SIZE
,
2217 .bEndpointAddress
= USB_DIR_IN
| 3,
2218 .bmAttributes
= USB_ENDPOINT_XFER_ISOC
,
2219 .reg_udccs
= &UDCCS3
,
2225 .name
= "ep4out-iso",
2226 .ops
= &pxa2xx_ep_ops
,
2227 .maxpacket
= ISO_FIFO_SIZE
,
2230 .fifo_size
= ISO_FIFO_SIZE
,
2231 .bEndpointAddress
= 4,
2232 .bmAttributes
= USB_ENDPOINT_XFER_ISOC
,
2233 .reg_udccs
= &UDCCS4
,
2240 .name
= "ep5in-int",
2241 .ops
= &pxa2xx_ep_ops
,
2242 .maxpacket
= INT_FIFO_SIZE
,
2245 .fifo_size
= INT_FIFO_SIZE
,
2246 .bEndpointAddress
= USB_DIR_IN
| 5,
2247 .bmAttributes
= USB_ENDPOINT_XFER_INT
,
2248 .reg_udccs
= &UDCCS5
,
2252 /* second group of endpoints */
2255 .name
= "ep6in-bulk",
2256 .ops
= &pxa2xx_ep_ops
,
2257 .maxpacket
= BULK_FIFO_SIZE
,
2260 .fifo_size
= BULK_FIFO_SIZE
,
2261 .bEndpointAddress
= USB_DIR_IN
| 6,
2262 .bmAttributes
= USB_ENDPOINT_XFER_BULK
,
2263 .reg_udccs
= &UDCCS6
,
2269 .name
= "ep7out-bulk",
2270 .ops
= &pxa2xx_ep_ops
,
2271 .maxpacket
= BULK_FIFO_SIZE
,
2274 .fifo_size
= BULK_FIFO_SIZE
,
2275 .bEndpointAddress
= 7,
2276 .bmAttributes
= USB_ENDPOINT_XFER_BULK
,
2277 .reg_udccs
= &UDCCS7
,
2284 .name
= "ep8in-iso",
2285 .ops
= &pxa2xx_ep_ops
,
2286 .maxpacket
= ISO_FIFO_SIZE
,
2289 .fifo_size
= ISO_FIFO_SIZE
,
2290 .bEndpointAddress
= USB_DIR_IN
| 8,
2291 .bmAttributes
= USB_ENDPOINT_XFER_ISOC
,
2292 .reg_udccs
= &UDCCS8
,
2298 .name
= "ep9out-iso",
2299 .ops
= &pxa2xx_ep_ops
,
2300 .maxpacket
= ISO_FIFO_SIZE
,
2303 .fifo_size
= ISO_FIFO_SIZE
,
2304 .bEndpointAddress
= 9,
2305 .bmAttributes
= USB_ENDPOINT_XFER_ISOC
,
2306 .reg_udccs
= &UDCCS9
,
2313 .name
= "ep10in-int",
2314 .ops
= &pxa2xx_ep_ops
,
2315 .maxpacket
= INT_FIFO_SIZE
,
2318 .fifo_size
= INT_FIFO_SIZE
,
2319 .bEndpointAddress
= USB_DIR_IN
| 10,
2320 .bmAttributes
= USB_ENDPOINT_XFER_INT
,
2321 .reg_udccs
= &UDCCS10
,
2322 .reg_uddr
= &UDDR10
,
2325 /* third group of endpoints */
2328 .name
= "ep11in-bulk",
2329 .ops
= &pxa2xx_ep_ops
,
2330 .maxpacket
= BULK_FIFO_SIZE
,
2333 .fifo_size
= BULK_FIFO_SIZE
,
2334 .bEndpointAddress
= USB_DIR_IN
| 11,
2335 .bmAttributes
= USB_ENDPOINT_XFER_BULK
,
2336 .reg_udccs
= &UDCCS11
,
2337 .reg_uddr
= &UDDR11
,
2342 .name
= "ep12out-bulk",
2343 .ops
= &pxa2xx_ep_ops
,
2344 .maxpacket
= BULK_FIFO_SIZE
,
2347 .fifo_size
= BULK_FIFO_SIZE
,
2348 .bEndpointAddress
= 12,
2349 .bmAttributes
= USB_ENDPOINT_XFER_BULK
,
2350 .reg_udccs
= &UDCCS12
,
2351 .reg_ubcr
= &UBCR12
,
2352 .reg_uddr
= &UDDR12
,
2357 .name
= "ep13in-iso",
2358 .ops
= &pxa2xx_ep_ops
,
2359 .maxpacket
= ISO_FIFO_SIZE
,
2362 .fifo_size
= ISO_FIFO_SIZE
,
2363 .bEndpointAddress
= USB_DIR_IN
| 13,
2364 .bmAttributes
= USB_ENDPOINT_XFER_ISOC
,
2365 .reg_udccs
= &UDCCS13
,
2366 .reg_uddr
= &UDDR13
,
2371 .name
= "ep14out-iso",
2372 .ops
= &pxa2xx_ep_ops
,
2373 .maxpacket
= ISO_FIFO_SIZE
,
2376 .fifo_size
= ISO_FIFO_SIZE
,
2377 .bEndpointAddress
= 14,
2378 .bmAttributes
= USB_ENDPOINT_XFER_ISOC
,
2379 .reg_udccs
= &UDCCS14
,
2380 .reg_ubcr
= &UBCR14
,
2381 .reg_uddr
= &UDDR14
,
2386 .name
= "ep15in-int",
2387 .ops
= &pxa2xx_ep_ops
,
2388 .maxpacket
= INT_FIFO_SIZE
,
2391 .fifo_size
= INT_FIFO_SIZE
,
2392 .bEndpointAddress
= USB_DIR_IN
| 15,
2393 .bmAttributes
= USB_ENDPOINT_XFER_INT
,
2394 .reg_udccs
= &UDCCS15
,
2395 .reg_uddr
= &UDDR15
,
2397 #endif /* !CONFIG_USB_PXA2XX_SMALL */
2400 #define CP15R0_VENDOR_MASK 0xffffe000
2402 #if defined(CONFIG_ARCH_PXA)
2403 #define CP15R0_XSCALE_VALUE 0x69052000 /* intel/arm/xscale */
2405 #elif defined(CONFIG_ARCH_IXP4XX)
2406 #define CP15R0_XSCALE_VALUE 0x69054000 /* intel/arm/ixp4xx */
2410 #define CP15R0_PROD_MASK 0x000003f0
2411 #define PXA25x 0x00000100 /* and PXA26x */
2412 #define PXA210 0x00000120
2414 #define CP15R0_REV_MASK 0x0000000f
2416 #define CP15R0_PRODREV_MASK (CP15R0_PROD_MASK | CP15R0_REV_MASK)
2418 #define PXA255_A0 0x00000106 /* or PXA260_B1 */
2419 #define PXA250_C0 0x00000105 /* or PXA26x_B0 */
2420 #define PXA250_B2 0x00000104
2421 #define PXA250_B1 0x00000103 /* or PXA260_A0 */
2422 #define PXA250_B0 0x00000102
2423 #define PXA250_A1 0x00000101
2424 #define PXA250_A0 0x00000100
2426 #define PXA210_C0 0x00000125
2427 #define PXA210_B2 0x00000124
2428 #define PXA210_B1 0x00000123
2429 #define PXA210_B0 0x00000122
2430 #define IXP425_A0 0x000001c1
2433 * probe - binds to the platform device
2435 static int __init
pxa2xx_udc_probe(struct platform_device
*pdev
)
2437 struct pxa2xx_udc
*dev
= &memory
;
2438 int retval
, out_dma
= 1;
2441 /* insist on Intel/ARM/XScale */
2442 asm("mrc%? p15, 0, %0, c0, c0" : "=r" (chiprev
));
2443 if ((chiprev
& CP15R0_VENDOR_MASK
) != CP15R0_XSCALE_VALUE
) {
2444 printk(KERN_ERR
"%s: not XScale!\n", driver_name
);
2448 /* trigger chiprev-specific logic */
2449 switch (chiprev
& CP15R0_PRODREV_MASK
) {
2450 #if defined(CONFIG_ARCH_PXA)
2456 /* A0/A1 "not released"; ep 13, 15 unusable */
2458 case PXA250_B2
: case PXA210_B2
:
2459 case PXA250_B1
: case PXA210_B1
:
2460 case PXA250_B0
: case PXA210_B0
:
2463 case PXA250_C0
: case PXA210_C0
:
2465 #elif defined(CONFIG_ARCH_IXP4XX)
2472 printk(KERN_ERR
"%s: unrecognized processor: %08x\n",
2473 driver_name
, chiprev
);
2474 /* iop3xx, ixp4xx, ... */
2478 pr_debug("%s: IRQ %d%s%s%s\n", driver_name
, IRQ_USB
,
2479 dev
->has_cfr
? "" : " (!cfr)",
2480 out_dma
? "" : " (broken dma-out)",
2488 /* pxa 250 erratum 130 prevents using OUT dma (fixed C0) */
2490 DMSG("disabled OUT dma\n");
2491 dev
->ep
[ 2].reg_drcmr
= dev
->ep
[ 4].reg_drcmr
= 0;
2492 dev
->ep
[ 7].reg_drcmr
= dev
->ep
[ 9].reg_drcmr
= 0;
2493 dev
->ep
[12].reg_drcmr
= dev
->ep
[14].reg_drcmr
= 0;
2497 /* other non-static parts of init */
2498 dev
->dev
= &pdev
->dev
;
2499 dev
->mach
= pdev
->dev
.platform_data
;
2501 init_timer(&dev
->timer
);
2502 dev
->timer
.function
= udc_watchdog
;
2503 dev
->timer
.data
= (unsigned long) dev
;
2505 device_initialize(&dev
->gadget
.dev
);
2506 dev
->gadget
.dev
.parent
= &pdev
->dev
;
2507 dev
->gadget
.dev
.dma_mask
= pdev
->dev
.dma_mask
;
2509 the_controller
= dev
;
2510 platform_set_drvdata(pdev
, dev
);
2515 dev
->vbus
= is_vbus_present();
2517 /* irq setup after old hardware state is cleaned up */
2518 retval
= request_irq(IRQ_USB
, pxa2xx_udc_irq
,
2519 SA_INTERRUPT
, driver_name
, dev
);
2521 printk(KERN_ERR
"%s: can't get irq %i, err %d\n",
2522 driver_name
, IRQ_USB
, retval
);
2527 #ifdef CONFIG_ARCH_LUBBOCK
2528 if (machine_is_lubbock()) {
2529 retval
= request_irq(LUBBOCK_USB_DISC_IRQ
,
2531 SA_INTERRUPT
| SA_SAMPLE_RANDOM
,
2534 printk(KERN_ERR
"%s: can't get irq %i, err %d\n",
2535 driver_name
, LUBBOCK_USB_DISC_IRQ
, retval
);
2537 free_irq(IRQ_USB
, dev
);
2540 retval
= request_irq(LUBBOCK_USB_IRQ
,
2542 SA_INTERRUPT
| SA_SAMPLE_RANDOM
,
2545 printk(KERN_ERR
"%s: can't get irq %i, err %d\n",
2546 driver_name
, LUBBOCK_USB_IRQ
, retval
);
2547 free_irq(LUBBOCK_USB_DISC_IRQ
, dev
);
2551 /* with U-Boot (but not BLOB), hex is off by default */
2552 HEX_DISPLAY(dev
->stats
.irqs
);
2553 LUB_DISC_BLNK_LED
&= 0xff;
2557 create_proc_files();
2562 static void pxa2xx_udc_shutdown(struct platform_device
*_dev
)
2567 static int __exit
pxa2xx_udc_remove(struct platform_device
*pdev
)
2569 struct pxa2xx_udc
*dev
= platform_get_drvdata(pdev
);
2572 remove_proc_files();
2573 usb_gadget_unregister_driver(dev
->driver
);
2576 free_irq(IRQ_USB
, dev
);
2579 if (machine_is_lubbock()) {
2580 free_irq(LUBBOCK_USB_DISC_IRQ
, dev
);
2581 free_irq(LUBBOCK_USB_IRQ
, dev
);
2583 platform_set_drvdata(pdev
, NULL
);
2584 the_controller
= NULL
;
2588 /*-------------------------------------------------------------------------*/
2592 /* USB suspend (controlled by the host) and system suspend (controlled
2593 * by the PXA) don't necessarily work well together. If USB is active,
2594 * the 48 MHz clock is required; so the system can't enter 33 MHz idle
2595 * mode, or any deeper PM saving state.
2597 * For now, we punt and forcibly disconnect from the USB host when PXA
2598 * enters any suspend state. While we're disconnected, we always disable
2599 * the 48MHz USB clock ... allowing PXA sleep and/or 33 MHz idle states.
2600 * Boards without software pullup control shouldn't use those states.
2601 * VBUS IRQs should probably be ignored so that the PXA device just acts
2602 * "dead" to USB hosts until system resume.
2604 static int pxa2xx_udc_suspend(struct platform_device
*dev
, pm_message_t state
)
2606 struct pxa2xx_udc
*udc
= platform_get_drvdata(dev
);
2608 if (!udc
->mach
->udc_command
)
2609 WARN("USB host won't detect disconnect!\n");
2615 static int pxa2xx_udc_resume(struct platform_device
*dev
)
2617 struct pxa2xx_udc
*udc
= platform_get_drvdata(dev
);
2625 #define pxa2xx_udc_suspend NULL
2626 #define pxa2xx_udc_resume NULL
2629 /*-------------------------------------------------------------------------*/
2631 static struct platform_driver udc_driver
= {
2632 .probe
= pxa2xx_udc_probe
,
2633 .shutdown
= pxa2xx_udc_shutdown
,
2634 .remove
= __exit_p(pxa2xx_udc_remove
),
2635 .suspend
= pxa2xx_udc_suspend
,
2636 .resume
= pxa2xx_udc_resume
,
2638 .owner
= THIS_MODULE
,
2639 .name
= "pxa2xx-udc",
2643 static int __init
udc_init(void)
2645 printk(KERN_INFO
"%s: version %s\n", driver_name
, DRIVER_VERSION
);
2646 return platform_driver_register(&udc_driver
);
2648 module_init(udc_init
);
2650 static void __exit
udc_exit(void)
2652 platform_driver_unregister(&udc_driver
);
2654 module_exit(udc_exit
);
2656 MODULE_DESCRIPTION(DRIVER_DESC
);
2657 MODULE_AUTHOR("Frank Becker, Robert Schwebel, David Brownell");
2658 MODULE_LICENSE("GPL");