2 * linux/drivers/usb/gadget/s3c-hsotg.c
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * Copyright 2008 Openmoko, Inc.
8 * Copyright 2008 Simtec Electronics
9 * Ben Dooks <ben@simtec.co.uk>
10 * http://armlinux.simtec.co.uk/
12 * S3C USB2.0 High-speed / OtG driver
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/spinlock.h>
22 #include <linux/interrupt.h>
23 #include <linux/platform_device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/debugfs.h>
26 #include <linux/seq_file.h>
27 #include <linux/delay.h>
29 #include <linux/slab.h>
30 #include <linux/clk.h>
31 #include <linux/regulator/consumer.h>
33 #include <linux/usb/ch9.h>
34 #include <linux/usb/gadget.h>
35 #include <linux/platform_data/s3c-hsotg.h>
39 #include "s3c-hsotg.h"
41 #define DMA_ADDR_INVALID (~((dma_addr_t)0))
43 static const char * const s3c_hsotg_supply_names
[] = {
44 "vusb_d", /* digital USB supply, 1.2V */
45 "vusb_a", /* analog USB supply, 1.1V */
51 * Unfortunately there seems to be a limit of the amount of data that can
52 * be transferred by IN transactions on EP0. This is either 127 bytes or 3
53 * packets (which practically means 1 packet and 63 bytes of data) when the
56 * This means if we are wanting to move >127 bytes of data, we need to
57 * split the transactions up, but just doing one packet at a time does
58 * not work (this may be an implicit DATA0 PID on first packet of the
59 * transaction) and doing 2 packets is outside the controller's limits.
61 * If we try to lower the MPS size for EP0, then no transfers work properly
62 * for EP0, and the system will fail basic enumeration. As no cause for this
63 * has currently been found, we cannot support any large IN transfers for
66 #define EP0_MPS_LIMIT 64
72 * struct s3c_hsotg_ep - driver endpoint definition.
73 * @ep: The gadget layer representation of the endpoint.
74 * @name: The driver generated name for the endpoint.
75 * @queue: Queue of requests for this endpoint.
76 * @parent: Reference back to the parent device structure.
77 * @req: The current request that the endpoint is processing. This is
78 * used to indicate an request has been loaded onto the endpoint
79 * and has yet to be completed (maybe due to data move, or simply
80 * awaiting an ack from the core all the data has been completed).
81 * @debugfs: File entry for debugfs file for this endpoint.
82 * @lock: State lock to protect contents of endpoint.
83 * @dir_in: Set to true if this endpoint is of the IN direction, which
84 * means that it is sending data to the Host.
85 * @index: The index for the endpoint registers.
86 * @name: The name array passed to the USB core.
87 * @halted: Set if the endpoint has been halted.
88 * @periodic: Set if this is a periodic ep, such as Interrupt
89 * @sent_zlp: Set if we've sent a zero-length packet.
90 * @total_data: The total number of data bytes done.
91 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
92 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
93 * @last_load: The offset of data for the last start of request.
94 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
96 * This is the driver's state for each registered enpoint, allowing it
97 * to keep track of transactions that need doing. Each endpoint has a
98 * lock to protect the state, to try and avoid using an overall lock
99 * for the host controller as much as possible.
101 * For periodic IN endpoints, we have fifo_size and fifo_load to try
102 * and keep track of the amount of data in the periodic FIFO for each
103 * of these as we don't have a status register that tells us how much
104 * is in each of them. (note, this may actually be useless information
105 * as in shared-fifo mode periodic in acts like a single-frame packet
106 * buffer than a fifo)
108 struct s3c_hsotg_ep
{
110 struct list_head queue
;
111 struct s3c_hsotg
*parent
;
112 struct s3c_hsotg_req
*req
;
113 struct dentry
*debugfs
;
116 unsigned long total_data
;
117 unsigned int size_loaded
;
118 unsigned int last_load
;
119 unsigned int fifo_load
;
120 unsigned short fifo_size
;
122 unsigned char dir_in
;
125 unsigned int halted
:1;
126 unsigned int periodic
:1;
127 unsigned int sent_zlp
:1;
133 * struct s3c_hsotg - driver state.
134 * @dev: The parent device supplied to the probe function
135 * @driver: USB gadget driver
136 * @plat: The platform specific configuration data.
137 * @regs: The memory area mapped for accessing registers.
138 * @irq: The IRQ number we are using
139 * @supplies: Definition of USB power supplies
140 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
141 * @num_of_eps: Number of available EPs (excluding EP0)
142 * @debug_root: root directrory for debugfs.
143 * @debug_file: main status file for debugfs.
144 * @debug_fifo: FIFO status file for debugfs.
145 * @ep0_reply: Request used for ep0 reply.
146 * @ep0_buff: Buffer for EP0 reply data, if needed.
147 * @ctrl_buff: Buffer for EP0 control requests.
148 * @ctrl_req: Request for EP0 control packets.
149 * @setup: NAK management for EP0 SETUP
150 * @last_rst: Time of last reset
151 * @eps: The endpoints being supplied to the gadget framework
155 struct usb_gadget_driver
*driver
;
156 struct s3c_hsotg_plat
*plat
;
164 struct regulator_bulk_data supplies
[ARRAY_SIZE(s3c_hsotg_supply_names
)];
166 unsigned int dedicated_fifos
:1;
167 unsigned char num_of_eps
;
169 struct dentry
*debug_root
;
170 struct dentry
*debug_file
;
171 struct dentry
*debug_fifo
;
173 struct usb_request
*ep0_reply
;
174 struct usb_request
*ctrl_req
;
178 struct usb_gadget gadget
;
180 unsigned long last_rst
;
181 struct s3c_hsotg_ep
*eps
;
185 * struct s3c_hsotg_req - data transfer request
186 * @req: The USB gadget request
187 * @queue: The list of requests for the endpoint this is queued for.
188 * @in_progress: Has already had size/packets written to core
189 * @mapped: DMA buffer for this request has been mapped via dma_map_single().
191 struct s3c_hsotg_req
{
192 struct usb_request req
;
193 struct list_head queue
;
194 unsigned char in_progress
;
195 unsigned char mapped
;
198 /* conversion functions */
199 static inline struct s3c_hsotg_req
*our_req(struct usb_request
*req
)
201 return container_of(req
, struct s3c_hsotg_req
, req
);
204 static inline struct s3c_hsotg_ep
*our_ep(struct usb_ep
*ep
)
206 return container_of(ep
, struct s3c_hsotg_ep
, ep
);
209 static inline struct s3c_hsotg
*to_hsotg(struct usb_gadget
*gadget
)
211 return container_of(gadget
, struct s3c_hsotg
, gadget
);
214 static inline void __orr32(void __iomem
*ptr
, u32 val
)
216 writel(readl(ptr
) | val
, ptr
);
219 static inline void __bic32(void __iomem
*ptr
, u32 val
)
221 writel(readl(ptr
) & ~val
, ptr
);
224 /* forward decleration of functions */
225 static void s3c_hsotg_dump(struct s3c_hsotg
*hsotg
);
228 * using_dma - return the DMA status of the driver.
229 * @hsotg: The driver state.
231 * Return true if we're using DMA.
233 * Currently, we have the DMA support code worked into everywhere
234 * that needs it, but the AMBA DMA implementation in the hardware can
235 * only DMA from 32bit aligned addresses. This means that gadgets such
236 * as the CDC Ethernet cannot work as they often pass packets which are
239 * Unfortunately the choice to use DMA or not is global to the controller
240 * and seems to be only settable when the controller is being put through
241 * a core reset. This means we either need to fix the gadgets to take
242 * account of DMA alignment, or add bounce buffers (yuerk).
244 * Until this issue is sorted out, we always return 'false'.
246 static inline bool using_dma(struct s3c_hsotg
*hsotg
)
248 return false; /* support is not complete */
252 * s3c_hsotg_en_gsint - enable one or more of the general interrupt
253 * @hsotg: The device state
254 * @ints: A bitmask of the interrupts to enable
256 static void s3c_hsotg_en_gsint(struct s3c_hsotg
*hsotg
, u32 ints
)
258 u32 gsintmsk
= readl(hsotg
->regs
+ GINTMSK
);
261 new_gsintmsk
= gsintmsk
| ints
;
263 if (new_gsintmsk
!= gsintmsk
) {
264 dev_dbg(hsotg
->dev
, "gsintmsk now 0x%08x\n", new_gsintmsk
);
265 writel(new_gsintmsk
, hsotg
->regs
+ GINTMSK
);
270 * s3c_hsotg_disable_gsint - disable one or more of the general interrupt
271 * @hsotg: The device state
272 * @ints: A bitmask of the interrupts to enable
274 static void s3c_hsotg_disable_gsint(struct s3c_hsotg
*hsotg
, u32 ints
)
276 u32 gsintmsk
= readl(hsotg
->regs
+ GINTMSK
);
279 new_gsintmsk
= gsintmsk
& ~ints
;
281 if (new_gsintmsk
!= gsintmsk
)
282 writel(new_gsintmsk
, hsotg
->regs
+ GINTMSK
);
286 * s3c_hsotg_ctrl_epint - enable/disable an endpoint irq
287 * @hsotg: The device state
288 * @ep: The endpoint index
289 * @dir_in: True if direction is in.
290 * @en: The enable value, true to enable
292 * Set or clear the mask for an individual endpoint's interrupt
295 static void s3c_hsotg_ctrl_epint(struct s3c_hsotg
*hsotg
,
296 unsigned int ep
, unsigned int dir_in
,
306 local_irq_save(flags
);
307 daint
= readl(hsotg
->regs
+ DAINTMSK
);
312 writel(daint
, hsotg
->regs
+ DAINTMSK
);
313 local_irq_restore(flags
);
317 * s3c_hsotg_init_fifo - initialise non-periodic FIFOs
318 * @hsotg: The device instance.
320 static void s3c_hsotg_init_fifo(struct s3c_hsotg
*hsotg
)
328 /* set FIFO sizes to 2048/1024 */
330 writel(2048, hsotg
->regs
+ GRXFSIZ
);
331 writel(GNPTXFSIZ_NPTxFStAddr(2048) |
332 GNPTXFSIZ_NPTxFDep(1024),
333 hsotg
->regs
+ GNPTXFSIZ
);
336 * arange all the rest of the TX FIFOs, as some versions of this
337 * block have overlapping default addresses. This also ensures
338 * that if the settings have been changed, then they are set to
342 /* start at the end of the GNPTXFSIZ, rounded up */
347 * currently we allocate TX FIFOs for all possible endpoints,
348 * and assume that they are all the same size.
351 for (ep
= 1; ep
<= 15; ep
++) {
353 val
|= size
<< DPTXFSIZn_DPTxFSize_SHIFT
;
356 writel(val
, hsotg
->regs
+ DPTXFSIZn(ep
));
360 * according to p428 of the design guide, we need to ensure that
361 * all fifos are flushed before continuing
364 writel(GRSTCTL_TxFNum(0x10) | GRSTCTL_TxFFlsh
|
365 GRSTCTL_RxFFlsh
, hsotg
->regs
+ GRSTCTL
);
367 /* wait until the fifos are both flushed */
370 val
= readl(hsotg
->regs
+ GRSTCTL
);
372 if ((val
& (GRSTCTL_TxFFlsh
| GRSTCTL_RxFFlsh
)) == 0)
375 if (--timeout
== 0) {
377 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
384 dev_dbg(hsotg
->dev
, "FIFOs reset, timeout at %d\n", timeout
);
388 * @ep: USB endpoint to allocate request for.
389 * @flags: Allocation flags
391 * Allocate a new USB request structure appropriate for the specified endpoint
393 static struct usb_request
*s3c_hsotg_ep_alloc_request(struct usb_ep
*ep
,
396 struct s3c_hsotg_req
*req
;
398 req
= kzalloc(sizeof(struct s3c_hsotg_req
), flags
);
402 INIT_LIST_HEAD(&req
->queue
);
404 req
->req
.dma
= DMA_ADDR_INVALID
;
409 * is_ep_periodic - return true if the endpoint is in periodic mode.
410 * @hs_ep: The endpoint to query.
412 * Returns true if the endpoint is in periodic mode, meaning it is being
413 * used for an Interrupt or ISO transfer.
415 static inline int is_ep_periodic(struct s3c_hsotg_ep
*hs_ep
)
417 return hs_ep
->periodic
;
421 * s3c_hsotg_unmap_dma - unmap the DMA memory being used for the request
422 * @hsotg: The device state.
423 * @hs_ep: The endpoint for the request
424 * @hs_req: The request being processed.
426 * This is the reverse of s3c_hsotg_map_dma(), called for the completion
427 * of a request to ensure the buffer is ready for access by the caller.
429 static void s3c_hsotg_unmap_dma(struct s3c_hsotg
*hsotg
,
430 struct s3c_hsotg_ep
*hs_ep
,
431 struct s3c_hsotg_req
*hs_req
)
433 struct usb_request
*req
= &hs_req
->req
;
434 enum dma_data_direction dir
;
436 dir
= hs_ep
->dir_in
? DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
438 /* ignore this if we're not moving any data */
439 if (hs_req
->req
.length
== 0)
442 if (hs_req
->mapped
) {
443 /* we mapped this, so unmap and remove the dma */
445 dma_unmap_single(hsotg
->dev
, req
->dma
, req
->length
, dir
);
447 req
->dma
= DMA_ADDR_INVALID
;
450 dma_sync_single_for_cpu(hsotg
->dev
, req
->dma
, req
->length
, dir
);
455 * s3c_hsotg_write_fifo - write packet Data to the TxFIFO
456 * @hsotg: The controller state.
457 * @hs_ep: The endpoint we're going to write for.
458 * @hs_req: The request to write data for.
460 * This is called when the TxFIFO has some space in it to hold a new
461 * transmission and we have something to give it. The actual setup of
462 * the data size is done elsewhere, so all we have to do is to actually
465 * The return value is zero if there is more space (or nothing was done)
466 * otherwise -ENOSPC is returned if the FIFO space was used up.
468 * This routine is only needed for PIO
470 static int s3c_hsotg_write_fifo(struct s3c_hsotg
*hsotg
,
471 struct s3c_hsotg_ep
*hs_ep
,
472 struct s3c_hsotg_req
*hs_req
)
474 bool periodic
= is_ep_periodic(hs_ep
);
475 u32 gnptxsts
= readl(hsotg
->regs
+ GNPTXSTS
);
476 int buf_pos
= hs_req
->req
.actual
;
477 int to_write
= hs_ep
->size_loaded
;
482 to_write
-= (buf_pos
- hs_ep
->last_load
);
484 /* if there's nothing to write, get out early */
488 if (periodic
&& !hsotg
->dedicated_fifos
) {
489 u32 epsize
= readl(hsotg
->regs
+ DIEPTSIZ(hs_ep
->index
));
494 * work out how much data was loaded so we can calculate
495 * how much data is left in the fifo.
498 size_left
= DxEPTSIZ_XferSize_GET(epsize
);
501 * if shared fifo, we cannot write anything until the
502 * previous data has been completely sent.
504 if (hs_ep
->fifo_load
!= 0) {
505 s3c_hsotg_en_gsint(hsotg
, GINTSTS_PTxFEmp
);
509 dev_dbg(hsotg
->dev
, "%s: left=%d, load=%d, fifo=%d, size %d\n",
511 hs_ep
->size_loaded
, hs_ep
->fifo_load
, hs_ep
->fifo_size
);
513 /* how much of the data has moved */
514 size_done
= hs_ep
->size_loaded
- size_left
;
516 /* how much data is left in the fifo */
517 can_write
= hs_ep
->fifo_load
- size_done
;
518 dev_dbg(hsotg
->dev
, "%s: => can_write1=%d\n",
519 __func__
, can_write
);
521 can_write
= hs_ep
->fifo_size
- can_write
;
522 dev_dbg(hsotg
->dev
, "%s: => can_write2=%d\n",
523 __func__
, can_write
);
525 if (can_write
<= 0) {
526 s3c_hsotg_en_gsint(hsotg
, GINTSTS_PTxFEmp
);
529 } else if (hsotg
->dedicated_fifos
&& hs_ep
->index
!= 0) {
530 can_write
= readl(hsotg
->regs
+ DTXFSTS(hs_ep
->index
));
535 if (GNPTXSTS_NPTxQSpcAvail_GET(gnptxsts
) == 0) {
537 "%s: no queue slots available (0x%08x)\n",
540 s3c_hsotg_en_gsint(hsotg
, GINTSTS_NPTxFEmp
);
544 can_write
= GNPTXSTS_NPTxFSpcAvail_GET(gnptxsts
);
545 can_write
*= 4; /* fifo size is in 32bit quantities. */
548 dev_dbg(hsotg
->dev
, "%s: GNPTXSTS=%08x, can=%d, to=%d, mps %d\n",
549 __func__
, gnptxsts
, can_write
, to_write
, hs_ep
->ep
.maxpacket
);
552 * limit to 512 bytes of data, it seems at least on the non-periodic
553 * FIFO, requests of >512 cause the endpoint to get stuck with a
554 * fragment of the end of the transfer in it.
560 * limit the write to one max-packet size worth of data, but allow
561 * the transfer to return that it did not run out of fifo space
564 if (to_write
> hs_ep
->ep
.maxpacket
) {
565 to_write
= hs_ep
->ep
.maxpacket
;
567 s3c_hsotg_en_gsint(hsotg
,
568 periodic
? GINTSTS_PTxFEmp
:
572 /* see if we can write data */
574 if (to_write
> can_write
) {
575 to_write
= can_write
;
576 pkt_round
= to_write
% hs_ep
->ep
.maxpacket
;
579 * Round the write down to an
580 * exact number of packets.
582 * Note, we do not currently check to see if we can ever
583 * write a full packet or not to the FIFO.
587 to_write
-= pkt_round
;
590 * enable correct FIFO interrupt to alert us when there
594 s3c_hsotg_en_gsint(hsotg
,
595 periodic
? GINTSTS_PTxFEmp
:
599 dev_dbg(hsotg
->dev
, "write %d/%d, can_write %d, done %d\n",
600 to_write
, hs_req
->req
.length
, can_write
, buf_pos
);
605 hs_req
->req
.actual
= buf_pos
+ to_write
;
606 hs_ep
->total_data
+= to_write
;
609 hs_ep
->fifo_load
+= to_write
;
611 to_write
= DIV_ROUND_UP(to_write
, 4);
612 data
= hs_req
->req
.buf
+ buf_pos
;
614 writesl(hsotg
->regs
+ EPFIFO(hs_ep
->index
), data
, to_write
);
616 return (to_write
>= can_write
) ? -ENOSPC
: 0;
620 * get_ep_limit - get the maximum data legnth for this endpoint
621 * @hs_ep: The endpoint
623 * Return the maximum data that can be queued in one go on a given endpoint
624 * so that transfers that are too long can be split.
626 static unsigned get_ep_limit(struct s3c_hsotg_ep
*hs_ep
)
628 int index
= hs_ep
->index
;
633 maxsize
= DxEPTSIZ_XferSize_LIMIT
+ 1;
634 maxpkt
= DxEPTSIZ_PktCnt_LIMIT
+ 1;
638 maxpkt
= DIEPTSIZ0_PktCnt_LIMIT
+ 1;
643 /* we made the constant loading easier above by using +1 */
648 * constrain by packet count if maxpkts*pktsize is greater
649 * than the length register size.
652 if ((maxpkt
* hs_ep
->ep
.maxpacket
) < maxsize
)
653 maxsize
= maxpkt
* hs_ep
->ep
.maxpacket
;
659 * s3c_hsotg_start_req - start a USB request from an endpoint's queue
660 * @hsotg: The controller state.
661 * @hs_ep: The endpoint to process a request for
662 * @hs_req: The request to start.
663 * @continuing: True if we are doing more for the current request.
665 * Start the given request running by setting the endpoint registers
666 * appropriately, and writing any data to the FIFOs.
668 static void s3c_hsotg_start_req(struct s3c_hsotg
*hsotg
,
669 struct s3c_hsotg_ep
*hs_ep
,
670 struct s3c_hsotg_req
*hs_req
,
673 struct usb_request
*ureq
= &hs_req
->req
;
674 int index
= hs_ep
->index
;
675 int dir_in
= hs_ep
->dir_in
;
685 if (hs_ep
->req
&& !continuing
) {
686 dev_err(hsotg
->dev
, "%s: active request\n", __func__
);
689 } else if (hs_ep
->req
!= hs_req
&& continuing
) {
691 "%s: continue different req\n", __func__
);
697 epctrl_reg
= dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
698 epsize_reg
= dir_in
? DIEPTSIZ(index
) : DOEPTSIZ(index
);
700 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
701 __func__
, readl(hsotg
->regs
+ epctrl_reg
), index
,
702 hs_ep
->dir_in
? "in" : "out");
704 /* If endpoint is stalled, we will restart request later */
705 ctrl
= readl(hsotg
->regs
+ epctrl_reg
);
707 if (ctrl
& DxEPCTL_Stall
) {
708 dev_warn(hsotg
->dev
, "%s: ep%d is stalled\n", __func__
, index
);
712 length
= ureq
->length
- ureq
->actual
;
713 dev_dbg(hsotg
->dev
, "ureq->length:%d ureq->actual:%d\n",
714 ureq
->length
, ureq
->actual
);
717 "REQ buf %p len %d dma 0x%08x noi=%d zp=%d snok=%d\n",
718 ureq
->buf
, length
, ureq
->dma
,
719 ureq
->no_interrupt
, ureq
->zero
, ureq
->short_not_ok
);
721 maxreq
= get_ep_limit(hs_ep
);
722 if (length
> maxreq
) {
723 int round
= maxreq
% hs_ep
->ep
.maxpacket
;
725 dev_dbg(hsotg
->dev
, "%s: length %d, max-req %d, r %d\n",
726 __func__
, length
, maxreq
, round
);
728 /* round down to multiple of packets */
736 packets
= DIV_ROUND_UP(length
, hs_ep
->ep
.maxpacket
);
738 packets
= 1; /* send one packet if length is zero. */
740 if (dir_in
&& index
!= 0)
741 epsize
= DxEPTSIZ_MC(1);
745 if (index
!= 0 && ureq
->zero
) {
747 * test for the packets being exactly right for the
751 if (length
== (packets
* hs_ep
->ep
.maxpacket
))
755 epsize
|= DxEPTSIZ_PktCnt(packets
);
756 epsize
|= DxEPTSIZ_XferSize(length
);
758 dev_dbg(hsotg
->dev
, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
759 __func__
, packets
, length
, ureq
->length
, epsize
, epsize_reg
);
761 /* store the request as the current one we're doing */
764 /* write size / packets */
765 writel(epsize
, hsotg
->regs
+ epsize_reg
);
767 if (using_dma(hsotg
) && !continuing
) {
768 unsigned int dma_reg
;
771 * write DMA address to control register, buffer already
772 * synced by s3c_hsotg_ep_queue().
775 dma_reg
= dir_in
? DIEPDMA(index
) : DOEPDMA(index
);
776 writel(ureq
->dma
, hsotg
->regs
+ dma_reg
);
778 dev_dbg(hsotg
->dev
, "%s: 0x%08x => 0x%08x\n",
779 __func__
, ureq
->dma
, dma_reg
);
782 ctrl
|= DxEPCTL_EPEna
; /* ensure ep enabled */
783 ctrl
|= DxEPCTL_USBActEp
;
785 dev_dbg(hsotg
->dev
, "setup req:%d\n", hsotg
->setup
);
787 /* For Setup request do not clear NAK */
788 if (hsotg
->setup
&& index
== 0)
791 ctrl
|= DxEPCTL_CNAK
; /* clear NAK set by core */
794 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x\n", __func__
, ctrl
);
795 writel(ctrl
, hsotg
->regs
+ epctrl_reg
);
798 * set these, it seems that DMA support increments past the end
799 * of the packet buffer so we need to calculate the length from
802 hs_ep
->size_loaded
= length
;
803 hs_ep
->last_load
= ureq
->actual
;
805 if (dir_in
&& !using_dma(hsotg
)) {
806 /* set these anyway, we may need them for non-periodic in */
807 hs_ep
->fifo_load
= 0;
809 s3c_hsotg_write_fifo(hsotg
, hs_ep
, hs_req
);
813 * clear the INTknTXFEmpMsk when we start request, more as a aide
814 * to debugging to see what is going on.
817 writel(DIEPMSK_INTknTXFEmpMsk
,
818 hsotg
->regs
+ DIEPINT(index
));
821 * Note, trying to clear the NAK here causes problems with transmit
822 * on the S3C6400 ending up with the TXFIFO becoming full.
825 /* check ep is enabled */
826 if (!(readl(hsotg
->regs
+ epctrl_reg
) & DxEPCTL_EPEna
))
828 "ep%d: failed to become enabled (DxEPCTL=0x%08x)?\n",
829 index
, readl(hsotg
->regs
+ epctrl_reg
));
831 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x\n",
832 __func__
, readl(hsotg
->regs
+ epctrl_reg
));
836 * s3c_hsotg_map_dma - map the DMA memory being used for the request
837 * @hsotg: The device state.
838 * @hs_ep: The endpoint the request is on.
839 * @req: The request being processed.
841 * We've been asked to queue a request, so ensure that the memory buffer
842 * is correctly setup for DMA. If we've been passed an extant DMA address
843 * then ensure the buffer has been synced to memory. If our buffer has no
844 * DMA memory, then we map the memory and mark our request to allow us to
845 * cleanup on completion.
847 static int s3c_hsotg_map_dma(struct s3c_hsotg
*hsotg
,
848 struct s3c_hsotg_ep
*hs_ep
,
849 struct usb_request
*req
)
851 enum dma_data_direction dir
;
852 struct s3c_hsotg_req
*hs_req
= our_req(req
);
854 dir
= hs_ep
->dir_in
? DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
856 /* if the length is zero, ignore the DMA data */
857 if (hs_req
->req
.length
== 0)
860 if (req
->dma
== DMA_ADDR_INVALID
) {
863 dma
= dma_map_single(hsotg
->dev
, req
->buf
, req
->length
, dir
);
865 if (unlikely(dma_mapping_error(hsotg
->dev
, dma
)))
869 dev_err(hsotg
->dev
, "%s: unaligned dma buffer\n",
872 dma_unmap_single(hsotg
->dev
, dma
, req
->length
, dir
);
879 dma_sync_single_for_cpu(hsotg
->dev
, req
->dma
, req
->length
, dir
);
886 dev_err(hsotg
->dev
, "%s: failed to map buffer %p, %d bytes\n",
887 __func__
, req
->buf
, req
->length
);
892 static int s3c_hsotg_ep_queue(struct usb_ep
*ep
, struct usb_request
*req
,
895 struct s3c_hsotg_req
*hs_req
= our_req(req
);
896 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
897 struct s3c_hsotg
*hs
= hs_ep
->parent
;
898 unsigned long irqflags
;
901 dev_dbg(hs
->dev
, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
902 ep
->name
, req
, req
->length
, req
->buf
, req
->no_interrupt
,
903 req
->zero
, req
->short_not_ok
);
905 spin_lock_irqsave(&hs
->lock
, irqflags
);
907 /* initialise status of the request */
908 INIT_LIST_HEAD(&hs_req
->queue
);
910 req
->status
= -EINPROGRESS
;
912 /* if we're using DMA, sync the buffers as necessary */
914 int ret
= s3c_hsotg_map_dma(hs
, hs_ep
, req
);
919 first
= list_empty(&hs_ep
->queue
);
920 list_add_tail(&hs_req
->queue
, &hs_ep
->queue
);
923 s3c_hsotg_start_req(hs
, hs_ep
, hs_req
, false);
925 spin_unlock_irqrestore(&hs
->lock
, irqflags
);
930 static void s3c_hsotg_ep_free_request(struct usb_ep
*ep
,
931 struct usb_request
*req
)
933 struct s3c_hsotg_req
*hs_req
= our_req(req
);
939 * s3c_hsotg_complete_oursetup - setup completion callback
940 * @ep: The endpoint the request was on.
941 * @req: The request completed.
943 * Called on completion of any requests the driver itself
944 * submitted that need cleaning up.
946 static void s3c_hsotg_complete_oursetup(struct usb_ep
*ep
,
947 struct usb_request
*req
)
949 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
950 struct s3c_hsotg
*hsotg
= hs_ep
->parent
;
952 dev_dbg(hsotg
->dev
, "%s: ep %p, req %p\n", __func__
, ep
, req
);
954 s3c_hsotg_ep_free_request(ep
, req
);
958 * ep_from_windex - convert control wIndex value to endpoint
959 * @hsotg: The driver state.
960 * @windex: The control request wIndex field (in host order).
962 * Convert the given wIndex into a pointer to an driver endpoint
963 * structure, or return NULL if it is not a valid endpoint.
965 static struct s3c_hsotg_ep
*ep_from_windex(struct s3c_hsotg
*hsotg
,
968 struct s3c_hsotg_ep
*ep
= &hsotg
->eps
[windex
& 0x7F];
969 int dir
= (windex
& USB_DIR_IN
) ? 1 : 0;
970 int idx
= windex
& 0x7F;
975 if (idx
> hsotg
->num_of_eps
)
978 if (idx
&& ep
->dir_in
!= dir
)
985 * s3c_hsotg_send_reply - send reply to control request
986 * @hsotg: The device state
988 * @buff: Buffer for request
989 * @length: Length of reply.
991 * Create a request and queue it on the given endpoint. This is useful as
992 * an internal method of sending replies to certain control requests, etc.
994 static int s3c_hsotg_send_reply(struct s3c_hsotg
*hsotg
,
995 struct s3c_hsotg_ep
*ep
,
999 struct usb_request
*req
;
1002 dev_dbg(hsotg
->dev
, "%s: buff %p, len %d\n", __func__
, buff
, length
);
1004 req
= s3c_hsotg_ep_alloc_request(&ep
->ep
, GFP_ATOMIC
);
1005 hsotg
->ep0_reply
= req
;
1007 dev_warn(hsotg
->dev
, "%s: cannot alloc req\n", __func__
);
1011 req
->buf
= hsotg
->ep0_buff
;
1012 req
->length
= length
;
1013 req
->zero
= 1; /* always do zero-length final transfer */
1014 req
->complete
= s3c_hsotg_complete_oursetup
;
1017 memcpy(req
->buf
, buff
, length
);
1021 ret
= s3c_hsotg_ep_queue(&ep
->ep
, req
, GFP_ATOMIC
);
1023 dev_warn(hsotg
->dev
, "%s: cannot queue req\n", __func__
);
1031 * s3c_hsotg_process_req_status - process request GET_STATUS
1032 * @hsotg: The device state
1033 * @ctrl: USB control request
1035 static int s3c_hsotg_process_req_status(struct s3c_hsotg
*hsotg
,
1036 struct usb_ctrlrequest
*ctrl
)
1038 struct s3c_hsotg_ep
*ep0
= &hsotg
->eps
[0];
1039 struct s3c_hsotg_ep
*ep
;
1043 dev_dbg(hsotg
->dev
, "%s: USB_REQ_GET_STATUS\n", __func__
);
1046 dev_warn(hsotg
->dev
, "%s: direction out?\n", __func__
);
1050 switch (ctrl
->bRequestType
& USB_RECIP_MASK
) {
1051 case USB_RECIP_DEVICE
:
1052 reply
= cpu_to_le16(0); /* bit 0 => self powered,
1053 * bit 1 => remote wakeup */
1056 case USB_RECIP_INTERFACE
:
1057 /* currently, the data result should be zero */
1058 reply
= cpu_to_le16(0);
1061 case USB_RECIP_ENDPOINT
:
1062 ep
= ep_from_windex(hsotg
, le16_to_cpu(ctrl
->wIndex
));
1066 reply
= cpu_to_le16(ep
->halted
? 1 : 0);
1073 if (le16_to_cpu(ctrl
->wLength
) != 2)
1076 ret
= s3c_hsotg_send_reply(hsotg
, ep0
, &reply
, 2);
1078 dev_err(hsotg
->dev
, "%s: failed to send reply\n", __func__
);
1085 static int s3c_hsotg_ep_sethalt(struct usb_ep
*ep
, int value
);
1088 * get_ep_head - return the first request on the endpoint
1089 * @hs_ep: The controller endpoint to get
1091 * Get the first request on the endpoint.
1093 static struct s3c_hsotg_req
*get_ep_head(struct s3c_hsotg_ep
*hs_ep
)
1095 if (list_empty(&hs_ep
->queue
))
1098 return list_first_entry(&hs_ep
->queue
, struct s3c_hsotg_req
, queue
);
1102 * s3c_hsotg_process_req_featire - process request {SET,CLEAR}_FEATURE
1103 * @hsotg: The device state
1104 * @ctrl: USB control request
1106 static int s3c_hsotg_process_req_feature(struct s3c_hsotg
*hsotg
,
1107 struct usb_ctrlrequest
*ctrl
)
1109 struct s3c_hsotg_ep
*ep0
= &hsotg
->eps
[0];
1110 struct s3c_hsotg_req
*hs_req
;
1112 bool set
= (ctrl
->bRequest
== USB_REQ_SET_FEATURE
);
1113 struct s3c_hsotg_ep
*ep
;
1116 dev_dbg(hsotg
->dev
, "%s: %s_FEATURE\n",
1117 __func__
, set
? "SET" : "CLEAR");
1119 if (ctrl
->bRequestType
== USB_RECIP_ENDPOINT
) {
1120 ep
= ep_from_windex(hsotg
, le16_to_cpu(ctrl
->wIndex
));
1122 dev_dbg(hsotg
->dev
, "%s: no endpoint for 0x%04x\n",
1123 __func__
, le16_to_cpu(ctrl
->wIndex
));
1127 switch (le16_to_cpu(ctrl
->wValue
)) {
1128 case USB_ENDPOINT_HALT
:
1129 s3c_hsotg_ep_sethalt(&ep
->ep
, set
);
1131 ret
= s3c_hsotg_send_reply(hsotg
, ep0
, NULL
, 0);
1134 "%s: failed to send reply\n", __func__
);
1140 * If we have request in progress,
1146 list_del_init(&hs_req
->queue
);
1147 hs_req
->req
.complete(&ep
->ep
,
1151 /* If we have pending request, then start it */
1152 restart
= !list_empty(&ep
->queue
);
1154 hs_req
= get_ep_head(ep
);
1155 s3c_hsotg_start_req(hsotg
, ep
,
1166 return -ENOENT
; /* currently only deal with endpoint */
1172 * s3c_hsotg_process_control - process a control request
1173 * @hsotg: The device state
1174 * @ctrl: The control request received
1176 * The controller has received the SETUP phase of a control request, and
1177 * needs to work out what to do next (and whether to pass it on to the
1180 static void s3c_hsotg_process_control(struct s3c_hsotg
*hsotg
,
1181 struct usb_ctrlrequest
*ctrl
)
1183 struct s3c_hsotg_ep
*ep0
= &hsotg
->eps
[0];
1189 dev_dbg(hsotg
->dev
, "ctrl Req=%02x, Type=%02x, V=%04x, L=%04x\n",
1190 ctrl
->bRequest
, ctrl
->bRequestType
,
1191 ctrl
->wValue
, ctrl
->wLength
);
1194 * record the direction of the request, for later use when enquing
1198 ep0
->dir_in
= (ctrl
->bRequestType
& USB_DIR_IN
) ? 1 : 0;
1199 dev_dbg(hsotg
->dev
, "ctrl: dir_in=%d\n", ep0
->dir_in
);
1202 * if we've no data with this request, then the last part of the
1203 * transaction is going to implicitly be IN.
1205 if (ctrl
->wLength
== 0)
1208 if ((ctrl
->bRequestType
& USB_TYPE_MASK
) == USB_TYPE_STANDARD
) {
1209 switch (ctrl
->bRequest
) {
1210 case USB_REQ_SET_ADDRESS
:
1211 dcfg
= readl(hsotg
->regs
+ DCFG
);
1212 dcfg
&= ~DCFG_DevAddr_MASK
;
1213 dcfg
|= ctrl
->wValue
<< DCFG_DevAddr_SHIFT
;
1214 writel(dcfg
, hsotg
->regs
+ DCFG
);
1216 dev_info(hsotg
->dev
, "new address %d\n", ctrl
->wValue
);
1218 ret
= s3c_hsotg_send_reply(hsotg
, ep0
, NULL
, 0);
1221 case USB_REQ_GET_STATUS
:
1222 ret
= s3c_hsotg_process_req_status(hsotg
, ctrl
);
1225 case USB_REQ_CLEAR_FEATURE
:
1226 case USB_REQ_SET_FEATURE
:
1227 ret
= s3c_hsotg_process_req_feature(hsotg
, ctrl
);
1232 /* as a fallback, try delivering it to the driver to deal with */
1234 if (ret
== 0 && hsotg
->driver
) {
1235 ret
= hsotg
->driver
->setup(&hsotg
->gadget
, ctrl
);
1237 dev_dbg(hsotg
->dev
, "driver->setup() ret %d\n", ret
);
1241 * the request is either unhandlable, or is not formatted correctly
1242 * so respond with a STALL for the status stage to indicate failure.
1249 dev_dbg(hsotg
->dev
, "ep0 stall (dir=%d)\n", ep0
->dir_in
);
1250 reg
= (ep0
->dir_in
) ? DIEPCTL0
: DOEPCTL0
;
1253 * DxEPCTL_Stall will be cleared by EP once it has
1254 * taken effect, so no need to clear later.
1257 ctrl
= readl(hsotg
->regs
+ reg
);
1258 ctrl
|= DxEPCTL_Stall
;
1259 ctrl
|= DxEPCTL_CNAK
;
1260 writel(ctrl
, hsotg
->regs
+ reg
);
1263 "written DxEPCTL=0x%08x to %08x (DxEPCTL=0x%08x)\n",
1264 ctrl
, reg
, readl(hsotg
->regs
+ reg
));
1267 * don't believe we need to anything more to get the EP
1268 * to reply with a STALL packet
1273 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg
*hsotg
);
1276 * s3c_hsotg_complete_setup - completion of a setup transfer
1277 * @ep: The endpoint the request was on.
1278 * @req: The request completed.
1280 * Called on completion of any requests the driver itself submitted for
1283 static void s3c_hsotg_complete_setup(struct usb_ep
*ep
,
1284 struct usb_request
*req
)
1286 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
1287 struct s3c_hsotg
*hsotg
= hs_ep
->parent
;
1289 if (req
->status
< 0) {
1290 dev_dbg(hsotg
->dev
, "%s: failed %d\n", __func__
, req
->status
);
1294 if (req
->actual
== 0)
1295 s3c_hsotg_enqueue_setup(hsotg
);
1297 s3c_hsotg_process_control(hsotg
, req
->buf
);
1301 * s3c_hsotg_enqueue_setup - start a request for EP0 packets
1302 * @hsotg: The device state.
1304 * Enqueue a request on EP0 if necessary to received any SETUP packets
1305 * received from the host.
1307 static void s3c_hsotg_enqueue_setup(struct s3c_hsotg
*hsotg
)
1309 struct usb_request
*req
= hsotg
->ctrl_req
;
1310 struct s3c_hsotg_req
*hs_req
= our_req(req
);
1313 dev_dbg(hsotg
->dev
, "%s: queueing setup request\n", __func__
);
1317 req
->buf
= hsotg
->ctrl_buff
;
1318 req
->complete
= s3c_hsotg_complete_setup
;
1320 if (!list_empty(&hs_req
->queue
)) {
1321 dev_dbg(hsotg
->dev
, "%s already queued???\n", __func__
);
1325 hsotg
->eps
[0].dir_in
= 0;
1327 ret
= s3c_hsotg_ep_queue(&hsotg
->eps
[0].ep
, req
, GFP_ATOMIC
);
1329 dev_err(hsotg
->dev
, "%s: failed queue (%d)\n", __func__
, ret
);
1331 * Don't think there's much we can do other than watch the
1338 * s3c_hsotg_complete_request - complete a request given to us
1339 * @hsotg: The device state.
1340 * @hs_ep: The endpoint the request was on.
1341 * @hs_req: The request to complete.
1342 * @result: The result code (0 => Ok, otherwise errno)
1344 * The given request has finished, so call the necessary completion
1345 * if it has one and then look to see if we can start a new request
1348 * Note, expects the ep to already be locked as appropriate.
1350 static void s3c_hsotg_complete_request(struct s3c_hsotg
*hsotg
,
1351 struct s3c_hsotg_ep
*hs_ep
,
1352 struct s3c_hsotg_req
*hs_req
,
1358 dev_dbg(hsotg
->dev
, "%s: nothing to complete?\n", __func__
);
1362 dev_dbg(hsotg
->dev
, "complete: ep %p %s, req %p, %d => %p\n",
1363 hs_ep
, hs_ep
->ep
.name
, hs_req
, result
, hs_req
->req
.complete
);
1366 * only replace the status if we've not already set an error
1367 * from a previous transaction
1370 if (hs_req
->req
.status
== -EINPROGRESS
)
1371 hs_req
->req
.status
= result
;
1374 list_del_init(&hs_req
->queue
);
1376 if (using_dma(hsotg
))
1377 s3c_hsotg_unmap_dma(hsotg
, hs_ep
, hs_req
);
1380 * call the complete request with the locks off, just in case the
1381 * request tries to queue more work for this endpoint.
1384 if (hs_req
->req
.complete
) {
1385 spin_unlock(&hsotg
->lock
);
1386 hs_req
->req
.complete(&hs_ep
->ep
, &hs_req
->req
);
1387 spin_lock(&hsotg
->lock
);
1391 * Look to see if there is anything else to do. Note, the completion
1392 * of the previous request may have caused a new request to be started
1393 * so be careful when doing this.
1396 if (!hs_ep
->req
&& result
>= 0) {
1397 restart
= !list_empty(&hs_ep
->queue
);
1399 hs_req
= get_ep_head(hs_ep
);
1400 s3c_hsotg_start_req(hsotg
, hs_ep
, hs_req
, false);
1406 * s3c_hsotg_complete_request_lock - complete a request given to us (locked)
1407 * @hsotg: The device state.
1408 * @hs_ep: The endpoint the request was on.
1409 * @hs_req: The request to complete.
1410 * @result: The result code (0 => Ok, otherwise errno)
1412 * See s3c_hsotg_complete_request(), but called with the endpoint's
1415 static void s3c_hsotg_complete_request_lock(struct s3c_hsotg
*hsotg
,
1416 struct s3c_hsotg_ep
*hs_ep
,
1417 struct s3c_hsotg_req
*hs_req
,
1420 unsigned long flags
;
1422 spin_lock_irqsave(&hsotg
->lock
, flags
);
1423 s3c_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, result
);
1424 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
1428 * s3c_hsotg_rx_data - receive data from the FIFO for an endpoint
1429 * @hsotg: The device state.
1430 * @ep_idx: The endpoint index for the data
1431 * @size: The size of data in the fifo, in bytes
1433 * The FIFO status shows there is data to read from the FIFO for a given
1434 * endpoint, so sort out whether we need to read the data into a request
1435 * that has been made for that endpoint.
1437 static void s3c_hsotg_rx_data(struct s3c_hsotg
*hsotg
, int ep_idx
, int size
)
1439 struct s3c_hsotg_ep
*hs_ep
= &hsotg
->eps
[ep_idx
];
1440 struct s3c_hsotg_req
*hs_req
= hs_ep
->req
;
1441 void __iomem
*fifo
= hsotg
->regs
+ EPFIFO(ep_idx
);
1446 spin_lock(&hsotg
->lock
);
1449 u32 epctl
= readl(hsotg
->regs
+ DOEPCTL(ep_idx
));
1452 dev_warn(hsotg
->dev
,
1453 "%s: FIFO %d bytes on ep%d but no req (DxEPCTl=0x%08x)\n",
1454 __func__
, size
, ep_idx
, epctl
);
1456 /* dump the data from the FIFO, we've nothing we can do */
1457 for (ptr
= 0; ptr
< size
; ptr
+= 4)
1460 spin_unlock(&hsotg
->lock
);
1465 read_ptr
= hs_req
->req
.actual
;
1466 max_req
= hs_req
->req
.length
- read_ptr
;
1468 dev_dbg(hsotg
->dev
, "%s: read %d/%d, done %d/%d\n",
1469 __func__
, to_read
, max_req
, read_ptr
, hs_req
->req
.length
);
1471 if (to_read
> max_req
) {
1473 * more data appeared than we where willing
1474 * to deal with in this request.
1477 /* currently we don't deal this */
1481 hs_ep
->total_data
+= to_read
;
1482 hs_req
->req
.actual
+= to_read
;
1483 to_read
= DIV_ROUND_UP(to_read
, 4);
1486 * note, we might over-write the buffer end by 3 bytes depending on
1487 * alignment of the data.
1489 readsl(fifo
, hs_req
->req
.buf
+ read_ptr
, to_read
);
1491 spin_unlock(&hsotg
->lock
);
1495 * s3c_hsotg_send_zlp - send zero-length packet on control endpoint
1496 * @hsotg: The device instance
1497 * @req: The request currently on this endpoint
1499 * Generate a zero-length IN packet request for terminating a SETUP
1502 * Note, since we don't write any data to the TxFIFO, then it is
1503 * currently believed that we do not need to wait for any space in
1506 static void s3c_hsotg_send_zlp(struct s3c_hsotg
*hsotg
,
1507 struct s3c_hsotg_req
*req
)
1512 dev_warn(hsotg
->dev
, "%s: no request?\n", __func__
);
1516 if (req
->req
.length
== 0) {
1517 hsotg
->eps
[0].sent_zlp
= 1;
1518 s3c_hsotg_enqueue_setup(hsotg
);
1522 hsotg
->eps
[0].dir_in
= 1;
1523 hsotg
->eps
[0].sent_zlp
= 1;
1525 dev_dbg(hsotg
->dev
, "sending zero-length packet\n");
1527 /* issue a zero-sized packet to terminate this */
1528 writel(DxEPTSIZ_MC(1) | DxEPTSIZ_PktCnt(1) |
1529 DxEPTSIZ_XferSize(0), hsotg
->regs
+ DIEPTSIZ(0));
1531 ctrl
= readl(hsotg
->regs
+ DIEPCTL0
);
1532 ctrl
|= DxEPCTL_CNAK
; /* clear NAK set by core */
1533 ctrl
|= DxEPCTL_EPEna
; /* ensure ep enabled */
1534 ctrl
|= DxEPCTL_USBActEp
;
1535 writel(ctrl
, hsotg
->regs
+ DIEPCTL0
);
1539 * s3c_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1540 * @hsotg: The device instance
1541 * @epnum: The endpoint received from
1542 * @was_setup: Set if processing a SetupDone event.
1544 * The RXFIFO has delivered an OutDone event, which means that the data
1545 * transfer for an OUT endpoint has been completed, either by a short
1546 * packet or by the finish of a transfer.
1548 static void s3c_hsotg_handle_outdone(struct s3c_hsotg
*hsotg
,
1549 int epnum
, bool was_setup
)
1551 u32 epsize
= readl(hsotg
->regs
+ DOEPTSIZ(epnum
));
1552 struct s3c_hsotg_ep
*hs_ep
= &hsotg
->eps
[epnum
];
1553 struct s3c_hsotg_req
*hs_req
= hs_ep
->req
;
1554 struct usb_request
*req
= &hs_req
->req
;
1555 unsigned size_left
= DxEPTSIZ_XferSize_GET(epsize
);
1559 dev_dbg(hsotg
->dev
, "%s: no request active\n", __func__
);
1563 if (using_dma(hsotg
)) {
1567 * Calculate the size of the transfer by checking how much
1568 * is left in the endpoint size register and then working it
1569 * out from the amount we loaded for the transfer.
1571 * We need to do this as DMA pointers are always 32bit aligned
1572 * so may overshoot/undershoot the transfer.
1575 size_done
= hs_ep
->size_loaded
- size_left
;
1576 size_done
+= hs_ep
->last_load
;
1578 req
->actual
= size_done
;
1581 /* if there is more request to do, schedule new transfer */
1582 if (req
->actual
< req
->length
&& size_left
== 0) {
1583 s3c_hsotg_start_req(hsotg
, hs_ep
, hs_req
, true);
1585 } else if (epnum
== 0) {
1587 * After was_setup = 1 =>
1588 * set CNAK for non Setup requests
1590 hsotg
->setup
= was_setup
? 0 : 1;
1593 if (req
->actual
< req
->length
&& req
->short_not_ok
) {
1594 dev_dbg(hsotg
->dev
, "%s: got %d/%d (short not ok) => error\n",
1595 __func__
, req
->actual
, req
->length
);
1598 * todo - what should we return here? there's no one else
1599 * even bothering to check the status.
1605 * Condition req->complete != s3c_hsotg_complete_setup says:
1606 * send ZLP when we have an asynchronous request from gadget
1608 if (!was_setup
&& req
->complete
!= s3c_hsotg_complete_setup
)
1609 s3c_hsotg_send_zlp(hsotg
, hs_req
);
1612 s3c_hsotg_complete_request_lock(hsotg
, hs_ep
, hs_req
, result
);
1616 * s3c_hsotg_read_frameno - read current frame number
1617 * @hsotg: The device instance
1619 * Return the current frame number
1621 static u32
s3c_hsotg_read_frameno(struct s3c_hsotg
*hsotg
)
1625 dsts
= readl(hsotg
->regs
+ DSTS
);
1626 dsts
&= DSTS_SOFFN_MASK
;
1627 dsts
>>= DSTS_SOFFN_SHIFT
;
1633 * s3c_hsotg_handle_rx - RX FIFO has data
1634 * @hsotg: The device instance
1636 * The IRQ handler has detected that the RX FIFO has some data in it
1637 * that requires processing, so find out what is in there and do the
1640 * The RXFIFO is a true FIFO, the packets coming out are still in packet
1641 * chunks, so if you have x packets received on an endpoint you'll get x
1642 * FIFO events delivered, each with a packet's worth of data in it.
1644 * When using DMA, we should not be processing events from the RXFIFO
1645 * as the actual data should be sent to the memory directly and we turn
1646 * on the completion interrupts to get notifications of transfer completion.
1648 static void s3c_hsotg_handle_rx(struct s3c_hsotg
*hsotg
)
1650 u32 grxstsr
= readl(hsotg
->regs
+ GRXSTSP
);
1651 u32 epnum
, status
, size
;
1653 WARN_ON(using_dma(hsotg
));
1655 epnum
= grxstsr
& GRXSTS_EPNum_MASK
;
1656 status
= grxstsr
& GRXSTS_PktSts_MASK
;
1658 size
= grxstsr
& GRXSTS_ByteCnt_MASK
;
1659 size
>>= GRXSTS_ByteCnt_SHIFT
;
1662 dev_dbg(hsotg
->dev
, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1663 __func__
, grxstsr
, size
, epnum
);
1665 #define __status(x) ((x) >> GRXSTS_PktSts_SHIFT)
1667 switch (status
>> GRXSTS_PktSts_SHIFT
) {
1668 case __status(GRXSTS_PktSts_GlobalOutNAK
):
1669 dev_dbg(hsotg
->dev
, "GlobalOutNAK\n");
1672 case __status(GRXSTS_PktSts_OutDone
):
1673 dev_dbg(hsotg
->dev
, "OutDone (Frame=0x%08x)\n",
1674 s3c_hsotg_read_frameno(hsotg
));
1676 if (!using_dma(hsotg
))
1677 s3c_hsotg_handle_outdone(hsotg
, epnum
, false);
1680 case __status(GRXSTS_PktSts_SetupDone
):
1682 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1683 s3c_hsotg_read_frameno(hsotg
),
1684 readl(hsotg
->regs
+ DOEPCTL(0)));
1686 s3c_hsotg_handle_outdone(hsotg
, epnum
, true);
1689 case __status(GRXSTS_PktSts_OutRX
):
1690 s3c_hsotg_rx_data(hsotg
, epnum
, size
);
1693 case __status(GRXSTS_PktSts_SetupRX
):
1695 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1696 s3c_hsotg_read_frameno(hsotg
),
1697 readl(hsotg
->regs
+ DOEPCTL(0)));
1699 s3c_hsotg_rx_data(hsotg
, epnum
, size
);
1703 dev_warn(hsotg
->dev
, "%s: unknown status %08x\n",
1706 s3c_hsotg_dump(hsotg
);
1712 * s3c_hsotg_ep0_mps - turn max packet size into register setting
1713 * @mps: The maximum packet size in bytes.
1715 static u32
s3c_hsotg_ep0_mps(unsigned int mps
)
1719 return D0EPCTL_MPS_64
;
1721 return D0EPCTL_MPS_32
;
1723 return D0EPCTL_MPS_16
;
1725 return D0EPCTL_MPS_8
;
1728 /* bad max packet size, warn and return invalid result */
1734 * s3c_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1735 * @hsotg: The driver state.
1736 * @ep: The index number of the endpoint
1737 * @mps: The maximum packet size in bytes
1739 * Configure the maximum packet size for the given endpoint, updating
1740 * the hardware control registers to reflect this.
1742 static void s3c_hsotg_set_ep_maxpacket(struct s3c_hsotg
*hsotg
,
1743 unsigned int ep
, unsigned int mps
)
1745 struct s3c_hsotg_ep
*hs_ep
= &hsotg
->eps
[ep
];
1746 void __iomem
*regs
= hsotg
->regs
;
1751 /* EP0 is a special case */
1752 mpsval
= s3c_hsotg_ep0_mps(mps
);
1756 if (mps
>= DxEPCTL_MPS_LIMIT
+1)
1762 hs_ep
->ep
.maxpacket
= mps
;
1765 * update both the in and out endpoint controldir_ registers, even
1766 * if one of the directions may not be in use.
1769 reg
= readl(regs
+ DIEPCTL(ep
));
1770 reg
&= ~DxEPCTL_MPS_MASK
;
1772 writel(reg
, regs
+ DIEPCTL(ep
));
1775 reg
= readl(regs
+ DOEPCTL(ep
));
1776 reg
&= ~DxEPCTL_MPS_MASK
;
1778 writel(reg
, regs
+ DOEPCTL(ep
));
1784 dev_err(hsotg
->dev
, "ep%d: bad mps of %d\n", ep
, mps
);
1788 * s3c_hsotg_txfifo_flush - flush Tx FIFO
1789 * @hsotg: The driver state
1790 * @idx: The index for the endpoint (0..15)
1792 static void s3c_hsotg_txfifo_flush(struct s3c_hsotg
*hsotg
, unsigned int idx
)
1797 writel(GRSTCTL_TxFNum(idx
) | GRSTCTL_TxFFlsh
,
1798 hsotg
->regs
+ GRSTCTL
);
1800 /* wait until the fifo is flushed */
1804 val
= readl(hsotg
->regs
+ GRSTCTL
);
1806 if ((val
& (GRSTCTL_TxFFlsh
)) == 0)
1809 if (--timeout
== 0) {
1811 "%s: timeout flushing fifo (GRSTCTL=%08x)\n",
1820 * s3c_hsotg_trytx - check to see if anything needs transmitting
1821 * @hsotg: The driver state
1822 * @hs_ep: The driver endpoint to check.
1824 * Check to see if there is a request that has data to send, and if so
1825 * make an attempt to write data into the FIFO.
1827 static int s3c_hsotg_trytx(struct s3c_hsotg
*hsotg
,
1828 struct s3c_hsotg_ep
*hs_ep
)
1830 struct s3c_hsotg_req
*hs_req
= hs_ep
->req
;
1832 if (!hs_ep
->dir_in
|| !hs_req
)
1835 if (hs_req
->req
.actual
< hs_req
->req
.length
) {
1836 dev_dbg(hsotg
->dev
, "trying to write more for ep%d\n",
1838 return s3c_hsotg_write_fifo(hsotg
, hs_ep
, hs_req
);
1845 * s3c_hsotg_complete_in - complete IN transfer
1846 * @hsotg: The device state.
1847 * @hs_ep: The endpoint that has just completed.
1849 * An IN transfer has been completed, update the transfer's state and then
1850 * call the relevant completion routines.
1852 static void s3c_hsotg_complete_in(struct s3c_hsotg
*hsotg
,
1853 struct s3c_hsotg_ep
*hs_ep
)
1855 struct s3c_hsotg_req
*hs_req
= hs_ep
->req
;
1856 u32 epsize
= readl(hsotg
->regs
+ DIEPTSIZ(hs_ep
->index
));
1857 int size_left
, size_done
;
1860 dev_dbg(hsotg
->dev
, "XferCompl but no req\n");
1864 /* Finish ZLP handling for IN EP0 transactions */
1865 if (hsotg
->eps
[0].sent_zlp
) {
1866 dev_dbg(hsotg
->dev
, "zlp packet received\n");
1867 s3c_hsotg_complete_request_lock(hsotg
, hs_ep
, hs_req
, 0);
1872 * Calculate the size of the transfer by checking how much is left
1873 * in the endpoint size register and then working it out from
1874 * the amount we loaded for the transfer.
1876 * We do this even for DMA, as the transfer may have incremented
1877 * past the end of the buffer (DMA transfers are always 32bit
1881 size_left
= DxEPTSIZ_XferSize_GET(epsize
);
1883 size_done
= hs_ep
->size_loaded
- size_left
;
1884 size_done
+= hs_ep
->last_load
;
1886 if (hs_req
->req
.actual
!= size_done
)
1887 dev_dbg(hsotg
->dev
, "%s: adjusting size done %d => %d\n",
1888 __func__
, hs_req
->req
.actual
, size_done
);
1890 hs_req
->req
.actual
= size_done
;
1891 dev_dbg(hsotg
->dev
, "req->length:%d req->actual:%d req->zero:%d\n",
1892 hs_req
->req
.length
, hs_req
->req
.actual
, hs_req
->req
.zero
);
1895 * Check if dealing with Maximum Packet Size(MPS) IN transfer at EP0
1896 * When sent data is a multiple MPS size (e.g. 64B ,128B ,192B
1897 * ,256B ... ), after last MPS sized packet send IN ZLP packet to
1898 * inform the host that no more data is available.
1899 * The state of req.zero member is checked to be sure that the value to
1900 * send is smaller than wValue expected from host.
1901 * Check req.length to NOT send another ZLP when the current one is
1902 * under completion (the one for which this completion has been called).
1904 if (hs_req
->req
.length
&& hs_ep
->index
== 0 && hs_req
->req
.zero
&&
1905 hs_req
->req
.length
== hs_req
->req
.actual
&&
1906 !(hs_req
->req
.length
% hs_ep
->ep
.maxpacket
)) {
1908 dev_dbg(hsotg
->dev
, "ep0 zlp IN packet sent\n");
1909 s3c_hsotg_send_zlp(hsotg
, hs_req
);
1914 if (!size_left
&& hs_req
->req
.actual
< hs_req
->req
.length
) {
1915 dev_dbg(hsotg
->dev
, "%s trying more for req...\n", __func__
);
1916 s3c_hsotg_start_req(hsotg
, hs_ep
, hs_req
, true);
1918 s3c_hsotg_complete_request_lock(hsotg
, hs_ep
, hs_req
, 0);
1922 * s3c_hsotg_epint - handle an in/out endpoint interrupt
1923 * @hsotg: The driver state
1924 * @idx: The index for the endpoint (0..15)
1925 * @dir_in: Set if this is an IN endpoint
1927 * Process and clear any interrupt pending for an individual endpoint
1929 static void s3c_hsotg_epint(struct s3c_hsotg
*hsotg
, unsigned int idx
,
1932 struct s3c_hsotg_ep
*hs_ep
= &hsotg
->eps
[idx
];
1933 u32 epint_reg
= dir_in
? DIEPINT(idx
) : DOEPINT(idx
);
1934 u32 epctl_reg
= dir_in
? DIEPCTL(idx
) : DOEPCTL(idx
);
1935 u32 epsiz_reg
= dir_in
? DIEPTSIZ(idx
) : DOEPTSIZ(idx
);
1938 ints
= readl(hsotg
->regs
+ epint_reg
);
1940 /* Clear endpoint interrupts */
1941 writel(ints
, hsotg
->regs
+ epint_reg
);
1943 dev_dbg(hsotg
->dev
, "%s: ep%d(%s) DxEPINT=0x%08x\n",
1944 __func__
, idx
, dir_in
? "in" : "out", ints
);
1946 if (ints
& DxEPINT_XferCompl
) {
1948 "%s: XferCompl: DxEPCTL=0x%08x, DxEPTSIZ=%08x\n",
1949 __func__
, readl(hsotg
->regs
+ epctl_reg
),
1950 readl(hsotg
->regs
+ epsiz_reg
));
1953 * we get OutDone from the FIFO, so we only need to look
1954 * at completing IN requests here
1957 s3c_hsotg_complete_in(hsotg
, hs_ep
);
1959 if (idx
== 0 && !hs_ep
->req
)
1960 s3c_hsotg_enqueue_setup(hsotg
);
1961 } else if (using_dma(hsotg
)) {
1963 * We're using DMA, we need to fire an OutDone here
1964 * as we ignore the RXFIFO.
1967 s3c_hsotg_handle_outdone(hsotg
, idx
, false);
1971 if (ints
& DxEPINT_EPDisbld
) {
1972 dev_dbg(hsotg
->dev
, "%s: EPDisbld\n", __func__
);
1975 int epctl
= readl(hsotg
->regs
+ epctl_reg
);
1977 s3c_hsotg_txfifo_flush(hsotg
, idx
);
1979 if ((epctl
& DxEPCTL_Stall
) &&
1980 (epctl
& DxEPCTL_EPType_Bulk
)) {
1981 int dctl
= readl(hsotg
->regs
+ DCTL
);
1983 dctl
|= DCTL_CGNPInNAK
;
1984 writel(dctl
, hsotg
->regs
+ DCTL
);
1989 if (ints
& DxEPINT_AHBErr
)
1990 dev_dbg(hsotg
->dev
, "%s: AHBErr\n", __func__
);
1992 if (ints
& DxEPINT_Setup
) { /* Setup or Timeout */
1993 dev_dbg(hsotg
->dev
, "%s: Setup/Timeout\n", __func__
);
1995 if (using_dma(hsotg
) && idx
== 0) {
1997 * this is the notification we've received a
1998 * setup packet. In non-DMA mode we'd get this
1999 * from the RXFIFO, instead we need to process
2006 s3c_hsotg_handle_outdone(hsotg
, 0, true);
2010 if (ints
& DxEPINT_Back2BackSetup
)
2011 dev_dbg(hsotg
->dev
, "%s: B2BSetup/INEPNakEff\n", __func__
);
2014 /* not sure if this is important, but we'll clear it anyway */
2015 if (ints
& DIEPMSK_INTknTXFEmpMsk
) {
2016 dev_dbg(hsotg
->dev
, "%s: ep%d: INTknTXFEmpMsk\n",
2020 /* this probably means something bad is happening */
2021 if (ints
& DIEPMSK_INTknEPMisMsk
) {
2022 dev_warn(hsotg
->dev
, "%s: ep%d: INTknEP\n",
2026 /* FIFO has space or is empty (see GAHBCFG) */
2027 if (hsotg
->dedicated_fifos
&&
2028 ints
& DIEPMSK_TxFIFOEmpty
) {
2029 dev_dbg(hsotg
->dev
, "%s: ep%d: TxFIFOEmpty\n",
2031 if (!using_dma(hsotg
))
2032 s3c_hsotg_trytx(hsotg
, hs_ep
);
2038 * s3c_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
2039 * @hsotg: The device state.
2041 * Handle updating the device settings after the enumeration phase has
2044 static void s3c_hsotg_irq_enumdone(struct s3c_hsotg
*hsotg
)
2046 u32 dsts
= readl(hsotg
->regs
+ DSTS
);
2047 int ep0_mps
= 0, ep_mps
;
2050 * This should signal the finish of the enumeration phase
2051 * of the USB handshaking, so we should now know what rate
2055 dev_dbg(hsotg
->dev
, "EnumDone (DSTS=0x%08x)\n", dsts
);
2058 * note, since we're limited by the size of transfer on EP0, and
2059 * it seems IN transfers must be a even number of packets we do
2060 * not advertise a 64byte MPS on EP0.
2063 /* catch both EnumSpd_FS and EnumSpd_FS48 */
2064 switch (dsts
& DSTS_EnumSpd_MASK
) {
2065 case DSTS_EnumSpd_FS
:
2066 case DSTS_EnumSpd_FS48
:
2067 hsotg
->gadget
.speed
= USB_SPEED_FULL
;
2068 ep0_mps
= EP0_MPS_LIMIT
;
2072 case DSTS_EnumSpd_HS
:
2073 hsotg
->gadget
.speed
= USB_SPEED_HIGH
;
2074 ep0_mps
= EP0_MPS_LIMIT
;
2078 case DSTS_EnumSpd_LS
:
2079 hsotg
->gadget
.speed
= USB_SPEED_LOW
;
2081 * note, we don't actually support LS in this driver at the
2082 * moment, and the documentation seems to imply that it isn't
2083 * supported by the PHYs on some of the devices.
2087 dev_info(hsotg
->dev
, "new device is %s\n",
2088 usb_speed_string(hsotg
->gadget
.speed
));
2091 * we should now know the maximum packet size for an
2092 * endpoint, so set the endpoints to a default value.
2097 s3c_hsotg_set_ep_maxpacket(hsotg
, 0, ep0_mps
);
2098 for (i
= 1; i
< hsotg
->num_of_eps
; i
++)
2099 s3c_hsotg_set_ep_maxpacket(hsotg
, i
, ep_mps
);
2102 /* ensure after enumeration our EP0 is active */
2104 s3c_hsotg_enqueue_setup(hsotg
);
2106 dev_dbg(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2107 readl(hsotg
->regs
+ DIEPCTL0
),
2108 readl(hsotg
->regs
+ DOEPCTL0
));
2112 * kill_all_requests - remove all requests from the endpoint's queue
2113 * @hsotg: The device state.
2114 * @ep: The endpoint the requests may be on.
2115 * @result: The result code to use.
2116 * @force: Force removal of any current requests
2118 * Go through the requests on the given endpoint and mark them
2119 * completed with the given result code.
2121 static void kill_all_requests(struct s3c_hsotg
*hsotg
,
2122 struct s3c_hsotg_ep
*ep
,
2123 int result
, bool force
)
2125 struct s3c_hsotg_req
*req
, *treq
;
2126 unsigned long flags
;
2128 spin_lock_irqsave(&hsotg
->lock
, flags
);
2130 list_for_each_entry_safe(req
, treq
, &ep
->queue
, queue
) {
2132 * currently, we can't do much about an already
2133 * running request on an in endpoint
2136 if (ep
->req
== req
&& ep
->dir_in
&& !force
)
2139 s3c_hsotg_complete_request(hsotg
, ep
, req
,
2143 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2146 #define call_gadget(_hs, _entry) \
2147 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
2148 (_hs)->driver && (_hs)->driver->_entry) \
2149 (_hs)->driver->_entry(&(_hs)->gadget);
2152 * s3c_hsotg_disconnect - disconnect service
2153 * @hsotg: The device state.
2155 * The device has been disconnected. Remove all current
2156 * transactions and signal the gadget driver that this
2159 static void s3c_hsotg_disconnect(struct s3c_hsotg
*hsotg
)
2163 for (ep
= 0; ep
< hsotg
->num_of_eps
; ep
++)
2164 kill_all_requests(hsotg
, &hsotg
->eps
[ep
], -ESHUTDOWN
, true);
2166 call_gadget(hsotg
, disconnect
);
2170 * s3c_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
2171 * @hsotg: The device state:
2172 * @periodic: True if this is a periodic FIFO interrupt
2174 static void s3c_hsotg_irq_fifoempty(struct s3c_hsotg
*hsotg
, bool periodic
)
2176 struct s3c_hsotg_ep
*ep
;
2179 /* look through for any more data to transmit */
2181 for (epno
= 0; epno
< hsotg
->num_of_eps
; epno
++) {
2182 ep
= &hsotg
->eps
[epno
];
2187 if ((periodic
&& !ep
->periodic
) ||
2188 (!periodic
&& ep
->periodic
))
2191 ret
= s3c_hsotg_trytx(hsotg
, ep
);
2197 /* IRQ flags which will trigger a retry around the IRQ loop */
2198 #define IRQ_RETRY_MASK (GINTSTS_NPTxFEmp | \
2203 * s3c_hsotg_corereset - issue softreset to the core
2204 * @hsotg: The device state
2206 * Issue a soft reset to the core, and await the core finishing it.
2208 static int s3c_hsotg_corereset(struct s3c_hsotg
*hsotg
)
2213 dev_dbg(hsotg
->dev
, "resetting core\n");
2215 /* issue soft reset */
2216 writel(GRSTCTL_CSftRst
, hsotg
->regs
+ GRSTCTL
);
2220 grstctl
= readl(hsotg
->regs
+ GRSTCTL
);
2221 } while ((grstctl
& GRSTCTL_CSftRst
) && timeout
-- > 0);
2223 if (grstctl
& GRSTCTL_CSftRst
) {
2224 dev_err(hsotg
->dev
, "Failed to get CSftRst asserted\n");
2231 u32 grstctl
= readl(hsotg
->regs
+ GRSTCTL
);
2233 if (timeout
-- < 0) {
2234 dev_info(hsotg
->dev
,
2235 "%s: reset failed, GRSTCTL=%08x\n",
2240 if (!(grstctl
& GRSTCTL_AHBIdle
))
2243 break; /* reset done */
2246 dev_dbg(hsotg
->dev
, "reset successful\n");
2251 * s3c_hsotg_core_init - issue softreset to the core
2252 * @hsotg: The device state
2254 * Issue a soft reset to the core, and await the core finishing it.
2256 static void s3c_hsotg_core_init(struct s3c_hsotg
*hsotg
)
2258 s3c_hsotg_corereset(hsotg
);
2261 * we must now enable ep0 ready for host detection and then
2262 * set configuration.
2265 /* set the PLL on, remove the HNP/SRP and set the PHY */
2266 writel(GUSBCFG_PHYIf16
| GUSBCFG_TOutCal(7) |
2267 (0x5 << 10), hsotg
->regs
+ GUSBCFG
);
2269 s3c_hsotg_init_fifo(hsotg
);
2271 __orr32(hsotg
->regs
+ DCTL
, DCTL_SftDiscon
);
2273 writel(1 << 18 | DCFG_DevSpd_HS
, hsotg
->regs
+ DCFG
);
2275 /* Clear any pending OTG interrupts */
2276 writel(0xffffffff, hsotg
->regs
+ GOTGINT
);
2278 /* Clear any pending interrupts */
2279 writel(0xffffffff, hsotg
->regs
+ GINTSTS
);
2281 writel(GINTSTS_ErlySusp
| GINTSTS_SessReqInt
|
2282 GINTSTS_GOUTNakEff
| GINTSTS_GINNakEff
|
2283 GINTSTS_ConIDStsChng
| GINTSTS_USBRst
|
2284 GINTSTS_EnumDone
| GINTSTS_OTGInt
|
2285 GINTSTS_USBSusp
| GINTSTS_WkUpInt
,
2286 hsotg
->regs
+ GINTMSK
);
2288 if (using_dma(hsotg
))
2289 writel(GAHBCFG_GlblIntrEn
| GAHBCFG_DMAEn
|
2290 GAHBCFG_HBstLen_Incr4
,
2291 hsotg
->regs
+ GAHBCFG
);
2293 writel(GAHBCFG_GlblIntrEn
, hsotg
->regs
+ GAHBCFG
);
2296 * Enabling INTknTXFEmpMsk here seems to be a big mistake, we end
2297 * up being flooded with interrupts if the host is polling the
2298 * endpoint to try and read data.
2301 writel(((hsotg
->dedicated_fifos
) ? DIEPMSK_TxFIFOEmpty
: 0) |
2302 DIEPMSK_EPDisbldMsk
| DIEPMSK_XferComplMsk
|
2303 DIEPMSK_TimeOUTMsk
| DIEPMSK_AHBErrMsk
|
2304 DIEPMSK_INTknEPMisMsk
,
2305 hsotg
->regs
+ DIEPMSK
);
2308 * don't need XferCompl, we get that from RXFIFO in slave mode. In
2309 * DMA mode we may need this.
2311 writel((using_dma(hsotg
) ? (DIEPMSK_XferComplMsk
|
2312 DIEPMSK_TimeOUTMsk
) : 0) |
2313 DOEPMSK_EPDisbldMsk
| DOEPMSK_AHBErrMsk
|
2315 hsotg
->regs
+ DOEPMSK
);
2317 writel(0, hsotg
->regs
+ DAINTMSK
);
2319 dev_dbg(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2320 readl(hsotg
->regs
+ DIEPCTL0
),
2321 readl(hsotg
->regs
+ DOEPCTL0
));
2323 /* enable in and out endpoint interrupts */
2324 s3c_hsotg_en_gsint(hsotg
, GINTSTS_OEPInt
| GINTSTS_IEPInt
);
2327 * Enable the RXFIFO when in slave mode, as this is how we collect
2328 * the data. In DMA mode, we get events from the FIFO but also
2329 * things we cannot process, so do not use it.
2331 if (!using_dma(hsotg
))
2332 s3c_hsotg_en_gsint(hsotg
, GINTSTS_RxFLvl
);
2334 /* Enable interrupts for EP0 in and out */
2335 s3c_hsotg_ctrl_epint(hsotg
, 0, 0, 1);
2336 s3c_hsotg_ctrl_epint(hsotg
, 0, 1, 1);
2338 __orr32(hsotg
->regs
+ DCTL
, DCTL_PWROnPrgDone
);
2339 udelay(10); /* see openiboot */
2340 __bic32(hsotg
->regs
+ DCTL
, DCTL_PWROnPrgDone
);
2342 dev_dbg(hsotg
->dev
, "DCTL=0x%08x\n", readl(hsotg
->regs
+ DCTL
));
2345 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
2346 * writing to the EPCTL register..
2349 /* set to read 1 8byte packet */
2350 writel(DxEPTSIZ_MC(1) | DxEPTSIZ_PktCnt(1) |
2351 DxEPTSIZ_XferSize(8), hsotg
->regs
+ DOEPTSIZ0
);
2353 writel(s3c_hsotg_ep0_mps(hsotg
->eps
[0].ep
.maxpacket
) |
2354 DxEPCTL_CNAK
| DxEPCTL_EPEna
|
2356 hsotg
->regs
+ DOEPCTL0
);
2358 /* enable, but don't activate EP0in */
2359 writel(s3c_hsotg_ep0_mps(hsotg
->eps
[0].ep
.maxpacket
) |
2360 DxEPCTL_USBActEp
, hsotg
->regs
+ DIEPCTL0
);
2362 s3c_hsotg_enqueue_setup(hsotg
);
2364 dev_dbg(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2365 readl(hsotg
->regs
+ DIEPCTL0
),
2366 readl(hsotg
->regs
+ DOEPCTL0
));
2368 /* clear global NAKs */
2369 writel(DCTL_CGOUTNak
| DCTL_CGNPInNAK
,
2370 hsotg
->regs
+ DCTL
);
2372 /* must be at-least 3ms to allow bus to see disconnect */
2375 /* remove the soft-disconnect and let's go */
2376 __bic32(hsotg
->regs
+ DCTL
, DCTL_SftDiscon
);
2380 * s3c_hsotg_irq - handle device interrupt
2381 * @irq: The IRQ number triggered
2382 * @pw: The pw value when registered the handler.
2384 static irqreturn_t
s3c_hsotg_irq(int irq
, void *pw
)
2386 struct s3c_hsotg
*hsotg
= pw
;
2387 int retry_count
= 8;
2392 gintsts
= readl(hsotg
->regs
+ GINTSTS
);
2393 gintmsk
= readl(hsotg
->regs
+ GINTMSK
);
2395 dev_dbg(hsotg
->dev
, "%s: %08x %08x (%08x) retry %d\n",
2396 __func__
, gintsts
, gintsts
& gintmsk
, gintmsk
, retry_count
);
2400 if (gintsts
& GINTSTS_OTGInt
) {
2401 u32 otgint
= readl(hsotg
->regs
+ GOTGINT
);
2403 dev_info(hsotg
->dev
, "OTGInt: %08x\n", otgint
);
2405 writel(otgint
, hsotg
->regs
+ GOTGINT
);
2408 if (gintsts
& GINTSTS_SessReqInt
) {
2409 dev_dbg(hsotg
->dev
, "%s: SessReqInt\n", __func__
);
2410 writel(GINTSTS_SessReqInt
, hsotg
->regs
+ GINTSTS
);
2413 if (gintsts
& GINTSTS_EnumDone
) {
2414 writel(GINTSTS_EnumDone
, hsotg
->regs
+ GINTSTS
);
2416 s3c_hsotg_irq_enumdone(hsotg
);
2419 if (gintsts
& GINTSTS_ConIDStsChng
) {
2420 dev_dbg(hsotg
->dev
, "ConIDStsChg (DSTS=0x%08x, GOTCTL=%08x)\n",
2421 readl(hsotg
->regs
+ DSTS
),
2422 readl(hsotg
->regs
+ GOTGCTL
));
2424 writel(GINTSTS_ConIDStsChng
, hsotg
->regs
+ GINTSTS
);
2427 if (gintsts
& (GINTSTS_OEPInt
| GINTSTS_IEPInt
)) {
2428 u32 daint
= readl(hsotg
->regs
+ DAINT
);
2429 u32 daint_out
= daint
>> DAINT_OutEP_SHIFT
;
2430 u32 daint_in
= daint
& ~(daint_out
<< DAINT_OutEP_SHIFT
);
2433 dev_dbg(hsotg
->dev
, "%s: daint=%08x\n", __func__
, daint
);
2435 for (ep
= 0; ep
< 15 && daint_out
; ep
++, daint_out
>>= 1) {
2437 s3c_hsotg_epint(hsotg
, ep
, 0);
2440 for (ep
= 0; ep
< 15 && daint_in
; ep
++, daint_in
>>= 1) {
2442 s3c_hsotg_epint(hsotg
, ep
, 1);
2446 if (gintsts
& GINTSTS_USBRst
) {
2448 u32 usb_status
= readl(hsotg
->regs
+ GOTGCTL
);
2450 dev_info(hsotg
->dev
, "%s: USBRst\n", __func__
);
2451 dev_dbg(hsotg
->dev
, "GNPTXSTS=%08x\n",
2452 readl(hsotg
->regs
+ GNPTXSTS
));
2454 writel(GINTSTS_USBRst
, hsotg
->regs
+ GINTSTS
);
2456 if (usb_status
& GOTGCTL_BSESVLD
) {
2457 if (time_after(jiffies
, hsotg
->last_rst
+
2458 msecs_to_jiffies(200))) {
2460 kill_all_requests(hsotg
, &hsotg
->eps
[0],
2463 s3c_hsotg_core_init(hsotg
);
2464 hsotg
->last_rst
= jiffies
;
2469 /* check both FIFOs */
2471 if (gintsts
& GINTSTS_NPTxFEmp
) {
2472 dev_dbg(hsotg
->dev
, "NPTxFEmp\n");
2475 * Disable the interrupt to stop it happening again
2476 * unless one of these endpoint routines decides that
2477 * it needs re-enabling
2480 s3c_hsotg_disable_gsint(hsotg
, GINTSTS_NPTxFEmp
);
2481 s3c_hsotg_irq_fifoempty(hsotg
, false);
2484 if (gintsts
& GINTSTS_PTxFEmp
) {
2485 dev_dbg(hsotg
->dev
, "PTxFEmp\n");
2487 /* See note in GINTSTS_NPTxFEmp */
2489 s3c_hsotg_disable_gsint(hsotg
, GINTSTS_PTxFEmp
);
2490 s3c_hsotg_irq_fifoempty(hsotg
, true);
2493 if (gintsts
& GINTSTS_RxFLvl
) {
2495 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2496 * we need to retry s3c_hsotg_handle_rx if this is still
2500 s3c_hsotg_handle_rx(hsotg
);
2503 if (gintsts
& GINTSTS_ModeMis
) {
2504 dev_warn(hsotg
->dev
, "warning, mode mismatch triggered\n");
2505 writel(GINTSTS_ModeMis
, hsotg
->regs
+ GINTSTS
);
2508 if (gintsts
& GINTSTS_USBSusp
) {
2509 dev_info(hsotg
->dev
, "GINTSTS_USBSusp\n");
2510 writel(GINTSTS_USBSusp
, hsotg
->regs
+ GINTSTS
);
2512 call_gadget(hsotg
, suspend
);
2513 s3c_hsotg_disconnect(hsotg
);
2516 if (gintsts
& GINTSTS_WkUpInt
) {
2517 dev_info(hsotg
->dev
, "GINTSTS_WkUpIn\n");
2518 writel(GINTSTS_WkUpInt
, hsotg
->regs
+ GINTSTS
);
2520 call_gadget(hsotg
, resume
);
2523 if (gintsts
& GINTSTS_ErlySusp
) {
2524 dev_dbg(hsotg
->dev
, "GINTSTS_ErlySusp\n");
2525 writel(GINTSTS_ErlySusp
, hsotg
->regs
+ GINTSTS
);
2527 s3c_hsotg_disconnect(hsotg
);
2531 * these next two seem to crop-up occasionally causing the core
2532 * to shutdown the USB transfer, so try clearing them and logging
2536 if (gintsts
& GINTSTS_GOUTNakEff
) {
2537 dev_info(hsotg
->dev
, "GOUTNakEff triggered\n");
2539 writel(DCTL_CGOUTNak
, hsotg
->regs
+ DCTL
);
2541 s3c_hsotg_dump(hsotg
);
2544 if (gintsts
& GINTSTS_GINNakEff
) {
2545 dev_info(hsotg
->dev
, "GINNakEff triggered\n");
2547 writel(DCTL_CGNPInNAK
, hsotg
->regs
+ DCTL
);
2549 s3c_hsotg_dump(hsotg
);
2553 * if we've had fifo events, we should try and go around the
2554 * loop again to see if there's any point in returning yet.
2557 if (gintsts
& IRQ_RETRY_MASK
&& --retry_count
> 0)
2564 * s3c_hsotg_ep_enable - enable the given endpoint
2565 * @ep: The USB endpint to configure
2566 * @desc: The USB endpoint descriptor to configure with.
2568 * This is called from the USB gadget code's usb_ep_enable().
2570 static int s3c_hsotg_ep_enable(struct usb_ep
*ep
,
2571 const struct usb_endpoint_descriptor
*desc
)
2573 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2574 struct s3c_hsotg
*hsotg
= hs_ep
->parent
;
2575 unsigned long flags
;
2576 int index
= hs_ep
->index
;
2584 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2585 __func__
, ep
->name
, desc
->bEndpointAddress
, desc
->bmAttributes
,
2586 desc
->wMaxPacketSize
, desc
->bInterval
);
2588 /* not to be called for EP0 */
2589 WARN_ON(index
== 0);
2591 dir_in
= (desc
->bEndpointAddress
& USB_ENDPOINT_DIR_MASK
) ? 1 : 0;
2592 if (dir_in
!= hs_ep
->dir_in
) {
2593 dev_err(hsotg
->dev
, "%s: direction mismatch!\n", __func__
);
2597 mps
= usb_endpoint_maxp(desc
);
2599 /* note, we handle this here instead of s3c_hsotg_set_ep_maxpacket */
2601 epctrl_reg
= dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
2602 epctrl
= readl(hsotg
->regs
+ epctrl_reg
);
2604 dev_dbg(hsotg
->dev
, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2605 __func__
, epctrl
, epctrl_reg
);
2607 spin_lock_irqsave(&hsotg
->lock
, flags
);
2609 epctrl
&= ~(DxEPCTL_EPType_MASK
| DxEPCTL_MPS_MASK
);
2610 epctrl
|= DxEPCTL_MPS(mps
);
2613 * mark the endpoint as active, otherwise the core may ignore
2614 * transactions entirely for this endpoint
2616 epctrl
|= DxEPCTL_USBActEp
;
2619 * set the NAK status on the endpoint, otherwise we might try and
2620 * do something with data that we've yet got a request to process
2621 * since the RXFIFO will take data for an endpoint even if the
2622 * size register hasn't been set.
2625 epctrl
|= DxEPCTL_SNAK
;
2627 /* update the endpoint state */
2628 hs_ep
->ep
.maxpacket
= mps
;
2630 /* default, set to non-periodic */
2631 hs_ep
->periodic
= 0;
2633 switch (desc
->bmAttributes
& USB_ENDPOINT_XFERTYPE_MASK
) {
2634 case USB_ENDPOINT_XFER_ISOC
:
2635 dev_err(hsotg
->dev
, "no current ISOC support\n");
2639 case USB_ENDPOINT_XFER_BULK
:
2640 epctrl
|= DxEPCTL_EPType_Bulk
;
2643 case USB_ENDPOINT_XFER_INT
:
2646 * Allocate our TxFNum by simply using the index
2647 * of the endpoint for the moment. We could do
2648 * something better if the host indicates how
2649 * many FIFOs we are expecting to use.
2652 hs_ep
->periodic
= 1;
2653 epctrl
|= DxEPCTL_TxFNum(index
);
2656 epctrl
|= DxEPCTL_EPType_Intterupt
;
2659 case USB_ENDPOINT_XFER_CONTROL
:
2660 epctrl
|= DxEPCTL_EPType_Control
;
2665 * if the hardware has dedicated fifos, we must give each IN EP
2666 * a unique tx-fifo even if it is non-periodic.
2668 if (dir_in
&& hsotg
->dedicated_fifos
)
2669 epctrl
|= DxEPCTL_TxFNum(index
);
2671 /* for non control endpoints, set PID to D0 */
2673 epctrl
|= DxEPCTL_SetD0PID
;
2675 dev_dbg(hsotg
->dev
, "%s: write DxEPCTL=0x%08x\n",
2678 writel(epctrl
, hsotg
->regs
+ epctrl_reg
);
2679 dev_dbg(hsotg
->dev
, "%s: read DxEPCTL=0x%08x\n",
2680 __func__
, readl(hsotg
->regs
+ epctrl_reg
));
2682 /* enable the endpoint interrupt */
2683 s3c_hsotg_ctrl_epint(hsotg
, index
, dir_in
, 1);
2686 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2691 * s3c_hsotg_ep_disable - disable given endpoint
2692 * @ep: The endpoint to disable.
2694 static int s3c_hsotg_ep_disable(struct usb_ep
*ep
)
2696 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2697 struct s3c_hsotg
*hsotg
= hs_ep
->parent
;
2698 int dir_in
= hs_ep
->dir_in
;
2699 int index
= hs_ep
->index
;
2700 unsigned long flags
;
2704 dev_info(hsotg
->dev
, "%s(ep %p)\n", __func__
, ep
);
2706 if (ep
== &hsotg
->eps
[0].ep
) {
2707 dev_err(hsotg
->dev
, "%s: called for ep0\n", __func__
);
2711 epctrl_reg
= dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
2713 /* terminate all requests with shutdown */
2714 kill_all_requests(hsotg
, hs_ep
, -ESHUTDOWN
, false);
2716 spin_lock_irqsave(&hsotg
->lock
, flags
);
2718 ctrl
= readl(hsotg
->regs
+ epctrl_reg
);
2719 ctrl
&= ~DxEPCTL_EPEna
;
2720 ctrl
&= ~DxEPCTL_USBActEp
;
2721 ctrl
|= DxEPCTL_SNAK
;
2723 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x\n", __func__
, ctrl
);
2724 writel(ctrl
, hsotg
->regs
+ epctrl_reg
);
2726 /* disable endpoint interrupts */
2727 s3c_hsotg_ctrl_epint(hsotg
, hs_ep
->index
, hs_ep
->dir_in
, 0);
2729 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
2734 * on_list - check request is on the given endpoint
2735 * @ep: The endpoint to check.
2736 * @test: The request to test if it is on the endpoint.
2738 static bool on_list(struct s3c_hsotg_ep
*ep
, struct s3c_hsotg_req
*test
)
2740 struct s3c_hsotg_req
*req
, *treq
;
2742 list_for_each_entry_safe(req
, treq
, &ep
->queue
, queue
) {
2751 * s3c_hsotg_ep_dequeue - dequeue given endpoint
2752 * @ep: The endpoint to dequeue.
2753 * @req: The request to be removed from a queue.
2755 static int s3c_hsotg_ep_dequeue(struct usb_ep
*ep
, struct usb_request
*req
)
2757 struct s3c_hsotg_req
*hs_req
= our_req(req
);
2758 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2759 struct s3c_hsotg
*hs
= hs_ep
->parent
;
2760 unsigned long flags
;
2762 dev_info(hs
->dev
, "ep_dequeue(%p,%p)\n", ep
, req
);
2764 spin_lock_irqsave(&hs
->lock
, flags
);
2766 if (!on_list(hs_ep
, hs_req
)) {
2767 spin_unlock_irqrestore(&hs
->lock
, flags
);
2771 s3c_hsotg_complete_request(hs
, hs_ep
, hs_req
, -ECONNRESET
);
2772 spin_unlock_irqrestore(&hs
->lock
, flags
);
2778 * s3c_hsotg_ep_sethalt - set halt on a given endpoint
2779 * @ep: The endpoint to set halt.
2780 * @value: Set or unset the halt.
2782 static int s3c_hsotg_ep_sethalt(struct usb_ep
*ep
, int value
)
2784 struct s3c_hsotg_ep
*hs_ep
= our_ep(ep
);
2785 struct s3c_hsotg
*hs
= hs_ep
->parent
;
2786 int index
= hs_ep
->index
;
2787 unsigned long irqflags
;
2792 dev_info(hs
->dev
, "%s(ep %p %s, %d)\n", __func__
, ep
, ep
->name
, value
);
2794 spin_lock_irqsave(&hs
->lock
, irqflags
);
2796 /* write both IN and OUT control registers */
2798 epreg
= DIEPCTL(index
);
2799 epctl
= readl(hs
->regs
+ epreg
);
2802 epctl
|= DxEPCTL_Stall
+ DxEPCTL_SNAK
;
2803 if (epctl
& DxEPCTL_EPEna
)
2804 epctl
|= DxEPCTL_EPDis
;
2806 epctl
&= ~DxEPCTL_Stall
;
2807 xfertype
= epctl
& DxEPCTL_EPType_MASK
;
2808 if (xfertype
== DxEPCTL_EPType_Bulk
||
2809 xfertype
== DxEPCTL_EPType_Intterupt
)
2810 epctl
|= DxEPCTL_SetD0PID
;
2813 writel(epctl
, hs
->regs
+ epreg
);
2815 epreg
= DOEPCTL(index
);
2816 epctl
= readl(hs
->regs
+ epreg
);
2819 epctl
|= DxEPCTL_Stall
;
2821 epctl
&= ~DxEPCTL_Stall
;
2822 xfertype
= epctl
& DxEPCTL_EPType_MASK
;
2823 if (xfertype
== DxEPCTL_EPType_Bulk
||
2824 xfertype
== DxEPCTL_EPType_Intterupt
)
2825 epctl
|= DxEPCTL_SetD0PID
;
2828 writel(epctl
, hs
->regs
+ epreg
);
2830 spin_unlock_irqrestore(&hs
->lock
, irqflags
);
2835 static struct usb_ep_ops s3c_hsotg_ep_ops
= {
2836 .enable
= s3c_hsotg_ep_enable
,
2837 .disable
= s3c_hsotg_ep_disable
,
2838 .alloc_request
= s3c_hsotg_ep_alloc_request
,
2839 .free_request
= s3c_hsotg_ep_free_request
,
2840 .queue
= s3c_hsotg_ep_queue
,
2841 .dequeue
= s3c_hsotg_ep_dequeue
,
2842 .set_halt
= s3c_hsotg_ep_sethalt
,
2843 /* note, don't believe we have any call for the fifo routines */
2847 * s3c_hsotg_phy_enable - enable platform phy dev
2848 * @hsotg: The driver state
2850 * A wrapper for platform code responsible for controlling
2851 * low-level USB code
2853 static void s3c_hsotg_phy_enable(struct s3c_hsotg
*hsotg
)
2855 struct platform_device
*pdev
= to_platform_device(hsotg
->dev
);
2857 dev_dbg(hsotg
->dev
, "pdev 0x%p\n", pdev
);
2858 if (hsotg
->plat
->phy_init
)
2859 hsotg
->plat
->phy_init(pdev
, hsotg
->plat
->phy_type
);
2863 * s3c_hsotg_phy_disable - disable platform phy dev
2864 * @hsotg: The driver state
2866 * A wrapper for platform code responsible for controlling
2867 * low-level USB code
2869 static void s3c_hsotg_phy_disable(struct s3c_hsotg
*hsotg
)
2871 struct platform_device
*pdev
= to_platform_device(hsotg
->dev
);
2873 if (hsotg
->plat
->phy_exit
)
2874 hsotg
->plat
->phy_exit(pdev
, hsotg
->plat
->phy_type
);
2878 * s3c_hsotg_init - initalize the usb core
2879 * @hsotg: The driver state
2881 static void s3c_hsotg_init(struct s3c_hsotg
*hsotg
)
2883 /* unmask subset of endpoint interrupts */
2885 writel(DIEPMSK_TimeOUTMsk
| DIEPMSK_AHBErrMsk
|
2886 DIEPMSK_EPDisbldMsk
| DIEPMSK_XferComplMsk
,
2887 hsotg
->regs
+ DIEPMSK
);
2889 writel(DOEPMSK_SetupMsk
| DOEPMSK_AHBErrMsk
|
2890 DOEPMSK_EPDisbldMsk
| DOEPMSK_XferComplMsk
,
2891 hsotg
->regs
+ DOEPMSK
);
2893 writel(0, hsotg
->regs
+ DAINTMSK
);
2895 /* Be in disconnected state until gadget is registered */
2896 __orr32(hsotg
->regs
+ DCTL
, DCTL_SftDiscon
);
2899 /* post global nak until we're ready */
2900 writel(DCTL_SGNPInNAK
| DCTL_SGOUTNak
,
2901 hsotg
->regs
+ DCTL
);
2906 dev_dbg(hsotg
->dev
, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
2907 readl(hsotg
->regs
+ GRXFSIZ
),
2908 readl(hsotg
->regs
+ GNPTXFSIZ
));
2910 s3c_hsotg_init_fifo(hsotg
);
2912 /* set the PLL on, remove the HNP/SRP and set the PHY */
2913 writel(GUSBCFG_PHYIf16
| GUSBCFG_TOutCal(7) | (0x5 << 10),
2914 hsotg
->regs
+ GUSBCFG
);
2916 writel(using_dma(hsotg
) ? GAHBCFG_DMAEn
: 0x0,
2917 hsotg
->regs
+ GAHBCFG
);
2921 * s3c_hsotg_udc_start - prepare the udc for work
2922 * @gadget: The usb gadget state
2923 * @driver: The usb gadget driver
2925 * Perform initialization to prepare udc device and driver
2928 static int s3c_hsotg_udc_start(struct usb_gadget
*gadget
,
2929 struct usb_gadget_driver
*driver
)
2931 struct s3c_hsotg
*hsotg
= to_hsotg(gadget
);
2935 printk(KERN_ERR
"%s: called with no device\n", __func__
);
2940 dev_err(hsotg
->dev
, "%s: no driver\n", __func__
);
2944 if (driver
->max_speed
< USB_SPEED_FULL
)
2945 dev_err(hsotg
->dev
, "%s: bad speed\n", __func__
);
2947 if (!driver
->setup
) {
2948 dev_err(hsotg
->dev
, "%s: missing entry points\n", __func__
);
2952 WARN_ON(hsotg
->driver
);
2954 driver
->driver
.bus
= NULL
;
2955 hsotg
->driver
= driver
;
2956 hsotg
->gadget
.dev
.driver
= &driver
->driver
;
2957 hsotg
->gadget
.dev
.dma_mask
= hsotg
->dev
->dma_mask
;
2958 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
2960 ret
= regulator_bulk_enable(ARRAY_SIZE(hsotg
->supplies
),
2963 dev_err(hsotg
->dev
, "failed to enable supplies: %d\n", ret
);
2967 s3c_hsotg_phy_enable(hsotg
);
2969 s3c_hsotg_core_init(hsotg
);
2970 hsotg
->last_rst
= jiffies
;
2971 dev_info(hsotg
->dev
, "bound driver %s\n", driver
->driver
.name
);
2975 hsotg
->driver
= NULL
;
2976 hsotg
->gadget
.dev
.driver
= NULL
;
2981 * s3c_hsotg_udc_stop - stop the udc
2982 * @gadget: The usb gadget state
2983 * @driver: The usb gadget driver
2985 * Stop udc hw block and stay tunned for future transmissions
2987 static int s3c_hsotg_udc_stop(struct usb_gadget
*gadget
,
2988 struct usb_gadget_driver
*driver
)
2990 struct s3c_hsotg
*hsotg
= to_hsotg(gadget
);
2996 if (!driver
|| driver
!= hsotg
->driver
|| !driver
->unbind
)
2999 /* all endpoints should be shutdown */
3000 for (ep
= 0; ep
< hsotg
->num_of_eps
; ep
++)
3001 s3c_hsotg_ep_disable(&hsotg
->eps
[ep
].ep
);
3003 s3c_hsotg_phy_disable(hsotg
);
3004 regulator_bulk_disable(ARRAY_SIZE(hsotg
->supplies
), hsotg
->supplies
);
3006 hsotg
->driver
= NULL
;
3007 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
3008 hsotg
->gadget
.dev
.driver
= NULL
;
3010 dev_info(hsotg
->dev
, "unregistered gadget driver '%s'\n",
3011 driver
->driver
.name
);
3017 * s3c_hsotg_gadget_getframe - read the frame number
3018 * @gadget: The usb gadget state
3020 * Read the {micro} frame number
3022 static int s3c_hsotg_gadget_getframe(struct usb_gadget
*gadget
)
3024 return s3c_hsotg_read_frameno(to_hsotg(gadget
));
3027 static struct usb_gadget_ops s3c_hsotg_gadget_ops
= {
3028 .get_frame
= s3c_hsotg_gadget_getframe
,
3029 .udc_start
= s3c_hsotg_udc_start
,
3030 .udc_stop
= s3c_hsotg_udc_stop
,
3034 * s3c_hsotg_initep - initialise a single endpoint
3035 * @hsotg: The device state.
3036 * @hs_ep: The endpoint to be initialised.
3037 * @epnum: The endpoint number
3039 * Initialise the given endpoint (as part of the probe and device state
3040 * creation) to give to the gadget driver. Setup the endpoint name, any
3041 * direction information and other state that may be required.
3043 static void __devinit
s3c_hsotg_initep(struct s3c_hsotg
*hsotg
,
3044 struct s3c_hsotg_ep
*hs_ep
,
3052 else if ((epnum
% 2) == 0) {
3059 hs_ep
->index
= epnum
;
3061 snprintf(hs_ep
->name
, sizeof(hs_ep
->name
), "ep%d%s", epnum
, dir
);
3063 INIT_LIST_HEAD(&hs_ep
->queue
);
3064 INIT_LIST_HEAD(&hs_ep
->ep
.ep_list
);
3066 /* add to the list of endpoints known by the gadget driver */
3068 list_add_tail(&hs_ep
->ep
.ep_list
, &hsotg
->gadget
.ep_list
);
3070 hs_ep
->parent
= hsotg
;
3071 hs_ep
->ep
.name
= hs_ep
->name
;
3072 hs_ep
->ep
.maxpacket
= epnum
? 512 : EP0_MPS_LIMIT
;
3073 hs_ep
->ep
.ops
= &s3c_hsotg_ep_ops
;
3076 * Read the FIFO size for the Periodic TX FIFO, even if we're
3077 * an OUT endpoint, we may as well do this if in future the
3078 * code is changed to make each endpoint's direction changeable.
3081 ptxfifo
= readl(hsotg
->regs
+ DPTXFSIZn(epnum
));
3082 hs_ep
->fifo_size
= DPTXFSIZn_DPTxFSize_GET(ptxfifo
) * 4;
3085 * if we're using dma, we need to set the next-endpoint pointer
3086 * to be something valid.
3089 if (using_dma(hsotg
)) {
3090 u32 next
= DxEPCTL_NextEp((epnum
+ 1) % 15);
3091 writel(next
, hsotg
->regs
+ DIEPCTL(epnum
));
3092 writel(next
, hsotg
->regs
+ DOEPCTL(epnum
));
3097 * s3c_hsotg_hw_cfg - read HW configuration registers
3098 * @param: The device state
3100 * Read the USB core HW configuration registers
3102 static void s3c_hsotg_hw_cfg(struct s3c_hsotg
*hsotg
)
3105 /* check hardware configuration */
3107 cfg2
= readl(hsotg
->regs
+ 0x48);
3108 hsotg
->num_of_eps
= (cfg2
>> 10) & 0xF;
3110 dev_info(hsotg
->dev
, "EPs:%d\n", hsotg
->num_of_eps
);
3112 cfg4
= readl(hsotg
->regs
+ 0x50);
3113 hsotg
->dedicated_fifos
= (cfg4
>> 25) & 1;
3115 dev_info(hsotg
->dev
, "%s fifos\n",
3116 hsotg
->dedicated_fifos
? "dedicated" : "shared");
3120 * s3c_hsotg_dump - dump state of the udc
3121 * @param: The device state
3123 static void s3c_hsotg_dump(struct s3c_hsotg
*hsotg
)
3126 struct device
*dev
= hsotg
->dev
;
3127 void __iomem
*regs
= hsotg
->regs
;
3131 dev_info(dev
, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
3132 readl(regs
+ DCFG
), readl(regs
+ DCTL
),
3133 readl(regs
+ DIEPMSK
));
3135 dev_info(dev
, "GAHBCFG=0x%08x, 0x44=0x%08x\n",
3136 readl(regs
+ GAHBCFG
), readl(regs
+ 0x44));
3138 dev_info(dev
, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
3139 readl(regs
+ GRXFSIZ
), readl(regs
+ GNPTXFSIZ
));
3141 /* show periodic fifo settings */
3143 for (idx
= 1; idx
<= 15; idx
++) {
3144 val
= readl(regs
+ DPTXFSIZn(idx
));
3145 dev_info(dev
, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx
,
3146 val
>> DPTXFSIZn_DPTxFSize_SHIFT
,
3147 val
& DPTXFSIZn_DPTxFStAddr_MASK
);
3150 for (idx
= 0; idx
< 15; idx
++) {
3152 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx
,
3153 readl(regs
+ DIEPCTL(idx
)),
3154 readl(regs
+ DIEPTSIZ(idx
)),
3155 readl(regs
+ DIEPDMA(idx
)));
3157 val
= readl(regs
+ DOEPCTL(idx
));
3159 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
3160 idx
, readl(regs
+ DOEPCTL(idx
)),
3161 readl(regs
+ DOEPTSIZ(idx
)),
3162 readl(regs
+ DOEPDMA(idx
)));
3166 dev_info(dev
, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
3167 readl(regs
+ DVBUSDIS
), readl(regs
+ DVBUSPULSE
));
3172 * state_show - debugfs: show overall driver and device state.
3173 * @seq: The seq file to write to.
3174 * @v: Unused parameter.
3176 * This debugfs entry shows the overall state of the hardware and
3177 * some general information about each of the endpoints available
3180 static int state_show(struct seq_file
*seq
, void *v
)
3182 struct s3c_hsotg
*hsotg
= seq
->private;
3183 void __iomem
*regs
= hsotg
->regs
;
3186 seq_printf(seq
, "DCFG=0x%08x, DCTL=0x%08x, DSTS=0x%08x\n",
3189 readl(regs
+ DSTS
));
3191 seq_printf(seq
, "DIEPMSK=0x%08x, DOEPMASK=0x%08x\n",
3192 readl(regs
+ DIEPMSK
), readl(regs
+ DOEPMSK
));
3194 seq_printf(seq
, "GINTMSK=0x%08x, GINTSTS=0x%08x\n",
3195 readl(regs
+ GINTMSK
),
3196 readl(regs
+ GINTSTS
));
3198 seq_printf(seq
, "DAINTMSK=0x%08x, DAINT=0x%08x\n",
3199 readl(regs
+ DAINTMSK
),
3200 readl(regs
+ DAINT
));
3202 seq_printf(seq
, "GNPTXSTS=0x%08x, GRXSTSR=%08x\n",
3203 readl(regs
+ GNPTXSTS
),
3204 readl(regs
+ GRXSTSR
));
3206 seq_printf(seq
, "\nEndpoint status:\n");
3208 for (idx
= 0; idx
< 15; idx
++) {
3211 in
= readl(regs
+ DIEPCTL(idx
));
3212 out
= readl(regs
+ DOEPCTL(idx
));
3214 seq_printf(seq
, "ep%d: DIEPCTL=0x%08x, DOEPCTL=0x%08x",
3217 in
= readl(regs
+ DIEPTSIZ(idx
));
3218 out
= readl(regs
+ DOEPTSIZ(idx
));
3220 seq_printf(seq
, ", DIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x",
3223 seq_printf(seq
, "\n");
3229 static int state_open(struct inode
*inode
, struct file
*file
)
3231 return single_open(file
, state_show
, inode
->i_private
);
3234 static const struct file_operations state_fops
= {
3235 .owner
= THIS_MODULE
,
3238 .llseek
= seq_lseek
,
3239 .release
= single_release
,
3243 * fifo_show - debugfs: show the fifo information
3244 * @seq: The seq_file to write data to.
3245 * @v: Unused parameter.
3247 * Show the FIFO information for the overall fifo and all the
3248 * periodic transmission FIFOs.
3250 static int fifo_show(struct seq_file
*seq
, void *v
)
3252 struct s3c_hsotg
*hsotg
= seq
->private;
3253 void __iomem
*regs
= hsotg
->regs
;
3257 seq_printf(seq
, "Non-periodic FIFOs:\n");
3258 seq_printf(seq
, "RXFIFO: Size %d\n", readl(regs
+ GRXFSIZ
));
3260 val
= readl(regs
+ GNPTXFSIZ
);
3261 seq_printf(seq
, "NPTXFIFO: Size %d, Start 0x%08x\n",
3262 val
>> GNPTXFSIZ_NPTxFDep_SHIFT
,
3263 val
& GNPTXFSIZ_NPTxFStAddr_MASK
);
3265 seq_printf(seq
, "\nPeriodic TXFIFOs:\n");
3267 for (idx
= 1; idx
<= 15; idx
++) {
3268 val
= readl(regs
+ DPTXFSIZn(idx
));
3270 seq_printf(seq
, "\tDPTXFIFO%2d: Size %d, Start 0x%08x\n", idx
,
3271 val
>> DPTXFSIZn_DPTxFSize_SHIFT
,
3272 val
& DPTXFSIZn_DPTxFStAddr_MASK
);
3278 static int fifo_open(struct inode
*inode
, struct file
*file
)
3280 return single_open(file
, fifo_show
, inode
->i_private
);
3283 static const struct file_operations fifo_fops
= {
3284 .owner
= THIS_MODULE
,
3287 .llseek
= seq_lseek
,
3288 .release
= single_release
,
3292 static const char *decode_direction(int is_in
)
3294 return is_in
? "in" : "out";
3298 * ep_show - debugfs: show the state of an endpoint.
3299 * @seq: The seq_file to write data to.
3300 * @v: Unused parameter.
3302 * This debugfs entry shows the state of the given endpoint (one is
3303 * registered for each available).
3305 static int ep_show(struct seq_file
*seq
, void *v
)
3307 struct s3c_hsotg_ep
*ep
= seq
->private;
3308 struct s3c_hsotg
*hsotg
= ep
->parent
;
3309 struct s3c_hsotg_req
*req
;
3310 void __iomem
*regs
= hsotg
->regs
;
3311 int index
= ep
->index
;
3312 int show_limit
= 15;
3313 unsigned long flags
;
3315 seq_printf(seq
, "Endpoint index %d, named %s, dir %s:\n",
3316 ep
->index
, ep
->ep
.name
, decode_direction(ep
->dir_in
));
3318 /* first show the register state */
3320 seq_printf(seq
, "\tDIEPCTL=0x%08x, DOEPCTL=0x%08x\n",
3321 readl(regs
+ DIEPCTL(index
)),
3322 readl(regs
+ DOEPCTL(index
)));
3324 seq_printf(seq
, "\tDIEPDMA=0x%08x, DOEPDMA=0x%08x\n",
3325 readl(regs
+ DIEPDMA(index
)),
3326 readl(regs
+ DOEPDMA(index
)));
3328 seq_printf(seq
, "\tDIEPINT=0x%08x, DOEPINT=0x%08x\n",
3329 readl(regs
+ DIEPINT(index
)),
3330 readl(regs
+ DOEPINT(index
)));
3332 seq_printf(seq
, "\tDIEPTSIZ=0x%08x, DOEPTSIZ=0x%08x\n",
3333 readl(regs
+ DIEPTSIZ(index
)),
3334 readl(regs
+ DOEPTSIZ(index
)));
3336 seq_printf(seq
, "\n");
3337 seq_printf(seq
, "mps %d\n", ep
->ep
.maxpacket
);
3338 seq_printf(seq
, "total_data=%ld\n", ep
->total_data
);
3340 seq_printf(seq
, "request list (%p,%p):\n",
3341 ep
->queue
.next
, ep
->queue
.prev
);
3343 spin_lock_irqsave(&hsotg
->lock
, flags
);
3345 list_for_each_entry(req
, &ep
->queue
, queue
) {
3346 if (--show_limit
< 0) {
3347 seq_printf(seq
, "not showing more requests...\n");
3351 seq_printf(seq
, "%c req %p: %d bytes @%p, ",
3352 req
== ep
->req
? '*' : ' ',
3353 req
, req
->req
.length
, req
->req
.buf
);
3354 seq_printf(seq
, "%d done, res %d\n",
3355 req
->req
.actual
, req
->req
.status
);
3358 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3363 static int ep_open(struct inode
*inode
, struct file
*file
)
3365 return single_open(file
, ep_show
, inode
->i_private
);
3368 static const struct file_operations ep_fops
= {
3369 .owner
= THIS_MODULE
,
3372 .llseek
= seq_lseek
,
3373 .release
= single_release
,
3377 * s3c_hsotg_create_debug - create debugfs directory and files
3378 * @hsotg: The driver state
3380 * Create the debugfs files to allow the user to get information
3381 * about the state of the system. The directory name is created
3382 * with the same name as the device itself, in case we end up
3383 * with multiple blocks in future systems.
3385 static void __devinit
s3c_hsotg_create_debug(struct s3c_hsotg
*hsotg
)
3387 struct dentry
*root
;
3390 root
= debugfs_create_dir(dev_name(hsotg
->dev
), NULL
);
3391 hsotg
->debug_root
= root
;
3393 dev_err(hsotg
->dev
, "cannot create debug root\n");
3397 /* create general state file */
3399 hsotg
->debug_file
= debugfs_create_file("state", 0444, root
,
3400 hsotg
, &state_fops
);
3402 if (IS_ERR(hsotg
->debug_file
))
3403 dev_err(hsotg
->dev
, "%s: failed to create state\n", __func__
);
3405 hsotg
->debug_fifo
= debugfs_create_file("fifo", 0444, root
,
3408 if (IS_ERR(hsotg
->debug_fifo
))
3409 dev_err(hsotg
->dev
, "%s: failed to create fifo\n", __func__
);
3411 /* create one file for each endpoint */
3413 for (epidx
= 0; epidx
< hsotg
->num_of_eps
; epidx
++) {
3414 struct s3c_hsotg_ep
*ep
= &hsotg
->eps
[epidx
];
3416 ep
->debugfs
= debugfs_create_file(ep
->name
, 0444,
3417 root
, ep
, &ep_fops
);
3419 if (IS_ERR(ep
->debugfs
))
3420 dev_err(hsotg
->dev
, "failed to create %s debug file\n",
3426 * s3c_hsotg_delete_debug - cleanup debugfs entries
3427 * @hsotg: The driver state
3429 * Cleanup (remove) the debugfs files for use on module exit.
3431 static void __devexit
s3c_hsotg_delete_debug(struct s3c_hsotg
*hsotg
)
3435 for (epidx
= 0; epidx
< hsotg
->num_of_eps
; epidx
++) {
3436 struct s3c_hsotg_ep
*ep
= &hsotg
->eps
[epidx
];
3437 debugfs_remove(ep
->debugfs
);
3440 debugfs_remove(hsotg
->debug_file
);
3441 debugfs_remove(hsotg
->debug_fifo
);
3442 debugfs_remove(hsotg
->debug_root
);
3446 * s3c_hsotg_release - release callback for hsotg device
3447 * @dev: Device to for which release is called
3449 static void s3c_hsotg_release(struct device
*dev
)
3451 struct s3c_hsotg
*hsotg
= dev_get_drvdata(dev
);
3457 * s3c_hsotg_probe - probe function for hsotg driver
3458 * @pdev: The platform information for the driver
3461 static int __devinit
s3c_hsotg_probe(struct platform_device
*pdev
)
3463 struct s3c_hsotg_plat
*plat
= pdev
->dev
.platform_data
;
3464 struct device
*dev
= &pdev
->dev
;
3465 struct s3c_hsotg_ep
*eps
;
3466 struct s3c_hsotg
*hsotg
;
3467 struct resource
*res
;
3472 plat
= pdev
->dev
.platform_data
;
3474 dev_err(&pdev
->dev
, "no platform data defined\n");
3478 hsotg
= devm_kzalloc(&pdev
->dev
, sizeof(struct s3c_hsotg
), GFP_KERNEL
);
3480 dev_err(dev
, "cannot get memory\n");
3487 hsotg
->clk
= clk_get(&pdev
->dev
, "otg");
3488 if (IS_ERR(hsotg
->clk
)) {
3489 dev_err(dev
, "cannot get otg clock\n");
3490 return PTR_ERR(hsotg
->clk
);
3493 platform_set_drvdata(pdev
, hsotg
);
3495 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
3497 hsotg
->regs
= devm_request_and_ioremap(&pdev
->dev
, res
);
3499 dev_err(dev
, "cannot map registers\n");
3504 ret
= platform_get_irq(pdev
, 0);
3506 dev_err(dev
, "cannot find IRQ\n");
3510 spin_lock_init(&hsotg
->lock
);
3514 ret
= devm_request_irq(&pdev
->dev
, hsotg
->irq
, s3c_hsotg_irq
, 0,
3515 dev_name(dev
), hsotg
);
3517 dev_err(dev
, "cannot claim IRQ\n");
3521 dev_info(dev
, "regs %p, irq %d\n", hsotg
->regs
, hsotg
->irq
);
3523 device_initialize(&hsotg
->gadget
.dev
);
3525 dev_set_name(&hsotg
->gadget
.dev
, "gadget");
3527 hsotg
->gadget
.max_speed
= USB_SPEED_HIGH
;
3528 hsotg
->gadget
.ops
= &s3c_hsotg_gadget_ops
;
3529 hsotg
->gadget
.name
= dev_name(dev
);
3531 hsotg
->gadget
.dev
.parent
= dev
;
3532 hsotg
->gadget
.dev
.dma_mask
= dev
->dma_mask
;
3533 hsotg
->gadget
.dev
.release
= s3c_hsotg_release
;
3535 /* reset the system */
3537 clk_prepare_enable(hsotg
->clk
);
3541 for (i
= 0; i
< ARRAY_SIZE(hsotg
->supplies
); i
++)
3542 hsotg
->supplies
[i
].supply
= s3c_hsotg_supply_names
[i
];
3544 ret
= regulator_bulk_get(dev
, ARRAY_SIZE(hsotg
->supplies
),
3547 dev_err(dev
, "failed to request supplies: %d\n", ret
);
3551 ret
= regulator_bulk_enable(ARRAY_SIZE(hsotg
->supplies
),
3555 dev_err(hsotg
->dev
, "failed to enable supplies: %d\n", ret
);
3559 /* usb phy enable */
3560 s3c_hsotg_phy_enable(hsotg
);
3562 s3c_hsotg_corereset(hsotg
);
3563 s3c_hsotg_init(hsotg
);
3564 s3c_hsotg_hw_cfg(hsotg
);
3566 /* hsotg->num_of_eps holds number of EPs other than ep0 */
3568 if (hsotg
->num_of_eps
== 0) {
3569 dev_err(dev
, "wrong number of EPs (zero)\n");
3573 eps
= kcalloc(hsotg
->num_of_eps
+ 1, sizeof(struct s3c_hsotg_ep
),
3576 dev_err(dev
, "cannot get memory\n");
3582 /* setup endpoint information */
3584 INIT_LIST_HEAD(&hsotg
->gadget
.ep_list
);
3585 hsotg
->gadget
.ep0
= &hsotg
->eps
[0].ep
;
3587 /* allocate EP0 request */
3589 hsotg
->ctrl_req
= s3c_hsotg_ep_alloc_request(&hsotg
->eps
[0].ep
,
3591 if (!hsotg
->ctrl_req
) {
3592 dev_err(dev
, "failed to allocate ctrl req\n");
3596 /* initialise the endpoints now the core has been initialised */
3597 for (epnum
= 0; epnum
< hsotg
->num_of_eps
; epnum
++)
3598 s3c_hsotg_initep(hsotg
, &hsotg
->eps
[epnum
], epnum
);
3600 /* disable power and clock */
3602 ret
= regulator_bulk_disable(ARRAY_SIZE(hsotg
->supplies
),
3605 dev_err(hsotg
->dev
, "failed to disable supplies: %d\n", ret
);
3609 s3c_hsotg_phy_disable(hsotg
);
3611 ret
= device_add(&hsotg
->gadget
.dev
);
3613 put_device(&hsotg
->gadget
.dev
);
3617 ret
= usb_add_gadget_udc(&pdev
->dev
, &hsotg
->gadget
);
3621 s3c_hsotg_create_debug(hsotg
);
3623 s3c_hsotg_dump(hsotg
);
3630 s3c_hsotg_phy_disable(hsotg
);
3631 regulator_bulk_free(ARRAY_SIZE(hsotg
->supplies
), hsotg
->supplies
);
3634 clk_disable_unprepare(hsotg
->clk
);
3635 clk_put(hsotg
->clk
);
3641 * s3c_hsotg_remove - remove function for hsotg driver
3642 * @pdev: The platform information for the driver
3644 static int __devexit
s3c_hsotg_remove(struct platform_device
*pdev
)
3646 struct s3c_hsotg
*hsotg
= platform_get_drvdata(pdev
);
3648 usb_del_gadget_udc(&hsotg
->gadget
);
3650 s3c_hsotg_delete_debug(hsotg
);
3652 if (hsotg
->driver
) {
3653 /* should have been done already by driver model core */
3654 usb_gadget_unregister_driver(hsotg
->driver
);
3657 s3c_hsotg_phy_disable(hsotg
);
3658 regulator_bulk_free(ARRAY_SIZE(hsotg
->supplies
), hsotg
->supplies
);
3660 clk_disable_unprepare(hsotg
->clk
);
3661 clk_put(hsotg
->clk
);
3663 device_unregister(&hsotg
->gadget
.dev
);
3668 #define s3c_hsotg_suspend NULL
3669 #define s3c_hsotg_resume NULL
3672 static struct platform_driver s3c_hsotg_driver
= {
3674 .name
= "s3c-hsotg",
3675 .owner
= THIS_MODULE
,
3677 .probe
= s3c_hsotg_probe
,
3678 .remove
= __devexit_p(s3c_hsotg_remove
),
3679 .suspend
= s3c_hsotg_suspend
,
3680 .resume
= s3c_hsotg_resume
,
3683 module_platform_driver(s3c_hsotg_driver
);
3685 MODULE_DESCRIPTION("Samsung S3C USB High-speed/OtG device");
3686 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
3687 MODULE_LICENSE("GPL");
3688 MODULE_ALIAS("platform:s3c-hsotg");