2 * This file contains code to reset and initialize USB host controllers.
3 * Some of it includes work-arounds for PCI hardware and BIOS quirks.
4 * It may need to run early during booting -- before USB would normally
5 * initialize -- to ensure that Linux doesn't use any legacy modes.
7 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
11 #include <linux/types.h>
12 #include <linux/kernel.h>
13 #include <linux/pci.h>
14 #include <linux/delay.h>
15 #include <linux/export.h>
16 #include <linux/acpi.h>
17 #include <linux/dmi.h>
18 #include "pci-quirks.h"
19 #include "xhci-ext-caps.h"
22 #define UHCI_USBLEGSUP 0xc0 /* legacy support */
23 #define UHCI_USBCMD 0 /* command register */
24 #define UHCI_USBINTR 4 /* interrupt register */
25 #define UHCI_USBLEGSUP_RWC 0x8f00 /* the R/WC bits */
26 #define UHCI_USBLEGSUP_RO 0x5040 /* R/O and reserved bits */
27 #define UHCI_USBCMD_RUN 0x0001 /* RUN/STOP bit */
28 #define UHCI_USBCMD_HCRESET 0x0002 /* Host Controller reset */
29 #define UHCI_USBCMD_EGSM 0x0008 /* Global Suspend Mode */
30 #define UHCI_USBCMD_CONFIGURE 0x0040 /* Config Flag */
31 #define UHCI_USBINTR_RESUME 0x0002 /* Resume interrupt enable */
33 #define OHCI_CONTROL 0x04
34 #define OHCI_CMDSTATUS 0x08
35 #define OHCI_INTRSTATUS 0x0c
36 #define OHCI_INTRENABLE 0x10
37 #define OHCI_INTRDISABLE 0x14
38 #define OHCI_FMINTERVAL 0x34
39 #define OHCI_HCFS (3 << 6) /* hc functional state */
40 #define OHCI_HCR (1 << 0) /* host controller reset */
41 #define OHCI_OCR (1 << 3) /* ownership change request */
42 #define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
43 #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
44 #define OHCI_INTR_OC (1 << 30) /* ownership change */
46 #define EHCI_HCC_PARAMS 0x08 /* extended capabilities */
47 #define EHCI_USBCMD 0 /* command register */
48 #define EHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */
49 #define EHCI_USBSTS 4 /* status register */
50 #define EHCI_USBSTS_HALTED (1 << 12) /* HCHalted bit */
51 #define EHCI_USBINTR 8 /* interrupt register */
52 #define EHCI_CONFIGFLAG 0x40 /* configured flag register */
53 #define EHCI_USBLEGSUP 0 /* legacy support register */
54 #define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */
55 #define EHCI_USBLEGSUP_OS (1 << 24) /* OS semaphore */
56 #define EHCI_USBLEGCTLSTS 4 /* legacy control/status */
57 #define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */
60 #define AB_REG_BAR_LOW 0xe0
61 #define AB_REG_BAR_HIGH 0xe1
62 #define AB_REG_BAR_SB700 0xf0
63 #define AB_INDX(addr) ((addr) + 0x00)
64 #define AB_DATA(addr) ((addr) + 0x04)
68 #define NB_PCIE_INDX_ADDR 0xe0
69 #define NB_PCIE_INDX_DATA 0xe4
70 #define PCIE_P_CNTL 0x10040
71 #define BIF_NB 0x10002
72 #define NB_PIF0_PWRDOWN_0 0x01100012
73 #define NB_PIF0_PWRDOWN_1 0x01100013
75 #define USB_INTEL_XUSB2PR 0xD0
76 #define USB_INTEL_USB2PRM 0xD4
77 #define USB_INTEL_USB3_PSSEN 0xD8
78 #define USB_INTEL_USB3PRM 0xDC
80 /* ASMEDIA quirk use */
81 #define ASMT_DATA_WRITE0_REG 0xF8
82 #define ASMT_DATA_WRITE1_REG 0xFC
83 #define ASMT_CONTROL_REG 0xE0
84 #define ASMT_CONTROL_WRITE_BIT 0x02
85 #define ASMT_WRITEREG_CMD 0x10423
86 #define ASMT_FLOWCTL_ADDR 0xFA30
87 #define ASMT_FLOWCTL_DATA 0xBA
88 #define ASMT_PSEUDO_DATA 0
91 * amd_chipset_gen values represent AMD different chipset generations
93 enum amd_chipset_gen
{
104 struct amd_chipset_type
{
105 enum amd_chipset_gen gen
;
109 static struct amd_chipset_info
{
110 struct pci_dev
*nb_dev
;
111 struct pci_dev
*smbus_dev
;
113 struct amd_chipset_type sb_type
;
119 static DEFINE_SPINLOCK(amd_lock
);
122 * amd_chipset_sb_type_init - initialize amd chipset southbridge type
124 * AMD FCH/SB generation and revision is identified by SMBus controller
125 * vendor, device and revision IDs.
127 * Returns: 1 if it is an AMD chipset, 0 otherwise.
129 static int amd_chipset_sb_type_init(struct amd_chipset_info
*pinfo
)
132 pinfo
->sb_type
.gen
= AMD_CHIPSET_UNKNOWN
;
134 pinfo
->smbus_dev
= pci_get_device(PCI_VENDOR_ID_ATI
,
135 PCI_DEVICE_ID_ATI_SBX00_SMBUS
, NULL
);
136 if (pinfo
->smbus_dev
) {
137 rev
= pinfo
->smbus_dev
->revision
;
138 if (rev
>= 0x10 && rev
<= 0x1f)
139 pinfo
->sb_type
.gen
= AMD_CHIPSET_SB600
;
140 else if (rev
>= 0x30 && rev
<= 0x3f)
141 pinfo
->sb_type
.gen
= AMD_CHIPSET_SB700
;
142 else if (rev
>= 0x40 && rev
<= 0x4f)
143 pinfo
->sb_type
.gen
= AMD_CHIPSET_SB800
;
145 pinfo
->smbus_dev
= pci_get_device(PCI_VENDOR_ID_AMD
,
146 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS
, NULL
);
148 if (!pinfo
->smbus_dev
) {
149 pinfo
->sb_type
.gen
= NOT_AMD_CHIPSET
;
153 rev
= pinfo
->smbus_dev
->revision
;
154 if (rev
>= 0x11 && rev
<= 0x14)
155 pinfo
->sb_type
.gen
= AMD_CHIPSET_HUDSON2
;
156 else if (rev
>= 0x15 && rev
<= 0x18)
157 pinfo
->sb_type
.gen
= AMD_CHIPSET_BOLTON
;
158 else if (rev
>= 0x39 && rev
<= 0x3a)
159 pinfo
->sb_type
.gen
= AMD_CHIPSET_YANGTZE
;
162 pinfo
->sb_type
.rev
= rev
;
166 void sb800_prefetch(struct device
*dev
, int on
)
169 struct pci_dev
*pdev
= to_pci_dev(dev
);
171 pci_read_config_word(pdev
, 0x50, &misc
);
173 pci_write_config_word(pdev
, 0x50, misc
& 0xfcff);
175 pci_write_config_word(pdev
, 0x50, misc
| 0x0300);
177 EXPORT_SYMBOL_GPL(sb800_prefetch
);
179 int usb_amd_find_chipset_info(void)
182 struct amd_chipset_info info
;
185 spin_lock_irqsave(&amd_lock
, flags
);
187 /* probe only once */
188 if (amd_chipset
.probe_count
> 0) {
189 amd_chipset
.probe_count
++;
190 spin_unlock_irqrestore(&amd_lock
, flags
);
191 return amd_chipset
.probe_result
;
193 memset(&info
, 0, sizeof(info
));
194 spin_unlock_irqrestore(&amd_lock
, flags
);
196 if (!amd_chipset_sb_type_init(&info
)) {
201 /* Below chipset generations needn't enable AMD PLL quirk */
202 if (info
.sb_type
.gen
== AMD_CHIPSET_UNKNOWN
||
203 info
.sb_type
.gen
== AMD_CHIPSET_SB600
||
204 info
.sb_type
.gen
== AMD_CHIPSET_YANGTZE
||
205 (info
.sb_type
.gen
== AMD_CHIPSET_SB700
&&
206 info
.sb_type
.rev
> 0x3b)) {
207 if (info
.smbus_dev
) {
208 pci_dev_put(info
.smbus_dev
);
209 info
.smbus_dev
= NULL
;
215 info
.nb_dev
= pci_get_device(PCI_VENDOR_ID_AMD
, 0x9601, NULL
);
219 info
.nb_dev
= pci_get_device(PCI_VENDOR_ID_AMD
, 0x1510, NULL
);
223 info
.nb_dev
= pci_get_device(PCI_VENDOR_ID_AMD
,
230 ret
= info
.probe_result
= 1;
231 printk(KERN_DEBUG
"QUIRK: Enable AMD PLL fix\n");
235 spin_lock_irqsave(&amd_lock
, flags
);
236 if (amd_chipset
.probe_count
> 0) {
237 /* race - someone else was faster - drop devices */
239 /* Mark that we where here */
240 amd_chipset
.probe_count
++;
241 ret
= amd_chipset
.probe_result
;
243 spin_unlock_irqrestore(&amd_lock
, flags
);
245 pci_dev_put(info
.nb_dev
);
246 pci_dev_put(info
.smbus_dev
);
249 /* no race - commit the result */
252 spin_unlock_irqrestore(&amd_lock
, flags
);
257 EXPORT_SYMBOL_GPL(usb_amd_find_chipset_info
);
259 int usb_hcd_amd_remote_wakeup_quirk(struct pci_dev
*pdev
)
261 /* Make sure amd chipset type has already been initialized */
262 usb_amd_find_chipset_info();
263 if (amd_chipset
.sb_type
.gen
!= AMD_CHIPSET_YANGTZE
)
266 dev_dbg(&pdev
->dev
, "QUIRK: Enable AMD remote wakeup fix\n");
269 EXPORT_SYMBOL_GPL(usb_hcd_amd_remote_wakeup_quirk
);
271 bool usb_amd_hang_symptom_quirk(void)
275 usb_amd_find_chipset_info();
276 rev
= amd_chipset
.sb_type
.rev
;
277 /* SB600 and old version of SB700 have hang symptom bug */
278 return amd_chipset
.sb_type
.gen
== AMD_CHIPSET_SB600
||
279 (amd_chipset
.sb_type
.gen
== AMD_CHIPSET_SB700
&&
280 rev
>= 0x3a && rev
<= 0x3b);
282 EXPORT_SYMBOL_GPL(usb_amd_hang_symptom_quirk
);
284 bool usb_amd_prefetch_quirk(void)
286 usb_amd_find_chipset_info();
287 /* SB800 needs pre-fetch fix */
288 return amd_chipset
.sb_type
.gen
== AMD_CHIPSET_SB800
;
290 EXPORT_SYMBOL_GPL(usb_amd_prefetch_quirk
);
293 * The hardware normally enables the A-link power management feature, which
294 * lets the system lower the power consumption in idle states.
296 * This USB quirk prevents the link going into that lower power state
297 * during isochronous transfers.
299 * Without this quirk, isochronous stream on OHCI/EHCI/xHCI controllers of
300 * some AMD platforms may stutter or have breaks occasionally.
302 static void usb_amd_quirk_pll(int disable
)
304 u32 addr
, addr_low
, addr_high
, val
;
305 u32 bit
= disable
? 0 : 1;
308 spin_lock_irqsave(&amd_lock
, flags
);
311 amd_chipset
.isoc_reqs
++;
312 if (amd_chipset
.isoc_reqs
> 1) {
313 spin_unlock_irqrestore(&amd_lock
, flags
);
317 amd_chipset
.isoc_reqs
--;
318 if (amd_chipset
.isoc_reqs
> 0) {
319 spin_unlock_irqrestore(&amd_lock
, flags
);
324 if (amd_chipset
.sb_type
.gen
== AMD_CHIPSET_SB800
||
325 amd_chipset
.sb_type
.gen
== AMD_CHIPSET_HUDSON2
||
326 amd_chipset
.sb_type
.gen
== AMD_CHIPSET_BOLTON
) {
327 outb_p(AB_REG_BAR_LOW
, 0xcd6);
328 addr_low
= inb_p(0xcd7);
329 outb_p(AB_REG_BAR_HIGH
, 0xcd6);
330 addr_high
= inb_p(0xcd7);
331 addr
= addr_high
<< 8 | addr_low
;
333 outl_p(0x30, AB_INDX(addr
));
334 outl_p(0x40, AB_DATA(addr
));
335 outl_p(0x34, AB_INDX(addr
));
336 val
= inl_p(AB_DATA(addr
));
337 } else if (amd_chipset
.sb_type
.gen
== AMD_CHIPSET_SB700
&&
338 amd_chipset
.sb_type
.rev
<= 0x3b) {
339 pci_read_config_dword(amd_chipset
.smbus_dev
,
340 AB_REG_BAR_SB700
, &addr
);
341 outl(AX_INDXC
, AB_INDX(addr
));
342 outl(0x40, AB_DATA(addr
));
343 outl(AX_DATAC
, AB_INDX(addr
));
344 val
= inl(AB_DATA(addr
));
346 spin_unlock_irqrestore(&amd_lock
, flags
);
352 val
|= (1 << 4) | (1 << 9);
355 val
&= ~((1 << 4) | (1 << 9));
357 outl_p(val
, AB_DATA(addr
));
359 if (!amd_chipset
.nb_dev
) {
360 spin_unlock_irqrestore(&amd_lock
, flags
);
364 if (amd_chipset
.nb_type
== 1 || amd_chipset
.nb_type
== 3) {
366 pci_write_config_dword(amd_chipset
.nb_dev
,
367 NB_PCIE_INDX_ADDR
, addr
);
368 pci_read_config_dword(amd_chipset
.nb_dev
,
369 NB_PCIE_INDX_DATA
, &val
);
371 val
&= ~(1 | (1 << 3) | (1 << 4) | (1 << 9) | (1 << 12));
372 val
|= bit
| (bit
<< 3) | (bit
<< 12);
373 val
|= ((!bit
) << 4) | ((!bit
) << 9);
374 pci_write_config_dword(amd_chipset
.nb_dev
,
375 NB_PCIE_INDX_DATA
, val
);
378 pci_write_config_dword(amd_chipset
.nb_dev
,
379 NB_PCIE_INDX_ADDR
, addr
);
380 pci_read_config_dword(amd_chipset
.nb_dev
,
381 NB_PCIE_INDX_DATA
, &val
);
385 pci_write_config_dword(amd_chipset
.nb_dev
,
386 NB_PCIE_INDX_DATA
, val
);
387 } else if (amd_chipset
.nb_type
== 2) {
388 addr
= NB_PIF0_PWRDOWN_0
;
389 pci_write_config_dword(amd_chipset
.nb_dev
,
390 NB_PCIE_INDX_ADDR
, addr
);
391 pci_read_config_dword(amd_chipset
.nb_dev
,
392 NB_PCIE_INDX_DATA
, &val
);
398 pci_write_config_dword(amd_chipset
.nb_dev
,
399 NB_PCIE_INDX_DATA
, val
);
401 addr
= NB_PIF0_PWRDOWN_1
;
402 pci_write_config_dword(amd_chipset
.nb_dev
,
403 NB_PCIE_INDX_ADDR
, addr
);
404 pci_read_config_dword(amd_chipset
.nb_dev
,
405 NB_PCIE_INDX_DATA
, &val
);
411 pci_write_config_dword(amd_chipset
.nb_dev
,
412 NB_PCIE_INDX_DATA
, val
);
415 spin_unlock_irqrestore(&amd_lock
, flags
);
419 void usb_amd_quirk_pll_disable(void)
421 usb_amd_quirk_pll(1);
423 EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_disable
);
425 static int usb_asmedia_wait_write(struct pci_dev
*pdev
)
427 unsigned long retry_count
;
430 for (retry_count
= 1000; retry_count
> 0; --retry_count
) {
432 pci_read_config_byte(pdev
, ASMT_CONTROL_REG
, &value
);
435 dev_err(&pdev
->dev
, "%s: check_ready ERROR", __func__
);
439 if ((value
& ASMT_CONTROL_WRITE_BIT
) == 0)
442 usleep_range(40, 60);
445 dev_warn(&pdev
->dev
, "%s: check_write_ready timeout", __func__
);
449 void usb_asmedia_modifyflowcontrol(struct pci_dev
*pdev
)
451 if (usb_asmedia_wait_write(pdev
) != 0)
454 /* send command and address to device */
455 pci_write_config_dword(pdev
, ASMT_DATA_WRITE0_REG
, ASMT_WRITEREG_CMD
);
456 pci_write_config_dword(pdev
, ASMT_DATA_WRITE1_REG
, ASMT_FLOWCTL_ADDR
);
457 pci_write_config_byte(pdev
, ASMT_CONTROL_REG
, ASMT_CONTROL_WRITE_BIT
);
459 if (usb_asmedia_wait_write(pdev
) != 0)
462 /* send data to device */
463 pci_write_config_dword(pdev
, ASMT_DATA_WRITE0_REG
, ASMT_FLOWCTL_DATA
);
464 pci_write_config_dword(pdev
, ASMT_DATA_WRITE1_REG
, ASMT_PSEUDO_DATA
);
465 pci_write_config_byte(pdev
, ASMT_CONTROL_REG
, ASMT_CONTROL_WRITE_BIT
);
467 EXPORT_SYMBOL_GPL(usb_asmedia_modifyflowcontrol
);
469 void usb_amd_quirk_pll_enable(void)
471 usb_amd_quirk_pll(0);
473 EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_enable
);
475 void usb_amd_dev_put(void)
477 struct pci_dev
*nb
, *smbus
;
480 spin_lock_irqsave(&amd_lock
, flags
);
482 amd_chipset
.probe_count
--;
483 if (amd_chipset
.probe_count
> 0) {
484 spin_unlock_irqrestore(&amd_lock
, flags
);
488 /* save them to pci_dev_put outside of spinlock */
489 nb
= amd_chipset
.nb_dev
;
490 smbus
= amd_chipset
.smbus_dev
;
492 amd_chipset
.nb_dev
= NULL
;
493 amd_chipset
.smbus_dev
= NULL
;
494 amd_chipset
.nb_type
= 0;
495 memset(&amd_chipset
.sb_type
, 0, sizeof(amd_chipset
.sb_type
));
496 amd_chipset
.isoc_reqs
= 0;
497 amd_chipset
.probe_result
= 0;
499 spin_unlock_irqrestore(&amd_lock
, flags
);
504 EXPORT_SYMBOL_GPL(usb_amd_dev_put
);
507 * Make sure the controller is completely inactive, unable to
508 * generate interrupts or do DMA.
510 void uhci_reset_hc(struct pci_dev
*pdev
, unsigned long base
)
512 /* Turn off PIRQ enable and SMI enable. (This also turns off the
513 * BIOS's USB Legacy Support.) Turn off all the R/WC bits too.
515 pci_write_config_word(pdev
, UHCI_USBLEGSUP
, UHCI_USBLEGSUP_RWC
);
517 /* Reset the HC - this will force us to get a
518 * new notification of any already connected
519 * ports due to the virtual disconnect that it
522 outw(UHCI_USBCMD_HCRESET
, base
+ UHCI_USBCMD
);
525 if (inw(base
+ UHCI_USBCMD
) & UHCI_USBCMD_HCRESET
)
526 dev_warn(&pdev
->dev
, "HCRESET not completed yet!\n");
528 /* Just to be safe, disable interrupt requests and
529 * make sure the controller is stopped.
531 outw(0, base
+ UHCI_USBINTR
);
532 outw(0, base
+ UHCI_USBCMD
);
534 EXPORT_SYMBOL_GPL(uhci_reset_hc
);
537 * Initialize a controller that was newly discovered or has just been
538 * resumed. In either case we can't be sure of its previous state.
540 * Returns: 1 if the controller was reset, 0 otherwise.
542 int uhci_check_and_reset_hc(struct pci_dev
*pdev
, unsigned long base
)
545 unsigned int cmd
, intr
;
548 * When restarting a suspended controller, we expect all the
549 * settings to be the same as we left them:
551 * PIRQ and SMI disabled, no R/W bits set in USBLEGSUP;
552 * Controller is stopped and configured with EGSM set;
553 * No interrupts enabled except possibly Resume Detect.
555 * If any of these conditions are violated we do a complete reset.
557 pci_read_config_word(pdev
, UHCI_USBLEGSUP
, &legsup
);
558 if (legsup
& ~(UHCI_USBLEGSUP_RO
| UHCI_USBLEGSUP_RWC
)) {
559 dev_dbg(&pdev
->dev
, "%s: legsup = 0x%04x\n",
564 cmd
= inw(base
+ UHCI_USBCMD
);
565 if ((cmd
& UHCI_USBCMD_RUN
) || !(cmd
& UHCI_USBCMD_CONFIGURE
) ||
566 !(cmd
& UHCI_USBCMD_EGSM
)) {
567 dev_dbg(&pdev
->dev
, "%s: cmd = 0x%04x\n",
572 intr
= inw(base
+ UHCI_USBINTR
);
573 if (intr
& (~UHCI_USBINTR_RESUME
)) {
574 dev_dbg(&pdev
->dev
, "%s: intr = 0x%04x\n",
581 dev_dbg(&pdev
->dev
, "Performing full reset\n");
582 uhci_reset_hc(pdev
, base
);
585 EXPORT_SYMBOL_GPL(uhci_check_and_reset_hc
);
587 static inline int io_type_enabled(struct pci_dev
*pdev
, unsigned int mask
)
590 return !pci_read_config_word(pdev
, PCI_COMMAND
, &cmd
) && (cmd
& mask
);
593 #define pio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_IO)
594 #define mmio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_MEMORY)
596 static void quirk_usb_handoff_uhci(struct pci_dev
*pdev
)
598 unsigned long base
= 0;
601 if (!pio_enabled(pdev
))
604 for (i
= 0; i
< PCI_ROM_RESOURCE
; i
++)
605 if ((pci_resource_flags(pdev
, i
) & IORESOURCE_IO
)) {
606 base
= pci_resource_start(pdev
, i
);
611 uhci_check_and_reset_hc(pdev
, base
);
614 static int mmio_resource_enabled(struct pci_dev
*pdev
, int idx
)
616 return pci_resource_start(pdev
, idx
) && mmio_enabled(pdev
);
619 static void quirk_usb_handoff_ohci(struct pci_dev
*pdev
)
624 bool no_fminterval
= false;
627 if (!mmio_resource_enabled(pdev
, 0))
630 base
= pci_ioremap_bar(pdev
, 0);
635 * ULi M5237 OHCI controller locks the whole system when accessing
636 * the OHCI_FMINTERVAL offset.
638 if (pdev
->vendor
== PCI_VENDOR_ID_AL
&& pdev
->device
== 0x5237)
639 no_fminterval
= true;
641 control
= readl(base
+ OHCI_CONTROL
);
643 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
645 #define OHCI_CTRL_MASK (OHCI_CTRL_RWC | OHCI_CTRL_IR)
647 #define OHCI_CTRL_MASK OHCI_CTRL_RWC
649 if (control
& OHCI_CTRL_IR
) {
650 int wait_time
= 500; /* arbitrary; 5 seconds */
651 writel(OHCI_INTR_OC
, base
+ OHCI_INTRENABLE
);
652 writel(OHCI_OCR
, base
+ OHCI_CMDSTATUS
);
653 while (wait_time
> 0 &&
654 readl(base
+ OHCI_CONTROL
) & OHCI_CTRL_IR
) {
660 "OHCI: BIOS handoff failed (BIOS bug?) %08x\n",
661 readl(base
+ OHCI_CONTROL
));
665 /* disable interrupts */
666 writel((u32
) ~0, base
+ OHCI_INTRDISABLE
);
668 /* Reset the USB bus, if the controller isn't already in RESET */
669 if (control
& OHCI_HCFS
) {
670 /* Go into RESET, preserving RWC (and possibly IR) */
671 writel(control
& OHCI_CTRL_MASK
, base
+ OHCI_CONTROL
);
672 readl(base
+ OHCI_CONTROL
);
674 /* drive bus reset for at least 50 ms (7.1.7.5) */
678 /* software reset of the controller, preserving HcFmInterval */
680 fminterval
= readl(base
+ OHCI_FMINTERVAL
);
682 writel(OHCI_HCR
, base
+ OHCI_CMDSTATUS
);
684 /* reset requires max 10 us delay */
685 for (cnt
= 30; cnt
> 0; --cnt
) { /* ... allow extra time */
686 if ((readl(base
+ OHCI_CMDSTATUS
) & OHCI_HCR
) == 0)
692 writel(fminterval
, base
+ OHCI_FMINTERVAL
);
694 /* Now the controller is safely in SUSPEND and nothing can wake it up */
698 static const struct dmi_system_id ehci_dmi_nohandoff_table
[] = {
700 /* Pegatron Lucid (ExoPC) */
702 DMI_MATCH(DMI_BOARD_NAME
, "EXOPG06411"),
703 DMI_MATCH(DMI_BIOS_VERSION
, "Lucid-CE-133"),
707 /* Pegatron Lucid (Ordissimo AIRIS) */
709 DMI_MATCH(DMI_BOARD_NAME
, "M11JB"),
710 DMI_MATCH(DMI_BIOS_VERSION
, "Lucid-"),
714 /* Pegatron Lucid (Ordissimo) */
716 DMI_MATCH(DMI_BOARD_NAME
, "Ordissimo"),
717 DMI_MATCH(DMI_BIOS_VERSION
, "Lucid-"),
723 DMI_MATCH(DMI_BOARD_VENDOR
, "HASEE"),
724 DMI_MATCH(DMI_BOARD_NAME
, "E210"),
725 DMI_MATCH(DMI_BIOS_VERSION
, "6.00"),
731 static void ehci_bios_handoff(struct pci_dev
*pdev
,
732 void __iomem
*op_reg_base
,
735 int try_handoff
= 1, tried_handoff
= 0;
738 * The Pegatron Lucid tablet sporadically waits for 98 seconds trying
739 * the handoff on its unused controller. Skip it.
741 * The HASEE E200 hangs when the semaphore is set (bugzilla #77021).
743 if (pdev
->vendor
== 0x8086 && (pdev
->device
== 0x283a ||
744 pdev
->device
== 0x27cc)) {
745 if (dmi_check_system(ehci_dmi_nohandoff_table
))
749 if (try_handoff
&& (cap
& EHCI_USBLEGSUP_BIOS
)) {
750 dev_dbg(&pdev
->dev
, "EHCI: BIOS handoff\n");
753 /* aleksey_gorelov@phoenix.com reports that some systems need SMI forced on,
754 * but that seems dubious in general (the BIOS left it off intentionally)
755 * and is known to prevent some systems from booting. so we won't do this
756 * unless maybe we can determine when we're on a system that needs SMI forced.
758 /* BIOS workaround (?): be sure the pre-Linux code
761 pci_read_config_dword(pdev
, offset
+ EHCI_USBLEGCTLSTS
, &val
);
762 pci_write_config_dword(pdev
, offset
+ EHCI_USBLEGCTLSTS
,
763 val
| EHCI_USBLEGCTLSTS_SOOE
);
766 /* some systems get upset if this semaphore is
767 * set for any other reason than forcing a BIOS
770 pci_write_config_byte(pdev
, offset
+ 3, 1);
773 /* if boot firmware now owns EHCI, spin till it hands it over. */
776 while ((cap
& EHCI_USBLEGSUP_BIOS
) && (msec
> 0)) {
780 pci_read_config_dword(pdev
, offset
, &cap
);
784 if (cap
& EHCI_USBLEGSUP_BIOS
) {
785 /* well, possibly buggy BIOS... try to shut it down,
786 * and hope nothing goes too wrong
790 "EHCI: BIOS handoff failed (BIOS bug?) %08x\n",
792 pci_write_config_byte(pdev
, offset
+ 2, 0);
795 /* just in case, always disable EHCI SMIs */
796 pci_write_config_dword(pdev
, offset
+ EHCI_USBLEGCTLSTS
, 0);
798 /* If the BIOS ever owned the controller then we can't expect
799 * any power sessions to remain intact.
802 writel(0, op_reg_base
+ EHCI_CONFIGFLAG
);
805 static void quirk_usb_disable_ehci(struct pci_dev
*pdev
)
807 void __iomem
*base
, *op_reg_base
;
808 u32 hcc_params
, cap
, val
;
809 u8 offset
, cap_length
;
810 int wait_time
, count
= 256/4;
812 if (!mmio_resource_enabled(pdev
, 0))
815 base
= pci_ioremap_bar(pdev
, 0);
819 cap_length
= readb(base
);
820 op_reg_base
= base
+ cap_length
;
822 /* EHCI 0.96 and later may have "extended capabilities"
823 * spec section 5.1 explains the bios handoff, e.g. for
824 * booting from USB disk or using a usb keyboard
826 hcc_params
= readl(base
+ EHCI_HCC_PARAMS
);
827 offset
= (hcc_params
>> 8) & 0xff;
828 while (offset
&& --count
) {
829 pci_read_config_dword(pdev
, offset
, &cap
);
831 switch (cap
& 0xff) {
833 ehci_bios_handoff(pdev
, op_reg_base
, cap
, offset
);
835 case 0: /* Illegal reserved cap, set cap=0 so we exit */
836 cap
= 0; /* then fallthrough... */
839 "EHCI: unrecognized capability %02x\n",
842 offset
= (cap
>> 8) & 0xff;
845 dev_printk(KERN_DEBUG
, &pdev
->dev
, "EHCI: capability loop?\n");
848 * halt EHCI & disable its interrupts in any case
850 val
= readl(op_reg_base
+ EHCI_USBSTS
);
851 if ((val
& EHCI_USBSTS_HALTED
) == 0) {
852 val
= readl(op_reg_base
+ EHCI_USBCMD
);
853 val
&= ~EHCI_USBCMD_RUN
;
854 writel(val
, op_reg_base
+ EHCI_USBCMD
);
858 writel(0x3f, op_reg_base
+ EHCI_USBSTS
);
861 val
= readl(op_reg_base
+ EHCI_USBSTS
);
862 if ((val
== ~(u32
)0) || (val
& EHCI_USBSTS_HALTED
)) {
865 } while (wait_time
> 0);
867 writel(0, op_reg_base
+ EHCI_USBINTR
);
868 writel(0x3f, op_reg_base
+ EHCI_USBSTS
);
874 * handshake - spin reading a register until handshake completes
875 * @ptr: address of hc register to be read
876 * @mask: bits to look at in result of read
877 * @done: value of those bits when handshake succeeds
878 * @wait_usec: timeout in microseconds
879 * @delay_usec: delay in microseconds to wait between polling
881 * Polls a register every delay_usec microseconds.
882 * Returns 0 when the mask bits have the value done.
883 * Returns -ETIMEDOUT if this condition is not true after
884 * wait_usec microseconds have passed.
886 static int handshake(void __iomem
*ptr
, u32 mask
, u32 done
,
887 int wait_usec
, int delay_usec
)
897 wait_usec
-= delay_usec
;
898 } while (wait_usec
> 0);
903 * Intel's Panther Point chipset has two host controllers (EHCI and xHCI) that
904 * share some number of ports. These ports can be switched between either
905 * controller. Not all of the ports under the EHCI host controller may be
908 * The ports should be switched over to xHCI before PCI probes for any device
909 * start. This avoids active devices under EHCI being disconnected during the
910 * port switchover, which could cause loss of data on USB storage devices, or
911 * failed boot when the root file system is on a USB mass storage device and is
912 * enumerated under EHCI first.
914 * We write into the xHC's PCI configuration space in some Intel-specific
915 * registers to switch the ports over. The USB 3.0 terminations and the USB
916 * 2.0 data wires are switched separately. We want to enable the SuperSpeed
917 * terminations before switching the USB 2.0 wires over, so that USB 3.0
918 * devices connect at SuperSpeed, rather than at USB 2.0 speeds.
920 void usb_enable_intel_xhci_ports(struct pci_dev
*xhci_pdev
)
923 bool ehci_found
= false;
924 struct pci_dev
*companion
= NULL
;
926 /* Sony VAIO t-series with subsystem device ID 90a8 is not capable of
927 * switching ports from EHCI to xHCI
929 if (xhci_pdev
->subsystem_vendor
== PCI_VENDOR_ID_SONY
&&
930 xhci_pdev
->subsystem_device
== 0x90a8)
933 /* make sure an intel EHCI controller exists */
934 for_each_pci_dev(companion
) {
935 if (companion
->class == PCI_CLASS_SERIAL_USB_EHCI
&&
936 companion
->vendor
== PCI_VENDOR_ID_INTEL
) {
945 /* Don't switchover the ports if the user hasn't compiled the xHCI
946 * driver. Otherwise they will see "dead" USB ports that don't power
949 if (!IS_ENABLED(CONFIG_USB_XHCI_HCD
)) {
950 dev_warn(&xhci_pdev
->dev
,
951 "CONFIG_USB_XHCI_HCD is turned off, defaulting to EHCI.\n");
952 dev_warn(&xhci_pdev
->dev
,
953 "USB 3.0 devices will work at USB 2.0 speeds.\n");
954 usb_disable_xhci_ports(xhci_pdev
);
958 /* Read USB3PRM, the USB 3.0 Port Routing Mask Register
959 * Indicate the ports that can be changed from OS.
961 pci_read_config_dword(xhci_pdev
, USB_INTEL_USB3PRM
,
964 dev_dbg(&xhci_pdev
->dev
, "Configurable ports to enable SuperSpeed: 0x%x\n",
967 /* Write USB3_PSSEN, the USB 3.0 Port SuperSpeed Enable
968 * Register, to turn on SuperSpeed terminations for the
971 pci_write_config_dword(xhci_pdev
, USB_INTEL_USB3_PSSEN
,
974 pci_read_config_dword(xhci_pdev
, USB_INTEL_USB3_PSSEN
,
976 dev_dbg(&xhci_pdev
->dev
,
977 "USB 3.0 ports that are now enabled under xHCI: 0x%x\n",
980 /* Read XUSB2PRM, xHCI USB 2.0 Port Routing Mask Register
981 * Indicate the USB 2.0 ports to be controlled by the xHCI host.
984 pci_read_config_dword(xhci_pdev
, USB_INTEL_USB2PRM
,
987 dev_dbg(&xhci_pdev
->dev
, "Configurable USB 2.0 ports to hand over to xCHI: 0x%x\n",
990 /* Write XUSB2PR, the xHC USB 2.0 Port Routing Register, to
991 * switch the USB 2.0 power and data lines over to the xHCI
994 pci_write_config_dword(xhci_pdev
, USB_INTEL_XUSB2PR
,
997 pci_read_config_dword(xhci_pdev
, USB_INTEL_XUSB2PR
,
999 dev_dbg(&xhci_pdev
->dev
,
1000 "USB 2.0 ports that are now switched over to xHCI: 0x%x\n",
1003 EXPORT_SYMBOL_GPL(usb_enable_intel_xhci_ports
);
1005 void usb_disable_xhci_ports(struct pci_dev
*xhci_pdev
)
1007 pci_write_config_dword(xhci_pdev
, USB_INTEL_USB3_PSSEN
, 0x0);
1008 pci_write_config_dword(xhci_pdev
, USB_INTEL_XUSB2PR
, 0x0);
1010 EXPORT_SYMBOL_GPL(usb_disable_xhci_ports
);
1013 * PCI Quirks for xHCI.
1015 * Takes care of the handoff between the Pre-OS (i.e. BIOS) and the OS.
1016 * It signals to the BIOS that the OS wants control of the host controller,
1017 * and then waits 5 seconds for the BIOS to hand over control.
1018 * If we timeout, assume the BIOS is broken and take control anyway.
1020 static void quirk_usb_handoff_xhci(struct pci_dev
*pdev
)
1024 void __iomem
*op_reg_base
;
1027 int len
= pci_resource_len(pdev
, 0);
1029 if (!mmio_resource_enabled(pdev
, 0))
1032 base
= ioremap_nocache(pci_resource_start(pdev
, 0), len
);
1037 * Find the Legacy Support Capability register -
1038 * this is optional for xHCI host controllers.
1040 ext_cap_offset
= xhci_find_next_ext_cap(base
, 0, XHCI_EXT_CAPS_LEGACY
);
1042 if (!ext_cap_offset
)
1045 if ((ext_cap_offset
+ sizeof(val
)) > len
) {
1046 /* We're reading garbage from the controller */
1047 dev_warn(&pdev
->dev
, "xHCI controller failing to respond");
1050 val
= readl(base
+ ext_cap_offset
);
1052 /* Auto handoff never worked for these devices. Force it and continue */
1053 if ((pdev
->vendor
== PCI_VENDOR_ID_TI
&& pdev
->device
== 0x8241) ||
1054 (pdev
->vendor
== PCI_VENDOR_ID_RENESAS
1055 && pdev
->device
== 0x0014)) {
1056 val
= (val
| XHCI_HC_OS_OWNED
) & ~XHCI_HC_BIOS_OWNED
;
1057 writel(val
, base
+ ext_cap_offset
);
1060 /* If the BIOS owns the HC, signal that the OS wants it, and wait */
1061 if (val
& XHCI_HC_BIOS_OWNED
) {
1062 writel(val
| XHCI_HC_OS_OWNED
, base
+ ext_cap_offset
);
1064 /* Wait for 5 seconds with 10 microsecond polling interval */
1065 timeout
= handshake(base
+ ext_cap_offset
, XHCI_HC_BIOS_OWNED
,
1068 /* Assume a buggy BIOS and take HC ownership anyway */
1070 dev_warn(&pdev
->dev
,
1071 "xHCI BIOS handoff failed (BIOS bug ?) %08x\n",
1073 writel(val
& ~XHCI_HC_BIOS_OWNED
, base
+ ext_cap_offset
);
1077 val
= readl(base
+ ext_cap_offset
+ XHCI_LEGACY_CONTROL_OFFSET
);
1078 /* Mask off (turn off) any enabled SMIs */
1079 val
&= XHCI_LEGACY_DISABLE_SMI
;
1080 /* Mask all SMI events bits, RW1C */
1081 val
|= XHCI_LEGACY_SMI_EVENTS
;
1082 /* Disable any BIOS SMIs and clear all SMI events*/
1083 writel(val
, base
+ ext_cap_offset
+ XHCI_LEGACY_CONTROL_OFFSET
);
1086 if (pdev
->vendor
== PCI_VENDOR_ID_INTEL
)
1087 usb_enable_intel_xhci_ports(pdev
);
1089 op_reg_base
= base
+ XHCI_HC_LENGTH(readl(base
));
1091 /* Wait for the host controller to be ready before writing any
1092 * operational or runtime registers. Wait 5 seconds and no more.
1094 timeout
= handshake(op_reg_base
+ XHCI_STS_OFFSET
, XHCI_STS_CNR
, 0,
1096 /* Assume a buggy HC and start HC initialization anyway */
1098 val
= readl(op_reg_base
+ XHCI_STS_OFFSET
);
1099 dev_warn(&pdev
->dev
,
1100 "xHCI HW not ready after 5 sec (HC bug?) status = 0x%x\n",
1104 /* Send the halt and disable interrupts command */
1105 val
= readl(op_reg_base
+ XHCI_CMD_OFFSET
);
1106 val
&= ~(XHCI_CMD_RUN
| XHCI_IRQS
);
1107 writel(val
, op_reg_base
+ XHCI_CMD_OFFSET
);
1109 /* Wait for the HC to halt - poll every 125 usec (one microframe). */
1110 timeout
= handshake(op_reg_base
+ XHCI_STS_OFFSET
, XHCI_STS_HALT
, 1,
1111 XHCI_MAX_HALT_USEC
, 125);
1113 val
= readl(op_reg_base
+ XHCI_STS_OFFSET
);
1114 dev_warn(&pdev
->dev
,
1115 "xHCI HW did not halt within %d usec status = 0x%x\n",
1116 XHCI_MAX_HALT_USEC
, val
);
1123 static void quirk_usb_early_handoff(struct pci_dev
*pdev
)
1125 /* Skip Netlogic mips SoC's internal PCI USB controller.
1126 * This device does not need/support EHCI/OHCI handoff
1128 if (pdev
->vendor
== 0x184e) /* vendor Netlogic */
1130 if (pdev
->class != PCI_CLASS_SERIAL_USB_UHCI
&&
1131 pdev
->class != PCI_CLASS_SERIAL_USB_OHCI
&&
1132 pdev
->class != PCI_CLASS_SERIAL_USB_EHCI
&&
1133 pdev
->class != PCI_CLASS_SERIAL_USB_XHCI
)
1136 if (pci_enable_device(pdev
) < 0) {
1137 dev_warn(&pdev
->dev
,
1138 "Can't enable PCI device, BIOS handoff failed.\n");
1141 if (pdev
->class == PCI_CLASS_SERIAL_USB_UHCI
)
1142 quirk_usb_handoff_uhci(pdev
);
1143 else if (pdev
->class == PCI_CLASS_SERIAL_USB_OHCI
)
1144 quirk_usb_handoff_ohci(pdev
);
1145 else if (pdev
->class == PCI_CLASS_SERIAL_USB_EHCI
)
1146 quirk_usb_disable_ehci(pdev
);
1147 else if (pdev
->class == PCI_CLASS_SERIAL_USB_XHCI
)
1148 quirk_usb_handoff_xhci(pdev
);
1149 pci_disable_device(pdev
);
1151 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID
, PCI_ANY_ID
,
1152 PCI_CLASS_SERIAL_USB
, 8, quirk_usb_early_handoff
);