2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/usb.h>
24 #include <linux/pci.h>
25 #include <linux/slab.h>
26 #include <linux/dmapool.h>
27 #include <linux/dma-mapping.h>
30 #include "xhci-trace.h"
33 * Allocates a generic ring segment from the ring pool, sets the dma address,
34 * initializes the segment to zero, and sets the private next pointer to NULL.
37 * "All components of all Command and Transfer TRBs shall be initialized to '0'"
39 static struct xhci_segment
*xhci_segment_alloc(struct xhci_hcd
*xhci
,
40 unsigned int cycle_state
,
41 unsigned int max_packet
,
44 struct xhci_segment
*seg
;
48 seg
= kzalloc(sizeof *seg
, flags
);
52 seg
->trbs
= dma_pool_zalloc(xhci
->segment_pool
, flags
, &dma
);
59 seg
->bounce_buf
= kzalloc(max_packet
, flags
| GFP_DMA
);
60 if (!seg
->bounce_buf
) {
61 dma_pool_free(xhci
->segment_pool
, seg
->trbs
, dma
);
66 /* If the cycle state is 0, set the cycle bit to 1 for all the TRBs */
67 if (cycle_state
== 0) {
68 for (i
= 0; i
< TRBS_PER_SEGMENT
; i
++)
69 seg
->trbs
[i
].link
.control
|= cpu_to_le32(TRB_CYCLE
);
77 static void xhci_segment_free(struct xhci_hcd
*xhci
, struct xhci_segment
*seg
)
80 dma_pool_free(xhci
->segment_pool
, seg
->trbs
, seg
->dma
);
83 kfree(seg
->bounce_buf
);
87 static void xhci_free_segments_for_ring(struct xhci_hcd
*xhci
,
88 struct xhci_segment
*first
)
90 struct xhci_segment
*seg
;
93 while (seg
!= first
) {
94 struct xhci_segment
*next
= seg
->next
;
95 xhci_segment_free(xhci
, seg
);
98 xhci_segment_free(xhci
, first
);
102 * Make the prev segment point to the next segment.
104 * Change the last TRB in the prev segment to be a Link TRB which points to the
105 * DMA address of the next segment. The caller needs to set any Link TRB
106 * related flags, such as End TRB, Toggle Cycle, and no snoop.
108 static void xhci_link_segments(struct xhci_hcd
*xhci
, struct xhci_segment
*prev
,
109 struct xhci_segment
*next
, enum xhci_ring_type type
)
116 if (type
!= TYPE_EVENT
) {
117 prev
->trbs
[TRBS_PER_SEGMENT
-1].link
.segment_ptr
=
118 cpu_to_le64(next
->dma
);
120 /* Set the last TRB in the segment to have a TRB type ID of Link TRB */
121 val
= le32_to_cpu(prev
->trbs
[TRBS_PER_SEGMENT
-1].link
.control
);
122 val
&= ~TRB_TYPE_BITMASK
;
123 val
|= TRB_TYPE(TRB_LINK
);
124 /* Always set the chain bit with 0.95 hardware */
125 /* Set chain bit for isoc rings on AMD 0.96 host */
126 if (xhci_link_trb_quirk(xhci
) ||
127 (type
== TYPE_ISOC
&&
128 (xhci
->quirks
& XHCI_AMD_0x96_HOST
)))
130 prev
->trbs
[TRBS_PER_SEGMENT
-1].link
.control
= cpu_to_le32(val
);
135 * Link the ring to the new segments.
136 * Set Toggle Cycle for the new ring if needed.
138 static void xhci_link_rings(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
139 struct xhci_segment
*first
, struct xhci_segment
*last
,
140 unsigned int num_segs
)
142 struct xhci_segment
*next
;
144 if (!ring
|| !first
|| !last
)
147 next
= ring
->enq_seg
->next
;
148 xhci_link_segments(xhci
, ring
->enq_seg
, first
, ring
->type
);
149 xhci_link_segments(xhci
, last
, next
, ring
->type
);
150 ring
->num_segs
+= num_segs
;
151 ring
->num_trbs_free
+= (TRBS_PER_SEGMENT
- 1) * num_segs
;
153 if (ring
->type
!= TYPE_EVENT
&& ring
->enq_seg
== ring
->last_seg
) {
154 ring
->last_seg
->trbs
[TRBS_PER_SEGMENT
-1].link
.control
155 &= ~cpu_to_le32(LINK_TOGGLE
);
156 last
->trbs
[TRBS_PER_SEGMENT
-1].link
.control
157 |= cpu_to_le32(LINK_TOGGLE
);
158 ring
->last_seg
= last
;
163 * We need a radix tree for mapping physical addresses of TRBs to which stream
164 * ID they belong to. We need to do this because the host controller won't tell
165 * us which stream ring the TRB came from. We could store the stream ID in an
166 * event data TRB, but that doesn't help us for the cancellation case, since the
167 * endpoint may stop before it reaches that event data TRB.
169 * The radix tree maps the upper portion of the TRB DMA address to a ring
170 * segment that has the same upper portion of DMA addresses. For example, say I
171 * have segments of size 1KB, that are always 1KB aligned. A segment may
172 * start at 0x10c91000 and end at 0x10c913f0. If I use the upper 10 bits, the
173 * key to the stream ID is 0x43244. I can use the DMA address of the TRB to
174 * pass the radix tree a key to get the right stream ID:
176 * 0x10c90fff >> 10 = 0x43243
177 * 0x10c912c0 >> 10 = 0x43244
178 * 0x10c91400 >> 10 = 0x43245
180 * Obviously, only those TRBs with DMA addresses that are within the segment
181 * will make the radix tree return the stream ID for that ring.
183 * Caveats for the radix tree:
185 * The radix tree uses an unsigned long as a key pair. On 32-bit systems, an
186 * unsigned long will be 32-bits; on a 64-bit system an unsigned long will be
187 * 64-bits. Since we only request 32-bit DMA addresses, we can use that as the
188 * key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit
189 * PCI DMA addresses on a 64-bit system). There might be a problem on 32-bit
190 * extended systems (where the DMA address can be bigger than 32-bits),
191 * if we allow the PCI dma mask to be bigger than 32-bits. So don't do that.
193 static int xhci_insert_segment_mapping(struct radix_tree_root
*trb_address_map
,
194 struct xhci_ring
*ring
,
195 struct xhci_segment
*seg
,
201 key
= (unsigned long)(seg
->dma
>> TRB_SEGMENT_SHIFT
);
202 /* Skip any segments that were already added. */
203 if (radix_tree_lookup(trb_address_map
, key
))
206 ret
= radix_tree_maybe_preload(mem_flags
);
209 ret
= radix_tree_insert(trb_address_map
,
211 radix_tree_preload_end();
215 static void xhci_remove_segment_mapping(struct radix_tree_root
*trb_address_map
,
216 struct xhci_segment
*seg
)
220 key
= (unsigned long)(seg
->dma
>> TRB_SEGMENT_SHIFT
);
221 if (radix_tree_lookup(trb_address_map
, key
))
222 radix_tree_delete(trb_address_map
, key
);
225 static int xhci_update_stream_segment_mapping(
226 struct radix_tree_root
*trb_address_map
,
227 struct xhci_ring
*ring
,
228 struct xhci_segment
*first_seg
,
229 struct xhci_segment
*last_seg
,
232 struct xhci_segment
*seg
;
233 struct xhci_segment
*failed_seg
;
236 if (WARN_ON_ONCE(trb_address_map
== NULL
))
241 ret
= xhci_insert_segment_mapping(trb_address_map
,
242 ring
, seg
, mem_flags
);
248 } while (seg
!= first_seg
);
256 xhci_remove_segment_mapping(trb_address_map
, seg
);
257 if (seg
== failed_seg
)
260 } while (seg
!= first_seg
);
265 static void xhci_remove_stream_mapping(struct xhci_ring
*ring
)
267 struct xhci_segment
*seg
;
269 if (WARN_ON_ONCE(ring
->trb_address_map
== NULL
))
272 seg
= ring
->first_seg
;
274 xhci_remove_segment_mapping(ring
->trb_address_map
, seg
);
276 } while (seg
!= ring
->first_seg
);
279 static int xhci_update_stream_mapping(struct xhci_ring
*ring
, gfp_t mem_flags
)
281 return xhci_update_stream_segment_mapping(ring
->trb_address_map
, ring
,
282 ring
->first_seg
, ring
->last_seg
, mem_flags
);
285 /* XXX: Do we need the hcd structure in all these functions? */
286 void xhci_ring_free(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
)
291 if (ring
->first_seg
) {
292 if (ring
->type
== TYPE_STREAM
)
293 xhci_remove_stream_mapping(ring
);
294 xhci_free_segments_for_ring(xhci
, ring
->first_seg
);
300 static void xhci_initialize_ring_info(struct xhci_ring
*ring
,
301 unsigned int cycle_state
)
303 /* The ring is empty, so the enqueue pointer == dequeue pointer */
304 ring
->enqueue
= ring
->first_seg
->trbs
;
305 ring
->enq_seg
= ring
->first_seg
;
306 ring
->dequeue
= ring
->enqueue
;
307 ring
->deq_seg
= ring
->first_seg
;
308 /* The ring is initialized to 0. The producer must write 1 to the cycle
309 * bit to handover ownership of the TRB, so PCS = 1. The consumer must
310 * compare CCS to the cycle bit to check ownership, so CCS = 1.
312 * New rings are initialized with cycle state equal to 1; if we are
313 * handling ring expansion, set the cycle state equal to the old ring.
315 ring
->cycle_state
= cycle_state
;
316 /* Not necessary for new rings, but needed for re-initialized rings */
317 ring
->enq_updates
= 0;
318 ring
->deq_updates
= 0;
321 * Each segment has a link TRB, and leave an extra TRB for SW
324 ring
->num_trbs_free
= ring
->num_segs
* (TRBS_PER_SEGMENT
- 1) - 1;
327 /* Allocate segments and link them for a ring */
328 static int xhci_alloc_segments_for_ring(struct xhci_hcd
*xhci
,
329 struct xhci_segment
**first
, struct xhci_segment
**last
,
330 unsigned int num_segs
, unsigned int cycle_state
,
331 enum xhci_ring_type type
, unsigned int max_packet
, gfp_t flags
)
333 struct xhci_segment
*prev
;
335 prev
= xhci_segment_alloc(xhci
, cycle_state
, max_packet
, flags
);
341 while (num_segs
> 0) {
342 struct xhci_segment
*next
;
344 next
= xhci_segment_alloc(xhci
, cycle_state
, max_packet
, flags
);
349 xhci_segment_free(xhci
, prev
);
354 xhci_link_segments(xhci
, prev
, next
, type
);
359 xhci_link_segments(xhci
, prev
, *first
, type
);
366 * Create a new ring with zero or more segments.
368 * Link each segment together into a ring.
369 * Set the end flag and the cycle toggle bit on the last segment.
370 * See section 4.9.1 and figures 15 and 16.
372 static struct xhci_ring
*xhci_ring_alloc(struct xhci_hcd
*xhci
,
373 unsigned int num_segs
, unsigned int cycle_state
,
374 enum xhci_ring_type type
, unsigned int max_packet
, gfp_t flags
)
376 struct xhci_ring
*ring
;
379 ring
= kzalloc(sizeof *(ring
), flags
);
383 ring
->num_segs
= num_segs
;
384 ring
->bounce_buf_len
= max_packet
;
385 INIT_LIST_HEAD(&ring
->td_list
);
390 ret
= xhci_alloc_segments_for_ring(xhci
, &ring
->first_seg
,
391 &ring
->last_seg
, num_segs
, cycle_state
, type
,
396 /* Only event ring does not use link TRB */
397 if (type
!= TYPE_EVENT
) {
398 /* See section 4.9.2.1 and 6.4.4.1 */
399 ring
->last_seg
->trbs
[TRBS_PER_SEGMENT
- 1].link
.control
|=
400 cpu_to_le32(LINK_TOGGLE
);
402 xhci_initialize_ring_info(ring
, cycle_state
);
410 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd
*xhci
,
411 struct xhci_virt_device
*virt_dev
,
412 unsigned int ep_index
)
416 rings_cached
= virt_dev
->num_rings_cached
;
417 if (rings_cached
< XHCI_MAX_RINGS_CACHED
) {
418 virt_dev
->ring_cache
[rings_cached
] =
419 virt_dev
->eps
[ep_index
].ring
;
420 virt_dev
->num_rings_cached
++;
421 xhci_dbg(xhci
, "Cached old ring, "
422 "%d ring%s cached\n",
423 virt_dev
->num_rings_cached
,
424 (virt_dev
->num_rings_cached
> 1) ? "s" : "");
426 xhci_ring_free(xhci
, virt_dev
->eps
[ep_index
].ring
);
427 xhci_dbg(xhci
, "Ring cache full (%d rings), "
429 virt_dev
->num_rings_cached
);
431 virt_dev
->eps
[ep_index
].ring
= NULL
;
434 /* Zero an endpoint ring (except for link TRBs) and move the enqueue and dequeue
435 * pointers to the beginning of the ring.
437 static void xhci_reinit_cached_ring(struct xhci_hcd
*xhci
,
438 struct xhci_ring
*ring
, unsigned int cycle_state
,
439 enum xhci_ring_type type
)
441 struct xhci_segment
*seg
= ring
->first_seg
;
446 sizeof(union xhci_trb
)*TRBS_PER_SEGMENT
);
447 if (cycle_state
== 0) {
448 for (i
= 0; i
< TRBS_PER_SEGMENT
; i
++)
449 seg
->trbs
[i
].link
.control
|=
450 cpu_to_le32(TRB_CYCLE
);
452 /* All endpoint rings have link TRBs */
453 xhci_link_segments(xhci
, seg
, seg
->next
, type
);
455 } while (seg
!= ring
->first_seg
);
457 xhci_initialize_ring_info(ring
, cycle_state
);
458 /* td list should be empty since all URBs have been cancelled,
459 * but just in case...
461 INIT_LIST_HEAD(&ring
->td_list
);
465 * Expand an existing ring.
466 * Look for a cached ring or allocate a new ring which has same segment numbers
467 * and link the two rings.
469 int xhci_ring_expansion(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
470 unsigned int num_trbs
, gfp_t flags
)
472 struct xhci_segment
*first
;
473 struct xhci_segment
*last
;
474 unsigned int num_segs
;
475 unsigned int num_segs_needed
;
478 num_segs_needed
= (num_trbs
+ (TRBS_PER_SEGMENT
- 1) - 1) /
479 (TRBS_PER_SEGMENT
- 1);
481 /* Allocate number of segments we needed, or double the ring size */
482 num_segs
= ring
->num_segs
> num_segs_needed
?
483 ring
->num_segs
: num_segs_needed
;
485 ret
= xhci_alloc_segments_for_ring(xhci
, &first
, &last
,
486 num_segs
, ring
->cycle_state
, ring
->type
,
487 ring
->bounce_buf_len
, flags
);
491 if (ring
->type
== TYPE_STREAM
)
492 ret
= xhci_update_stream_segment_mapping(ring
->trb_address_map
,
493 ring
, first
, last
, flags
);
495 struct xhci_segment
*next
;
498 xhci_segment_free(xhci
, first
);
506 xhci_link_rings(xhci
, ring
, first
, last
, num_segs
);
507 xhci_dbg_trace(xhci
, trace_xhci_dbg_ring_expansion
,
508 "ring expansion succeed, now has %d segments",
514 #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
516 static struct xhci_container_ctx
*xhci_alloc_container_ctx(struct xhci_hcd
*xhci
,
517 int type
, gfp_t flags
)
519 struct xhci_container_ctx
*ctx
;
521 if ((type
!= XHCI_CTX_TYPE_DEVICE
) && (type
!= XHCI_CTX_TYPE_INPUT
))
524 ctx
= kzalloc(sizeof(*ctx
), flags
);
529 ctx
->size
= HCC_64BYTE_CONTEXT(xhci
->hcc_params
) ? 2048 : 1024;
530 if (type
== XHCI_CTX_TYPE_INPUT
)
531 ctx
->size
+= CTX_SIZE(xhci
->hcc_params
);
533 ctx
->bytes
= dma_pool_zalloc(xhci
->device_pool
, flags
, &ctx
->dma
);
541 static void xhci_free_container_ctx(struct xhci_hcd
*xhci
,
542 struct xhci_container_ctx
*ctx
)
546 dma_pool_free(xhci
->device_pool
, ctx
->bytes
, ctx
->dma
);
550 struct xhci_input_control_ctx
*xhci_get_input_control_ctx(
551 struct xhci_container_ctx
*ctx
)
553 if (ctx
->type
!= XHCI_CTX_TYPE_INPUT
)
556 return (struct xhci_input_control_ctx
*)ctx
->bytes
;
559 struct xhci_slot_ctx
*xhci_get_slot_ctx(struct xhci_hcd
*xhci
,
560 struct xhci_container_ctx
*ctx
)
562 if (ctx
->type
== XHCI_CTX_TYPE_DEVICE
)
563 return (struct xhci_slot_ctx
*)ctx
->bytes
;
565 return (struct xhci_slot_ctx
*)
566 (ctx
->bytes
+ CTX_SIZE(xhci
->hcc_params
));
569 struct xhci_ep_ctx
*xhci_get_ep_ctx(struct xhci_hcd
*xhci
,
570 struct xhci_container_ctx
*ctx
,
571 unsigned int ep_index
)
573 /* increment ep index by offset of start of ep ctx array */
575 if (ctx
->type
== XHCI_CTX_TYPE_INPUT
)
578 return (struct xhci_ep_ctx
*)
579 (ctx
->bytes
+ (ep_index
* CTX_SIZE(xhci
->hcc_params
)));
583 /***************** Streams structures manipulation *************************/
585 static void xhci_free_stream_ctx(struct xhci_hcd
*xhci
,
586 unsigned int num_stream_ctxs
,
587 struct xhci_stream_ctx
*stream_ctx
, dma_addr_t dma
)
589 struct device
*dev
= xhci_to_hcd(xhci
)->self
.controller
;
590 size_t size
= sizeof(struct xhci_stream_ctx
) * num_stream_ctxs
;
592 if (size
> MEDIUM_STREAM_ARRAY_SIZE
)
593 dma_free_coherent(dev
, size
,
595 else if (size
<= SMALL_STREAM_ARRAY_SIZE
)
596 return dma_pool_free(xhci
->small_streams_pool
,
599 return dma_pool_free(xhci
->medium_streams_pool
,
604 * The stream context array for each endpoint with bulk streams enabled can
605 * vary in size, based on:
606 * - how many streams the endpoint supports,
607 * - the maximum primary stream array size the host controller supports,
608 * - and how many streams the device driver asks for.
610 * The stream context array must be a power of 2, and can be as small as
611 * 64 bytes or as large as 1MB.
613 static struct xhci_stream_ctx
*xhci_alloc_stream_ctx(struct xhci_hcd
*xhci
,
614 unsigned int num_stream_ctxs
, dma_addr_t
*dma
,
617 struct device
*dev
= xhci_to_hcd(xhci
)->self
.controller
;
618 size_t size
= sizeof(struct xhci_stream_ctx
) * num_stream_ctxs
;
620 if (size
> MEDIUM_STREAM_ARRAY_SIZE
)
621 return dma_alloc_coherent(dev
, size
,
623 else if (size
<= SMALL_STREAM_ARRAY_SIZE
)
624 return dma_pool_alloc(xhci
->small_streams_pool
,
627 return dma_pool_alloc(xhci
->medium_streams_pool
,
631 struct xhci_ring
*xhci_dma_to_transfer_ring(
632 struct xhci_virt_ep
*ep
,
635 if (ep
->ep_state
& EP_HAS_STREAMS
)
636 return radix_tree_lookup(&ep
->stream_info
->trb_address_map
,
637 address
>> TRB_SEGMENT_SHIFT
);
641 struct xhci_ring
*xhci_stream_id_to_ring(
642 struct xhci_virt_device
*dev
,
643 unsigned int ep_index
,
644 unsigned int stream_id
)
646 struct xhci_virt_ep
*ep
= &dev
->eps
[ep_index
];
650 if (!ep
->stream_info
)
653 if (stream_id
> ep
->stream_info
->num_streams
)
655 return ep
->stream_info
->stream_rings
[stream_id
];
659 * Change an endpoint's internal structure so it supports stream IDs. The
660 * number of requested streams includes stream 0, which cannot be used by device
663 * The number of stream contexts in the stream context array may be bigger than
664 * the number of streams the driver wants to use. This is because the number of
665 * stream context array entries must be a power of two.
667 struct xhci_stream_info
*xhci_alloc_stream_info(struct xhci_hcd
*xhci
,
668 unsigned int num_stream_ctxs
,
669 unsigned int num_streams
,
670 unsigned int max_packet
, gfp_t mem_flags
)
672 struct xhci_stream_info
*stream_info
;
674 struct xhci_ring
*cur_ring
;
678 xhci_dbg(xhci
, "Allocating %u streams and %u "
679 "stream context array entries.\n",
680 num_streams
, num_stream_ctxs
);
681 if (xhci
->cmd_ring_reserved_trbs
== MAX_RSVD_CMD_TRBS
) {
682 xhci_dbg(xhci
, "Command ring has no reserved TRBs available\n");
685 xhci
->cmd_ring_reserved_trbs
++;
687 stream_info
= kzalloc(sizeof(struct xhci_stream_info
), mem_flags
);
691 stream_info
->num_streams
= num_streams
;
692 stream_info
->num_stream_ctxs
= num_stream_ctxs
;
694 /* Initialize the array of virtual pointers to stream rings. */
695 stream_info
->stream_rings
= kzalloc(
696 sizeof(struct xhci_ring
*)*num_streams
,
698 if (!stream_info
->stream_rings
)
701 /* Initialize the array of DMA addresses for stream rings for the HW. */
702 stream_info
->stream_ctx_array
= xhci_alloc_stream_ctx(xhci
,
703 num_stream_ctxs
, &stream_info
->ctx_array_dma
,
705 if (!stream_info
->stream_ctx_array
)
707 memset(stream_info
->stream_ctx_array
, 0,
708 sizeof(struct xhci_stream_ctx
)*num_stream_ctxs
);
710 /* Allocate everything needed to free the stream rings later */
711 stream_info
->free_streams_command
=
712 xhci_alloc_command(xhci
, true, true, mem_flags
);
713 if (!stream_info
->free_streams_command
)
716 INIT_RADIX_TREE(&stream_info
->trb_address_map
, GFP_ATOMIC
);
718 /* Allocate rings for all the streams that the driver will use,
719 * and add their segment DMA addresses to the radix tree.
720 * Stream 0 is reserved.
723 for (cur_stream
= 1; cur_stream
< num_streams
; cur_stream
++) {
724 stream_info
->stream_rings
[cur_stream
] =
725 xhci_ring_alloc(xhci
, 2, 1, TYPE_STREAM
, max_packet
,
727 cur_ring
= stream_info
->stream_rings
[cur_stream
];
730 cur_ring
->stream_id
= cur_stream
;
731 cur_ring
->trb_address_map
= &stream_info
->trb_address_map
;
732 /* Set deq ptr, cycle bit, and stream context type */
733 addr
= cur_ring
->first_seg
->dma
|
734 SCT_FOR_CTX(SCT_PRI_TR
) |
735 cur_ring
->cycle_state
;
736 stream_info
->stream_ctx_array
[cur_stream
].stream_ring
=
738 xhci_dbg(xhci
, "Setting stream %d ring ptr to 0x%08llx\n",
739 cur_stream
, (unsigned long long) addr
);
741 ret
= xhci_update_stream_mapping(cur_ring
, mem_flags
);
743 xhci_ring_free(xhci
, cur_ring
);
744 stream_info
->stream_rings
[cur_stream
] = NULL
;
748 /* Leave the other unused stream ring pointers in the stream context
749 * array initialized to zero. This will cause the xHC to give us an
750 * error if the device asks for a stream ID we don't have setup (if it
751 * was any other way, the host controller would assume the ring is
752 * "empty" and wait forever for data to be queued to that stream ID).
758 for (cur_stream
= 1; cur_stream
< num_streams
; cur_stream
++) {
759 cur_ring
= stream_info
->stream_rings
[cur_stream
];
761 xhci_ring_free(xhci
, cur_ring
);
762 stream_info
->stream_rings
[cur_stream
] = NULL
;
765 xhci_free_command(xhci
, stream_info
->free_streams_command
);
767 kfree(stream_info
->stream_rings
);
771 xhci
->cmd_ring_reserved_trbs
--;
775 * Sets the MaxPStreams field and the Linear Stream Array field.
776 * Sets the dequeue pointer to the stream context array.
778 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd
*xhci
,
779 struct xhci_ep_ctx
*ep_ctx
,
780 struct xhci_stream_info
*stream_info
)
782 u32 max_primary_streams
;
783 /* MaxPStreams is the number of stream context array entries, not the
784 * number we're actually using. Must be in 2^(MaxPstreams + 1) format.
785 * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc.
787 max_primary_streams
= fls(stream_info
->num_stream_ctxs
) - 2;
788 xhci_dbg_trace(xhci
, trace_xhci_dbg_context_change
,
789 "Setting number of stream ctx array entries to %u",
790 1 << (max_primary_streams
+ 1));
791 ep_ctx
->ep_info
&= cpu_to_le32(~EP_MAXPSTREAMS_MASK
);
792 ep_ctx
->ep_info
|= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams
)
794 ep_ctx
->deq
= cpu_to_le64(stream_info
->ctx_array_dma
);
798 * Sets the MaxPStreams field and the Linear Stream Array field to 0.
799 * Reinstalls the "normal" endpoint ring (at its previous dequeue mark,
800 * not at the beginning of the ring).
802 void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx
*ep_ctx
,
803 struct xhci_virt_ep
*ep
)
806 ep_ctx
->ep_info
&= cpu_to_le32(~(EP_MAXPSTREAMS_MASK
| EP_HAS_LSA
));
807 addr
= xhci_trb_virt_to_dma(ep
->ring
->deq_seg
, ep
->ring
->dequeue
);
808 ep_ctx
->deq
= cpu_to_le64(addr
| ep
->ring
->cycle_state
);
811 /* Frees all stream contexts associated with the endpoint,
813 * Caller should fix the endpoint context streams fields.
815 void xhci_free_stream_info(struct xhci_hcd
*xhci
,
816 struct xhci_stream_info
*stream_info
)
819 struct xhci_ring
*cur_ring
;
824 for (cur_stream
= 1; cur_stream
< stream_info
->num_streams
;
826 cur_ring
= stream_info
->stream_rings
[cur_stream
];
828 xhci_ring_free(xhci
, cur_ring
);
829 stream_info
->stream_rings
[cur_stream
] = NULL
;
832 xhci_free_command(xhci
, stream_info
->free_streams_command
);
833 xhci
->cmd_ring_reserved_trbs
--;
834 if (stream_info
->stream_ctx_array
)
835 xhci_free_stream_ctx(xhci
,
836 stream_info
->num_stream_ctxs
,
837 stream_info
->stream_ctx_array
,
838 stream_info
->ctx_array_dma
);
840 kfree(stream_info
->stream_rings
);
845 /***************** Device context manipulation *************************/
847 static void xhci_init_endpoint_timer(struct xhci_hcd
*xhci
,
848 struct xhci_virt_ep
*ep
)
850 setup_timer(&ep
->stop_cmd_timer
, xhci_stop_endpoint_command_watchdog
,
855 static void xhci_free_tt_info(struct xhci_hcd
*xhci
,
856 struct xhci_virt_device
*virt_dev
,
859 struct list_head
*tt_list_head
;
860 struct xhci_tt_bw_info
*tt_info
, *next
;
861 bool slot_found
= false;
863 /* If the device never made it past the Set Address stage,
864 * it may not have the real_port set correctly.
866 if (virt_dev
->real_port
== 0 ||
867 virt_dev
->real_port
> HCS_MAX_PORTS(xhci
->hcs_params1
)) {
868 xhci_dbg(xhci
, "Bad real port.\n");
872 tt_list_head
= &(xhci
->rh_bw
[virt_dev
->real_port
- 1].tts
);
873 list_for_each_entry_safe(tt_info
, next
, tt_list_head
, tt_list
) {
874 /* Multi-TT hubs will have more than one entry */
875 if (tt_info
->slot_id
== slot_id
) {
877 list_del(&tt_info
->tt_list
);
879 } else if (slot_found
) {
885 int xhci_alloc_tt_info(struct xhci_hcd
*xhci
,
886 struct xhci_virt_device
*virt_dev
,
887 struct usb_device
*hdev
,
888 struct usb_tt
*tt
, gfp_t mem_flags
)
890 struct xhci_tt_bw_info
*tt_info
;
891 unsigned int num_ports
;
897 num_ports
= hdev
->maxchild
;
899 for (i
= 0; i
< num_ports
; i
++, tt_info
++) {
900 struct xhci_interval_bw_table
*bw_table
;
902 tt_info
= kzalloc(sizeof(*tt_info
), mem_flags
);
905 INIT_LIST_HEAD(&tt_info
->tt_list
);
906 list_add(&tt_info
->tt_list
,
907 &xhci
->rh_bw
[virt_dev
->real_port
- 1].tts
);
908 tt_info
->slot_id
= virt_dev
->udev
->slot_id
;
910 tt_info
->ttport
= i
+1;
911 bw_table
= &tt_info
->bw_table
;
912 for (j
= 0; j
< XHCI_MAX_INTERVAL
; j
++)
913 INIT_LIST_HEAD(&bw_table
->interval_bw
[j
].endpoints
);
918 xhci_free_tt_info(xhci
, virt_dev
, virt_dev
->udev
->slot_id
);
923 /* All the xhci_tds in the ring's TD list should be freed at this point.
924 * Should be called with xhci->lock held if there is any chance the TT lists
925 * will be manipulated by the configure endpoint, allocate device, or update
926 * hub functions while this function is removing the TT entries from the list.
928 void xhci_free_virt_device(struct xhci_hcd
*xhci
, int slot_id
)
930 struct xhci_virt_device
*dev
;
932 int old_active_eps
= 0;
934 /* Slot ID 0 is reserved */
935 if (slot_id
== 0 || !xhci
->devs
[slot_id
])
938 dev
= xhci
->devs
[slot_id
];
939 xhci
->dcbaa
->dev_context_ptrs
[slot_id
] = 0;
944 old_active_eps
= dev
->tt_info
->active_eps
;
946 for (i
= 0; i
< 31; ++i
) {
947 if (dev
->eps
[i
].ring
)
948 xhci_ring_free(xhci
, dev
->eps
[i
].ring
);
949 if (dev
->eps
[i
].stream_info
)
950 xhci_free_stream_info(xhci
,
951 dev
->eps
[i
].stream_info
);
952 /* Endpoints on the TT/root port lists should have been removed
953 * when usb_disable_device() was called for the device.
954 * We can't drop them anyway, because the udev might have gone
955 * away by this point, and we can't tell what speed it was.
957 if (!list_empty(&dev
->eps
[i
].bw_endpoint_list
))
958 xhci_warn(xhci
, "Slot %u endpoint %u "
959 "not removed from BW list!\n",
962 /* If this is a hub, free the TT(s) from the TT list */
963 xhci_free_tt_info(xhci
, dev
, slot_id
);
964 /* If necessary, update the number of active TTs on this root port */
965 xhci_update_tt_active_eps(xhci
, dev
, old_active_eps
);
967 if (dev
->ring_cache
) {
968 for (i
= 0; i
< dev
->num_rings_cached
; i
++)
969 xhci_ring_free(xhci
, dev
->ring_cache
[i
]);
970 kfree(dev
->ring_cache
);
974 xhci_free_container_ctx(xhci
, dev
->in_ctx
);
976 xhci_free_container_ctx(xhci
, dev
->out_ctx
);
978 kfree(xhci
->devs
[slot_id
]);
979 xhci
->devs
[slot_id
] = NULL
;
982 int xhci_alloc_virt_device(struct xhci_hcd
*xhci
, int slot_id
,
983 struct usb_device
*udev
, gfp_t flags
)
985 struct xhci_virt_device
*dev
;
988 /* Slot ID 0 is reserved */
989 if (slot_id
== 0 || xhci
->devs
[slot_id
]) {
990 xhci_warn(xhci
, "Bad Slot ID %d\n", slot_id
);
994 xhci
->devs
[slot_id
] = kzalloc(sizeof(*xhci
->devs
[slot_id
]), flags
);
995 if (!xhci
->devs
[slot_id
])
997 dev
= xhci
->devs
[slot_id
];
999 /* Allocate the (output) device context that will be used in the HC. */
1000 dev
->out_ctx
= xhci_alloc_container_ctx(xhci
, XHCI_CTX_TYPE_DEVICE
, flags
);
1004 xhci_dbg(xhci
, "Slot %d output ctx = 0x%llx (dma)\n", slot_id
,
1005 (unsigned long long)dev
->out_ctx
->dma
);
1007 /* Allocate the (input) device context for address device command */
1008 dev
->in_ctx
= xhci_alloc_container_ctx(xhci
, XHCI_CTX_TYPE_INPUT
, flags
);
1012 xhci_dbg(xhci
, "Slot %d input ctx = 0x%llx (dma)\n", slot_id
,
1013 (unsigned long long)dev
->in_ctx
->dma
);
1015 /* Initialize the cancellation list and watchdog timers for each ep */
1016 for (i
= 0; i
< 31; i
++) {
1017 xhci_init_endpoint_timer(xhci
, &dev
->eps
[i
]);
1018 INIT_LIST_HEAD(&dev
->eps
[i
].cancelled_td_list
);
1019 INIT_LIST_HEAD(&dev
->eps
[i
].bw_endpoint_list
);
1022 /* Allocate endpoint 0 ring */
1023 dev
->eps
[0].ring
= xhci_ring_alloc(xhci
, 2, 1, TYPE_CTRL
, 0, flags
);
1024 if (!dev
->eps
[0].ring
)
1027 /* Allocate pointers to the ring cache */
1028 dev
->ring_cache
= kzalloc(
1029 sizeof(struct xhci_ring
*)*XHCI_MAX_RINGS_CACHED
,
1031 if (!dev
->ring_cache
)
1033 dev
->num_rings_cached
= 0;
1037 /* Point to output device context in dcbaa. */
1038 xhci
->dcbaa
->dev_context_ptrs
[slot_id
] = cpu_to_le64(dev
->out_ctx
->dma
);
1039 xhci_dbg(xhci
, "Set slot id %d dcbaa entry %p to 0x%llx\n",
1041 &xhci
->dcbaa
->dev_context_ptrs
[slot_id
],
1042 le64_to_cpu(xhci
->dcbaa
->dev_context_ptrs
[slot_id
]));
1046 xhci_free_virt_device(xhci
, slot_id
);
1050 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd
*xhci
,
1051 struct usb_device
*udev
)
1053 struct xhci_virt_device
*virt_dev
;
1054 struct xhci_ep_ctx
*ep0_ctx
;
1055 struct xhci_ring
*ep_ring
;
1057 virt_dev
= xhci
->devs
[udev
->slot_id
];
1058 ep0_ctx
= xhci_get_ep_ctx(xhci
, virt_dev
->in_ctx
, 0);
1059 ep_ring
= virt_dev
->eps
[0].ring
;
1061 * FIXME we don't keep track of the dequeue pointer very well after a
1062 * Set TR dequeue pointer, so we're setting the dequeue pointer of the
1063 * host to our enqueue pointer. This should only be called after a
1064 * configured device has reset, so all control transfers should have
1065 * been completed or cancelled before the reset.
1067 ep0_ctx
->deq
= cpu_to_le64(xhci_trb_virt_to_dma(ep_ring
->enq_seg
,
1069 | ep_ring
->cycle_state
);
1073 * The xHCI roothub may have ports of differing speeds in any order in the port
1074 * status registers. xhci->port_array provides an array of the port speed for
1075 * each offset into the port status registers.
1077 * The xHCI hardware wants to know the roothub port number that the USB device
1078 * is attached to (or the roothub port its ancestor hub is attached to). All we
1079 * know is the index of that port under either the USB 2.0 or the USB 3.0
1080 * roothub, but that doesn't give us the real index into the HW port status
1081 * registers. Call xhci_find_raw_port_number() to get real index.
1083 static u32
xhci_find_real_port_number(struct xhci_hcd
*xhci
,
1084 struct usb_device
*udev
)
1086 struct usb_device
*top_dev
;
1087 struct usb_hcd
*hcd
;
1089 if (udev
->speed
>= USB_SPEED_SUPER
)
1090 hcd
= xhci
->shared_hcd
;
1092 hcd
= xhci
->main_hcd
;
1094 for (top_dev
= udev
; top_dev
->parent
&& top_dev
->parent
->parent
;
1095 top_dev
= top_dev
->parent
)
1096 /* Found device below root hub */;
1098 return xhci_find_raw_port_number(hcd
, top_dev
->portnum
);
1101 /* Setup an xHCI virtual device for a Set Address command */
1102 int xhci_setup_addressable_virt_dev(struct xhci_hcd
*xhci
, struct usb_device
*udev
)
1104 struct xhci_virt_device
*dev
;
1105 struct xhci_ep_ctx
*ep0_ctx
;
1106 struct xhci_slot_ctx
*slot_ctx
;
1109 struct usb_device
*top_dev
;
1111 dev
= xhci
->devs
[udev
->slot_id
];
1112 /* Slot ID 0 is reserved */
1113 if (udev
->slot_id
== 0 || !dev
) {
1114 xhci_warn(xhci
, "Slot ID %d is not assigned to this device\n",
1118 ep0_ctx
= xhci_get_ep_ctx(xhci
, dev
->in_ctx
, 0);
1119 slot_ctx
= xhci_get_slot_ctx(xhci
, dev
->in_ctx
);
1121 /* 3) Only the control endpoint is valid - one endpoint context */
1122 slot_ctx
->dev_info
|= cpu_to_le32(LAST_CTX(1) | udev
->route
);
1123 switch (udev
->speed
) {
1124 case USB_SPEED_SUPER_PLUS
:
1125 slot_ctx
->dev_info
|= cpu_to_le32(SLOT_SPEED_SSP
);
1126 max_packets
= MAX_PACKET(512);
1128 case USB_SPEED_SUPER
:
1129 slot_ctx
->dev_info
|= cpu_to_le32(SLOT_SPEED_SS
);
1130 max_packets
= MAX_PACKET(512);
1132 case USB_SPEED_HIGH
:
1133 slot_ctx
->dev_info
|= cpu_to_le32(SLOT_SPEED_HS
);
1134 max_packets
= MAX_PACKET(64);
1136 /* USB core guesses at a 64-byte max packet first for FS devices */
1137 case USB_SPEED_FULL
:
1138 slot_ctx
->dev_info
|= cpu_to_le32(SLOT_SPEED_FS
);
1139 max_packets
= MAX_PACKET(64);
1142 slot_ctx
->dev_info
|= cpu_to_le32(SLOT_SPEED_LS
);
1143 max_packets
= MAX_PACKET(8);
1145 case USB_SPEED_WIRELESS
:
1146 xhci_dbg(xhci
, "FIXME xHCI doesn't support wireless speeds\n");
1150 /* Speed was set earlier, this shouldn't happen. */
1153 /* Find the root hub port this device is under */
1154 port_num
= xhci_find_real_port_number(xhci
, udev
);
1157 slot_ctx
->dev_info2
|= cpu_to_le32(ROOT_HUB_PORT(port_num
));
1158 /* Set the port number in the virtual_device to the faked port number */
1159 for (top_dev
= udev
; top_dev
->parent
&& top_dev
->parent
->parent
;
1160 top_dev
= top_dev
->parent
)
1161 /* Found device below root hub */;
1162 dev
->fake_port
= top_dev
->portnum
;
1163 dev
->real_port
= port_num
;
1164 xhci_dbg(xhci
, "Set root hub portnum to %d\n", port_num
);
1165 xhci_dbg(xhci
, "Set fake root hub portnum to %d\n", dev
->fake_port
);
1167 /* Find the right bandwidth table that this device will be a part of.
1168 * If this is a full speed device attached directly to a root port (or a
1169 * decendent of one), it counts as a primary bandwidth domain, not a
1170 * secondary bandwidth domain under a TT. An xhci_tt_info structure
1171 * will never be created for the HS root hub.
1173 if (!udev
->tt
|| !udev
->tt
->hub
->parent
) {
1174 dev
->bw_table
= &xhci
->rh_bw
[port_num
- 1].bw_table
;
1176 struct xhci_root_port_bw_info
*rh_bw
;
1177 struct xhci_tt_bw_info
*tt_bw
;
1179 rh_bw
= &xhci
->rh_bw
[port_num
- 1];
1180 /* Find the right TT. */
1181 list_for_each_entry(tt_bw
, &rh_bw
->tts
, tt_list
) {
1182 if (tt_bw
->slot_id
!= udev
->tt
->hub
->slot_id
)
1185 if (!dev
->udev
->tt
->multi
||
1187 tt_bw
->ttport
== dev
->udev
->ttport
)) {
1188 dev
->bw_table
= &tt_bw
->bw_table
;
1189 dev
->tt_info
= tt_bw
;
1194 xhci_warn(xhci
, "WARN: Didn't find a matching TT\n");
1197 /* Is this a LS/FS device under an external HS hub? */
1198 if (udev
->tt
&& udev
->tt
->hub
->parent
) {
1199 slot_ctx
->tt_info
= cpu_to_le32(udev
->tt
->hub
->slot_id
|
1200 (udev
->ttport
<< 8));
1201 if (udev
->tt
->multi
)
1202 slot_ctx
->dev_info
|= cpu_to_le32(DEV_MTT
);
1204 xhci_dbg(xhci
, "udev->tt = %p\n", udev
->tt
);
1205 xhci_dbg(xhci
, "udev->ttport = 0x%x\n", udev
->ttport
);
1207 /* Step 4 - ring already allocated */
1209 ep0_ctx
->ep_info2
= cpu_to_le32(EP_TYPE(CTRL_EP
));
1211 /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
1212 ep0_ctx
->ep_info2
|= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3) |
1215 ep0_ctx
->deq
= cpu_to_le64(dev
->eps
[0].ring
->first_seg
->dma
|
1216 dev
->eps
[0].ring
->cycle_state
);
1218 /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
1224 * Convert interval expressed as 2^(bInterval - 1) == interval into
1225 * straight exponent value 2^n == interval.
1228 static unsigned int xhci_parse_exponent_interval(struct usb_device
*udev
,
1229 struct usb_host_endpoint
*ep
)
1231 unsigned int interval
;
1233 interval
= clamp_val(ep
->desc
.bInterval
, 1, 16) - 1;
1234 if (interval
!= ep
->desc
.bInterval
- 1)
1235 dev_warn(&udev
->dev
,
1236 "ep %#x - rounding interval to %d %sframes\n",
1237 ep
->desc
.bEndpointAddress
,
1239 udev
->speed
== USB_SPEED_FULL
? "" : "micro");
1241 if (udev
->speed
== USB_SPEED_FULL
) {
1243 * Full speed isoc endpoints specify interval in frames,
1244 * not microframes. We are using microframes everywhere,
1245 * so adjust accordingly.
1247 interval
+= 3; /* 1 frame = 2^3 uframes */
1254 * Convert bInterval expressed in microframes (in 1-255 range) to exponent of
1255 * microframes, rounded down to nearest power of 2.
1257 static unsigned int xhci_microframes_to_exponent(struct usb_device
*udev
,
1258 struct usb_host_endpoint
*ep
, unsigned int desc_interval
,
1259 unsigned int min_exponent
, unsigned int max_exponent
)
1261 unsigned int interval
;
1263 interval
= fls(desc_interval
) - 1;
1264 interval
= clamp_val(interval
, min_exponent
, max_exponent
);
1265 if ((1 << interval
) != desc_interval
)
1267 "ep %#x - rounding interval to %d microframes, ep desc says %d microframes\n",
1268 ep
->desc
.bEndpointAddress
,
1275 static unsigned int xhci_parse_microframe_interval(struct usb_device
*udev
,
1276 struct usb_host_endpoint
*ep
)
1278 if (ep
->desc
.bInterval
== 0)
1280 return xhci_microframes_to_exponent(udev
, ep
,
1281 ep
->desc
.bInterval
, 0, 15);
1285 static unsigned int xhci_parse_frame_interval(struct usb_device
*udev
,
1286 struct usb_host_endpoint
*ep
)
1288 return xhci_microframes_to_exponent(udev
, ep
,
1289 ep
->desc
.bInterval
* 8, 3, 10);
1292 /* Return the polling or NAK interval.
1294 * The polling interval is expressed in "microframes". If xHCI's Interval field
1295 * is set to N, it will service the endpoint every 2^(Interval)*125us.
1297 * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
1300 static unsigned int xhci_get_endpoint_interval(struct usb_device
*udev
,
1301 struct usb_host_endpoint
*ep
)
1303 unsigned int interval
= 0;
1305 switch (udev
->speed
) {
1306 case USB_SPEED_HIGH
:
1308 if (usb_endpoint_xfer_control(&ep
->desc
) ||
1309 usb_endpoint_xfer_bulk(&ep
->desc
)) {
1310 interval
= xhci_parse_microframe_interval(udev
, ep
);
1313 /* Fall through - SS and HS isoc/int have same decoding */
1315 case USB_SPEED_SUPER_PLUS
:
1316 case USB_SPEED_SUPER
:
1317 if (usb_endpoint_xfer_int(&ep
->desc
) ||
1318 usb_endpoint_xfer_isoc(&ep
->desc
)) {
1319 interval
= xhci_parse_exponent_interval(udev
, ep
);
1323 case USB_SPEED_FULL
:
1324 if (usb_endpoint_xfer_isoc(&ep
->desc
)) {
1325 interval
= xhci_parse_exponent_interval(udev
, ep
);
1329 * Fall through for interrupt endpoint interval decoding
1330 * since it uses the same rules as low speed interrupt
1335 if (usb_endpoint_xfer_int(&ep
->desc
) ||
1336 usb_endpoint_xfer_isoc(&ep
->desc
)) {
1338 interval
= xhci_parse_frame_interval(udev
, ep
);
1348 /* The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
1349 * High speed endpoint descriptors can define "the number of additional
1350 * transaction opportunities per microframe", but that goes in the Max Burst
1351 * endpoint context field.
1353 static u32
xhci_get_endpoint_mult(struct usb_device
*udev
,
1354 struct usb_host_endpoint
*ep
)
1356 if (udev
->speed
< USB_SPEED_SUPER
||
1357 !usb_endpoint_xfer_isoc(&ep
->desc
))
1359 return ep
->ss_ep_comp
.bmAttributes
;
1362 static u32
xhci_get_endpoint_max_burst(struct usb_device
*udev
,
1363 struct usb_host_endpoint
*ep
)
1365 /* Super speed and Plus have max burst in ep companion desc */
1366 if (udev
->speed
>= USB_SPEED_SUPER
)
1367 return ep
->ss_ep_comp
.bMaxBurst
;
1369 if (udev
->speed
== USB_SPEED_HIGH
&&
1370 (usb_endpoint_xfer_isoc(&ep
->desc
) ||
1371 usb_endpoint_xfer_int(&ep
->desc
)))
1372 return (usb_endpoint_maxp(&ep
->desc
) & 0x1800) >> 11;
1377 static u32
xhci_get_endpoint_type(struct usb_host_endpoint
*ep
)
1381 in
= usb_endpoint_dir_in(&ep
->desc
);
1383 if (usb_endpoint_xfer_control(&ep
->desc
))
1385 if (usb_endpoint_xfer_bulk(&ep
->desc
))
1386 return in
? BULK_IN_EP
: BULK_OUT_EP
;
1387 if (usb_endpoint_xfer_isoc(&ep
->desc
))
1388 return in
? ISOC_IN_EP
: ISOC_OUT_EP
;
1389 if (usb_endpoint_xfer_int(&ep
->desc
))
1390 return in
? INT_IN_EP
: INT_OUT_EP
;
1394 /* Return the maximum endpoint service interval time (ESIT) payload.
1395 * Basically, this is the maxpacket size, multiplied by the burst size
1398 static u32
xhci_get_max_esit_payload(struct usb_device
*udev
,
1399 struct usb_host_endpoint
*ep
)
1404 /* Only applies for interrupt or isochronous endpoints */
1405 if (usb_endpoint_xfer_control(&ep
->desc
) ||
1406 usb_endpoint_xfer_bulk(&ep
->desc
))
1409 /* SuperSpeedPlus Isoc ep sending over 48k per esit */
1410 if ((udev
->speed
>= USB_SPEED_SUPER_PLUS
) &&
1411 USB_SS_SSP_ISOC_COMP(ep
->ss_ep_comp
.bmAttributes
))
1412 return le32_to_cpu(ep
->ssp_isoc_ep_comp
.dwBytesPerInterval
);
1413 /* SuperSpeed or SuperSpeedPlus Isoc ep with less than 48k per esit */
1414 else if (udev
->speed
>= USB_SPEED_SUPER
)
1415 return le16_to_cpu(ep
->ss_ep_comp
.wBytesPerInterval
);
1417 max_packet
= GET_MAX_PACKET(usb_endpoint_maxp(&ep
->desc
));
1418 max_burst
= (usb_endpoint_maxp(&ep
->desc
) & 0x1800) >> 11;
1419 /* A 0 in max burst means 1 transfer per ESIT */
1420 return max_packet
* (max_burst
+ 1);
1423 /* Set up an endpoint with one ring segment. Do not allocate stream rings.
1424 * Drivers will have to call usb_alloc_streams() to do that.
1426 int xhci_endpoint_init(struct xhci_hcd
*xhci
,
1427 struct xhci_virt_device
*virt_dev
,
1428 struct usb_device
*udev
,
1429 struct usb_host_endpoint
*ep
,
1432 unsigned int ep_index
;
1433 struct xhci_ep_ctx
*ep_ctx
;
1434 struct xhci_ring
*ep_ring
;
1435 unsigned int max_packet
;
1436 enum xhci_ring_type ring_type
;
1437 u32 max_esit_payload
;
1439 unsigned int max_burst
;
1440 unsigned int interval
;
1442 unsigned int avg_trb_len
;
1443 unsigned int err_count
= 0;
1445 ep_index
= xhci_get_endpoint_index(&ep
->desc
);
1446 ep_ctx
= xhci_get_ep_ctx(xhci
, virt_dev
->in_ctx
, ep_index
);
1448 endpoint_type
= xhci_get_endpoint_type(ep
);
1452 ring_type
= usb_endpoint_type(&ep
->desc
);
1455 * Get values to fill the endpoint context, mostly from ep descriptor.
1456 * The average TRB buffer lengt for bulk endpoints is unclear as we
1457 * have no clue on scatter gather list entry size. For Isoc and Int,
1458 * set it to max available. See xHCI 1.1 spec 4.14.1.1 for details.
1460 max_esit_payload
= xhci_get_max_esit_payload(udev
, ep
);
1461 interval
= xhci_get_endpoint_interval(udev
, ep
);
1462 mult
= xhci_get_endpoint_mult(udev
, ep
);
1463 max_packet
= GET_MAX_PACKET(usb_endpoint_maxp(&ep
->desc
));
1464 max_burst
= xhci_get_endpoint_max_burst(udev
, ep
);
1465 avg_trb_len
= max_esit_payload
;
1467 /* FIXME dig Mult and streams info out of ep companion desc */
1469 /* Allow 3 retries for everything but isoc, set CErr = 3 */
1470 if (!usb_endpoint_xfer_isoc(&ep
->desc
))
1472 /* Some devices get this wrong */
1473 if (usb_endpoint_xfer_bulk(&ep
->desc
) && udev
->speed
== USB_SPEED_HIGH
)
1475 /* xHCI 1.0 and 1.1 indicates that ctrl ep avg TRB Length should be 8 */
1476 if (usb_endpoint_xfer_control(&ep
->desc
) && xhci
->hci_version
>= 0x100)
1478 /* xhci 1.1 with LEC support doesn't use mult field, use RsvdZ */
1479 if ((xhci
->hci_version
> 0x100) && HCC2_LEC(xhci
->hcc_params2
))
1482 /* Set up the endpoint ring */
1483 virt_dev
->eps
[ep_index
].new_ring
=
1484 xhci_ring_alloc(xhci
, 2, 1, ring_type
, max_packet
, mem_flags
);
1485 if (!virt_dev
->eps
[ep_index
].new_ring
) {
1486 /* Attempt to use the ring cache */
1487 if (virt_dev
->num_rings_cached
== 0)
1489 virt_dev
->num_rings_cached
--;
1490 virt_dev
->eps
[ep_index
].new_ring
=
1491 virt_dev
->ring_cache
[virt_dev
->num_rings_cached
];
1492 virt_dev
->ring_cache
[virt_dev
->num_rings_cached
] = NULL
;
1493 xhci_reinit_cached_ring(xhci
, virt_dev
->eps
[ep_index
].new_ring
,
1496 virt_dev
->eps
[ep_index
].skip
= false;
1497 ep_ring
= virt_dev
->eps
[ep_index
].new_ring
;
1499 /* Fill the endpoint context */
1500 ep_ctx
->ep_info
= cpu_to_le32(EP_MAX_ESIT_PAYLOAD_HI(max_esit_payload
) |
1501 EP_INTERVAL(interval
) |
1503 ep_ctx
->ep_info2
= cpu_to_le32(EP_TYPE(endpoint_type
) |
1504 MAX_PACKET(max_packet
) |
1505 MAX_BURST(max_burst
) |
1506 ERROR_COUNT(err_count
));
1507 ep_ctx
->deq
= cpu_to_le64(ep_ring
->first_seg
->dma
|
1508 ep_ring
->cycle_state
);
1510 ep_ctx
->tx_info
= cpu_to_le32(EP_MAX_ESIT_PAYLOAD_LO(max_esit_payload
) |
1511 EP_AVG_TRB_LENGTH(avg_trb_len
));
1513 /* FIXME Debug endpoint context */
1517 void xhci_endpoint_zero(struct xhci_hcd
*xhci
,
1518 struct xhci_virt_device
*virt_dev
,
1519 struct usb_host_endpoint
*ep
)
1521 unsigned int ep_index
;
1522 struct xhci_ep_ctx
*ep_ctx
;
1524 ep_index
= xhci_get_endpoint_index(&ep
->desc
);
1525 ep_ctx
= xhci_get_ep_ctx(xhci
, virt_dev
->in_ctx
, ep_index
);
1527 ep_ctx
->ep_info
= 0;
1528 ep_ctx
->ep_info2
= 0;
1530 ep_ctx
->tx_info
= 0;
1531 /* Don't free the endpoint ring until the set interface or configuration
1536 void xhci_clear_endpoint_bw_info(struct xhci_bw_info
*bw_info
)
1538 bw_info
->ep_interval
= 0;
1540 bw_info
->num_packets
= 0;
1541 bw_info
->max_packet_size
= 0;
1543 bw_info
->max_esit_payload
= 0;
1546 void xhci_update_bw_info(struct xhci_hcd
*xhci
,
1547 struct xhci_container_ctx
*in_ctx
,
1548 struct xhci_input_control_ctx
*ctrl_ctx
,
1549 struct xhci_virt_device
*virt_dev
)
1551 struct xhci_bw_info
*bw_info
;
1552 struct xhci_ep_ctx
*ep_ctx
;
1553 unsigned int ep_type
;
1556 for (i
= 1; i
< 31; ++i
) {
1557 bw_info
= &virt_dev
->eps
[i
].bw_info
;
1559 /* We can't tell what endpoint type is being dropped, but
1560 * unconditionally clearing the bandwidth info for non-periodic
1561 * endpoints should be harmless because the info will never be
1562 * set in the first place.
1564 if (!EP_IS_ADDED(ctrl_ctx
, i
) && EP_IS_DROPPED(ctrl_ctx
, i
)) {
1565 /* Dropped endpoint */
1566 xhci_clear_endpoint_bw_info(bw_info
);
1570 if (EP_IS_ADDED(ctrl_ctx
, i
)) {
1571 ep_ctx
= xhci_get_ep_ctx(xhci
, in_ctx
, i
);
1572 ep_type
= CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx
->ep_info2
));
1574 /* Ignore non-periodic endpoints */
1575 if (ep_type
!= ISOC_OUT_EP
&& ep_type
!= INT_OUT_EP
&&
1576 ep_type
!= ISOC_IN_EP
&&
1577 ep_type
!= INT_IN_EP
)
1580 /* Added or changed endpoint */
1581 bw_info
->ep_interval
= CTX_TO_EP_INTERVAL(
1582 le32_to_cpu(ep_ctx
->ep_info
));
1583 /* Number of packets and mult are zero-based in the
1584 * input context, but we want one-based for the
1587 bw_info
->mult
= CTX_TO_EP_MULT(
1588 le32_to_cpu(ep_ctx
->ep_info
)) + 1;
1589 bw_info
->num_packets
= CTX_TO_MAX_BURST(
1590 le32_to_cpu(ep_ctx
->ep_info2
)) + 1;
1591 bw_info
->max_packet_size
= MAX_PACKET_DECODED(
1592 le32_to_cpu(ep_ctx
->ep_info2
));
1593 bw_info
->type
= ep_type
;
1594 bw_info
->max_esit_payload
= CTX_TO_MAX_ESIT_PAYLOAD(
1595 le32_to_cpu(ep_ctx
->tx_info
));
1600 /* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
1601 * Useful when you want to change one particular aspect of the endpoint and then
1602 * issue a configure endpoint command.
1604 void xhci_endpoint_copy(struct xhci_hcd
*xhci
,
1605 struct xhci_container_ctx
*in_ctx
,
1606 struct xhci_container_ctx
*out_ctx
,
1607 unsigned int ep_index
)
1609 struct xhci_ep_ctx
*out_ep_ctx
;
1610 struct xhci_ep_ctx
*in_ep_ctx
;
1612 out_ep_ctx
= xhci_get_ep_ctx(xhci
, out_ctx
, ep_index
);
1613 in_ep_ctx
= xhci_get_ep_ctx(xhci
, in_ctx
, ep_index
);
1615 in_ep_ctx
->ep_info
= out_ep_ctx
->ep_info
;
1616 in_ep_ctx
->ep_info2
= out_ep_ctx
->ep_info2
;
1617 in_ep_ctx
->deq
= out_ep_ctx
->deq
;
1618 in_ep_ctx
->tx_info
= out_ep_ctx
->tx_info
;
1621 /* Copy output xhci_slot_ctx to the input xhci_slot_ctx.
1622 * Useful when you want to change one particular aspect of the endpoint and then
1623 * issue a configure endpoint command. Only the context entries field matters,
1624 * but we'll copy the whole thing anyway.
1626 void xhci_slot_copy(struct xhci_hcd
*xhci
,
1627 struct xhci_container_ctx
*in_ctx
,
1628 struct xhci_container_ctx
*out_ctx
)
1630 struct xhci_slot_ctx
*in_slot_ctx
;
1631 struct xhci_slot_ctx
*out_slot_ctx
;
1633 in_slot_ctx
= xhci_get_slot_ctx(xhci
, in_ctx
);
1634 out_slot_ctx
= xhci_get_slot_ctx(xhci
, out_ctx
);
1636 in_slot_ctx
->dev_info
= out_slot_ctx
->dev_info
;
1637 in_slot_ctx
->dev_info2
= out_slot_ctx
->dev_info2
;
1638 in_slot_ctx
->tt_info
= out_slot_ctx
->tt_info
;
1639 in_slot_ctx
->dev_state
= out_slot_ctx
->dev_state
;
1642 /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
1643 static int scratchpad_alloc(struct xhci_hcd
*xhci
, gfp_t flags
)
1646 struct device
*dev
= xhci_to_hcd(xhci
)->self
.controller
;
1647 int num_sp
= HCS_MAX_SCRATCHPAD(xhci
->hcs_params2
);
1649 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
1650 "Allocating %d scratchpad buffers", num_sp
);
1655 xhci
->scratchpad
= kzalloc(sizeof(*xhci
->scratchpad
), flags
);
1656 if (!xhci
->scratchpad
)
1659 xhci
->scratchpad
->sp_array
= dma_alloc_coherent(dev
,
1660 num_sp
* sizeof(u64
),
1661 &xhci
->scratchpad
->sp_dma
, flags
);
1662 if (!xhci
->scratchpad
->sp_array
)
1665 xhci
->scratchpad
->sp_buffers
= kzalloc(sizeof(void *) * num_sp
, flags
);
1666 if (!xhci
->scratchpad
->sp_buffers
)
1669 xhci
->scratchpad
->sp_dma_buffers
=
1670 kzalloc(sizeof(dma_addr_t
) * num_sp
, flags
);
1672 if (!xhci
->scratchpad
->sp_dma_buffers
)
1675 xhci
->dcbaa
->dev_context_ptrs
[0] = cpu_to_le64(xhci
->scratchpad
->sp_dma
);
1676 for (i
= 0; i
< num_sp
; i
++) {
1678 void *buf
= dma_alloc_coherent(dev
, xhci
->page_size
, &dma
,
1683 xhci
->scratchpad
->sp_array
[i
] = dma
;
1684 xhci
->scratchpad
->sp_buffers
[i
] = buf
;
1685 xhci
->scratchpad
->sp_dma_buffers
[i
] = dma
;
1691 for (i
= i
- 1; i
>= 0; i
--) {
1692 dma_free_coherent(dev
, xhci
->page_size
,
1693 xhci
->scratchpad
->sp_buffers
[i
],
1694 xhci
->scratchpad
->sp_dma_buffers
[i
]);
1696 kfree(xhci
->scratchpad
->sp_dma_buffers
);
1699 kfree(xhci
->scratchpad
->sp_buffers
);
1702 dma_free_coherent(dev
, num_sp
* sizeof(u64
),
1703 xhci
->scratchpad
->sp_array
,
1704 xhci
->scratchpad
->sp_dma
);
1707 kfree(xhci
->scratchpad
);
1708 xhci
->scratchpad
= NULL
;
1714 static void scratchpad_free(struct xhci_hcd
*xhci
)
1718 struct device
*dev
= xhci_to_hcd(xhci
)->self
.controller
;
1720 if (!xhci
->scratchpad
)
1723 num_sp
= HCS_MAX_SCRATCHPAD(xhci
->hcs_params2
);
1725 for (i
= 0; i
< num_sp
; i
++) {
1726 dma_free_coherent(dev
, xhci
->page_size
,
1727 xhci
->scratchpad
->sp_buffers
[i
],
1728 xhci
->scratchpad
->sp_dma_buffers
[i
]);
1730 kfree(xhci
->scratchpad
->sp_dma_buffers
);
1731 kfree(xhci
->scratchpad
->sp_buffers
);
1732 dma_free_coherent(dev
, num_sp
* sizeof(u64
),
1733 xhci
->scratchpad
->sp_array
,
1734 xhci
->scratchpad
->sp_dma
);
1735 kfree(xhci
->scratchpad
);
1736 xhci
->scratchpad
= NULL
;
1739 struct xhci_command
*xhci_alloc_command(struct xhci_hcd
*xhci
,
1740 bool allocate_in_ctx
, bool allocate_completion
,
1743 struct xhci_command
*command
;
1745 command
= kzalloc(sizeof(*command
), mem_flags
);
1749 if (allocate_in_ctx
) {
1751 xhci_alloc_container_ctx(xhci
, XHCI_CTX_TYPE_INPUT
,
1753 if (!command
->in_ctx
) {
1759 if (allocate_completion
) {
1760 command
->completion
=
1761 kzalloc(sizeof(struct completion
), mem_flags
);
1762 if (!command
->completion
) {
1763 xhci_free_container_ctx(xhci
, command
->in_ctx
);
1767 init_completion(command
->completion
);
1770 command
->status
= 0;
1771 INIT_LIST_HEAD(&command
->cmd_list
);
1775 void xhci_urb_free_priv(struct urb_priv
*urb_priv
)
1778 kfree(urb_priv
->td
[0]);
1783 void xhci_free_command(struct xhci_hcd
*xhci
,
1784 struct xhci_command
*command
)
1786 xhci_free_container_ctx(xhci
,
1788 kfree(command
->completion
);
1792 void xhci_mem_cleanup(struct xhci_hcd
*xhci
)
1794 struct device
*dev
= xhci_to_hcd(xhci
)->self
.controller
;
1796 int i
, j
, num_ports
;
1798 del_timer_sync(&xhci
->cmd_timer
);
1800 /* Free the Event Ring Segment Table and the actual Event Ring */
1801 size
= sizeof(struct xhci_erst_entry
)*(xhci
->erst
.num_entries
);
1802 if (xhci
->erst
.entries
)
1803 dma_free_coherent(dev
, size
,
1804 xhci
->erst
.entries
, xhci
->erst
.erst_dma_addr
);
1805 xhci
->erst
.entries
= NULL
;
1806 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "Freed ERST");
1807 if (xhci
->event_ring
)
1808 xhci_ring_free(xhci
, xhci
->event_ring
);
1809 xhci
->event_ring
= NULL
;
1810 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "Freed event ring");
1812 if (xhci
->lpm_command
)
1813 xhci_free_command(xhci
, xhci
->lpm_command
);
1814 xhci
->lpm_command
= NULL
;
1816 xhci_ring_free(xhci
, xhci
->cmd_ring
);
1817 xhci
->cmd_ring
= NULL
;
1818 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "Freed command ring");
1819 xhci_cleanup_command_queue(xhci
);
1821 num_ports
= HCS_MAX_PORTS(xhci
->hcs_params1
);
1822 for (i
= 0; i
< num_ports
&& xhci
->rh_bw
; i
++) {
1823 struct xhci_interval_bw_table
*bwt
= &xhci
->rh_bw
[i
].bw_table
;
1824 for (j
= 0; j
< XHCI_MAX_INTERVAL
; j
++) {
1825 struct list_head
*ep
= &bwt
->interval_bw
[j
].endpoints
;
1826 while (!list_empty(ep
))
1827 list_del_init(ep
->next
);
1831 for (i
= 1; i
< MAX_HC_SLOTS
; ++i
)
1832 xhci_free_virt_device(xhci
, i
);
1834 dma_pool_destroy(xhci
->segment_pool
);
1835 xhci
->segment_pool
= NULL
;
1836 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "Freed segment pool");
1838 dma_pool_destroy(xhci
->device_pool
);
1839 xhci
->device_pool
= NULL
;
1840 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "Freed device context pool");
1842 dma_pool_destroy(xhci
->small_streams_pool
);
1843 xhci
->small_streams_pool
= NULL
;
1844 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
1845 "Freed small stream array pool");
1847 dma_pool_destroy(xhci
->medium_streams_pool
);
1848 xhci
->medium_streams_pool
= NULL
;
1849 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
1850 "Freed medium stream array pool");
1853 dma_free_coherent(dev
, sizeof(*xhci
->dcbaa
),
1854 xhci
->dcbaa
, xhci
->dcbaa
->dma
);
1857 scratchpad_free(xhci
);
1862 for (i
= 0; i
< num_ports
; i
++) {
1863 struct xhci_tt_bw_info
*tt
, *n
;
1864 list_for_each_entry_safe(tt
, n
, &xhci
->rh_bw
[i
].tts
, tt_list
) {
1865 list_del(&tt
->tt_list
);
1871 xhci
->cmd_ring_reserved_trbs
= 0;
1872 xhci
->num_usb2_ports
= 0;
1873 xhci
->num_usb3_ports
= 0;
1874 xhci
->num_active_eps
= 0;
1875 kfree(xhci
->usb2_ports
);
1876 kfree(xhci
->usb3_ports
);
1877 kfree(xhci
->port_array
);
1879 kfree(xhci
->ext_caps
);
1881 xhci
->usb2_ports
= NULL
;
1882 xhci
->usb3_ports
= NULL
;
1883 xhci
->port_array
= NULL
;
1885 xhci
->ext_caps
= NULL
;
1887 xhci
->page_size
= 0;
1888 xhci
->page_shift
= 0;
1889 xhci
->bus_state
[0].bus_suspended
= 0;
1890 xhci
->bus_state
[1].bus_suspended
= 0;
1893 static int xhci_test_trb_in_td(struct xhci_hcd
*xhci
,
1894 struct xhci_segment
*input_seg
,
1895 union xhci_trb
*start_trb
,
1896 union xhci_trb
*end_trb
,
1897 dma_addr_t input_dma
,
1898 struct xhci_segment
*result_seg
,
1899 char *test_name
, int test_number
)
1901 unsigned long long start_dma
;
1902 unsigned long long end_dma
;
1903 struct xhci_segment
*seg
;
1905 start_dma
= xhci_trb_virt_to_dma(input_seg
, start_trb
);
1906 end_dma
= xhci_trb_virt_to_dma(input_seg
, end_trb
);
1908 seg
= trb_in_td(xhci
, input_seg
, start_trb
, end_trb
, input_dma
, false);
1909 if (seg
!= result_seg
) {
1910 xhci_warn(xhci
, "WARN: %s TRB math test %d failed!\n",
1911 test_name
, test_number
);
1912 xhci_warn(xhci
, "Tested TRB math w/ seg %p and "
1913 "input DMA 0x%llx\n",
1915 (unsigned long long) input_dma
);
1916 xhci_warn(xhci
, "starting TRB %p (0x%llx DMA), "
1917 "ending TRB %p (0x%llx DMA)\n",
1918 start_trb
, start_dma
,
1920 xhci_warn(xhci
, "Expected seg %p, got seg %p\n",
1922 trb_in_td(xhci
, input_seg
, start_trb
, end_trb
, input_dma
,
1929 /* TRB math checks for xhci_trb_in_td(), using the command and event rings. */
1930 static int xhci_check_trb_in_td_math(struct xhci_hcd
*xhci
)
1933 dma_addr_t input_dma
;
1934 struct xhci_segment
*result_seg
;
1935 } simple_test_vector
[] = {
1936 /* A zeroed DMA field should fail */
1938 /* One TRB before the ring start should fail */
1939 { xhci
->event_ring
->first_seg
->dma
- 16, NULL
},
1940 /* One byte before the ring start should fail */
1941 { xhci
->event_ring
->first_seg
->dma
- 1, NULL
},
1942 /* Starting TRB should succeed */
1943 { xhci
->event_ring
->first_seg
->dma
, xhci
->event_ring
->first_seg
},
1944 /* Ending TRB should succeed */
1945 { xhci
->event_ring
->first_seg
->dma
+ (TRBS_PER_SEGMENT
- 1)*16,
1946 xhci
->event_ring
->first_seg
},
1947 /* One byte after the ring end should fail */
1948 { xhci
->event_ring
->first_seg
->dma
+ (TRBS_PER_SEGMENT
- 1)*16 + 1, NULL
},
1949 /* One TRB after the ring end should fail */
1950 { xhci
->event_ring
->first_seg
->dma
+ (TRBS_PER_SEGMENT
)*16, NULL
},
1951 /* An address of all ones should fail */
1952 { (dma_addr_t
) (~0), NULL
},
1955 struct xhci_segment
*input_seg
;
1956 union xhci_trb
*start_trb
;
1957 union xhci_trb
*end_trb
;
1958 dma_addr_t input_dma
;
1959 struct xhci_segment
*result_seg
;
1960 } complex_test_vector
[] = {
1961 /* Test feeding a valid DMA address from a different ring */
1962 { .input_seg
= xhci
->event_ring
->first_seg
,
1963 .start_trb
= xhci
->event_ring
->first_seg
->trbs
,
1964 .end_trb
= &xhci
->event_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 1],
1965 .input_dma
= xhci
->cmd_ring
->first_seg
->dma
,
1968 /* Test feeding a valid end TRB from a different ring */
1969 { .input_seg
= xhci
->event_ring
->first_seg
,
1970 .start_trb
= xhci
->event_ring
->first_seg
->trbs
,
1971 .end_trb
= &xhci
->cmd_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 1],
1972 .input_dma
= xhci
->cmd_ring
->first_seg
->dma
,
1975 /* Test feeding a valid start and end TRB from a different ring */
1976 { .input_seg
= xhci
->event_ring
->first_seg
,
1977 .start_trb
= xhci
->cmd_ring
->first_seg
->trbs
,
1978 .end_trb
= &xhci
->cmd_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 1],
1979 .input_dma
= xhci
->cmd_ring
->first_seg
->dma
,
1982 /* TRB in this ring, but after this TD */
1983 { .input_seg
= xhci
->event_ring
->first_seg
,
1984 .start_trb
= &xhci
->event_ring
->first_seg
->trbs
[0],
1985 .end_trb
= &xhci
->event_ring
->first_seg
->trbs
[3],
1986 .input_dma
= xhci
->event_ring
->first_seg
->dma
+ 4*16,
1989 /* TRB in this ring, but before this TD */
1990 { .input_seg
= xhci
->event_ring
->first_seg
,
1991 .start_trb
= &xhci
->event_ring
->first_seg
->trbs
[3],
1992 .end_trb
= &xhci
->event_ring
->first_seg
->trbs
[6],
1993 .input_dma
= xhci
->event_ring
->first_seg
->dma
+ 2*16,
1996 /* TRB in this ring, but after this wrapped TD */
1997 { .input_seg
= xhci
->event_ring
->first_seg
,
1998 .start_trb
= &xhci
->event_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 3],
1999 .end_trb
= &xhci
->event_ring
->first_seg
->trbs
[1],
2000 .input_dma
= xhci
->event_ring
->first_seg
->dma
+ 2*16,
2003 /* TRB in this ring, but before this wrapped TD */
2004 { .input_seg
= xhci
->event_ring
->first_seg
,
2005 .start_trb
= &xhci
->event_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 3],
2006 .end_trb
= &xhci
->event_ring
->first_seg
->trbs
[1],
2007 .input_dma
= xhci
->event_ring
->first_seg
->dma
+ (TRBS_PER_SEGMENT
- 4)*16,
2010 /* TRB not in this ring, and we have a wrapped TD */
2011 { .input_seg
= xhci
->event_ring
->first_seg
,
2012 .start_trb
= &xhci
->event_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 3],
2013 .end_trb
= &xhci
->event_ring
->first_seg
->trbs
[1],
2014 .input_dma
= xhci
->cmd_ring
->first_seg
->dma
+ 2*16,
2019 unsigned int num_tests
;
2022 num_tests
= ARRAY_SIZE(simple_test_vector
);
2023 for (i
= 0; i
< num_tests
; i
++) {
2024 ret
= xhci_test_trb_in_td(xhci
,
2025 xhci
->event_ring
->first_seg
,
2026 xhci
->event_ring
->first_seg
->trbs
,
2027 &xhci
->event_ring
->first_seg
->trbs
[TRBS_PER_SEGMENT
- 1],
2028 simple_test_vector
[i
].input_dma
,
2029 simple_test_vector
[i
].result_seg
,
2035 num_tests
= ARRAY_SIZE(complex_test_vector
);
2036 for (i
= 0; i
< num_tests
; i
++) {
2037 ret
= xhci_test_trb_in_td(xhci
,
2038 complex_test_vector
[i
].input_seg
,
2039 complex_test_vector
[i
].start_trb
,
2040 complex_test_vector
[i
].end_trb
,
2041 complex_test_vector
[i
].input_dma
,
2042 complex_test_vector
[i
].result_seg
,
2047 xhci_dbg(xhci
, "TRB math tests passed.\n");
2051 static void xhci_set_hc_event_deq(struct xhci_hcd
*xhci
)
2056 deq
= xhci_trb_virt_to_dma(xhci
->event_ring
->deq_seg
,
2057 xhci
->event_ring
->dequeue
);
2058 if (deq
== 0 && !in_interrupt())
2059 xhci_warn(xhci
, "WARN something wrong with SW event ring "
2061 /* Update HC event ring dequeue pointer */
2062 temp
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
2063 temp
&= ERST_PTR_MASK
;
2064 /* Don't clear the EHB bit (which is RW1C) because
2065 * there might be more events to service.
2068 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2069 "// Write event ring dequeue pointer, "
2070 "preserving EHB bit");
2071 xhci_write_64(xhci
, ((u64
) deq
& (u64
) ~ERST_PTR_MASK
) | temp
,
2072 &xhci
->ir_set
->erst_dequeue
);
2075 static void xhci_add_in_port(struct xhci_hcd
*xhci
, unsigned int num_ports
,
2076 __le32 __iomem
*addr
, int max_caps
)
2078 u32 temp
, port_offset
, port_count
;
2081 struct xhci_hub
*rhub
;
2084 major_revision
= XHCI_EXT_PORT_MAJOR(temp
);
2086 if (major_revision
== 0x03) {
2087 rhub
= &xhci
->usb3_rhub
;
2088 } else if (major_revision
<= 0x02) {
2089 rhub
= &xhci
->usb2_rhub
;
2091 xhci_warn(xhci
, "Ignoring unknown port speed, "
2092 "Ext Cap %p, revision = 0x%x\n",
2093 addr
, major_revision
);
2094 /* Ignoring port protocol we can't understand. FIXME */
2097 rhub
->maj_rev
= XHCI_EXT_PORT_MAJOR(temp
);
2098 rhub
->min_rev
= XHCI_EXT_PORT_MINOR(temp
);
2100 /* Port offset and count in the third dword, see section 7.2 */
2101 temp
= readl(addr
+ 2);
2102 port_offset
= XHCI_EXT_PORT_OFF(temp
);
2103 port_count
= XHCI_EXT_PORT_COUNT(temp
);
2104 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2105 "Ext Cap %p, port offset = %u, "
2106 "count = %u, revision = 0x%x",
2107 addr
, port_offset
, port_count
, major_revision
);
2108 /* Port count includes the current port offset */
2109 if (port_offset
== 0 || (port_offset
+ port_count
- 1) > num_ports
)
2110 /* WTF? "Valid values are ‘1’ to MaxPorts" */
2113 rhub
->psi_count
= XHCI_EXT_PORT_PSIC(temp
);
2114 if (rhub
->psi_count
) {
2115 rhub
->psi
= kcalloc(rhub
->psi_count
, sizeof(*rhub
->psi
),
2118 rhub
->psi_count
= 0;
2120 rhub
->psi_uid_count
++;
2121 for (i
= 0; i
< rhub
->psi_count
; i
++) {
2122 rhub
->psi
[i
] = readl(addr
+ 4 + i
);
2124 /* count unique ID values, two consecutive entries can
2125 * have the same ID if link is assymetric
2127 if (i
&& (XHCI_EXT_PORT_PSIV(rhub
->psi
[i
]) !=
2128 XHCI_EXT_PORT_PSIV(rhub
->psi
[i
- 1])))
2129 rhub
->psi_uid_count
++;
2131 xhci_dbg(xhci
, "PSIV:%d PSIE:%d PLT:%d PFD:%d LP:%d PSIM:%d\n",
2132 XHCI_EXT_PORT_PSIV(rhub
->psi
[i
]),
2133 XHCI_EXT_PORT_PSIE(rhub
->psi
[i
]),
2134 XHCI_EXT_PORT_PLT(rhub
->psi
[i
]),
2135 XHCI_EXT_PORT_PFD(rhub
->psi
[i
]),
2136 XHCI_EXT_PORT_LP(rhub
->psi
[i
]),
2137 XHCI_EXT_PORT_PSIM(rhub
->psi
[i
]));
2140 /* cache usb2 port capabilities */
2141 if (major_revision
< 0x03 && xhci
->num_ext_caps
< max_caps
)
2142 xhci
->ext_caps
[xhci
->num_ext_caps
++] = temp
;
2144 /* Check the host's USB2 LPM capability */
2145 if ((xhci
->hci_version
== 0x96) && (major_revision
!= 0x03) &&
2146 (temp
& XHCI_L1C
)) {
2147 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2148 "xHCI 0.96: support USB2 software lpm");
2149 xhci
->sw_lpm_support
= 1;
2152 if ((xhci
->hci_version
>= 0x100) && (major_revision
!= 0x03)) {
2153 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2154 "xHCI 1.0: support USB2 software lpm");
2155 xhci
->sw_lpm_support
= 1;
2156 if (temp
& XHCI_HLC
) {
2157 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2158 "xHCI 1.0: support USB2 hardware lpm");
2159 xhci
->hw_lpm_support
= 1;
2164 for (i
= port_offset
; i
< (port_offset
+ port_count
); i
++) {
2165 /* Duplicate entry. Ignore the port if the revisions differ. */
2166 if (xhci
->port_array
[i
] != 0) {
2167 xhci_warn(xhci
, "Duplicate port entry, Ext Cap %p,"
2168 " port %u\n", addr
, i
);
2169 xhci_warn(xhci
, "Port was marked as USB %u, "
2170 "duplicated as USB %u\n",
2171 xhci
->port_array
[i
], major_revision
);
2172 /* Only adjust the roothub port counts if we haven't
2173 * found a similar duplicate.
2175 if (xhci
->port_array
[i
] != major_revision
&&
2176 xhci
->port_array
[i
] != DUPLICATE_ENTRY
) {
2177 if (xhci
->port_array
[i
] == 0x03)
2178 xhci
->num_usb3_ports
--;
2180 xhci
->num_usb2_ports
--;
2181 xhci
->port_array
[i
] = DUPLICATE_ENTRY
;
2183 /* FIXME: Should we disable the port? */
2186 xhci
->port_array
[i
] = major_revision
;
2187 if (major_revision
== 0x03)
2188 xhci
->num_usb3_ports
++;
2190 xhci
->num_usb2_ports
++;
2192 /* FIXME: Should we disable ports not in the Extended Capabilities? */
2196 * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that
2197 * specify what speeds each port is supposed to be. We can't count on the port
2198 * speed bits in the PORTSC register being correct until a device is connected,
2199 * but we need to set up the two fake roothubs with the correct number of USB
2200 * 3.0 and USB 2.0 ports at host controller initialization time.
2202 static int xhci_setup_port_arrays(struct xhci_hcd
*xhci
, gfp_t flags
)
2206 unsigned int num_ports
;
2207 int i
, j
, port_index
;
2211 num_ports
= HCS_MAX_PORTS(xhci
->hcs_params1
);
2212 xhci
->port_array
= kzalloc(sizeof(*xhci
->port_array
)*num_ports
, flags
);
2213 if (!xhci
->port_array
)
2216 xhci
->rh_bw
= kzalloc(sizeof(*xhci
->rh_bw
)*num_ports
, flags
);
2219 for (i
= 0; i
< num_ports
; i
++) {
2220 struct xhci_interval_bw_table
*bw_table
;
2222 INIT_LIST_HEAD(&xhci
->rh_bw
[i
].tts
);
2223 bw_table
= &xhci
->rh_bw
[i
].bw_table
;
2224 for (j
= 0; j
< XHCI_MAX_INTERVAL
; j
++)
2225 INIT_LIST_HEAD(&bw_table
->interval_bw
[j
].endpoints
);
2227 base
= &xhci
->cap_regs
->hc_capbase
;
2229 cap_start
= xhci_find_next_ext_cap(base
, 0, XHCI_EXT_CAPS_PROTOCOL
);
2231 xhci_err(xhci
, "No Extended Capability registers, unable to set up roothub\n");
2236 /* count extended protocol capability entries for later caching */
2239 offset
= xhci_find_next_ext_cap(base
, offset
,
2240 XHCI_EXT_CAPS_PROTOCOL
);
2243 xhci
->ext_caps
= kzalloc(sizeof(*xhci
->ext_caps
) * cap_count
, flags
);
2244 if (!xhci
->ext_caps
)
2250 xhci_add_in_port(xhci
, num_ports
, base
+ offset
, cap_count
);
2251 if (xhci
->num_usb2_ports
+ xhci
->num_usb3_ports
== num_ports
)
2253 offset
= xhci_find_next_ext_cap(base
, offset
,
2254 XHCI_EXT_CAPS_PROTOCOL
);
2257 if (xhci
->num_usb2_ports
== 0 && xhci
->num_usb3_ports
== 0) {
2258 xhci_warn(xhci
, "No ports on the roothubs?\n");
2261 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2262 "Found %u USB 2.0 ports and %u USB 3.0 ports.",
2263 xhci
->num_usb2_ports
, xhci
->num_usb3_ports
);
2265 /* Place limits on the number of roothub ports so that the hub
2266 * descriptors aren't longer than the USB core will allocate.
2268 if (xhci
->num_usb3_ports
> 15) {
2269 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2270 "Limiting USB 3.0 roothub ports to 15.");
2271 xhci
->num_usb3_ports
= 15;
2273 if (xhci
->num_usb2_ports
> USB_MAXCHILDREN
) {
2274 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2275 "Limiting USB 2.0 roothub ports to %u.",
2277 xhci
->num_usb2_ports
= USB_MAXCHILDREN
;
2281 * Note we could have all USB 3.0 ports, or all USB 2.0 ports.
2282 * Not sure how the USB core will handle a hub with no ports...
2284 if (xhci
->num_usb2_ports
) {
2285 xhci
->usb2_ports
= kmalloc(sizeof(*xhci
->usb2_ports
)*
2286 xhci
->num_usb2_ports
, flags
);
2287 if (!xhci
->usb2_ports
)
2291 for (i
= 0; i
< num_ports
; i
++) {
2292 if (xhci
->port_array
[i
] == 0x03 ||
2293 xhci
->port_array
[i
] == 0 ||
2294 xhci
->port_array
[i
] == DUPLICATE_ENTRY
)
2297 xhci
->usb2_ports
[port_index
] =
2298 &xhci
->op_regs
->port_status_base
+
2300 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2301 "USB 2.0 port at index %u, "
2303 xhci
->usb2_ports
[port_index
]);
2305 if (port_index
== xhci
->num_usb2_ports
)
2309 if (xhci
->num_usb3_ports
) {
2310 xhci
->usb3_ports
= kmalloc(sizeof(*xhci
->usb3_ports
)*
2311 xhci
->num_usb3_ports
, flags
);
2312 if (!xhci
->usb3_ports
)
2316 for (i
= 0; i
< num_ports
; i
++)
2317 if (xhci
->port_array
[i
] == 0x03) {
2318 xhci
->usb3_ports
[port_index
] =
2319 &xhci
->op_regs
->port_status_base
+
2321 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2322 "USB 3.0 port at index %u, "
2324 xhci
->usb3_ports
[port_index
]);
2326 if (port_index
== xhci
->num_usb3_ports
)
2333 int xhci_mem_init(struct xhci_hcd
*xhci
, gfp_t flags
)
2336 struct device
*dev
= xhci_to_hcd(xhci
)->self
.controller
;
2337 unsigned int val
, val2
;
2339 struct xhci_segment
*seg
;
2340 u32 page_size
, temp
;
2343 INIT_LIST_HEAD(&xhci
->cmd_list
);
2345 /* init command timeout timer */
2346 setup_timer(&xhci
->cmd_timer
, xhci_handle_command_timeout
,
2347 (unsigned long)xhci
);
2349 page_size
= readl(&xhci
->op_regs
->page_size
);
2350 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2351 "Supported page size register = 0x%x", page_size
);
2352 for (i
= 0; i
< 16; i
++) {
2353 if ((0x1 & page_size
) != 0)
2355 page_size
= page_size
>> 1;
2358 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2359 "Supported page size of %iK", (1 << (i
+12)) / 1024);
2361 xhci_warn(xhci
, "WARN: no supported page size\n");
2362 /* Use 4K pages, since that's common and the minimum the HC supports */
2363 xhci
->page_shift
= 12;
2364 xhci
->page_size
= 1 << xhci
->page_shift
;
2365 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2366 "HCD page size set to %iK", xhci
->page_size
/ 1024);
2369 * Program the Number of Device Slots Enabled field in the CONFIG
2370 * register with the max value of slots the HC can handle.
2372 val
= HCS_MAX_SLOTS(readl(&xhci
->cap_regs
->hcs_params1
));
2373 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2374 "// xHC can handle at most %d device slots.", val
);
2375 val2
= readl(&xhci
->op_regs
->config_reg
);
2376 val
|= (val2
& ~HCS_SLOTS_MASK
);
2377 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2378 "// Setting Max device slots reg = 0x%x.", val
);
2379 writel(val
, &xhci
->op_regs
->config_reg
);
2382 * Section 5.4.8 - doorbell array must be
2383 * "physically contiguous and 64-byte (cache line) aligned".
2385 xhci
->dcbaa
= dma_alloc_coherent(dev
, sizeof(*xhci
->dcbaa
), &dma
,
2389 memset(xhci
->dcbaa
, 0, sizeof *(xhci
->dcbaa
));
2390 xhci
->dcbaa
->dma
= dma
;
2391 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2392 "// Device context base array address = 0x%llx (DMA), %p (virt)",
2393 (unsigned long long)xhci
->dcbaa
->dma
, xhci
->dcbaa
);
2394 xhci_write_64(xhci
, dma
, &xhci
->op_regs
->dcbaa_ptr
);
2397 * Initialize the ring segment pool. The ring must be a contiguous
2398 * structure comprised of TRBs. The TRBs must be 16 byte aligned,
2399 * however, the command ring segment needs 64-byte aligned segments
2400 * and our use of dma addresses in the trb_address_map radix tree needs
2401 * TRB_SEGMENT_SIZE alignment, so we pick the greater alignment need.
2403 xhci
->segment_pool
= dma_pool_create("xHCI ring segments", dev
,
2404 TRB_SEGMENT_SIZE
, TRB_SEGMENT_SIZE
, xhci
->page_size
);
2406 /* See Table 46 and Note on Figure 55 */
2407 xhci
->device_pool
= dma_pool_create("xHCI input/output contexts", dev
,
2408 2112, 64, xhci
->page_size
);
2409 if (!xhci
->segment_pool
|| !xhci
->device_pool
)
2412 /* Linear stream context arrays don't have any boundary restrictions,
2413 * and only need to be 16-byte aligned.
2415 xhci
->small_streams_pool
=
2416 dma_pool_create("xHCI 256 byte stream ctx arrays",
2417 dev
, SMALL_STREAM_ARRAY_SIZE
, 16, 0);
2418 xhci
->medium_streams_pool
=
2419 dma_pool_create("xHCI 1KB stream ctx arrays",
2420 dev
, MEDIUM_STREAM_ARRAY_SIZE
, 16, 0);
2421 /* Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE
2422 * will be allocated with dma_alloc_coherent()
2425 if (!xhci
->small_streams_pool
|| !xhci
->medium_streams_pool
)
2428 /* Set up the command ring to have one segments for now. */
2429 xhci
->cmd_ring
= xhci_ring_alloc(xhci
, 1, 1, TYPE_COMMAND
, 0, flags
);
2430 if (!xhci
->cmd_ring
)
2432 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2433 "Allocated command ring at %p", xhci
->cmd_ring
);
2434 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "First segment DMA is 0x%llx",
2435 (unsigned long long)xhci
->cmd_ring
->first_seg
->dma
);
2437 /* Set the address in the Command Ring Control register */
2438 val_64
= xhci_read_64(xhci
, &xhci
->op_regs
->cmd_ring
);
2439 val_64
= (val_64
& (u64
) CMD_RING_RSVD_BITS
) |
2440 (xhci
->cmd_ring
->first_seg
->dma
& (u64
) ~CMD_RING_RSVD_BITS
) |
2441 xhci
->cmd_ring
->cycle_state
;
2442 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2443 "// Setting command ring address to 0x%x", val
);
2444 xhci_write_64(xhci
, val_64
, &xhci
->op_regs
->cmd_ring
);
2445 xhci_dbg_cmd_ptrs(xhci
);
2447 xhci
->lpm_command
= xhci_alloc_command(xhci
, true, true, flags
);
2448 if (!xhci
->lpm_command
)
2451 /* Reserve one command ring TRB for disabling LPM.
2452 * Since the USB core grabs the shared usb_bus bandwidth mutex before
2453 * disabling LPM, we only need to reserve one TRB for all devices.
2455 xhci
->cmd_ring_reserved_trbs
++;
2457 val
= readl(&xhci
->cap_regs
->db_off
);
2459 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2460 "// Doorbell array is located at offset 0x%x"
2461 " from cap regs base addr", val
);
2462 xhci
->dba
= (void __iomem
*) xhci
->cap_regs
+ val
;
2463 xhci_dbg_regs(xhci
);
2464 xhci_print_run_regs(xhci
);
2465 /* Set ir_set to interrupt register set 0 */
2466 xhci
->ir_set
= &xhci
->run_regs
->ir_set
[0];
2469 * Event ring setup: Allocate a normal ring, but also setup
2470 * the event ring segment table (ERST). Section 4.9.3.
2472 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
, "// Allocating event ring");
2473 xhci
->event_ring
= xhci_ring_alloc(xhci
, ERST_NUM_SEGS
, 1, TYPE_EVENT
,
2475 if (!xhci
->event_ring
)
2477 if (xhci_check_trb_in_td_math(xhci
) < 0)
2480 xhci
->erst
.entries
= dma_alloc_coherent(dev
,
2481 sizeof(struct xhci_erst_entry
) * ERST_NUM_SEGS
, &dma
,
2483 if (!xhci
->erst
.entries
)
2485 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2486 "// Allocated event ring segment table at 0x%llx",
2487 (unsigned long long)dma
);
2489 memset(xhci
->erst
.entries
, 0, sizeof(struct xhci_erst_entry
)*ERST_NUM_SEGS
);
2490 xhci
->erst
.num_entries
= ERST_NUM_SEGS
;
2491 xhci
->erst
.erst_dma_addr
= dma
;
2492 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2493 "Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx",
2494 xhci
->erst
.num_entries
,
2496 (unsigned long long)xhci
->erst
.erst_dma_addr
);
2498 /* set ring base address and size for each segment table entry */
2499 for (val
= 0, seg
= xhci
->event_ring
->first_seg
; val
< ERST_NUM_SEGS
; val
++) {
2500 struct xhci_erst_entry
*entry
= &xhci
->erst
.entries
[val
];
2501 entry
->seg_addr
= cpu_to_le64(seg
->dma
);
2502 entry
->seg_size
= cpu_to_le32(TRBS_PER_SEGMENT
);
2507 /* set ERST count with the number of entries in the segment table */
2508 val
= readl(&xhci
->ir_set
->erst_size
);
2509 val
&= ERST_SIZE_MASK
;
2510 val
|= ERST_NUM_SEGS
;
2511 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2512 "// Write ERST size = %i to ir_set 0 (some bits preserved)",
2514 writel(val
, &xhci
->ir_set
->erst_size
);
2516 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2517 "// Set ERST entries to point to event ring.");
2518 /* set the segment table base address */
2519 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2520 "// Set ERST base address for ir_set 0 = 0x%llx",
2521 (unsigned long long)xhci
->erst
.erst_dma_addr
);
2522 val_64
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_base
);
2523 val_64
&= ERST_PTR_MASK
;
2524 val_64
|= (xhci
->erst
.erst_dma_addr
& (u64
) ~ERST_PTR_MASK
);
2525 xhci_write_64(xhci
, val_64
, &xhci
->ir_set
->erst_base
);
2527 /* Set the event ring dequeue address */
2528 xhci_set_hc_event_deq(xhci
);
2529 xhci_dbg_trace(xhci
, trace_xhci_dbg_init
,
2530 "Wrote ERST address to ir_set 0.");
2531 xhci_print_ir_set(xhci
, 0);
2534 * XXX: Might need to set the Interrupter Moderation Register to
2535 * something other than the default (~1ms minimum between interrupts).
2536 * See section 5.5.1.2.
2538 init_completion(&xhci
->addr_dev
);
2539 for (i
= 0; i
< MAX_HC_SLOTS
; ++i
)
2540 xhci
->devs
[i
] = NULL
;
2541 for (i
= 0; i
< USB_MAXCHILDREN
; ++i
) {
2542 xhci
->bus_state
[0].resume_done
[i
] = 0;
2543 xhci
->bus_state
[1].resume_done
[i
] = 0;
2544 /* Only the USB 2.0 completions will ever be used. */
2545 init_completion(&xhci
->bus_state
[1].rexit_done
[i
]);
2548 if (scratchpad_alloc(xhci
, flags
))
2550 if (xhci_setup_port_arrays(xhci
, flags
))
2553 /* Enable USB 3.0 device notifications for function remote wake, which
2554 * is necessary for allowing USB 3.0 devices to do remote wakeup from
2555 * U3 (device suspend).
2557 temp
= readl(&xhci
->op_regs
->dev_notification
);
2558 temp
&= ~DEV_NOTE_MASK
;
2559 temp
|= DEV_NOTE_FWAKE
;
2560 writel(temp
, &xhci
->op_regs
->dev_notification
);
2565 xhci_warn(xhci
, "Couldn't initialize memory\n");
2568 xhci_mem_cleanup(xhci
);