2 * VFIO PCI config space virtualization
4 * Copyright (C) 2012 Red Hat, Inc. All rights reserved.
5 * Author: Alex Williamson <alex.williamson@redhat.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * Derived from original vfio:
12 * Copyright 2010 Cisco Systems, Inc. All rights reserved.
13 * Author: Tom Lyon, pugs@cisco.com
17 * This code handles reading and writing of PCI configuration registers.
18 * This is hairy because we want to allow a lot of flexibility to the
19 * user driver, but cannot trust it with all of the config fields.
20 * Tables determine which fields can be read and written, as well as
21 * which fields are 'virtualized' - special actions and translations to
22 * make it appear to the user that he has control, when in fact things
23 * must be negotiated with the underlying OS.
27 #include <linux/pci.h>
28 #include <linux/uaccess.h>
29 #include <linux/vfio.h>
30 #include <linux/slab.h>
32 #include "vfio_pci_private.h"
34 #define PCI_CFG_SPACE_SIZE 256
36 /* Useful "pseudo" capabilities */
37 #define PCI_CAP_ID_BASIC 0
38 #define PCI_CAP_ID_INVALID 0xFF
40 #define is_bar(offset) \
41 ((offset >= PCI_BASE_ADDRESS_0 && offset < PCI_BASE_ADDRESS_5 + 4) || \
42 (offset >= PCI_ROM_ADDRESS && offset < PCI_ROM_ADDRESS + 4))
45 * Lengths of PCI Config Capabilities
46 * 0: Removed from the user visible capability list
49 static u8 pci_cap_length
[] = {
50 [PCI_CAP_ID_BASIC
] = PCI_STD_HEADER_SIZEOF
, /* pci config header */
51 [PCI_CAP_ID_PM
] = PCI_PM_SIZEOF
,
52 [PCI_CAP_ID_AGP
] = PCI_AGP_SIZEOF
,
53 [PCI_CAP_ID_VPD
] = PCI_CAP_VPD_SIZEOF
,
54 [PCI_CAP_ID_SLOTID
] = 0, /* bridge - don't care */
55 [PCI_CAP_ID_MSI
] = 0xFF, /* 10, 14, 20, or 24 */
56 [PCI_CAP_ID_CHSWP
] = 0, /* cpci - not yet */
57 [PCI_CAP_ID_PCIX
] = 0xFF, /* 8 or 24 */
58 [PCI_CAP_ID_HT
] = 0xFF, /* hypertransport */
59 [PCI_CAP_ID_VNDR
] = 0xFF, /* variable */
60 [PCI_CAP_ID_DBG
] = 0, /* debug - don't care */
61 [PCI_CAP_ID_CCRC
] = 0, /* cpci - not yet */
62 [PCI_CAP_ID_SHPC
] = 0, /* hotswap - not yet */
63 [PCI_CAP_ID_SSVID
] = 0, /* bridge - don't care */
64 [PCI_CAP_ID_AGP3
] = 0, /* AGP8x - not yet */
65 [PCI_CAP_ID_SECDEV
] = 0, /* secure device not yet */
66 [PCI_CAP_ID_EXP
] = 0xFF, /* 20 or 44 */
67 [PCI_CAP_ID_MSIX
] = PCI_CAP_MSIX_SIZEOF
,
68 [PCI_CAP_ID_SATA
] = 0xFF,
69 [PCI_CAP_ID_AF
] = PCI_CAP_AF_SIZEOF
,
73 * Lengths of PCIe/PCI-X Extended Config Capabilities
74 * 0: Removed or masked from the user visible capabilty list
77 static u16 pci_ext_cap_length
[] = {
78 [PCI_EXT_CAP_ID_ERR
] = PCI_ERR_ROOT_COMMAND
,
79 [PCI_EXT_CAP_ID_VC
] = 0xFF,
80 [PCI_EXT_CAP_ID_DSN
] = PCI_EXT_CAP_DSN_SIZEOF
,
81 [PCI_EXT_CAP_ID_PWR
] = PCI_EXT_CAP_PWR_SIZEOF
,
82 [PCI_EXT_CAP_ID_RCLD
] = 0, /* root only - don't care */
83 [PCI_EXT_CAP_ID_RCILC
] = 0, /* root only - don't care */
84 [PCI_EXT_CAP_ID_RCEC
] = 0, /* root only - don't care */
85 [PCI_EXT_CAP_ID_MFVC
] = 0xFF,
86 [PCI_EXT_CAP_ID_VC9
] = 0xFF, /* same as CAP_ID_VC */
87 [PCI_EXT_CAP_ID_RCRB
] = 0, /* root only - don't care */
88 [PCI_EXT_CAP_ID_VNDR
] = 0xFF,
89 [PCI_EXT_CAP_ID_CAC
] = 0, /* obsolete */
90 [PCI_EXT_CAP_ID_ACS
] = 0xFF,
91 [PCI_EXT_CAP_ID_ARI
] = PCI_EXT_CAP_ARI_SIZEOF
,
92 [PCI_EXT_CAP_ID_ATS
] = PCI_EXT_CAP_ATS_SIZEOF
,
93 [PCI_EXT_CAP_ID_SRIOV
] = PCI_EXT_CAP_SRIOV_SIZEOF
,
94 [PCI_EXT_CAP_ID_MRIOV
] = 0, /* not yet */
95 [PCI_EXT_CAP_ID_MCAST
] = PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF
,
96 [PCI_EXT_CAP_ID_PRI
] = PCI_EXT_CAP_PRI_SIZEOF
,
97 [PCI_EXT_CAP_ID_AMD_XXX
] = 0, /* not yet */
98 [PCI_EXT_CAP_ID_REBAR
] = 0xFF,
99 [PCI_EXT_CAP_ID_DPA
] = 0xFF,
100 [PCI_EXT_CAP_ID_TPH
] = 0xFF,
101 [PCI_EXT_CAP_ID_LTR
] = PCI_EXT_CAP_LTR_SIZEOF
,
102 [PCI_EXT_CAP_ID_SECPCI
] = 0, /* not yet */
103 [PCI_EXT_CAP_ID_PMUX
] = 0, /* not yet */
104 [PCI_EXT_CAP_ID_PASID
] = 0, /* not yet */
108 * Read/Write Permission Bits - one bit for each bit in capability
109 * Any field can be read if it exists, but what is read depends on
110 * whether the field is 'virtualized', or just pass thru to the
111 * hardware. Any virtualized field is also virtualized for writes.
112 * Writes are only permitted if they have a 1 bit here.
115 u8
*virt
; /* read/write virtual data, not hw */
116 u8
*write
; /* writeable bits */
117 int (*readfn
)(struct vfio_pci_device
*vdev
, int pos
, int count
,
118 struct perm_bits
*perm
, int offset
, __le32
*val
);
119 int (*writefn
)(struct vfio_pci_device
*vdev
, int pos
, int count
,
120 struct perm_bits
*perm
, int offset
, __le32 val
);
124 #define ALL_VIRT 0xFFFFFFFFU
126 #define ALL_WRITE 0xFFFFFFFFU
128 static int vfio_user_config_read(struct pci_dev
*pdev
, int offset
,
129 __le32
*val
, int count
)
138 ret
= pci_user_read_config_byte(pdev
, offset
, &tmp
);
145 ret
= pci_user_read_config_word(pdev
, offset
, &tmp
);
150 ret
= pci_user_read_config_dword(pdev
, offset
, &tmp_val
);
154 *val
= cpu_to_le32(tmp_val
);
156 return pcibios_err_to_errno(ret
);
159 static int vfio_user_config_write(struct pci_dev
*pdev
, int offset
,
160 __le32 val
, int count
)
163 u32 tmp_val
= le32_to_cpu(val
);
167 ret
= pci_user_write_config_byte(pdev
, offset
, tmp_val
);
170 ret
= pci_user_write_config_word(pdev
, offset
, tmp_val
);
173 ret
= pci_user_write_config_dword(pdev
, offset
, tmp_val
);
177 return pcibios_err_to_errno(ret
);
180 static int vfio_default_config_read(struct vfio_pci_device
*vdev
, int pos
,
181 int count
, struct perm_bits
*perm
,
182 int offset
, __le32
*val
)
186 memcpy(val
, vdev
->vconfig
+ pos
, count
);
188 memcpy(&virt
, perm
->virt
+ offset
, count
);
190 /* Any non-virtualized bits? */
191 if (cpu_to_le32(~0U >> (32 - (count
* 8))) != virt
) {
192 struct pci_dev
*pdev
= vdev
->pdev
;
196 ret
= vfio_user_config_read(pdev
, pos
, &phys_val
, count
);
200 *val
= (phys_val
& ~virt
) | (*val
& virt
);
206 static int vfio_default_config_write(struct vfio_pci_device
*vdev
, int pos
,
207 int count
, struct perm_bits
*perm
,
208 int offset
, __le32 val
)
210 __le32 virt
= 0, write
= 0;
212 memcpy(&write
, perm
->write
+ offset
, count
);
215 return count
; /* drop, no writable bits */
217 memcpy(&virt
, perm
->virt
+ offset
, count
);
219 /* Virtualized and writable bits go to vconfig */
223 memcpy(&virt_val
, vdev
->vconfig
+ pos
, count
);
225 virt_val
&= ~(write
& virt
);
226 virt_val
|= (val
& (write
& virt
));
228 memcpy(vdev
->vconfig
+ pos
, &virt_val
, count
);
231 /* Non-virtualzed and writable bits go to hardware */
233 struct pci_dev
*pdev
= vdev
->pdev
;
237 ret
= vfio_user_config_read(pdev
, pos
, &phys_val
, count
);
241 phys_val
&= ~(write
& ~virt
);
242 phys_val
|= (val
& (write
& ~virt
));
244 ret
= vfio_user_config_write(pdev
, pos
, phys_val
, count
);
252 /* Allow direct read from hardware, except for capability next pointer */
253 static int vfio_direct_config_read(struct vfio_pci_device
*vdev
, int pos
,
254 int count
, struct perm_bits
*perm
,
255 int offset
, __le32
*val
)
259 ret
= vfio_user_config_read(vdev
->pdev
, pos
, val
, count
);
261 return pcibios_err_to_errno(ret
);
263 if (pos
>= PCI_CFG_SPACE_SIZE
) { /* Extended cap header mangling */
265 memcpy(val
, vdev
->vconfig
+ pos
, count
);
266 } else if (pos
>= PCI_STD_HEADER_SIZEOF
) { /* Std cap mangling */
267 if (offset
== PCI_CAP_LIST_ID
&& count
> 1)
268 memcpy(val
, vdev
->vconfig
+ pos
,
269 min(PCI_CAP_FLAGS
, count
));
270 else if (offset
== PCI_CAP_LIST_NEXT
)
271 memcpy(val
, vdev
->vconfig
+ pos
, 1);
277 static int vfio_direct_config_write(struct vfio_pci_device
*vdev
, int pos
,
278 int count
, struct perm_bits
*perm
,
279 int offset
, __le32 val
)
283 ret
= vfio_user_config_write(vdev
->pdev
, pos
, val
, count
);
290 /* Default all regions to read-only, no-virtualization */
291 static struct perm_bits cap_perms
[PCI_CAP_ID_MAX
+ 1] = {
292 [0 ... PCI_CAP_ID_MAX
] = { .readfn
= vfio_direct_config_read
}
294 static struct perm_bits ecap_perms
[PCI_EXT_CAP_ID_MAX
+ 1] = {
295 [0 ... PCI_EXT_CAP_ID_MAX
] = { .readfn
= vfio_direct_config_read
}
298 static void free_perm_bits(struct perm_bits
*perm
)
306 static int alloc_perm_bits(struct perm_bits
*perm
, int size
)
309 * Round up all permission bits to the next dword, this lets us
310 * ignore whether a read/write exceeds the defined capability
311 * structure. We can do this because:
312 * - Standard config space is already dword aligned
313 * - Capabilities are all dword alinged (bits 0:1 of next reserved)
314 * - Express capabilities defined as dword aligned
316 size
= round_up(size
, 4);
320 * - All Readable, None Writeable, None Virtualized
322 perm
->virt
= kzalloc(size
, GFP_KERNEL
);
323 perm
->write
= kzalloc(size
, GFP_KERNEL
);
324 if (!perm
->virt
|| !perm
->write
) {
325 free_perm_bits(perm
);
329 perm
->readfn
= vfio_default_config_read
;
330 perm
->writefn
= vfio_default_config_write
;
336 * Helper functions for filling in permission tables
338 static inline void p_setb(struct perm_bits
*p
, int off
, u8 virt
, u8 write
)
341 p
->write
[off
] = write
;
344 /* Handle endian-ness - pci and tables are little-endian */
345 static inline void p_setw(struct perm_bits
*p
, int off
, u16 virt
, u16 write
)
347 *(__le16
*)(&p
->virt
[off
]) = cpu_to_le16(virt
);
348 *(__le16
*)(&p
->write
[off
]) = cpu_to_le16(write
);
351 /* Handle endian-ness - pci and tables are little-endian */
352 static inline void p_setd(struct perm_bits
*p
, int off
, u32 virt
, u32 write
)
354 *(__le32
*)(&p
->virt
[off
]) = cpu_to_le32(virt
);
355 *(__le32
*)(&p
->write
[off
]) = cpu_to_le32(write
);
359 * Restore the *real* BARs after we detect a FLR or backdoor reset.
360 * (backdoor = some device specific technique that we didn't catch)
362 static void vfio_bar_restore(struct vfio_pci_device
*vdev
)
364 struct pci_dev
*pdev
= vdev
->pdev
;
365 u32
*rbar
= vdev
->rbar
;
371 pr_info("%s: %s reset recovery - restoring bars\n",
372 __func__
, dev_name(&pdev
->dev
));
374 for (i
= PCI_BASE_ADDRESS_0
; i
<= PCI_BASE_ADDRESS_5
; i
+= 4, rbar
++)
375 pci_user_write_config_dword(pdev
, i
, *rbar
);
377 pci_user_write_config_dword(pdev
, PCI_ROM_ADDRESS
, *rbar
);
380 static __le32
vfio_generate_bar_flags(struct pci_dev
*pdev
, int bar
)
382 unsigned long flags
= pci_resource_flags(pdev
, bar
);
385 if (flags
& IORESOURCE_IO
)
386 return cpu_to_le32(PCI_BASE_ADDRESS_SPACE_IO
);
388 val
= PCI_BASE_ADDRESS_SPACE_MEMORY
;
390 if (flags
& IORESOURCE_PREFETCH
)
391 val
|= PCI_BASE_ADDRESS_MEM_PREFETCH
;
393 if (flags
& IORESOURCE_MEM_64
)
394 val
|= PCI_BASE_ADDRESS_MEM_TYPE_64
;
396 return cpu_to_le32(val
);
400 * Pretend we're hardware and tweak the values of the *virtual* PCI BARs
401 * to reflect the hardware capabilities. This implements BAR sizing.
403 static void vfio_bar_fixup(struct vfio_pci_device
*vdev
)
405 struct pci_dev
*pdev
= vdev
->pdev
;
410 bar
= (__le32
*)&vdev
->vconfig
[PCI_BASE_ADDRESS_0
];
412 for (i
= PCI_STD_RESOURCES
; i
<= PCI_STD_RESOURCE_END
; i
++, bar
++) {
413 if (!pci_resource_start(pdev
, i
)) {
414 *bar
= 0; /* Unmapped by host = unimplemented to user */
418 mask
= ~(pci_resource_len(pdev
, i
) - 1);
420 *bar
&= cpu_to_le32((u32
)mask
);
421 *bar
|= vfio_generate_bar_flags(pdev
, i
);
423 if (*bar
& cpu_to_le32(PCI_BASE_ADDRESS_MEM_TYPE_64
)) {
425 *bar
&= cpu_to_le32((u32
)(mask
>> 32));
430 bar
= (__le32
*)&vdev
->vconfig
[PCI_ROM_ADDRESS
];
433 * NB. we expose the actual BAR size here, regardless of whether
434 * we can read it. When we report the REGION_INFO for the ROM
435 * we report what PCI tells us is the actual ROM size.
437 if (pci_resource_start(pdev
, PCI_ROM_RESOURCE
)) {
438 mask
= ~(pci_resource_len(pdev
, PCI_ROM_RESOURCE
) - 1);
439 mask
|= PCI_ROM_ADDRESS_ENABLE
;
440 *bar
&= cpu_to_le32((u32
)mask
);
444 vdev
->bardirty
= false;
447 static int vfio_basic_config_read(struct vfio_pci_device
*vdev
, int pos
,
448 int count
, struct perm_bits
*perm
,
449 int offset
, __le32
*val
)
451 if (is_bar(offset
)) /* pos == offset for basic config */
452 vfio_bar_fixup(vdev
);
454 count
= vfio_default_config_read(vdev
, pos
, count
, perm
, offset
, val
);
456 /* Mask in virtual memory enable for SR-IOV devices */
457 if (offset
== PCI_COMMAND
&& vdev
->pdev
->is_virtfn
) {
458 u16 cmd
= le16_to_cpu(*(__le16
*)&vdev
->vconfig
[PCI_COMMAND
]);
459 u32 tmp_val
= le32_to_cpu(*val
);
461 tmp_val
|= cmd
& PCI_COMMAND_MEMORY
;
462 *val
= cpu_to_le32(tmp_val
);
468 static int vfio_basic_config_write(struct vfio_pci_device
*vdev
, int pos
,
469 int count
, struct perm_bits
*perm
,
470 int offset
, __le32 val
)
472 struct pci_dev
*pdev
= vdev
->pdev
;
477 virt_cmd
= (__le16
*)&vdev
->vconfig
[PCI_COMMAND
];
479 if (offset
== PCI_COMMAND
) {
480 bool phys_mem
, virt_mem
, new_mem
, phys_io
, virt_io
, new_io
;
483 ret
= pci_user_read_config_word(pdev
, PCI_COMMAND
, &phys_cmd
);
487 new_cmd
= le32_to_cpu(val
);
489 phys_mem
= !!(phys_cmd
& PCI_COMMAND_MEMORY
);
490 virt_mem
= !!(le16_to_cpu(*virt_cmd
) & PCI_COMMAND_MEMORY
);
491 new_mem
= !!(new_cmd
& PCI_COMMAND_MEMORY
);
493 phys_io
= !!(phys_cmd
& PCI_COMMAND_IO
);
494 virt_io
= !!(le16_to_cpu(*virt_cmd
) & PCI_COMMAND_IO
);
495 new_io
= !!(new_cmd
& PCI_COMMAND_IO
);
498 * If the user is writing mem/io enable (new_mem/io) and we
499 * think it's already enabled (virt_mem/io), but the hardware
500 * shows it disabled (phys_mem/io, then the device has
501 * undergone some kind of backdoor reset and needs to be
502 * restored before we allow it to enable the bars.
503 * SR-IOV devices will trigger this, but we catch them later
505 if ((new_mem
&& virt_mem
&& !phys_mem
) ||
506 (new_io
&& virt_io
&& !phys_io
))
507 vfio_bar_restore(vdev
);
510 count
= vfio_default_config_write(vdev
, pos
, count
, perm
, offset
, val
);
515 * Save current memory/io enable bits in vconfig to allow for
516 * the test above next time.
518 if (offset
== PCI_COMMAND
) {
519 u16 mask
= PCI_COMMAND_MEMORY
| PCI_COMMAND_IO
;
521 *virt_cmd
&= cpu_to_le16(~mask
);
522 *virt_cmd
|= cpu_to_le16(new_cmd
& mask
);
525 /* Emulate INTx disable */
526 if (offset
>= PCI_COMMAND
&& offset
<= PCI_COMMAND
+ 1) {
527 bool virt_intx_disable
;
529 virt_intx_disable
= !!(le16_to_cpu(*virt_cmd
) &
530 PCI_COMMAND_INTX_DISABLE
);
532 if (virt_intx_disable
&& !vdev
->virq_disabled
) {
533 vdev
->virq_disabled
= true;
534 vfio_pci_intx_mask(vdev
);
535 } else if (!virt_intx_disable
&& vdev
->virq_disabled
) {
536 vdev
->virq_disabled
= false;
537 vfio_pci_intx_unmask(vdev
);
542 vdev
->bardirty
= true;
547 /* Permissions for the Basic PCI Header */
548 static int __init
init_pci_cap_basic_perm(struct perm_bits
*perm
)
550 if (alloc_perm_bits(perm
, PCI_STD_HEADER_SIZEOF
))
553 perm
->readfn
= vfio_basic_config_read
;
554 perm
->writefn
= vfio_basic_config_write
;
556 /* Virtualized for SR-IOV functions, which just have FFFF */
557 p_setw(perm
, PCI_VENDOR_ID
, (u16
)ALL_VIRT
, NO_WRITE
);
558 p_setw(perm
, PCI_DEVICE_ID
, (u16
)ALL_VIRT
, NO_WRITE
);
561 * Virtualize INTx disable, we use it internally for interrupt
562 * control and can emulate it for non-PCI 2.3 devices.
564 p_setw(perm
, PCI_COMMAND
, PCI_COMMAND_INTX_DISABLE
, (u16
)ALL_WRITE
);
566 /* Virtualize capability list, we might want to skip/disable */
567 p_setw(perm
, PCI_STATUS
, PCI_STATUS_CAP_LIST
, NO_WRITE
);
569 /* No harm to write */
570 p_setb(perm
, PCI_CACHE_LINE_SIZE
, NO_VIRT
, (u8
)ALL_WRITE
);
571 p_setb(perm
, PCI_LATENCY_TIMER
, NO_VIRT
, (u8
)ALL_WRITE
);
572 p_setb(perm
, PCI_BIST
, NO_VIRT
, (u8
)ALL_WRITE
);
574 /* Virtualize all bars, can't touch the real ones */
575 p_setd(perm
, PCI_BASE_ADDRESS_0
, ALL_VIRT
, ALL_WRITE
);
576 p_setd(perm
, PCI_BASE_ADDRESS_1
, ALL_VIRT
, ALL_WRITE
);
577 p_setd(perm
, PCI_BASE_ADDRESS_2
, ALL_VIRT
, ALL_WRITE
);
578 p_setd(perm
, PCI_BASE_ADDRESS_3
, ALL_VIRT
, ALL_WRITE
);
579 p_setd(perm
, PCI_BASE_ADDRESS_4
, ALL_VIRT
, ALL_WRITE
);
580 p_setd(perm
, PCI_BASE_ADDRESS_5
, ALL_VIRT
, ALL_WRITE
);
581 p_setd(perm
, PCI_ROM_ADDRESS
, ALL_VIRT
, ALL_WRITE
);
583 /* Allow us to adjust capability chain */
584 p_setb(perm
, PCI_CAPABILITY_LIST
, (u8
)ALL_VIRT
, NO_WRITE
);
586 /* Sometimes used by sw, just virtualize */
587 p_setb(perm
, PCI_INTERRUPT_LINE
, (u8
)ALL_VIRT
, (u8
)ALL_WRITE
);
591 static int vfio_pm_config_write(struct vfio_pci_device
*vdev
, int pos
,
592 int count
, struct perm_bits
*perm
,
593 int offset
, __le32 val
)
595 count
= vfio_default_config_write(vdev
, pos
, count
, perm
, offset
, val
);
599 if (offset
== PCI_PM_CTRL
) {
602 switch (le32_to_cpu(val
) & PCI_PM_CTRL_STATE_MASK
) {
617 pci_set_power_state(vdev
->pdev
, state
);
623 /* Permissions for the Power Management capability */
624 static int __init
init_pci_cap_pm_perm(struct perm_bits
*perm
)
626 if (alloc_perm_bits(perm
, pci_cap_length
[PCI_CAP_ID_PM
]))
629 perm
->writefn
= vfio_pm_config_write
;
632 * We always virtualize the next field so we can remove
633 * capabilities from the chain if we want to.
635 p_setb(perm
, PCI_CAP_LIST_NEXT
, (u8
)ALL_VIRT
, NO_WRITE
);
638 * Power management is defined *per function*, so we can let
639 * the user change power state, but we trap and initiate the
640 * change ourselves, so the state bits are read-only.
642 p_setd(perm
, PCI_PM_CTRL
, NO_VIRT
, ~PCI_PM_CTRL_STATE_MASK
);
646 /* Permissions for PCI-X capability */
647 static int __init
init_pci_cap_pcix_perm(struct perm_bits
*perm
)
649 /* Alloc 24, but only 8 are used in v0 */
650 if (alloc_perm_bits(perm
, PCI_CAP_PCIX_SIZEOF_V2
))
653 p_setb(perm
, PCI_CAP_LIST_NEXT
, (u8
)ALL_VIRT
, NO_WRITE
);
655 p_setw(perm
, PCI_X_CMD
, NO_VIRT
, (u16
)ALL_WRITE
);
656 p_setd(perm
, PCI_X_ECC_CSR
, NO_VIRT
, ALL_WRITE
);
660 /* Permissions for PCI Express capability */
661 static int __init
init_pci_cap_exp_perm(struct perm_bits
*perm
)
663 /* Alloc larger of two possible sizes */
664 if (alloc_perm_bits(perm
, PCI_CAP_EXP_ENDPOINT_SIZEOF_V2
))
667 p_setb(perm
, PCI_CAP_LIST_NEXT
, (u8
)ALL_VIRT
, NO_WRITE
);
670 * Allow writes to device control fields (includes FLR!)
671 * but not to devctl_phantom which could confuse IOMMU
672 * or to the ARI bit in devctl2 which is set at probe time
674 p_setw(perm
, PCI_EXP_DEVCTL
, NO_VIRT
, ~PCI_EXP_DEVCTL_PHANTOM
);
675 p_setw(perm
, PCI_EXP_DEVCTL2
, NO_VIRT
, ~PCI_EXP_DEVCTL2_ARI
);
679 /* Permissions for Advanced Function capability */
680 static int __init
init_pci_cap_af_perm(struct perm_bits
*perm
)
682 if (alloc_perm_bits(perm
, pci_cap_length
[PCI_CAP_ID_AF
]))
685 p_setb(perm
, PCI_CAP_LIST_NEXT
, (u8
)ALL_VIRT
, NO_WRITE
);
686 p_setb(perm
, PCI_AF_CTRL
, NO_VIRT
, PCI_AF_CTRL_FLR
);
690 /* Permissions for Advanced Error Reporting extended capability */
691 static int __init
init_pci_ext_cap_err_perm(struct perm_bits
*perm
)
695 if (alloc_perm_bits(perm
, pci_ext_cap_length
[PCI_EXT_CAP_ID_ERR
]))
699 * Virtualize the first dword of all express capabilities
700 * because it includes the next pointer. This lets us later
701 * remove capabilities from the chain if we need to.
703 p_setd(perm
, 0, ALL_VIRT
, NO_WRITE
);
705 /* Writable bits mask */
706 mask
= PCI_ERR_UNC_TRAIN
| /* Training */
707 PCI_ERR_UNC_DLP
| /* Data Link Protocol */
708 PCI_ERR_UNC_SURPDN
| /* Surprise Down */
709 PCI_ERR_UNC_POISON_TLP
| /* Poisoned TLP */
710 PCI_ERR_UNC_FCP
| /* Flow Control Protocol */
711 PCI_ERR_UNC_COMP_TIME
| /* Completion Timeout */
712 PCI_ERR_UNC_COMP_ABORT
| /* Completer Abort */
713 PCI_ERR_UNC_UNX_COMP
| /* Unexpected Completion */
714 PCI_ERR_UNC_RX_OVER
| /* Receiver Overflow */
715 PCI_ERR_UNC_MALF_TLP
| /* Malformed TLP */
716 PCI_ERR_UNC_ECRC
| /* ECRC Error Status */
717 PCI_ERR_UNC_UNSUP
| /* Unsupported Request */
718 PCI_ERR_UNC_ACSV
| /* ACS Violation */
719 PCI_ERR_UNC_INTN
| /* internal error */
720 PCI_ERR_UNC_MCBTLP
| /* MC blocked TLP */
721 PCI_ERR_UNC_ATOMEG
| /* Atomic egress blocked */
722 PCI_ERR_UNC_TLPPRE
; /* TLP prefix blocked */
723 p_setd(perm
, PCI_ERR_UNCOR_STATUS
, NO_VIRT
, mask
);
724 p_setd(perm
, PCI_ERR_UNCOR_MASK
, NO_VIRT
, mask
);
725 p_setd(perm
, PCI_ERR_UNCOR_SEVER
, NO_VIRT
, mask
);
727 mask
= PCI_ERR_COR_RCVR
| /* Receiver Error Status */
728 PCI_ERR_COR_BAD_TLP
| /* Bad TLP Status */
729 PCI_ERR_COR_BAD_DLLP
| /* Bad DLLP Status */
730 PCI_ERR_COR_REP_ROLL
| /* REPLAY_NUM Rollover */
731 PCI_ERR_COR_REP_TIMER
| /* Replay Timer Timeout */
732 PCI_ERR_COR_ADV_NFAT
| /* Advisory Non-Fatal */
733 PCI_ERR_COR_INTERNAL
| /* Corrected Internal */
734 PCI_ERR_COR_LOG_OVER
; /* Header Log Overflow */
735 p_setd(perm
, PCI_ERR_COR_STATUS
, NO_VIRT
, mask
);
736 p_setd(perm
, PCI_ERR_COR_MASK
, NO_VIRT
, mask
);
738 mask
= PCI_ERR_CAP_ECRC_GENE
| /* ECRC Generation Enable */
739 PCI_ERR_CAP_ECRC_CHKE
; /* ECRC Check Enable */
740 p_setd(perm
, PCI_ERR_CAP
, NO_VIRT
, mask
);
744 /* Permissions for Power Budgeting extended capability */
745 static int __init
init_pci_ext_cap_pwr_perm(struct perm_bits
*perm
)
747 if (alloc_perm_bits(perm
, pci_ext_cap_length
[PCI_EXT_CAP_ID_PWR
]))
750 p_setd(perm
, 0, ALL_VIRT
, NO_WRITE
);
752 /* Writing the data selector is OK, the info is still read-only */
753 p_setb(perm
, PCI_PWR_DATA
, NO_VIRT
, (u8
)ALL_WRITE
);
758 * Initialize the shared permission tables
760 void vfio_pci_uninit_perm_bits(void)
762 free_perm_bits(&cap_perms
[PCI_CAP_ID_BASIC
]);
764 free_perm_bits(&cap_perms
[PCI_CAP_ID_PM
]);
765 free_perm_bits(&cap_perms
[PCI_CAP_ID_PCIX
]);
766 free_perm_bits(&cap_perms
[PCI_CAP_ID_EXP
]);
767 free_perm_bits(&cap_perms
[PCI_CAP_ID_AF
]);
769 free_perm_bits(&ecap_perms
[PCI_EXT_CAP_ID_ERR
]);
770 free_perm_bits(&ecap_perms
[PCI_EXT_CAP_ID_PWR
]);
773 int __init
vfio_pci_init_perm_bits(void)
777 /* Basic config space */
778 ret
= init_pci_cap_basic_perm(&cap_perms
[PCI_CAP_ID_BASIC
]);
781 ret
|= init_pci_cap_pm_perm(&cap_perms
[PCI_CAP_ID_PM
]);
782 cap_perms
[PCI_CAP_ID_VPD
].writefn
= vfio_direct_config_write
;
783 ret
|= init_pci_cap_pcix_perm(&cap_perms
[PCI_CAP_ID_PCIX
]);
784 cap_perms
[PCI_CAP_ID_VNDR
].writefn
= vfio_direct_config_write
;
785 ret
|= init_pci_cap_exp_perm(&cap_perms
[PCI_CAP_ID_EXP
]);
786 ret
|= init_pci_cap_af_perm(&cap_perms
[PCI_CAP_ID_AF
]);
788 /* Extended capabilities */
789 ret
|= init_pci_ext_cap_err_perm(&ecap_perms
[PCI_EXT_CAP_ID_ERR
]);
790 ret
|= init_pci_ext_cap_pwr_perm(&ecap_perms
[PCI_EXT_CAP_ID_PWR
]);
791 ecap_perms
[PCI_EXT_CAP_ID_VNDR
].writefn
= vfio_direct_config_write
;
794 vfio_pci_uninit_perm_bits();
799 static int vfio_find_cap_start(struct vfio_pci_device
*vdev
, int pos
)
802 int base
= (pos
>= PCI_CFG_SPACE_SIZE
) ? PCI_CFG_SPACE_SIZE
:
803 PCI_STD_HEADER_SIZEOF
;
807 cap
= vdev
->pci_config_map
[pos
];
809 if (cap
== PCI_CAP_ID_BASIC
)
812 /* XXX Can we have to abutting capabilities of the same type? */
813 while (pos
- 1 >= base
&& vdev
->pci_config_map
[pos
- 1] == cap
)
819 static int vfio_msi_config_read(struct vfio_pci_device
*vdev
, int pos
,
820 int count
, struct perm_bits
*perm
,
821 int offset
, __le32
*val
)
823 /* Update max available queue size from msi_qmax */
824 if (offset
<= PCI_MSI_FLAGS
&& offset
+ count
>= PCI_MSI_FLAGS
) {
828 start
= vfio_find_cap_start(vdev
, pos
);
830 flags
= (__le16
*)&vdev
->vconfig
[start
];
832 *flags
&= cpu_to_le16(~PCI_MSI_FLAGS_QMASK
);
833 *flags
|= cpu_to_le16(vdev
->msi_qmax
<< 1);
836 return vfio_default_config_read(vdev
, pos
, count
, perm
, offset
, val
);
839 static int vfio_msi_config_write(struct vfio_pci_device
*vdev
, int pos
,
840 int count
, struct perm_bits
*perm
,
841 int offset
, __le32 val
)
843 count
= vfio_default_config_write(vdev
, pos
, count
, perm
, offset
, val
);
847 /* Fixup and write configured queue size and enable to hardware */
848 if (offset
<= PCI_MSI_FLAGS
&& offset
+ count
>= PCI_MSI_FLAGS
) {
853 start
= vfio_find_cap_start(vdev
, pos
);
855 pflags
= (__le16
*)&vdev
->vconfig
[start
+ PCI_MSI_FLAGS
];
857 flags
= le16_to_cpu(*pflags
);
859 /* MSI is enabled via ioctl */
861 flags
&= ~PCI_MSI_FLAGS_ENABLE
;
863 /* Check queue size */
864 if ((flags
& PCI_MSI_FLAGS_QSIZE
) >> 4 > vdev
->msi_qmax
) {
865 flags
&= ~PCI_MSI_FLAGS_QSIZE
;
866 flags
|= vdev
->msi_qmax
<< 4;
869 /* Write back to virt and to hardware */
870 *pflags
= cpu_to_le16(flags
);
871 ret
= pci_user_write_config_word(vdev
->pdev
,
872 start
+ PCI_MSI_FLAGS
,
875 return pcibios_err_to_errno(ret
);
882 * MSI determination is per-device, so this routine gets used beyond
883 * initialization time. Don't add __init
885 static int init_pci_cap_msi_perm(struct perm_bits
*perm
, int len
, u16 flags
)
887 if (alloc_perm_bits(perm
, len
))
890 perm
->readfn
= vfio_msi_config_read
;
891 perm
->writefn
= vfio_msi_config_write
;
893 p_setb(perm
, PCI_CAP_LIST_NEXT
, (u8
)ALL_VIRT
, NO_WRITE
);
896 * The upper byte of the control register is reserved,
897 * just setup the lower byte.
899 p_setb(perm
, PCI_MSI_FLAGS
, (u8
)ALL_VIRT
, (u8
)ALL_WRITE
);
900 p_setd(perm
, PCI_MSI_ADDRESS_LO
, ALL_VIRT
, ALL_WRITE
);
901 if (flags
& PCI_MSI_FLAGS_64BIT
) {
902 p_setd(perm
, PCI_MSI_ADDRESS_HI
, ALL_VIRT
, ALL_WRITE
);
903 p_setw(perm
, PCI_MSI_DATA_64
, (u16
)ALL_VIRT
, (u16
)ALL_WRITE
);
904 if (flags
& PCI_MSI_FLAGS_MASKBIT
) {
905 p_setd(perm
, PCI_MSI_MASK_64
, NO_VIRT
, ALL_WRITE
);
906 p_setd(perm
, PCI_MSI_PENDING_64
, NO_VIRT
, ALL_WRITE
);
909 p_setw(perm
, PCI_MSI_DATA_32
, (u16
)ALL_VIRT
, (u16
)ALL_WRITE
);
910 if (flags
& PCI_MSI_FLAGS_MASKBIT
) {
911 p_setd(perm
, PCI_MSI_MASK_32
, NO_VIRT
, ALL_WRITE
);
912 p_setd(perm
, PCI_MSI_PENDING_32
, NO_VIRT
, ALL_WRITE
);
918 /* Determine MSI CAP field length; initialize msi_perms on 1st call per vdev */
919 static int vfio_msi_cap_len(struct vfio_pci_device
*vdev
, u8 pos
)
921 struct pci_dev
*pdev
= vdev
->pdev
;
925 ret
= pci_read_config_word(pdev
, pos
+ PCI_MSI_FLAGS
, &flags
);
927 return pcibios_err_to_errno(ret
);
929 len
= 10; /* Minimum size */
930 if (flags
& PCI_MSI_FLAGS_64BIT
)
932 if (flags
& PCI_MSI_FLAGS_MASKBIT
)
938 vdev
->msi_perm
= kmalloc(sizeof(struct perm_bits
), GFP_KERNEL
);
942 ret
= init_pci_cap_msi_perm(vdev
->msi_perm
, len
, flags
);
949 /* Determine extended capability length for VC (2 & 9) and MFVC */
950 static int vfio_vc_cap_len(struct vfio_pci_device
*vdev
, u16 pos
)
952 struct pci_dev
*pdev
= vdev
->pdev
;
954 int ret
, evcc
, phases
, vc_arb
;
955 int len
= PCI_CAP_VC_BASE_SIZEOF
;
957 ret
= pci_read_config_dword(pdev
, pos
+ PCI_VC_PORT_REG1
, &tmp
);
959 return pcibios_err_to_errno(ret
);
961 evcc
= tmp
& PCI_VC_REG1_EVCC
; /* extended vc count */
962 ret
= pci_read_config_dword(pdev
, pos
+ PCI_VC_PORT_REG2
, &tmp
);
964 return pcibios_err_to_errno(ret
);
966 if (tmp
& PCI_VC_REG2_128_PHASE
)
968 else if (tmp
& PCI_VC_REG2_64_PHASE
)
970 else if (tmp
& PCI_VC_REG2_32_PHASE
)
978 * Port arbitration tables are root & switch only;
979 * function arbitration tables are function 0 only.
980 * In either case, we'll never let user write them so
981 * we don't care how big they are
983 len
+= (1 + evcc
) * PCI_CAP_VC_PER_VC_SIZEOF
;
985 len
= round_up(len
, 16);
991 static int vfio_cap_len(struct vfio_pci_device
*vdev
, u8 cap
, u8 pos
)
993 struct pci_dev
*pdev
= vdev
->pdev
;
1000 return vfio_msi_cap_len(vdev
, pos
);
1001 case PCI_CAP_ID_PCIX
:
1002 ret
= pci_read_config_word(pdev
, pos
+ PCI_X_CMD
, &word
);
1004 return pcibios_err_to_errno(ret
);
1006 if (PCI_X_CMD_VERSION(word
)) {
1007 vdev
->extended_caps
= true;
1008 return PCI_CAP_PCIX_SIZEOF_V2
;
1010 return PCI_CAP_PCIX_SIZEOF_V0
;
1011 case PCI_CAP_ID_VNDR
:
1012 /* length follows next field */
1013 ret
= pci_read_config_byte(pdev
, pos
+ PCI_CAP_FLAGS
, &byte
);
1015 return pcibios_err_to_errno(ret
);
1018 case PCI_CAP_ID_EXP
:
1019 /* length based on version */
1020 ret
= pci_read_config_word(pdev
, pos
+ PCI_EXP_FLAGS
, &word
);
1022 return pcibios_err_to_errno(ret
);
1024 vdev
->extended_caps
= true;
1026 if ((word
& PCI_EXP_FLAGS_VERS
) == 1)
1027 return PCI_CAP_EXP_ENDPOINT_SIZEOF_V1
;
1029 return PCI_CAP_EXP_ENDPOINT_SIZEOF_V2
;
1031 ret
= pci_read_config_byte(pdev
, pos
+ 3, &byte
);
1033 return pcibios_err_to_errno(ret
);
1035 return (byte
& HT_3BIT_CAP_MASK
) ?
1036 HT_CAP_SIZEOF_SHORT
: HT_CAP_SIZEOF_LONG
;
1037 case PCI_CAP_ID_SATA
:
1038 ret
= pci_read_config_byte(pdev
, pos
+ PCI_SATA_REGS
, &byte
);
1040 return pcibios_err_to_errno(ret
);
1042 byte
&= PCI_SATA_REGS_MASK
;
1043 if (byte
== PCI_SATA_REGS_INLINE
)
1044 return PCI_SATA_SIZEOF_LONG
;
1046 return PCI_SATA_SIZEOF_SHORT
;
1048 pr_warn("%s: %s unknown length for pci cap 0x%x@0x%x\n",
1049 dev_name(&pdev
->dev
), __func__
, cap
, pos
);
1055 static int vfio_ext_cap_len(struct vfio_pci_device
*vdev
, u16 ecap
, u16 epos
)
1057 struct pci_dev
*pdev
= vdev
->pdev
;
1063 case PCI_EXT_CAP_ID_VNDR
:
1064 ret
= pci_read_config_dword(pdev
, epos
+ PCI_VSEC_HDR
, &dword
);
1066 return pcibios_err_to_errno(ret
);
1068 return dword
>> PCI_VSEC_HDR_LEN_SHIFT
;
1069 case PCI_EXT_CAP_ID_VC
:
1070 case PCI_EXT_CAP_ID_VC9
:
1071 case PCI_EXT_CAP_ID_MFVC
:
1072 return vfio_vc_cap_len(vdev
, epos
);
1073 case PCI_EXT_CAP_ID_ACS
:
1074 ret
= pci_read_config_byte(pdev
, epos
+ PCI_ACS_CAP
, &byte
);
1076 return pcibios_err_to_errno(ret
);
1078 if (byte
& PCI_ACS_EC
) {
1081 ret
= pci_read_config_byte(pdev
,
1082 epos
+ PCI_ACS_EGRESS_BITS
,
1085 return pcibios_err_to_errno(ret
);
1087 bits
= byte
? round_up(byte
, 32) : 256;
1088 return 8 + (bits
/ 8);
1092 case PCI_EXT_CAP_ID_REBAR
:
1093 ret
= pci_read_config_byte(pdev
, epos
+ PCI_REBAR_CTRL
, &byte
);
1095 return pcibios_err_to_errno(ret
);
1097 byte
&= PCI_REBAR_CTRL_NBAR_MASK
;
1098 byte
>>= PCI_REBAR_CTRL_NBAR_SHIFT
;
1100 return 4 + (byte
* 8);
1101 case PCI_EXT_CAP_ID_DPA
:
1102 ret
= pci_read_config_byte(pdev
, epos
+ PCI_DPA_CAP
, &byte
);
1104 return pcibios_err_to_errno(ret
);
1106 byte
&= PCI_DPA_CAP_SUBSTATE_MASK
;
1107 byte
= round_up(byte
+ 1, 4);
1108 return PCI_DPA_BASE_SIZEOF
+ byte
;
1109 case PCI_EXT_CAP_ID_TPH
:
1110 ret
= pci_read_config_dword(pdev
, epos
+ PCI_TPH_CAP
, &dword
);
1112 return pcibios_err_to_errno(ret
);
1114 if ((dword
& PCI_TPH_CAP_LOC_MASK
) == PCI_TPH_LOC_CAP
) {
1117 sts
= byte
& PCI_TPH_CAP_ST_MASK
;
1118 sts
>>= PCI_TPH_CAP_ST_SHIFT
;
1119 return PCI_TPH_BASE_SIZEOF
+ round_up(sts
* 2, 4);
1121 return PCI_TPH_BASE_SIZEOF
;
1123 pr_warn("%s: %s unknown length for pci ecap 0x%x@0x%x\n",
1124 dev_name(&pdev
->dev
), __func__
, ecap
, epos
);
1130 static int vfio_fill_vconfig_bytes(struct vfio_pci_device
*vdev
,
1131 int offset
, int size
)
1133 struct pci_dev
*pdev
= vdev
->pdev
;
1137 * We try to read physical config space in the largest chunks
1138 * we can, assuming that all of the fields support dword access.
1139 * pci_save_state() makes this same assumption and seems to do ok.
1144 if (size
>= 4 && !(offset
% 4)) {
1145 __le32
*dwordp
= (__le32
*)&vdev
->vconfig
[offset
];
1148 ret
= pci_read_config_dword(pdev
, offset
, &dword
);
1151 *dwordp
= cpu_to_le32(dword
);
1153 } else if (size
>= 2 && !(offset
% 2)) {
1154 __le16
*wordp
= (__le16
*)&vdev
->vconfig
[offset
];
1157 ret
= pci_read_config_word(pdev
, offset
, &word
);
1160 *wordp
= cpu_to_le16(word
);
1163 u8
*byte
= &vdev
->vconfig
[offset
];
1164 ret
= pci_read_config_byte(pdev
, offset
, byte
);
1177 static int vfio_cap_init(struct vfio_pci_device
*vdev
)
1179 struct pci_dev
*pdev
= vdev
->pdev
;
1180 u8
*map
= vdev
->pci_config_map
;
1183 int loops
, ret
, caps
= 0;
1185 /* Any capabilities? */
1186 ret
= pci_read_config_word(pdev
, PCI_STATUS
, &status
);
1190 if (!(status
& PCI_STATUS_CAP_LIST
))
1191 return 0; /* Done */
1193 ret
= pci_read_config_byte(pdev
, PCI_CAPABILITY_LIST
, &pos
);
1197 /* Mark the previous position in case we want to skip a capability */
1198 prev
= &vdev
->vconfig
[PCI_CAPABILITY_LIST
];
1200 /* We can bound our loop, capabilities are dword aligned */
1201 loops
= (PCI_CFG_SPACE_SIZE
- PCI_STD_HEADER_SIZEOF
) / PCI_CAP_SIZEOF
;
1202 while (pos
&& loops
--) {
1206 ret
= pci_read_config_byte(pdev
, pos
, &cap
);
1210 ret
= pci_read_config_byte(pdev
,
1211 pos
+ PCI_CAP_LIST_NEXT
, &next
);
1215 if (cap
<= PCI_CAP_ID_MAX
) {
1216 len
= pci_cap_length
[cap
];
1217 if (len
== 0xFF) { /* Variable length */
1218 len
= vfio_cap_len(vdev
, cap
, pos
);
1225 pr_info("%s: %s hiding cap 0x%x\n",
1226 __func__
, dev_name(&pdev
->dev
), cap
);
1232 /* Sanity check, do we overlap other capabilities? */
1233 for (i
= 0; i
< len
; i
+= 4) {
1234 if (likely(map
[(pos
+ i
) / 4] == PCI_CAP_ID_INVALID
))
1237 pr_warn("%s: %s pci config conflict @0x%x, was cap 0x%x now cap 0x%x\n",
1238 __func__
, dev_name(&pdev
->dev
),
1239 pos
+ i
, map
[pos
+ i
], cap
);
1242 memset(map
+ (pos
/ 4), cap
, len
/ 4);
1243 ret
= vfio_fill_vconfig_bytes(vdev
, pos
, len
);
1247 prev
= &vdev
->vconfig
[pos
+ PCI_CAP_LIST_NEXT
];
1252 /* If we didn't fill any capabilities, clear the status flag */
1254 __le16
*vstatus
= (__le16
*)&vdev
->vconfig
[PCI_STATUS
];
1255 *vstatus
&= ~cpu_to_le16(PCI_STATUS_CAP_LIST
);
1261 static int vfio_ecap_init(struct vfio_pci_device
*vdev
)
1263 struct pci_dev
*pdev
= vdev
->pdev
;
1264 u8
*map
= vdev
->pci_config_map
;
1266 __le32
*prev
= NULL
;
1267 int loops
, ret
, ecaps
= 0;
1269 if (!vdev
->extended_caps
)
1272 epos
= PCI_CFG_SPACE_SIZE
;
1274 loops
= (pdev
->cfg_size
- PCI_CFG_SPACE_SIZE
) / PCI_CAP_SIZEOF
;
1276 while (loops
-- && epos
>= PCI_CFG_SPACE_SIZE
) {
1280 bool hidden
= false;
1282 ret
= pci_read_config_dword(pdev
, epos
, &header
);
1286 ecap
= PCI_EXT_CAP_ID(header
);
1288 if (ecap
<= PCI_EXT_CAP_ID_MAX
) {
1289 len
= pci_ext_cap_length
[ecap
];
1291 len
= vfio_ext_cap_len(vdev
, ecap
, epos
);
1298 pr_info("%s: %s hiding ecap 0x%x@0x%x\n",
1299 __func__
, dev_name(&pdev
->dev
), ecap
, epos
);
1301 /* If not the first in the chain, we can skip over it */
1303 u32 val
= epos
= PCI_EXT_CAP_NEXT(header
);
1304 *prev
&= cpu_to_le32(~(0xffcU
<< 20));
1305 *prev
|= cpu_to_le32(val
<< 20);
1310 * Otherwise, fill in a placeholder, the direct
1311 * readfn will virtualize this automatically
1313 len
= PCI_CAP_SIZEOF
;
1317 for (i
= 0; i
< len
; i
+= 4) {
1318 if (likely(map
[(epos
+ i
) / 4] == PCI_CAP_ID_INVALID
))
1321 pr_warn("%s: %s pci config conflict @0x%x, was ecap 0x%x now ecap 0x%x\n",
1322 __func__
, dev_name(&pdev
->dev
),
1323 epos
+ i
, map
[epos
+ i
], ecap
);
1327 * Even though ecap is 2 bytes, we're currently a long way
1328 * from exceeding 1 byte capabilities. If we ever make it
1329 * up to 0xFF we'll need to up this to a two-byte, byte map.
1331 BUILD_BUG_ON(PCI_EXT_CAP_ID_MAX
>= PCI_CAP_ID_INVALID
);
1333 memset(map
+ (epos
/ 4), ecap
, len
/ 4);
1334 ret
= vfio_fill_vconfig_bytes(vdev
, epos
, len
);
1339 * If we're just using this capability to anchor the list,
1340 * hide the real ID. Only count real ecaps. XXX PCI spec
1341 * indicates to use cap id = 0, version = 0, next = 0 if
1342 * ecaps are absent, hope users check all the way to next.
1345 *(__le32
*)&vdev
->vconfig
[epos
] &=
1346 cpu_to_le32((0xffcU
<< 20));
1350 prev
= (__le32
*)&vdev
->vconfig
[epos
];
1351 epos
= PCI_EXT_CAP_NEXT(header
);
1355 *(u32
*)&vdev
->vconfig
[PCI_CFG_SPACE_SIZE
] = 0;
1361 * For each device we allocate a pci_config_map that indicates the
1362 * capability occupying each dword and thus the struct perm_bits we
1363 * use for read and write. We also allocate a virtualized config
1364 * space which tracks reads and writes to bits that we emulate for
1365 * the user. Initial values filled from device.
1367 * Using shared stuct perm_bits between all vfio-pci devices saves
1368 * us from allocating cfg_size buffers for virt and write for every
1369 * device. We could remove vconfig and allocate individual buffers
1370 * for each area requring emulated bits, but the array of pointers
1371 * would be comparable in size (at least for standard config space).
1373 int vfio_config_init(struct vfio_pci_device
*vdev
)
1375 struct pci_dev
*pdev
= vdev
->pdev
;
1380 * Config space, caps and ecaps are all dword aligned, so we can
1381 * use one byte per dword to record the type.
1383 map
= kmalloc(pdev
->cfg_size
/ 4, GFP_KERNEL
);
1387 vconfig
= kmalloc(pdev
->cfg_size
, GFP_KERNEL
);
1393 vdev
->pci_config_map
= map
;
1394 vdev
->vconfig
= vconfig
;
1396 memset(map
, PCI_CAP_ID_BASIC
, PCI_STD_HEADER_SIZEOF
/ 4);
1397 memset(map
+ (PCI_STD_HEADER_SIZEOF
/ 4), PCI_CAP_ID_INVALID
,
1398 (pdev
->cfg_size
- PCI_STD_HEADER_SIZEOF
) / 4);
1400 ret
= vfio_fill_vconfig_bytes(vdev
, 0, PCI_STD_HEADER_SIZEOF
);
1404 vdev
->bardirty
= true;
1407 * XXX can we just pci_load_saved_state/pci_restore_state?
1408 * may need to rebuild vconfig after that
1411 /* For restore after reset */
1412 vdev
->rbar
[0] = le32_to_cpu(*(__le32
*)&vconfig
[PCI_BASE_ADDRESS_0
]);
1413 vdev
->rbar
[1] = le32_to_cpu(*(__le32
*)&vconfig
[PCI_BASE_ADDRESS_1
]);
1414 vdev
->rbar
[2] = le32_to_cpu(*(__le32
*)&vconfig
[PCI_BASE_ADDRESS_2
]);
1415 vdev
->rbar
[3] = le32_to_cpu(*(__le32
*)&vconfig
[PCI_BASE_ADDRESS_3
]);
1416 vdev
->rbar
[4] = le32_to_cpu(*(__le32
*)&vconfig
[PCI_BASE_ADDRESS_4
]);
1417 vdev
->rbar
[5] = le32_to_cpu(*(__le32
*)&vconfig
[PCI_BASE_ADDRESS_5
]);
1418 vdev
->rbar
[6] = le32_to_cpu(*(__le32
*)&vconfig
[PCI_ROM_ADDRESS
]);
1420 if (pdev
->is_virtfn
) {
1421 *(__le16
*)&vconfig
[PCI_VENDOR_ID
] = cpu_to_le16(pdev
->vendor
);
1422 *(__le16
*)&vconfig
[PCI_DEVICE_ID
] = cpu_to_le16(pdev
->device
);
1425 ret
= vfio_cap_init(vdev
);
1429 ret
= vfio_ecap_init(vdev
);
1437 vdev
->pci_config_map
= NULL
;
1439 vdev
->vconfig
= NULL
;
1440 return pcibios_err_to_errno(ret
);
1443 void vfio_config_free(struct vfio_pci_device
*vdev
)
1445 kfree(vdev
->vconfig
);
1446 vdev
->vconfig
= NULL
;
1447 kfree(vdev
->pci_config_map
);
1448 vdev
->pci_config_map
= NULL
;
1449 kfree(vdev
->msi_perm
);
1450 vdev
->msi_perm
= NULL
;
1453 static ssize_t
vfio_config_do_rw(struct vfio_pci_device
*vdev
, char __user
*buf
,
1454 size_t count
, loff_t
*ppos
, bool iswrite
)
1456 struct pci_dev
*pdev
= vdev
->pdev
;
1457 struct perm_bits
*perm
;
1459 int cap_start
= 0, offset
;
1461 ssize_t ret
= count
;
1463 if (*ppos
< 0 || *ppos
+ count
> pdev
->cfg_size
)
1467 * gcc can't seem to figure out we're a static function, only called
1468 * with count of 1/2/4 and hits copy_from_user_overflow without this.
1470 if (count
> sizeof(val
))
1473 cap_id
= vdev
->pci_config_map
[*ppos
/ 4];
1475 if (cap_id
== PCI_CAP_ID_INVALID
) {
1477 return ret
; /* drop */
1480 * Per PCI spec 3.0, section 6.1, reads from reserved and
1481 * unimplemented registers return 0
1483 if (copy_to_user(buf
, &val
, count
))
1490 * All capabilities are minimum 4 bytes and aligned on dword
1491 * boundaries. Since we don't support unaligned accesses, we're
1492 * only ever accessing a single capability.
1494 if (*ppos
>= PCI_CFG_SPACE_SIZE
) {
1495 WARN_ON(cap_id
> PCI_EXT_CAP_ID_MAX
);
1497 perm
= &ecap_perms
[cap_id
];
1498 cap_start
= vfio_find_cap_start(vdev
, *ppos
);
1501 WARN_ON(cap_id
> PCI_CAP_ID_MAX
);
1503 perm
= &cap_perms
[cap_id
];
1505 if (cap_id
== PCI_CAP_ID_MSI
)
1506 perm
= vdev
->msi_perm
;
1508 if (cap_id
> PCI_CAP_ID_BASIC
)
1509 cap_start
= vfio_find_cap_start(vdev
, *ppos
);
1512 WARN_ON(!cap_start
&& cap_id
!= PCI_CAP_ID_BASIC
);
1513 WARN_ON(cap_start
> *ppos
);
1515 offset
= *ppos
- cap_start
;
1521 if (copy_from_user(&val
, buf
, count
))
1524 ret
= perm
->writefn(vdev
, *ppos
, count
, perm
, offset
, val
);
1527 ret
= perm
->readfn(vdev
, *ppos
, count
,
1528 perm
, offset
, &val
);
1533 if (copy_to_user(buf
, &val
, count
))
1540 ssize_t
vfio_pci_config_rw(struct vfio_pci_device
*vdev
, char __user
*buf
,
1541 size_t count
, loff_t
*ppos
, bool iswrite
)
1547 pos
&= VFIO_PCI_OFFSET_MASK
;
1550 * We want to both keep the access size the caller users as well as
1551 * support reading large chunks of config space in a single call.
1552 * PCI doesn't support unaligned accesses, so we can safely break
1556 if (count
>= 4 && !(pos
% 4))
1557 ret
= vfio_config_do_rw(vdev
, buf
, 4, &pos
, iswrite
);
1558 else if (count
>= 2 && !(pos
% 2))
1559 ret
= vfio_config_do_rw(vdev
, buf
, 2, &pos
, iswrite
);
1561 ret
= vfio_config_do_rw(vdev
, buf
, 1, &pos
, iswrite
);